2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb *dev_to_musb(struct device *dev)
128 return dev_get_drvdata(dev);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
136 void __iomem *addr = otg->io_priv;
141 /* Make sure the transceiver is not in low power mode */
142 power = musb_readb(addr, MUSB_POWER);
143 power &= ~MUSB_POWER_SUSPENDM;
144 musb_writeb(addr, MUSB_POWER, power);
146 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
147 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
150 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
151 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
152 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
154 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
155 & MUSB_ULPI_REG_CMPLT)) {
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
165 return musb_readb(addr, MUSB_ULPI_REG_DATA);
168 static int musb_ulpi_write(struct otg_transceiver *otg,
169 u32 offset, u32 data)
171 void __iomem *addr = otg->io_priv;
176 /* Make sure the transceiver is not in low power mode */
177 power = musb_readb(addr, MUSB_POWER);
178 power &= ~MUSB_POWER_SUSPENDM;
179 musb_writeb(addr, MUSB_POWER, power);
181 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
182 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
185 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
186 & MUSB_ULPI_REG_CMPLT)) {
192 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
193 r &= ~MUSB_ULPI_REG_CMPLT;
194 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
199 #define musb_ulpi_read NULL
200 #define musb_ulpi_write NULL
203 static struct otg_io_access_ops musb_ulpi_access = {
204 .read = musb_ulpi_read,
205 .write = musb_ulpi_write,
208 /*-------------------------------------------------------------------------*/
210 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
213 * Load an endpoint's FIFO
215 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
217 struct musb *musb = hw_ep->musb;
218 void __iomem *fifo = hw_ep->fifo;
222 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
223 'T', hw_ep->epnum, fifo, len, src);
225 /* we can't assume unaligned reads work */
226 if (likely((0x01 & (unsigned long) src) == 0)) {
229 /* best case is 32bit-aligned source address */
230 if ((0x02 & (unsigned long) src) == 0) {
232 writesl(fifo, src + index, len >> 2);
233 index += len & ~0x03;
236 musb_writew(fifo, 0, *(u16 *)&src[index]);
241 writesw(fifo, src + index, len >> 1);
242 index += len & ~0x01;
246 musb_writeb(fifo, 0, src[index]);
249 writesb(fifo, src, len);
253 #if !defined(CONFIG_USB_MUSB_AM35X)
255 * Unload an endpoint's FIFO
257 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
259 struct musb *musb = hw_ep->musb;
260 void __iomem *fifo = hw_ep->fifo;
262 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
263 'R', hw_ep->epnum, fifo, len, dst);
265 /* we can't assume unaligned writes work */
266 if (likely((0x01 & (unsigned long) dst) == 0)) {
269 /* best case is 32bit-aligned destination address */
270 if ((0x02 & (unsigned long) dst) == 0) {
272 readsl(fifo, dst, len >> 2);
276 *(u16 *)&dst[index] = musb_readw(fifo, 0);
281 readsw(fifo, dst, len >> 1);
286 dst[index] = musb_readb(fifo, 0);
289 readsb(fifo, dst, len);
294 #endif /* normal PIO */
297 /*-------------------------------------------------------------------------*/
299 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
300 static const u8 musb_test_packet[53] = {
301 /* implicit SYNC then DATA0 to start */
304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
306 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
308 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
309 /* JJJJJJJKKKKKKK x8 */
310 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
312 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
313 /* JKKKKKKK x10, JK */
314 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
316 /* implicit CRC16 then EOP to end */
319 void musb_load_testpacket(struct musb *musb)
321 void __iomem *regs = musb->endpoints[0].regs;
323 musb_ep_select(musb->mregs, 0);
324 musb_write_fifo(musb->control_ep,
325 sizeof(musb_test_packet), musb_test_packet);
326 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
329 /*-------------------------------------------------------------------------*/
332 * Handles OTG hnp timeouts, such as b_ase0_brst
334 void musb_otg_timer_func(unsigned long data)
336 struct musb *musb = (struct musb *)data;
339 spin_lock_irqsave(&musb->lock, flags);
340 switch (musb->xceiv->state) {
341 case OTG_STATE_B_WAIT_ACON:
342 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
343 musb_g_disconnect(musb);
344 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
347 case OTG_STATE_A_SUSPEND:
348 case OTG_STATE_A_WAIT_BCON:
349 dev_dbg(musb->controller, "HNP: %s timeout\n",
350 otg_state_string(musb->xceiv->state));
351 musb_platform_set_vbus(musb, 0);
352 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
355 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
356 otg_state_string(musb->xceiv->state));
358 musb->ignore_disconnect = 0;
359 spin_unlock_irqrestore(&musb->lock, flags);
363 * Stops the HNP transition. Caller must take care of locking.
365 void musb_hnp_stop(struct musb *musb)
367 struct usb_hcd *hcd = musb_to_hcd(musb);
368 void __iomem *mbase = musb->mregs;
371 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
373 switch (musb->xceiv->state) {
374 case OTG_STATE_A_PERIPHERAL:
375 musb_g_disconnect(musb);
376 dev_dbg(musb->controller, "HNP: back to %s\n",
377 otg_state_string(musb->xceiv->state));
379 case OTG_STATE_B_HOST:
380 dev_dbg(musb->controller, "HNP: Disabling HR\n");
381 hcd->self.is_b_host = 0;
382 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
384 reg = musb_readb(mbase, MUSB_POWER);
385 reg |= MUSB_POWER_SUSPENDM;
386 musb_writeb(mbase, MUSB_POWER, reg);
387 /* REVISIT: Start SESSION_REQUEST here? */
390 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
391 otg_state_string(musb->xceiv->state));
395 * When returning to A state after HNP, avoid hub_port_rebounce(),
396 * which cause occasional OPT A "Did not receive reset after connect"
399 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
403 * Interrupt Service Routine to record USB "global" interrupts.
404 * Since these do not happen often and signify things of
405 * paramount importance, it seems OK to check them individually;
406 * the order of the tests is specified in the manual
408 * @param musb instance pointer
409 * @param int_usb register contents
414 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
417 irqreturn_t handled = IRQ_NONE;
419 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
422 /* in host mode, the peripheral may issue remote wakeup.
423 * in peripheral mode, the host may resume the link.
424 * spurious RESUME irqs happen too, paired with SUSPEND.
426 if (int_usb & MUSB_INTR_RESUME) {
427 handled = IRQ_HANDLED;
428 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
430 if (devctl & MUSB_DEVCTL_HM) {
431 void __iomem *mbase = musb->mregs;
433 switch (musb->xceiv->state) {
434 case OTG_STATE_A_SUSPEND:
435 /* remote wakeup? later, GetPortStatus
436 * will stop RESUME signaling
439 if (power & MUSB_POWER_SUSPENDM) {
441 musb->int_usb &= ~MUSB_INTR_SUSPEND;
442 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
446 power &= ~MUSB_POWER_SUSPENDM;
447 musb_writeb(mbase, MUSB_POWER,
448 power | MUSB_POWER_RESUME);
450 musb->port1_status |=
451 (USB_PORT_STAT_C_SUSPEND << 16)
452 | MUSB_PORT_STAT_RESUME;
453 musb->rh_timer = jiffies
454 + msecs_to_jiffies(20);
456 musb->xceiv->state = OTG_STATE_A_HOST;
458 usb_hcd_resume_root_hub(musb_to_hcd(musb));
460 case OTG_STATE_B_WAIT_ACON:
461 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
466 WARNING("bogus %s RESUME (%s)\n",
468 otg_state_string(musb->xceiv->state));
471 switch (musb->xceiv->state) {
472 case OTG_STATE_A_SUSPEND:
473 /* possibly DISCONNECT is upcoming */
474 musb->xceiv->state = OTG_STATE_A_HOST;
475 usb_hcd_resume_root_hub(musb_to_hcd(musb));
477 case OTG_STATE_B_WAIT_ACON:
478 case OTG_STATE_B_PERIPHERAL:
479 /* disconnect while suspended? we may
480 * not get a disconnect irq...
482 if ((devctl & MUSB_DEVCTL_VBUS)
483 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
485 musb->int_usb |= MUSB_INTR_DISCONNECT;
486 musb->int_usb &= ~MUSB_INTR_SUSPEND;
491 case OTG_STATE_B_IDLE:
492 musb->int_usb &= ~MUSB_INTR_SUSPEND;
495 WARNING("bogus %s RESUME (%s)\n",
497 otg_state_string(musb->xceiv->state));
502 /* see manual for the order of the tests */
503 if (int_usb & MUSB_INTR_SESSREQ) {
504 void __iomem *mbase = musb->mregs;
506 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
507 && (devctl & MUSB_DEVCTL_BDEVICE)) {
508 dev_dbg(musb->controller, "SessReq while on B state\n");
512 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
513 otg_state_string(musb->xceiv->state));
515 /* IRQ arrives from ID pin sense or (later, if VBUS power
516 * is removed) SRP. responses are time critical:
517 * - turn on VBUS (with silicon-specific mechanism)
518 * - go through A_WAIT_VRISE
519 * - ... to A_WAIT_BCON.
520 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
522 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
523 musb->ep0_stage = MUSB_EP0_START;
524 musb->xceiv->state = OTG_STATE_A_IDLE;
526 musb_platform_set_vbus(musb, 1);
528 handled = IRQ_HANDLED;
531 if (int_usb & MUSB_INTR_VBUSERROR) {
534 /* During connection as an A-Device, we may see a short
535 * current spikes causing voltage drop, because of cable
536 * and peripheral capacitance combined with vbus draw.
537 * (So: less common with truly self-powered devices, where
538 * vbus doesn't act like a power supply.)
540 * Such spikes are short; usually less than ~500 usec, max
541 * of ~2 msec. That is, they're not sustained overcurrent
542 * errors, though they're reported using VBUSERROR irqs.
544 * Workarounds: (a) hardware: use self powered devices.
545 * (b) software: ignore non-repeated VBUS errors.
547 * REVISIT: do delays from lots of DEBUG_KERNEL checks
548 * make trouble here, keeping VBUS < 4.4V ?
550 switch (musb->xceiv->state) {
551 case OTG_STATE_A_HOST:
552 /* recovery is dicey once we've gotten past the
553 * initial stages of enumeration, but if VBUS
554 * stayed ok at the other end of the link, and
555 * another reset is due (at least for high speed,
556 * to redo the chirp etc), it might work OK...
558 case OTG_STATE_A_WAIT_BCON:
559 case OTG_STATE_A_WAIT_VRISE:
560 if (musb->vbuserr_retry) {
561 void __iomem *mbase = musb->mregs;
563 musb->vbuserr_retry--;
565 devctl |= MUSB_DEVCTL_SESSION;
566 musb_writeb(mbase, MUSB_DEVCTL, devctl);
568 musb->port1_status |=
569 USB_PORT_STAT_OVERCURRENT
570 | (USB_PORT_STAT_C_OVERCURRENT << 16);
577 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
578 otg_state_string(musb->xceiv->state),
581 switch (devctl & MUSB_DEVCTL_VBUS) {
582 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
583 s = "<SessEnd"; break;
584 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
585 s = "<AValid"; break;
586 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
587 s = "<VBusValid"; break;
588 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
592 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
595 /* go through A_WAIT_VFALL then start a new session */
597 musb_platform_set_vbus(musb, 0);
598 handled = IRQ_HANDLED;
601 if (int_usb & MUSB_INTR_SUSPEND) {
602 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
603 otg_state_string(musb->xceiv->state), devctl, power);
604 handled = IRQ_HANDLED;
606 switch (musb->xceiv->state) {
607 case OTG_STATE_A_PERIPHERAL:
608 /* We also come here if the cable is removed, since
609 * this silicon doesn't report ID-no-longer-grounded.
611 * We depend on T(a_wait_bcon) to shut us down, and
612 * hope users don't do anything dicey during this
613 * undesired detour through A_WAIT_BCON.
616 usb_hcd_resume_root_hub(musb_to_hcd(musb));
617 musb_root_disconnect(musb);
618 musb_platform_try_idle(musb, jiffies
619 + msecs_to_jiffies(musb->a_wait_bcon
620 ? : OTG_TIME_A_WAIT_BCON));
623 case OTG_STATE_B_IDLE:
624 if (!musb->is_active)
626 case OTG_STATE_B_PERIPHERAL:
627 musb_g_suspend(musb);
628 musb->is_active = is_otg_enabled(musb)
629 && musb->xceiv->gadget->b_hnp_enable;
630 if (musb->is_active) {
631 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
632 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
633 mod_timer(&musb->otg_timer, jiffies
635 OTG_TIME_B_ASE0_BRST));
638 case OTG_STATE_A_WAIT_BCON:
639 if (musb->a_wait_bcon != 0)
640 musb_platform_try_idle(musb, jiffies
641 + msecs_to_jiffies(musb->a_wait_bcon));
643 case OTG_STATE_A_HOST:
644 musb->xceiv->state = OTG_STATE_A_SUSPEND;
645 musb->is_active = is_otg_enabled(musb)
646 && musb->xceiv->host->b_hnp_enable;
648 case OTG_STATE_B_HOST:
649 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
650 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
653 /* "should not happen" */
658 switch (musb->xceiv->state) {
659 case OTG_STATE_B_IDLE:
660 case OTG_STATE_B_PERIPHERAL:
661 cancel_delayed_work(&musb->vbus_workaround_work);
662 schedule_delayed_work(&musb->vbus_workaround_work, HZ / 2);
668 if (int_usb & MUSB_INTR_CONNECT) {
669 struct usb_hcd *hcd = musb_to_hcd(musb);
671 handled = IRQ_HANDLED;
673 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
675 musb->ep0_stage = MUSB_EP0_START;
677 /* flush endpoints when transitioning from Device Mode */
678 if (is_peripheral_active(musb)) {
679 /* REVISIT HNP; just force disconnect */
681 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
682 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
683 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
684 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
685 |USB_PORT_STAT_HIGH_SPEED
686 |USB_PORT_STAT_ENABLE
688 musb->port1_status |= USB_PORT_STAT_CONNECTION
689 |(USB_PORT_STAT_C_CONNECTION << 16);
691 /* high vs full speed is just a guess until after reset */
692 if (devctl & MUSB_DEVCTL_LSDEV)
693 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
695 /* indicate new connection to OTG machine */
696 switch (musb->xceiv->state) {
697 case OTG_STATE_B_PERIPHERAL:
698 if (int_usb & MUSB_INTR_SUSPEND) {
699 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
700 int_usb &= ~MUSB_INTR_SUSPEND;
703 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
705 case OTG_STATE_B_WAIT_ACON:
706 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
708 musb->xceiv->state = OTG_STATE_B_HOST;
709 hcd->self.is_b_host = 1;
710 musb->ignore_disconnect = 0;
711 del_timer(&musb->otg_timer);
714 if ((devctl & MUSB_DEVCTL_VBUS)
715 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
716 musb->xceiv->state = OTG_STATE_A_HOST;
717 hcd->self.is_b_host = 0;
722 /* poke the root hub */
725 usb_hcd_poll_rh_status(hcd);
727 usb_hcd_resume_root_hub(hcd);
729 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
730 otg_state_string(musb->xceiv->state), devctl);
733 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
734 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
735 otg_state_string(musb->xceiv->state),
736 MUSB_MODE(musb), devctl);
737 handled = IRQ_HANDLED;
739 switch (musb->xceiv->state) {
740 case OTG_STATE_A_HOST:
741 case OTG_STATE_A_SUSPEND:
742 usb_hcd_resume_root_hub(musb_to_hcd(musb));
743 musb_root_disconnect(musb);
744 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
745 musb_platform_try_idle(musb, jiffies
746 + msecs_to_jiffies(musb->a_wait_bcon));
748 case OTG_STATE_B_HOST:
749 /* REVISIT this behaves for "real disconnect"
750 * cases; make sure the other transitions from
751 * from B_HOST act right too. The B_HOST code
752 * in hnp_stop() is currently not used...
754 musb_root_disconnect(musb);
755 musb_to_hcd(musb)->self.is_b_host = 0;
756 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
758 musb_g_disconnect(musb);
760 case OTG_STATE_A_PERIPHERAL:
762 musb_root_disconnect(musb);
764 case OTG_STATE_B_WAIT_ACON:
766 case OTG_STATE_B_PERIPHERAL:
767 case OTG_STATE_B_IDLE:
768 musb_g_disconnect(musb);
771 WARNING("unhandled DISCONNECT transition (%s)\n",
772 otg_state_string(musb->xceiv->state));
777 /* mentor saves a bit: bus reset and babble share the same irq.
778 * only host sees babble; only peripheral sees bus reset.
780 if (int_usb & MUSB_INTR_RESET) {
781 handled = IRQ_HANDLED;
782 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
784 * Looks like non-HS BABBLE can be ignored, but
785 * HS BABBLE is an error condition. For HS the solution
786 * is to avoid babble in the first place and fix what
787 * caused BABBLE. When HS BABBLE happens we can only
790 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
791 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
793 ERR("Stopping host session -- babble\n");
794 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
796 } else if (is_peripheral_capable()) {
797 dev_dbg(musb->controller, "BUS RESET as %s\n",
798 otg_state_string(musb->xceiv->state));
799 switch (musb->xceiv->state) {
800 case OTG_STATE_A_SUSPEND:
801 /* We need to ignore disconnect on suspend
802 * otherwise tusb 2.0 won't reconnect after a
803 * power cycle, which breaks otg compliance.
805 musb->ignore_disconnect = 1;
808 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
809 /* never use invalid T(a_wait_bcon) */
810 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
811 otg_state_string(musb->xceiv->state),
813 mod_timer(&musb->otg_timer, jiffies
814 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
816 case OTG_STATE_A_PERIPHERAL:
817 musb->ignore_disconnect = 0;
818 del_timer(&musb->otg_timer);
821 case OTG_STATE_B_WAIT_ACON:
822 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
823 otg_state_string(musb->xceiv->state));
824 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
827 case OTG_STATE_B_IDLE:
828 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
830 case OTG_STATE_B_PERIPHERAL:
834 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
835 otg_state_string(musb->xceiv->state));
841 /* REVISIT ... this would be for multiplexing periodic endpoints, or
842 * supporting transfer phasing to prevent exceeding ISO bandwidth
843 * limits of a given frame or microframe.
845 * It's not needed for peripheral side, which dedicates endpoints;
846 * though it _might_ use SOF irqs for other purposes.
848 * And it's not currently needed for host side, which also dedicates
849 * endpoints, relies on TX/RX interval registers, and isn't claimed
850 * to support ISO transfers yet.
852 if (int_usb & MUSB_INTR_SOF) {
853 void __iomem *mbase = musb->mregs;
854 struct musb_hw_ep *ep;
858 dev_dbg(musb->controller, "START_OF_FRAME\n");
859 handled = IRQ_HANDLED;
861 /* start any periodic Tx transfers waiting for current frame */
862 frame = musb_readw(mbase, MUSB_FRAME);
863 ep = musb->endpoints;
864 for (epnum = 1; (epnum < musb->nr_endpoints)
865 && (musb->epmask >= (1 << epnum));
868 * FIXME handle framecounter wraps (12 bits)
869 * eliminate duplicated StartUrb logic
871 if (ep->dwWaitFrame >= frame) {
873 pr_debug("SOF --> periodic TX%s on %d\n",
874 ep->tx_channel ? " DMA" : "",
877 musb_h_tx_start(musb, epnum);
879 cppi_hostdma_start(musb, epnum);
881 } /* end of for loop */
885 schedule_work(&musb->irq_work);
890 /*-------------------------------------------------------------------------*/
893 * Program the HDRC to start (enable interrupts, dma, etc.).
895 void musb_start(struct musb *musb)
897 void __iomem *regs = musb->mregs;
898 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
900 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
902 /* Set INT enable registers, enable interrupts */
903 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
904 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
905 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
907 musb_writeb(regs, MUSB_TESTMODE, 0);
909 /* put into basic highspeed mode and start session */
910 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
912 /* ENSUSPEND wedges tusb */
913 /* | MUSB_POWER_ENSUSPEND */
917 devctl = musb_readb(regs, MUSB_DEVCTL);
918 devctl &= ~MUSB_DEVCTL_SESSION;
920 if (is_otg_enabled(musb)) {
921 /* session started after:
922 * (a) ID-grounded irq, host mode;
923 * (b) vbus present/connect IRQ, peripheral mode;
924 * (c) peripheral initiates, using SRP
926 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
929 devctl |= MUSB_DEVCTL_SESSION;
931 } else if (is_host_enabled(musb)) {
932 /* assume ID pin is hard-wired to ground */
933 devctl |= MUSB_DEVCTL_SESSION;
935 } else /* peripheral is enabled */ {
936 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
939 musb_platform_enable(musb);
940 musb_writeb(regs, MUSB_DEVCTL, devctl);
944 static void musb_generic_disable(struct musb *musb)
946 void __iomem *mbase = musb->mregs;
949 /* disable interrupts */
950 musb_writeb(mbase, MUSB_INTRUSBE, 0);
951 musb_writew(mbase, MUSB_INTRTXE, 0);
952 musb_writew(mbase, MUSB_INTRRXE, 0);
955 musb_writeb(mbase, MUSB_DEVCTL, 0);
957 /* flush pending interrupts */
958 temp = musb_readb(mbase, MUSB_INTRUSB);
959 temp = musb_readw(mbase, MUSB_INTRTX);
960 temp = musb_readw(mbase, MUSB_INTRRX);
965 * Make the HDRC stop (disable interrupts, etc.);
966 * reversible by musb_start
967 * called on gadget driver unregister
968 * with controller locked, irqs blocked
969 * acts as a NOP unless some role activated the hardware
971 void musb_stop(struct musb *musb)
973 /* stop IRQs, timers, ... */
974 musb_platform_disable(musb);
975 musb_generic_disable(musb);
976 dev_dbg(musb->controller, "HDRC disabled\n");
979 * - mark host and/or peripheral drivers unusable/inactive
980 * - disable DMA (and enable it in HdrcStart)
981 * - make sure we can musb_start() after musb_stop(); with
982 * OTG mode, gadget driver module rmmod/modprobe cycles that
985 musb_platform_try_idle(musb, 0);
988 static void musb_shutdown(struct platform_device *pdev)
990 struct musb *musb = dev_to_musb(&pdev->dev);
993 pm_runtime_get_sync(musb->controller);
995 musb_gadget_cleanup(musb);
997 spin_lock_irqsave(&musb->lock, flags);
998 musb_platform_disable(musb);
999 musb_generic_disable(musb);
1000 spin_unlock_irqrestore(&musb->lock, flags);
1002 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1003 usb_remove_hcd(musb_to_hcd(musb));
1004 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1005 musb_platform_exit(musb);
1007 pm_runtime_put(musb->controller);
1009 cancel_delayed_work(&musb->vbus_workaround_work);
1011 /* FIXME power down */
1015 /*-------------------------------------------------------------------------*/
1018 * The silicon either has hard-wired endpoint configurations, or else
1019 * "dynamic fifo" sizing. The driver has support for both, though at this
1020 * writing only the dynamic sizing is very well tested. Since we switched
1021 * away from compile-time hardware parameters, we can no longer rely on
1022 * dead code elimination to leave only the relevant one in the object file.
1024 * We don't currently use dynamic fifo setup capability to do anything
1025 * more than selecting one of a bunch of predefined configurations.
1027 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1028 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1029 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1030 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1031 || defined(CONFIG_USB_MUSB_AM35X) \
1032 || defined(CONFIG_USB_MUSB_AM35X_MODULE)
1033 static ushort __initdata fifo_mode = 4;
1034 #elif defined(CONFIG_USB_MUSB_UX500) \
1035 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1036 static ushort __initdata fifo_mode = 5;
1038 static ushort __initdata fifo_mode = 2;
1041 /* "modprobe ... fifo_mode=1" etc */
1042 module_param(fifo_mode, ushort, 0);
1043 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1046 * tables defining fifo_mode values. define more if you like.
1047 * for host side, make sure both halves of ep1 are set up.
1050 /* mode 0 - fits in 2KB */
1051 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1052 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1053 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1054 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1055 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1056 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1059 /* mode 1 - fits in 4KB */
1060 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1061 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1062 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1063 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1064 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1065 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1068 /* mode 2 - fits in 4KB */
1069 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1070 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1073 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1074 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1075 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1078 /* mode 3 - fits in 4KB */
1079 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1080 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1081 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1082 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1085 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1088 /* mode 4 - fits in 16KB */
1089 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1090 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1091 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1092 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1093 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1094 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1095 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1096 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1097 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1098 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1099 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1100 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1101 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1102 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1107 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1108 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1109 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1110 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1111 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1112 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1113 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1114 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1115 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1116 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1119 /* mode 5 - fits in 8KB */
1120 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1121 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1122 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1123 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1124 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1125 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1126 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1127 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1128 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1129 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1130 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1131 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1132 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1133 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1134 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1135 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1136 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1137 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1138 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1139 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1140 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1141 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1142 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1143 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1144 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1145 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1146 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1147 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1151 * configure a fifo; for non-shared endpoints, this may be called
1152 * once for a tx fifo and once for an rx fifo.
1154 * returns negative errno or offset for next fifo.
1157 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1158 const struct musb_fifo_cfg *cfg, u16 offset)
1160 void __iomem *mbase = musb->mregs;
1162 u16 maxpacket = cfg->maxpacket;
1163 u16 c_off = offset >> 3;
1166 /* expect hw_ep has already been zero-initialized */
1168 size = ffs(max(maxpacket, (u16) 8)) - 1;
1169 maxpacket = 1 << size;
1172 if (cfg->mode == BUF_DOUBLE) {
1173 if ((offset + (maxpacket << 1)) >
1174 (1 << (musb->config->ram_bits + 2)))
1176 c_size |= MUSB_FIFOSZ_DPB;
1178 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1182 /* configure the FIFO */
1183 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1185 /* EP0 reserved endpoint for control, bidirectional;
1186 * EP1 reserved for bulk, two unidirection halves.
1188 if (hw_ep->epnum == 1)
1189 musb->bulk_ep = hw_ep;
1190 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1191 switch (cfg->style) {
1193 musb_write_txfifosz(mbase, c_size);
1194 musb_write_txfifoadd(mbase, c_off);
1195 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1196 hw_ep->max_packet_sz_tx = maxpacket;
1199 musb_write_rxfifosz(mbase, c_size);
1200 musb_write_rxfifoadd(mbase, c_off);
1201 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1202 hw_ep->max_packet_sz_rx = maxpacket;
1205 musb_write_txfifosz(mbase, c_size);
1206 musb_write_txfifoadd(mbase, c_off);
1207 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1208 hw_ep->max_packet_sz_rx = maxpacket;
1210 musb_write_rxfifosz(mbase, c_size);
1211 musb_write_rxfifoadd(mbase, c_off);
1212 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1213 hw_ep->max_packet_sz_tx = maxpacket;
1215 hw_ep->is_shared_fifo = true;
1219 /* NOTE rx and tx endpoint irqs aren't managed separately,
1220 * which happens to be ok
1222 musb->epmask |= (1 << hw_ep->epnum);
1224 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1227 static struct musb_fifo_cfg __initdata ep0_cfg = {
1228 .style = FIFO_RXTX, .maxpacket = 64,
1231 static int __init ep_config_from_table(struct musb *musb)
1233 const struct musb_fifo_cfg *cfg;
1236 struct musb_hw_ep *hw_ep = musb->endpoints;
1238 if (musb->config->fifo_cfg) {
1239 cfg = musb->config->fifo_cfg;
1240 n = musb->config->fifo_cfg_size;
1244 switch (fifo_mode) {
1250 n = ARRAY_SIZE(mode_0_cfg);
1254 n = ARRAY_SIZE(mode_1_cfg);
1258 n = ARRAY_SIZE(mode_2_cfg);
1262 n = ARRAY_SIZE(mode_3_cfg);
1266 n = ARRAY_SIZE(mode_4_cfg);
1270 n = ARRAY_SIZE(mode_5_cfg);
1274 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1275 musb_driver_name, fifo_mode);
1279 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1280 /* assert(offset > 0) */
1282 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1283 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1286 for (i = 0; i < n; i++) {
1287 u8 epn = cfg->hw_ep_num;
1289 if (epn >= musb->config->num_eps) {
1290 pr_debug("%s: invalid ep %d\n",
1291 musb_driver_name, epn);
1294 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1296 pr_debug("%s: mem overrun, ep %d\n",
1297 musb_driver_name, epn);
1301 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1304 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1306 n + 1, musb->config->num_eps * 2 - 1,
1307 offset, (1 << (musb->config->ram_bits + 2)));
1309 if (!musb->bulk_ep) {
1310 pr_debug("%s: missing bulk\n", musb_driver_name);
1319 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1320 * @param musb the controller
1322 static int __init ep_config_from_hw(struct musb *musb)
1325 struct musb_hw_ep *hw_ep;
1326 void *mbase = musb->mregs;
1329 dev_dbg(musb->controller, "<== static silicon ep config\n");
1331 /* FIXME pick up ep0 maxpacket size */
1333 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1334 musb_ep_select(mbase, epnum);
1335 hw_ep = musb->endpoints + epnum;
1337 ret = musb_read_fifosize(musb, hw_ep, epnum);
1341 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1343 /* pick an RX/TX endpoint for bulk */
1344 if (hw_ep->max_packet_sz_tx < 512
1345 || hw_ep->max_packet_sz_rx < 512)
1348 /* REVISIT: this algorithm is lazy, we should at least
1349 * try to pick a double buffered endpoint.
1353 musb->bulk_ep = hw_ep;
1356 if (!musb->bulk_ep) {
1357 pr_debug("%s: missing bulk\n", musb_driver_name);
1364 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1366 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1367 * configure endpoints, or take their config from silicon
1369 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1373 char aInfo[90], aRevision[32], aDate[12];
1374 void __iomem *mbase = musb->mregs;
1378 /* log core options (read using indexed model) */
1379 reg = musb_read_configdata(mbase);
1381 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1382 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1383 strcat(aInfo, ", dyn FIFOs");
1384 musb->dyn_fifo = true;
1386 if (reg & MUSB_CONFIGDATA_MPRXE) {
1387 strcat(aInfo, ", bulk combine");
1388 musb->bulk_combine = true;
1390 if (reg & MUSB_CONFIGDATA_MPTXE) {
1391 strcat(aInfo, ", bulk split");
1392 musb->bulk_split = true;
1394 if (reg & MUSB_CONFIGDATA_HBRXE) {
1395 strcat(aInfo, ", HB-ISO Rx");
1396 musb->hb_iso_rx = true;
1398 if (reg & MUSB_CONFIGDATA_HBTXE) {
1399 strcat(aInfo, ", HB-ISO Tx");
1400 musb->hb_iso_tx = true;
1402 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1403 strcat(aInfo, ", SoftConn");
1405 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1406 musb_driver_name, reg, aInfo);
1409 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1410 musb->is_multipoint = 1;
1413 musb->is_multipoint = 0;
1415 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1417 "%s: kernel must blacklist external hubs\n",
1422 /* log release info */
1423 musb->hwvers = musb_read_hwvers(mbase);
1424 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1425 MUSB_HWVERS_MINOR(musb->hwvers),
1426 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1427 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1428 musb_driver_name, type, aRevision, aDate);
1431 musb_configure_ep0(musb);
1433 /* discover endpoint configuration */
1434 musb->nr_endpoints = 1;
1438 status = ep_config_from_table(musb);
1440 status = ep_config_from_hw(musb);
1445 /* finish init, and print endpoint config */
1446 for (i = 0; i < musb->nr_endpoints; i++) {
1447 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1449 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1450 #ifdef CONFIG_USB_MUSB_TUSB6010
1451 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1452 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1453 hw_ep->fifo_sync_va =
1454 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1457 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1459 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1462 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1463 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1464 hw_ep->rx_reinit = 1;
1465 hw_ep->tx_reinit = 1;
1467 if (hw_ep->max_packet_sz_tx) {
1468 dev_dbg(musb->controller,
1469 "%s: hw_ep %d%s, %smax %d\n",
1470 musb_driver_name, i,
1471 hw_ep->is_shared_fifo ? "shared" : "tx",
1472 hw_ep->tx_double_buffered
1473 ? "doublebuffer, " : "",
1474 hw_ep->max_packet_sz_tx);
1476 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1477 dev_dbg(musb->controller,
1478 "%s: hw_ep %d%s, %smax %d\n",
1479 musb_driver_name, i,
1481 hw_ep->rx_double_buffered
1482 ? "doublebuffer, " : "",
1483 hw_ep->max_packet_sz_rx);
1485 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1486 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1492 /*-------------------------------------------------------------------------*/
1494 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1495 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1497 static irqreturn_t generic_interrupt(int irq, void *__hci)
1499 unsigned long flags;
1500 irqreturn_t retval = IRQ_NONE;
1501 struct musb *musb = __hci;
1503 spin_lock_irqsave(&musb->lock, flags);
1505 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1506 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1507 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1509 if (musb->int_usb || musb->int_tx || musb->int_rx)
1510 retval = musb_interrupt(musb);
1512 spin_unlock_irqrestore(&musb->lock, flags);
1518 #define generic_interrupt NULL
1522 * handle all the irqs defined by the HDRC core. for now we expect: other
1523 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1524 * will be assigned, and the irq will already have been acked.
1526 * called in irq context with spinlock held, irqs blocked
1528 irqreturn_t musb_interrupt(struct musb *musb)
1530 irqreturn_t retval = IRQ_NONE;
1535 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1536 power = musb_readb(musb->mregs, MUSB_POWER);
1538 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1539 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1540 musb->int_usb, musb->int_tx, musb->int_rx);
1542 /* the core can interrupt us for multiple reasons; docs have
1543 * a generic interrupt flowchart to follow
1546 retval |= musb_stage0_irq(musb, musb->int_usb,
1549 /* "stage 1" is handling endpoint irqs */
1551 /* handle endpoint 0 first */
1552 if (musb->int_tx & 1) {
1553 if (devctl & MUSB_DEVCTL_HM)
1554 retval |= musb_h_ep0_irq(musb);
1556 retval |= musb_g_ep0_irq(musb);
1559 /* RX on endpoints 1-15 */
1560 reg = musb->int_rx >> 1;
1564 /* musb_ep_select(musb->mregs, ep_num); */
1565 /* REVISIT just retval = ep->rx_irq(...) */
1566 retval = IRQ_HANDLED;
1567 if (devctl & MUSB_DEVCTL_HM) {
1568 if (is_host_capable())
1569 musb_host_rx(musb, ep_num);
1571 if (is_peripheral_capable())
1572 musb_g_rx(musb, ep_num);
1580 /* TX on endpoints 1-15 */
1581 reg = musb->int_tx >> 1;
1585 /* musb_ep_select(musb->mregs, ep_num); */
1586 /* REVISIT just retval |= ep->tx_irq(...) */
1587 retval = IRQ_HANDLED;
1588 if (devctl & MUSB_DEVCTL_HM) {
1589 if (is_host_capable())
1590 musb_host_tx(musb, ep_num);
1592 if (is_peripheral_capable())
1593 musb_g_tx(musb, ep_num);
1602 EXPORT_SYMBOL_GPL(musb_interrupt);
1604 #ifndef CONFIG_MUSB_PIO_ONLY
1605 static int __initdata use_dma = 1;
1607 /* "modprobe ... use_dma=0" etc */
1608 module_param(use_dma, bool, 0);
1609 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1611 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1613 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1615 /* called with controller lock already held */
1618 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1619 if (!is_cppi_enabled()) {
1621 if (devctl & MUSB_DEVCTL_HM)
1622 musb_h_ep0_irq(musb);
1624 musb_g_ep0_irq(musb);
1628 /* endpoints 1..15 */
1630 if (devctl & MUSB_DEVCTL_HM) {
1631 if (is_host_capable())
1632 musb_host_tx(musb, epnum);
1634 if (is_peripheral_capable())
1635 musb_g_tx(musb, epnum);
1639 if (devctl & MUSB_DEVCTL_HM) {
1640 if (is_host_capable())
1641 musb_host_rx(musb, epnum);
1643 if (is_peripheral_capable())
1644 musb_g_rx(musb, epnum);
1654 /*-------------------------------------------------------------------------*/
1659 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1661 struct musb *musb = dev_to_musb(dev);
1662 unsigned long flags;
1665 spin_lock_irqsave(&musb->lock, flags);
1666 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1667 spin_unlock_irqrestore(&musb->lock, flags);
1673 musb_mode_store(struct device *dev, struct device_attribute *attr,
1674 const char *buf, size_t n)
1676 struct musb *musb = dev_to_musb(dev);
1677 unsigned long flags;
1680 spin_lock_irqsave(&musb->lock, flags);
1681 if (sysfs_streq(buf, "host"))
1682 status = musb_platform_set_mode(musb, MUSB_HOST);
1683 else if (sysfs_streq(buf, "peripheral"))
1684 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1685 else if (sysfs_streq(buf, "otg"))
1686 status = musb_platform_set_mode(musb, MUSB_OTG);
1689 spin_unlock_irqrestore(&musb->lock, flags);
1691 return (status == 0) ? n : status;
1693 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1696 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1697 const char *buf, size_t n)
1699 struct musb *musb = dev_to_musb(dev);
1700 unsigned long flags;
1703 if (sscanf(buf, "%lu", &val) < 1) {
1704 dev_err(dev, "Invalid VBUS timeout ms value\n");
1708 spin_lock_irqsave(&musb->lock, flags);
1709 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1710 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1711 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1712 musb->is_active = 0;
1713 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1714 spin_unlock_irqrestore(&musb->lock, flags);
1720 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1722 struct musb *musb = dev_to_musb(dev);
1723 unsigned long flags;
1727 spin_lock_irqsave(&musb->lock, flags);
1728 val = musb->a_wait_bcon;
1729 /* FIXME get_vbus_status() is normally #defined as false...
1730 * and is effectively TUSB-specific.
1732 vbus = musb_platform_get_vbus_status(musb);
1733 spin_unlock_irqrestore(&musb->lock, flags);
1735 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1736 vbus ? "on" : "off", val);
1738 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1740 /* Gadget drivers can't know that a host is connected so they might want
1741 * to start SRP, but users can. This allows userspace to trigger SRP.
1744 musb_srp_store(struct device *dev, struct device_attribute *attr,
1745 const char *buf, size_t n)
1747 struct musb *musb = dev_to_musb(dev);
1750 if (sscanf(buf, "%hu", &srp) != 1
1752 dev_err(dev, "SRP: Value must be 1\n");
1757 musb_g_wakeup(musb);
1761 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1763 static struct attribute *musb_attributes[] = {
1764 &dev_attr_mode.attr,
1765 &dev_attr_vbus.attr,
1770 static const struct attribute_group musb_attr_group = {
1771 .attrs = musb_attributes,
1776 /* Only used to provide driver mode change events */
1777 static void musb_irq_work(struct work_struct *data)
1779 struct musb *musb = container_of(data, struct musb, irq_work);
1780 static int old_state;
1782 if (musb->xceiv->state != old_state) {
1783 old_state = musb->xceiv->state;
1784 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1788 #include <linux/usb/ulpi.h>
1790 static void musb_vbus_workaround_work(struct work_struct *work)
1792 struct musb *musb = container_of(work, struct musb, vbus_workaround_work.work);
1796 if (musb_ulpi_access.write == NULL)
1799 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1802 * I don't really know why but VBUS sometimes gets stuck and
1803 * causes session to never end. It would look like some pullup
1804 * is enabled when it shouldn't be on certain PHY states.
1805 * Turning on pulldowns magically drains VBUS to zero and allows
1806 * session to end, so let's do that here.
1808 * XXX: probably better check VBUS on TWL?
1809 * beagle sometimes has session bit set but no VBUS on twl?
1811 if ((musb->xceiv->state == OTG_STATE_B_PERIPHERAL ||
1812 musb->xceiv->state == OTG_STATE_B_IDLE) &&
1813 (devctl & MUSB_DEVCTL_VBUS) != (3 << MUSB_DEVCTL_VBUS_SHIFT) &&
1814 (devctl & MUSB_DEVCTL_VBUS) != (0 << MUSB_DEVCTL_VBUS_SHIFT)) {
1815 dev_dbg(musb->controller, "VBUS workaround..\n");
1816 ret = musb_ulpi_access.write(musb->xceiv, ULPI_SET(ULPI_OTG_CTRL),
1817 ULPI_OTG_CTRL_DM_PULLDOWN | ULPI_OTG_CTRL_DP_PULLDOWN);
1819 // dev_err(musb->controller, "VBUS workaround error\n");
1823 /* --------------------------------------------------------------------------
1827 static struct musb *__init
1828 allocate_instance(struct device *dev,
1829 struct musb_hdrc_config *config, void __iomem *mbase)
1832 struct musb_hw_ep *ep;
1834 struct usb_hcd *hcd;
1836 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1839 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1841 musb = hcd_to_musb(hcd);
1842 INIT_LIST_HEAD(&musb->control);
1843 INIT_LIST_HEAD(&musb->in_bulk);
1844 INIT_LIST_HEAD(&musb->out_bulk);
1846 hcd->uses_new_polling = 1;
1849 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1850 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1851 dev_set_drvdata(dev, musb);
1852 musb->mregs = mbase;
1853 musb->ctrl_base = mbase;
1854 musb->nIrq = -ENODEV;
1855 musb->config = config;
1856 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1857 for (epnum = 0, ep = musb->endpoints;
1858 epnum < musb->config->num_eps;
1864 musb->controller = dev;
1869 static void musb_free(struct musb *musb)
1871 /* this has multiple entry modes. it handles fault cleanup after
1872 * probe(), where things may be partially set up, as well as rmmod
1873 * cleanup after everything's been de-activated.
1877 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1880 if (musb->nIrq >= 0) {
1882 disable_irq_wake(musb->nIrq);
1883 free_irq(musb->nIrq, musb);
1885 if (is_dma_capable() && musb->dma_controller) {
1886 struct dma_controller *c = musb->dma_controller;
1889 dma_controller_destroy(c);
1896 * Perform generic per-controller initialization.
1898 * @pDevice: the controller (already clocked, etc)
1900 * @mregs: virtual address of controller registers,
1901 * not yet corrected for platform-specific offsets
1904 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1908 struct musb_hdrc_platform_data *plat = dev->platform_data;
1910 /* The driver might handle more features than the board; OK.
1911 * Fail when the board needs a feature that's not enabled.
1914 dev_dbg(dev, "no platform_data?\n");
1920 musb = allocate_instance(dev, plat->config, ctrl);
1926 pm_runtime_use_autosuspend(musb->controller);
1927 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1928 pm_runtime_enable(musb->controller);
1930 spin_lock_init(&musb->lock);
1931 musb->board_mode = plat->mode;
1932 musb->board_set_power = plat->set_power;
1933 musb->min_power = plat->min_power;
1934 musb->ops = plat->platform_ops;
1936 /* The musb_platform_init() call:
1937 * - adjusts musb->mregs and musb->isr if needed,
1938 * - may initialize an integrated tranceiver
1939 * - initializes musb->xceiv, usually by otg_get_transceiver()
1940 * - stops powering VBUS
1942 * There are various transceiver configurations. Blackfin,
1943 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1944 * external/discrete ones in various flavors (twl4030 family,
1945 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1947 musb->isr = generic_interrupt;
1948 status = musb_platform_init(musb);
1957 if (!musb->xceiv->io_ops) {
1958 musb->xceiv->io_priv = musb->mregs;
1959 musb->xceiv->io_ops = &musb_ulpi_access;
1962 #ifndef CONFIG_MUSB_PIO_ONLY
1963 if (use_dma && dev->dma_mask) {
1964 struct dma_controller *c;
1966 c = dma_controller_create(musb, musb->mregs);
1967 musb->dma_controller = c;
1972 /* ideally this would be abstracted in platform setup */
1973 if (!is_dma_capable() || !musb->dma_controller)
1974 dev->dma_mask = NULL;
1976 /* be sure interrupts are disabled before connecting ISR */
1977 musb_platform_disable(musb);
1978 musb_generic_disable(musb);
1980 /* setup musb parts of the core (especially endpoints) */
1981 status = musb_core_init(plat->config->multipoint
1982 ? MUSB_CONTROLLER_MHDRC
1983 : MUSB_CONTROLLER_HDRC, musb);
1987 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1989 /* Init IRQ workqueue before request_irq */
1990 INIT_WORK(&musb->irq_work, musb_irq_work);
1992 INIT_DELAYED_WORK(&musb->vbus_workaround_work, musb_vbus_workaround_work);
1994 /* attach to the IRQ */
1995 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1996 dev_err(dev, "request_irq %d failed!\n", nIrq);
2001 /* FIXME this handles wakeup irqs wrong */
2002 if (enable_irq_wake(nIrq) == 0) {
2004 device_init_wakeup(dev, 1);
2009 /* host side needs more setup */
2010 if (is_host_enabled(musb)) {
2011 struct usb_hcd *hcd = musb_to_hcd(musb);
2013 otg_set_host(musb->xceiv, &hcd->self);
2015 if (is_otg_enabled(musb))
2016 hcd->self.otg_port = 1;
2017 musb->xceiv->host = &hcd->self;
2018 hcd->power_budget = 2 * (plat->power ? : 250);
2020 /* program PHY to use external vBus if required */
2021 if (plat->extvbus) {
2022 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2023 busctl |= MUSB_ULPI_USE_EXTVBUS;
2024 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2028 /* For the host-only role, we can activate right away.
2029 * (We expect the ID pin to be forcibly grounded!!)
2030 * Otherwise, wait till the gadget driver hooks up.
2032 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2033 struct usb_hcd *hcd = musb_to_hcd(musb);
2035 MUSB_HST_MODE(musb);
2036 musb->xceiv->default_a = 1;
2037 musb->xceiv->state = OTG_STATE_A_IDLE;
2039 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2041 hcd->self.uses_pio_for_control = 1;
2042 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2044 musb_readb(musb->mregs, MUSB_DEVCTL),
2045 (musb_readb(musb->mregs, MUSB_DEVCTL)
2046 & MUSB_DEVCTL_BDEVICE
2049 } else /* peripheral is enabled */ {
2050 MUSB_DEV_MODE(musb);
2051 musb->xceiv->default_a = 0;
2052 musb->xceiv->state = OTG_STATE_B_IDLE;
2054 status = musb_gadget_setup(musb);
2056 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2057 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2059 musb_readb(musb->mregs, MUSB_DEVCTL));
2065 pm_runtime_put(musb->controller);
2067 status = musb_init_debugfs(musb);
2072 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2077 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2079 switch (musb->board_mode) {
2080 case MUSB_HOST: s = "Host"; break;
2081 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2082 default: s = "OTG"; break;
2085 (is_dma_capable() && musb->dma_controller)
2092 musb_exit_debugfs(musb);
2095 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2096 usb_remove_hcd(musb_to_hcd(musb));
2098 musb_gadget_cleanup(musb);
2102 device_init_wakeup(dev, 0);
2103 musb_platform_exit(musb);
2106 dev_err(musb->controller,
2107 "musb_init_controller failed with status %d\n", status);
2117 /*-------------------------------------------------------------------------*/
2119 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2120 * bridge to a platform device; this driver then suffices.
2123 #ifndef CONFIG_MUSB_PIO_ONLY
2124 static u64 *orig_dma_mask;
2127 static int __init musb_probe(struct platform_device *pdev)
2129 struct device *dev = &pdev->dev;
2130 int irq = platform_get_irq_byname(pdev, "mc");
2132 struct resource *iomem;
2135 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2136 if (!iomem || irq <= 0)
2139 base = ioremap(iomem->start, resource_size(iomem));
2141 dev_err(dev, "ioremap failed\n");
2145 #ifndef CONFIG_MUSB_PIO_ONLY
2146 /* clobbered by use_dma=n */
2147 orig_dma_mask = dev->dma_mask;
2149 status = musb_init_controller(dev, irq, base);
2156 static int __exit musb_remove(struct platform_device *pdev)
2158 struct musb *musb = dev_to_musb(&pdev->dev);
2159 void __iomem *ctrl_base = musb->ctrl_base;
2161 /* this gets called on rmmod.
2162 * - Host mode: host may still be active
2163 * - Peripheral mode: peripheral is deactivated (or never-activated)
2164 * - OTG mode: both roles are deactivated (or never-activated)
2166 musb_exit_debugfs(musb);
2167 musb_shutdown(pdev);
2171 device_init_wakeup(&pdev->dev, 0);
2172 #ifndef CONFIG_MUSB_PIO_ONLY
2173 pdev->dev.dma_mask = orig_dma_mask;
2180 static void musb_save_context(struct musb *musb)
2183 void __iomem *musb_base = musb->mregs;
2186 if (is_host_enabled(musb)) {
2187 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2188 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2189 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2191 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2192 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2193 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2194 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2195 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2196 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2198 for (i = 0; i < musb->config->num_eps; ++i) {
2199 struct musb_hw_ep *hw_ep;
2201 hw_ep = &musb->endpoints[i];
2209 musb_writeb(musb_base, MUSB_INDEX, i);
2210 musb->context.index_regs[i].txmaxp =
2211 musb_readw(epio, MUSB_TXMAXP);
2212 musb->context.index_regs[i].txcsr =
2213 musb_readw(epio, MUSB_TXCSR);
2214 musb->context.index_regs[i].rxmaxp =
2215 musb_readw(epio, MUSB_RXMAXP);
2216 musb->context.index_regs[i].rxcsr =
2217 musb_readw(epio, MUSB_RXCSR);
2219 if (musb->dyn_fifo) {
2220 musb->context.index_regs[i].txfifoadd =
2221 musb_read_txfifoadd(musb_base);
2222 musb->context.index_regs[i].rxfifoadd =
2223 musb_read_rxfifoadd(musb_base);
2224 musb->context.index_regs[i].txfifosz =
2225 musb_read_txfifosz(musb_base);
2226 musb->context.index_regs[i].rxfifosz =
2227 musb_read_rxfifosz(musb_base);
2229 if (is_host_enabled(musb)) {
2230 musb->context.index_regs[i].txtype =
2231 musb_readb(epio, MUSB_TXTYPE);
2232 musb->context.index_regs[i].txinterval =
2233 musb_readb(epio, MUSB_TXINTERVAL);
2234 musb->context.index_regs[i].rxtype =
2235 musb_readb(epio, MUSB_RXTYPE);
2236 musb->context.index_regs[i].rxinterval =
2237 musb_readb(epio, MUSB_RXINTERVAL);
2239 musb->context.index_regs[i].txfunaddr =
2240 musb_read_txfunaddr(musb_base, i);
2241 musb->context.index_regs[i].txhubaddr =
2242 musb_read_txhubaddr(musb_base, i);
2243 musb->context.index_regs[i].txhubport =
2244 musb_read_txhubport(musb_base, i);
2246 musb->context.index_regs[i].rxfunaddr =
2247 musb_read_rxfunaddr(musb_base, i);
2248 musb->context.index_regs[i].rxhubaddr =
2249 musb_read_rxhubaddr(musb_base, i);
2250 musb->context.index_regs[i].rxhubport =
2251 musb_read_rxhubport(musb_base, i);
2256 static void musb_restore_context(struct musb *musb)
2259 void __iomem *musb_base = musb->mregs;
2260 void __iomem *ep_target_regs;
2263 if (is_host_enabled(musb)) {
2264 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2265 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2266 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2268 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2269 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2270 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2271 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2272 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2274 for (i = 0; i < musb->config->num_eps; ++i) {
2275 struct musb_hw_ep *hw_ep;
2277 hw_ep = &musb->endpoints[i];
2285 musb_writeb(musb_base, MUSB_INDEX, i);
2286 musb_writew(epio, MUSB_TXMAXP,
2287 musb->context.index_regs[i].txmaxp);
2288 musb_writew(epio, MUSB_TXCSR,
2289 musb->context.index_regs[i].txcsr);
2290 musb_writew(epio, MUSB_RXMAXP,
2291 musb->context.index_regs[i].rxmaxp);
2292 musb_writew(epio, MUSB_RXCSR,
2293 musb->context.index_regs[i].rxcsr);
2295 if (musb->dyn_fifo) {
2296 musb_write_txfifosz(musb_base,
2297 musb->context.index_regs[i].txfifosz);
2298 musb_write_rxfifosz(musb_base,
2299 musb->context.index_regs[i].rxfifosz);
2300 musb_write_txfifoadd(musb_base,
2301 musb->context.index_regs[i].txfifoadd);
2302 musb_write_rxfifoadd(musb_base,
2303 musb->context.index_regs[i].rxfifoadd);
2306 if (is_host_enabled(musb)) {
2307 musb_writeb(epio, MUSB_TXTYPE,
2308 musb->context.index_regs[i].txtype);
2309 musb_writeb(epio, MUSB_TXINTERVAL,
2310 musb->context.index_regs[i].txinterval);
2311 musb_writeb(epio, MUSB_RXTYPE,
2312 musb->context.index_regs[i].rxtype);
2313 musb_writeb(epio, MUSB_RXINTERVAL,
2315 musb->context.index_regs[i].rxinterval);
2316 musb_write_txfunaddr(musb_base, i,
2317 musb->context.index_regs[i].txfunaddr);
2318 musb_write_txhubaddr(musb_base, i,
2319 musb->context.index_regs[i].txhubaddr);
2320 musb_write_txhubport(musb_base, i,
2321 musb->context.index_regs[i].txhubport);
2324 musb_read_target_reg_base(i, musb_base);
2326 musb_write_rxfunaddr(ep_target_regs,
2327 musb->context.index_regs[i].rxfunaddr);
2328 musb_write_rxhubaddr(ep_target_regs,
2329 musb->context.index_regs[i].rxhubaddr);
2330 musb_write_rxhubport(ep_target_regs,
2331 musb->context.index_regs[i].rxhubport);
2334 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2337 static int musb_suspend(struct device *dev)
2339 struct musb *musb = dev_to_musb(dev);
2340 unsigned long flags;
2342 spin_lock_irqsave(&musb->lock, flags);
2344 if (is_peripheral_active(musb)) {
2345 /* FIXME force disconnect unless we know USB will wake
2346 * the system up quickly enough to respond ...
2348 } else if (is_host_active(musb)) {
2349 /* we know all the children are suspended; sometimes
2350 * they will even be wakeup-enabled.
2354 spin_unlock_irqrestore(&musb->lock, flags);
2358 static int musb_resume_noirq(struct device *dev)
2360 /* for static cmos like DaVinci, register values were preserved
2361 * unless for some reason the whole soc powered down or the USB
2362 * module got reset through the PSC (vs just being disabled).
2367 static int musb_runtime_suspend(struct device *dev)
2369 struct musb *musb = dev_to_musb(dev);
2371 musb_save_context(musb);
2376 static int musb_runtime_resume(struct device *dev)
2378 struct musb *musb = dev_to_musb(dev);
2379 static int first = 1;
2382 * When pm_runtime_get_sync called for the first time in driver
2383 * init, some of the structure is still not initialized which is
2384 * used in restore function. But clock needs to be
2385 * enabled before any register access, so
2386 * pm_runtime_get_sync has to be called.
2387 * Also context restore without save does not make
2391 musb_restore_context(musb);
2397 static const struct dev_pm_ops musb_dev_pm_ops = {
2398 .suspend = musb_suspend,
2399 .resume_noirq = musb_resume_noirq,
2400 .runtime_suspend = musb_runtime_suspend,
2401 .runtime_resume = musb_runtime_resume,
2404 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2406 #define MUSB_DEV_PM_OPS NULL
2409 static struct platform_driver musb_driver = {
2411 .name = (char *)musb_driver_name,
2412 .bus = &platform_bus_type,
2413 .owner = THIS_MODULE,
2414 .pm = MUSB_DEV_PM_OPS,
2416 .remove = __exit_p(musb_remove),
2417 .shutdown = musb_shutdown,
2420 /*-------------------------------------------------------------------------*/
2422 static int __init musb_init(void)
2427 pr_info("%s: version " MUSB_VERSION ", "
2430 "otg (peripheral+host)",
2432 return platform_driver_probe(&musb_driver, musb_probe);
2435 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2436 * and before usb gadget and host-side drivers start to register
2438 fs_initcall(musb_init);
2440 static void __exit musb_cleanup(void)
2442 platform_driver_unregister(&musb_driver);
2444 module_exit(musb_cleanup);