2 * MUSB OTG controller driver for Blackfin Processors
4 * Copyright 2006-2008 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/init.h>
15 #include <linux/list.h>
16 #include <linux/gpio.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
21 #include <asm/cacheflush.h>
23 #include "musb_core.h"
24 #include "musbhsdma.h"
29 struct platform_device *musb;
31 #define glue_to_musb(g) platform_get_drvdata(g->musb)
34 * Load an endpoint's FIFO
36 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
38 void __iomem *fifo = hw_ep->fifo;
39 void __iomem *epio = hw_ep->regs;
40 u8 epnum = hw_ep->epnum;
44 musb_writew(epio, MUSB_TXCOUNT, len);
46 DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
47 hw_ep->epnum, fifo, len, src, epio);
49 dump_fifo_data(src, len);
51 if (!ANOMALY_05000380 && epnum != 0) {
54 flush_dcache_range((unsigned long)src,
55 (unsigned long)(src + len));
57 /* Setup DMA address register */
59 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
62 dma_reg = (u32)src >> 16;
63 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
66 /* Setup DMA count register */
67 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
68 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
72 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
73 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
76 /* Wait for compelete */
77 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
80 /* acknowledge dma interrupt */
81 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
85 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
90 if (unlikely((unsigned long)src & 0x01))
91 outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
93 outsw((unsigned long)fifo, src, (len + 1) >> 1);
97 * Unload an endpoint's FIFO
99 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
101 void __iomem *fifo = hw_ep->fifo;
102 u8 epnum = hw_ep->epnum;
104 if (ANOMALY_05000467 && epnum != 0) {
107 invalidate_dcache_range((unsigned long)dst,
108 (unsigned long)(dst + len));
110 /* Setup DMA address register */
112 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
115 dma_reg = (u32)dst >> 16;
116 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
119 /* Setup DMA count register */
120 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
121 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
125 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
126 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
129 /* Wait for compelete */
130 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
133 /* acknowledge dma interrupt */
134 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
138 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
142 /* Read the last byte of packet with odd size from address fifo + 4
143 * to trigger 1 byte access to EP0 FIFO.
146 *dst = (u8)inw((unsigned long)fifo + 4);
148 if (unlikely((unsigned long)dst & 0x01))
149 insw_8((unsigned long)fifo, dst, len >> 1);
151 insw((unsigned long)fifo, dst, len >> 1);
154 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
157 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
158 'R', hw_ep->epnum, fifo, len, dst);
160 dump_fifo_data(dst, len);
163 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
166 irqreturn_t retval = IRQ_NONE;
167 struct musb *musb = __hci;
169 spin_lock_irqsave(&musb->lock, flags);
171 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
172 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
173 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
175 if (musb->int_usb || musb->int_tx || musb->int_rx) {
176 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
177 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
178 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
179 retval = musb_interrupt(musb);
182 /* Start sampling ID pin, when plug is removed from MUSB */
183 if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
184 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) ||
185 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
186 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
187 musb->a_wait_bcon = TIMER_DELAY;
190 spin_unlock_irqrestore(&musb->lock, flags);
195 static void musb_conn_timer_handler(unsigned long _musb)
197 struct musb *musb = (void *)_musb;
202 spin_lock_irqsave(&musb->lock, flags);
203 switch (musb->xceiv->state) {
204 case OTG_STATE_A_IDLE:
205 case OTG_STATE_A_WAIT_BCON:
206 /* Start a new session */
207 val = musb_readw(musb->mregs, MUSB_DEVCTL);
208 val &= ~MUSB_DEVCTL_SESSION;
209 musb_writew(musb->mregs, MUSB_DEVCTL, val);
210 val |= MUSB_DEVCTL_SESSION;
211 musb_writew(musb->mregs, MUSB_DEVCTL, val);
212 /* Check if musb is host or peripheral. */
213 val = musb_readw(musb->mregs, MUSB_DEVCTL);
215 if (!(val & MUSB_DEVCTL_BDEVICE)) {
216 gpio_set_value(musb->config->gpio_vrsel, 1);
217 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
219 gpio_set_value(musb->config->gpio_vrsel, 0);
220 /* Ignore VBUSERROR and SUSPEND IRQ */
221 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
222 val &= ~MUSB_INTR_VBUSERROR;
223 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
225 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
226 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
227 if (is_otg_enabled(musb))
228 musb->xceiv->state = OTG_STATE_B_IDLE;
230 musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
232 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
234 case OTG_STATE_B_IDLE:
236 if (!is_peripheral_enabled(musb))
238 /* Start a new session. It seems that MUSB needs taking
239 * some time to recognize the type of the plug inserted?
241 val = musb_readw(musb->mregs, MUSB_DEVCTL);
242 val |= MUSB_DEVCTL_SESSION;
243 musb_writew(musb->mregs, MUSB_DEVCTL, val);
244 val = musb_readw(musb->mregs, MUSB_DEVCTL);
246 if (!(val & MUSB_DEVCTL_BDEVICE)) {
247 gpio_set_value(musb->config->gpio_vrsel, 1);
248 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
250 gpio_set_value(musb->config->gpio_vrsel, 0);
252 /* Ignore VBUSERROR and SUSPEND IRQ */
253 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
254 val &= ~MUSB_INTR_VBUSERROR;
255 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
257 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
258 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
260 /* Toggle the Soft Conn bit, so that we can response to
261 * the inserting of either A-plug or B-plug.
264 val = musb_readb(musb->mregs, MUSB_POWER);
265 val &= ~MUSB_POWER_SOFTCONN;
266 musb_writeb(musb->mregs, MUSB_POWER, val);
269 val = musb_readb(musb->mregs, MUSB_POWER);
270 val |= MUSB_POWER_SOFTCONN;
271 musb_writeb(musb->mregs, MUSB_POWER, val);
274 /* The delay time is set to 1/4 second by default,
275 * shortening it, if accelerating A-plug detection
276 * is needed in OTG mode.
278 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
282 DBG(1, "%s state not handled\n", otg_state_string(musb));
285 spin_unlock_irqrestore(&musb->lock, flags);
287 DBG(4, "state is %s\n", otg_state_string(musb));
290 static void bfin_musb_enable(struct musb *musb)
292 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
293 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
294 musb->a_wait_bcon = TIMER_DELAY;
298 static void bfin_musb_disable(struct musb *musb)
302 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
304 int value = musb->config->gpio_vrsel_active;
307 gpio_set_value(musb->config->gpio_vrsel, value);
309 DBG(1, "VBUS %s, devctl %02x "
310 /* otg %3x conf %08x prcm %08x */ "\n",
311 otg_state_string(musb),
312 musb_readb(musb->mregs, MUSB_DEVCTL));
315 static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
320 static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
322 if (!is_otg_enabled(musb) && is_host_enabled(musb))
323 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
326 static int bfin_musb_vbus_status(struct musb *musb)
331 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
336 static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
337 u16 packet_sz, u8 *mode,
338 dma_addr_t *dma_addr, u32 *len)
340 struct musb_dma_channel *musb_channel = channel->private_data;
343 * Anomaly 05000450 might cause data corruption when using DMA
344 * MODE 1 transmits with short packet. So to work around this,
345 * we truncate all MODE 1 transfers down to a multiple of the
346 * max packet size, and then do the last short packet transfer
347 * (if there is any) using MODE 0.
349 if (ANOMALY_05000450) {
350 if (musb_channel->transmit && *mode == 1)
351 *len = *len - (*len % packet_sz);
357 static void bfin_musb_reg_init(struct musb *musb)
359 if (ANOMALY_05000346) {
360 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
364 if (ANOMALY_05000347) {
365 bfin_write_USB_APHY_CNTRL(0x0);
369 /* Configure PLL oscillator register */
370 bfin_write_USB_PLLOSC_CTRL(0x3080 |
371 ((480/musb->config->clkin) << 1));
374 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
377 bfin_write_USB_EP_NI0_RXMAXP(64);
380 bfin_write_USB_EP_NI0_TXMAXP(64);
383 /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
384 bfin_write_USB_GLOBINTR(0x7);
387 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
388 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
389 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
390 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
391 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
395 static int bfin_musb_init(struct musb *musb)
399 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
400 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
401 * be low for DEVICE mode and high for HOST mode. We set it high
402 * here because we are in host mode
405 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
406 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
407 musb->config->gpio_vrsel);
410 gpio_direction_output(musb->config->gpio_vrsel, 0);
412 usb_nop_xceiv_register();
413 musb->xceiv = otg_get_transceiver();
415 gpio_free(musb->config->gpio_vrsel);
419 bfin_musb_reg_init(musb);
421 if (is_host_enabled(musb)) {
422 setup_timer(&musb_conn_timer,
423 musb_conn_timer_handler, (unsigned long) musb);
425 if (is_peripheral_enabled(musb))
426 musb->xceiv->set_power = bfin_musb_set_power;
428 musb->isr = blackfin_interrupt;
429 musb->double_buffer_not_ok = true;
434 static int bfin_musb_exit(struct musb *musb)
436 gpio_free(musb->config->gpio_vrsel);
438 otg_put_transceiver(musb->xceiv);
439 usb_nop_xceiv_unregister();
443 static const struct musb_platform_ops bfin_ops = {
444 .init = bfin_musb_init,
445 .exit = bfin_musb_exit,
447 .enable = bfin_musb_enable,
448 .disable = bfin_musb_disable,
450 .set_mode = bfin_musb_set_mode,
451 .try_idle = bfin_musb_try_idle,
453 .vbus_status = bfin_musb_vbus_status,
454 .set_vbus = bfin_musb_set_vbus,
456 .adjust_channel_params = bfin_musb_adjust_channel_params,
459 static u64 bfin_dmamask = DMA_BIT_MASK(32);
461 static int __init bfin_probe(struct platform_device *pdev)
463 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
464 struct platform_device *musb;
465 struct bfin_glue *glue;
469 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
471 dev_err(&pdev->dev, "failed to allocate glue context\n");
475 musb = platform_device_alloc("musb-hdrc", -1);
477 dev_err(&pdev->dev, "failed to allocate musb device\n");
481 musb->dev.parent = &pdev->dev;
482 musb->dev.dma_mask = &bfin_dmamask;
483 musb->dev.coherent_dma_mask = bfin_dmamask;
485 glue->dev = &pdev->dev;
488 pdata->platform_ops = &bfin_ops;
490 platform_set_drvdata(pdev, glue);
492 ret = platform_device_add_resources(musb, pdev->resource,
493 pdev->num_resources);
495 dev_err(&pdev->dev, "failed to add resources\n");
499 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
501 dev_err(&pdev->dev, "failed to add platform_data\n");
505 ret = platform_device_add(musb);
507 dev_err(&pdev->dev, "failed to register musb device\n");
514 platform_device_put(musb);
523 static int __exit bfin_remove(struct platform_device *pdev)
525 struct bfin_glue *glue = platform_get_drvdata(pdev);
527 platform_device_del(glue->musb);
528 platform_device_put(glue->musb);
535 static int bfin_suspend(struct device *dev)
537 struct bfin_glue *glue = dev_get_drvdata(dev);
538 struct musb *musb = glue_to_musb(glue);
540 if (is_host_active(musb))
542 * During hibernate gpio_vrsel will change from high to low
543 * low which will generate wakeup event resume the system
544 * immediately. Set it to 0 before hibernate to avoid this
547 gpio_set_value(musb->config->gpio_vrsel, 0);
552 static int bfin_resume(struct device *dev)
554 struct bfin_glue *glue = dev_get_drvdata(dev);
555 struct musb *musb = glue_to_musb(glue);
557 bfin_musb_reg_init(musb);
562 static struct dev_pm_ops bfin_pm_ops = {
563 .suspend = bfin_suspend,
564 .resume = bfin_resume,
567 #define DEV_PM_OPS &bfin_pm_ops
569 #define DEV_PM_OPS NULL
572 static struct platform_driver bfin_driver = {
573 .remove = __exit_p(bfin_remove),
575 .name = "musb-blackfin",
580 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
581 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
582 MODULE_LICENSE("GPL v2");
584 static int __init bfin_init(void)
586 return platform_driver_probe(&bfin_driver, bfin_probe);
588 subsys_initcall(bfin_init);
590 static void __exit bfin_exit(void)
592 platform_driver_unregister(&bfin_driver);
594 module_exit(bfin_exit);