2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
82 unsigned long segment_offset;
84 if (!seg || !trb || trb < seg->trbs)
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
90 return seg->dma + (segment_offset * sizeof(*trb));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
116 return TRB_TYPE_LINK_LE32(trb->link.control);
119 static int enqueue_is_link_trb(struct xhci_ring *ring)
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
134 if (last_trb(xhci, ring, *seg, *trb)) {
136 *trb = ((*seg)->trbs);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
148 unsigned long long addr;
154 * Update the dequeue pointer further if that was a link TRB or
155 * we're at the end of an event ring segment (which doesn't have
158 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
159 if (consumer && last_trb_on_last_seg(xhci, ring,
160 ring->deq_seg, ring->dequeue)) {
162 xhci_dbg(xhci, "Toggle cycle state "
163 "for ring %p = %i\n",
167 ring->cycle_state = (ring->cycle_state ? 0 : 1);
169 ring->deq_seg = ring->deq_seg->next;
170 ring->dequeue = ring->deq_seg->trbs;
174 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
180 * See Cycle bit rules. SW is the consumer for the event ring only.
181 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
183 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
184 * chain bit is set), then set the chain bit in all the following link TRBs.
185 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
186 * have their chain bit cleared (so that each Link TRB is a separate TD).
188 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
189 * set, but other sections talk about dealing with the chain bit set. This was
190 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
191 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
193 * @more_trbs_coming: Will you enqueue more TRBs before calling
194 * prepare_transfer()?
196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
197 bool consumer, bool more_trbs_coming, bool isoc)
200 union xhci_trb *next;
201 unsigned long long addr;
203 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
204 next = ++(ring->enqueue);
207 /* Update the dequeue pointer further if that was a link TRB or we're at
208 * the end of an event ring segment (which doesn't have link TRBS)
210 while (last_trb(xhci, ring, ring->enq_seg, next)) {
212 if (ring != xhci->event_ring) {
214 * If the caller doesn't plan on enqueueing more
215 * TDs before ringing the doorbell, then we
216 * don't want to give the link TRB to the
217 * hardware just yet. We'll give the link TRB
218 * back in prepare_ring() just before we enqueue
219 * the TD at the top of the ring.
221 if (!chain && !more_trbs_coming)
224 /* If we're not dealing with 0.95 hardware or
225 * isoc rings on AMD 0.96 host,
226 * carry over the chain bit of the previous TRB
227 * (which may mean the chain bit is cleared).
229 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
230 && !xhci_link_trb_quirk(xhci)) {
231 next->link.control &=
232 cpu_to_le32(~TRB_CHAIN);
233 next->link.control |=
236 /* Give this link TRB to the hardware */
238 next->link.control ^= cpu_to_le32(TRB_CYCLE);
240 /* Toggle the cycle bit after the last ring segment. */
241 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
242 ring->cycle_state = (ring->cycle_state ? 0 : 1);
244 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
246 (unsigned int) ring->cycle_state);
249 ring->enq_seg = ring->enq_seg->next;
250 ring->enqueue = ring->enq_seg->trbs;
251 next = ring->enqueue;
253 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
257 * Check to see if there's room to enqueue num_trbs on the ring. See rules
259 * FIXME: this would be simpler and faster if we just kept track of the number
260 * of free TRBs in a ring.
262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
263 unsigned int num_trbs)
266 union xhci_trb *enq = ring->enqueue;
267 struct xhci_segment *enq_seg = ring->enq_seg;
268 struct xhci_segment *cur_seg;
269 unsigned int left_on_ring;
271 /* If we are currently pointing to a link TRB, advance the
272 * enqueue pointer before checking for space */
273 while (last_trb(xhci, ring, enq_seg, enq)) {
274 enq_seg = enq_seg->next;
278 /* Check if ring is empty */
279 if (enq == ring->dequeue) {
280 /* Can't use link trbs */
281 left_on_ring = TRBS_PER_SEGMENT - 1;
282 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
283 cur_seg = cur_seg->next)
284 left_on_ring += TRBS_PER_SEGMENT - 1;
286 /* Always need one TRB free in the ring. */
288 if (num_trbs > left_on_ring) {
289 xhci_warn(xhci, "Not enough room on ring; "
290 "need %u TRBs, %u TRBs left\n",
291 num_trbs, left_on_ring);
296 /* Make sure there's an extra empty TRB available */
297 for (i = 0; i <= num_trbs; ++i) {
298 if (enq == ring->dequeue)
301 while (last_trb(xhci, ring, enq_seg, enq)) {
302 enq_seg = enq_seg->next;
309 /* Ring the host controller doorbell after placing a command on the ring */
310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
312 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
315 xhci_dbg(xhci, "// Ding dong!\n");
316 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
317 /* Flush PCI posted writes */
318 xhci_readl(xhci, &xhci->dba->doorbell[0]);
321 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
322 unsigned int slot_id,
323 unsigned int ep_index,
324 unsigned int stream_id)
326 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
327 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
328 unsigned int ep_state = ep->ep_state;
330 /* Don't ring the doorbell for this endpoint if there are pending
331 * cancellations because we don't want to interrupt processing.
332 * We don't want to restart any stream rings if there's a set dequeue
333 * pointer command pending because the device can choose to start any
334 * stream once the endpoint is on the HW schedule.
335 * FIXME - check all the stream rings for pending cancellations.
337 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
338 (ep_state & EP_HALTED))
340 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
341 /* The CPU has better things to do at this point than wait for a
342 * write-posting flush. It'll get there soon enough.
346 /* Ring the doorbell for any rings with pending URBs */
347 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
348 unsigned int slot_id,
349 unsigned int ep_index)
351 unsigned int stream_id;
352 struct xhci_virt_ep *ep;
354 ep = &xhci->devs[slot_id]->eps[ep_index];
356 /* A ring has pending URBs if its TD list is not empty */
357 if (!(ep->ep_state & EP_HAS_STREAMS)) {
358 if (!(list_empty(&ep->ring->td_list)))
359 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
363 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
365 struct xhci_stream_info *stream_info = ep->stream_info;
366 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
367 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
373 * Find the segment that trb is in. Start searching in start_seg.
374 * If we must move past a segment that has a link TRB with a toggle cycle state
375 * bit set, then we will toggle the value pointed at by cycle_state.
377 static struct xhci_segment *find_trb_seg(
378 struct xhci_segment *start_seg,
379 union xhci_trb *trb, int *cycle_state)
381 struct xhci_segment *cur_seg = start_seg;
382 struct xhci_generic_trb *generic_trb;
384 while (cur_seg->trbs > trb ||
385 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
386 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
387 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
389 cur_seg = cur_seg->next;
390 if (cur_seg == start_seg)
391 /* Looped over the entire list. Oops! */
398 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
399 unsigned int slot_id, unsigned int ep_index,
400 unsigned int stream_id)
402 struct xhci_virt_ep *ep;
404 ep = &xhci->devs[slot_id]->eps[ep_index];
405 /* Common case: no streams */
406 if (!(ep->ep_state & EP_HAS_STREAMS))
409 if (stream_id == 0) {
411 "WARN: Slot ID %u, ep index %u has streams, "
412 "but URB has no stream ID.\n",
417 if (stream_id < ep->stream_info->num_streams)
418 return ep->stream_info->stream_rings[stream_id];
421 "WARN: Slot ID %u, ep index %u has "
422 "stream IDs 1 to %u allocated, "
423 "but stream ID %u is requested.\n",
425 ep->stream_info->num_streams - 1,
430 /* Get the right ring for the given URB.
431 * If the endpoint supports streams, boundary check the URB's stream ID.
432 * If the endpoint doesn't support streams, return the singular endpoint ring.
434 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
437 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
438 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
442 * Move the xHC's endpoint ring dequeue pointer past cur_td.
443 * Record the new state of the xHC's endpoint ring dequeue segment,
444 * dequeue pointer, and new consumer cycle state in state.
445 * Update our internal representation of the ring's dequeue pointer.
447 * We do this in three jumps:
448 * - First we update our new ring state to be the same as when the xHC stopped.
449 * - Then we traverse the ring to find the segment that contains
450 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
451 * any link TRBs with the toggle cycle bit set.
452 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
453 * if we've moved it past a link TRB with the toggle cycle bit set.
455 * Some of the uses of xhci_generic_trb are grotty, but if they're done
456 * with correct __le32 accesses they should work fine. Only users of this are
459 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
460 unsigned int slot_id, unsigned int ep_index,
461 unsigned int stream_id, struct xhci_td *cur_td,
462 struct xhci_dequeue_state *state)
464 struct xhci_virt_device *dev = xhci->devs[slot_id];
465 struct xhci_ring *ep_ring;
466 struct xhci_generic_trb *trb;
467 struct xhci_ep_ctx *ep_ctx;
470 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
471 ep_index, stream_id);
473 xhci_warn(xhci, "WARN can't find new dequeue state "
474 "for invalid stream ID %u.\n",
478 state->new_cycle_state = 0;
479 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
480 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
481 dev->eps[ep_index].stopped_trb,
482 &state->new_cycle_state);
483 if (!state->new_deq_seg) {
488 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
489 xhci_dbg(xhci, "Finding endpoint context\n");
490 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
491 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
493 state->new_deq_ptr = cur_td->last_trb;
494 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
495 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
497 &state->new_cycle_state);
498 if (!state->new_deq_seg) {
503 trb = &state->new_deq_ptr->generic;
504 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
505 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
506 state->new_cycle_state ^= 0x1;
507 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
510 * If there is only one segment in a ring, find_trb_seg()'s while loop
511 * will not run, and it will return before it has a chance to see if it
512 * needs to toggle the cycle bit. It can't tell if the stalled transfer
513 * ended just before the link TRB on a one-segment ring, or if the TD
514 * wrapped around the top of the ring, because it doesn't have the TD in
515 * question. Look for the one-segment case where stalled TRB's address
516 * is greater than the new dequeue pointer address.
518 if (ep_ring->first_seg == ep_ring->first_seg->next &&
519 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
520 state->new_cycle_state ^= 0x1;
521 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
523 /* Don't update the ring cycle state for the producer (us). */
524 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
526 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
527 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
528 (unsigned long long) addr);
531 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
532 * (The last TRB actually points to the ring enqueue pointer, which is not part
533 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
535 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
536 struct xhci_td *cur_td, bool flip_cycle)
538 struct xhci_segment *cur_seg;
539 union xhci_trb *cur_trb;
541 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
543 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
544 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
545 /* Unchain any chained Link TRBs, but
546 * leave the pointers intact.
548 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
549 /* Flip the cycle bit (link TRBs can't be the first
553 cur_trb->generic.field[3] ^=
554 cpu_to_le32(TRB_CYCLE);
555 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
556 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
557 "in seg %p (0x%llx dma)\n",
559 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
561 (unsigned long long)cur_seg->dma);
563 cur_trb->generic.field[0] = 0;
564 cur_trb->generic.field[1] = 0;
565 cur_trb->generic.field[2] = 0;
566 /* Preserve only the cycle bit of this TRB */
567 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
568 /* Flip the cycle bit except on the first or last TRB */
569 if (flip_cycle && cur_trb != cur_td->first_trb &&
570 cur_trb != cur_td->last_trb)
571 cur_trb->generic.field[3] ^=
572 cpu_to_le32(TRB_CYCLE);
573 cur_trb->generic.field[3] |= cpu_to_le32(
574 TRB_TYPE(TRB_TR_NOOP));
575 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
576 "in seg %p (0x%llx dma)\n",
578 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
580 (unsigned long long)cur_seg->dma);
582 if (cur_trb == cur_td->last_trb)
587 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
588 unsigned int ep_index, unsigned int stream_id,
589 struct xhci_segment *deq_seg,
590 union xhci_trb *deq_ptr, u32 cycle_state);
592 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
593 unsigned int slot_id, unsigned int ep_index,
594 unsigned int stream_id,
595 struct xhci_dequeue_state *deq_state)
597 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
599 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
600 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
601 deq_state->new_deq_seg,
602 (unsigned long long)deq_state->new_deq_seg->dma,
603 deq_state->new_deq_ptr,
604 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
605 deq_state->new_cycle_state);
606 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
607 deq_state->new_deq_seg,
608 deq_state->new_deq_ptr,
609 (u32) deq_state->new_cycle_state);
610 /* Stop the TD queueing code from ringing the doorbell until
611 * this command completes. The HC won't set the dequeue pointer
612 * if the ring is running, and ringing the doorbell starts the
615 ep->ep_state |= SET_DEQ_PENDING;
618 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
619 struct xhci_virt_ep *ep)
621 ep->ep_state &= ~EP_HALT_PENDING;
622 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
623 * timer is running on another CPU, we don't decrement stop_cmds_pending
624 * (since we didn't successfully stop the watchdog timer).
626 if (del_timer(&ep->stop_cmd_timer))
627 ep->stop_cmds_pending--;
630 /* Must be called with xhci->lock held in interrupt context */
631 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
632 struct xhci_td *cur_td, int status, char *adjective)
636 struct urb_priv *urb_priv;
639 urb_priv = urb->hcpriv;
641 hcd = bus_to_hcd(urb->dev->bus);
643 /* Only giveback urb when this is the last td in urb */
644 if (urb_priv->td_cnt == urb_priv->length) {
645 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
646 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
647 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
648 if (xhci->quirks & XHCI_AMD_PLL_FIX)
649 usb_amd_quirk_pll_enable();
652 usb_hcd_unlink_urb_from_ep(hcd, urb);
654 spin_unlock(&xhci->lock);
655 usb_hcd_giveback_urb(hcd, urb, status);
656 xhci_urb_free_priv(xhci, urb_priv);
657 spin_lock(&xhci->lock);
662 * When we get a command completion for a Stop Endpoint Command, we need to
663 * unlink any cancelled TDs from the ring. There are two ways to do that:
665 * 1. If the HW was in the middle of processing the TD that needs to be
666 * cancelled, then we must move the ring's dequeue pointer past the last TRB
667 * in the TD with a Set Dequeue Pointer Command.
668 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
669 * bit cleared) so that the HW will skip over them.
671 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
672 union xhci_trb *trb, struct xhci_event_cmd *event)
674 unsigned int slot_id;
675 unsigned int ep_index;
676 struct xhci_virt_device *virt_dev;
677 struct xhci_ring *ep_ring;
678 struct xhci_virt_ep *ep;
679 struct list_head *entry;
680 struct xhci_td *cur_td = NULL;
681 struct xhci_td *last_unlinked_td;
683 struct xhci_dequeue_state deq_state;
685 if (unlikely(TRB_TO_SUSPEND_PORT(
686 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
687 slot_id = TRB_TO_SLOT_ID(
688 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
689 virt_dev = xhci->devs[slot_id];
691 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
694 xhci_warn(xhci, "Stop endpoint command "
695 "completion for disabled slot %u\n",
700 memset(&deq_state, 0, sizeof(deq_state));
701 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
702 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
703 ep = &xhci->devs[slot_id]->eps[ep_index];
705 if (list_empty(&ep->cancelled_td_list)) {
706 xhci_stop_watchdog_timer_in_irq(xhci, ep);
707 ep->stopped_td = NULL;
708 ep->stopped_trb = NULL;
709 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
713 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
714 * We have the xHCI lock, so nothing can modify this list until we drop
715 * it. We're also in the event handler, so we can't get re-interrupted
716 * if another Stop Endpoint command completes
718 list_for_each(entry, &ep->cancelled_td_list) {
719 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
720 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
722 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
723 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
725 /* This shouldn't happen unless a driver is mucking
726 * with the stream ID after submission. This will
727 * leave the TD on the hardware ring, and the hardware
728 * will try to execute it, and may access a buffer
729 * that has already been freed. In the best case, the
730 * hardware will execute it, and the event handler will
731 * ignore the completion event for that TD, since it was
732 * removed from the td_list for that endpoint. In
733 * short, don't muck with the stream ID after
736 xhci_warn(xhci, "WARN Cancelled URB %p "
737 "has invalid stream ID %u.\n",
739 cur_td->urb->stream_id);
740 goto remove_finished_td;
743 * If we stopped on the TD we need to cancel, then we have to
744 * move the xHC endpoint ring dequeue pointer past this TD.
746 if (cur_td == ep->stopped_td)
747 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
748 cur_td->urb->stream_id,
751 td_to_noop(xhci, ep_ring, cur_td, false);
754 * The event handler won't see a completion for this TD anymore,
755 * so remove it from the endpoint ring's TD list. Keep it in
756 * the cancelled TD list for URB completion later.
758 list_del_init(&cur_td->td_list);
760 last_unlinked_td = cur_td;
761 xhci_stop_watchdog_timer_in_irq(xhci, ep);
763 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
764 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
765 xhci_queue_new_dequeue_state(xhci,
767 ep->stopped_td->urb->stream_id,
769 xhci_ring_cmd_db(xhci);
771 /* Otherwise ring the doorbell(s) to restart queued transfers */
772 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
774 ep->stopped_td = NULL;
775 ep->stopped_trb = NULL;
778 * Drop the lock and complete the URBs in the cancelled TD list.
779 * New TDs to be cancelled might be added to the end of the list before
780 * we can complete all the URBs for the TDs we already unlinked.
781 * So stop when we've completed the URB for the last TD we unlinked.
784 cur_td = list_entry(ep->cancelled_td_list.next,
785 struct xhci_td, cancelled_td_list);
786 list_del_init(&cur_td->cancelled_td_list);
788 /* Clean up the cancelled URB */
789 /* Doesn't matter what we pass for status, since the core will
790 * just overwrite it (because the URB has been unlinked).
792 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
794 /* Stop processing the cancelled list if the watchdog timer is
797 if (xhci->xhc_state & XHCI_STATE_DYING)
799 } while (cur_td != last_unlinked_td);
801 /* Return to the event handler with xhci->lock re-acquired */
804 /* Watchdog timer function for when a stop endpoint command fails to complete.
805 * In this case, we assume the host controller is broken or dying or dead. The
806 * host may still be completing some other events, so we have to be careful to
807 * let the event ring handler and the URB dequeueing/enqueueing functions know
808 * through xhci->state.
810 * The timer may also fire if the host takes a very long time to respond to the
811 * command, and the stop endpoint command completion handler cannot delete the
812 * timer before the timer function is called. Another endpoint cancellation may
813 * sneak in before the timer function can grab the lock, and that may queue
814 * another stop endpoint command and add the timer back. So we cannot use a
815 * simple flag to say whether there is a pending stop endpoint command for a
816 * particular endpoint.
818 * Instead we use a combination of that flag and a counter for the number of
819 * pending stop endpoint commands. If the timer is the tail end of the last
820 * stop endpoint command, and the endpoint's command is still pending, we assume
823 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
825 struct xhci_hcd *xhci;
826 struct xhci_virt_ep *ep;
827 struct xhci_virt_ep *temp_ep;
828 struct xhci_ring *ring;
829 struct xhci_td *cur_td;
833 ep = (struct xhci_virt_ep *) arg;
836 spin_lock_irqsave(&xhci->lock, flags);
838 ep->stop_cmds_pending--;
839 if (xhci->xhc_state & XHCI_STATE_DYING) {
840 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
841 "xHCI as DYING, exiting.\n");
842 spin_unlock_irqrestore(&xhci->lock, flags);
845 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
846 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
848 spin_unlock_irqrestore(&xhci->lock, flags);
852 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
853 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
854 /* Oops, HC is dead or dying or at least not responding to the stop
857 xhci->xhc_state |= XHCI_STATE_DYING;
858 /* Disable interrupts from the host controller and start halting it */
860 spin_unlock_irqrestore(&xhci->lock, flags);
862 ret = xhci_halt(xhci);
864 spin_lock_irqsave(&xhci->lock, flags);
866 /* This is bad; the host is not responding to commands and it's
867 * not allowing itself to be halted. At least interrupts are
868 * disabled. If we call usb_hc_died(), it will attempt to
869 * disconnect all device drivers under this host. Those
870 * disconnect() methods will wait for all URBs to be unlinked,
871 * so we must complete them.
873 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
874 xhci_warn(xhci, "Completing active URBs anyway.\n");
875 /* We could turn all TDs on the rings to no-ops. This won't
876 * help if the host has cached part of the ring, and is slow if
877 * we want to preserve the cycle bit. Skip it and hope the host
878 * doesn't touch the memory.
881 for (i = 0; i < MAX_HC_SLOTS; i++) {
884 for (j = 0; j < 31; j++) {
885 temp_ep = &xhci->devs[i]->eps[j];
886 ring = temp_ep->ring;
889 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
890 "ep index %u\n", i, j);
891 while (!list_empty(&ring->td_list)) {
892 cur_td = list_first_entry(&ring->td_list,
895 list_del_init(&cur_td->td_list);
896 if (!list_empty(&cur_td->cancelled_td_list))
897 list_del_init(&cur_td->cancelled_td_list);
898 xhci_giveback_urb_in_irq(xhci, cur_td,
899 -ESHUTDOWN, "killed");
901 while (!list_empty(&temp_ep->cancelled_td_list)) {
902 cur_td = list_first_entry(
903 &temp_ep->cancelled_td_list,
906 list_del_init(&cur_td->cancelled_td_list);
907 xhci_giveback_urb_in_irq(xhci, cur_td,
908 -ESHUTDOWN, "killed");
912 spin_unlock_irqrestore(&xhci->lock, flags);
913 xhci_dbg(xhci, "Calling usb_hc_died()\n");
914 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
915 xhci_dbg(xhci, "xHCI host controller is dead.\n");
919 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
920 * we need to clear the set deq pending flag in the endpoint ring state, so that
921 * the TD queueing code can ring the doorbell again. We also need to ring the
922 * endpoint doorbell to restart the ring, but only if there aren't more
923 * cancellations pending.
925 static void handle_set_deq_completion(struct xhci_hcd *xhci,
926 struct xhci_event_cmd *event,
929 unsigned int slot_id;
930 unsigned int ep_index;
931 unsigned int stream_id;
932 struct xhci_ring *ep_ring;
933 struct xhci_virt_device *dev;
934 struct xhci_ep_ctx *ep_ctx;
935 struct xhci_slot_ctx *slot_ctx;
937 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
938 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
939 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
940 dev = xhci->devs[slot_id];
942 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
944 xhci_warn(xhci, "WARN Set TR deq ptr command for "
945 "freed stream ID %u\n",
947 /* XXX: Harmless??? */
948 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
952 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
953 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
955 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
956 unsigned int ep_state;
957 unsigned int slot_state;
959 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
961 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
962 "of stream ID configuration\n");
965 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
966 "to incorrect slot or ep state.\n");
967 ep_state = le32_to_cpu(ep_ctx->ep_info);
968 ep_state &= EP_STATE_MASK;
969 slot_state = le32_to_cpu(slot_ctx->dev_state);
970 slot_state = GET_SLOT_STATE(slot_state);
971 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
972 slot_state, ep_state);
975 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
976 "slot %u was not enabled.\n", slot_id);
979 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
980 "completion code of %u.\n",
981 GET_COMP_CODE(le32_to_cpu(event->status)));
984 /* OK what do we do now? The endpoint state is hosed, and we
985 * should never get to this point if the synchronization between
986 * queueing, and endpoint state are correct. This might happen
987 * if the device gets disconnected after we've finished
988 * cancelling URBs, which might not be an error...
991 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
992 le64_to_cpu(ep_ctx->deq));
993 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
994 dev->eps[ep_index].queued_deq_ptr) ==
995 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
996 /* Update the ring's dequeue segment and dequeue pointer
997 * to reflect the new position.
999 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1000 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1002 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1003 "Ptr command & xHCI internal state.\n");
1004 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1005 dev->eps[ep_index].queued_deq_seg,
1006 dev->eps[ep_index].queued_deq_ptr);
1010 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1011 dev->eps[ep_index].queued_deq_seg = NULL;
1012 dev->eps[ep_index].queued_deq_ptr = NULL;
1013 /* Restart any rings with pending URBs */
1014 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1017 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1018 struct xhci_event_cmd *event,
1019 union xhci_trb *trb)
1022 unsigned int ep_index;
1024 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1025 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1026 /* This command will only fail if the endpoint wasn't halted,
1027 * but we don't care.
1029 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1030 GET_COMP_CODE(le32_to_cpu(event->status)));
1032 /* HW with the reset endpoint quirk needs to have a configure endpoint
1033 * command complete before the endpoint can be used. Queue that here
1034 * because the HW can't handle two commands being queued in a row.
1036 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1037 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1038 xhci_queue_configure_endpoint(xhci,
1039 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1041 xhci_ring_cmd_db(xhci);
1043 /* Clear our internal halted state and restart the ring(s) */
1044 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1045 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1049 /* Check to see if a command in the device's command queue matches this one.
1050 * Signal the completion or free the command, and return 1. Return 0 if the
1051 * completed command isn't at the head of the command list.
1053 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1054 struct xhci_virt_device *virt_dev,
1055 struct xhci_event_cmd *event)
1057 struct xhci_command *command;
1059 if (list_empty(&virt_dev->cmd_list))
1062 command = list_entry(virt_dev->cmd_list.next,
1063 struct xhci_command, cmd_list);
1064 if (xhci->cmd_ring->dequeue != command->command_trb)
1067 command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1068 list_del(&command->cmd_list);
1069 if (command->completion)
1070 complete(command->completion);
1072 xhci_free_command(xhci, command);
1076 static void handle_cmd_completion(struct xhci_hcd *xhci,
1077 struct xhci_event_cmd *event)
1079 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1081 dma_addr_t cmd_dequeue_dma;
1082 struct xhci_input_control_ctx *ctrl_ctx;
1083 struct xhci_virt_device *virt_dev;
1084 unsigned int ep_index;
1085 struct xhci_ring *ep_ring;
1086 unsigned int ep_state;
1088 cmd_dma = le64_to_cpu(event->cmd_trb);
1089 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1090 xhci->cmd_ring->dequeue);
1091 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1092 if (cmd_dequeue_dma == 0) {
1093 xhci->error_bitmask |= 1 << 4;
1096 /* Does the DMA address match our internal dequeue pointer address? */
1097 if (cmd_dma != (u64) cmd_dequeue_dma) {
1098 xhci->error_bitmask |= 1 << 5;
1101 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1102 & TRB_TYPE_BITMASK) {
1103 case TRB_TYPE(TRB_ENABLE_SLOT):
1104 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1105 xhci->slot_id = slot_id;
1108 complete(&xhci->addr_dev);
1110 case TRB_TYPE(TRB_DISABLE_SLOT):
1111 if (xhci->devs[slot_id]) {
1112 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1113 /* Delete default control endpoint resources */
1114 xhci_free_device_endpoint_resources(xhci,
1115 xhci->devs[slot_id], true);
1116 xhci_free_virt_device(xhci, slot_id);
1119 case TRB_TYPE(TRB_CONFIG_EP):
1120 virt_dev = xhci->devs[slot_id];
1121 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1124 * Configure endpoint commands can come from the USB core
1125 * configuration or alt setting changes, or because the HW
1126 * needed an extra configure endpoint command after a reset
1127 * endpoint command or streams were being configured.
1128 * If the command was for a halted endpoint, the xHCI driver
1129 * is not waiting on the configure endpoint command.
1131 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1133 /* Input ctx add_flags are the endpoint index plus one */
1134 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1135 /* A usb_set_interface() call directly after clearing a halted
1136 * condition may race on this quirky hardware. Not worth
1137 * worrying about, since this is prototype hardware. Not sure
1138 * if this will work for streams, but streams support was
1139 * untested on this prototype.
1141 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1142 ep_index != (unsigned int) -1 &&
1143 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1144 le32_to_cpu(ctrl_ctx->drop_flags)) {
1145 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1146 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1147 if (!(ep_state & EP_HALTED))
1148 goto bandwidth_change;
1149 xhci_dbg(xhci, "Completed config ep cmd - "
1150 "last ep index = %d, state = %d\n",
1151 ep_index, ep_state);
1152 /* Clear internal halted state and restart ring(s) */
1153 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1155 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1159 xhci_dbg(xhci, "Completed config ep cmd\n");
1160 xhci->devs[slot_id]->cmd_status =
1161 GET_COMP_CODE(le32_to_cpu(event->status));
1162 complete(&xhci->devs[slot_id]->cmd_completion);
1164 case TRB_TYPE(TRB_EVAL_CONTEXT):
1165 virt_dev = xhci->devs[slot_id];
1166 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1168 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1169 complete(&xhci->devs[slot_id]->cmd_completion);
1171 case TRB_TYPE(TRB_ADDR_DEV):
1172 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1173 complete(&xhci->addr_dev);
1175 case TRB_TYPE(TRB_STOP_RING):
1176 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1178 case TRB_TYPE(TRB_SET_DEQ):
1179 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1181 case TRB_TYPE(TRB_CMD_NOOP):
1183 case TRB_TYPE(TRB_RESET_EP):
1184 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1186 case TRB_TYPE(TRB_RESET_DEV):
1187 xhci_dbg(xhci, "Completed reset device command.\n");
1188 slot_id = TRB_TO_SLOT_ID(
1189 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1190 virt_dev = xhci->devs[slot_id];
1192 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1194 xhci_warn(xhci, "Reset device command completion "
1195 "for disabled slot %u\n", slot_id);
1197 case TRB_TYPE(TRB_NEC_GET_FW):
1198 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1199 xhci->error_bitmask |= 1 << 6;
1202 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1203 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1204 NEC_FW_MINOR(le32_to_cpu(event->status)));
1207 /* Skip over unknown commands on the event ring */
1208 xhci->error_bitmask |= 1 << 6;
1211 inc_deq(xhci, xhci->cmd_ring, false);
1214 static void handle_vendor_event(struct xhci_hcd *xhci,
1215 union xhci_trb *event)
1219 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1220 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1221 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1222 handle_cmd_completion(xhci, &event->event_cmd);
1225 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1226 * port registers -- USB 3.0 and USB 2.0).
1228 * Returns a zero-based port number, which is suitable for indexing into each of
1229 * the split roothubs' port arrays and bus state arrays.
1230 * Add one to it in order to call xhci_find_slot_id_by_port.
1232 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1233 struct xhci_hcd *xhci, u32 port_id)
1236 unsigned int num_similar_speed_ports = 0;
1238 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1239 * and usb2_ports are 0-based indexes. Count the number of similar
1240 * speed ports, up to 1 port before this port.
1242 for (i = 0; i < (port_id - 1); i++) {
1243 u8 port_speed = xhci->port_array[i];
1246 * Skip ports that don't have known speeds, or have duplicate
1247 * Extended Capabilities port speed entries.
1249 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1253 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1254 * 1.1 ports are under the USB 2.0 hub. If the port speed
1255 * matches the device speed, it's a similar speed port.
1257 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1258 num_similar_speed_ports++;
1260 return num_similar_speed_ports;
1263 static void handle_port_status(struct xhci_hcd *xhci,
1264 union xhci_trb *event)
1266 struct usb_hcd *hcd;
1271 unsigned int faked_port_index;
1273 struct xhci_bus_state *bus_state;
1274 __le32 __iomem **port_array;
1275 bool bogus_port_status = false;
1277 /* Port status change events always have a successful completion code */
1278 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1279 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1280 xhci->error_bitmask |= 1 << 8;
1282 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1283 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1285 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1286 if ((port_id <= 0) || (port_id > max_ports)) {
1287 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1288 bogus_port_status = true;
1292 /* Figure out which usb_hcd this port is attached to:
1293 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1295 major_revision = xhci->port_array[port_id - 1];
1296 if (major_revision == 0) {
1297 xhci_warn(xhci, "Event for port %u not in "
1298 "Extended Capabilities, ignoring.\n",
1300 bogus_port_status = true;
1303 if (major_revision == DUPLICATE_ENTRY) {
1304 xhci_warn(xhci, "Event for port %u duplicated in"
1305 "Extended Capabilities, ignoring.\n",
1307 bogus_port_status = true;
1312 * Hardware port IDs reported by a Port Status Change Event include USB
1313 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1314 * resume event, but we first need to translate the hardware port ID
1315 * into the index into the ports on the correct split roothub, and the
1316 * correct bus_state structure.
1318 /* Find the right roothub. */
1319 hcd = xhci_to_hcd(xhci);
1320 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1321 hcd = xhci->shared_hcd;
1322 bus_state = &xhci->bus_state[hcd_index(hcd)];
1323 if (hcd->speed == HCD_USB3)
1324 port_array = xhci->usb3_ports;
1326 port_array = xhci->usb2_ports;
1327 /* Find the faked port hub number */
1328 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1331 temp = xhci_readl(xhci, port_array[faked_port_index]);
1332 if (hcd->state == HC_STATE_SUSPENDED) {
1333 xhci_dbg(xhci, "resume root hub\n");
1334 usb_hcd_resume_root_hub(hcd);
1337 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1338 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1340 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1341 if (!(temp1 & CMD_RUN)) {
1342 xhci_warn(xhci, "xHC is not running.\n");
1346 if (DEV_SUPERSPEED(temp)) {
1347 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1348 xhci_set_link_state(xhci, port_array, faked_port_index,
1350 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1351 faked_port_index + 1);
1353 xhci_dbg(xhci, "slot_id is zero\n");
1356 xhci_ring_device(xhci, slot_id);
1357 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1358 /* Clear PORT_PLC */
1359 xhci_test_and_clear_bit(xhci, port_array,
1360 faked_port_index, PORT_PLC);
1362 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1363 bus_state->resume_done[faked_port_index] = jiffies +
1364 msecs_to_jiffies(20);
1365 mod_timer(&hcd->rh_timer,
1366 bus_state->resume_done[faked_port_index]);
1367 /* Do the rest in GetPortStatus */
1371 if (hcd->speed != HCD_USB3)
1372 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1376 /* Update event ring dequeue pointer before dropping the lock */
1377 inc_deq(xhci, xhci->event_ring, true);
1379 /* Don't make the USB core poll the roothub if we got a bad port status
1380 * change event. Besides, at that point we can't tell which roothub
1381 * (USB 2.0 or USB 3.0) to kick.
1383 if (bogus_port_status)
1386 spin_unlock(&xhci->lock);
1387 /* Pass this up to the core */
1388 usb_hcd_poll_rh_status(hcd);
1389 spin_lock(&xhci->lock);
1393 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1394 * at end_trb, which may be in another segment. If the suspect DMA address is a
1395 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1398 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1399 union xhci_trb *start_trb,
1400 union xhci_trb *end_trb,
1401 dma_addr_t suspect_dma)
1403 dma_addr_t start_dma;
1404 dma_addr_t end_seg_dma;
1405 dma_addr_t end_trb_dma;
1406 struct xhci_segment *cur_seg;
1408 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1409 cur_seg = start_seg;
1414 /* We may get an event for a Link TRB in the middle of a TD */
1415 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1416 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1417 /* If the end TRB isn't in this segment, this is set to 0 */
1418 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1420 if (end_trb_dma > 0) {
1421 /* The end TRB is in this segment, so suspect should be here */
1422 if (start_dma <= end_trb_dma) {
1423 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1426 /* Case for one segment with
1427 * a TD wrapped around to the top
1429 if ((suspect_dma >= start_dma &&
1430 suspect_dma <= end_seg_dma) ||
1431 (suspect_dma >= cur_seg->dma &&
1432 suspect_dma <= end_trb_dma))
1437 /* Might still be somewhere in this segment */
1438 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1441 cur_seg = cur_seg->next;
1442 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1443 } while (cur_seg != start_seg);
1448 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1449 unsigned int slot_id, unsigned int ep_index,
1450 unsigned int stream_id,
1451 struct xhci_td *td, union xhci_trb *event_trb)
1453 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1454 ep->ep_state |= EP_HALTED;
1455 ep->stopped_td = td;
1456 ep->stopped_trb = event_trb;
1457 ep->stopped_stream = stream_id;
1459 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1460 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1462 ep->stopped_td = NULL;
1463 ep->stopped_trb = NULL;
1464 ep->stopped_stream = 0;
1466 xhci_ring_cmd_db(xhci);
1469 /* Check if an error has halted the endpoint ring. The class driver will
1470 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1471 * However, a babble and other errors also halt the endpoint ring, and the class
1472 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1473 * Ring Dequeue Pointer command manually.
1475 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1476 struct xhci_ep_ctx *ep_ctx,
1477 unsigned int trb_comp_code)
1479 /* TRB completion codes that may require a manual halt cleanup */
1480 if (trb_comp_code == COMP_TX_ERR ||
1481 trb_comp_code == COMP_BABBLE ||
1482 trb_comp_code == COMP_SPLIT_ERR)
1483 /* The 0.96 spec says a babbling control endpoint
1484 * is not halted. The 0.96 spec says it is. Some HW
1485 * claims to be 0.95 compliant, but it halts the control
1486 * endpoint anyway. Check if a babble halted the
1489 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1490 cpu_to_le32(EP_STATE_HALTED))
1496 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1498 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1499 /* Vendor defined "informational" completion code,
1500 * treat as not-an-error.
1502 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1504 xhci_dbg(xhci, "Treating code as success.\n");
1511 * Finish the td processing, remove the td from td list;
1512 * Return 1 if the urb can be given back.
1514 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1515 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1516 struct xhci_virt_ep *ep, int *status, bool skip)
1518 struct xhci_virt_device *xdev;
1519 struct xhci_ring *ep_ring;
1520 unsigned int slot_id;
1522 struct urb *urb = NULL;
1523 struct xhci_ep_ctx *ep_ctx;
1525 struct urb_priv *urb_priv;
1528 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1529 xdev = xhci->devs[slot_id];
1530 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1531 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1532 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1533 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1538 if (trb_comp_code == COMP_STOP_INVAL ||
1539 trb_comp_code == COMP_STOP) {
1540 /* The Endpoint Stop Command completion will take care of any
1541 * stopped TDs. A stopped TD may be restarted, so don't update
1542 * the ring dequeue pointer or take this TD off any lists yet.
1544 ep->stopped_td = td;
1545 ep->stopped_trb = event_trb;
1548 if (trb_comp_code == COMP_STALL) {
1549 /* The transfer is completed from the driver's
1550 * perspective, but we need to issue a set dequeue
1551 * command for this stalled endpoint to move the dequeue
1552 * pointer past the TD. We can't do that here because
1553 * the halt condition must be cleared first. Let the
1554 * USB class driver clear the stall later.
1556 ep->stopped_td = td;
1557 ep->stopped_trb = event_trb;
1558 ep->stopped_stream = ep_ring->stream_id;
1559 } else if (xhci_requires_manual_halt_cleanup(xhci,
1560 ep_ctx, trb_comp_code)) {
1561 /* Other types of errors halt the endpoint, but the
1562 * class driver doesn't call usb_reset_endpoint() unless
1563 * the error is -EPIPE. Clear the halted status in the
1564 * xHCI hardware manually.
1566 xhci_cleanup_halted_endpoint(xhci,
1567 slot_id, ep_index, ep_ring->stream_id,
1570 /* Update ring dequeue pointer */
1571 while (ep_ring->dequeue != td->last_trb)
1572 inc_deq(xhci, ep_ring, false);
1573 inc_deq(xhci, ep_ring, false);
1577 /* Clean up the endpoint's TD list */
1579 urb_priv = urb->hcpriv;
1581 /* Do one last check of the actual transfer length.
1582 * If the host controller said we transferred more data than
1583 * the buffer length, urb->actual_length will be a very big
1584 * number (since it's unsigned). Play it safe and say we didn't
1585 * transfer anything.
1587 if (urb->actual_length > urb->transfer_buffer_length) {
1588 xhci_warn(xhci, "URB transfer length is wrong, "
1589 "xHC issue? req. len = %u, "
1591 urb->transfer_buffer_length,
1592 urb->actual_length);
1593 urb->actual_length = 0;
1594 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1595 *status = -EREMOTEIO;
1599 list_del_init(&td->td_list);
1600 /* Was this TD slated to be cancelled but completed anyway? */
1601 if (!list_empty(&td->cancelled_td_list))
1602 list_del_init(&td->cancelled_td_list);
1605 /* Giveback the urb when all the tds are completed */
1606 if (urb_priv->td_cnt == urb_priv->length) {
1608 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1609 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1610 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1612 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1613 usb_amd_quirk_pll_enable();
1623 * Process control tds, update urb status and actual_length.
1625 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1626 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1627 struct xhci_virt_ep *ep, int *status)
1629 struct xhci_virt_device *xdev;
1630 struct xhci_ring *ep_ring;
1631 unsigned int slot_id;
1633 struct xhci_ep_ctx *ep_ctx;
1636 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1637 xdev = xhci->devs[slot_id];
1638 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1639 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1640 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1641 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1643 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1644 switch (trb_comp_code) {
1646 if (event_trb == ep_ring->dequeue) {
1647 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1648 "without IOC set??\n");
1649 *status = -ESHUTDOWN;
1650 } else if (event_trb != td->last_trb) {
1651 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1652 "without IOC set??\n");
1653 *status = -ESHUTDOWN;
1659 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1660 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1661 *status = -EREMOTEIO;
1665 case COMP_STOP_INVAL:
1667 return finish_td(xhci, td, event_trb, event, ep, status, false);
1669 if (!xhci_requires_manual_halt_cleanup(xhci,
1670 ep_ctx, trb_comp_code))
1672 xhci_dbg(xhci, "TRB error code %u, "
1673 "halted endpoint index = %u\n",
1674 trb_comp_code, ep_index);
1675 /* else fall through */
1677 /* Did we transfer part of the data (middle) phase? */
1678 if (event_trb != ep_ring->dequeue &&
1679 event_trb != td->last_trb)
1680 td->urb->actual_length =
1681 td->urb->transfer_buffer_length
1682 - TRB_LEN(le32_to_cpu(event->transfer_len));
1684 td->urb->actual_length = 0;
1686 xhci_cleanup_halted_endpoint(xhci,
1687 slot_id, ep_index, 0, td, event_trb);
1688 return finish_td(xhci, td, event_trb, event, ep, status, true);
1691 * Did we transfer any data, despite the errors that might have
1692 * happened? I.e. did we get past the setup stage?
1694 if (event_trb != ep_ring->dequeue) {
1695 /* The event was for the status stage */
1696 if (event_trb == td->last_trb) {
1697 if (td->urb->actual_length != 0) {
1698 /* Don't overwrite a previously set error code
1700 if ((*status == -EINPROGRESS || *status == 0) &&
1701 (td->urb->transfer_flags
1702 & URB_SHORT_NOT_OK))
1703 /* Did we already see a short data
1705 *status = -EREMOTEIO;
1707 td->urb->actual_length =
1708 td->urb->transfer_buffer_length;
1711 /* Maybe the event was for the data stage? */
1712 td->urb->actual_length =
1713 td->urb->transfer_buffer_length -
1714 TRB_LEN(le32_to_cpu(event->transfer_len));
1715 xhci_dbg(xhci, "Waiting for status "
1721 return finish_td(xhci, td, event_trb, event, ep, status, false);
1725 * Process isochronous tds, update urb packet status and actual_length.
1727 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1728 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1729 struct xhci_virt_ep *ep, int *status)
1731 struct xhci_ring *ep_ring;
1732 struct urb_priv *urb_priv;
1735 union xhci_trb *cur_trb;
1736 struct xhci_segment *cur_seg;
1737 struct usb_iso_packet_descriptor *frame;
1739 bool skip_td = false;
1741 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1742 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1743 urb_priv = td->urb->hcpriv;
1744 idx = urb_priv->td_cnt;
1745 frame = &td->urb->iso_frame_desc[idx];
1747 /* handle completion code */
1748 switch (trb_comp_code) {
1750 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
1754 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
1755 trb_comp_code = COMP_SHORT_TX;
1757 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1761 frame->status = -ECOMM;
1764 case COMP_BUFF_OVER:
1766 frame->status = -EOVERFLOW;
1772 frame->status = -EPROTO;
1776 case COMP_STOP_INVAL:
1783 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1784 frame->actual_length = frame->length;
1785 td->urb->actual_length += frame->length;
1787 for (cur_trb = ep_ring->dequeue,
1788 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1789 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1790 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1791 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1792 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1794 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1795 TRB_LEN(le32_to_cpu(event->transfer_len));
1797 if (trb_comp_code != COMP_STOP_INVAL) {
1798 frame->actual_length = len;
1799 td->urb->actual_length += len;
1803 return finish_td(xhci, td, event_trb, event, ep, status, false);
1806 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1807 struct xhci_transfer_event *event,
1808 struct xhci_virt_ep *ep, int *status)
1810 struct xhci_ring *ep_ring;
1811 struct urb_priv *urb_priv;
1812 struct usb_iso_packet_descriptor *frame;
1815 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1816 urb_priv = td->urb->hcpriv;
1817 idx = urb_priv->td_cnt;
1818 frame = &td->urb->iso_frame_desc[idx];
1820 /* The transfer is partly done. */
1821 frame->status = -EXDEV;
1823 /* calc actual length */
1824 frame->actual_length = 0;
1826 /* Update ring dequeue pointer */
1827 while (ep_ring->dequeue != td->last_trb)
1828 inc_deq(xhci, ep_ring, false);
1829 inc_deq(xhci, ep_ring, false);
1831 return finish_td(xhci, td, NULL, event, ep, status, true);
1835 * Process bulk and interrupt tds, update urb status and actual_length.
1837 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1838 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1839 struct xhci_virt_ep *ep, int *status)
1841 struct xhci_ring *ep_ring;
1842 union xhci_trb *cur_trb;
1843 struct xhci_segment *cur_seg;
1846 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1847 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1849 switch (trb_comp_code) {
1851 /* Double check that the HW transferred everything. */
1852 if (event_trb != td->last_trb ||
1853 TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1854 xhci_warn(xhci, "WARN Successful completion "
1856 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1857 *status = -EREMOTEIO;
1860 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
1861 trb_comp_code = COMP_SHORT_TX;
1867 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1868 *status = -EREMOTEIO;
1873 /* Others already handled above */
1876 if (trb_comp_code == COMP_SHORT_TX)
1877 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1878 "%d bytes untransferred\n",
1879 td->urb->ep->desc.bEndpointAddress,
1880 td->urb->transfer_buffer_length,
1881 TRB_LEN(le32_to_cpu(event->transfer_len)));
1882 /* Fast path - was this the last TRB in the TD for this URB? */
1883 if (event_trb == td->last_trb) {
1884 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1885 td->urb->actual_length =
1886 td->urb->transfer_buffer_length -
1887 TRB_LEN(le32_to_cpu(event->transfer_len));
1888 if (td->urb->transfer_buffer_length <
1889 td->urb->actual_length) {
1890 xhci_warn(xhci, "HC gave bad length "
1891 "of %d bytes left\n",
1892 TRB_LEN(le32_to_cpu(event->transfer_len)));
1893 td->urb->actual_length = 0;
1894 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1895 *status = -EREMOTEIO;
1899 /* Don't overwrite a previously set error code */
1900 if (*status == -EINPROGRESS) {
1901 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1902 *status = -EREMOTEIO;
1907 td->urb->actual_length =
1908 td->urb->transfer_buffer_length;
1909 /* Ignore a short packet completion if the
1910 * untransferred length was zero.
1912 if (*status == -EREMOTEIO)
1916 /* Slow path - walk the list, starting from the dequeue
1917 * pointer, to get the actual length transferred.
1919 td->urb->actual_length = 0;
1920 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1921 cur_trb != event_trb;
1922 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1923 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1924 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1925 td->urb->actual_length +=
1926 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1928 /* If the ring didn't stop on a Link or No-op TRB, add
1929 * in the actual bytes transferred from the Normal TRB
1931 if (trb_comp_code != COMP_STOP_INVAL)
1932 td->urb->actual_length +=
1933 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1934 TRB_LEN(le32_to_cpu(event->transfer_len));
1937 return finish_td(xhci, td, event_trb, event, ep, status, false);
1941 * If this function returns an error condition, it means it got a Transfer
1942 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1943 * At this point, the host controller is probably hosed and should be reset.
1945 static int handle_tx_event(struct xhci_hcd *xhci,
1946 struct xhci_transfer_event *event)
1948 struct xhci_virt_device *xdev;
1949 struct xhci_virt_ep *ep;
1950 struct xhci_ring *ep_ring;
1951 unsigned int slot_id;
1953 struct xhci_td *td = NULL;
1954 dma_addr_t event_dma;
1955 struct xhci_segment *event_seg;
1956 union xhci_trb *event_trb;
1957 struct urb *urb = NULL;
1958 int status = -EINPROGRESS;
1959 struct urb_priv *urb_priv;
1960 struct xhci_ep_ctx *ep_ctx;
1961 struct list_head *tmp;
1966 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1967 xdev = xhci->devs[slot_id];
1969 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1973 /* Endpoint ID is 1 based, our index is zero based */
1974 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1975 ep = &xdev->eps[ep_index];
1976 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1977 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1979 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1980 EP_STATE_DISABLED) {
1981 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1982 "or incorrect stream ring\n");
1986 /* Count current td numbers if ep->skip is set */
1988 list_for_each(tmp, &ep_ring->td_list)
1992 event_dma = le64_to_cpu(event->buffer);
1993 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1994 /* Look for common error cases */
1995 switch (trb_comp_code) {
1996 /* Skip codes that require special handling depending on
2000 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2002 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2003 trb_comp_code = COMP_SHORT_TX;
2005 xhci_warn(xhci, "WARN Successful completion on short TX: "
2006 "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2010 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2012 case COMP_STOP_INVAL:
2013 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2016 xhci_warn(xhci, "WARN: Stalled endpoint\n");
2017 ep->ep_state |= EP_HALTED;
2021 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2024 case COMP_SPLIT_ERR:
2026 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
2030 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2031 status = -EOVERFLOW;
2034 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2038 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2040 case COMP_BUFF_OVER:
2041 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2045 * When the Isoch ring is empty, the xHC will generate
2046 * a Ring Overrun Event for IN Isoch endpoint or Ring
2047 * Underrun Event for OUT Isoch endpoint.
2049 xhci_dbg(xhci, "underrun event on endpoint\n");
2050 if (!list_empty(&ep_ring->td_list))
2051 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2052 "still with TDs queued?\n",
2053 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2057 xhci_dbg(xhci, "overrun event on endpoint\n");
2058 if (!list_empty(&ep_ring->td_list))
2059 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2060 "still with TDs queued?\n",
2061 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2065 xhci_warn(xhci, "WARN: detect an incompatible device");
2068 case COMP_MISSED_INT:
2070 * When encounter missed service error, one or more isoc tds
2071 * may be missed by xHC.
2072 * Set skip flag of the ep_ring; Complete the missed tds as
2073 * short transfer when process the ep_ring next time.
2076 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2079 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2083 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2089 /* This TRB should be in the TD at the head of this ring's
2092 if (list_empty(&ep_ring->td_list)) {
2093 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2094 "with no TDs queued?\n",
2095 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2097 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2098 (le32_to_cpu(event->flags) &
2099 TRB_TYPE_BITMASK)>>10);
2100 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2103 xhci_dbg(xhci, "td_list is empty while skip "
2104 "flag set. Clear skip flag.\n");
2110 /* We've skipped all the TDs on the ep ring when ep->skip set */
2111 if (ep->skip && td_num == 0) {
2113 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2114 "Clear skip flag.\n");
2119 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2123 /* Is this a TRB in the currently executing TD? */
2124 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2125 td->last_trb, event_dma);
2128 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2129 * is not in the current TD pointed by ep_ring->dequeue because
2130 * that the hardware dequeue pointer still at the previous TRB
2131 * of the current TD. The previous TRB maybe a Link TD or the
2132 * last TRB of the previous TD. The command completion handle
2133 * will take care the rest.
2135 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2142 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2143 /* Some host controllers give a spurious
2144 * successful event after a short transfer.
2147 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2148 ep_ring->last_td_was_short) {
2149 ep_ring->last_td_was_short = false;
2153 /* HC is busted, give up! */
2155 "ERROR Transfer event TRB DMA ptr not "
2156 "part of current TD\n");
2160 ret = skip_isoc_td(xhci, td, event, ep, &status);
2163 if (trb_comp_code == COMP_SHORT_TX)
2164 ep_ring->last_td_was_short = true;
2166 ep_ring->last_td_was_short = false;
2169 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2173 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2174 sizeof(*event_trb)];
2176 * No-op TRB should not trigger interrupts.
2177 * If event_trb is a no-op TRB, it means the
2178 * corresponding TD has been cancelled. Just ignore
2181 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2183 "event_trb is a no-op TRB. Skip it\n");
2187 /* Now update the urb's actual_length and give back to
2190 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2191 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2193 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2194 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2197 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2202 * Do not update event ring dequeue pointer if ep->skip is set.
2203 * Will roll back to continue process missed tds.
2205 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2206 inc_deq(xhci, xhci->event_ring, true);
2211 urb_priv = urb->hcpriv;
2212 /* Leave the TD around for the reset endpoint function
2213 * to use(but only if it's not a control endpoint,
2214 * since we already queued the Set TR dequeue pointer
2215 * command for stalled control endpoints).
2217 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2218 (trb_comp_code != COMP_STALL &&
2219 trb_comp_code != COMP_BABBLE))
2220 xhci_urb_free_priv(xhci, urb_priv);
2222 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2223 if ((urb->actual_length != urb->transfer_buffer_length &&
2224 (urb->transfer_flags &
2225 URB_SHORT_NOT_OK)) ||
2227 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2228 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2229 "expected = %x, status = %d\n",
2230 urb, urb->actual_length,
2231 urb->transfer_buffer_length,
2233 spin_unlock(&xhci->lock);
2234 /* EHCI, UHCI, and OHCI always unconditionally set the
2235 * urb->status of an isochronous endpoint to 0.
2237 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2239 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2240 spin_lock(&xhci->lock);
2244 * If ep->skip is set, it means there are missed tds on the
2245 * endpoint ring need to take care of.
2246 * Process them as short transfer until reach the td pointed by
2249 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2255 * This function handles all OS-owned events on the event ring. It may drop
2256 * xhci->lock between event processing (e.g. to pass up port status changes).
2257 * Returns >0 for "possibly more events to process" (caller should call again),
2258 * otherwise 0 if done. In future, <0 returns should indicate error code.
2260 static int xhci_handle_event(struct xhci_hcd *xhci)
2262 union xhci_trb *event;
2263 int update_ptrs = 1;
2266 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2267 xhci->error_bitmask |= 1 << 1;
2271 event = xhci->event_ring->dequeue;
2272 /* Does the HC or OS own the TRB? */
2273 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2274 xhci->event_ring->cycle_state) {
2275 xhci->error_bitmask |= 1 << 2;
2280 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2281 * speculative reads of the event's flags/data below.
2284 /* FIXME: Handle more event types. */
2285 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2286 case TRB_TYPE(TRB_COMPLETION):
2287 handle_cmd_completion(xhci, &event->event_cmd);
2289 case TRB_TYPE(TRB_PORT_STATUS):
2290 handle_port_status(xhci, event);
2293 case TRB_TYPE(TRB_TRANSFER):
2294 ret = handle_tx_event(xhci, &event->trans_event);
2296 xhci->error_bitmask |= 1 << 9;
2301 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2303 handle_vendor_event(xhci, event);
2305 xhci->error_bitmask |= 1 << 3;
2307 /* Any of the above functions may drop and re-acquire the lock, so check
2308 * to make sure a watchdog timer didn't mark the host as non-responsive.
2310 if (xhci->xhc_state & XHCI_STATE_DYING) {
2311 xhci_dbg(xhci, "xHCI host dying, returning from "
2312 "event handler.\n");
2317 /* Update SW event ring dequeue pointer */
2318 inc_deq(xhci, xhci->event_ring, true);
2320 /* Are there more items on the event ring? Caller will call us again to
2327 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2328 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2329 * indicators of an event TRB error, but we check the status *first* to be safe.
2331 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2333 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2335 union xhci_trb *trb;
2337 union xhci_trb *event_ring_deq;
2340 spin_lock(&xhci->lock);
2341 trb = xhci->event_ring->dequeue;
2342 /* Check if the xHC generated the interrupt, or the irq is shared */
2343 status = xhci_readl(xhci, &xhci->op_regs->status);
2344 if (status == 0xffffffff)
2347 if (!(status & STS_EINT)) {
2348 spin_unlock(&xhci->lock);
2351 if (status & STS_FATAL) {
2352 xhci_warn(xhci, "WARNING: Host System Error\n");
2355 spin_unlock(&xhci->lock);
2360 * Clear the op reg interrupt status first,
2361 * so we can receive interrupts from other MSI-X interrupters.
2362 * Write 1 to clear the interrupt status.
2365 xhci_writel(xhci, status, &xhci->op_regs->status);
2366 /* FIXME when MSI-X is supported and there are multiple vectors */
2367 /* Clear the MSI-X event interrupt status */
2369 if (hcd->irq != -1) {
2371 /* Acknowledge the PCI interrupt */
2372 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2373 irq_pending |= IMAN_IP;
2374 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2377 if (xhci->xhc_state & XHCI_STATE_DYING) {
2378 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2379 "Shouldn't IRQs be disabled?\n");
2380 /* Clear the event handler busy flag (RW1C);
2381 * the event ring should be empty.
2383 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2384 xhci_write_64(xhci, temp_64 | ERST_EHB,
2385 &xhci->ir_set->erst_dequeue);
2386 spin_unlock(&xhci->lock);
2391 event_ring_deq = xhci->event_ring->dequeue;
2392 /* FIXME this should be a delayed service routine
2393 * that clears the EHB.
2395 while (xhci_handle_event(xhci) > 0) {}
2397 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2398 /* If necessary, update the HW's version of the event ring deq ptr. */
2399 if (event_ring_deq != xhci->event_ring->dequeue) {
2400 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2401 xhci->event_ring->dequeue);
2403 xhci_warn(xhci, "WARN something wrong with SW event "
2404 "ring dequeue ptr.\n");
2405 /* Update HC event ring dequeue pointer */
2406 temp_64 &= ERST_PTR_MASK;
2407 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2410 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2411 temp_64 |= ERST_EHB;
2412 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2414 spin_unlock(&xhci->lock);
2419 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2422 struct xhci_hcd *xhci;
2424 xhci = hcd_to_xhci(hcd);
2425 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2426 if (xhci->shared_hcd)
2427 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2429 ret = xhci_irq(hcd);
2434 /**** Endpoint Ring Operations ****/
2437 * Generic function for queueing a TRB on a ring.
2438 * The caller must have checked to make sure there's room on the ring.
2440 * @more_trbs_coming: Will you enqueue more TRBs before calling
2441 * prepare_transfer()?
2443 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2444 bool consumer, bool more_trbs_coming, bool isoc,
2445 u32 field1, u32 field2, u32 field3, u32 field4)
2447 struct xhci_generic_trb *trb;
2449 trb = &ring->enqueue->generic;
2450 trb->field[0] = cpu_to_le32(field1);
2451 trb->field[1] = cpu_to_le32(field2);
2452 trb->field[2] = cpu_to_le32(field3);
2453 trb->field[3] = cpu_to_le32(field4);
2454 inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2458 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2459 * FIXME allocate segments if the ring is full.
2461 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2462 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2464 /* Make sure the endpoint has been added to xHC schedule */
2466 case EP_STATE_DISABLED:
2468 * USB core changed config/interfaces without notifying us,
2469 * or hardware is reporting the wrong state.
2471 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2473 case EP_STATE_ERROR:
2474 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2475 /* FIXME event handling code for error needs to clear it */
2476 /* XXX not sure if this should be -ENOENT or not */
2478 case EP_STATE_HALTED:
2479 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2480 case EP_STATE_STOPPED:
2481 case EP_STATE_RUNNING:
2484 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2486 * FIXME issue Configure Endpoint command to try to get the HC
2487 * back into a known state.
2491 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2492 /* FIXME allocate more room */
2493 xhci_err(xhci, "ERROR no room on ep ring\n");
2497 if (enqueue_is_link_trb(ep_ring)) {
2498 struct xhci_ring *ring = ep_ring;
2499 union xhci_trb *next;
2501 next = ring->enqueue;
2503 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2504 /* If we're not dealing with 0.95 hardware or isoc rings
2505 * on AMD 0.96 host, clear the chain bit.
2507 if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2508 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2509 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2511 next->link.control |= cpu_to_le32(TRB_CHAIN);
2514 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2516 /* Toggle the cycle bit after the last ring segment. */
2517 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2518 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2519 if (!in_interrupt()) {
2520 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2521 "state for ring %p = %i\n",
2522 ring, (unsigned int)ring->cycle_state);
2525 ring->enq_seg = ring->enq_seg->next;
2526 ring->enqueue = ring->enq_seg->trbs;
2527 next = ring->enqueue;
2534 static int prepare_transfer(struct xhci_hcd *xhci,
2535 struct xhci_virt_device *xdev,
2536 unsigned int ep_index,
2537 unsigned int stream_id,
2538 unsigned int num_trbs,
2540 unsigned int td_index,
2545 struct urb_priv *urb_priv;
2547 struct xhci_ring *ep_ring;
2548 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2550 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2552 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2557 ret = prepare_ring(xhci, ep_ring,
2558 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2559 num_trbs, isoc, mem_flags);
2563 urb_priv = urb->hcpriv;
2564 td = urb_priv->td[td_index];
2566 INIT_LIST_HEAD(&td->td_list);
2567 INIT_LIST_HEAD(&td->cancelled_td_list);
2569 if (td_index == 0) {
2570 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2576 /* Add this TD to the tail of the endpoint ring's TD list */
2577 list_add_tail(&td->td_list, &ep_ring->td_list);
2578 td->start_seg = ep_ring->enq_seg;
2579 td->first_trb = ep_ring->enqueue;
2581 urb_priv->td[td_index] = td;
2586 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2588 int num_sgs, num_trbs, running_total, temp, i;
2589 struct scatterlist *sg;
2592 num_sgs = urb->num_mapped_sgs;
2593 temp = urb->transfer_buffer_length;
2595 xhci_dbg(xhci, "count sg list trbs: \n");
2597 for_each_sg(urb->sg, sg, num_sgs, i) {
2598 unsigned int previous_total_trbs = num_trbs;
2599 unsigned int len = sg_dma_len(sg);
2601 /* Scatter gather list entries may cross 64KB boundaries */
2602 running_total = TRB_MAX_BUFF_SIZE -
2603 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2604 running_total &= TRB_MAX_BUFF_SIZE - 1;
2605 if (running_total != 0)
2608 /* How many more 64KB chunks to transfer, how many more TRBs? */
2609 while (running_total < sg_dma_len(sg) && running_total < temp) {
2611 running_total += TRB_MAX_BUFF_SIZE;
2613 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2614 i, (unsigned long long)sg_dma_address(sg),
2615 len, len, num_trbs - previous_total_trbs);
2617 len = min_t(int, len, temp);
2622 xhci_dbg(xhci, "\n");
2623 if (!in_interrupt())
2624 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2626 urb->ep->desc.bEndpointAddress,
2627 urb->transfer_buffer_length,
2632 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2635 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2636 "TRBs, %d left\n", __func__,
2637 urb->ep->desc.bEndpointAddress, num_trbs);
2638 if (running_total != urb->transfer_buffer_length)
2639 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2640 "queued %#x (%d), asked for %#x (%d)\n",
2642 urb->ep->desc.bEndpointAddress,
2643 running_total, running_total,
2644 urb->transfer_buffer_length,
2645 urb->transfer_buffer_length);
2648 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2649 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2650 struct xhci_generic_trb *start_trb)
2653 * Pass all the TRBs to the hardware at once and make sure this write
2658 start_trb->field[3] |= cpu_to_le32(start_cycle);
2660 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2661 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2665 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2666 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2667 * (comprised of sg list entries) can take several service intervals to
2670 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2671 struct urb *urb, int slot_id, unsigned int ep_index)
2673 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2674 xhci->devs[slot_id]->out_ctx, ep_index);
2678 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2679 ep_interval = urb->interval;
2680 /* Convert to microframes */
2681 if (urb->dev->speed == USB_SPEED_LOW ||
2682 urb->dev->speed == USB_SPEED_FULL)
2684 /* FIXME change this to a warning and a suggestion to use the new API
2685 * to set the polling interval (once the API is added).
2687 if (xhci_interval != ep_interval) {
2688 if (printk_ratelimit())
2689 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2690 " (%d microframe%s) than xHCI "
2691 "(%d microframe%s)\n",
2693 ep_interval == 1 ? "" : "s",
2695 xhci_interval == 1 ? "" : "s");
2696 urb->interval = xhci_interval;
2697 /* Convert back to frames for LS/FS devices */
2698 if (urb->dev->speed == USB_SPEED_LOW ||
2699 urb->dev->speed == USB_SPEED_FULL)
2702 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2706 * The TD size is the number of bytes remaining in the TD (including this TRB),
2707 * right shifted by 10.
2708 * It must fit in bits 21:17, so it can't be bigger than 31.
2710 static u32 xhci_td_remainder(unsigned int remainder)
2712 u32 max = (1 << (21 - 17 + 1)) - 1;
2714 if ((remainder >> 10) >= max)
2717 return (remainder >> 10) << 17;
2721 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2722 * the TD (*not* including this TRB).
2724 * Total TD packet count = total_packet_count =
2725 * roundup(TD size in bytes / wMaxPacketSize)
2727 * Packets transferred up to and including this TRB = packets_transferred =
2728 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2730 * TD size = total_packet_count - packets_transferred
2732 * It must fit in bits 21:17, so it can't be bigger than 31.
2735 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2736 unsigned int total_packet_count, struct urb *urb)
2738 int packets_transferred;
2740 /* One TRB with a zero-length data packet. */
2741 if (running_total == 0 && trb_buff_len == 0)
2744 /* All the TRB queueing functions don't count the current TRB in
2747 packets_transferred = (running_total + trb_buff_len) /
2748 usb_endpoint_maxp(&urb->ep->desc);
2750 return xhci_td_remainder(total_packet_count - packets_transferred);
2753 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2754 struct urb *urb, int slot_id, unsigned int ep_index)
2756 struct xhci_ring *ep_ring;
2757 unsigned int num_trbs;
2758 struct urb_priv *urb_priv;
2760 struct scatterlist *sg;
2762 int trb_buff_len, this_sg_len, running_total;
2763 unsigned int total_packet_count;
2766 bool more_trbs_coming;
2768 struct xhci_generic_trb *start_trb;
2771 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2775 num_trbs = count_sg_trbs_needed(xhci, urb);
2776 num_sgs = urb->num_mapped_sgs;
2777 total_packet_count = roundup(urb->transfer_buffer_length,
2778 usb_endpoint_maxp(&urb->ep->desc));
2780 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2781 ep_index, urb->stream_id,
2782 num_trbs, urb, 0, false, mem_flags);
2783 if (trb_buff_len < 0)
2784 return trb_buff_len;
2786 urb_priv = urb->hcpriv;
2787 td = urb_priv->td[0];
2790 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2791 * until we've finished creating all the other TRBs. The ring's cycle
2792 * state may change as we enqueue the other TRBs, so save it too.
2794 start_trb = &ep_ring->enqueue->generic;
2795 start_cycle = ep_ring->cycle_state;
2799 * How much data is in the first TRB?
2801 * There are three forces at work for TRB buffer pointers and lengths:
2802 * 1. We don't want to walk off the end of this sg-list entry buffer.
2803 * 2. The transfer length that the driver requested may be smaller than
2804 * the amount of memory allocated for this scatter-gather list.
2805 * 3. TRBs buffers can't cross 64KB boundaries.
2808 addr = (u64) sg_dma_address(sg);
2809 this_sg_len = sg_dma_len(sg);
2810 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2811 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2812 if (trb_buff_len > urb->transfer_buffer_length)
2813 trb_buff_len = urb->transfer_buffer_length;
2814 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2818 /* Queue the first TRB, even if it's zero-length */
2821 u32 length_field = 0;
2824 /* Don't change the cycle bit of the first TRB until later */
2827 if (start_cycle == 0)
2830 field |= ep_ring->cycle_state;
2832 /* Chain all the TRBs together; clear the chain bit in the last
2833 * TRB to indicate it's the last TRB in the chain.
2838 /* FIXME - add check for ZERO_PACKET flag before this */
2839 td->last_trb = ep_ring->enqueue;
2843 /* Only set interrupt on short packet for IN endpoints */
2844 if (usb_urb_dir_in(urb))
2847 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2848 "64KB boundary at %#x, end dma = %#x\n",
2849 (unsigned int) addr, trb_buff_len, trb_buff_len,
2850 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2851 (unsigned int) addr + trb_buff_len);
2852 if (TRB_MAX_BUFF_SIZE -
2853 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2854 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2855 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2856 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2857 (unsigned int) addr + trb_buff_len);
2860 /* Set the TRB length, TD size, and interrupter fields. */
2861 if (xhci->hci_version < 0x100) {
2862 remainder = xhci_td_remainder(
2863 urb->transfer_buffer_length -
2866 remainder = xhci_v1_0_td_remainder(running_total,
2867 trb_buff_len, total_packet_count, urb);
2869 length_field = TRB_LEN(trb_buff_len) |
2874 more_trbs_coming = true;
2876 more_trbs_coming = false;
2877 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2878 lower_32_bits(addr),
2879 upper_32_bits(addr),
2881 field | TRB_TYPE(TRB_NORMAL));
2883 running_total += trb_buff_len;
2885 /* Calculate length for next transfer --
2886 * Are we done queueing all the TRBs for this sg entry?
2888 this_sg_len -= trb_buff_len;
2889 if (this_sg_len == 0) {
2894 addr = (u64) sg_dma_address(sg);
2895 this_sg_len = sg_dma_len(sg);
2897 addr += trb_buff_len;
2900 trb_buff_len = TRB_MAX_BUFF_SIZE -
2901 (addr & (TRB_MAX_BUFF_SIZE - 1));
2902 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2903 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2905 urb->transfer_buffer_length - running_total;
2906 } while (running_total < urb->transfer_buffer_length);
2908 check_trb_math(urb, num_trbs, running_total);
2909 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2910 start_cycle, start_trb);
2914 /* This is very similar to what ehci-q.c qtd_fill() does */
2915 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2916 struct urb *urb, int slot_id, unsigned int ep_index)
2918 struct xhci_ring *ep_ring;
2919 struct urb_priv *urb_priv;
2922 struct xhci_generic_trb *start_trb;
2924 bool more_trbs_coming;
2926 u32 field, length_field;
2928 int running_total, trb_buff_len, ret;
2929 unsigned int total_packet_count;
2933 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2935 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2940 /* How much data is (potentially) left before the 64KB boundary? */
2941 running_total = TRB_MAX_BUFF_SIZE -
2942 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2943 running_total &= TRB_MAX_BUFF_SIZE - 1;
2945 /* If there's some data on this 64KB chunk, or we have to send a
2946 * zero-length transfer, we need at least one TRB
2948 if (running_total != 0 || urb->transfer_buffer_length == 0)
2950 /* How many more 64KB chunks to transfer, how many more TRBs? */
2951 while (running_total < urb->transfer_buffer_length) {
2953 running_total += TRB_MAX_BUFF_SIZE;
2955 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2957 if (!in_interrupt())
2958 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2959 "addr = %#llx, num_trbs = %d\n",
2960 urb->ep->desc.bEndpointAddress,
2961 urb->transfer_buffer_length,
2962 urb->transfer_buffer_length,
2963 (unsigned long long)urb->transfer_dma,
2966 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2967 ep_index, urb->stream_id,
2968 num_trbs, urb, 0, false, mem_flags);
2972 urb_priv = urb->hcpriv;
2973 td = urb_priv->td[0];
2976 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2977 * until we've finished creating all the other TRBs. The ring's cycle
2978 * state may change as we enqueue the other TRBs, so save it too.
2980 start_trb = &ep_ring->enqueue->generic;
2981 start_cycle = ep_ring->cycle_state;
2984 total_packet_count = roundup(urb->transfer_buffer_length,
2985 usb_endpoint_maxp(&urb->ep->desc));
2986 /* How much data is in the first TRB? */
2987 addr = (u64) urb->transfer_dma;
2988 trb_buff_len = TRB_MAX_BUFF_SIZE -
2989 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2990 if (trb_buff_len > urb->transfer_buffer_length)
2991 trb_buff_len = urb->transfer_buffer_length;
2995 /* Queue the first TRB, even if it's zero-length */
3000 /* Don't change the cycle bit of the first TRB until later */
3003 if (start_cycle == 0)
3006 field |= ep_ring->cycle_state;
3008 /* Chain all the TRBs together; clear the chain bit in the last
3009 * TRB to indicate it's the last TRB in the chain.
3014 /* FIXME - add check for ZERO_PACKET flag before this */
3015 td->last_trb = ep_ring->enqueue;
3019 /* Only set interrupt on short packet for IN endpoints */
3020 if (usb_urb_dir_in(urb))
3023 /* Set the TRB length, TD size, and interrupter fields. */
3024 if (xhci->hci_version < 0x100) {
3025 remainder = xhci_td_remainder(
3026 urb->transfer_buffer_length -
3029 remainder = xhci_v1_0_td_remainder(running_total,
3030 trb_buff_len, total_packet_count, urb);
3032 length_field = TRB_LEN(trb_buff_len) |
3037 more_trbs_coming = true;
3039 more_trbs_coming = false;
3040 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3041 lower_32_bits(addr),
3042 upper_32_bits(addr),
3044 field | TRB_TYPE(TRB_NORMAL));
3046 running_total += trb_buff_len;
3048 /* Calculate length for next transfer */
3049 addr += trb_buff_len;
3050 trb_buff_len = urb->transfer_buffer_length - running_total;
3051 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3052 trb_buff_len = TRB_MAX_BUFF_SIZE;
3053 } while (running_total < urb->transfer_buffer_length);
3055 check_trb_math(urb, num_trbs, running_total);
3056 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3057 start_cycle, start_trb);
3061 /* Caller must have locked xhci->lock */
3062 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3063 struct urb *urb, int slot_id, unsigned int ep_index)
3065 struct xhci_ring *ep_ring;
3068 struct usb_ctrlrequest *setup;
3069 struct xhci_generic_trb *start_trb;
3071 u32 field, length_field;
3072 struct urb_priv *urb_priv;
3075 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3080 * Need to copy setup packet into setup TRB, so we can't use the setup
3083 if (!urb->setup_packet)
3086 if (!in_interrupt())
3087 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3089 /* 1 TRB for setup, 1 for status */
3092 * Don't need to check if we need additional event data and normal TRBs,
3093 * since data in control transfers will never get bigger than 16MB
3094 * XXX: can we get a buffer that crosses 64KB boundaries?
3096 if (urb->transfer_buffer_length > 0)
3098 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3099 ep_index, urb->stream_id,
3100 num_trbs, urb, 0, false, mem_flags);
3104 urb_priv = urb->hcpriv;
3105 td = urb_priv->td[0];
3108 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3109 * until we've finished creating all the other TRBs. The ring's cycle
3110 * state may change as we enqueue the other TRBs, so save it too.
3112 start_trb = &ep_ring->enqueue->generic;
3113 start_cycle = ep_ring->cycle_state;
3115 /* Queue setup TRB - see section 6.4.1.2.1 */
3116 /* FIXME better way to translate setup_packet into two u32 fields? */
3117 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3119 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3120 if (start_cycle == 0)
3123 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3124 if (xhci->hci_version == 0x100) {
3125 if (urb->transfer_buffer_length > 0) {
3126 if (setup->bRequestType & USB_DIR_IN)
3127 field |= TRB_TX_TYPE(TRB_DATA_IN);
3129 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3133 queue_trb(xhci, ep_ring, false, true, false,
3134 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3135 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3136 TRB_LEN(8) | TRB_INTR_TARGET(0),
3137 /* Immediate data in pointer */
3140 /* If there's data, queue data TRBs */
3141 /* Only set interrupt on short packet for IN endpoints */
3142 if (usb_urb_dir_in(urb))
3143 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3145 field = TRB_TYPE(TRB_DATA);
3147 length_field = TRB_LEN(urb->transfer_buffer_length) |
3148 xhci_td_remainder(urb->transfer_buffer_length) |
3150 if (urb->transfer_buffer_length > 0) {
3151 if (setup->bRequestType & USB_DIR_IN)
3152 field |= TRB_DIR_IN;
3153 queue_trb(xhci, ep_ring, false, true, false,
3154 lower_32_bits(urb->transfer_dma),
3155 upper_32_bits(urb->transfer_dma),
3157 field | ep_ring->cycle_state);
3160 /* Save the DMA address of the last TRB in the TD */
3161 td->last_trb = ep_ring->enqueue;
3163 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3164 /* If the device sent data, the status stage is an OUT transfer */
3165 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3169 queue_trb(xhci, ep_ring, false, false, false,
3173 /* Event on completion */
3174 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3176 giveback_first_trb(xhci, slot_id, ep_index, 0,
3177 start_cycle, start_trb);
3181 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3182 struct urb *urb, int i)
3187 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3188 td_len = urb->iso_frame_desc[i].length;
3190 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3199 * The transfer burst count field of the isochronous TRB defines the number of
3200 * bursts that are required to move all packets in this TD. Only SuperSpeed
3201 * devices can burst up to bMaxBurst number of packets per service interval.
3202 * This field is zero based, meaning a value of zero in the field means one
3203 * burst. Basically, for everything but SuperSpeed devices, this field will be
3204 * zero. Only xHCI 1.0 host controllers support this field.
3206 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3207 struct usb_device *udev,
3208 struct urb *urb, unsigned int total_packet_count)
3210 unsigned int max_burst;
3212 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3215 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3216 return roundup(total_packet_count, max_burst + 1) - 1;
3220 * Returns the number of packets in the last "burst" of packets. This field is
3221 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3222 * the last burst packet count is equal to the total number of packets in the
3223 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3224 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3225 * contain 1 to (bMaxBurst + 1) packets.
3227 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3228 struct usb_device *udev,
3229 struct urb *urb, unsigned int total_packet_count)
3231 unsigned int max_burst;
3232 unsigned int residue;
3234 if (xhci->hci_version < 0x100)
3237 switch (udev->speed) {
3238 case USB_SPEED_SUPER:
3239 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3240 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3241 residue = total_packet_count % (max_burst + 1);
3242 /* If residue is zero, the last burst contains (max_burst + 1)
3243 * number of packets, but the TLBPC field is zero-based.
3249 if (total_packet_count == 0)
3251 return total_packet_count - 1;
3255 /* This is for isoc transfer */
3256 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3257 struct urb *urb, int slot_id, unsigned int ep_index)
3259 struct xhci_ring *ep_ring;
3260 struct urb_priv *urb_priv;
3262 int num_tds, trbs_per_td;
3263 struct xhci_generic_trb *start_trb;
3266 u32 field, length_field;
3267 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3268 u64 start_addr, addr;
3270 bool more_trbs_coming;
3272 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3274 num_tds = urb->number_of_packets;
3276 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3280 if (!in_interrupt())
3281 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3282 " addr = %#llx, num_tds = %d\n",
3283 urb->ep->desc.bEndpointAddress,
3284 urb->transfer_buffer_length,
3285 urb->transfer_buffer_length,
3286 (unsigned long long)urb->transfer_dma,
3289 start_addr = (u64) urb->transfer_dma;
3290 start_trb = &ep_ring->enqueue->generic;
3291 start_cycle = ep_ring->cycle_state;
3293 urb_priv = urb->hcpriv;
3294 /* Queue the first TRB, even if it's zero-length */
3295 for (i = 0; i < num_tds; i++) {
3296 unsigned int total_packet_count;
3297 unsigned int burst_count;
3298 unsigned int residue;
3302 addr = start_addr + urb->iso_frame_desc[i].offset;
3303 td_len = urb->iso_frame_desc[i].length;
3304 td_remain_len = td_len;
3305 total_packet_count = roundup(td_len,
3306 usb_endpoint_maxp(&urb->ep->desc));
3307 /* A zero-length transfer still involves at least one packet. */
3308 if (total_packet_count == 0)
3309 total_packet_count++;
3310 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3311 total_packet_count);
3312 residue = xhci_get_last_burst_packet_count(xhci,
3313 urb->dev, urb, total_packet_count);
3315 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3317 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3318 urb->stream_id, trbs_per_td, urb, i, true,
3326 td = urb_priv->td[i];
3327 for (j = 0; j < trbs_per_td; j++) {
3329 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3332 /* Queue the isoc TRB */
3333 field |= TRB_TYPE(TRB_ISOC);
3334 /* Assume URB_ISO_ASAP is set */
3337 if (start_cycle == 0)
3340 field |= ep_ring->cycle_state;
3343 /* Queue other normal TRBs */
3344 field |= TRB_TYPE(TRB_NORMAL);
3345 field |= ep_ring->cycle_state;
3348 /* Only set interrupt on short packet for IN EPs */
3349 if (usb_urb_dir_in(urb))
3352 /* Chain all the TRBs together; clear the chain bit in
3353 * the last TRB to indicate it's the last TRB in the
3356 if (j < trbs_per_td - 1) {
3358 more_trbs_coming = true;
3360 td->last_trb = ep_ring->enqueue;
3362 if (xhci->hci_version == 0x100) {
3363 /* Set BEI bit except for the last td */
3364 if (i < num_tds - 1)
3367 more_trbs_coming = false;
3370 /* Calculate TRB length */
3371 trb_buff_len = TRB_MAX_BUFF_SIZE -
3372 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3373 if (trb_buff_len > td_remain_len)
3374 trb_buff_len = td_remain_len;
3376 /* Set the TRB length, TD size, & interrupter fields. */
3377 if (xhci->hci_version < 0x100) {
3378 remainder = xhci_td_remainder(
3379 td_len - running_total);
3381 remainder = xhci_v1_0_td_remainder(
3382 running_total, trb_buff_len,
3383 total_packet_count, urb);
3385 length_field = TRB_LEN(trb_buff_len) |
3389 queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3390 lower_32_bits(addr),
3391 upper_32_bits(addr),
3394 running_total += trb_buff_len;
3396 addr += trb_buff_len;
3397 td_remain_len -= trb_buff_len;
3400 /* Check TD length */
3401 if (running_total != td_len) {
3402 xhci_err(xhci, "ISOC TD length unmatch\n");
3408 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3409 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3410 usb_amd_quirk_pll_disable();
3412 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3414 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3415 start_cycle, start_trb);
3418 /* Clean up a partially enqueued isoc transfer. */
3420 for (i--; i >= 0; i--)
3421 list_del_init(&urb_priv->td[i]->td_list);
3423 /* Use the first TD as a temporary variable to turn the TDs we've queued
3424 * into No-ops with a software-owned cycle bit. That way the hardware
3425 * won't accidentally start executing bogus TDs when we partially
3426 * overwrite them. td->first_trb and td->start_seg are already set.
3428 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3429 /* Every TRB except the first & last will have its cycle bit flipped. */
3430 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3432 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3433 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3434 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3435 ep_ring->cycle_state = start_cycle;
3436 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3441 * Check transfer ring to guarantee there is enough room for the urb.
3442 * Update ISO URB start_frame and interval.
3443 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3444 * update the urb->start_frame by now.
3445 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3447 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3448 struct urb *urb, int slot_id, unsigned int ep_index)
3450 struct xhci_virt_device *xdev;
3451 struct xhci_ring *ep_ring;
3452 struct xhci_ep_ctx *ep_ctx;
3456 int num_tds, num_trbs, i;
3459 xdev = xhci->devs[slot_id];
3460 ep_ring = xdev->eps[ep_index].ring;
3461 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3464 num_tds = urb->number_of_packets;
3465 for (i = 0; i < num_tds; i++)
3466 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3468 /* Check the ring to guarantee there is enough room for the whole urb.
3469 * Do not insert any td of the urb to the ring if the check failed.
3471 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3472 num_trbs, true, mem_flags);
3476 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3477 start_frame &= 0x3fff;
3479 urb->start_frame = start_frame;
3480 if (urb->dev->speed == USB_SPEED_LOW ||
3481 urb->dev->speed == USB_SPEED_FULL)
3482 urb->start_frame >>= 3;
3484 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3485 ep_interval = urb->interval;
3486 /* Convert to microframes */
3487 if (urb->dev->speed == USB_SPEED_LOW ||
3488 urb->dev->speed == USB_SPEED_FULL)
3490 /* FIXME change this to a warning and a suggestion to use the new API
3491 * to set the polling interval (once the API is added).
3493 if (xhci_interval != ep_interval) {
3494 if (printk_ratelimit())
3495 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3496 " (%d microframe%s) than xHCI "
3497 "(%d microframe%s)\n",
3499 ep_interval == 1 ? "" : "s",
3501 xhci_interval == 1 ? "" : "s");
3502 urb->interval = xhci_interval;
3503 /* Convert back to frames for LS/FS devices */
3504 if (urb->dev->speed == USB_SPEED_LOW ||
3505 urb->dev->speed == USB_SPEED_FULL)
3508 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3511 /**** Command Ring Operations ****/
3513 /* Generic function for queueing a command TRB on the command ring.
3514 * Check to make sure there's room on the command ring for one command TRB.
3515 * Also check that there's room reserved for commands that must not fail.
3516 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3517 * then only check for the number of reserved spots.
3518 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3519 * because the command event handler may want to resubmit a failed command.
3521 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3522 u32 field3, u32 field4, bool command_must_succeed)
3524 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3527 if (!command_must_succeed)
3530 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3531 reserved_trbs, false, GFP_ATOMIC);
3533 xhci_err(xhci, "ERR: No room for command on command ring\n");
3534 if (command_must_succeed)
3535 xhci_err(xhci, "ERR: Reserved TRB counting for "
3536 "unfailable commands failed.\n");
3539 queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3540 field3, field4 | xhci->cmd_ring->cycle_state);
3544 /* Queue a slot enable or disable request on the command ring */
3545 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3547 return queue_command(xhci, 0, 0, 0,
3548 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3551 /* Queue an address device command TRB */
3552 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3555 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3556 upper_32_bits(in_ctx_ptr), 0,
3557 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3561 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3562 u32 field1, u32 field2, u32 field3, u32 field4)
3564 return queue_command(xhci, field1, field2, field3, field4, false);
3567 /* Queue a reset device command TRB */
3568 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3570 return queue_command(xhci, 0, 0, 0,
3571 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3575 /* Queue a configure endpoint command TRB */
3576 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3577 u32 slot_id, bool command_must_succeed)
3579 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3580 upper_32_bits(in_ctx_ptr), 0,
3581 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3582 command_must_succeed);
3585 /* Queue an evaluate context command TRB */
3586 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3589 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3590 upper_32_bits(in_ctx_ptr), 0,
3591 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3596 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3597 * activity on an endpoint that is about to be suspended.
3599 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3600 unsigned int ep_index, int suspend)
3602 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3603 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3604 u32 type = TRB_TYPE(TRB_STOP_RING);
3605 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3607 return queue_command(xhci, 0, 0, 0,
3608 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3611 /* Set Transfer Ring Dequeue Pointer command.
3612 * This should not be used for endpoints that have streams enabled.
3614 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3615 unsigned int ep_index, unsigned int stream_id,
3616 struct xhci_segment *deq_seg,
3617 union xhci_trb *deq_ptr, u32 cycle_state)
3620 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3621 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3622 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3623 u32 type = TRB_TYPE(TRB_SET_DEQ);
3624 struct xhci_virt_ep *ep;
3626 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3628 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3629 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3633 ep = &xhci->devs[slot_id]->eps[ep_index];
3634 if ((ep->ep_state & SET_DEQ_PENDING)) {
3635 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3636 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3639 ep->queued_deq_seg = deq_seg;
3640 ep->queued_deq_ptr = deq_ptr;
3641 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3642 upper_32_bits(addr), trb_stream_id,
3643 trb_slot_id | trb_ep_index | type, false);
3646 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3647 unsigned int ep_index)
3649 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3650 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3651 u32 type = TRB_TYPE(TRB_RESET_EP);
3653 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,