drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         do {
 153                 /*
 154                  * Update the dequeue pointer further if that was a link TRB or
 155                  * we're at the end of an event ring segment (which doesn't have
 156                  * link TRBS)
 157                  */
 158                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 159                         if (consumer && last_trb_on_last_seg(xhci, ring,
 160                                                 ring->deq_seg, ring->dequeue)) {
 161                                 if (!in_interrupt())
 162                                         xhci_dbg(xhci, "Toggle cycle state "
 163                                                         "for ring %p = %i\n",
 164                                                         ring,
 165                                                         (unsigned int)
 166                                                         ring->cycle_state);
 167                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 168                         }
 169                         ring->deq_seg = ring->deq_seg->next;
 170                         ring->dequeue = ring->deq_seg->trbs;
 171                 } else {
 172                         ring->dequeue++;
 173                 }
 174         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 175
 176         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 177 }
 178
 179 /*
 180  * See Cycle bit rules. SW is the consumer for the event ring only.
 181  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 182  *
 183  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 184  * chain bit is set), then set the chain bit in all the following link TRBs.
 185  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 186  * have their chain bit cleared (so that each Link TRB is a separate TD).
 187  *
 188  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 189  * set, but other sections talk about dealing with the chain bit set.  This was
 190  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 191  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 192  *
 193  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 194  *                      prepare_transfer()?
 195  */
 196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 197                 bool consumer, bool more_trbs_coming, bool isoc)
 198 {
 199         u32 chain;
 200         union xhci_trb *next;
 201         unsigned long long addr;
 202
 203         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 204         next = ++(ring->enqueue);
 205
 206         ring->enq_updates++;
 207         /* Update the dequeue pointer further if that was a link TRB or we're at
 208          * the end of an event ring segment (which doesn't have link TRBS)
 209          */
 210         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 211                 if (!consumer) {
 212                         if (ring != xhci->event_ring) {
 213                                 /*
 214                                  * If the caller doesn't plan on enqueueing more
 215                                  * TDs before ringing the doorbell, then we
 216                                  * don't want to give the link TRB to the
 217                                  * hardware just yet.  We'll give the link TRB
 218                                  * back in prepare_ring() just before we enqueue
 219                                  * the TD at the top of the ring.
 220                                  */
 221                                 if (!chain && !more_trbs_coming)
 222                                         break;
 223
 224                                 /* If we're not dealing with 0.95 hardware or
 225                                  * isoc rings on AMD 0.96 host,
 226                                  * carry over the chain bit of the previous TRB
 227                                  * (which may mean the chain bit is cleared).
 228                                  */
 229                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 230                                                 && !xhci_link_trb_quirk(xhci)) {
 231                                         next->link.control &=
 232                                                 cpu_to_le32(~TRB_CHAIN);
 233                                         next->link.control |=
 234                                                 cpu_to_le32(chain);
 235                                 }
 236                                 /* Give this link TRB to the hardware */
 237                                 wmb();
 238                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 239                         }
 240                         /* Toggle the cycle bit after the last ring segment. */
 241                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 242                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 243                                 if (!in_interrupt())
 244                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 245                                                         ring,
 246                                                         (unsigned int) ring->cycle_state);
 247                         }
 248                 }
 249                 ring->enq_seg = ring->enq_seg->next;
 250                 ring->enqueue = ring->enq_seg->trbs;
 251                 next = ring->enqueue;
 252         }
 253         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 254 }
 255
 256 /*
 257  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 258  * above.
 259  * FIXME: this would be simpler and faster if we just kept track of the number
 260  * of free TRBs in a ring.
 261  */
 262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 263                 unsigned int num_trbs)
 264 {
 265         int i;
 266         union xhci_trb *enq = ring->enqueue;
 267         struct xhci_segment *enq_seg = ring->enq_seg;
 268         struct xhci_segment *cur_seg;
 269         unsigned int left_on_ring;
 270
 271         /* If we are currently pointing to a link TRB, advance the
 272          * enqueue pointer before checking for space */
 273         while (last_trb(xhci, ring, enq_seg, enq)) {
 274                 enq_seg = enq_seg->next;
 275                 enq = enq_seg->trbs;
 276         }
 277
 278         /* Check if ring is empty */
 279         if (enq == ring->dequeue) {
 280                 /* Can't use link trbs */
 281                 left_on_ring = TRBS_PER_SEGMENT - 1;
 282                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 283                                 cur_seg = cur_seg->next)
 284                         left_on_ring += TRBS_PER_SEGMENT - 1;
 285
 286                 /* Always need one TRB free in the ring. */
 287                 left_on_ring -= 1;
 288                 if (num_trbs > left_on_ring) {
 289                         xhci_warn(xhci, "Not enough room on ring; "
 290                                         "need %u TRBs, %u TRBs left\n",
 291                                         num_trbs, left_on_ring);
 292                         return 0;
 293                 }
 294                 return 1;
 295         }
 296         /* Make sure there's an extra empty TRB available */
 297         for (i = 0; i <= num_trbs; ++i) {
 298                 if (enq == ring->dequeue)
 299                         return 0;
 300                 enq++;
 301                 while (last_trb(xhci, ring, enq_seg, enq)) {
 302                         enq_seg = enq_seg->next;
 303                         enq = enq_seg->trbs;
 304                 }
 305         }
 306         return 1;
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 313                 return;
 314
 315         xhci_dbg(xhci, "// Ding dong!\n");
 316         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 322 {
 323         u64 temp_64;
 324         int ret;
 325
 326         xhci_dbg(xhci, "Abort command ring\n");
 327
 328         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 329                 xhci_dbg(xhci, "The command ring isn't running, "
 330                                 "Have the command ring been stopped?\n");
 331                 return 0;
 332         }
 333
 334         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 335         if (!(temp_64 & CMD_RING_RUNNING)) {
 336                 xhci_dbg(xhci, "Command ring had been stopped\n");
 337                 return 0;
 338         }
 339         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 340         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 341                         &xhci->op_regs->cmd_ring);
 342
 343         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 344          * time the completion od all xHCI commands, including
 345          * the Command Abort operation. If software doesn't see
 346          * CRR negated in a timely manner (e.g. longer than 5
 347          * seconds), then it should assume that the there are
 348          * larger problems with the xHC and assert HCRST.
 349          */
 350         ret = handshake(xhci, &xhci->op_regs->cmd_ring,
 351                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 352         if (ret < 0) {
 353                 xhci_err(xhci, "Stopped the command ring failed, "
 354                                 "maybe the host is dead\n");
 355                 xhci->xhc_state |= XHCI_STATE_DYING;
 356                 xhci_quiesce(xhci);
 357                 xhci_halt(xhci);
 358                 return -ESHUTDOWN;
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int xhci_queue_cd(struct xhci_hcd *xhci,
 365                 struct xhci_command *command,
 366                 union xhci_trb *cmd_trb)
 367 {
 368         struct xhci_cd *cd;
 369         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 370         if (!cd)
 371                 return -ENOMEM;
 372         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 373
 374         cd->command = command;
 375         cd->cmd_trb = cmd_trb;
 376         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 377
 378         return 0;
 379 }
 380
 381 /*
 382  * Cancel the command which has issue.
 383  *
 384  * Some commands may hang due to waiting for acknowledgement from
 385  * usb device. It is outside of the xHC's ability to control and
 386  * will cause the command ring is blocked. When it occurs software
 387  * should intervene to recover the command ring.
 388  * See Section 4.6.1.1 and 4.6.1.2
 389  */
 390 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 391                 union xhci_trb *cmd_trb)
 392 {
 393         int retval = 0;
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&xhci->lock, flags);
 397
 398         if (xhci->xhc_state & XHCI_STATE_DYING) {
 399                 xhci_warn(xhci, "Abort the command ring,"
 400                                 " but the xHCI is dead.\n");
 401                 retval = -ESHUTDOWN;
 402                 goto fail;
 403         }
 404
 405         /* queue the cmd desriptor to cancel_cmd_list */
 406         retval = xhci_queue_cd(xhci, command, cmd_trb);
 407         if (retval) {
 408                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 409                 goto fail;
 410         }
 411
 412         /* abort command ring */
 413         retval = xhci_abort_cmd_ring(xhci);
 414         if (retval) {
 415                 xhci_err(xhci, "Abort command ring failed\n");
 416                 if (unlikely(retval == -ESHUTDOWN)) {
 417                         spin_unlock_irqrestore(&xhci->lock, flags);
 418                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 419                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 420                         return retval;
 421                 }
 422         }
 423
 424 fail:
 425         spin_unlock_irqrestore(&xhci->lock, flags);
 426         return retval;
 427 }
 428
 429 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 430                 unsigned int slot_id,
 431                 unsigned int ep_index,
 432                 unsigned int stream_id)
 433 {
 434         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 435         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 436         unsigned int ep_state = ep->ep_state;
 437
 438         /* Don't ring the doorbell for this endpoint if there are pending
 439          * cancellations because we don't want to interrupt processing.
 440          * We don't want to restart any stream rings if there's a set dequeue
 441          * pointer command pending because the device can choose to start any
 442          * stream once the endpoint is on the HW schedule.
 443          * FIXME - check all the stream rings for pending cancellations.
 444          */
 445         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 446             (ep_state & EP_HALTED))
 447                 return;
 448         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 449         /* The CPU has better things to do at this point than wait for a
 450          * write-posting flush.  It'll get there soon enough.
 451          */
 452 }
 453
 454 /* Ring the doorbell for any rings with pending URBs */
 455 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 456                 unsigned int slot_id,
 457                 unsigned int ep_index)
 458 {
 459         unsigned int stream_id;
 460         struct xhci_virt_ep *ep;
 461
 462         ep = &xhci->devs[slot_id]->eps[ep_index];
 463
 464         /* A ring has pending URBs if its TD list is not empty */
 465         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 466                 if (!(list_empty(&ep->ring->td_list)))
 467                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 468                 return;
 469         }
 470
 471         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 472                         stream_id++) {
 473                 struct xhci_stream_info *stream_info = ep->stream_info;
 474                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 475                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 476                                                 stream_id);
 477         }
 478 }
 479
 480 /*
 481  * Find the segment that trb is in.  Start searching in start_seg.
 482  * If we must move past a segment that has a link TRB with a toggle cycle state
 483  * bit set, then we will toggle the value pointed at by cycle_state.
 484  */
 485 static struct xhci_segment *find_trb_seg(
 486                 struct xhci_segment *start_seg,
 487                 union xhci_trb  *trb, int *cycle_state)
 488 {
 489         struct xhci_segment *cur_seg = start_seg;
 490         struct xhci_generic_trb *generic_trb;
 491
 492         while (cur_seg->trbs > trb ||
 493                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 494                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 495                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 496                         *cycle_state ^= 0x1;
 497                 cur_seg = cur_seg->next;
 498                 if (cur_seg == start_seg)
 499                         /* Looped over the entire list.  Oops! */
 500                         return NULL;
 501         }
 502         return cur_seg;
 503 }
 504
 505
 506 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 507                 unsigned int slot_id, unsigned int ep_index,
 508                 unsigned int stream_id)
 509 {
 510         struct xhci_virt_ep *ep;
 511
 512         ep = &xhci->devs[slot_id]->eps[ep_index];
 513         /* Common case: no streams */
 514         if (!(ep->ep_state & EP_HAS_STREAMS))
 515                 return ep->ring;
 516
 517         if (stream_id == 0) {
 518                 xhci_warn(xhci,
 519                                 "WARN: Slot ID %u, ep index %u has streams, "
 520                                 "but URB has no stream ID.\n",
 521                                 slot_id, ep_index);
 522                 return NULL;
 523         }
 524
 525         if (stream_id < ep->stream_info->num_streams)
 526                 return ep->stream_info->stream_rings[stream_id];
 527
 528         xhci_warn(xhci,
 529                         "WARN: Slot ID %u, ep index %u has "
 530                         "stream IDs 1 to %u allocated, "
 531                         "but stream ID %u is requested.\n",
 532                         slot_id, ep_index,
 533                         ep->stream_info->num_streams - 1,
 534                         stream_id);
 535         return NULL;
 536 }
 537
 538 /* Get the right ring for the given URB.
 539  * If the endpoint supports streams, boundary check the URB's stream ID.
 540  * If the endpoint doesn't support streams, return the singular endpoint ring.
 541  */
 542 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 543                 struct urb *urb)
 544 {
 545         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 546                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 547 }
 548
 549 /*
 550  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 551  * Record the new state of the xHC's endpoint ring dequeue segment,
 552  * dequeue pointer, and new consumer cycle state in state.
 553  * Update our internal representation of the ring's dequeue pointer.
 554  *
 555  * We do this in three jumps:
 556  *  - First we update our new ring state to be the same as when the xHC stopped.
 557  *  - Then we traverse the ring to find the segment that contains
 558  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 559  *    any link TRBs with the toggle cycle bit set.
 560  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 561  *    if we've moved it past a link TRB with the toggle cycle bit set.
 562  *
 563  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 564  * with correct __le32 accesses they should work fine.  Only users of this are
 565  * in here.
 566  */
 567 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 568                 unsigned int slot_id, unsigned int ep_index,
 569                 unsigned int stream_id, struct xhci_td *cur_td,
 570                 struct xhci_dequeue_state *state)
 571 {
 572         struct xhci_virt_device *dev = xhci->devs[slot_id];
 573         struct xhci_ring *ep_ring;
 574         struct xhci_generic_trb *trb;
 575         struct xhci_ep_ctx *ep_ctx;
 576         dma_addr_t addr;
 577
 578         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 579                         ep_index, stream_id);
 580         if (!ep_ring) {
 581                 xhci_warn(xhci, "WARN can't find new dequeue state "
 582                                 "for invalid stream ID %u.\n",
 583                                 stream_id);
 584                 return;
 585         }
 586         state->new_cycle_state = 0;
 587         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 588         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 589                         dev->eps[ep_index].stopped_trb,
 590                         &state->new_cycle_state);
 591         if (!state->new_deq_seg) {
 592                 WARN_ON(1);
 593                 return;
 594         }
 595
 596         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 597         xhci_dbg(xhci, "Finding endpoint context\n");
 598         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 599         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 600
 601         state->new_deq_ptr = cur_td->last_trb;
 602         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 603         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 604                         state->new_deq_ptr,
 605                         &state->new_cycle_state);
 606         if (!state->new_deq_seg) {
 607                 WARN_ON(1);
 608                 return;
 609         }
 610
 611         trb = &state->new_deq_ptr->generic;
 612         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 613             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 614                 state->new_cycle_state ^= 0x1;
 615         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 616
 617         /*
 618          * If there is only one segment in a ring, find_trb_seg()'s while loop
 619          * will not run, and it will return before it has a chance to see if it
 620          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 621          * ended just before the link TRB on a one-segment ring, or if the TD
 622          * wrapped around the top of the ring, because it doesn't have the TD in
 623          * question.  Look for the one-segment case where stalled TRB's address
 624          * is greater than the new dequeue pointer address.
 625          */
 626         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 627                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 628                 state->new_cycle_state ^= 0x1;
 629         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 630
 631         /* Don't update the ring cycle state for the producer (us). */
 632         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 633                         state->new_deq_seg);
 634         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 635         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 636                         (unsigned long long) addr);
 637 }
 638
 639 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 640  * (The last TRB actually points to the ring enqueue pointer, which is not part
 641  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 642  */
 643 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 644                 struct xhci_td *cur_td, bool flip_cycle)
 645 {
 646         struct xhci_segment *cur_seg;
 647         union xhci_trb *cur_trb;
 648
 649         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 650                         true;
 651                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 652                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 653                         /* Unchain any chained Link TRBs, but
 654                          * leave the pointers intact.
 655                          */
 656                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 657                         /* Flip the cycle bit (link TRBs can't be the first
 658                          * or last TRB).
 659                          */
 660                         if (flip_cycle)
 661                                 cur_trb->generic.field[3] ^=
 662                                         cpu_to_le32(TRB_CYCLE);
 663                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 664                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 665                                         "in seg %p (0x%llx dma)\n",
 666                                         cur_trb,
 667                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 668                                         cur_seg,
 669                                         (unsigned long long)cur_seg->dma);
 670                 } else {
 671                         cur_trb->generic.field[0] = 0;
 672                         cur_trb->generic.field[1] = 0;
 673                         cur_trb->generic.field[2] = 0;
 674                         /* Preserve only the cycle bit of this TRB */
 675                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 676                         /* Flip the cycle bit except on the first or last TRB */
 677                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 678                                         cur_trb != cur_td->last_trb)
 679                                 cur_trb->generic.field[3] ^=
 680                                         cpu_to_le32(TRB_CYCLE);
 681                         cur_trb->generic.field[3] |= cpu_to_le32(
 682                                 TRB_TYPE(TRB_TR_NOOP));
 683                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 684                                         "in seg %p (0x%llx dma)\n",
 685                                         cur_trb,
 686                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 687                                         cur_seg,
 688                                         (unsigned long long)cur_seg->dma);
 689                 }
 690                 if (cur_trb == cur_td->last_trb)
 691                         break;
 692         }
 693 }
 694
 695 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 696                 unsigned int ep_index, unsigned int stream_id,
 697                 struct xhci_segment *deq_seg,
 698                 union xhci_trb *deq_ptr, u32 cycle_state);
 699
 700 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 701                 unsigned int slot_id, unsigned int ep_index,
 702                 unsigned int stream_id,
 703                 struct xhci_dequeue_state *deq_state)
 704 {
 705         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 706
 707         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 708                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 709                         deq_state->new_deq_seg,
 710                         (unsigned long long)deq_state->new_deq_seg->dma,
 711                         deq_state->new_deq_ptr,
 712                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 713                         deq_state->new_cycle_state);
 714         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 715                         deq_state->new_deq_seg,
 716                         deq_state->new_deq_ptr,
 717                         (u32) deq_state->new_cycle_state);
 718         /* Stop the TD queueing code from ringing the doorbell until
 719          * this command completes.  The HC won't set the dequeue pointer
 720          * if the ring is running, and ringing the doorbell starts the
 721          * ring running.
 722          */
 723         ep->ep_state |= SET_DEQ_PENDING;
 724 }
 725
 726 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 727                 struct xhci_virt_ep *ep)
 728 {
 729         ep->ep_state &= ~EP_HALT_PENDING;
 730         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 731          * timer is running on another CPU, we don't decrement stop_cmds_pending
 732          * (since we didn't successfully stop the watchdog timer).
 733          */
 734         if (del_timer(&ep->stop_cmd_timer))
 735                 ep->stop_cmds_pending--;
 736 }
 737
 738 /* Must be called with xhci->lock held in interrupt context */
 739 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 740                 struct xhci_td *cur_td, int status, char *adjective)
 741 {
 742         struct usb_hcd *hcd;
 743         struct urb      *urb;
 744         struct urb_priv *urb_priv;
 745
 746         urb = cur_td->urb;
 747         urb_priv = urb->hcpriv;
 748         urb_priv->td_cnt++;
 749         hcd = bus_to_hcd(urb->dev->bus);
 750
 751         /* Only giveback urb when this is the last td in urb */
 752         if (urb_priv->td_cnt == urb_priv->length) {
 753                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 754                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 755                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 756                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 757                                         usb_amd_quirk_pll_enable();
 758                         }
 759                 }
 760                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 761
 762                 spin_unlock(&xhci->lock);
 763                 usb_hcd_giveback_urb(hcd, urb, status);
 764                 xhci_urb_free_priv(xhci, urb_priv);
 765                 spin_lock(&xhci->lock);
 766         }
 767 }
 768
 769 /*
 770  * When we get a command completion for a Stop Endpoint Command, we need to
 771  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 772  *
 773  *  1. If the HW was in the middle of processing the TD that needs to be
 774  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 775  *     in the TD with a Set Dequeue Pointer Command.
 776  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 777  *     bit cleared) so that the HW will skip over them.
 778  */
 779 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 780                 union xhci_trb *trb, struct xhci_event_cmd *event)
 781 {
 782         unsigned int slot_id;
 783         unsigned int ep_index;
 784         struct xhci_virt_device *virt_dev;
 785         struct xhci_ring *ep_ring;
 786         struct xhci_virt_ep *ep;
 787         struct list_head *entry;
 788         struct xhci_td *cur_td = NULL;
 789         struct xhci_td *last_unlinked_td;
 790
 791         struct xhci_dequeue_state deq_state;
 792
 793         if (unlikely(TRB_TO_SUSPEND_PORT(
 794                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 795                 slot_id = TRB_TO_SLOT_ID(
 796                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 797                 virt_dev = xhci->devs[slot_id];
 798                 if (virt_dev)
 799                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 800                                 event);
 801                 else
 802                         xhci_warn(xhci, "Stop endpoint command "
 803                                 "completion for disabled slot %u\n",
 804                                 slot_id);
 805                 return;
 806         }
 807
 808         memset(&deq_state, 0, sizeof(deq_state));
 809         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 810         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 811         ep = &xhci->devs[slot_id]->eps[ep_index];
 812
 813         if (list_empty(&ep->cancelled_td_list)) {
 814                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 815                 ep->stopped_td = NULL;
 816                 ep->stopped_trb = NULL;
 817                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 818                 return;
 819         }
 820
 821         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 822          * We have the xHCI lock, so nothing can modify this list until we drop
 823          * it.  We're also in the event handler, so we can't get re-interrupted
 824          * if another Stop Endpoint command completes
 825          */
 826         list_for_each(entry, &ep->cancelled_td_list) {
 827                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 828                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 829                                 cur_td->first_trb,
 830                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 831                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 832                 if (!ep_ring) {
 833                         /* This shouldn't happen unless a driver is mucking
 834                          * with the stream ID after submission.  This will
 835                          * leave the TD on the hardware ring, and the hardware
 836                          * will try to execute it, and may access a buffer
 837                          * that has already been freed.  In the best case, the
 838                          * hardware will execute it, and the event handler will
 839                          * ignore the completion event for that TD, since it was
 840                          * removed from the td_list for that endpoint.  In
 841                          * short, don't muck with the stream ID after
 842                          * submission.
 843                          */
 844                         xhci_warn(xhci, "WARN Cancelled URB %p "
 845                                         "has invalid stream ID %u.\n",
 846                                         cur_td->urb,
 847                                         cur_td->urb->stream_id);
 848                         goto remove_finished_td;
 849                 }
 850                 /*
 851                  * If we stopped on the TD we need to cancel, then we have to
 852                  * move the xHC endpoint ring dequeue pointer past this TD.
 853                  */
 854                 if (cur_td == ep->stopped_td)
 855                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 856                                         cur_td->urb->stream_id,
 857                                         cur_td, &deq_state);
 858                 else
 859                         td_to_noop(xhci, ep_ring, cur_td, false);
 860 remove_finished_td:
 861                 /*
 862                  * The event handler won't see a completion for this TD anymore,
 863                  * so remove it from the endpoint ring's TD list.  Keep it in
 864                  * the cancelled TD list for URB completion later.
 865                  */
 866                 list_del_init(&cur_td->td_list);
 867         }
 868         last_unlinked_td = cur_td;
 869         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 870
 871         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 872         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 873                 xhci_queue_new_dequeue_state(xhci,
 874                                 slot_id, ep_index,
 875                                 ep->stopped_td->urb->stream_id,
 876                                 &deq_state);
 877                 xhci_ring_cmd_db(xhci);
 878         } else {
 879                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 880                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 881         }
 882         ep->stopped_td = NULL;
 883         ep->stopped_trb = NULL;
 884
 885         /*
 886          * Drop the lock and complete the URBs in the cancelled TD list.
 887          * New TDs to be cancelled might be added to the end of the list before
 888          * we can complete all the URBs for the TDs we already unlinked.
 889          * So stop when we've completed the URB for the last TD we unlinked.
 890          */
 891         do {
 892                 cur_td = list_entry(ep->cancelled_td_list.next,
 893                                 struct xhci_td, cancelled_td_list);
 894                 list_del_init(&cur_td->cancelled_td_list);
 895
 896                 /* Clean up the cancelled URB */
 897                 /* Doesn't matter what we pass for status, since the core will
 898                  * just overwrite it (because the URB has been unlinked).
 899                  */
 900                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 901
 902                 /* Stop processing the cancelled list if the watchdog timer is
 903                  * running.
 904                  */
 905                 if (xhci->xhc_state & XHCI_STATE_DYING)
 906                         return;
 907         } while (cur_td != last_unlinked_td);
 908
 909         /* Return to the event handler with xhci->lock re-acquired */
 910 }
 911
 912 /* Watchdog timer function for when a stop endpoint command fails to complete.
 913  * In this case, we assume the host controller is broken or dying or dead.  The
 914  * host may still be completing some other events, so we have to be careful to
 915  * let the event ring handler and the URB dequeueing/enqueueing functions know
 916  * through xhci->state.
 917  *
 918  * The timer may also fire if the host takes a very long time to respond to the
 919  * command, and the stop endpoint command completion handler cannot delete the
 920  * timer before the timer function is called.  Another endpoint cancellation may
 921  * sneak in before the timer function can grab the lock, and that may queue
 922  * another stop endpoint command and add the timer back.  So we cannot use a
 923  * simple flag to say whether there is a pending stop endpoint command for a
 924  * particular endpoint.
 925  *
 926  * Instead we use a combination of that flag and a counter for the number of
 927  * pending stop endpoint commands.  If the timer is the tail end of the last
 928  * stop endpoint command, and the endpoint's command is still pending, we assume
 929  * the host is dying.
 930  */
 931 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 932 {
 933         struct xhci_hcd *xhci;
 934         struct xhci_virt_ep *ep;
 935         struct xhci_virt_ep *temp_ep;
 936         struct xhci_ring *ring;
 937         struct xhci_td *cur_td;
 938         int ret, i, j;
 939         unsigned long flags;
 940
 941         ep = (struct xhci_virt_ep *) arg;
 942         xhci = ep->xhci;
 943
 944         spin_lock_irqsave(&xhci->lock, flags);
 945
 946         ep->stop_cmds_pending--;
 947         if (xhci->xhc_state & XHCI_STATE_DYING) {
 948                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 949                                 "xHCI as DYING, exiting.\n");
 950                 spin_unlock_irqrestore(&xhci->lock, flags);
 951                 return;
 952         }
 953         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 954                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 955                                 "exiting.\n");
 956                 spin_unlock_irqrestore(&xhci->lock, flags);
 957                 return;
 958         }
 959
 960         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 961         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 962         /* Oops, HC is dead or dying or at least not responding to the stop
 963          * endpoint command.
 964          */
 965         xhci->xhc_state |= XHCI_STATE_DYING;
 966         /* Disable interrupts from the host controller and start halting it */
 967         xhci_quiesce(xhci);
 968         spin_unlock_irqrestore(&xhci->lock, flags);
 969
 970         ret = xhci_halt(xhci);
 971
 972         spin_lock_irqsave(&xhci->lock, flags);
 973         if (ret < 0) {
 974                 /* This is bad; the host is not responding to commands and it's
 975                  * not allowing itself to be halted.  At least interrupts are
 976                  * disabled. If we call usb_hc_died(), it will attempt to
 977                  * disconnect all device drivers under this host.  Those
 978                  * disconnect() methods will wait for all URBs to be unlinked,
 979                  * so we must complete them.
 980                  */
 981                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 982                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 983                 /* We could turn all TDs on the rings to no-ops.  This won't
 984                  * help if the host has cached part of the ring, and is slow if
 985                  * we want to preserve the cycle bit.  Skip it and hope the host
 986                  * doesn't touch the memory.
 987                  */
 988         }
 989         for (i = 0; i < MAX_HC_SLOTS; i++) {
 990                 if (!xhci->devs[i])
 991                         continue;
 992                 for (j = 0; j < 31; j++) {
 993                         temp_ep = &xhci->devs[i]->eps[j];
 994                         ring = temp_ep->ring;
 995                         if (!ring)
 996                                 continue;
 997                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 998                                         "ep index %u\n", i, j);
 999                         while (!list_empty(&ring->td_list)) {
1000                                 cur_td = list_first_entry(&ring->td_list,
1001                                                 struct xhci_td,
1002                                                 td_list);
1003                                 list_del_init(&cur_td->td_list);
1004                                 if (!list_empty(&cur_td->cancelled_td_list))
1005                                         list_del_init(&cur_td->cancelled_td_list);
1006                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1007                                                 -ESHUTDOWN, "killed");
1008                         }
1009                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1010                                 cur_td = list_first_entry(
1011                                                 &temp_ep->cancelled_td_list,
1012                                                 struct xhci_td,
1013                                                 cancelled_td_list);
1014                                 list_del_init(&cur_td->cancelled_td_list);
1015                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1016                                                 -ESHUTDOWN, "killed");
1017                         }
1018                 }
1019         }
1020         spin_unlock_irqrestore(&xhci->lock, flags);
1021         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1022         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1023         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1024 }
1025
1026 /*
1027  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1028  * we need to clear the set deq pending flag in the endpoint ring state, so that
1029  * the TD queueing code can ring the doorbell again.  We also need to ring the
1030  * endpoint doorbell to restart the ring, but only if there aren't more
1031  * cancellations pending.
1032  */
1033 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1034                 struct xhci_event_cmd *event,
1035                 union xhci_trb *trb)
1036 {
1037         unsigned int slot_id;
1038         unsigned int ep_index;
1039         unsigned int stream_id;
1040         struct xhci_ring *ep_ring;
1041         struct xhci_virt_device *dev;
1042         struct xhci_ep_ctx *ep_ctx;
1043         struct xhci_slot_ctx *slot_ctx;
1044
1045         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1046         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1047         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1048         dev = xhci->devs[slot_id];
1049
1050         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1051         if (!ep_ring) {
1052                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1053                                 "freed stream ID %u\n",
1054                                 stream_id);
1055                 /* XXX: Harmless??? */
1056                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1057                 return;
1058         }
1059
1060         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1061         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1062
1063         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1064                 unsigned int ep_state;
1065                 unsigned int slot_state;
1066
1067                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1068                 case COMP_TRB_ERR:
1069                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1070                                         "of stream ID configuration\n");
1071                         break;
1072                 case COMP_CTX_STATE:
1073                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1074                                         "to incorrect slot or ep state.\n");
1075                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1076                         ep_state &= EP_STATE_MASK;
1077                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1078                         slot_state = GET_SLOT_STATE(slot_state);
1079                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1080                                         slot_state, ep_state);
1081                         break;
1082                 case COMP_EBADSLT:
1083                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1084                                         "slot %u was not enabled.\n", slot_id);
1085                         break;
1086                 default:
1087                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1088                                         "completion code of %u.\n",
1089                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1090                         break;
1091                 }
1092                 /* OK what do we do now?  The endpoint state is hosed, and we
1093                  * should never get to this point if the synchronization between
1094                  * queueing, and endpoint state are correct.  This might happen
1095                  * if the device gets disconnected after we've finished
1096                  * cancelling URBs, which might not be an error...
1097                  */
1098         } else {
1099                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1100                          le64_to_cpu(ep_ctx->deq));
1101                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1102                                          dev->eps[ep_index].queued_deq_ptr) ==
1103                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1104                         /* Update the ring's dequeue segment and dequeue pointer
1105                          * to reflect the new position.
1106                          */
1107                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1108                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1109                 } else {
1110                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1111                                         "Ptr command & xHCI internal state.\n");
1112                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1113                                         dev->eps[ep_index].queued_deq_seg,
1114                                         dev->eps[ep_index].queued_deq_ptr);
1115                 }
1116         }
1117
1118         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1119         dev->eps[ep_index].queued_deq_seg = NULL;
1120         dev->eps[ep_index].queued_deq_ptr = NULL;
1121         /* Restart any rings with pending URBs */
1122         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1123 }
1124
1125 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1126                 struct xhci_event_cmd *event,
1127                 union xhci_trb *trb)
1128 {
1129         int slot_id;
1130         unsigned int ep_index;
1131
1132         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1133         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1134         /* This command will only fail if the endpoint wasn't halted,
1135          * but we don't care.
1136          */
1137         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1138                  GET_COMP_CODE(le32_to_cpu(event->status)));
1139
1140         /* HW with the reset endpoint quirk needs to have a configure endpoint
1141          * command complete before the endpoint can be used.  Queue that here
1142          * because the HW can't handle two commands being queued in a row.
1143          */
1144         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1145                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1146                 xhci_queue_configure_endpoint(xhci,
1147                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1148                                 false);
1149                 xhci_ring_cmd_db(xhci);
1150         } else {
1151                 /* Clear our internal halted state and restart the ring(s) */
1152                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1153                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1154         }
1155 }
1156
1157 /* Complete the command and detele it from the devcie's command queue.
1158  */
1159 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1160                 struct xhci_command *command, u32 status)
1161 {
1162         command->status = status;
1163         list_del(&command->cmd_list);
1164         if (command->completion)
1165                 complete(command->completion);
1166         else
1167                 xhci_free_command(xhci, command);
1168 }
1169
1170
1171 /* Check to see if a command in the device's command queue matches this one.
1172  * Signal the completion or free the command, and return 1.  Return 0 if the
1173  * completed command isn't at the head of the command list.
1174  */
1175 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1176                 struct xhci_virt_device *virt_dev,
1177                 struct xhci_event_cmd *event)
1178 {
1179         struct xhci_command *command;
1180
1181         if (list_empty(&virt_dev->cmd_list))
1182                 return 0;
1183
1184         command = list_entry(virt_dev->cmd_list.next,
1185                         struct xhci_command, cmd_list);
1186         if (xhci->cmd_ring->dequeue != command->command_trb)
1187                 return 0;
1188
1189         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1190                         GET_COMP_CODE(le32_to_cpu(event->status)));
1191         return 1;
1192 }
1193
1194 /*
1195  * Finding the command trb need to be cancelled and modifying it to
1196  * NO OP command. And if the command is in device's command wait
1197  * list, finishing and freeing it.
1198  *
1199  * If we can't find the command trb, we think it had already been
1200  * executed.
1201  */
1202 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1203 {
1204         struct xhci_segment *cur_seg;
1205         union xhci_trb *cmd_trb;
1206         u32 cycle_state;
1207
1208         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1209                 return;
1210
1211         /* find the current segment of command ring */
1212         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1213                         xhci->cmd_ring->dequeue, &cycle_state);
1214
1215         if (!cur_seg) {
1216                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1217                                 xhci->cmd_ring->dequeue,
1218                                 (unsigned long long)
1219                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1220                                         xhci->cmd_ring->dequeue));
1221                 xhci_debug_ring(xhci, xhci->cmd_ring);
1222                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1223                 return;
1224         }
1225
1226         /* find the command trb matched by cd from command ring */
1227         for (cmd_trb = xhci->cmd_ring->dequeue;
1228                         cmd_trb != xhci->cmd_ring->enqueue;
1229                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1230                 /* If the trb is link trb, continue */
1231                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1232                         continue;
1233
1234                 if (cur_cd->cmd_trb == cmd_trb) {
1235
1236                         /* If the command in device's command list, we should
1237                          * finish it and free the command structure.
1238                          */
1239                         if (cur_cd->command)
1240                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1241                                         cur_cd->command, COMP_CMD_STOP);
1242
1243                         /* get cycle state from the origin command trb */
1244                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1245                                 & TRB_CYCLE;
1246
1247                         /* modify the command trb to NO OP command */
1248                         cmd_trb->generic.field[0] = 0;
1249                         cmd_trb->generic.field[1] = 0;
1250                         cmd_trb->generic.field[2] = 0;
1251                         cmd_trb->generic.field[3] = cpu_to_le32(
1252                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1253                         break;
1254                 }
1255         }
1256 }
1257
1258 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1259 {
1260         struct xhci_cd *cur_cd, *next_cd;
1261
1262         if (list_empty(&xhci->cancel_cmd_list))
1263                 return;
1264
1265         list_for_each_entry_safe(cur_cd, next_cd,
1266                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1267                 xhci_cmd_to_noop(xhci, cur_cd);
1268                 list_del(&cur_cd->cancel_cmd_list);
1269                 kfree(cur_cd);
1270         }
1271 }
1272
1273 /*
1274  * traversing the cancel_cmd_list. If the command descriptor according
1275  * to cmd_trb is found, the function free it and return 1, otherwise
1276  * return 0.
1277  */
1278 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1279                 union xhci_trb *cmd_trb)
1280 {
1281         struct xhci_cd *cur_cd, *next_cd;
1282
1283         if (list_empty(&xhci->cancel_cmd_list))
1284                 return 0;
1285
1286         list_for_each_entry_safe(cur_cd, next_cd,
1287                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1288                 if (cur_cd->cmd_trb == cmd_trb) {
1289                         if (cur_cd->command)
1290                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1291                                         cur_cd->command, COMP_CMD_STOP);
1292                         list_del(&cur_cd->cancel_cmd_list);
1293                         kfree(cur_cd);
1294                         return 1;
1295                 }
1296         }
1297
1298         return 0;
1299 }
1300
1301 /*
1302  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1303  * trb pointed by the command ring dequeue pointer is the trb we want to
1304  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1305  * traverse the cancel_cmd_list to trun the all of the commands according
1306  * to command descriptor to NO-OP trb.
1307  */
1308 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1309                 int cmd_trb_comp_code)
1310 {
1311         int cur_trb_is_good = 0;
1312
1313         /* Searching the cmd trb pointed by the command ring dequeue
1314          * pointer in command descriptor list. If it is found, free it.
1315          */
1316         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1317                         xhci->cmd_ring->dequeue);
1318
1319         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1320                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1321         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1322                 /* traversing the cancel_cmd_list and canceling
1323                  * the command according to command descriptor
1324                  */
1325                 xhci_cancel_cmd_in_cd_list(xhci);
1326
1327                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1328                 /*
1329                  * ring command ring doorbell again to restart the
1330                  * command ring
1331                  */
1332                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1333                         xhci_ring_cmd_db(xhci);
1334         }
1335         return cur_trb_is_good;
1336 }
1337
1338 static void handle_cmd_completion(struct xhci_hcd *xhci,
1339                 struct xhci_event_cmd *event)
1340 {
1341         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1342         u64 cmd_dma;
1343         dma_addr_t cmd_dequeue_dma;
1344         struct xhci_input_control_ctx *ctrl_ctx;
1345         struct xhci_virt_device *virt_dev;
1346         unsigned int ep_index;
1347         struct xhci_ring *ep_ring;
1348         unsigned int ep_state;
1349
1350         cmd_dma = le64_to_cpu(event->cmd_trb);
1351         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1352                         xhci->cmd_ring->dequeue);
1353         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1354         if (cmd_dequeue_dma == 0) {
1355                 xhci->error_bitmask |= 1 << 4;
1356                 return;
1357         }
1358         /* Does the DMA address match our internal dequeue pointer address? */
1359         if (cmd_dma != (u64) cmd_dequeue_dma) {
1360                 xhci->error_bitmask |= 1 << 5;
1361                 return;
1362         }
1363
1364         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1365                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1366                 /* If the return value is 0, we think the trb pointed by
1367                  * command ring dequeue pointer is a good trb. The good
1368                  * trb means we don't want to cancel the trb, but it have
1369                  * been stopped by host. So we should handle it normally.
1370                  * Otherwise, driver should invoke inc_deq() and return.
1371                  */
1372                 if (handle_stopped_cmd_ring(xhci,
1373                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1374                         inc_deq(xhci, xhci->cmd_ring, false);
1375                         return;
1376                 }
1377         }
1378
1379         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1380                 & TRB_TYPE_BITMASK) {
1381         case TRB_TYPE(TRB_ENABLE_SLOT):
1382                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1383                         xhci->slot_id = slot_id;
1384                 else
1385                         xhci->slot_id = 0;
1386                 complete(&xhci->addr_dev);
1387                 break;
1388         case TRB_TYPE(TRB_DISABLE_SLOT):
1389                 if (xhci->devs[slot_id]) {
1390                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1391                                 /* Delete default control endpoint resources */
1392                                 xhci_free_device_endpoint_resources(xhci,
1393                                                 xhci->devs[slot_id], true);
1394                         xhci_free_virt_device(xhci, slot_id);
1395                 }
1396                 break;
1397         case TRB_TYPE(TRB_CONFIG_EP):
1398                 virt_dev = xhci->devs[slot_id];
1399                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1400                         break;
1401                 /*
1402                  * Configure endpoint commands can come from the USB core
1403                  * configuration or alt setting changes, or because the HW
1404                  * needed an extra configure endpoint command after a reset
1405                  * endpoint command or streams were being configured.
1406                  * If the command was for a halted endpoint, the xHCI driver
1407                  * is not waiting on the configure endpoint command.
1408                  */
1409                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1410                                 virt_dev->in_ctx);
1411                 /* Input ctx add_flags are the endpoint index plus one */
1412                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1413                 /* A usb_set_interface() call directly after clearing a halted
1414                  * condition may race on this quirky hardware.  Not worth
1415                  * worrying about, since this is prototype hardware.  Not sure
1416                  * if this will work for streams, but streams support was
1417                  * untested on this prototype.
1418                  */
1419                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1420                                 ep_index != (unsigned int) -1 &&
1421                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1422                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1423                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1424                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1425                         if (!(ep_state & EP_HALTED))
1426                                 goto bandwidth_change;
1427                         xhci_dbg(xhci, "Completed config ep cmd - "
1428                                         "last ep index = %d, state = %d\n",
1429                                         ep_index, ep_state);
1430                         /* Clear internal halted state and restart ring(s) */
1431                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1432                                 ~EP_HALTED;
1433                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1434                         break;
1435                 }
1436 bandwidth_change:
1437                 xhci_dbg(xhci, "Completed config ep cmd\n");
1438                 xhci->devs[slot_id]->cmd_status =
1439                         GET_COMP_CODE(le32_to_cpu(event->status));
1440                 complete(&xhci->devs[slot_id]->cmd_completion);
1441                 break;
1442         case TRB_TYPE(TRB_EVAL_CONTEXT):
1443                 virt_dev = xhci->devs[slot_id];
1444                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1445                         break;
1446                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1447                 complete(&xhci->devs[slot_id]->cmd_completion);
1448                 break;
1449         case TRB_TYPE(TRB_ADDR_DEV):
1450                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1451                 complete(&xhci->addr_dev);
1452                 break;
1453         case TRB_TYPE(TRB_STOP_RING):
1454                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1455                 break;
1456         case TRB_TYPE(TRB_SET_DEQ):
1457                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1458                 break;
1459         case TRB_TYPE(TRB_CMD_NOOP):
1460                 break;
1461         case TRB_TYPE(TRB_RESET_EP):
1462                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1463                 break;
1464         case TRB_TYPE(TRB_RESET_DEV):
1465                 xhci_dbg(xhci, "Completed reset device command.\n");
1466                 slot_id = TRB_TO_SLOT_ID(
1467                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1468                 virt_dev = xhci->devs[slot_id];
1469                 if (virt_dev)
1470                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1471                 else
1472                         xhci_warn(xhci, "Reset device command completion "
1473                                         "for disabled slot %u\n", slot_id);
1474                 break;
1475         case TRB_TYPE(TRB_NEC_GET_FW):
1476                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1477                         xhci->error_bitmask |= 1 << 6;
1478                         break;
1479                 }
1480                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1481                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1482                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1483                 break;
1484         default:
1485                 /* Skip over unknown commands on the event ring */
1486                 xhci->error_bitmask |= 1 << 6;
1487                 break;
1488         }
1489         inc_deq(xhci, xhci->cmd_ring, false);
1490 }
1491
1492 static void handle_vendor_event(struct xhci_hcd *xhci,
1493                 union xhci_trb *event)
1494 {
1495         u32 trb_type;
1496
1497         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1498         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1499         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1500                 handle_cmd_completion(xhci, &event->event_cmd);
1501 }
1502
1503 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1504  * port registers -- USB 3.0 and USB 2.0).
1505  *
1506  * Returns a zero-based port number, which is suitable for indexing into each of
1507  * the split roothubs' port arrays and bus state arrays.
1508  * Add one to it in order to call xhci_find_slot_id_by_port.
1509  */
1510 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1511                 struct xhci_hcd *xhci, u32 port_id)
1512 {
1513         unsigned int i;
1514         unsigned int num_similar_speed_ports = 0;
1515
1516         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1517          * and usb2_ports are 0-based indexes.  Count the number of similar
1518          * speed ports, up to 1 port before this port.
1519          */
1520         for (i = 0; i < (port_id - 1); i++) {
1521                 u8 port_speed = xhci->port_array[i];
1522
1523                 /*
1524                  * Skip ports that don't have known speeds, or have duplicate
1525                  * Extended Capabilities port speed entries.
1526                  */
1527                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1528                         continue;
1529
1530                 /*
1531                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1532                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1533                  * matches the device speed, it's a similar speed port.
1534                  */
1535                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1536                         num_similar_speed_ports++;
1537         }
1538         return num_similar_speed_ports;
1539 }
1540
1541 static void handle_port_status(struct xhci_hcd *xhci,
1542                 union xhci_trb *event)
1543 {
1544         struct usb_hcd *hcd;
1545         u32 port_id;
1546         u32 temp, temp1;
1547         int max_ports;
1548         int slot_id;
1549         unsigned int faked_port_index;
1550         u8 major_revision;
1551         struct xhci_bus_state *bus_state;
1552         __le32 __iomem **port_array;
1553         bool bogus_port_status = false;
1554
1555         /* Port status change events always have a successful completion code */
1556         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1557                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1558                 xhci->error_bitmask |= 1 << 8;
1559         }
1560         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1561         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1562
1563         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1564         if ((port_id <= 0) || (port_id > max_ports)) {
1565                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1566                 bogus_port_status = true;
1567                 goto cleanup;
1568         }
1569
1570         /* Figure out which usb_hcd this port is attached to:
1571          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1572          */
1573         major_revision = xhci->port_array[port_id - 1];
1574         if (major_revision == 0) {
1575                 xhci_warn(xhci, "Event for port %u not in "
1576                                 "Extended Capabilities, ignoring.\n",
1577                                 port_id);
1578                 bogus_port_status = true;
1579                 goto cleanup;
1580         }
1581         if (major_revision == DUPLICATE_ENTRY) {
1582                 xhci_warn(xhci, "Event for port %u duplicated in"
1583                                 "Extended Capabilities, ignoring.\n",
1584                                 port_id);
1585                 bogus_port_status = true;
1586                 goto cleanup;
1587         }
1588
1589         /*
1590          * Hardware port IDs reported by a Port Status Change Event include USB
1591          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1592          * resume event, but we first need to translate the hardware port ID
1593          * into the index into the ports on the correct split roothub, and the
1594          * correct bus_state structure.
1595          */
1596         /* Find the right roothub. */
1597         hcd = xhci_to_hcd(xhci);
1598         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1599                 hcd = xhci->shared_hcd;
1600         bus_state = &xhci->bus_state[hcd_index(hcd)];
1601         if (hcd->speed == HCD_USB3)
1602                 port_array = xhci->usb3_ports;
1603         else
1604                 port_array = xhci->usb2_ports;
1605         /* Find the faked port hub number */
1606         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1607                         port_id);
1608
1609         temp = xhci_readl(xhci, port_array[faked_port_index]);
1610         if (hcd->state == HC_STATE_SUSPENDED) {
1611                 xhci_dbg(xhci, "resume root hub\n");
1612                 usb_hcd_resume_root_hub(hcd);
1613         }
1614
1615         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1616                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1617
1618                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1619                 if (!(temp1 & CMD_RUN)) {
1620                         xhci_warn(xhci, "xHC is not running.\n");
1621                         goto cleanup;
1622                 }
1623
1624                 if (DEV_SUPERSPEED(temp)) {
1625                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1626                         xhci_set_link_state(xhci, port_array, faked_port_index,
1627                                                 XDEV_U0);
1628                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1629                                         faked_port_index + 1);
1630                         if (!slot_id) {
1631                                 xhci_dbg(xhci, "slot_id is zero\n");
1632                                 goto cleanup;
1633                         }
1634                         xhci_ring_device(xhci, slot_id);
1635                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1636                         /* Clear PORT_PLC */
1637                         xhci_test_and_clear_bit(xhci, port_array,
1638                                                 faked_port_index, PORT_PLC);
1639                 } else {
1640                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1641                         bus_state->resume_done[faked_port_index] = jiffies +
1642                                 msecs_to_jiffies(20);
1643                         mod_timer(&hcd->rh_timer,
1644                                   bus_state->resume_done[faked_port_index]);
1645                         /* Do the rest in GetPortStatus */
1646                 }
1647         }
1648
1649         if (hcd->speed != HCD_USB3)
1650                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1651                                         PORT_PLC);
1652
1653 cleanup:
1654         /* Update event ring dequeue pointer before dropping the lock */
1655         inc_deq(xhci, xhci->event_ring, true);
1656
1657         /* Don't make the USB core poll the roothub if we got a bad port status
1658          * change event.  Besides, at that point we can't tell which roothub
1659          * (USB 2.0 or USB 3.0) to kick.
1660          */
1661         if (bogus_port_status)
1662                 return;
1663
1664         /*
1665          * xHCI port-status-change events occur when the "or" of all the
1666          * status-change bits in the portsc register changes from 0 to 1.
1667          * New status changes won't cause an event if any other change
1668          * bits are still set.  When an event occurs, switch over to
1669          * polling to avoid losing status changes.
1670          */
1671         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1672         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1673         spin_unlock(&xhci->lock);
1674         /* Pass this up to the core */
1675         usb_hcd_poll_rh_status(hcd);
1676         spin_lock(&xhci->lock);
1677 }
1678
1679 /*
1680  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1681  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1682  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1683  * returns 0.
1684  */
1685 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1686                 union xhci_trb  *start_trb,
1687                 union xhci_trb  *end_trb,
1688                 dma_addr_t      suspect_dma)
1689 {
1690         dma_addr_t start_dma;
1691         dma_addr_t end_seg_dma;
1692         dma_addr_t end_trb_dma;
1693         struct xhci_segment *cur_seg;
1694
1695         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1696         cur_seg = start_seg;
1697
1698         do {
1699                 if (start_dma == 0)
1700                         return NULL;
1701                 /* We may get an event for a Link TRB in the middle of a TD */
1702                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1703                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1704                 /* If the end TRB isn't in this segment, this is set to 0 */
1705                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1706
1707                 if (end_trb_dma > 0) {
1708                         /* The end TRB is in this segment, so suspect should be here */
1709                         if (start_dma <= end_trb_dma) {
1710                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1711                                         return cur_seg;
1712                         } else {
1713                                 /* Case for one segment with
1714                                  * a TD wrapped around to the top
1715                                  */
1716                                 if ((suspect_dma >= start_dma &&
1717                                                         suspect_dma <= end_seg_dma) ||
1718                                                 (suspect_dma >= cur_seg->dma &&
1719                                                  suspect_dma <= end_trb_dma))
1720                                         return cur_seg;
1721                         }
1722                         return NULL;
1723                 } else {
1724                         /* Might still be somewhere in this segment */
1725                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1726                                 return cur_seg;
1727                 }
1728                 cur_seg = cur_seg->next;
1729                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1730         } while (cur_seg != start_seg);
1731
1732         return NULL;
1733 }
1734
1735 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1736                 unsigned int slot_id, unsigned int ep_index,
1737                 unsigned int stream_id,
1738                 struct xhci_td *td, union xhci_trb *event_trb)
1739 {
1740         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1741         ep->ep_state |= EP_HALTED;
1742         ep->stopped_td = td;
1743         ep->stopped_trb = event_trb;
1744         ep->stopped_stream = stream_id;
1745
1746         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1747         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1748
1749         ep->stopped_td = NULL;
1750         ep->stopped_trb = NULL;
1751         ep->stopped_stream = 0;
1752
1753         xhci_ring_cmd_db(xhci);
1754 }
1755
1756 /* Check if an error has halted the endpoint ring.  The class driver will
1757  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1758  * However, a babble and other errors also halt the endpoint ring, and the class
1759  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1760  * Ring Dequeue Pointer command manually.
1761  */
1762 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1763                 struct xhci_ep_ctx *ep_ctx,
1764                 unsigned int trb_comp_code)
1765 {
1766         /* TRB completion codes that may require a manual halt cleanup */
1767         if (trb_comp_code == COMP_TX_ERR ||
1768                         trb_comp_code == COMP_BABBLE ||
1769                         trb_comp_code == COMP_SPLIT_ERR)
1770                 /* The 0.96 spec says a babbling control endpoint
1771                  * is not halted. The 0.96 spec says it is.  Some HW
1772                  * claims to be 0.95 compliant, but it halts the control
1773                  * endpoint anyway.  Check if a babble halted the
1774                  * endpoint.
1775                  */
1776                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1777                     cpu_to_le32(EP_STATE_HALTED))
1778                         return 1;
1779
1780         return 0;
1781 }
1782
1783 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1784 {
1785         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1786                 /* Vendor defined "informational" completion code,
1787                  * treat as not-an-error.
1788                  */
1789                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1790                                 trb_comp_code);
1791                 xhci_dbg(xhci, "Treating code as success.\n");
1792                 return 1;
1793         }
1794         return 0;
1795 }
1796
1797 /*
1798  * Finish the td processing, remove the td from td list;
1799  * Return 1 if the urb can be given back.
1800  */
1801 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1802         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1803         struct xhci_virt_ep *ep, int *status, bool skip)
1804 {
1805         struct xhci_virt_device *xdev;
1806         struct xhci_ring *ep_ring;
1807         unsigned int slot_id;
1808         int ep_index;
1809         struct urb *urb = NULL;
1810         struct xhci_ep_ctx *ep_ctx;
1811         int ret = 0;
1812         struct urb_priv *urb_priv;
1813         u32 trb_comp_code;
1814
1815         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1816         xdev = xhci->devs[slot_id];
1817         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1818         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1819         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1820         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1821
1822         if (skip)
1823                 goto td_cleanup;
1824
1825         if (trb_comp_code == COMP_STOP_INVAL ||
1826                         trb_comp_code == COMP_STOP) {
1827                 /* The Endpoint Stop Command completion will take care of any
1828                  * stopped TDs.  A stopped TD may be restarted, so don't update
1829                  * the ring dequeue pointer or take this TD off any lists yet.
1830                  */
1831                 ep->stopped_td = td;
1832                 ep->stopped_trb = event_trb;
1833                 return 0;
1834         } else {
1835                 if (trb_comp_code == COMP_STALL) {
1836                         /* The transfer is completed from the driver's
1837                          * perspective, but we need to issue a set dequeue
1838                          * command for this stalled endpoint to move the dequeue
1839                          * pointer past the TD.  We can't do that here because
1840                          * the halt condition must be cleared first.  Let the
1841                          * USB class driver clear the stall later.
1842                          */
1843                         ep->stopped_td = td;
1844                         ep->stopped_trb = event_trb;
1845                         ep->stopped_stream = ep_ring->stream_id;
1846                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1847                                         ep_ctx, trb_comp_code)) {
1848                         /* Other types of errors halt the endpoint, but the
1849                          * class driver doesn't call usb_reset_endpoint() unless
1850                          * the error is -EPIPE.  Clear the halted status in the
1851                          * xHCI hardware manually.
1852                          */
1853                         xhci_cleanup_halted_endpoint(xhci,
1854                                         slot_id, ep_index, ep_ring->stream_id,
1855                                         td, event_trb);
1856                 } else {
1857                         /* Update ring dequeue pointer */
1858                         while (ep_ring->dequeue != td->last_trb)
1859                                 inc_deq(xhci, ep_ring, false);
1860                         inc_deq(xhci, ep_ring, false);
1861                 }
1862
1863 td_cleanup:
1864                 /* Clean up the endpoint's TD list */
1865                 urb = td->urb;
1866                 urb_priv = urb->hcpriv;
1867
1868                 /* Do one last check of the actual transfer length.
1869                  * If the host controller said we transferred more data than
1870                  * the buffer length, urb->actual_length will be a very big
1871                  * number (since it's unsigned).  Play it safe and say we didn't
1872                  * transfer anything.
1873                  */
1874                 if (urb->actual_length > urb->transfer_buffer_length) {
1875                         xhci_warn(xhci, "URB transfer length is wrong, "
1876                                         "xHC issue? req. len = %u, "
1877                                         "act. len = %u\n",
1878                                         urb->transfer_buffer_length,
1879                                         urb->actual_length);
1880                         urb->actual_length = 0;
1881                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1882                                 *status = -EREMOTEIO;
1883                         else
1884                                 *status = 0;
1885                 }
1886                 list_del_init(&td->td_list);
1887                 /* Was this TD slated to be cancelled but completed anyway? */
1888                 if (!list_empty(&td->cancelled_td_list))
1889                         list_del_init(&td->cancelled_td_list);
1890
1891                 urb_priv->td_cnt++;
1892                 /* Giveback the urb when all the tds are completed */
1893                 if (urb_priv->td_cnt == urb_priv->length) {
1894                         ret = 1;
1895                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1896                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1897                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1898                                         == 0) {
1899                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1900                                                 usb_amd_quirk_pll_enable();
1901                                 }
1902                         }
1903                 }
1904         }
1905
1906         return ret;
1907 }
1908
1909 /*
1910  * Process control tds, update urb status and actual_length.
1911  */
1912 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1913         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1914         struct xhci_virt_ep *ep, int *status)
1915 {
1916         struct xhci_virt_device *xdev;
1917         struct xhci_ring *ep_ring;
1918         unsigned int slot_id;
1919         int ep_index;
1920         struct xhci_ep_ctx *ep_ctx;
1921         u32 trb_comp_code;
1922
1923         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1924         xdev = xhci->devs[slot_id];
1925         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1926         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1927         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1928         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1929
1930         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1931         switch (trb_comp_code) {
1932         case COMP_SUCCESS:
1933                 if (event_trb == ep_ring->dequeue) {
1934                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1935                                         "without IOC set??\n");
1936                         *status = -ESHUTDOWN;
1937                 } else if (event_trb != td->last_trb) {
1938                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1939                                         "without IOC set??\n");
1940                         *status = -ESHUTDOWN;
1941                 } else {
1942                         *status = 0;
1943                 }
1944                 break;
1945         case COMP_SHORT_TX:
1946                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1947                         *status = -EREMOTEIO;
1948                 else
1949                         *status = 0;
1950                 break;
1951         case COMP_STOP_INVAL:
1952         case COMP_STOP:
1953                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1954         default:
1955                 if (!xhci_requires_manual_halt_cleanup(xhci,
1956                                         ep_ctx, trb_comp_code))
1957                         break;
1958                 xhci_dbg(xhci, "TRB error code %u, "
1959                                 "halted endpoint index = %u\n",
1960                                 trb_comp_code, ep_index);
1961                 /* else fall through */
1962         case COMP_STALL:
1963                 /* Did we transfer part of the data (middle) phase? */
1964                 if (event_trb != ep_ring->dequeue &&
1965                                 event_trb != td->last_trb)
1966                         td->urb->actual_length =
1967                                 td->urb->transfer_buffer_length -
1968                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1969                 else
1970                         td->urb->actual_length = 0;
1971
1972                 xhci_cleanup_halted_endpoint(xhci,
1973                         slot_id, ep_index, 0, td, event_trb);
1974                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1975         }
1976         /*
1977          * Did we transfer any data, despite the errors that might have
1978          * happened?  I.e. did we get past the setup stage?
1979          */
1980         if (event_trb != ep_ring->dequeue) {
1981                 /* The event was for the status stage */
1982                 if (event_trb == td->last_trb) {
1983                         if (td->urb->actual_length != 0) {
1984                                 /* Don't overwrite a previously set error code
1985                                  */
1986                                 if ((*status == -EINPROGRESS || *status == 0) &&
1987                                                 (td->urb->transfer_flags
1988                                                  & URB_SHORT_NOT_OK))
1989                                         /* Did we already see a short data
1990                                          * stage? */
1991                                         *status = -EREMOTEIO;
1992                         } else {
1993                                 td->urb->actual_length =
1994                                         td->urb->transfer_buffer_length;
1995                         }
1996                 } else {
1997                 /* Maybe the event was for the data stage? */
1998                         td->urb->actual_length =
1999                                 td->urb->transfer_buffer_length -
2000                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2001                         xhci_dbg(xhci, "Waiting for status "
2002                                         "stage event\n");
2003                         return 0;
2004                 }
2005         }
2006
2007         return finish_td(xhci, td, event_trb, event, ep, status, false);
2008 }
2009
2010 /*
2011  * Process isochronous tds, update urb packet status and actual_length.
2012  */
2013 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2014         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2015         struct xhci_virt_ep *ep, int *status)
2016 {
2017         struct xhci_ring *ep_ring;
2018         struct urb_priv *urb_priv;
2019         int idx;
2020         int len = 0;
2021         union xhci_trb *cur_trb;
2022         struct xhci_segment *cur_seg;
2023         struct usb_iso_packet_descriptor *frame;
2024         u32 trb_comp_code;
2025         bool skip_td = false;
2026
2027         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2028         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2029         urb_priv = td->urb->hcpriv;
2030         idx = urb_priv->td_cnt;
2031         frame = &td->urb->iso_frame_desc[idx];
2032
2033         /* handle completion code */
2034         switch (trb_comp_code) {
2035         case COMP_SUCCESS:
2036                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2037                         frame->status = 0;
2038                         break;
2039                 }
2040                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2041                         trb_comp_code = COMP_SHORT_TX;
2042         case COMP_SHORT_TX:
2043                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2044                                 -EREMOTEIO : 0;
2045                 break;
2046         case COMP_BW_OVER:
2047                 frame->status = -ECOMM;
2048                 skip_td = true;
2049                 break;
2050         case COMP_BUFF_OVER:
2051         case COMP_BABBLE:
2052                 frame->status = -EOVERFLOW;
2053                 skip_td = true;
2054                 break;
2055         case COMP_DEV_ERR:
2056         case COMP_STALL:
2057         case COMP_TX_ERR:
2058                 frame->status = -EPROTO;
2059                 skip_td = true;
2060                 break;
2061         case COMP_STOP:
2062         case COMP_STOP_INVAL:
2063                 break;
2064         default:
2065                 frame->status = -1;
2066                 break;
2067         }
2068
2069         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2070                 frame->actual_length = frame->length;
2071                 td->urb->actual_length += frame->length;
2072         } else {
2073                 for (cur_trb = ep_ring->dequeue,
2074                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2075                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2076                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2077                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2078                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2079                 }
2080                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2081                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2082
2083                 if (trb_comp_code != COMP_STOP_INVAL) {
2084                         frame->actual_length = len;
2085                         td->urb->actual_length += len;
2086                 }
2087         }
2088
2089         return finish_td(xhci, td, event_trb, event, ep, status, false);
2090 }
2091
2092 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2093                         struct xhci_transfer_event *event,
2094                         struct xhci_virt_ep *ep, int *status)
2095 {
2096         struct xhci_ring *ep_ring;
2097         struct urb_priv *urb_priv;
2098         struct usb_iso_packet_descriptor *frame;
2099         int idx;
2100
2101         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2102         urb_priv = td->urb->hcpriv;
2103         idx = urb_priv->td_cnt;
2104         frame = &td->urb->iso_frame_desc[idx];
2105
2106         /* The transfer is partly done. */
2107         frame->status = -EXDEV;
2108
2109         /* calc actual length */
2110         frame->actual_length = 0;
2111
2112         /* Update ring dequeue pointer */
2113         while (ep_ring->dequeue != td->last_trb)
2114                 inc_deq(xhci, ep_ring, false);
2115         inc_deq(xhci, ep_ring, false);
2116
2117         return finish_td(xhci, td, NULL, event, ep, status, true);
2118 }
2119
2120 /*
2121  * Process bulk and interrupt tds, update urb status and actual_length.
2122  */
2123 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2124         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2125         struct xhci_virt_ep *ep, int *status)
2126 {
2127         struct xhci_ring *ep_ring;
2128         union xhci_trb *cur_trb;
2129         struct xhci_segment *cur_seg;
2130         u32 trb_comp_code;
2131
2132         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2133         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2134
2135         switch (trb_comp_code) {
2136         case COMP_SUCCESS:
2137                 /* Double check that the HW transferred everything. */
2138                 if (event_trb != td->last_trb ||
2139                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2140                         xhci_warn(xhci, "WARN Successful completion "
2141                                         "on short TX\n");
2142                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2143                                 *status = -EREMOTEIO;
2144                         else
2145                                 *status = 0;
2146                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2147                                 trb_comp_code = COMP_SHORT_TX;
2148                 } else {
2149                         *status = 0;
2150                 }
2151                 break;
2152         case COMP_SHORT_TX:
2153                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2154                         *status = -EREMOTEIO;
2155                 else
2156                         *status = 0;
2157                 break;
2158         default:
2159                 /* Others already handled above */
2160                 break;
2161         }
2162         if (trb_comp_code == COMP_SHORT_TX)
2163                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2164                                 "%d bytes untransferred\n",
2165                                 td->urb->ep->desc.bEndpointAddress,
2166                                 td->urb->transfer_buffer_length,
2167                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2168         /* Fast path - was this the last TRB in the TD for this URB? */
2169         if (event_trb == td->last_trb) {
2170                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2171                         td->urb->actual_length =
2172                                 td->urb->transfer_buffer_length -
2173                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2174                         if (td->urb->transfer_buffer_length <
2175                                         td->urb->actual_length) {
2176                                 xhci_warn(xhci, "HC gave bad length "
2177                                                 "of %d bytes left\n",
2178                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2179                                 td->urb->actual_length = 0;
2180                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2181                                         *status = -EREMOTEIO;
2182                                 else
2183                                         *status = 0;
2184                         }
2185                         /* Don't overwrite a previously set error code */
2186                         if (*status == -EINPROGRESS) {
2187                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2188                                         *status = -EREMOTEIO;
2189                                 else
2190                                         *status = 0;
2191                         }
2192                 } else {
2193                         td->urb->actual_length =
2194                                 td->urb->transfer_buffer_length;
2195                         /* Ignore a short packet completion if the
2196                          * untransferred length was zero.
2197                          */
2198                         if (*status == -EREMOTEIO)
2199                                 *status = 0;
2200                 }
2201         } else {
2202                 /* Slow path - walk the list, starting from the dequeue
2203                  * pointer, to get the actual length transferred.
2204                  */
2205                 td->urb->actual_length = 0;
2206                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2207                                 cur_trb != event_trb;
2208                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2209                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2210                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2211                                 td->urb->actual_length +=
2212                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2213                 }
2214                 /* If the ring didn't stop on a Link or No-op TRB, add
2215                  * in the actual bytes transferred from the Normal TRB
2216                  */
2217                 if (trb_comp_code != COMP_STOP_INVAL)
2218                         td->urb->actual_length +=
2219                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2220                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2221         }
2222
2223         return finish_td(xhci, td, event_trb, event, ep, status, false);
2224 }
2225
2226 /*
2227  * If this function returns an error condition, it means it got a Transfer
2228  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2229  * At this point, the host controller is probably hosed and should be reset.
2230  */
2231 static int handle_tx_event(struct xhci_hcd *xhci,
2232                 struct xhci_transfer_event *event)
2233 {
2234         struct xhci_virt_device *xdev;
2235         struct xhci_virt_ep *ep;
2236         struct xhci_ring *ep_ring;
2237         unsigned int slot_id;
2238         int ep_index;
2239         struct xhci_td *td = NULL;
2240         dma_addr_t event_dma;
2241         struct xhci_segment *event_seg;
2242         union xhci_trb *event_trb;
2243         struct urb *urb = NULL;
2244         int status = -EINPROGRESS;
2245         struct urb_priv *urb_priv;
2246         struct xhci_ep_ctx *ep_ctx;
2247         struct list_head *tmp;
2248         u32 trb_comp_code;
2249         int ret = 0;
2250         int td_num = 0;
2251
2252         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2253         xdev = xhci->devs[slot_id];
2254         if (!xdev) {
2255                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2256                 return -ENODEV;
2257         }
2258
2259         /* Endpoint ID is 1 based, our index is zero based */
2260         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2261         ep = &xdev->eps[ep_index];
2262         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2263         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2264         if (!ep_ring ||
2265             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2266             EP_STATE_DISABLED) {
2267                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2268                                 "or incorrect stream ring\n");
2269                 return -ENODEV;
2270         }
2271
2272         /* Count current td numbers if ep->skip is set */
2273         if (ep->skip) {
2274                 list_for_each(tmp, &ep_ring->td_list)
2275                         td_num++;
2276         }
2277
2278         event_dma = le64_to_cpu(event->buffer);
2279         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2280         /* Look for common error cases */
2281         switch (trb_comp_code) {
2282         /* Skip codes that require special handling depending on
2283          * transfer type
2284          */
2285         case COMP_SUCCESS:
2286                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2287                         break;
2288                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2289                         trb_comp_code = COMP_SHORT_TX;
2290                 else
2291                         xhci_warn(xhci, "WARN Successful completion on short TX: "
2292                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2293         case COMP_SHORT_TX:
2294                 break;
2295         case COMP_STOP:
2296                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2297                 break;
2298         case COMP_STOP_INVAL:
2299                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2300                 break;
2301         case COMP_STALL:
2302                 xhci_dbg(xhci, "Stalled endpoint\n");
2303                 ep->ep_state |= EP_HALTED;
2304                 status = -EPIPE;
2305                 break;
2306         case COMP_TRB_ERR:
2307                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2308                 status = -EILSEQ;
2309                 break;
2310         case COMP_SPLIT_ERR:
2311         case COMP_TX_ERR:
2312                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2313                 status = -EPROTO;
2314                 break;
2315         case COMP_BABBLE:
2316                 xhci_dbg(xhci, "Babble error on endpoint\n");
2317                 status = -EOVERFLOW;
2318                 break;
2319         case COMP_DB_ERR:
2320                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2321                 status = -ENOSR;
2322                 break;
2323         case COMP_BW_OVER:
2324                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2325                 break;
2326         case COMP_BUFF_OVER:
2327                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2328                 break;
2329         case COMP_UNDERRUN:
2330                 /*
2331                  * When the Isoch ring is empty, the xHC will generate
2332                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2333                  * Underrun Event for OUT Isoch endpoint.
2334                  */
2335                 xhci_dbg(xhci, "underrun event on endpoint\n");
2336                 if (!list_empty(&ep_ring->td_list))
2337                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2338                                         "still with TDs queued?\n",
2339                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2340                                  ep_index);
2341                 goto cleanup;
2342         case COMP_OVERRUN:
2343                 xhci_dbg(xhci, "overrun event on endpoint\n");
2344                 if (!list_empty(&ep_ring->td_list))
2345                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2346                                         "still with TDs queued?\n",
2347                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2348                                  ep_index);
2349                 goto cleanup;
2350         case COMP_DEV_ERR:
2351                 xhci_warn(xhci, "WARN: detect an incompatible device");
2352                 status = -EPROTO;
2353                 break;
2354         case COMP_MISSED_INT:
2355                 /*
2356                  * When encounter missed service error, one or more isoc tds
2357                  * may be missed by xHC.
2358                  * Set skip flag of the ep_ring; Complete the missed tds as
2359                  * short transfer when process the ep_ring next time.
2360                  */
2361                 ep->skip = true;
2362                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2363                 goto cleanup;
2364         default:
2365                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2366                         status = 0;
2367                         break;
2368                 }
2369                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2370                                 "busted\n");
2371                 goto cleanup;
2372         }
2373
2374         do {
2375                 /* This TRB should be in the TD at the head of this ring's
2376                  * TD list.
2377                  */
2378                 if (list_empty(&ep_ring->td_list)) {
2379                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2380                                         "with no TDs queued?\n",
2381                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2382                                   ep_index);
2383                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2384                                  (le32_to_cpu(event->flags) &
2385                                   TRB_TYPE_BITMASK)>>10);
2386                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2387                         if (ep->skip) {
2388                                 ep->skip = false;
2389                                 xhci_dbg(xhci, "td_list is empty while skip "
2390                                                 "flag set. Clear skip flag.\n");
2391                         }
2392                         ret = 0;
2393                         goto cleanup;
2394                 }
2395
2396                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2397                 if (ep->skip && td_num == 0) {
2398                         ep->skip = false;
2399                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2400                                                 "Clear skip flag.\n");
2401                         ret = 0;
2402                         goto cleanup;
2403                 }
2404
2405                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2406                 if (ep->skip)
2407                         td_num--;
2408
2409                 /* Is this a TRB in the currently executing TD? */
2410                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2411                                 td->last_trb, event_dma);
2412
2413                 /*
2414                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2415                  * is not in the current TD pointed by ep_ring->dequeue because
2416                  * that the hardware dequeue pointer still at the previous TRB
2417                  * of the current TD. The previous TRB maybe a Link TD or the
2418                  * last TRB of the previous TD. The command completion handle
2419                  * will take care the rest.
2420                  */
2421                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2422                         ret = 0;
2423                         goto cleanup;
2424                 }
2425
2426                 if (!event_seg) {
2427                         if (!ep->skip ||
2428                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2429                                 /* Some host controllers give a spurious
2430                                  * successful event after a short transfer.
2431                                  * Ignore it.
2432                                  */
2433                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2434                                                 ep_ring->last_td_was_short) {
2435                                         ep_ring->last_td_was_short = false;
2436                                         ret = 0;
2437                                         goto cleanup;
2438                                 }
2439                                 /* HC is busted, give up! */
2440                                 xhci_err(xhci,
2441                                         "ERROR Transfer event TRB DMA ptr not "
2442                                         "part of current TD\n");
2443                                 return -ESHUTDOWN;
2444                         }
2445
2446                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2447                         goto cleanup;
2448                 }
2449                 if (trb_comp_code == COMP_SHORT_TX)
2450                         ep_ring->last_td_was_short = true;
2451                 else
2452                         ep_ring->last_td_was_short = false;
2453
2454                 if (ep->skip) {
2455                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2456                         ep->skip = false;
2457                 }
2458
2459                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2460                                                 sizeof(*event_trb)];
2461                 /*
2462                  * No-op TRB should not trigger interrupts.
2463                  * If event_trb is a no-op TRB, it means the
2464                  * corresponding TD has been cancelled. Just ignore
2465                  * the TD.
2466                  */
2467                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2468                         xhci_dbg(xhci,
2469                                  "event_trb is a no-op TRB. Skip it\n");
2470                         goto cleanup;
2471                 }
2472
2473                 /* Now update the urb's actual_length and give back to
2474                  * the core
2475                  */
2476                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2477                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2478                                                  &status);
2479                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2480                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2481                                                  &status);
2482                 else
2483                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2484                                                  ep, &status);
2485
2486 cleanup:
2487                 /*
2488                  * Do not update event ring dequeue pointer if ep->skip is set.
2489                  * Will roll back to continue process missed tds.
2490                  */
2491                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2492                         inc_deq(xhci, xhci->event_ring, true);
2493                 }
2494
2495                 if (ret) {
2496                         urb = td->urb;
2497                         urb_priv = urb->hcpriv;
2498                         /* Leave the TD around for the reset endpoint function
2499                          * to use(but only if it's not a control endpoint,
2500                          * since we already queued the Set TR dequeue pointer
2501                          * command for stalled control endpoints).
2502                          */
2503                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2504                                 (trb_comp_code != COMP_STALL &&
2505                                         trb_comp_code != COMP_BABBLE))
2506                                 xhci_urb_free_priv(xhci, urb_priv);
2507                         else
2508                                 kfree(urb_priv);
2509
2510                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2511                         if ((urb->actual_length != urb->transfer_buffer_length &&
2512                                                 (urb->transfer_flags &
2513                                                  URB_SHORT_NOT_OK)) ||
2514                                         (status != 0 &&
2515                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2516                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2517                                                 "expected = %x, status = %d\n",
2518                                                 urb, urb->actual_length,
2519                                                 urb->transfer_buffer_length,
2520                                                 status);
2521                         spin_unlock(&xhci->lock);
2522                         /* EHCI, UHCI, and OHCI always unconditionally set the
2523                          * urb->status of an isochronous endpoint to 0.
2524                          */
2525                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2526                                 status = 0;
2527                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2528                         spin_lock(&xhci->lock);
2529                 }
2530
2531         /*
2532          * If ep->skip is set, it means there are missed tds on the
2533          * endpoint ring need to take care of.
2534          * Process them as short transfer until reach the td pointed by
2535          * the event.
2536          */
2537         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2538
2539         return 0;
2540 }
2541
2542 /*
2543  * This function handles all OS-owned events on the event ring.  It may drop
2544  * xhci->lock between event processing (e.g. to pass up port status changes).
2545  * Returns >0 for "possibly more events to process" (caller should call again),
2546  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2547  */
2548 static int xhci_handle_event(struct xhci_hcd *xhci)
2549 {
2550         union xhci_trb *event;
2551         int update_ptrs = 1;
2552         int ret;
2553
2554         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2555                 xhci->error_bitmask |= 1 << 1;
2556                 return 0;
2557         }
2558
2559         event = xhci->event_ring->dequeue;
2560         /* Does the HC or OS own the TRB? */
2561         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2562             xhci->event_ring->cycle_state) {
2563                 xhci->error_bitmask |= 1 << 2;
2564                 return 0;
2565         }
2566
2567         /*
2568          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2569          * speculative reads of the event's flags/data below.
2570          */
2571         rmb();
2572         /* FIXME: Handle more event types. */
2573         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2574         case TRB_TYPE(TRB_COMPLETION):
2575                 handle_cmd_completion(xhci, &event->event_cmd);
2576                 break;
2577         case TRB_TYPE(TRB_PORT_STATUS):
2578                 handle_port_status(xhci, event);
2579                 update_ptrs = 0;
2580                 break;
2581         case TRB_TYPE(TRB_TRANSFER):
2582                 ret = handle_tx_event(xhci, &event->trans_event);
2583                 if (ret < 0)
2584                         xhci->error_bitmask |= 1 << 9;
2585                 else
2586                         update_ptrs = 0;
2587                 break;
2588         default:
2589                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2590                     TRB_TYPE(48))
2591                         handle_vendor_event(xhci, event);
2592                 else
2593                         xhci->error_bitmask |= 1 << 3;
2594         }
2595         /* Any of the above functions may drop and re-acquire the lock, so check
2596          * to make sure a watchdog timer didn't mark the host as non-responsive.
2597          */
2598         if (xhci->xhc_state & XHCI_STATE_DYING) {
2599                 xhci_dbg(xhci, "xHCI host dying, returning from "
2600                                 "event handler.\n");
2601                 return 0;
2602         }
2603
2604         if (update_ptrs)
2605                 /* Update SW event ring dequeue pointer */
2606                 inc_deq(xhci, xhci->event_ring, true);
2607
2608         /* Are there more items on the event ring?  Caller will call us again to
2609          * check.
2610          */
2611         return 1;
2612 }
2613
2614 /*
2615  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2616  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2617  * indicators of an event TRB error, but we check the status *first* to be safe.
2618  */
2619 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2620 {
2621         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2622         u32 status;
2623         union xhci_trb *trb;
2624         u64 temp_64;
2625         union xhci_trb *event_ring_deq;
2626         dma_addr_t deq;
2627
2628         spin_lock(&xhci->lock);
2629         trb = xhci->event_ring->dequeue;
2630         /* Check if the xHC generated the interrupt, or the irq is shared */
2631         status = xhci_readl(xhci, &xhci->op_regs->status);
2632         if (status == 0xffffffff)
2633                 goto hw_died;
2634
2635         if (!(status & STS_EINT)) {
2636                 spin_unlock(&xhci->lock);
2637                 return IRQ_NONE;
2638         }
2639         if (status & STS_FATAL) {
2640                 xhci_warn(xhci, "WARNING: Host System Error\n");
2641                 xhci_halt(xhci);
2642 hw_died:
2643                 spin_unlock(&xhci->lock);
2644                 return -ESHUTDOWN;
2645         }
2646
2647         /*
2648          * Clear the op reg interrupt status first,
2649          * so we can receive interrupts from other MSI-X interrupters.
2650          * Write 1 to clear the interrupt status.
2651          */
2652         status |= STS_EINT;
2653         xhci_writel(xhci, status, &xhci->op_regs->status);
2654         /* FIXME when MSI-X is supported and there are multiple vectors */
2655         /* Clear the MSI-X event interrupt status */
2656
2657         if (hcd->irq != -1) {
2658                 u32 irq_pending;
2659                 /* Acknowledge the PCI interrupt */
2660                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2661                 irq_pending |= IMAN_IP;
2662                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2663         }
2664
2665         if (xhci->xhc_state & XHCI_STATE_DYING) {
2666                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2667                                 "Shouldn't IRQs be disabled?\n");
2668                 /* Clear the event handler busy flag (RW1C);
2669                  * the event ring should be empty.
2670                  */
2671                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2672                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2673                                 &xhci->ir_set->erst_dequeue);
2674                 spin_unlock(&xhci->lock);
2675
2676                 return IRQ_HANDLED;
2677         }
2678
2679         event_ring_deq = xhci->event_ring->dequeue;
2680         /* FIXME this should be a delayed service routine
2681          * that clears the EHB.
2682          */
2683         while (xhci_handle_event(xhci) > 0) {}
2684
2685         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2686         /* If necessary, update the HW's version of the event ring deq ptr. */
2687         if (event_ring_deq != xhci->event_ring->dequeue) {
2688                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2689                                 xhci->event_ring->dequeue);
2690                 if (deq == 0)
2691                         xhci_warn(xhci, "WARN something wrong with SW event "
2692                                         "ring dequeue ptr.\n");
2693                 /* Update HC event ring dequeue pointer */
2694                 temp_64 &= ERST_PTR_MASK;
2695                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2696         }
2697
2698         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2699         temp_64 |= ERST_EHB;
2700         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2701
2702         spin_unlock(&xhci->lock);
2703
2704         return IRQ_HANDLED;
2705 }
2706
2707 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2708 {
2709         irqreturn_t ret;
2710         struct xhci_hcd *xhci;
2711
2712         xhci = hcd_to_xhci(hcd);
2713         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2714         if (xhci->shared_hcd)
2715                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2716
2717         ret = xhci_irq(hcd);
2718
2719         return ret;
2720 }
2721
2722 /****           Endpoint Ring Operations        ****/
2723
2724 /*
2725  * Generic function for queueing a TRB on a ring.
2726  * The caller must have checked to make sure there's room on the ring.
2727  *
2728  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2729  *                      prepare_transfer()?
2730  */
2731 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2732                 bool consumer, bool more_trbs_coming, bool isoc,
2733                 u32 field1, u32 field2, u32 field3, u32 field4)
2734 {
2735         struct xhci_generic_trb *trb;
2736
2737         trb = &ring->enqueue->generic;
2738         trb->field[0] = cpu_to_le32(field1);
2739         trb->field[1] = cpu_to_le32(field2);
2740         trb->field[2] = cpu_to_le32(field3);
2741         trb->field[3] = cpu_to_le32(field4);
2742         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2743 }
2744
2745 /*
2746  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2747  * FIXME allocate segments if the ring is full.
2748  */
2749 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2750                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2751 {
2752         /* Make sure the endpoint has been added to xHC schedule */
2753         switch (ep_state) {
2754         case EP_STATE_DISABLED:
2755                 /*
2756                  * USB core changed config/interfaces without notifying us,
2757                  * or hardware is reporting the wrong state.
2758                  */
2759                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2760                 return -ENOENT;
2761         case EP_STATE_ERROR:
2762                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2763                 /* FIXME event handling code for error needs to clear it */
2764                 /* XXX not sure if this should be -ENOENT or not */
2765                 return -EINVAL;
2766         case EP_STATE_HALTED:
2767                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2768         case EP_STATE_STOPPED:
2769         case EP_STATE_RUNNING:
2770                 break;
2771         default:
2772                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2773                 /*
2774                  * FIXME issue Configure Endpoint command to try to get the HC
2775                  * back into a known state.
2776                  */
2777                 return -EINVAL;
2778         }
2779         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2780                 /* FIXME allocate more room */
2781                 xhci_err(xhci, "ERROR no room on ep ring\n");
2782                 return -ENOMEM;
2783         }
2784
2785         if (enqueue_is_link_trb(ep_ring)) {
2786                 struct xhci_ring *ring = ep_ring;
2787                 union xhci_trb *next;
2788
2789                 next = ring->enqueue;
2790
2791                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2792                         /* If we're not dealing with 0.95 hardware or isoc rings
2793                          * on AMD 0.96 host, clear the chain bit.
2794                          */
2795                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2796                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2797                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2798                         else
2799                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2800
2801                         wmb();
2802                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2803
2804                         /* Toggle the cycle bit after the last ring segment. */
2805                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2806                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2807                                 if (!in_interrupt()) {
2808                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2809                                                 "state for ring %p = %i\n",
2810                                                 ring, (unsigned int)ring->cycle_state);
2811                                 }
2812                         }
2813                         ring->enq_seg = ring->enq_seg->next;
2814                         ring->enqueue = ring->enq_seg->trbs;
2815                         next = ring->enqueue;
2816                 }
2817         }
2818
2819         return 0;
2820 }
2821
2822 static int prepare_transfer(struct xhci_hcd *xhci,
2823                 struct xhci_virt_device *xdev,
2824                 unsigned int ep_index,
2825                 unsigned int stream_id,
2826                 unsigned int num_trbs,
2827                 struct urb *urb,
2828                 unsigned int td_index,
2829                 bool isoc,
2830                 gfp_t mem_flags)
2831 {
2832         int ret;
2833         struct urb_priv *urb_priv;
2834         struct xhci_td  *td;
2835         struct xhci_ring *ep_ring;
2836         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2837
2838         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2839         if (!ep_ring) {
2840                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2841                                 stream_id);
2842                 return -EINVAL;
2843         }
2844
2845         ret = prepare_ring(xhci, ep_ring,
2846                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2847                            num_trbs, isoc, mem_flags);
2848         if (ret)
2849                 return ret;
2850
2851         urb_priv = urb->hcpriv;
2852         td = urb_priv->td[td_index];
2853
2854         INIT_LIST_HEAD(&td->td_list);
2855         INIT_LIST_HEAD(&td->cancelled_td_list);
2856
2857         if (td_index == 0) {
2858                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2859                 if (unlikely(ret))
2860                         return ret;
2861         }
2862
2863         td->urb = urb;
2864         /* Add this TD to the tail of the endpoint ring's TD list */
2865         list_add_tail(&td->td_list, &ep_ring->td_list);
2866         td->start_seg = ep_ring->enq_seg;
2867         td->first_trb = ep_ring->enqueue;
2868
2869         urb_priv->td[td_index] = td;
2870
2871         return 0;
2872 }
2873
2874 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2875 {
2876         int num_sgs, num_trbs, running_total, temp, i;
2877         struct scatterlist *sg;
2878
2879         sg = NULL;
2880         num_sgs = urb->num_mapped_sgs;
2881         temp = urb->transfer_buffer_length;
2882
2883         xhci_dbg(xhci, "count sg list trbs: \n");
2884         num_trbs = 0;
2885         for_each_sg(urb->sg, sg, num_sgs, i) {
2886                 unsigned int previous_total_trbs = num_trbs;
2887                 unsigned int len = sg_dma_len(sg);
2888
2889                 /* Scatter gather list entries may cross 64KB boundaries */
2890                 running_total = TRB_MAX_BUFF_SIZE -
2891                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2892                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2893                 if (running_total != 0)
2894                         num_trbs++;
2895
2896                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2897                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2898                         num_trbs++;
2899                         running_total += TRB_MAX_BUFF_SIZE;
2900                 }
2901                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2902                                 i, (unsigned long long)sg_dma_address(sg),
2903                                 len, len, num_trbs - previous_total_trbs);
2904
2905                 len = min_t(int, len, temp);
2906                 temp -= len;
2907                 if (temp == 0)
2908                         break;
2909         }
2910         xhci_dbg(xhci, "\n");
2911         if (!in_interrupt())
2912                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2913                                 "num_trbs = %d\n",
2914                                 urb->ep->desc.bEndpointAddress,
2915                                 urb->transfer_buffer_length,
2916                                 num_trbs);
2917         return num_trbs;
2918 }
2919
2920 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2921 {
2922         if (num_trbs != 0)
2923                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2924                                 "TRBs, %d left\n", __func__,
2925                                 urb->ep->desc.bEndpointAddress, num_trbs);
2926         if (running_total != urb->transfer_buffer_length)
2927                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2928                                 "queued %#x (%d), asked for %#x (%d)\n",
2929                                 __func__,
2930                                 urb->ep->desc.bEndpointAddress,
2931                                 running_total, running_total,
2932                                 urb->transfer_buffer_length,
2933                                 urb->transfer_buffer_length);
2934 }
2935
2936 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2937                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2938                 struct xhci_generic_trb *start_trb)
2939 {
2940         /*
2941          * Pass all the TRBs to the hardware at once and make sure this write
2942          * isn't reordered.
2943          */
2944         wmb();
2945         if (start_cycle)
2946                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2947         else
2948                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2949         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2950 }
2951
2952 /*
2953  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2954  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2955  * (comprised of sg list entries) can take several service intervals to
2956  * transmit.
2957  */
2958 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2959                 struct urb *urb, int slot_id, unsigned int ep_index)
2960 {
2961         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2962                         xhci->devs[slot_id]->out_ctx, ep_index);
2963         int xhci_interval;
2964         int ep_interval;
2965
2966         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2967         ep_interval = urb->interval;
2968         /* Convert to microframes */
2969         if (urb->dev->speed == USB_SPEED_LOW ||
2970                         urb->dev->speed == USB_SPEED_FULL)
2971                 ep_interval *= 8;
2972         /* FIXME change this to a warning and a suggestion to use the new API
2973          * to set the polling interval (once the API is added).
2974          */
2975         if (xhci_interval != ep_interval) {
2976                 if (printk_ratelimit())
2977                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2978                                         " (%d microframe%s) than xHCI "
2979                                         "(%d microframe%s)\n",
2980                                         ep_interval,
2981                                         ep_interval == 1 ? "" : "s",
2982                                         xhci_interval,
2983                                         xhci_interval == 1 ? "" : "s");
2984                 urb->interval = xhci_interval;
2985                 /* Convert back to frames for LS/FS devices */
2986                 if (urb->dev->speed == USB_SPEED_LOW ||
2987                                 urb->dev->speed == USB_SPEED_FULL)
2988                         urb->interval /= 8;
2989         }
2990         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2991 }
2992
2993 /*
2994  * The TD size is the number of bytes remaining in the TD (including this TRB),
2995  * right shifted by 10.
2996  * It must fit in bits 21:17, so it can't be bigger than 31.
2997  */
2998 static u32 xhci_td_remainder(unsigned int remainder)
2999 {
3000         u32 max = (1 << (21 - 17 + 1)) - 1;
3001
3002         if ((remainder >> 10) >= max)
3003                 return max << 17;
3004         else
3005                 return (remainder >> 10) << 17;
3006 }
3007
3008 /*
3009  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3010  * packets remaining in the TD (*not* including this TRB).
3011  *
3012  * Total TD packet count = total_packet_count =
3013  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3014  *
3015  * Packets transferred up to and including this TRB = packets_transferred =
3016  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3017  *
3018  * TD size = total_packet_count - packets_transferred
3019  *
3020  * It must fit in bits 21:17, so it can't be bigger than 31.
3021  * The last TRB in a TD must have the TD size set to zero.
3022  */
3023 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3024                 unsigned int total_packet_count, struct urb *urb,
3025                 unsigned int num_trbs_left)
3026 {
3027         int packets_transferred;
3028
3029         /* One TRB with a zero-length data packet. */
3030         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3031                 return 0;
3032
3033         /* All the TRB queueing functions don't count the current TRB in
3034          * running_total.
3035          */
3036         packets_transferred = (running_total + trb_buff_len) /
3037                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3038
3039         if ((total_packet_count - packets_transferred) > 31)
3040                 return 31 << 17;
3041         return (total_packet_count - packets_transferred) << 17;
3042 }
3043
3044 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3045                 struct urb *urb, int slot_id, unsigned int ep_index)
3046 {
3047         struct xhci_ring *ep_ring;
3048         unsigned int num_trbs;
3049         struct urb_priv *urb_priv;
3050         struct xhci_td *td;
3051         struct scatterlist *sg;
3052         int num_sgs;
3053         int trb_buff_len, this_sg_len, running_total;
3054         unsigned int total_packet_count;
3055         bool first_trb;
3056         u64 addr;
3057         bool more_trbs_coming;
3058
3059         struct xhci_generic_trb *start_trb;
3060         int start_cycle;
3061
3062         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3063         if (!ep_ring)
3064                 return -EINVAL;
3065
3066         num_trbs = count_sg_trbs_needed(xhci, urb);
3067         num_sgs = urb->num_mapped_sgs;
3068         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3069                         usb_endpoint_maxp(&urb->ep->desc));
3070
3071         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3072                         ep_index, urb->stream_id,
3073                         num_trbs, urb, 0, false, mem_flags);
3074         if (trb_buff_len < 0)
3075                 return trb_buff_len;
3076
3077         urb_priv = urb->hcpriv;
3078         td = urb_priv->td[0];
3079
3080         /*
3081          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3082          * until we've finished creating all the other TRBs.  The ring's cycle
3083          * state may change as we enqueue the other TRBs, so save it too.
3084          */
3085         start_trb = &ep_ring->enqueue->generic;
3086         start_cycle = ep_ring->cycle_state;
3087
3088         running_total = 0;
3089         /*
3090          * How much data is in the first TRB?
3091          *
3092          * There are three forces at work for TRB buffer pointers and lengths:
3093          * 1. We don't want to walk off the end of this sg-list entry buffer.
3094          * 2. The transfer length that the driver requested may be smaller than
3095          *    the amount of memory allocated for this scatter-gather list.
3096          * 3. TRBs buffers can't cross 64KB boundaries.
3097          */
3098         sg = urb->sg;
3099         addr = (u64) sg_dma_address(sg);
3100         this_sg_len = sg_dma_len(sg);
3101         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3102         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3103         if (trb_buff_len > urb->transfer_buffer_length)
3104                 trb_buff_len = urb->transfer_buffer_length;
3105         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3106                         trb_buff_len);
3107
3108         first_trb = true;
3109         /* Queue the first TRB, even if it's zero-length */
3110         do {
3111                 u32 field = 0;
3112                 u32 length_field = 0;
3113                 u32 remainder = 0;
3114
3115                 /* Don't change the cycle bit of the first TRB until later */
3116                 if (first_trb) {
3117                         first_trb = false;
3118                         if (start_cycle == 0)
3119                                 field |= 0x1;
3120                 } else
3121                         field |= ep_ring->cycle_state;
3122
3123                 /* Chain all the TRBs together; clear the chain bit in the last
3124                  * TRB to indicate it's the last TRB in the chain.
3125                  */
3126                 if (num_trbs > 1) {
3127                         field |= TRB_CHAIN;
3128                 } else {
3129                         /* FIXME - add check for ZERO_PACKET flag before this */
3130                         td->last_trb = ep_ring->enqueue;
3131                         field |= TRB_IOC;
3132                 }
3133
3134                 /* Only set interrupt on short packet for IN endpoints */
3135                 if (usb_urb_dir_in(urb))
3136                         field |= TRB_ISP;
3137
3138                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3139                                 "64KB boundary at %#x, end dma = %#x\n",
3140                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
3141                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3142                                 (unsigned int) addr + trb_buff_len);
3143                 if (TRB_MAX_BUFF_SIZE -
3144                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3145                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3146                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3147                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3148                                         (unsigned int) addr + trb_buff_len);
3149                 }
3150
3151                 /* Set the TRB length, TD size, and interrupter fields. */
3152                 if (xhci->hci_version < 0x100) {
3153                         remainder = xhci_td_remainder(
3154                                         urb->transfer_buffer_length -
3155                                         running_total);
3156                 } else {
3157                         remainder = xhci_v1_0_td_remainder(running_total,
3158                                         trb_buff_len, total_packet_count, urb,
3159                                         num_trbs - 1);
3160                 }
3161                 length_field = TRB_LEN(trb_buff_len) |
3162                         remainder |
3163                         TRB_INTR_TARGET(0);
3164
3165                 if (num_trbs > 1)
3166                         more_trbs_coming = true;
3167                 else
3168                         more_trbs_coming = false;
3169                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3170                                 lower_32_bits(addr),
3171                                 upper_32_bits(addr),
3172                                 length_field,
3173                                 field | TRB_TYPE(TRB_NORMAL));
3174                 --num_trbs;
3175                 running_total += trb_buff_len;
3176
3177                 /* Calculate length for next transfer --
3178                  * Are we done queueing all the TRBs for this sg entry?
3179                  */
3180                 this_sg_len -= trb_buff_len;
3181                 if (this_sg_len == 0) {
3182                         --num_sgs;
3183                         if (num_sgs == 0)
3184                                 break;
3185                         sg = sg_next(sg);
3186                         addr = (u64) sg_dma_address(sg);
3187                         this_sg_len = sg_dma_len(sg);
3188                 } else {
3189                         addr += trb_buff_len;
3190                 }
3191
3192                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3193                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3194                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3195                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3196                         trb_buff_len =
3197                                 urb->transfer_buffer_length - running_total;
3198         } while (running_total < urb->transfer_buffer_length);
3199
3200         check_trb_math(urb, num_trbs, running_total);
3201         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3202                         start_cycle, start_trb);
3203         return 0;
3204 }
3205
3206 /* This is very similar to what ehci-q.c qtd_fill() does */
3207 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3208                 struct urb *urb, int slot_id, unsigned int ep_index)
3209 {
3210         struct xhci_ring *ep_ring;
3211         struct urb_priv *urb_priv;
3212         struct xhci_td *td;
3213         int num_trbs;
3214         struct xhci_generic_trb *start_trb;
3215         bool first_trb;
3216         bool more_trbs_coming;
3217         int start_cycle;
3218         u32 field, length_field;
3219
3220         int running_total, trb_buff_len, ret;
3221         unsigned int total_packet_count;
3222         u64 addr;
3223
3224         if (urb->num_sgs)
3225                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3226
3227         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3228         if (!ep_ring)
3229                 return -EINVAL;
3230
3231         num_trbs = 0;
3232         /* How much data is (potentially) left before the 64KB boundary? */
3233         running_total = TRB_MAX_BUFF_SIZE -
3234                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3235         running_total &= TRB_MAX_BUFF_SIZE - 1;
3236
3237         /* If there's some data on this 64KB chunk, or we have to send a
3238          * zero-length transfer, we need at least one TRB
3239          */
3240         if (running_total != 0 || urb->transfer_buffer_length == 0)
3241                 num_trbs++;
3242         /* How many more 64KB chunks to transfer, how many more TRBs? */
3243         while (running_total < urb->transfer_buffer_length) {
3244                 num_trbs++;
3245                 running_total += TRB_MAX_BUFF_SIZE;
3246         }
3247         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3248
3249         if (!in_interrupt())
3250                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3251                                 "addr = %#llx, num_trbs = %d\n",
3252                                 urb->ep->desc.bEndpointAddress,
3253                                 urb->transfer_buffer_length,
3254                                 urb->transfer_buffer_length,
3255                                 (unsigned long long)urb->transfer_dma,
3256                                 num_trbs);
3257
3258         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3259                         ep_index, urb->stream_id,
3260                         num_trbs, urb, 0, false, mem_flags);
3261         if (ret < 0)
3262                 return ret;
3263
3264         urb_priv = urb->hcpriv;
3265         td = urb_priv->td[0];
3266
3267         /*
3268          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3269          * until we've finished creating all the other TRBs.  The ring's cycle
3270          * state may change as we enqueue the other TRBs, so save it too.
3271          */
3272         start_trb = &ep_ring->enqueue->generic;
3273         start_cycle = ep_ring->cycle_state;
3274
3275         running_total = 0;
3276         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3277                         usb_endpoint_maxp(&urb->ep->desc));
3278         /* How much data is in the first TRB? */
3279         addr = (u64) urb->transfer_dma;
3280         trb_buff_len = TRB_MAX_BUFF_SIZE -
3281                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3282         if (trb_buff_len > urb->transfer_buffer_length)
3283                 trb_buff_len = urb->transfer_buffer_length;
3284
3285         first_trb = true;
3286
3287         /* Queue the first TRB, even if it's zero-length */
3288         do {
3289                 u32 remainder = 0;
3290                 field = 0;
3291
3292                 /* Don't change the cycle bit of the first TRB until later */
3293                 if (first_trb) {
3294                         first_trb = false;
3295                         if (start_cycle == 0)
3296                                 field |= 0x1;
3297                 } else
3298                         field |= ep_ring->cycle_state;
3299
3300                 /* Chain all the TRBs together; clear the chain bit in the last
3301                  * TRB to indicate it's the last TRB in the chain.
3302                  */
3303                 if (num_trbs > 1) {
3304                         field |= TRB_CHAIN;
3305                 } else {
3306                         /* FIXME - add check for ZERO_PACKET flag before this */
3307                         td->last_trb = ep_ring->enqueue;
3308                         field |= TRB_IOC;
3309                 }
3310
3311                 /* Only set interrupt on short packet for IN endpoints */
3312                 if (usb_urb_dir_in(urb))
3313                         field |= TRB_ISP;
3314
3315                 /* Set the TRB length, TD size, and interrupter fields. */
3316                 if (xhci->hci_version < 0x100) {
3317                         remainder = xhci_td_remainder(
3318                                         urb->transfer_buffer_length -
3319                                         running_total);
3320                 } else {
3321                         remainder = xhci_v1_0_td_remainder(running_total,
3322                                         trb_buff_len, total_packet_count, urb,
3323                                         num_trbs - 1);
3324                 }
3325                 length_field = TRB_LEN(trb_buff_len) |
3326                         remainder |
3327                         TRB_INTR_TARGET(0);
3328
3329                 if (num_trbs > 1)
3330                         more_trbs_coming = true;
3331                 else
3332                         more_trbs_coming = false;
3333                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3334                                 lower_32_bits(addr),
3335                                 upper_32_bits(addr),
3336                                 length_field,
3337                                 field | TRB_TYPE(TRB_NORMAL));
3338                 --num_trbs;
3339                 running_total += trb_buff_len;
3340
3341                 /* Calculate length for next transfer */
3342                 addr += trb_buff_len;
3343                 trb_buff_len = urb->transfer_buffer_length - running_total;
3344                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3345                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3346         } while (running_total < urb->transfer_buffer_length);
3347
3348         check_trb_math(urb, num_trbs, running_total);
3349         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3350                         start_cycle, start_trb);
3351         return 0;
3352 }
3353
3354 /* Caller must have locked xhci->lock */
3355 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3356                 struct urb *urb, int slot_id, unsigned int ep_index)
3357 {
3358         struct xhci_ring *ep_ring;
3359         int num_trbs;
3360         int ret;
3361         struct usb_ctrlrequest *setup;
3362         struct xhci_generic_trb *start_trb;
3363         int start_cycle;
3364         u32 field, length_field;
3365         struct urb_priv *urb_priv;
3366         struct xhci_td *td;
3367
3368         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3369         if (!ep_ring)
3370                 return -EINVAL;
3371
3372         /*
3373          * Need to copy setup packet into setup TRB, so we can't use the setup
3374          * DMA address.
3375          */
3376         if (!urb->setup_packet)
3377                 return -EINVAL;
3378
3379         if (!in_interrupt())
3380                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3381                                 slot_id, ep_index);
3382         /* 1 TRB for setup, 1 for status */
3383         num_trbs = 2;
3384         /*
3385          * Don't need to check if we need additional event data and normal TRBs,
3386          * since data in control transfers will never get bigger than 16MB
3387          * XXX: can we get a buffer that crosses 64KB boundaries?
3388          */
3389         if (urb->transfer_buffer_length > 0)
3390                 num_trbs++;
3391         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3392                         ep_index, urb->stream_id,
3393                         num_trbs, urb, 0, false, mem_flags);
3394         if (ret < 0)
3395                 return ret;
3396
3397         urb_priv = urb->hcpriv;
3398         td = urb_priv->td[0];
3399
3400         /*
3401          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3402          * until we've finished creating all the other TRBs.  The ring's cycle
3403          * state may change as we enqueue the other TRBs, so save it too.
3404          */
3405         start_trb = &ep_ring->enqueue->generic;
3406         start_cycle = ep_ring->cycle_state;
3407
3408         /* Queue setup TRB - see section 6.4.1.2.1 */
3409         /* FIXME better way to translate setup_packet into two u32 fields? */
3410         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3411         field = 0;
3412         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3413         if (start_cycle == 0)
3414                 field |= 0x1;
3415
3416         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3417         if (xhci->hci_version == 0x100) {
3418                 if (urb->transfer_buffer_length > 0) {
3419                         if (setup->bRequestType & USB_DIR_IN)
3420                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3421                         else
3422                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3423                 }
3424         }
3425
3426         queue_trb(xhci, ep_ring, false, true, false,
3427                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3428                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3429                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3430                   /* Immediate data in pointer */
3431                   field);
3432
3433         /* If there's data, queue data TRBs */
3434         /* Only set interrupt on short packet for IN endpoints */
3435         if (usb_urb_dir_in(urb))
3436                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3437         else
3438                 field = TRB_TYPE(TRB_DATA);
3439
3440         length_field = TRB_LEN(urb->transfer_buffer_length) |
3441                 xhci_td_remainder(urb->transfer_buffer_length) |
3442                 TRB_INTR_TARGET(0);
3443         if (urb->transfer_buffer_length > 0) {
3444                 if (setup->bRequestType & USB_DIR_IN)
3445                         field |= TRB_DIR_IN;
3446                 queue_trb(xhci, ep_ring, false, true, false,
3447                                 lower_32_bits(urb->transfer_dma),
3448                                 upper_32_bits(urb->transfer_dma),
3449                                 length_field,
3450                                 field | ep_ring->cycle_state);
3451         }
3452
3453         /* Save the DMA address of the last TRB in the TD */
3454         td->last_trb = ep_ring->enqueue;
3455
3456         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3457         /* If the device sent data, the status stage is an OUT transfer */
3458         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3459                 field = 0;
3460         else
3461                 field = TRB_DIR_IN;
3462         queue_trb(xhci, ep_ring, false, false, false,
3463                         0,
3464                         0,
3465                         TRB_INTR_TARGET(0),
3466                         /* Event on completion */
3467                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3468
3469         giveback_first_trb(xhci, slot_id, ep_index, 0,
3470                         start_cycle, start_trb);
3471         return 0;
3472 }
3473
3474 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3475                 struct urb *urb, int i)
3476 {
3477         int num_trbs = 0;
3478         u64 addr, td_len;
3479
3480         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3481         td_len = urb->iso_frame_desc[i].length;
3482
3483         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3484                         TRB_MAX_BUFF_SIZE);
3485         if (num_trbs == 0)
3486                 num_trbs++;
3487
3488         return num_trbs;
3489 }
3490
3491 /*
3492  * The transfer burst count field of the isochronous TRB defines the number of
3493  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3494  * devices can burst up to bMaxBurst number of packets per service interval.
3495  * This field is zero based, meaning a value of zero in the field means one
3496  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3497  * zero.  Only xHCI 1.0 host controllers support this field.
3498  */
3499 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3500                 struct usb_device *udev,
3501                 struct urb *urb, unsigned int total_packet_count)
3502 {
3503         unsigned int max_burst;
3504
3505         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3506                 return 0;
3507
3508         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3509         return roundup(total_packet_count, max_burst + 1) - 1;
3510 }
3511
3512 /*
3513  * Returns the number of packets in the last "burst" of packets.  This field is
3514  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3515  * the last burst packet count is equal to the total number of packets in the
3516  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3517  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3518  * contain 1 to (bMaxBurst + 1) packets.
3519  */
3520 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3521                 struct usb_device *udev,
3522                 struct urb *urb, unsigned int total_packet_count)
3523 {
3524         unsigned int max_burst;
3525         unsigned int residue;
3526
3527         if (xhci->hci_version < 0x100)
3528                 return 0;
3529
3530         switch (udev->speed) {
3531         case USB_SPEED_SUPER:
3532                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3533                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3534                 residue = total_packet_count % (max_burst + 1);
3535                 /* If residue is zero, the last burst contains (max_burst + 1)
3536                  * number of packets, but the TLBPC field is zero-based.
3537                  */
3538                 if (residue == 0)
3539                         return max_burst;
3540                 return residue - 1;
3541         default:
3542                 if (total_packet_count == 0)
3543                         return 0;
3544                 return total_packet_count - 1;
3545         }
3546 }
3547
3548 /* This is for isoc transfer */
3549 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3550                 struct urb *urb, int slot_id, unsigned int ep_index)
3551 {
3552         struct xhci_ring *ep_ring;
3553         struct urb_priv *urb_priv;
3554         struct xhci_td *td;
3555         int num_tds, trbs_per_td;
3556         struct xhci_generic_trb *start_trb;
3557         bool first_trb;
3558         int start_cycle;
3559         u32 field, length_field;
3560         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3561         u64 start_addr, addr;
3562         int i, j;
3563         bool more_trbs_coming;
3564
3565         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3566
3567         num_tds = urb->number_of_packets;
3568         if (num_tds < 1) {
3569                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3570                 return -EINVAL;
3571         }
3572
3573         if (!in_interrupt())
3574                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3575                                 " addr = %#llx, num_tds = %d\n",
3576                                 urb->ep->desc.bEndpointAddress,
3577                                 urb->transfer_buffer_length,
3578                                 urb->transfer_buffer_length,
3579                                 (unsigned long long)urb->transfer_dma,
3580                                 num_tds);
3581
3582         start_addr = (u64) urb->transfer_dma;
3583         start_trb = &ep_ring->enqueue->generic;
3584         start_cycle = ep_ring->cycle_state;
3585
3586         urb_priv = urb->hcpriv;
3587         /* Queue the first TRB, even if it's zero-length */
3588         for (i = 0; i < num_tds; i++) {
3589                 unsigned int total_packet_count;
3590                 unsigned int burst_count;
3591                 unsigned int residue;
3592
3593                 first_trb = true;
3594                 running_total = 0;
3595                 addr = start_addr + urb->iso_frame_desc[i].offset;
3596                 td_len = urb->iso_frame_desc[i].length;
3597                 td_remain_len = td_len;
3598                 total_packet_count = DIV_ROUND_UP(td_len,
3599                                 GET_MAX_PACKET(
3600                                         usb_endpoint_maxp(&urb->ep->desc)));
3601                 /* A zero-length transfer still involves at least one packet. */
3602                 if (total_packet_count == 0)
3603                         total_packet_count++;
3604                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3605                                 total_packet_count);
3606                 residue = xhci_get_last_burst_packet_count(xhci,
3607                                 urb->dev, urb, total_packet_count);
3608
3609                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3610
3611                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3612                                 urb->stream_id, trbs_per_td, urb, i, true,
3613                                 mem_flags);
3614                 if (ret < 0) {
3615                         if (i == 0)
3616                                 return ret;
3617                         goto cleanup;
3618                 }
3619
3620                 td = urb_priv->td[i];
3621                 for (j = 0; j < trbs_per_td; j++) {
3622                         u32 remainder = 0;
3623                         field = 0;
3624
3625                         if (first_trb) {
3626                                 field = TRB_TBC(burst_count) |
3627                                         TRB_TLBPC(residue);
3628                                 /* Queue the isoc TRB */
3629                                 field |= TRB_TYPE(TRB_ISOC);
3630                                 /* Assume URB_ISO_ASAP is set */
3631                                 field |= TRB_SIA;
3632                                 if (i == 0) {
3633                                         if (start_cycle == 0)
3634                                                 field |= 0x1;
3635                                 } else
3636                                         field |= ep_ring->cycle_state;
3637                                 first_trb = false;
3638                         } else {
3639                                 /* Queue other normal TRBs */
3640                                 field |= TRB_TYPE(TRB_NORMAL);
3641                                 field |= ep_ring->cycle_state;
3642                         }
3643
3644                         /* Only set interrupt on short packet for IN EPs */
3645                         if (usb_urb_dir_in(urb))
3646                                 field |= TRB_ISP;
3647
3648                         /* Chain all the TRBs together; clear the chain bit in
3649                          * the last TRB to indicate it's the last TRB in the
3650                          * chain.
3651                          */
3652                         if (j < trbs_per_td - 1) {
3653                                 field |= TRB_CHAIN;
3654                                 more_trbs_coming = true;
3655                         } else {
3656                                 td->last_trb = ep_ring->enqueue;
3657                                 field |= TRB_IOC;
3658                                 if (xhci->hci_version == 0x100 &&
3659                                                 !(xhci->quirks &
3660                                                         XHCI_AVOID_BEI)) {
3661                                         /* Set BEI bit except for the last td */
3662                                         if (i < num_tds - 1)
3663                                                 field |= TRB_BEI;
3664                                 }
3665                                 more_trbs_coming = false;
3666                         }
3667
3668                         /* Calculate TRB length */
3669                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3670                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3671                         if (trb_buff_len > td_remain_len)
3672                                 trb_buff_len = td_remain_len;
3673
3674                         /* Set the TRB length, TD size, & interrupter fields. */
3675                         if (xhci->hci_version < 0x100) {
3676                                 remainder = xhci_td_remainder(
3677                                                 td_len - running_total);
3678                         } else {
3679                                 remainder = xhci_v1_0_td_remainder(
3680                                                 running_total, trb_buff_len,
3681                                                 total_packet_count, urb,
3682                                                 (trbs_per_td - j - 1));
3683                         }
3684                         length_field = TRB_LEN(trb_buff_len) |
3685                                 remainder |
3686                                 TRB_INTR_TARGET(0);
3687
3688                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3689                                 lower_32_bits(addr),
3690                                 upper_32_bits(addr),
3691                                 length_field,
3692                                 field);
3693                         running_total += trb_buff_len;
3694
3695                         addr += trb_buff_len;
3696                         td_remain_len -= trb_buff_len;
3697                 }
3698
3699                 /* Check TD length */
3700                 if (running_total != td_len) {
3701                         xhci_err(xhci, "ISOC TD length unmatch\n");
3702                         ret = -EINVAL;
3703                         goto cleanup;
3704                 }
3705         }
3706
3707         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3708                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3709                         usb_amd_quirk_pll_disable();
3710         }
3711         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3712
3713         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3714                         start_cycle, start_trb);
3715         return 0;
3716 cleanup:
3717         /* Clean up a partially enqueued isoc transfer. */
3718
3719         for (i--; i >= 0; i--)
3720                 list_del_init(&urb_priv->td[i]->td_list);
3721
3722         /* Use the first TD as a temporary variable to turn the TDs we've queued
3723          * into No-ops with a software-owned cycle bit. That way the hardware
3724          * won't accidentally start executing bogus TDs when we partially
3725          * overwrite them.  td->first_trb and td->start_seg are already set.
3726          */
3727         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3728         /* Every TRB except the first & last will have its cycle bit flipped. */
3729         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3730
3731         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3732         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3733         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3734         ep_ring->cycle_state = start_cycle;
3735         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3736         return ret;
3737 }
3738
3739 /*
3740  * Check transfer ring to guarantee there is enough room for the urb.
3741  * Update ISO URB start_frame and interval.
3742  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3743  * update the urb->start_frame by now.
3744  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3745  */
3746 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3747                 struct urb *urb, int slot_id, unsigned int ep_index)
3748 {
3749         struct xhci_virt_device *xdev;
3750         struct xhci_ring *ep_ring;
3751         struct xhci_ep_ctx *ep_ctx;
3752         int start_frame;
3753         int xhci_interval;
3754         int ep_interval;
3755         int num_tds, num_trbs, i;
3756         int ret;
3757
3758         xdev = xhci->devs[slot_id];
3759         ep_ring = xdev->eps[ep_index].ring;
3760         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3761
3762         num_trbs = 0;
3763         num_tds = urb->number_of_packets;
3764         for (i = 0; i < num_tds; i++)
3765                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3766
3767         /* Check the ring to guarantee there is enough room for the whole urb.
3768          * Do not insert any td of the urb to the ring if the check failed.
3769          */
3770         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3771                            num_trbs, true, mem_flags);
3772         if (ret)
3773                 return ret;
3774
3775         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3776         start_frame &= 0x3fff;
3777
3778         urb->start_frame = start_frame;
3779         if (urb->dev->speed == USB_SPEED_LOW ||
3780                         urb->dev->speed == USB_SPEED_FULL)
3781                 urb->start_frame >>= 3;
3782
3783         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3784         ep_interval = urb->interval;
3785         /* Convert to microframes */
3786         if (urb->dev->speed == USB_SPEED_LOW ||
3787                         urb->dev->speed == USB_SPEED_FULL)
3788                 ep_interval *= 8;
3789         /* FIXME change this to a warning and a suggestion to use the new API
3790          * to set the polling interval (once the API is added).
3791          */
3792         if (xhci_interval != ep_interval) {
3793                 if (printk_ratelimit())
3794                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3795                                         " (%d microframe%s) than xHCI "
3796                                         "(%d microframe%s)\n",
3797                                         ep_interval,
3798                                         ep_interval == 1 ? "" : "s",
3799                                         xhci_interval,
3800                                         xhci_interval == 1 ? "" : "s");
3801                 urb->interval = xhci_interval;
3802                 /* Convert back to frames for LS/FS devices */
3803                 if (urb->dev->speed == USB_SPEED_LOW ||
3804                                 urb->dev->speed == USB_SPEED_FULL)
3805                         urb->interval /= 8;
3806         }
3807         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3808 }
3809
3810 /****           Command Ring Operations         ****/
3811
3812 /* Generic function for queueing a command TRB on the command ring.
3813  * Check to make sure there's room on the command ring for one command TRB.
3814  * Also check that there's room reserved for commands that must not fail.
3815  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3816  * then only check for the number of reserved spots.
3817  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3818  * because the command event handler may want to resubmit a failed command.
3819  */
3820 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3821                 u32 field3, u32 field4, bool command_must_succeed)
3822 {
3823         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3824         int ret;
3825
3826         if (!command_must_succeed)
3827                 reserved_trbs++;
3828
3829         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3830                         reserved_trbs, false, GFP_ATOMIC);
3831         if (ret < 0) {
3832                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3833                 if (command_must_succeed)
3834                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3835                                         "unfailable commands failed.\n");
3836                 return ret;
3837         }
3838         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3839                         field3, field4 | xhci->cmd_ring->cycle_state);
3840         return 0;
3841 }
3842
3843 /* Queue a slot enable or disable request on the command ring */
3844 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3845 {
3846         return queue_command(xhci, 0, 0, 0,
3847                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3848 }
3849
3850 /* Queue an address device command TRB */
3851 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3852                 u32 slot_id)
3853 {
3854         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3855                         upper_32_bits(in_ctx_ptr), 0,
3856                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3857                         false);
3858 }
3859
3860 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3861                 u32 field1, u32 field2, u32 field3, u32 field4)
3862 {
3863         return queue_command(xhci, field1, field2, field3, field4, false);
3864 }
3865
3866 /* Queue a reset device command TRB */
3867 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3868 {
3869         return queue_command(xhci, 0, 0, 0,
3870                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3871                         false);
3872 }
3873
3874 /* Queue a configure endpoint command TRB */
3875 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3876                 u32 slot_id, bool command_must_succeed)
3877 {
3878         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3879                         upper_32_bits(in_ctx_ptr), 0,
3880                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3881                         command_must_succeed);
3882 }
3883
3884 /* Queue an evaluate context command TRB */
3885 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3886                 u32 slot_id)
3887 {
3888         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3889                         upper_32_bits(in_ctx_ptr), 0,
3890                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3891                         false);
3892 }
3893
3894 /*
3895  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3896  * activity on an endpoint that is about to be suspended.
3897  */
3898 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3899                 unsigned int ep_index, int suspend)
3900 {
3901         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3902         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3903         u32 type = TRB_TYPE(TRB_STOP_RING);
3904         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3905
3906         return queue_command(xhci, 0, 0, 0,
3907                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3908 }
3909
3910 /* Set Transfer Ring Dequeue Pointer command.
3911  * This should not be used for endpoints that have streams enabled.
3912  */
3913 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3914                 unsigned int ep_index, unsigned int stream_id,
3915                 struct xhci_segment *deq_seg,
3916                 union xhci_trb *deq_ptr, u32 cycle_state)
3917 {
3918         dma_addr_t addr;
3919         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3920         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3921         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3922         u32 type = TRB_TYPE(TRB_SET_DEQ);
3923         struct xhci_virt_ep *ep;
3924
3925         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3926         if (addr == 0) {
3927                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3928                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3929                                 deq_seg, deq_ptr);
3930                 return 0;
3931         }
3932         ep = &xhci->devs[slot_id]->eps[ep_index];
3933         if ((ep->ep_state & SET_DEQ_PENDING)) {
3934                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3935                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3936                 return 0;
3937         }
3938         ep->queued_deq_seg = deq_seg;
3939         ep->queued_deq_ptr = deq_ptr;
3940         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3941                         upper_32_bits(addr), trb_stream_id,
3942                         trb_slot_id | trb_ep_index | type, false);
3943 }
3944
3945 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3946                 unsigned int ep_index)
3947 {
3948         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3949         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3950         u32 type = TRB_TYPE(TRB_RESET_EP);
3951
3952         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3953                         false);
3954 }