drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return trb->link.control & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         union xhci_trb *next = ++(ring->dequeue);
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152         /* Update the dequeue pointer further if that was a link TRB or we're at
 153          * the end of an event ring segment (which doesn't have link TRBS)
 154          */
 155         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 156                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 157                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 158                         if (!in_interrupt())
 159                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 160                                                 ring,
 161                                                 (unsigned int) ring->cycle_state);
 162                 }
 163                 ring->deq_seg = ring->deq_seg->next;
 164                 ring->dequeue = ring->deq_seg->trbs;
 165                 next = ring->dequeue;
 166         }
 167         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 168         if (ring == xhci->event_ring)
 169                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 170         else if (ring == xhci->cmd_ring)
 171                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 172         else
 173                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 174 }
 175
 176 /*
 177  * See Cycle bit rules. SW is the consumer for the event ring only.
 178  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 179  *
 180  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 181  * chain bit is set), then set the chain bit in all the following link TRBs.
 182  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 183  * have their chain bit cleared (so that each Link TRB is a separate TD).
 184  *
 185  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 186  * set, but other sections talk about dealing with the chain bit set.  This was
 187  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 188  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 189  *
 190  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 191  *                      prepare_transfer()?
 192  */
 193 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 194                 bool consumer, bool more_trbs_coming)
 195 {
 196         u32 chain;
 197         union xhci_trb *next;
 198         unsigned long long addr;
 199
 200         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 201         next = ++(ring->enqueue);
 202
 203         ring->enq_updates++;
 204         /* Update the dequeue pointer further if that was a link TRB or we're at
 205          * the end of an event ring segment (which doesn't have link TRBS)
 206          */
 207         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 208                 if (!consumer) {
 209                         if (ring != xhci->event_ring) {
 210                                 /*
 211                                  * If the caller doesn't plan on enqueueing more
 212                                  * TDs before ringing the doorbell, then we
 213                                  * don't want to give the link TRB to the
 214                                  * hardware just yet.  We'll give the link TRB
 215                                  * back in prepare_ring() just before we enqueue
 216                                  * the TD at the top of the ring.
 217                                  */
 218                                 if (!chain && !more_trbs_coming)
 219                                         break;
 220
 221                                 /* If we're not dealing with 0.95 hardware,
 222                                  * carry over the chain bit of the previous TRB
 223                                  * (which may mean the chain bit is cleared).
 224                                  */
 225                                 if (!xhci_link_trb_quirk(xhci)) {
 226                                         next->link.control &= ~TRB_CHAIN;
 227                                         next->link.control |= chain;
 228                                 }
 229                                 /* Give this link TRB to the hardware */
 230                                 wmb();
 231                                 next->link.control ^= TRB_CYCLE;
 232                         }
 233                         /* Toggle the cycle bit after the last ring segment. */
 234                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 235                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 236                                 if (!in_interrupt())
 237                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 238                                                         ring,
 239                                                         (unsigned int) ring->cycle_state);
 240                         }
 241                 }
 242                 ring->enq_seg = ring->enq_seg->next;
 243                 ring->enqueue = ring->enq_seg->trbs;
 244                 next = ring->enqueue;
 245         }
 246         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 247         if (ring == xhci->event_ring)
 248                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 249         else if (ring == xhci->cmd_ring)
 250                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 251         else
 252                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 253 }
 254
 255 /*
 256  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 257  * above.
 258  * FIXME: this would be simpler and faster if we just kept track of the number
 259  * of free TRBs in a ring.
 260  */
 261 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 262                 unsigned int num_trbs)
 263 {
 264         int i;
 265         union xhci_trb *enq = ring->enqueue;
 266         struct xhci_segment *enq_seg = ring->enq_seg;
 267         struct xhci_segment *cur_seg;
 268         unsigned int left_on_ring;
 269
 270         /* If we are currently pointing to a link TRB, advance the
 271          * enqueue pointer before checking for space */
 272         while (last_trb(xhci, ring, enq_seg, enq)) {
 273                 enq_seg = enq_seg->next;
 274                 enq = enq_seg->trbs;
 275         }
 276
 277         /* Check if ring is empty */
 278         if (enq == ring->dequeue) {
 279                 /* Can't use link trbs */
 280                 left_on_ring = TRBS_PER_SEGMENT - 1;
 281                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 282                                 cur_seg = cur_seg->next)
 283                         left_on_ring += TRBS_PER_SEGMENT - 1;
 284
 285                 /* Always need one TRB free in the ring. */
 286                 left_on_ring -= 1;
 287                 if (num_trbs > left_on_ring) {
 288                         xhci_warn(xhci, "Not enough room on ring; "
 289                                         "need %u TRBs, %u TRBs left\n",
 290                                         num_trbs, left_on_ring);
 291                         return 0;
 292                 }
 293                 return 1;
 294         }
 295         /* Make sure there's an extra empty TRB available */
 296         for (i = 0; i <= num_trbs; ++i) {
 297                 if (enq == ring->dequeue)
 298                         return 0;
 299                 enq++;
 300                 while (last_trb(xhci, ring, enq_seg, enq)) {
 301                         enq_seg = enq_seg->next;
 302                         enq = enq_seg->trbs;
 303                 }
 304         }
 305         return 1;
 306 }
 307
 308 /* Ring the host controller doorbell after placing a command on the ring */
 309 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 310 {
 311         xhci_dbg(xhci, "// Ding dong!\n");
 312         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 313         /* Flush PCI posted writes */
 314         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 315 }
 316
 317 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 318                 unsigned int slot_id,
 319                 unsigned int ep_index,
 320                 unsigned int stream_id)
 321 {
 322         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 323         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 324         unsigned int ep_state = ep->ep_state;
 325
 326         /* Don't ring the doorbell for this endpoint if there are pending
 327          * cancellations because we don't want to interrupt processing.
 328          * We don't want to restart any stream rings if there's a set dequeue
 329          * pointer command pending because the device can choose to start any
 330          * stream once the endpoint is on the HW schedule.
 331          * FIXME - check all the stream rings for pending cancellations.
 332          */
 333         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 334             (ep_state & EP_HALTED))
 335                 return;
 336         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 337         /* The CPU has better things to do at this point than wait for a
 338          * write-posting flush.  It'll get there soon enough.
 339          */
 340 }
 341
 342 /* Ring the doorbell for any rings with pending URBs */
 343 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 344                 unsigned int slot_id,
 345                 unsigned int ep_index)
 346 {
 347         unsigned int stream_id;
 348         struct xhci_virt_ep *ep;
 349
 350         ep = &xhci->devs[slot_id]->eps[ep_index];
 351
 352         /* A ring has pending URBs if its TD list is not empty */
 353         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 354                 if (!(list_empty(&ep->ring->td_list)))
 355                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 356                 return;
 357         }
 358
 359         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 360                         stream_id++) {
 361                 struct xhci_stream_info *stream_info = ep->stream_info;
 362                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 363                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 364                                                 stream_id);
 365         }
 366 }
 367
 368 /*
 369  * Find the segment that trb is in.  Start searching in start_seg.
 370  * If we must move past a segment that has a link TRB with a toggle cycle state
 371  * bit set, then we will toggle the value pointed at by cycle_state.
 372  */
 373 static struct xhci_segment *find_trb_seg(
 374                 struct xhci_segment *start_seg,
 375                 union xhci_trb  *trb, int *cycle_state)
 376 {
 377         struct xhci_segment *cur_seg = start_seg;
 378         struct xhci_generic_trb *generic_trb;
 379
 380         while (cur_seg->trbs > trb ||
 381                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 382                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 383                 if (generic_trb->field[3] & LINK_TOGGLE)
 384                         *cycle_state ^= 0x1;
 385                 cur_seg = cur_seg->next;
 386                 if (cur_seg == start_seg)
 387                         /* Looped over the entire list.  Oops! */
 388                         return NULL;
 389         }
 390         return cur_seg;
 391 }
 392
 393
 394 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 395                 unsigned int slot_id, unsigned int ep_index,
 396                 unsigned int stream_id)
 397 {
 398         struct xhci_virt_ep *ep;
 399
 400         ep = &xhci->devs[slot_id]->eps[ep_index];
 401         /* Common case: no streams */
 402         if (!(ep->ep_state & EP_HAS_STREAMS))
 403                 return ep->ring;
 404
 405         if (stream_id == 0) {
 406                 xhci_warn(xhci,
 407                                 "WARN: Slot ID %u, ep index %u has streams, "
 408                                 "but URB has no stream ID.\n",
 409                                 slot_id, ep_index);
 410                 return NULL;
 411         }
 412
 413         if (stream_id < ep->stream_info->num_streams)
 414                 return ep->stream_info->stream_rings[stream_id];
 415
 416         xhci_warn(xhci,
 417                         "WARN: Slot ID %u, ep index %u has "
 418                         "stream IDs 1 to %u allocated, "
 419                         "but stream ID %u is requested.\n",
 420                         slot_id, ep_index,
 421                         ep->stream_info->num_streams - 1,
 422                         stream_id);
 423         return NULL;
 424 }
 425
 426 /* Get the right ring for the given URB.
 427  * If the endpoint supports streams, boundary check the URB's stream ID.
 428  * If the endpoint doesn't support streams, return the singular endpoint ring.
 429  */
 430 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 431                 struct urb *urb)
 432 {
 433         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 434                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 435 }
 436
 437 /*
 438  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 439  * Record the new state of the xHC's endpoint ring dequeue segment,
 440  * dequeue pointer, and new consumer cycle state in state.
 441  * Update our internal representation of the ring's dequeue pointer.
 442  *
 443  * We do this in three jumps:
 444  *  - First we update our new ring state to be the same as when the xHC stopped.
 445  *  - Then we traverse the ring to find the segment that contains
 446  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 447  *    any link TRBs with the toggle cycle bit set.
 448  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 449  *    if we've moved it past a link TRB with the toggle cycle bit set.
 450  */
 451 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 452                 unsigned int slot_id, unsigned int ep_index,
 453                 unsigned int stream_id, struct xhci_td *cur_td,
 454                 struct xhci_dequeue_state *state)
 455 {
 456         struct xhci_virt_device *dev = xhci->devs[slot_id];
 457         struct xhci_ring *ep_ring;
 458         struct xhci_generic_trb *trb;
 459         struct xhci_ep_ctx *ep_ctx;
 460         dma_addr_t addr;
 461
 462         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 463                         ep_index, stream_id);
 464         if (!ep_ring) {
 465                 xhci_warn(xhci, "WARN can't find new dequeue state "
 466                                 "for invalid stream ID %u.\n",
 467                                 stream_id);
 468                 return;
 469         }
 470         state->new_cycle_state = 0;
 471         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 472         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 473                         dev->eps[ep_index].stopped_trb,
 474                         &state->new_cycle_state);
 475         if (!state->new_deq_seg) {
 476                 WARN_ON(1);
 477                 return;
 478         }
 479
 480         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 481         xhci_dbg(xhci, "Finding endpoint context\n");
 482         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 483         state->new_cycle_state = 0x1 & ep_ctx->deq;
 484
 485         state->new_deq_ptr = cur_td->last_trb;
 486         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 487         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 488                         state->new_deq_ptr,
 489                         &state->new_cycle_state);
 490         if (!state->new_deq_seg) {
 491                 WARN_ON(1);
 492                 return;
 493         }
 494
 495         trb = &state->new_deq_ptr->generic;
 496         if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
 497                                 (trb->field[3] & LINK_TOGGLE))
 498                 state->new_cycle_state ^= 0x1;
 499         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 500
 501         /*
 502          * If there is only one segment in a ring, find_trb_seg()'s while loop
 503          * will not run, and it will return before it has a chance to see if it
 504          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 505          * ended just before the link TRB on a one-segment ring, or if the TD
 506          * wrapped around the top of the ring, because it doesn't have the TD in
 507          * question.  Look for the one-segment case where stalled TRB's address
 508          * is greater than the new dequeue pointer address.
 509          */
 510         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 511                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 512                 state->new_cycle_state ^= 0x1;
 513         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 514
 515         /* Don't update the ring cycle state for the producer (us). */
 516         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 517                         state->new_deq_seg);
 518         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 519         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 520                         (unsigned long long) addr);
 521 }
 522
 523 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 524                 struct xhci_td *cur_td)
 525 {
 526         struct xhci_segment *cur_seg;
 527         union xhci_trb *cur_trb;
 528
 529         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 530                         true;
 531                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 532                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 533                                 TRB_TYPE(TRB_LINK)) {
 534                         /* Unchain any chained Link TRBs, but
 535                          * leave the pointers intact.
 536                          */
 537                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 538                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 539                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 540                                         "in seg %p (0x%llx dma)\n",
 541                                         cur_trb,
 542                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 543                                         cur_seg,
 544                                         (unsigned long long)cur_seg->dma);
 545                 } else {
 546                         cur_trb->generic.field[0] = 0;
 547                         cur_trb->generic.field[1] = 0;
 548                         cur_trb->generic.field[2] = 0;
 549                         /* Preserve only the cycle bit of this TRB */
 550                         cur_trb->generic.field[3] &= TRB_CYCLE;
 551                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 552                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 553                                         "in seg %p (0x%llx dma)\n",
 554                                         cur_trb,
 555                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 556                                         cur_seg,
 557                                         (unsigned long long)cur_seg->dma);
 558                 }
 559                 if (cur_trb == cur_td->last_trb)
 560                         break;
 561         }
 562 }
 563
 564 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 565                 unsigned int ep_index, unsigned int stream_id,
 566                 struct xhci_segment *deq_seg,
 567                 union xhci_trb *deq_ptr, u32 cycle_state);
 568
 569 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 570                 unsigned int slot_id, unsigned int ep_index,
 571                 unsigned int stream_id,
 572                 struct xhci_dequeue_state *deq_state)
 573 {
 574         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 575
 576         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 577                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 578                         deq_state->new_deq_seg,
 579                         (unsigned long long)deq_state->new_deq_seg->dma,
 580                         deq_state->new_deq_ptr,
 581                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 582                         deq_state->new_cycle_state);
 583         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 584                         deq_state->new_deq_seg,
 585                         deq_state->new_deq_ptr,
 586                         (u32) deq_state->new_cycle_state);
 587         /* Stop the TD queueing code from ringing the doorbell until
 588          * this command completes.  The HC won't set the dequeue pointer
 589          * if the ring is running, and ringing the doorbell starts the
 590          * ring running.
 591          */
 592         ep->ep_state |= SET_DEQ_PENDING;
 593 }
 594
 595 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 596                 struct xhci_virt_ep *ep)
 597 {
 598         ep->ep_state &= ~EP_HALT_PENDING;
 599         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 600          * timer is running on another CPU, we don't decrement stop_cmds_pending
 601          * (since we didn't successfully stop the watchdog timer).
 602          */
 603         if (del_timer(&ep->stop_cmd_timer))
 604                 ep->stop_cmds_pending--;
 605 }
 606
 607 /* Must be called with xhci->lock held in interrupt context */
 608 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 609                 struct xhci_td *cur_td, int status, char *adjective)
 610 {
 611         struct usb_hcd *hcd;
 612         struct urb      *urb;
 613         struct urb_priv *urb_priv;
 614
 615         urb = cur_td->urb;
 616         urb_priv = urb->hcpriv;
 617         urb_priv->td_cnt++;
 618         hcd = bus_to_hcd(urb->dev->bus);
 619
 620         /* Only giveback urb when this is the last td in urb */
 621         if (urb_priv->td_cnt == urb_priv->length) {
 622                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 623                 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
 624
 625                 spin_unlock(&xhci->lock);
 626                 usb_hcd_giveback_urb(hcd, urb, status);
 627                 xhci_urb_free_priv(xhci, urb_priv);
 628                 spin_lock(&xhci->lock);
 629                 xhci_dbg(xhci, "%s URB given back\n", adjective);
 630         }
 631 }
 632
 633 /*
 634  * When we get a command completion for a Stop Endpoint Command, we need to
 635  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 636  *
 637  *  1. If the HW was in the middle of processing the TD that needs to be
 638  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 639  *     in the TD with a Set Dequeue Pointer Command.
 640  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 641  *     bit cleared) so that the HW will skip over them.
 642  */
 643 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 644                 union xhci_trb *trb, struct xhci_event_cmd *event)
 645 {
 646         unsigned int slot_id;
 647         unsigned int ep_index;
 648         struct xhci_virt_device *virt_dev;
 649         struct xhci_ring *ep_ring;
 650         struct xhci_virt_ep *ep;
 651         struct list_head *entry;
 652         struct xhci_td *cur_td = NULL;
 653         struct xhci_td *last_unlinked_td;
 654
 655         struct xhci_dequeue_state deq_state;
 656
 657         if (unlikely(TRB_TO_SUSPEND_PORT(
 658                         xhci->cmd_ring->dequeue->generic.field[3]))) {
 659                 slot_id = TRB_TO_SLOT_ID(
 660                         xhci->cmd_ring->dequeue->generic.field[3]);
 661                 virt_dev = xhci->devs[slot_id];
 662                 if (virt_dev)
 663                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 664                                 event);
 665                 else
 666                         xhci_warn(xhci, "Stop endpoint command "
 667                                 "completion for disabled slot %u\n",
 668                                 slot_id);
 669                 return;
 670         }
 671
 672         memset(&deq_state, 0, sizeof(deq_state));
 673         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 674         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 675         ep = &xhci->devs[slot_id]->eps[ep_index];
 676
 677         if (list_empty(&ep->cancelled_td_list)) {
 678                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 679                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 680                 return;
 681         }
 682
 683         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 684          * We have the xHCI lock, so nothing can modify this list until we drop
 685          * it.  We're also in the event handler, so we can't get re-interrupted
 686          * if another Stop Endpoint command completes
 687          */
 688         list_for_each(entry, &ep->cancelled_td_list) {
 689                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 690                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 691                                 cur_td->first_trb,
 692                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 693                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 694                 if (!ep_ring) {
 695                         /* This shouldn't happen unless a driver is mucking
 696                          * with the stream ID after submission.  This will
 697                          * leave the TD on the hardware ring, and the hardware
 698                          * will try to execute it, and may access a buffer
 699                          * that has already been freed.  In the best case, the
 700                          * hardware will execute it, and the event handler will
 701                          * ignore the completion event for that TD, since it was
 702                          * removed from the td_list for that endpoint.  In
 703                          * short, don't muck with the stream ID after
 704                          * submission.
 705                          */
 706                         xhci_warn(xhci, "WARN Cancelled URB %p "
 707                                         "has invalid stream ID %u.\n",
 708                                         cur_td->urb,
 709                                         cur_td->urb->stream_id);
 710                         goto remove_finished_td;
 711                 }
 712                 /*
 713                  * If we stopped on the TD we need to cancel, then we have to
 714                  * move the xHC endpoint ring dequeue pointer past this TD.
 715                  */
 716                 if (cur_td == ep->stopped_td)
 717                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 718                                         cur_td->urb->stream_id,
 719                                         cur_td, &deq_state);
 720                 else
 721                         td_to_noop(xhci, ep_ring, cur_td);
 722 remove_finished_td:
 723                 /*
 724                  * The event handler won't see a completion for this TD anymore,
 725                  * so remove it from the endpoint ring's TD list.  Keep it in
 726                  * the cancelled TD list for URB completion later.
 727                  */
 728                 list_del(&cur_td->td_list);
 729         }
 730         last_unlinked_td = cur_td;
 731         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 732
 733         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 734         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 735                 xhci_queue_new_dequeue_state(xhci,
 736                                 slot_id, ep_index,
 737                                 ep->stopped_td->urb->stream_id,
 738                                 &deq_state);
 739                 xhci_ring_cmd_db(xhci);
 740         } else {
 741                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 742                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 743         }
 744         ep->stopped_td = NULL;
 745         ep->stopped_trb = NULL;
 746
 747         /*
 748          * Drop the lock and complete the URBs in the cancelled TD list.
 749          * New TDs to be cancelled might be added to the end of the list before
 750          * we can complete all the URBs for the TDs we already unlinked.
 751          * So stop when we've completed the URB for the last TD we unlinked.
 752          */
 753         do {
 754                 cur_td = list_entry(ep->cancelled_td_list.next,
 755                                 struct xhci_td, cancelled_td_list);
 756                 list_del(&cur_td->cancelled_td_list);
 757
 758                 /* Clean up the cancelled URB */
 759                 /* Doesn't matter what we pass for status, since the core will
 760                  * just overwrite it (because the URB has been unlinked).
 761                  */
 762                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 763
 764                 /* Stop processing the cancelled list if the watchdog timer is
 765                  * running.
 766                  */
 767                 if (xhci->xhc_state & XHCI_STATE_DYING)
 768                         return;
 769         } while (cur_td != last_unlinked_td);
 770
 771         /* Return to the event handler with xhci->lock re-acquired */
 772 }
 773
 774 /* Watchdog timer function for when a stop endpoint command fails to complete.
 775  * In this case, we assume the host controller is broken or dying or dead.  The
 776  * host may still be completing some other events, so we have to be careful to
 777  * let the event ring handler and the URB dequeueing/enqueueing functions know
 778  * through xhci->state.
 779  *
 780  * The timer may also fire if the host takes a very long time to respond to the
 781  * command, and the stop endpoint command completion handler cannot delete the
 782  * timer before the timer function is called.  Another endpoint cancellation may
 783  * sneak in before the timer function can grab the lock, and that may queue
 784  * another stop endpoint command and add the timer back.  So we cannot use a
 785  * simple flag to say whether there is a pending stop endpoint command for a
 786  * particular endpoint.
 787  *
 788  * Instead we use a combination of that flag and a counter for the number of
 789  * pending stop endpoint commands.  If the timer is the tail end of the last
 790  * stop endpoint command, and the endpoint's command is still pending, we assume
 791  * the host is dying.
 792  */
 793 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 794 {
 795         struct xhci_hcd *xhci;
 796         struct xhci_virt_ep *ep;
 797         struct xhci_virt_ep *temp_ep;
 798         struct xhci_ring *ring;
 799         struct xhci_td *cur_td;
 800         int ret, i, j;
 801
 802         ep = (struct xhci_virt_ep *) arg;
 803         xhci = ep->xhci;
 804
 805         spin_lock(&xhci->lock);
 806
 807         ep->stop_cmds_pending--;
 808         if (xhci->xhc_state & XHCI_STATE_DYING) {
 809                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 810                                 "xHCI as DYING, exiting.\n");
 811                 spin_unlock(&xhci->lock);
 812                 return;
 813         }
 814         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 815                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 816                                 "exiting.\n");
 817                 spin_unlock(&xhci->lock);
 818                 return;
 819         }
 820
 821         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 822         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 823         /* Oops, HC is dead or dying or at least not responding to the stop
 824          * endpoint command.
 825          */
 826         xhci->xhc_state |= XHCI_STATE_DYING;
 827         /* Disable interrupts from the host controller and start halting it */
 828         xhci_quiesce(xhci);
 829         spin_unlock(&xhci->lock);
 830
 831         ret = xhci_halt(xhci);
 832
 833         spin_lock(&xhci->lock);
 834         if (ret < 0) {
 835                 /* This is bad; the host is not responding to commands and it's
 836                  * not allowing itself to be halted.  At least interrupts are
 837                  * disabled. If we call usb_hc_died(), it will attempt to
 838                  * disconnect all device drivers under this host.  Those
 839                  * disconnect() methods will wait for all URBs to be unlinked,
 840                  * so we must complete them.
 841                  */
 842                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 843                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 844                 /* We could turn all TDs on the rings to no-ops.  This won't
 845                  * help if the host has cached part of the ring, and is slow if
 846                  * we want to preserve the cycle bit.  Skip it and hope the host
 847                  * doesn't touch the memory.
 848                  */
 849         }
 850         for (i = 0; i < MAX_HC_SLOTS; i++) {
 851                 if (!xhci->devs[i])
 852                         continue;
 853                 for (j = 0; j < 31; j++) {
 854                         temp_ep = &xhci->devs[i]->eps[j];
 855                         ring = temp_ep->ring;
 856                         if (!ring)
 857                                 continue;
 858                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 859                                         "ep index %u\n", i, j);
 860                         while (!list_empty(&ring->td_list)) {
 861                                 cur_td = list_first_entry(&ring->td_list,
 862                                                 struct xhci_td,
 863                                                 td_list);
 864                                 list_del(&cur_td->td_list);
 865                                 if (!list_empty(&cur_td->cancelled_td_list))
 866                                         list_del(&cur_td->cancelled_td_list);
 867                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 868                                                 -ESHUTDOWN, "killed");
 869                         }
 870                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 871                                 cur_td = list_first_entry(
 872                                                 &temp_ep->cancelled_td_list,
 873                                                 struct xhci_td,
 874                                                 cancelled_td_list);
 875                                 list_del(&cur_td->cancelled_td_list);
 876                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 877                                                 -ESHUTDOWN, "killed");
 878                         }
 879                 }
 880         }
 881         spin_unlock(&xhci->lock);
 882         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 883         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 884         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 885 }
 886
 887 /*
 888  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 889  * we need to clear the set deq pending flag in the endpoint ring state, so that
 890  * the TD queueing code can ring the doorbell again.  We also need to ring the
 891  * endpoint doorbell to restart the ring, but only if there aren't more
 892  * cancellations pending.
 893  */
 894 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 895                 struct xhci_event_cmd *event,
 896                 union xhci_trb *trb)
 897 {
 898         unsigned int slot_id;
 899         unsigned int ep_index;
 900         unsigned int stream_id;
 901         struct xhci_ring *ep_ring;
 902         struct xhci_virt_device *dev;
 903         struct xhci_ep_ctx *ep_ctx;
 904         struct xhci_slot_ctx *slot_ctx;
 905
 906         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 907         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 908         stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
 909         dev = xhci->devs[slot_id];
 910
 911         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 912         if (!ep_ring) {
 913                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 914                                 "freed stream ID %u\n",
 915                                 stream_id);
 916                 /* XXX: Harmless??? */
 917                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 918                 return;
 919         }
 920
 921         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 922         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 923
 924         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 925                 unsigned int ep_state;
 926                 unsigned int slot_state;
 927
 928                 switch (GET_COMP_CODE(event->status)) {
 929                 case COMP_TRB_ERR:
 930                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 931                                         "of stream ID configuration\n");
 932                         break;
 933                 case COMP_CTX_STATE:
 934                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 935                                         "to incorrect slot or ep state.\n");
 936                         ep_state = ep_ctx->ep_info;
 937                         ep_state &= EP_STATE_MASK;
 938                         slot_state = slot_ctx->dev_state;
 939                         slot_state = GET_SLOT_STATE(slot_state);
 940                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 941                                         slot_state, ep_state);
 942                         break;
 943                 case COMP_EBADSLT:
 944                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 945                                         "slot %u was not enabled.\n", slot_id);
 946                         break;
 947                 default:
 948                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 949                                         "completion code of %u.\n",
 950                                         GET_COMP_CODE(event->status));
 951                         break;
 952                 }
 953                 /* OK what do we do now?  The endpoint state is hosed, and we
 954                  * should never get to this point if the synchronization between
 955                  * queueing, and endpoint state are correct.  This might happen
 956                  * if the device gets disconnected after we've finished
 957                  * cancelling URBs, which might not be an error...
 958                  */
 959         } else {
 960                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 961                                 ep_ctx->deq);
 962                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 963                                         dev->eps[ep_index].queued_deq_ptr) ==
 964                                 (ep_ctx->deq & ~(EP_CTX_CYCLE_MASK))) {
 965                         /* Update the ring's dequeue segment and dequeue pointer
 966                          * to reflect the new position.
 967                          */
 968                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
 969                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
 970                 } else {
 971                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 972                                         "Ptr command & xHCI internal state.\n");
 973                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 974                                         dev->eps[ep_index].queued_deq_seg,
 975                                         dev->eps[ep_index].queued_deq_ptr);
 976                 }
 977         }
 978
 979         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 980         dev->eps[ep_index].queued_deq_seg = NULL;
 981         dev->eps[ep_index].queued_deq_ptr = NULL;
 982         /* Restart any rings with pending URBs */
 983         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 984 }
 985
 986 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 987                 struct xhci_event_cmd *event,
 988                 union xhci_trb *trb)
 989 {
 990         int slot_id;
 991         unsigned int ep_index;
 992
 993         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 994         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 995         /* This command will only fail if the endpoint wasn't halted,
 996          * but we don't care.
 997          */
 998         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 999                         (unsigned int) GET_COMP_CODE(event->status));
1000
1001         /* HW with the reset endpoint quirk needs to have a configure endpoint
1002          * command complete before the endpoint can be used.  Queue that here
1003          * because the HW can't handle two commands being queued in a row.
1004          */
1005         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1006                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1007                 xhci_queue_configure_endpoint(xhci,
1008                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1009                                 false);
1010                 xhci_ring_cmd_db(xhci);
1011         } else {
1012                 /* Clear our internal halted state and restart the ring(s) */
1013                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1014                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1015         }
1016 }
1017
1018 /* Check to see if a command in the device's command queue matches this one.
1019  * Signal the completion or free the command, and return 1.  Return 0 if the
1020  * completed command isn't at the head of the command list.
1021  */
1022 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1023                 struct xhci_virt_device *virt_dev,
1024                 struct xhci_event_cmd *event)
1025 {
1026         struct xhci_command *command;
1027
1028         if (list_empty(&virt_dev->cmd_list))
1029                 return 0;
1030
1031         command = list_entry(virt_dev->cmd_list.next,
1032                         struct xhci_command, cmd_list);
1033         if (xhci->cmd_ring->dequeue != command->command_trb)
1034                 return 0;
1035
1036         command->status =
1037                 GET_COMP_CODE(event->status);
1038         list_del(&command->cmd_list);
1039         if (command->completion)
1040                 complete(command->completion);
1041         else
1042                 xhci_free_command(xhci, command);
1043         return 1;
1044 }
1045
1046 static void handle_cmd_completion(struct xhci_hcd *xhci,
1047                 struct xhci_event_cmd *event)
1048 {
1049         int slot_id = TRB_TO_SLOT_ID(event->flags);
1050         u64 cmd_dma;
1051         dma_addr_t cmd_dequeue_dma;
1052         struct xhci_input_control_ctx *ctrl_ctx;
1053         struct xhci_virt_device *virt_dev;
1054         unsigned int ep_index;
1055         struct xhci_ring *ep_ring;
1056         unsigned int ep_state;
1057
1058         cmd_dma = event->cmd_trb;
1059         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1060                         xhci->cmd_ring->dequeue);
1061         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1062         if (cmd_dequeue_dma == 0) {
1063                 xhci->error_bitmask |= 1 << 4;
1064                 return;
1065         }
1066         /* Does the DMA address match our internal dequeue pointer address? */
1067         if (cmd_dma != (u64) cmd_dequeue_dma) {
1068                 xhci->error_bitmask |= 1 << 5;
1069                 return;
1070         }
1071         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1072         case TRB_TYPE(TRB_ENABLE_SLOT):
1073                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1074                         xhci->slot_id = slot_id;
1075                 else
1076                         xhci->slot_id = 0;
1077                 complete(&xhci->addr_dev);
1078                 break;
1079         case TRB_TYPE(TRB_DISABLE_SLOT):
1080                 if (xhci->devs[slot_id])
1081                         xhci_free_virt_device(xhci, slot_id);
1082                 break;
1083         case TRB_TYPE(TRB_CONFIG_EP):
1084                 virt_dev = xhci->devs[slot_id];
1085                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1086                         break;
1087                 /*
1088                  * Configure endpoint commands can come from the USB core
1089                  * configuration or alt setting changes, or because the HW
1090                  * needed an extra configure endpoint command after a reset
1091                  * endpoint command or streams were being configured.
1092                  * If the command was for a halted endpoint, the xHCI driver
1093                  * is not waiting on the configure endpoint command.
1094                  */
1095                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1096                                 virt_dev->in_ctx);
1097                 /* Input ctx add_flags are the endpoint index plus one */
1098                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1099                 /* A usb_set_interface() call directly after clearing a halted
1100                  * condition may race on this quirky hardware.  Not worth
1101                  * worrying about, since this is prototype hardware.  Not sure
1102                  * if this will work for streams, but streams support was
1103                  * untested on this prototype.
1104                  */
1105                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1106                                 ep_index != (unsigned int) -1 &&
1107                                 ctrl_ctx->add_flags - SLOT_FLAG ==
1108                                         ctrl_ctx->drop_flags) {
1109                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1110                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1111                         if (!(ep_state & EP_HALTED))
1112                                 goto bandwidth_change;
1113                         xhci_dbg(xhci, "Completed config ep cmd - "
1114                                         "last ep index = %d, state = %d\n",
1115                                         ep_index, ep_state);
1116                         /* Clear internal halted state and restart ring(s) */
1117                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1118                                 ~EP_HALTED;
1119                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1120                         break;
1121                 }
1122 bandwidth_change:
1123                 xhci_dbg(xhci, "Completed config ep cmd\n");
1124                 xhci->devs[slot_id]->cmd_status =
1125                         GET_COMP_CODE(event->status);
1126                 complete(&xhci->devs[slot_id]->cmd_completion);
1127                 break;
1128         case TRB_TYPE(TRB_EVAL_CONTEXT):
1129                 virt_dev = xhci->devs[slot_id];
1130                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1131                         break;
1132                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1133                 complete(&xhci->devs[slot_id]->cmd_completion);
1134                 break;
1135         case TRB_TYPE(TRB_ADDR_DEV):
1136                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1137                 complete(&xhci->addr_dev);
1138                 break;
1139         case TRB_TYPE(TRB_STOP_RING):
1140                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1141                 break;
1142         case TRB_TYPE(TRB_SET_DEQ):
1143                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1144                 break;
1145         case TRB_TYPE(TRB_CMD_NOOP):
1146                 break;
1147         case TRB_TYPE(TRB_RESET_EP):
1148                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1149                 break;
1150         case TRB_TYPE(TRB_RESET_DEV):
1151                 xhci_dbg(xhci, "Completed reset device command.\n");
1152                 slot_id = TRB_TO_SLOT_ID(
1153                                 xhci->cmd_ring->dequeue->generic.field[3]);
1154                 virt_dev = xhci->devs[slot_id];
1155                 if (virt_dev)
1156                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1157                 else
1158                         xhci_warn(xhci, "Reset device command completion "
1159                                         "for disabled slot %u\n", slot_id);
1160                 break;
1161         case TRB_TYPE(TRB_NEC_GET_FW):
1162                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1163                         xhci->error_bitmask |= 1 << 6;
1164                         break;
1165                 }
1166                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1167                                 NEC_FW_MAJOR(event->status),
1168                                 NEC_FW_MINOR(event->status));
1169                 break;
1170         default:
1171                 /* Skip over unknown commands on the event ring */
1172                 xhci->error_bitmask |= 1 << 6;
1173                 break;
1174         }
1175         inc_deq(xhci, xhci->cmd_ring, false);
1176 }
1177
1178 static void handle_vendor_event(struct xhci_hcd *xhci,
1179                 union xhci_trb *event)
1180 {
1181         u32 trb_type;
1182
1183         trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1184         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1185         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1186                 handle_cmd_completion(xhci, &event->event_cmd);
1187 }
1188
1189 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1190  * port registers -- USB 3.0 and USB 2.0).
1191  *
1192  * Returns a zero-based port number, which is suitable for indexing into each of
1193  * the split roothubs' port arrays and bus state arrays.
1194  */
1195 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1196                 struct xhci_hcd *xhci, u32 port_id)
1197 {
1198         unsigned int i;
1199         unsigned int num_similar_speed_ports = 0;
1200
1201         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1202          * and usb2_ports are 0-based indexes.  Count the number of similar
1203          * speed ports, up to 1 port before this port.
1204          */
1205         for (i = 0; i < (port_id - 1); i++) {
1206                 u8 port_speed = xhci->port_array[i];
1207
1208                 /*
1209                  * Skip ports that don't have known speeds, or have duplicate
1210                  * Extended Capabilities port speed entries.
1211                  */
1212                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1213                         continue;
1214
1215                 /*
1216                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1217                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1218                  * matches the device speed, it's a similar speed port.
1219                  */
1220                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1221                         num_similar_speed_ports++;
1222         }
1223         return num_similar_speed_ports;
1224 }
1225
1226 static void handle_port_status(struct xhci_hcd *xhci,
1227                 union xhci_trb *event)
1228 {
1229         struct usb_hcd *hcd;
1230         u32 port_id;
1231         u32 temp, temp1;
1232         int max_ports;
1233         int slot_id;
1234         unsigned int faked_port_index;
1235         u8 major_revision;
1236         struct xhci_bus_state *bus_state;
1237         u32 __iomem **port_array;
1238
1239         /* Port status change events always have a successful completion code */
1240         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1241                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1242                 xhci->error_bitmask |= 1 << 8;
1243         }
1244         port_id = GET_PORT_ID(event->generic.field[0]);
1245         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1246
1247         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1248         if ((port_id <= 0) || (port_id > max_ports)) {
1249                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1250                 goto cleanup;
1251         }
1252
1253         /* Figure out which usb_hcd this port is attached to:
1254          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1255          */
1256         major_revision = xhci->port_array[port_id - 1];
1257         if (major_revision == 0) {
1258                 xhci_warn(xhci, "Event for port %u not in "
1259                                 "Extended Capabilities, ignoring.\n",
1260                                 port_id);
1261                 goto cleanup;
1262         }
1263         if (major_revision == DUPLICATE_ENTRY) {
1264                 xhci_warn(xhci, "Event for port %u duplicated in"
1265                                 "Extended Capabilities, ignoring.\n",
1266                                 port_id);
1267                 goto cleanup;
1268         }
1269
1270         /*
1271          * Hardware port IDs reported by a Port Status Change Event include USB
1272          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1273          * resume event, but we first need to translate the hardware port ID
1274          * into the index into the ports on the correct split roothub, and the
1275          * correct bus_state structure.
1276          */
1277         /* Find the right roothub. */
1278         hcd = xhci_to_hcd(xhci);
1279         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1280                 hcd = xhci->shared_hcd;
1281         bus_state = &xhci->bus_state[hcd_index(hcd)];
1282         if (hcd->speed == HCD_USB3)
1283                 port_array = xhci->usb3_ports;
1284         else
1285                 port_array = xhci->usb2_ports;
1286         /* Find the faked port hub number */
1287         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1288                         port_id);
1289
1290         temp = xhci_readl(xhci, port_array[faked_port_index]);
1291         if (hcd->state == HC_STATE_SUSPENDED) {
1292                 xhci_dbg(xhci, "resume root hub\n");
1293                 usb_hcd_resume_root_hub(hcd);
1294         }
1295
1296         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1297                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1298
1299                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1300                 if (!(temp1 & CMD_RUN)) {
1301                         xhci_warn(xhci, "xHC is not running.\n");
1302                         goto cleanup;
1303                 }
1304
1305                 if (DEV_SUPERSPEED(temp)) {
1306                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1307                         temp = xhci_port_state_to_neutral(temp);
1308                         temp &= ~PORT_PLS_MASK;
1309                         temp |= PORT_LINK_STROBE | XDEV_U0;
1310                         xhci_writel(xhci, temp, port_array[faked_port_index]);
1311                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1312                                         faked_port_index);
1313                         if (!slot_id) {
1314                                 xhci_dbg(xhci, "slot_id is zero\n");
1315                                 goto cleanup;
1316                         }
1317                         xhci_ring_device(xhci, slot_id);
1318                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1319                         /* Clear PORT_PLC */
1320                         temp = xhci_readl(xhci, port_array[faked_port_index]);
1321                         temp = xhci_port_state_to_neutral(temp);
1322                         temp |= PORT_PLC;
1323                         xhci_writel(xhci, temp, port_array[faked_port_index]);
1324                 } else {
1325                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1326                         bus_state->resume_done[faked_port_index] = jiffies +
1327                                 msecs_to_jiffies(20);
1328                         mod_timer(&hcd->rh_timer,
1329                                   bus_state->resume_done[faked_port_index]);
1330                         /* Do the rest in GetPortStatus */
1331                 }
1332         }
1333
1334 cleanup:
1335         /* Update event ring dequeue pointer before dropping the lock */
1336         inc_deq(xhci, xhci->event_ring, true);
1337
1338         spin_unlock(&xhci->lock);
1339         /* Pass this up to the core */
1340         usb_hcd_poll_rh_status(hcd);
1341         spin_lock(&xhci->lock);
1342 }
1343
1344 /*
1345  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1346  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1347  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1348  * returns 0.
1349  */
1350 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1351                 union xhci_trb  *start_trb,
1352                 union xhci_trb  *end_trb,
1353                 dma_addr_t      suspect_dma)
1354 {
1355         dma_addr_t start_dma;
1356         dma_addr_t end_seg_dma;
1357         dma_addr_t end_trb_dma;
1358         struct xhci_segment *cur_seg;
1359
1360         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1361         cur_seg = start_seg;
1362
1363         do {
1364                 if (start_dma == 0)
1365                         return NULL;
1366                 /* We may get an event for a Link TRB in the middle of a TD */
1367                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1368                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1369                 /* If the end TRB isn't in this segment, this is set to 0 */
1370                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1371
1372                 if (end_trb_dma > 0) {
1373                         /* The end TRB is in this segment, so suspect should be here */
1374                         if (start_dma <= end_trb_dma) {
1375                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1376                                         return cur_seg;
1377                         } else {
1378                                 /* Case for one segment with
1379                                  * a TD wrapped around to the top
1380                                  */
1381                                 if ((suspect_dma >= start_dma &&
1382                                                         suspect_dma <= end_seg_dma) ||
1383                                                 (suspect_dma >= cur_seg->dma &&
1384                                                  suspect_dma <= end_trb_dma))
1385                                         return cur_seg;
1386                         }
1387                         return NULL;
1388                 } else {
1389                         /* Might still be somewhere in this segment */
1390                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1391                                 return cur_seg;
1392                 }
1393                 cur_seg = cur_seg->next;
1394                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1395         } while (cur_seg != start_seg);
1396
1397         return NULL;
1398 }
1399
1400 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1401                 unsigned int slot_id, unsigned int ep_index,
1402                 unsigned int stream_id,
1403                 struct xhci_td *td, union xhci_trb *event_trb)
1404 {
1405         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1406         ep->ep_state |= EP_HALTED;
1407         ep->stopped_td = td;
1408         ep->stopped_trb = event_trb;
1409         ep->stopped_stream = stream_id;
1410
1411         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1412         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1413
1414         ep->stopped_td = NULL;
1415         ep->stopped_trb = NULL;
1416         ep->stopped_stream = 0;
1417
1418         xhci_ring_cmd_db(xhci);
1419 }
1420
1421 /* Check if an error has halted the endpoint ring.  The class driver will
1422  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1423  * However, a babble and other errors also halt the endpoint ring, and the class
1424  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1425  * Ring Dequeue Pointer command manually.
1426  */
1427 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1428                 struct xhci_ep_ctx *ep_ctx,
1429                 unsigned int trb_comp_code)
1430 {
1431         /* TRB completion codes that may require a manual halt cleanup */
1432         if (trb_comp_code == COMP_TX_ERR ||
1433                         trb_comp_code == COMP_BABBLE ||
1434                         trb_comp_code == COMP_SPLIT_ERR)
1435                 /* The 0.96 spec says a babbling control endpoint
1436                  * is not halted. The 0.96 spec says it is.  Some HW
1437                  * claims to be 0.95 compliant, but it halts the control
1438                  * endpoint anyway.  Check if a babble halted the
1439                  * endpoint.
1440                  */
1441                 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1442                         return 1;
1443
1444         return 0;
1445 }
1446
1447 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1448 {
1449         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1450                 /* Vendor defined "informational" completion code,
1451                  * treat as not-an-error.
1452                  */
1453                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1454                                 trb_comp_code);
1455                 xhci_dbg(xhci, "Treating code as success.\n");
1456                 return 1;
1457         }
1458         return 0;
1459 }
1460
1461 /*
1462  * Finish the td processing, remove the td from td list;
1463  * Return 1 if the urb can be given back.
1464  */
1465 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1466         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1467         struct xhci_virt_ep *ep, int *status, bool skip)
1468 {
1469         struct xhci_virt_device *xdev;
1470         struct xhci_ring *ep_ring;
1471         unsigned int slot_id;
1472         int ep_index;
1473         struct urb *urb = NULL;
1474         struct xhci_ep_ctx *ep_ctx;
1475         int ret = 0;
1476         struct urb_priv *urb_priv;
1477         u32 trb_comp_code;
1478
1479         slot_id = TRB_TO_SLOT_ID(event->flags);
1480         xdev = xhci->devs[slot_id];
1481         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1482         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1483         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1484         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1485
1486         if (skip)
1487                 goto td_cleanup;
1488
1489         if (trb_comp_code == COMP_STOP_INVAL ||
1490                         trb_comp_code == COMP_STOP) {
1491                 /* The Endpoint Stop Command completion will take care of any
1492                  * stopped TDs.  A stopped TD may be restarted, so don't update
1493                  * the ring dequeue pointer or take this TD off any lists yet.
1494                  */
1495                 ep->stopped_td = td;
1496                 ep->stopped_trb = event_trb;
1497                 return 0;
1498         } else {
1499                 if (trb_comp_code == COMP_STALL) {
1500                         /* The transfer is completed from the driver's
1501                          * perspective, but we need to issue a set dequeue
1502                          * command for this stalled endpoint to move the dequeue
1503                          * pointer past the TD.  We can't do that here because
1504                          * the halt condition must be cleared first.  Let the
1505                          * USB class driver clear the stall later.
1506                          */
1507                         ep->stopped_td = td;
1508                         ep->stopped_trb = event_trb;
1509                         ep->stopped_stream = ep_ring->stream_id;
1510                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1511                                         ep_ctx, trb_comp_code)) {
1512                         /* Other types of errors halt the endpoint, but the
1513                          * class driver doesn't call usb_reset_endpoint() unless
1514                          * the error is -EPIPE.  Clear the halted status in the
1515                          * xHCI hardware manually.
1516                          */
1517                         xhci_cleanup_halted_endpoint(xhci,
1518                                         slot_id, ep_index, ep_ring->stream_id,
1519                                         td, event_trb);
1520                 } else {
1521                         /* Update ring dequeue pointer */
1522                         while (ep_ring->dequeue != td->last_trb)
1523                                 inc_deq(xhci, ep_ring, false);
1524                         inc_deq(xhci, ep_ring, false);
1525                 }
1526
1527 td_cleanup:
1528                 /* Clean up the endpoint's TD list */
1529                 urb = td->urb;
1530                 urb_priv = urb->hcpriv;
1531
1532                 /* Do one last check of the actual transfer length.
1533                  * If the host controller said we transferred more data than
1534                  * the buffer length, urb->actual_length will be a very big
1535                  * number (since it's unsigned).  Play it safe and say we didn't
1536                  * transfer anything.
1537                  */
1538                 if (urb->actual_length > urb->transfer_buffer_length) {
1539                         xhci_warn(xhci, "URB transfer length is wrong, "
1540                                         "xHC issue? req. len = %u, "
1541                                         "act. len = %u\n",
1542                                         urb->transfer_buffer_length,
1543                                         urb->actual_length);
1544                         urb->actual_length = 0;
1545                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1546                                 *status = -EREMOTEIO;
1547                         else
1548                                 *status = 0;
1549                 }
1550                 list_del(&td->td_list);
1551                 /* Was this TD slated to be cancelled but completed anyway? */
1552                 if (!list_empty(&td->cancelled_td_list))
1553                         list_del(&td->cancelled_td_list);
1554
1555                 urb_priv->td_cnt++;
1556                 /* Giveback the urb when all the tds are completed */
1557                 if (urb_priv->td_cnt == urb_priv->length)
1558                         ret = 1;
1559         }
1560
1561         return ret;
1562 }
1563
1564 /*
1565  * Process control tds, update urb status and actual_length.
1566  */
1567 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1568         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1569         struct xhci_virt_ep *ep, int *status)
1570 {
1571         struct xhci_virt_device *xdev;
1572         struct xhci_ring *ep_ring;
1573         unsigned int slot_id;
1574         int ep_index;
1575         struct xhci_ep_ctx *ep_ctx;
1576         u32 trb_comp_code;
1577
1578         slot_id = TRB_TO_SLOT_ID(event->flags);
1579         xdev = xhci->devs[slot_id];
1580         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1581         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1582         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1583         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1584
1585         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1586         switch (trb_comp_code) {
1587         case COMP_SUCCESS:
1588                 if (event_trb == ep_ring->dequeue) {
1589                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1590                                         "without IOC set??\n");
1591                         *status = -ESHUTDOWN;
1592                 } else if (event_trb != td->last_trb) {
1593                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1594                                         "without IOC set??\n");
1595                         *status = -ESHUTDOWN;
1596                 } else {
1597                         xhci_dbg(xhci, "Successful control transfer!\n");
1598                         *status = 0;
1599                 }
1600                 break;
1601         case COMP_SHORT_TX:
1602                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1603                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1604                         *status = -EREMOTEIO;
1605                 else
1606                         *status = 0;
1607                 break;
1608         default:
1609                 if (!xhci_requires_manual_halt_cleanup(xhci,
1610                                         ep_ctx, trb_comp_code))
1611                         break;
1612                 xhci_dbg(xhci, "TRB error code %u, "
1613                                 "halted endpoint index = %u\n",
1614                                 trb_comp_code, ep_index);
1615                 /* else fall through */
1616         case COMP_STALL:
1617                 /* Did we transfer part of the data (middle) phase? */
1618                 if (event_trb != ep_ring->dequeue &&
1619                                 event_trb != td->last_trb)
1620                         td->urb->actual_length =
1621                                 td->urb->transfer_buffer_length
1622                                 - TRB_LEN(event->transfer_len);
1623                 else
1624                         td->urb->actual_length = 0;
1625
1626                 xhci_cleanup_halted_endpoint(xhci,
1627                         slot_id, ep_index, 0, td, event_trb);
1628                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1629         }
1630         /*
1631          * Did we transfer any data, despite the errors that might have
1632          * happened?  I.e. did we get past the setup stage?
1633          */
1634         if (event_trb != ep_ring->dequeue) {
1635                 /* The event was for the status stage */
1636                 if (event_trb == td->last_trb) {
1637                         if (td->urb->actual_length != 0) {
1638                                 /* Don't overwrite a previously set error code
1639                                  */
1640                                 if ((*status == -EINPROGRESS || *status == 0) &&
1641                                                 (td->urb->transfer_flags
1642                                                  & URB_SHORT_NOT_OK))
1643                                         /* Did we already see a short data
1644                                          * stage? */
1645                                         *status = -EREMOTEIO;
1646                         } else {
1647                                 td->urb->actual_length =
1648                                         td->urb->transfer_buffer_length;
1649                         }
1650                 } else {
1651                 /* Maybe the event was for the data stage? */
1652                         if (trb_comp_code != COMP_STOP_INVAL) {
1653                                 /* We didn't stop on a link TRB in the middle */
1654                                 td->urb->actual_length =
1655                                         td->urb->transfer_buffer_length -
1656                                         TRB_LEN(event->transfer_len);
1657                                 xhci_dbg(xhci, "Waiting for status "
1658                                                 "stage event\n");
1659                                 return 0;
1660                         }
1661                 }
1662         }
1663
1664         return finish_td(xhci, td, event_trb, event, ep, status, false);
1665 }
1666
1667 /*
1668  * Process isochronous tds, update urb packet status and actual_length.
1669  */
1670 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1671         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1672         struct xhci_virt_ep *ep, int *status)
1673 {
1674         struct xhci_ring *ep_ring;
1675         struct urb_priv *urb_priv;
1676         int idx;
1677         int len = 0;
1678         union xhci_trb *cur_trb;
1679         struct xhci_segment *cur_seg;
1680         struct usb_iso_packet_descriptor *frame;
1681         u32 trb_comp_code;
1682         bool skip_td = false;
1683
1684         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1685         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1686         urb_priv = td->urb->hcpriv;
1687         idx = urb_priv->td_cnt;
1688         frame = &td->urb->iso_frame_desc[idx];
1689
1690         /* handle completion code */
1691         switch (trb_comp_code) {
1692         case COMP_SUCCESS:
1693                 frame->status = 0;
1694                 xhci_dbg(xhci, "Successful isoc transfer!\n");
1695                 break;
1696         case COMP_SHORT_TX:
1697                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1698                                 -EREMOTEIO : 0;
1699                 break;
1700         case COMP_BW_OVER:
1701                 frame->status = -ECOMM;
1702                 skip_td = true;
1703                 break;
1704         case COMP_BUFF_OVER:
1705         case COMP_BABBLE:
1706                 frame->status = -EOVERFLOW;
1707                 skip_td = true;
1708                 break;
1709         case COMP_STALL:
1710                 frame->status = -EPROTO;
1711                 skip_td = true;
1712                 break;
1713         case COMP_STOP:
1714         case COMP_STOP_INVAL:
1715                 break;
1716         default:
1717                 frame->status = -1;
1718                 break;
1719         }
1720
1721         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1722                 frame->actual_length = frame->length;
1723                 td->urb->actual_length += frame->length;
1724         } else {
1725                 for (cur_trb = ep_ring->dequeue,
1726                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1727                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1728                         if ((cur_trb->generic.field[3] &
1729                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1730                             (cur_trb->generic.field[3] &
1731                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1732                                 len +=
1733                                     TRB_LEN(cur_trb->generic.field[2]);
1734                 }
1735                 len += TRB_LEN(cur_trb->generic.field[2]) -
1736                         TRB_LEN(event->transfer_len);
1737
1738                 if (trb_comp_code != COMP_STOP_INVAL) {
1739                         frame->actual_length = len;
1740                         td->urb->actual_length += len;
1741                 }
1742         }
1743
1744         if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1745                 *status = 0;
1746
1747         return finish_td(xhci, td, event_trb, event, ep, status, false);
1748 }
1749
1750 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1751                         struct xhci_transfer_event *event,
1752                         struct xhci_virt_ep *ep, int *status)
1753 {
1754         struct xhci_ring *ep_ring;
1755         struct urb_priv *urb_priv;
1756         struct usb_iso_packet_descriptor *frame;
1757         int idx;
1758
1759         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1760         urb_priv = td->urb->hcpriv;
1761         idx = urb_priv->td_cnt;
1762         frame = &td->urb->iso_frame_desc[idx];
1763
1764         /* The transfer is partly done */
1765         *status = -EXDEV;
1766         frame->status = -EXDEV;
1767
1768         /* calc actual length */
1769         frame->actual_length = 0;
1770
1771         /* Update ring dequeue pointer */
1772         while (ep_ring->dequeue != td->last_trb)
1773                 inc_deq(xhci, ep_ring, false);
1774         inc_deq(xhci, ep_ring, false);
1775
1776         return finish_td(xhci, td, NULL, event, ep, status, true);
1777 }
1778
1779 /*
1780  * Process bulk and interrupt tds, update urb status and actual_length.
1781  */
1782 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1783         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1784         struct xhci_virt_ep *ep, int *status)
1785 {
1786         struct xhci_ring *ep_ring;
1787         union xhci_trb *cur_trb;
1788         struct xhci_segment *cur_seg;
1789         u32 trb_comp_code;
1790
1791         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1792         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1793
1794         switch (trb_comp_code) {
1795         case COMP_SUCCESS:
1796                 /* Double check that the HW transferred everything. */
1797                 if (event_trb != td->last_trb) {
1798                         xhci_warn(xhci, "WARN Successful completion "
1799                                         "on short TX\n");
1800                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1801                                 *status = -EREMOTEIO;
1802                         else
1803                                 *status = 0;
1804                 } else {
1805                         if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1806                                 xhci_dbg(xhci, "Successful bulk "
1807                                                 "transfer!\n");
1808                         else
1809                                 xhci_dbg(xhci, "Successful interrupt "
1810                                                 "transfer!\n");
1811                         *status = 0;
1812                 }
1813                 break;
1814         case COMP_SHORT_TX:
1815                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1816                         *status = -EREMOTEIO;
1817                 else
1818                         *status = 0;
1819                 break;
1820         default:
1821                 /* Others already handled above */
1822                 break;
1823         }
1824         xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1825                         "%d bytes untransferred\n",
1826                         td->urb->ep->desc.bEndpointAddress,
1827                         td->urb->transfer_buffer_length,
1828                         TRB_LEN(event->transfer_len));
1829         /* Fast path - was this the last TRB in the TD for this URB? */
1830         if (event_trb == td->last_trb) {
1831                 if (TRB_LEN(event->transfer_len) != 0) {
1832                         td->urb->actual_length =
1833                                 td->urb->transfer_buffer_length -
1834                                 TRB_LEN(event->transfer_len);
1835                         if (td->urb->transfer_buffer_length <
1836                                         td->urb->actual_length) {
1837                                 xhci_warn(xhci, "HC gave bad length "
1838                                                 "of %d bytes left\n",
1839                                                 TRB_LEN(event->transfer_len));
1840                                 td->urb->actual_length = 0;
1841                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1842                                         *status = -EREMOTEIO;
1843                                 else
1844                                         *status = 0;
1845                         }
1846                         /* Don't overwrite a previously set error code */
1847                         if (*status == -EINPROGRESS) {
1848                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1849                                         *status = -EREMOTEIO;
1850                                 else
1851                                         *status = 0;
1852                         }
1853                 } else {
1854                         td->urb->actual_length =
1855                                 td->urb->transfer_buffer_length;
1856                         /* Ignore a short packet completion if the
1857                          * untransferred length was zero.
1858                          */
1859                         if (*status == -EREMOTEIO)
1860                                 *status = 0;
1861                 }
1862         } else {
1863                 /* Slow path - walk the list, starting from the dequeue
1864                  * pointer, to get the actual length transferred.
1865                  */
1866                 td->urb->actual_length = 0;
1867                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1868                                 cur_trb != event_trb;
1869                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1870                         if ((cur_trb->generic.field[3] &
1871                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1872                             (cur_trb->generic.field[3] &
1873                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1874                                 td->urb->actual_length +=
1875                                         TRB_LEN(cur_trb->generic.field[2]);
1876                 }
1877                 /* If the ring didn't stop on a Link or No-op TRB, add
1878                  * in the actual bytes transferred from the Normal TRB
1879                  */
1880                 if (trb_comp_code != COMP_STOP_INVAL)
1881                         td->urb->actual_length +=
1882                                 TRB_LEN(cur_trb->generic.field[2]) -
1883                                 TRB_LEN(event->transfer_len);
1884         }
1885
1886         return finish_td(xhci, td, event_trb, event, ep, status, false);
1887 }
1888
1889 /*
1890  * If this function returns an error condition, it means it got a Transfer
1891  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1892  * At this point, the host controller is probably hosed and should be reset.
1893  */
1894 static int handle_tx_event(struct xhci_hcd *xhci,
1895                 struct xhci_transfer_event *event)
1896 {
1897         struct xhci_virt_device *xdev;
1898         struct xhci_virt_ep *ep;
1899         struct xhci_ring *ep_ring;
1900         unsigned int slot_id;
1901         int ep_index;
1902         struct xhci_td *td = NULL;
1903         dma_addr_t event_dma;
1904         struct xhci_segment *event_seg;
1905         union xhci_trb *event_trb;
1906         struct urb *urb = NULL;
1907         int status = -EINPROGRESS;
1908         struct urb_priv *urb_priv;
1909         struct xhci_ep_ctx *ep_ctx;
1910         u32 trb_comp_code;
1911         int ret = 0;
1912
1913         slot_id = TRB_TO_SLOT_ID(event->flags);
1914         xdev = xhci->devs[slot_id];
1915         if (!xdev) {
1916                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1917                 return -ENODEV;
1918         }
1919
1920         /* Endpoint ID is 1 based, our index is zero based */
1921         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1922         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1923         ep = &xdev->eps[ep_index];
1924         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1925         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1926         if (!ep_ring ||
1927                 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1928                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1929                                 "or incorrect stream ring\n");
1930                 return -ENODEV;
1931         }
1932
1933         event_dma = event->buffer;
1934         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1935         /* Look for common error cases */
1936         switch (trb_comp_code) {
1937         /* Skip codes that require special handling depending on
1938          * transfer type
1939          */
1940         case COMP_SUCCESS:
1941         case COMP_SHORT_TX:
1942                 break;
1943         case COMP_STOP:
1944                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1945                 break;
1946         case COMP_STOP_INVAL:
1947                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1948                 break;
1949         case COMP_STALL:
1950                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1951                 ep->ep_state |= EP_HALTED;
1952                 status = -EPIPE;
1953                 break;
1954         case COMP_TRB_ERR:
1955                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1956                 status = -EILSEQ;
1957                 break;
1958         case COMP_SPLIT_ERR:
1959         case COMP_TX_ERR:
1960                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1961                 status = -EPROTO;
1962                 break;
1963         case COMP_BABBLE:
1964                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1965                 status = -EOVERFLOW;
1966                 break;
1967         case COMP_DB_ERR:
1968                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1969                 status = -ENOSR;
1970                 break;
1971         case COMP_BW_OVER:
1972                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1973                 break;
1974         case COMP_BUFF_OVER:
1975                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1976                 break;
1977         case COMP_UNDERRUN:
1978                 /*
1979                  * When the Isoch ring is empty, the xHC will generate
1980                  * a Ring Overrun Event for IN Isoch endpoint or Ring
1981                  * Underrun Event for OUT Isoch endpoint.
1982                  */
1983                 xhci_dbg(xhci, "underrun event on endpoint\n");
1984                 if (!list_empty(&ep_ring->td_list))
1985                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1986                                         "still with TDs queued?\n",
1987                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1988                 goto cleanup;
1989         case COMP_OVERRUN:
1990                 xhci_dbg(xhci, "overrun event on endpoint\n");
1991                 if (!list_empty(&ep_ring->td_list))
1992                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1993                                         "still with TDs queued?\n",
1994                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1995                 goto cleanup;
1996         case COMP_MISSED_INT:
1997                 /*
1998                  * When encounter missed service error, one or more isoc tds
1999                  * may be missed by xHC.
2000                  * Set skip flag of the ep_ring; Complete the missed tds as
2001                  * short transfer when process the ep_ring next time.
2002                  */
2003                 ep->skip = true;
2004                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2005                 goto cleanup;
2006         default:
2007                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2008                         status = 0;
2009                         break;
2010                 }
2011                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2012                                 "busted\n");
2013                 goto cleanup;
2014         }
2015
2016         do {
2017                 /* This TRB should be in the TD at the head of this ring's
2018                  * TD list.
2019                  */
2020                 if (list_empty(&ep_ring->td_list)) {
2021                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2022                                         "with no TDs queued?\n",
2023                                   TRB_TO_SLOT_ID(event->flags), ep_index);
2024                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2025                           (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
2026                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2027                         if (ep->skip) {
2028                                 ep->skip = false;
2029                                 xhci_dbg(xhci, "td_list is empty while skip "
2030                                                 "flag set. Clear skip flag.\n");
2031                         }
2032                         ret = 0;
2033                         goto cleanup;
2034                 }
2035
2036                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2037
2038                 /* Is this a TRB in the currently executing TD? */
2039                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2040                                 td->last_trb, event_dma);
2041                 if (!event_seg) {
2042                         if (!ep->skip ||
2043                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2044                                 /* HC is busted, give up! */
2045                                 xhci_err(xhci,
2046                                         "ERROR Transfer event TRB DMA ptr not "
2047                                         "part of current TD\n");
2048                                 return -ESHUTDOWN;
2049                         }
2050
2051                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2052                         goto cleanup;
2053                 }
2054
2055                 if (ep->skip) {
2056                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2057                         ep->skip = false;
2058                 }
2059
2060                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2061                                                 sizeof(*event_trb)];
2062                 /*
2063                  * No-op TRB should not trigger interrupts.
2064                  * If event_trb is a no-op TRB, it means the
2065                  * corresponding TD has been cancelled. Just ignore
2066                  * the TD.
2067                  */
2068                 if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
2069                                  == TRB_TYPE(TRB_TR_NOOP)) {
2070                         xhci_dbg(xhci,
2071                                  "event_trb is a no-op TRB. Skip it\n");
2072                         goto cleanup;
2073                 }
2074
2075                 /* Now update the urb's actual_length and give back to
2076                  * the core
2077                  */
2078                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2079                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2080                                                  &status);
2081                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2082                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2083                                                  &status);
2084                 else
2085                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2086                                                  ep, &status);
2087
2088 cleanup:
2089                 /*
2090                  * Do not update event ring dequeue pointer if ep->skip is set.
2091                  * Will roll back to continue process missed tds.
2092                  */
2093                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2094                         inc_deq(xhci, xhci->event_ring, true);
2095                 }
2096
2097                 if (ret) {
2098                         urb = td->urb;
2099                         urb_priv = urb->hcpriv;
2100                         /* Leave the TD around for the reset endpoint function
2101                          * to use(but only if it's not a control endpoint,
2102                          * since we already queued the Set TR dequeue pointer
2103                          * command for stalled control endpoints).
2104                          */
2105                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2106                                 (trb_comp_code != COMP_STALL &&
2107                                         trb_comp_code != COMP_BABBLE))
2108                                 xhci_urb_free_priv(xhci, urb_priv);
2109
2110                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2111                         xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2112                                         "status = %d\n",
2113                                         urb, urb->actual_length, status);
2114                         spin_unlock(&xhci->lock);
2115                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2116                         spin_lock(&xhci->lock);
2117                 }
2118
2119         /*
2120          * If ep->skip is set, it means there are missed tds on the
2121          * endpoint ring need to take care of.
2122          * Process them as short transfer until reach the td pointed by
2123          * the event.
2124          */
2125         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2126
2127         return 0;
2128 }
2129
2130 /*
2131  * This function handles all OS-owned events on the event ring.  It may drop
2132  * xhci->lock between event processing (e.g. to pass up port status changes).
2133  */
2134 static void xhci_handle_event(struct xhci_hcd *xhci)
2135 {
2136         union xhci_trb *event;
2137         int update_ptrs = 1;
2138         int ret;
2139
2140         xhci_dbg(xhci, "In %s\n", __func__);
2141         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2142                 xhci->error_bitmask |= 1 << 1;
2143                 return;
2144         }
2145
2146         event = xhci->event_ring->dequeue;
2147         /* Does the HC or OS own the TRB? */
2148         if ((event->event_cmd.flags & TRB_CYCLE) !=
2149                         xhci->event_ring->cycle_state) {
2150                 xhci->error_bitmask |= 1 << 2;
2151                 return;
2152         }
2153         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
2154
2155         /* FIXME: Handle more event types. */
2156         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
2157         case TRB_TYPE(TRB_COMPLETION):
2158                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
2159                 handle_cmd_completion(xhci, &event->event_cmd);
2160                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
2161                 break;
2162         case TRB_TYPE(TRB_PORT_STATUS):
2163                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
2164                 handle_port_status(xhci, event);
2165                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
2166                 update_ptrs = 0;
2167                 break;
2168         case TRB_TYPE(TRB_TRANSFER):
2169                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
2170                 ret = handle_tx_event(xhci, &event->trans_event);
2171                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
2172                 if (ret < 0)
2173                         xhci->error_bitmask |= 1 << 9;
2174                 else
2175                         update_ptrs = 0;
2176                 break;
2177         default:
2178                 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
2179                         handle_vendor_event(xhci, event);
2180                 else
2181                         xhci->error_bitmask |= 1 << 3;
2182         }
2183         /* Any of the above functions may drop and re-acquire the lock, so check
2184          * to make sure a watchdog timer didn't mark the host as non-responsive.
2185          */
2186         if (xhci->xhc_state & XHCI_STATE_DYING) {
2187                 xhci_dbg(xhci, "xHCI host dying, returning from "
2188                                 "event handler.\n");
2189                 return;
2190         }
2191
2192         if (update_ptrs)
2193                 /* Update SW event ring dequeue pointer */
2194                 inc_deq(xhci, xhci->event_ring, true);
2195
2196         /* Are there more items on the event ring? */
2197         xhci_handle_event(xhci);
2198 }
2199
2200 /*
2201  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2202  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2203  * indicators of an event TRB error, but we check the status *first* to be safe.
2204  */
2205 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2206 {
2207         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2208         u32 status;
2209         union xhci_trb *trb;
2210         u64 temp_64;
2211         union xhci_trb *event_ring_deq;
2212         dma_addr_t deq;
2213
2214         spin_lock(&xhci->lock);
2215         trb = xhci->event_ring->dequeue;
2216         /* Check if the xHC generated the interrupt, or the irq is shared */
2217         status = xhci_readl(xhci, &xhci->op_regs->status);
2218         if (status == 0xffffffff)
2219                 goto hw_died;
2220
2221         if (!(status & STS_EINT)) {
2222                 spin_unlock(&xhci->lock);
2223                 return IRQ_NONE;
2224         }
2225         xhci_dbg(xhci, "op reg status = %08x\n", status);
2226         xhci_dbg(xhci, "Event ring dequeue ptr:\n");
2227         xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
2228                         (unsigned long long)
2229                         xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
2230                         lower_32_bits(trb->link.segment_ptr),
2231                         upper_32_bits(trb->link.segment_ptr),
2232                         (unsigned int) trb->link.intr_target,
2233                         (unsigned int) trb->link.control);
2234
2235         if (status & STS_FATAL) {
2236                 xhci_warn(xhci, "WARNING: Host System Error\n");
2237                 xhci_halt(xhci);
2238 hw_died:
2239                 spin_unlock(&xhci->lock);
2240                 return -ESHUTDOWN;
2241         }
2242
2243         /*
2244          * Clear the op reg interrupt status first,
2245          * so we can receive interrupts from other MSI-X interrupters.
2246          * Write 1 to clear the interrupt status.
2247          */
2248         status |= STS_EINT;
2249         xhci_writel(xhci, status, &xhci->op_regs->status);
2250         /* FIXME when MSI-X is supported and there are multiple vectors */
2251         /* Clear the MSI-X event interrupt status */
2252
2253         if (hcd->irq != -1) {
2254                 u32 irq_pending;
2255                 /* Acknowledge the PCI interrupt */
2256                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2257                 irq_pending |= 0x3;
2258                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2259         }
2260
2261         if (xhci->xhc_state & XHCI_STATE_DYING) {
2262                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2263                                 "Shouldn't IRQs be disabled?\n");
2264                 /* Clear the event handler busy flag (RW1C);
2265                  * the event ring should be empty.
2266                  */
2267                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2268                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2269                                 &xhci->ir_set->erst_dequeue);
2270                 spin_unlock(&xhci->lock);
2271
2272                 return IRQ_HANDLED;
2273         }
2274
2275         event_ring_deq = xhci->event_ring->dequeue;
2276         /* FIXME this should be a delayed service routine
2277          * that clears the EHB.
2278          */
2279         xhci_handle_event(xhci);
2280
2281         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2282         /* If necessary, update the HW's version of the event ring deq ptr. */
2283         if (event_ring_deq != xhci->event_ring->dequeue) {
2284                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2285                                 xhci->event_ring->dequeue);
2286                 if (deq == 0)
2287                         xhci_warn(xhci, "WARN something wrong with SW event "
2288                                         "ring dequeue ptr.\n");
2289                 /* Update HC event ring dequeue pointer */
2290                 temp_64 &= ERST_PTR_MASK;
2291                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2292         }
2293
2294         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2295         temp_64 |= ERST_EHB;
2296         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2297
2298         spin_unlock(&xhci->lock);
2299
2300         return IRQ_HANDLED;
2301 }
2302
2303 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2304 {
2305         irqreturn_t ret;
2306         struct xhci_hcd *xhci;
2307
2308         xhci = hcd_to_xhci(hcd);
2309         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2310         if (xhci->shared_hcd)
2311                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2312
2313         ret = xhci_irq(hcd);
2314
2315         return ret;
2316 }
2317
2318 /****           Endpoint Ring Operations        ****/
2319
2320 /*
2321  * Generic function for queueing a TRB on a ring.
2322  * The caller must have checked to make sure there's room on the ring.
2323  *
2324  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2325  *                      prepare_transfer()?
2326  */
2327 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2328                 bool consumer, bool more_trbs_coming,
2329                 u32 field1, u32 field2, u32 field3, u32 field4)
2330 {
2331         struct xhci_generic_trb *trb;
2332
2333         trb = &ring->enqueue->generic;
2334         trb->field[0] = field1;
2335         trb->field[1] = field2;
2336         trb->field[2] = field3;
2337         trb->field[3] = field4;
2338         inc_enq(xhci, ring, consumer, more_trbs_coming);
2339 }
2340
2341 /*
2342  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2343  * FIXME allocate segments if the ring is full.
2344  */
2345 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2346                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2347 {
2348         /* Make sure the endpoint has been added to xHC schedule */
2349         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2350         switch (ep_state) {
2351         case EP_STATE_DISABLED:
2352                 /*
2353                  * USB core changed config/interfaces without notifying us,
2354                  * or hardware is reporting the wrong state.
2355                  */
2356                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2357                 return -ENOENT;
2358         case EP_STATE_ERROR:
2359                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2360                 /* FIXME event handling code for error needs to clear it */
2361                 /* XXX not sure if this should be -ENOENT or not */
2362                 return -EINVAL;
2363         case EP_STATE_HALTED:
2364                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2365         case EP_STATE_STOPPED:
2366         case EP_STATE_RUNNING:
2367                 break;
2368         default:
2369                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2370                 /*
2371                  * FIXME issue Configure Endpoint command to try to get the HC
2372                  * back into a known state.
2373                  */
2374                 return -EINVAL;
2375         }
2376         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2377                 /* FIXME allocate more room */
2378                 xhci_err(xhci, "ERROR no room on ep ring\n");
2379                 return -ENOMEM;
2380         }
2381
2382         if (enqueue_is_link_trb(ep_ring)) {
2383                 struct xhci_ring *ring = ep_ring;
2384                 union xhci_trb *next;
2385
2386                 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2387                 next = ring->enqueue;
2388
2389                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2390
2391                         /* If we're not dealing with 0.95 hardware,
2392                          * clear the chain bit.
2393                          */
2394                         if (!xhci_link_trb_quirk(xhci))
2395                                 next->link.control &= ~TRB_CHAIN;
2396                         else
2397                                 next->link.control |= TRB_CHAIN;
2398
2399                         wmb();
2400                         next->link.control ^= (u32) TRB_CYCLE;
2401
2402                         /* Toggle the cycle bit after the last ring segment. */
2403                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2404                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2405                                 if (!in_interrupt()) {
2406                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2407                                                 "state for ring %p = %i\n",
2408                                                 ring, (unsigned int)ring->cycle_state);
2409                                 }
2410                         }
2411                         ring->enq_seg = ring->enq_seg->next;
2412                         ring->enqueue = ring->enq_seg->trbs;
2413                         next = ring->enqueue;
2414                 }
2415         }
2416
2417         return 0;
2418 }
2419
2420 static int prepare_transfer(struct xhci_hcd *xhci,
2421                 struct xhci_virt_device *xdev,
2422                 unsigned int ep_index,
2423                 unsigned int stream_id,
2424                 unsigned int num_trbs,
2425                 struct urb *urb,
2426                 unsigned int td_index,
2427                 gfp_t mem_flags)
2428 {
2429         int ret;
2430         struct urb_priv *urb_priv;
2431         struct xhci_td  *td;
2432         struct xhci_ring *ep_ring;
2433         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2434
2435         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2436         if (!ep_ring) {
2437                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2438                                 stream_id);
2439                 return -EINVAL;
2440         }
2441
2442         ret = prepare_ring(xhci, ep_ring,
2443                         ep_ctx->ep_info & EP_STATE_MASK,
2444                         num_trbs, mem_flags);
2445         if (ret)
2446                 return ret;
2447
2448         urb_priv = urb->hcpriv;
2449         td = urb_priv->td[td_index];
2450
2451         INIT_LIST_HEAD(&td->td_list);
2452         INIT_LIST_HEAD(&td->cancelled_td_list);
2453
2454         if (td_index == 0) {
2455                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2456                 if (unlikely(ret)) {
2457                         xhci_urb_free_priv(xhci, urb_priv);
2458                         urb->hcpriv = NULL;
2459                         return ret;
2460                 }
2461         }
2462
2463         td->urb = urb;
2464         /* Add this TD to the tail of the endpoint ring's TD list */
2465         list_add_tail(&td->td_list, &ep_ring->td_list);
2466         td->start_seg = ep_ring->enq_seg;
2467         td->first_trb = ep_ring->enqueue;
2468
2469         urb_priv->td[td_index] = td;
2470
2471         return 0;
2472 }
2473
2474 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2475 {
2476         int num_sgs, num_trbs, running_total, temp, i;
2477         struct scatterlist *sg;
2478
2479         sg = NULL;
2480         num_sgs = urb->num_sgs;
2481         temp = urb->transfer_buffer_length;
2482
2483         xhci_dbg(xhci, "count sg list trbs: \n");
2484         num_trbs = 0;
2485         for_each_sg(urb->sg, sg, num_sgs, i) {
2486                 unsigned int previous_total_trbs = num_trbs;
2487                 unsigned int len = sg_dma_len(sg);
2488
2489                 /* Scatter gather list entries may cross 64KB boundaries */
2490                 running_total = TRB_MAX_BUFF_SIZE -
2491                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2492                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2493                 if (running_total != 0)
2494                         num_trbs++;
2495
2496                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2497                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2498                         num_trbs++;
2499                         running_total += TRB_MAX_BUFF_SIZE;
2500                 }
2501                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2502                                 i, (unsigned long long)sg_dma_address(sg),
2503                                 len, len, num_trbs - previous_total_trbs);
2504
2505                 len = min_t(int, len, temp);
2506                 temp -= len;
2507                 if (temp == 0)
2508                         break;
2509         }
2510         xhci_dbg(xhci, "\n");
2511         if (!in_interrupt())
2512                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2513                                 "num_trbs = %d\n",
2514                                 urb->ep->desc.bEndpointAddress,
2515                                 urb->transfer_buffer_length,
2516                                 num_trbs);
2517         return num_trbs;
2518 }
2519
2520 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2521 {
2522         if (num_trbs != 0)
2523                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2524                                 "TRBs, %d left\n", __func__,
2525                                 urb->ep->desc.bEndpointAddress, num_trbs);
2526         if (running_total != urb->transfer_buffer_length)
2527                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2528                                 "queued %#x (%d), asked for %#x (%d)\n",
2529                                 __func__,
2530                                 urb->ep->desc.bEndpointAddress,
2531                                 running_total, running_total,
2532                                 urb->transfer_buffer_length,
2533                                 urb->transfer_buffer_length);
2534 }
2535
2536 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2537                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2538                 struct xhci_generic_trb *start_trb)
2539 {
2540         /*
2541          * Pass all the TRBs to the hardware at once and make sure this write
2542          * isn't reordered.
2543          */
2544         wmb();
2545         if (start_cycle)
2546                 start_trb->field[3] |= start_cycle;
2547         else
2548                 start_trb->field[3] &= ~0x1;
2549         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2550 }
2551
2552 /*
2553  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2554  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2555  * (comprised of sg list entries) can take several service intervals to
2556  * transmit.
2557  */
2558 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2559                 struct urb *urb, int slot_id, unsigned int ep_index)
2560 {
2561         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2562                         xhci->devs[slot_id]->out_ctx, ep_index);
2563         int xhci_interval;
2564         int ep_interval;
2565
2566         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2567         ep_interval = urb->interval;
2568         /* Convert to microframes */
2569         if (urb->dev->speed == USB_SPEED_LOW ||
2570                         urb->dev->speed == USB_SPEED_FULL)
2571                 ep_interval *= 8;
2572         /* FIXME change this to a warning and a suggestion to use the new API
2573          * to set the polling interval (once the API is added).
2574          */
2575         if (xhci_interval != ep_interval) {
2576                 if (printk_ratelimit())
2577                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2578                                         " (%d microframe%s) than xHCI "
2579                                         "(%d microframe%s)\n",
2580                                         ep_interval,
2581                                         ep_interval == 1 ? "" : "s",
2582                                         xhci_interval,
2583                                         xhci_interval == 1 ? "" : "s");
2584                 urb->interval = xhci_interval;
2585                 /* Convert back to frames for LS/FS devices */
2586                 if (urb->dev->speed == USB_SPEED_LOW ||
2587                                 urb->dev->speed == USB_SPEED_FULL)
2588                         urb->interval /= 8;
2589         }
2590         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2591 }
2592
2593 /*
2594  * The TD size is the number of bytes remaining in the TD (including this TRB),
2595  * right shifted by 10.
2596  * It must fit in bits 21:17, so it can't be bigger than 31.
2597  */
2598 static u32 xhci_td_remainder(unsigned int remainder)
2599 {
2600         u32 max = (1 << (21 - 17 + 1)) - 1;
2601
2602         if ((remainder >> 10) >= max)
2603                 return max << 17;
2604         else
2605                 return (remainder >> 10) << 17;
2606 }
2607
2608 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2609                 struct urb *urb, int slot_id, unsigned int ep_index)
2610 {
2611         struct xhci_ring *ep_ring;
2612         unsigned int num_trbs;
2613         struct urb_priv *urb_priv;
2614         struct xhci_td *td;
2615         struct scatterlist *sg;
2616         int num_sgs;
2617         int trb_buff_len, this_sg_len, running_total;
2618         bool first_trb;
2619         u64 addr;
2620         bool more_trbs_coming;
2621
2622         struct xhci_generic_trb *start_trb;
2623         int start_cycle;
2624
2625         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2626         if (!ep_ring)
2627                 return -EINVAL;
2628
2629         num_trbs = count_sg_trbs_needed(xhci, urb);
2630         num_sgs = urb->num_sgs;
2631
2632         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2633                         ep_index, urb->stream_id,
2634                         num_trbs, urb, 0, mem_flags);
2635         if (trb_buff_len < 0)
2636                 return trb_buff_len;
2637
2638         urb_priv = urb->hcpriv;
2639         td = urb_priv->td[0];
2640
2641         /*
2642          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2643          * until we've finished creating all the other TRBs.  The ring's cycle
2644          * state may change as we enqueue the other TRBs, so save it too.
2645          */
2646         start_trb = &ep_ring->enqueue->generic;
2647         start_cycle = ep_ring->cycle_state;
2648
2649         running_total = 0;
2650         /*
2651          * How much data is in the first TRB?
2652          *
2653          * There are three forces at work for TRB buffer pointers and lengths:
2654          * 1. We don't want to walk off the end of this sg-list entry buffer.
2655          * 2. The transfer length that the driver requested may be smaller than
2656          *    the amount of memory allocated for this scatter-gather list.
2657          * 3. TRBs buffers can't cross 64KB boundaries.
2658          */
2659         sg = urb->sg;
2660         addr = (u64) sg_dma_address(sg);
2661         this_sg_len = sg_dma_len(sg);
2662         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2663         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2664         if (trb_buff_len > urb->transfer_buffer_length)
2665                 trb_buff_len = urb->transfer_buffer_length;
2666         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2667                         trb_buff_len);
2668
2669         first_trb = true;
2670         /* Queue the first TRB, even if it's zero-length */
2671         do {
2672                 u32 field = 0;
2673                 u32 length_field = 0;
2674                 u32 remainder = 0;
2675
2676                 /* Don't change the cycle bit of the first TRB until later */
2677                 if (first_trb) {
2678                         first_trb = false;
2679                         if (start_cycle == 0)
2680                                 field |= 0x1;
2681                 } else
2682                         field |= ep_ring->cycle_state;
2683
2684                 /* Chain all the TRBs together; clear the chain bit in the last
2685                  * TRB to indicate it's the last TRB in the chain.
2686                  */
2687                 if (num_trbs > 1) {
2688                         field |= TRB_CHAIN;
2689                 } else {
2690                         /* FIXME - add check for ZERO_PACKET flag before this */
2691                         td->last_trb = ep_ring->enqueue;
2692                         field |= TRB_IOC;
2693                 }
2694                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2695                                 "64KB boundary at %#x, end dma = %#x\n",
2696                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2697                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2698                                 (unsigned int) addr + trb_buff_len);
2699                 if (TRB_MAX_BUFF_SIZE -
2700                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2701                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2702                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2703                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2704                                         (unsigned int) addr + trb_buff_len);
2705                 }
2706                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2707                                 running_total) ;
2708                 length_field = TRB_LEN(trb_buff_len) |
2709                         remainder |
2710                         TRB_INTR_TARGET(0);
2711                 if (num_trbs > 1)
2712                         more_trbs_coming = true;
2713                 else
2714                         more_trbs_coming = false;
2715                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2716                                 lower_32_bits(addr),
2717                                 upper_32_bits(addr),
2718                                 length_field,
2719                                 /* We always want to know if the TRB was short,
2720                                  * or we won't get an event when it completes.
2721                                  * (Unless we use event data TRBs, which are a
2722                                  * waste of space and HC resources.)
2723                                  */
2724                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2725                 --num_trbs;
2726                 running_total += trb_buff_len;
2727
2728                 /* Calculate length for next transfer --
2729                  * Are we done queueing all the TRBs for this sg entry?
2730                  */
2731                 this_sg_len -= trb_buff_len;
2732                 if (this_sg_len == 0) {
2733                         --num_sgs;
2734                         if (num_sgs == 0)
2735                                 break;
2736                         sg = sg_next(sg);
2737                         addr = (u64) sg_dma_address(sg);
2738                         this_sg_len = sg_dma_len(sg);
2739                 } else {
2740                         addr += trb_buff_len;
2741                 }
2742
2743                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2744                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2745                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2746                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2747                         trb_buff_len =
2748                                 urb->transfer_buffer_length - running_total;
2749         } while (running_total < urb->transfer_buffer_length);
2750
2751         check_trb_math(urb, num_trbs, running_total);
2752         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2753                         start_cycle, start_trb);
2754         return 0;
2755 }
2756
2757 /* This is very similar to what ehci-q.c qtd_fill() does */
2758 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2759                 struct urb *urb, int slot_id, unsigned int ep_index)
2760 {
2761         struct xhci_ring *ep_ring;
2762         struct urb_priv *urb_priv;
2763         struct xhci_td *td;
2764         int num_trbs;
2765         struct xhci_generic_trb *start_trb;
2766         bool first_trb;
2767         bool more_trbs_coming;
2768         int start_cycle;
2769         u32 field, length_field;
2770
2771         int running_total, trb_buff_len, ret;
2772         u64 addr;
2773
2774         if (urb->num_sgs)
2775                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2776
2777         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2778         if (!ep_ring)
2779                 return -EINVAL;
2780
2781         num_trbs = 0;
2782         /* How much data is (potentially) left before the 64KB boundary? */
2783         running_total = TRB_MAX_BUFF_SIZE -
2784                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2785         running_total &= TRB_MAX_BUFF_SIZE - 1;
2786
2787         /* If there's some data on this 64KB chunk, or we have to send a
2788          * zero-length transfer, we need at least one TRB
2789          */
2790         if (running_total != 0 || urb->transfer_buffer_length == 0)
2791                 num_trbs++;
2792         /* How many more 64KB chunks to transfer, how many more TRBs? */
2793         while (running_total < urb->transfer_buffer_length) {
2794                 num_trbs++;
2795                 running_total += TRB_MAX_BUFF_SIZE;
2796         }
2797         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2798
2799         if (!in_interrupt())
2800                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2801                                 "addr = %#llx, num_trbs = %d\n",
2802                                 urb->ep->desc.bEndpointAddress,
2803                                 urb->transfer_buffer_length,
2804                                 urb->transfer_buffer_length,
2805                                 (unsigned long long)urb->transfer_dma,
2806                                 num_trbs);
2807
2808         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2809                         ep_index, urb->stream_id,
2810                         num_trbs, urb, 0, mem_flags);
2811         if (ret < 0)
2812                 return ret;
2813
2814         urb_priv = urb->hcpriv;
2815         td = urb_priv->td[0];
2816
2817         /*
2818          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2819          * until we've finished creating all the other TRBs.  The ring's cycle
2820          * state may change as we enqueue the other TRBs, so save it too.
2821          */
2822         start_trb = &ep_ring->enqueue->generic;
2823         start_cycle = ep_ring->cycle_state;
2824
2825         running_total = 0;
2826         /* How much data is in the first TRB? */
2827         addr = (u64) urb->transfer_dma;
2828         trb_buff_len = TRB_MAX_BUFF_SIZE -
2829                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2830         if (trb_buff_len > urb->transfer_buffer_length)
2831                 trb_buff_len = urb->transfer_buffer_length;
2832
2833         first_trb = true;
2834
2835         /* Queue the first TRB, even if it's zero-length */
2836         do {
2837                 u32 remainder = 0;
2838                 field = 0;
2839
2840                 /* Don't change the cycle bit of the first TRB until later */
2841                 if (first_trb) {
2842                         first_trb = false;
2843                         if (start_cycle == 0)
2844                                 field |= 0x1;
2845                 } else
2846                         field |= ep_ring->cycle_state;
2847
2848                 /* Chain all the TRBs together; clear the chain bit in the last
2849                  * TRB to indicate it's the last TRB in the chain.
2850                  */
2851                 if (num_trbs > 1) {
2852                         field |= TRB_CHAIN;
2853                 } else {
2854                         /* FIXME - add check for ZERO_PACKET flag before this */
2855                         td->last_trb = ep_ring->enqueue;
2856                         field |= TRB_IOC;
2857                 }
2858                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2859                                 running_total);
2860                 length_field = TRB_LEN(trb_buff_len) |
2861                         remainder |
2862                         TRB_INTR_TARGET(0);
2863                 if (num_trbs > 1)
2864                         more_trbs_coming = true;
2865                 else
2866                         more_trbs_coming = false;
2867                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2868                                 lower_32_bits(addr),
2869                                 upper_32_bits(addr),
2870                                 length_field,
2871                                 /* We always want to know if the TRB was short,
2872                                  * or we won't get an event when it completes.
2873                                  * (Unless we use event data TRBs, which are a
2874                                  * waste of space and HC resources.)
2875                                  */
2876                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2877                 --num_trbs;
2878                 running_total += trb_buff_len;
2879
2880                 /* Calculate length for next transfer */
2881                 addr += trb_buff_len;
2882                 trb_buff_len = urb->transfer_buffer_length - running_total;
2883                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2884                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2885         } while (running_total < urb->transfer_buffer_length);
2886
2887         check_trb_math(urb, num_trbs, running_total);
2888         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2889                         start_cycle, start_trb);
2890         return 0;
2891 }
2892
2893 /* Caller must have locked xhci->lock */
2894 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2895                 struct urb *urb, int slot_id, unsigned int ep_index)
2896 {
2897         struct xhci_ring *ep_ring;
2898         int num_trbs;
2899         int ret;
2900         struct usb_ctrlrequest *setup;
2901         struct xhci_generic_trb *start_trb;
2902         int start_cycle;
2903         u32 field, length_field;
2904         struct urb_priv *urb_priv;
2905         struct xhci_td *td;
2906
2907         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2908         if (!ep_ring)
2909                 return -EINVAL;
2910
2911         /*
2912          * Need to copy setup packet into setup TRB, so we can't use the setup
2913          * DMA address.
2914          */
2915         if (!urb->setup_packet)
2916                 return -EINVAL;
2917
2918         if (!in_interrupt())
2919                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2920                                 slot_id, ep_index);
2921         /* 1 TRB for setup, 1 for status */
2922         num_trbs = 2;
2923         /*
2924          * Don't need to check if we need additional event data and normal TRBs,
2925          * since data in control transfers will never get bigger than 16MB
2926          * XXX: can we get a buffer that crosses 64KB boundaries?
2927          */
2928         if (urb->transfer_buffer_length > 0)
2929                 num_trbs++;
2930         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2931                         ep_index, urb->stream_id,
2932                         num_trbs, urb, 0, mem_flags);
2933         if (ret < 0)
2934                 return ret;
2935
2936         urb_priv = urb->hcpriv;
2937         td = urb_priv->td[0];
2938
2939         /*
2940          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2941          * until we've finished creating all the other TRBs.  The ring's cycle
2942          * state may change as we enqueue the other TRBs, so save it too.
2943          */
2944         start_trb = &ep_ring->enqueue->generic;
2945         start_cycle = ep_ring->cycle_state;
2946
2947         /* Queue setup TRB - see section 6.4.1.2.1 */
2948         /* FIXME better way to translate setup_packet into two u32 fields? */
2949         setup = (struct usb_ctrlrequest *) urb->setup_packet;
2950         field = 0;
2951         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
2952         if (start_cycle == 0)
2953                 field |= 0x1;
2954         queue_trb(xhci, ep_ring, false, true,
2955                         /* FIXME endianness is probably going to bite my ass here. */
2956                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2957                         setup->wIndex | setup->wLength << 16,
2958                         TRB_LEN(8) | TRB_INTR_TARGET(0),
2959                         /* Immediate data in pointer */
2960                         field);
2961
2962         /* If there's data, queue data TRBs */
2963         field = 0;
2964         length_field = TRB_LEN(urb->transfer_buffer_length) |
2965                 xhci_td_remainder(urb->transfer_buffer_length) |
2966                 TRB_INTR_TARGET(0);
2967         if (urb->transfer_buffer_length > 0) {
2968                 if (setup->bRequestType & USB_DIR_IN)
2969                         field |= TRB_DIR_IN;
2970                 queue_trb(xhci, ep_ring, false, true,
2971                                 lower_32_bits(urb->transfer_dma),
2972                                 upper_32_bits(urb->transfer_dma),
2973                                 length_field,
2974                                 /* Event on short tx */
2975                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2976         }
2977
2978         /* Save the DMA address of the last TRB in the TD */
2979         td->last_trb = ep_ring->enqueue;
2980
2981         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2982         /* If the device sent data, the status stage is an OUT transfer */
2983         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2984                 field = 0;
2985         else
2986                 field = TRB_DIR_IN;
2987         queue_trb(xhci, ep_ring, false, false,
2988                         0,
2989                         0,
2990                         TRB_INTR_TARGET(0),
2991                         /* Event on completion */
2992                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2993
2994         giveback_first_trb(xhci, slot_id, ep_index, 0,
2995                         start_cycle, start_trb);
2996         return 0;
2997 }
2998
2999 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3000                 struct urb *urb, int i)
3001 {
3002         int num_trbs = 0;
3003         u64 addr, td_len, running_total;
3004
3005         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3006         td_len = urb->iso_frame_desc[i].length;
3007
3008         running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3009         running_total &= TRB_MAX_BUFF_SIZE - 1;
3010         if (running_total != 0)
3011                 num_trbs++;
3012
3013         while (running_total < td_len) {
3014                 num_trbs++;
3015                 running_total += TRB_MAX_BUFF_SIZE;
3016         }
3017
3018         return num_trbs;
3019 }
3020
3021 /* This is for isoc transfer */
3022 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3023                 struct urb *urb, int slot_id, unsigned int ep_index)
3024 {
3025         struct xhci_ring *ep_ring;
3026         struct urb_priv *urb_priv;
3027         struct xhci_td *td;
3028         int num_tds, trbs_per_td;
3029         struct xhci_generic_trb *start_trb;
3030         bool first_trb;
3031         int start_cycle;
3032         u32 field, length_field;
3033         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3034         u64 start_addr, addr;
3035         int i, j;
3036         bool more_trbs_coming;
3037
3038         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3039
3040         num_tds = urb->number_of_packets;
3041         if (num_tds < 1) {
3042                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3043                 return -EINVAL;
3044         }
3045
3046         if (!in_interrupt())
3047                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3048                                 " addr = %#llx, num_tds = %d\n",
3049                                 urb->ep->desc.bEndpointAddress,
3050                                 urb->transfer_buffer_length,
3051                                 urb->transfer_buffer_length,
3052                                 (unsigned long long)urb->transfer_dma,
3053                                 num_tds);
3054
3055         start_addr = (u64) urb->transfer_dma;
3056         start_trb = &ep_ring->enqueue->generic;
3057         start_cycle = ep_ring->cycle_state;
3058
3059         /* Queue the first TRB, even if it's zero-length */
3060         for (i = 0; i < num_tds; i++) {
3061                 first_trb = true;
3062
3063                 running_total = 0;
3064                 addr = start_addr + urb->iso_frame_desc[i].offset;
3065                 td_len = urb->iso_frame_desc[i].length;
3066                 td_remain_len = td_len;
3067
3068                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3069
3070                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3071                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3072                 if (ret < 0)
3073                         return ret;
3074
3075                 urb_priv = urb->hcpriv;
3076                 td = urb_priv->td[i];
3077
3078                 for (j = 0; j < trbs_per_td; j++) {
3079                         u32 remainder = 0;
3080                         field = 0;
3081
3082                         if (first_trb) {
3083                                 /* Queue the isoc TRB */
3084                                 field |= TRB_TYPE(TRB_ISOC);
3085                                 /* Assume URB_ISO_ASAP is set */
3086                                 field |= TRB_SIA;
3087                                 if (i == 0) {
3088                                         if (start_cycle == 0)
3089                                                 field |= 0x1;
3090                                 } else
3091                                         field |= ep_ring->cycle_state;
3092                                 first_trb = false;
3093                         } else {
3094                                 /* Queue other normal TRBs */
3095                                 field |= TRB_TYPE(TRB_NORMAL);
3096                                 field |= ep_ring->cycle_state;
3097                         }
3098
3099                         /* Chain all the TRBs together; clear the chain bit in
3100                          * the last TRB to indicate it's the last TRB in the
3101                          * chain.
3102                          */
3103                         if (j < trbs_per_td - 1) {
3104                                 field |= TRB_CHAIN;
3105                                 more_trbs_coming = true;
3106                         } else {
3107                                 td->last_trb = ep_ring->enqueue;
3108                                 field |= TRB_IOC;
3109                                 more_trbs_coming = false;
3110                         }
3111
3112                         /* Calculate TRB length */
3113                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3114                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3115                         if (trb_buff_len > td_remain_len)
3116                                 trb_buff_len = td_remain_len;
3117
3118                         remainder = xhci_td_remainder(td_len - running_total);
3119                         length_field = TRB_LEN(trb_buff_len) |
3120                                 remainder |
3121                                 TRB_INTR_TARGET(0);
3122                         queue_trb(xhci, ep_ring, false, more_trbs_coming,
3123                                 lower_32_bits(addr),
3124                                 upper_32_bits(addr),
3125                                 length_field,
3126                                 /* We always want to know if the TRB was short,
3127                                  * or we won't get an event when it completes.
3128                                  * (Unless we use event data TRBs, which are a
3129                                  * waste of space and HC resources.)
3130                                  */
3131                                 field | TRB_ISP);
3132                         running_total += trb_buff_len;
3133
3134                         addr += trb_buff_len;
3135                         td_remain_len -= trb_buff_len;
3136                 }
3137
3138                 /* Check TD length */
3139                 if (running_total != td_len) {
3140                         xhci_err(xhci, "ISOC TD length unmatch\n");
3141                         return -EINVAL;
3142                 }
3143         }
3144
3145         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3146                         start_cycle, start_trb);
3147         return 0;
3148 }
3149
3150 /*
3151  * Check transfer ring to guarantee there is enough room for the urb.
3152  * Update ISO URB start_frame and interval.
3153  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3154  * update the urb->start_frame by now.
3155  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3156  */
3157 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3158                 struct urb *urb, int slot_id, unsigned int ep_index)
3159 {
3160         struct xhci_virt_device *xdev;
3161         struct xhci_ring *ep_ring;
3162         struct xhci_ep_ctx *ep_ctx;
3163         int start_frame;
3164         int xhci_interval;
3165         int ep_interval;
3166         int num_tds, num_trbs, i;
3167         int ret;
3168
3169         xdev = xhci->devs[slot_id];
3170         ep_ring = xdev->eps[ep_index].ring;
3171         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3172
3173         num_trbs = 0;
3174         num_tds = urb->number_of_packets;
3175         for (i = 0; i < num_tds; i++)
3176                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3177
3178         /* Check the ring to guarantee there is enough room for the whole urb.
3179          * Do not insert any td of the urb to the ring if the check failed.
3180          */
3181         ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
3182                                 num_trbs, mem_flags);
3183         if (ret)
3184                 return ret;
3185
3186         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3187         start_frame &= 0x3fff;
3188
3189         urb->start_frame = start_frame;
3190         if (urb->dev->speed == USB_SPEED_LOW ||
3191                         urb->dev->speed == USB_SPEED_FULL)
3192                 urb->start_frame >>= 3;
3193
3194         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
3195         ep_interval = urb->interval;
3196         /* Convert to microframes */
3197         if (urb->dev->speed == USB_SPEED_LOW ||
3198                         urb->dev->speed == USB_SPEED_FULL)
3199                 ep_interval *= 8;
3200         /* FIXME change this to a warning and a suggestion to use the new API
3201          * to set the polling interval (once the API is added).
3202          */
3203         if (xhci_interval != ep_interval) {
3204                 if (printk_ratelimit())
3205                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3206                                         " (%d microframe%s) than xHCI "
3207                                         "(%d microframe%s)\n",
3208                                         ep_interval,
3209                                         ep_interval == 1 ? "" : "s",
3210                                         xhci_interval,
3211                                         xhci_interval == 1 ? "" : "s");
3212                 urb->interval = xhci_interval;
3213                 /* Convert back to frames for LS/FS devices */
3214                 if (urb->dev->speed == USB_SPEED_LOW ||
3215                                 urb->dev->speed == USB_SPEED_FULL)
3216                         urb->interval /= 8;
3217         }
3218         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3219 }
3220
3221 /****           Command Ring Operations         ****/
3222
3223 /* Generic function for queueing a command TRB on the command ring.
3224  * Check to make sure there's room on the command ring for one command TRB.
3225  * Also check that there's room reserved for commands that must not fail.
3226  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3227  * then only check for the number of reserved spots.
3228  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3229  * because the command event handler may want to resubmit a failed command.
3230  */
3231 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3232                 u32 field3, u32 field4, bool command_must_succeed)
3233 {
3234         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3235         int ret;
3236
3237         if (!command_must_succeed)
3238                 reserved_trbs++;
3239
3240         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3241                         reserved_trbs, GFP_ATOMIC);
3242         if (ret < 0) {
3243                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3244                 if (command_must_succeed)
3245                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3246                                         "unfailable commands failed.\n");
3247                 return ret;
3248         }
3249         queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3250                         field4 | xhci->cmd_ring->cycle_state);
3251         return 0;
3252 }
3253
3254 /* Queue a slot enable or disable request on the command ring */
3255 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3256 {
3257         return queue_command(xhci, 0, 0, 0,
3258                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3259 }
3260
3261 /* Queue an address device command TRB */
3262 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3263                 u32 slot_id)
3264 {
3265         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3266                         upper_32_bits(in_ctx_ptr), 0,
3267                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3268                         false);
3269 }
3270
3271 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3272                 u32 field1, u32 field2, u32 field3, u32 field4)
3273 {
3274         return queue_command(xhci, field1, field2, field3, field4, false);
3275 }
3276
3277 /* Queue a reset device command TRB */
3278 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3279 {
3280         return queue_command(xhci, 0, 0, 0,
3281                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3282                         false);
3283 }
3284
3285 /* Queue a configure endpoint command TRB */
3286 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3287                 u32 slot_id, bool command_must_succeed)
3288 {
3289         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3290                         upper_32_bits(in_ctx_ptr), 0,
3291                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3292                         command_must_succeed);
3293 }
3294
3295 /* Queue an evaluate context command TRB */
3296 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3297                 u32 slot_id)
3298 {
3299         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3300                         upper_32_bits(in_ctx_ptr), 0,
3301                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3302                         false);
3303 }
3304
3305 /*
3306  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3307  * activity on an endpoint that is about to be suspended.
3308  */
3309 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3310                 unsigned int ep_index, int suspend)
3311 {
3312         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3313         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3314         u32 type = TRB_TYPE(TRB_STOP_RING);
3315         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3316
3317         return queue_command(xhci, 0, 0, 0,
3318                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3319 }
3320
3321 /* Set Transfer Ring Dequeue Pointer command.
3322  * This should not be used for endpoints that have streams enabled.
3323  */
3324 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3325                 unsigned int ep_index, unsigned int stream_id,
3326                 struct xhci_segment *deq_seg,
3327                 union xhci_trb *deq_ptr, u32 cycle_state)
3328 {
3329         dma_addr_t addr;
3330         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3331         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3332         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3333         u32 type = TRB_TYPE(TRB_SET_DEQ);
3334         struct xhci_virt_ep *ep;
3335
3336         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3337         if (addr == 0) {
3338                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3339                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3340                                 deq_seg, deq_ptr);
3341                 return 0;
3342         }
3343         ep = &xhci->devs[slot_id]->eps[ep_index];
3344         if ((ep->ep_state & SET_DEQ_PENDING)) {
3345                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3346                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3347                 return 0;
3348         }
3349         ep->queued_deq_seg = deq_seg;
3350         ep->queued_deq_ptr = deq_ptr;
3351         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3352                         upper_32_bits(addr), trb_stream_id,
3353                         trb_slot_id | trb_ep_index | type, false);
3354 }
3355
3356 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3357                 unsigned int ep_index)
3358 {
3359         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3360         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3361         u32 type = TRB_TYPE(TRB_RESET_EP);
3362
3363         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3364                         false);
3365 }