2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
82 unsigned long segment_offset;
84 if (!seg || !trb || trb < seg->trbs)
87 segment_offset = trb - seg->trbs;
88 if (segment_offset >= TRBS_PER_SEGMENT)
90 return seg->dma + (segment_offset * sizeof(*trb));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
116 return TRB_TYPE_LINK_LE32(trb->link.control);
119 static int enqueue_is_link_trb(struct xhci_ring *ring)
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
134 if (last_trb(xhci, ring, *seg, *trb)) {
136 *trb = ((*seg)->trbs);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
148 unsigned long long addr;
154 * Update the dequeue pointer further if that was a link TRB or
155 * we're at the end of an event ring segment (which doesn't have
158 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
159 if (consumer && last_trb_on_last_seg(xhci, ring,
160 ring->deq_seg, ring->dequeue)) {
162 xhci_dbg(xhci, "Toggle cycle state "
163 "for ring %p = %i\n",
167 ring->cycle_state = (ring->cycle_state ? 0 : 1);
169 ring->deq_seg = ring->deq_seg->next;
170 ring->dequeue = ring->deq_seg->trbs;
174 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
180 * See Cycle bit rules. SW is the consumer for the event ring only.
181 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
183 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
184 * chain bit is set), then set the chain bit in all the following link TRBs.
185 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
186 * have their chain bit cleared (so that each Link TRB is a separate TD).
188 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
189 * set, but other sections talk about dealing with the chain bit set. This was
190 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
191 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
193 * @more_trbs_coming: Will you enqueue more TRBs before calling
194 * prepare_transfer()?
196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
197 bool consumer, bool more_trbs_coming, bool isoc)
200 union xhci_trb *next;
201 unsigned long long addr;
203 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
204 next = ++(ring->enqueue);
207 /* Update the dequeue pointer further if that was a link TRB or we're at
208 * the end of an event ring segment (which doesn't have link TRBS)
210 while (last_trb(xhci, ring, ring->enq_seg, next)) {
212 if (ring != xhci->event_ring) {
214 * If the caller doesn't plan on enqueueing more
215 * TDs before ringing the doorbell, then we
216 * don't want to give the link TRB to the
217 * hardware just yet. We'll give the link TRB
218 * back in prepare_ring() just before we enqueue
219 * the TD at the top of the ring.
221 if (!chain && !more_trbs_coming)
224 /* If we're not dealing with 0.95 hardware or
225 * isoc rings on AMD 0.96 host,
226 * carry over the chain bit of the previous TRB
227 * (which may mean the chain bit is cleared).
229 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
230 && !xhci_link_trb_quirk(xhci)) {
231 next->link.control &=
232 cpu_to_le32(~TRB_CHAIN);
233 next->link.control |=
236 /* Give this link TRB to the hardware */
238 next->link.control ^= cpu_to_le32(TRB_CYCLE);
240 /* Toggle the cycle bit after the last ring segment. */
241 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
242 ring->cycle_state = (ring->cycle_state ? 0 : 1);
244 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
246 (unsigned int) ring->cycle_state);
249 ring->enq_seg = ring->enq_seg->next;
250 ring->enqueue = ring->enq_seg->trbs;
251 next = ring->enqueue;
253 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
257 * Check to see if there's room to enqueue num_trbs on the ring. See rules
259 * FIXME: this would be simpler and faster if we just kept track of the number
260 * of free TRBs in a ring.
262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
263 unsigned int num_trbs)
266 union xhci_trb *enq = ring->enqueue;
267 struct xhci_segment *enq_seg = ring->enq_seg;
268 struct xhci_segment *cur_seg;
269 unsigned int left_on_ring;
271 /* If we are currently pointing to a link TRB, advance the
272 * enqueue pointer before checking for space */
273 while (last_trb(xhci, ring, enq_seg, enq)) {
274 enq_seg = enq_seg->next;
278 /* Check if ring is empty */
279 if (enq == ring->dequeue) {
280 /* Can't use link trbs */
281 left_on_ring = TRBS_PER_SEGMENT - 1;
282 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
283 cur_seg = cur_seg->next)
284 left_on_ring += TRBS_PER_SEGMENT - 1;
286 /* Always need one TRB free in the ring. */
288 if (num_trbs > left_on_ring) {
289 xhci_warn(xhci, "Not enough room on ring; "
290 "need %u TRBs, %u TRBs left\n",
291 num_trbs, left_on_ring);
296 /* Make sure there's an extra empty TRB available */
297 for (i = 0; i <= num_trbs; ++i) {
298 if (enq == ring->dequeue)
301 while (last_trb(xhci, ring, enq_seg, enq)) {
302 enq_seg = enq_seg->next;
309 /* Ring the host controller doorbell after placing a command on the ring */
310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
312 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
315 xhci_dbg(xhci, "// Ding dong!\n");
316 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
317 /* Flush PCI posted writes */
318 xhci_readl(xhci, &xhci->dba->doorbell[0]);
321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
326 xhci_dbg(xhci, "Abort command ring\n");
328 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
329 xhci_dbg(xhci, "The command ring isn't running, "
330 "Have the command ring been stopped?\n");
334 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
335 if (!(temp_64 & CMD_RING_RUNNING)) {
336 xhci_dbg(xhci, "Command ring had been stopped\n");
339 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
340 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
341 &xhci->op_regs->cmd_ring);
343 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
344 * time the completion od all xHCI commands, including
345 * the Command Abort operation. If software doesn't see
346 * CRR negated in a timely manner (e.g. longer than 5
347 * seconds), then it should assume that the there are
348 * larger problems with the xHC and assert HCRST.
350 ret = handshake(xhci, &xhci->op_regs->cmd_ring,
351 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
353 /* we are about to kill xhci, give it one more chance */
354 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
355 &xhci->op_regs->cmd_ring);
357 ret = handshake(xhci, &xhci->op_regs->cmd_ring,
358 CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
362 xhci_err(xhci, "Stopped the command ring failed, "
363 "maybe the host is dead\n");
364 xhci->xhc_state |= XHCI_STATE_DYING;
373 static int xhci_queue_cd(struct xhci_hcd *xhci,
374 struct xhci_command *command,
375 union xhci_trb *cmd_trb)
378 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
381 INIT_LIST_HEAD(&cd->cancel_cmd_list);
383 cd->command = command;
384 cd->cmd_trb = cmd_trb;
385 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
391 * Cancel the command which has issue.
393 * Some commands may hang due to waiting for acknowledgement from
394 * usb device. It is outside of the xHC's ability to control and
395 * will cause the command ring is blocked. When it occurs software
396 * should intervene to recover the command ring.
397 * See Section 4.6.1.1 and 4.6.1.2
399 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
400 union xhci_trb *cmd_trb)
405 spin_lock_irqsave(&xhci->lock, flags);
407 if (xhci->xhc_state & XHCI_STATE_DYING) {
408 xhci_warn(xhci, "Abort the command ring,"
409 " but the xHCI is dead.\n");
414 /* queue the cmd desriptor to cancel_cmd_list */
415 retval = xhci_queue_cd(xhci, command, cmd_trb);
417 xhci_warn(xhci, "Queuing command descriptor failed.\n");
421 /* abort command ring */
422 retval = xhci_abort_cmd_ring(xhci);
424 xhci_err(xhci, "Abort command ring failed\n");
425 if (unlikely(retval == -ESHUTDOWN)) {
426 spin_unlock_irqrestore(&xhci->lock, flags);
427 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
428 xhci_dbg(xhci, "xHCI host controller is dead.\n");
434 spin_unlock_irqrestore(&xhci->lock, flags);
438 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
439 unsigned int slot_id,
440 unsigned int ep_index,
441 unsigned int stream_id)
443 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
444 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
445 unsigned int ep_state = ep->ep_state;
447 /* Don't ring the doorbell for this endpoint if there are pending
448 * cancellations because we don't want to interrupt processing.
449 * We don't want to restart any stream rings if there's a set dequeue
450 * pointer command pending because the device can choose to start any
451 * stream once the endpoint is on the HW schedule.
452 * FIXME - check all the stream rings for pending cancellations.
454 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
455 (ep_state & EP_HALTED))
457 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
458 /* The CPU has better things to do at this point than wait for a
459 * write-posting flush. It'll get there soon enough.
463 /* Ring the doorbell for any rings with pending URBs */
464 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
465 unsigned int slot_id,
466 unsigned int ep_index)
468 unsigned int stream_id;
469 struct xhci_virt_ep *ep;
471 ep = &xhci->devs[slot_id]->eps[ep_index];
473 /* A ring has pending URBs if its TD list is not empty */
474 if (!(ep->ep_state & EP_HAS_STREAMS)) {
475 if (ep->ring && !(list_empty(&ep->ring->td_list)))
476 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
480 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
482 struct xhci_stream_info *stream_info = ep->stream_info;
483 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
484 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
490 * Find the segment that trb is in. Start searching in start_seg.
491 * If we must move past a segment that has a link TRB with a toggle cycle state
492 * bit set, then we will toggle the value pointed at by cycle_state.
494 static struct xhci_segment *find_trb_seg(
495 struct xhci_segment *start_seg,
496 union xhci_trb *trb, int *cycle_state)
498 struct xhci_segment *cur_seg = start_seg;
499 struct xhci_generic_trb *generic_trb;
501 while (cur_seg->trbs > trb ||
502 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
503 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
504 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
506 cur_seg = cur_seg->next;
507 if (cur_seg == start_seg)
508 /* Looped over the entire list. Oops! */
515 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
516 unsigned int slot_id, unsigned int ep_index,
517 unsigned int stream_id)
519 struct xhci_virt_ep *ep;
521 ep = &xhci->devs[slot_id]->eps[ep_index];
522 /* Common case: no streams */
523 if (!(ep->ep_state & EP_HAS_STREAMS))
526 if (stream_id == 0) {
528 "WARN: Slot ID %u, ep index %u has streams, "
529 "but URB has no stream ID.\n",
534 if (stream_id < ep->stream_info->num_streams)
535 return ep->stream_info->stream_rings[stream_id];
538 "WARN: Slot ID %u, ep index %u has "
539 "stream IDs 1 to %u allocated, "
540 "but stream ID %u is requested.\n",
542 ep->stream_info->num_streams - 1,
547 /* Get the right ring for the given URB.
548 * If the endpoint supports streams, boundary check the URB's stream ID.
549 * If the endpoint doesn't support streams, return the singular endpoint ring.
551 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
554 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
555 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
559 * Move the xHC's endpoint ring dequeue pointer past cur_td.
560 * Record the new state of the xHC's endpoint ring dequeue segment,
561 * dequeue pointer, and new consumer cycle state in state.
562 * Update our internal representation of the ring's dequeue pointer.
564 * We do this in three jumps:
565 * - First we update our new ring state to be the same as when the xHC stopped.
566 * - Then we traverse the ring to find the segment that contains
567 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
568 * any link TRBs with the toggle cycle bit set.
569 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
570 * if we've moved it past a link TRB with the toggle cycle bit set.
572 * Some of the uses of xhci_generic_trb are grotty, but if they're done
573 * with correct __le32 accesses they should work fine. Only users of this are
576 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
577 unsigned int slot_id, unsigned int ep_index,
578 unsigned int stream_id, struct xhci_td *cur_td,
579 struct xhci_dequeue_state *state)
581 struct xhci_virt_device *dev = xhci->devs[slot_id];
582 struct xhci_virt_ep *ep = &dev->eps[ep_index];
583 struct xhci_ring *ep_ring;
584 struct xhci_segment *new_seg;
585 union xhci_trb *new_deq;
588 bool cycle_found = false;
589 bool td_last_trb_found = false;
591 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
592 ep_index, stream_id);
594 xhci_warn(xhci, "WARN can't find new dequeue state "
595 "for invalid stream ID %u.\n",
600 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
601 xhci_dbg(xhci, "Finding endpoint context\n");
602 /* 4.6.9 the css flag is written to the stream context for streams */
603 if (ep->ep_state & EP_HAS_STREAMS) {
604 struct xhci_stream_ctx *ctx =
605 &ep->stream_info->stream_ctx_array[stream_id];
606 hw_dequeue = le64_to_cpu(ctx->stream_ring);
608 struct xhci_ep_ctx *ep_ctx
609 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
610 hw_dequeue = le64_to_cpu(ep_ctx->deq);
613 new_seg = ep_ring->deq_seg;
614 new_deq = ep_ring->dequeue;
615 state->new_cycle_state = hw_dequeue & 0x1;
618 * We want to find the pointer, segment and cycle state of the new trb
619 * (the one after current TD's last_trb). We know the cycle state at
620 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
624 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
625 == (dma_addr_t)(hw_dequeue & ~0xf)) {
627 if (td_last_trb_found)
630 if (new_deq == cur_td->last_trb)
631 td_last_trb_found = true;
634 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
635 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
636 state->new_cycle_state ^= 0x1;
638 next_trb(xhci, ep_ring, &new_seg, &new_deq);
640 /* Search wrapped around, bail out */
641 if (new_deq == ep->ring->dequeue) {
642 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
643 state->new_deq_seg = NULL;
644 state->new_deq_ptr = NULL;
648 } while (!cycle_found || !td_last_trb_found);
650 state->new_deq_seg = new_seg;
651 state->new_deq_ptr = new_deq;
653 /* Don't update the ring cycle state for the producer (us). */
654 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
656 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
658 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
659 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
660 (unsigned long long) addr);
663 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
664 * (The last TRB actually points to the ring enqueue pointer, which is not part
665 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
667 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
668 struct xhci_td *cur_td, bool flip_cycle)
670 struct xhci_segment *cur_seg;
671 union xhci_trb *cur_trb;
673 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
675 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
676 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
677 /* Unchain any chained Link TRBs, but
678 * leave the pointers intact.
680 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
681 /* Flip the cycle bit (link TRBs can't be the first
685 cur_trb->generic.field[3] ^=
686 cpu_to_le32(TRB_CYCLE);
687 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
688 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
689 "in seg %p (0x%llx dma)\n",
691 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
693 (unsigned long long)cur_seg->dma);
695 cur_trb->generic.field[0] = 0;
696 cur_trb->generic.field[1] = 0;
697 cur_trb->generic.field[2] = 0;
698 /* Preserve only the cycle bit of this TRB */
699 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
700 /* Flip the cycle bit except on the first or last TRB */
701 if (flip_cycle && cur_trb != cur_td->first_trb &&
702 cur_trb != cur_td->last_trb)
703 cur_trb->generic.field[3] ^=
704 cpu_to_le32(TRB_CYCLE);
705 cur_trb->generic.field[3] |= cpu_to_le32(
706 TRB_TYPE(TRB_TR_NOOP));
707 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
708 "in seg %p (0x%llx dma)\n",
710 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
712 (unsigned long long)cur_seg->dma);
714 if (cur_trb == cur_td->last_trb)
719 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
720 unsigned int ep_index, unsigned int stream_id,
721 struct xhci_segment *deq_seg,
722 union xhci_trb *deq_ptr, u32 cycle_state);
724 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
725 unsigned int slot_id, unsigned int ep_index,
726 unsigned int stream_id,
727 struct xhci_dequeue_state *deq_state)
729 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
731 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
732 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
733 deq_state->new_deq_seg,
734 (unsigned long long)deq_state->new_deq_seg->dma,
735 deq_state->new_deq_ptr,
736 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
737 deq_state->new_cycle_state);
738 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
739 deq_state->new_deq_seg,
740 deq_state->new_deq_ptr,
741 (u32) deq_state->new_cycle_state);
742 /* Stop the TD queueing code from ringing the doorbell until
743 * this command completes. The HC won't set the dequeue pointer
744 * if the ring is running, and ringing the doorbell starts the
747 ep->ep_state |= SET_DEQ_PENDING;
750 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
751 struct xhci_virt_ep *ep)
753 ep->ep_state &= ~EP_HALT_PENDING;
754 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
755 * timer is running on another CPU, we don't decrement stop_cmds_pending
756 * (since we didn't successfully stop the watchdog timer).
758 if (del_timer(&ep->stop_cmd_timer))
759 ep->stop_cmds_pending--;
762 /* Must be called with xhci->lock held in interrupt context */
763 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
764 struct xhci_td *cur_td, int status, char *adjective)
768 struct urb_priv *urb_priv;
771 urb_priv = urb->hcpriv;
773 hcd = bus_to_hcd(urb->dev->bus);
775 /* Only giveback urb when this is the last td in urb */
776 if (urb_priv->td_cnt == urb_priv->length) {
777 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
778 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
779 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
780 if (xhci->quirks & XHCI_AMD_PLL_FIX)
781 usb_amd_quirk_pll_enable();
784 usb_hcd_unlink_urb_from_ep(hcd, urb);
786 spin_unlock(&xhci->lock);
787 usb_hcd_giveback_urb(hcd, urb, status);
788 xhci_urb_free_priv(xhci, urb_priv);
789 spin_lock(&xhci->lock);
794 * When we get a command completion for a Stop Endpoint Command, we need to
795 * unlink any cancelled TDs from the ring. There are two ways to do that:
797 * 1. If the HW was in the middle of processing the TD that needs to be
798 * cancelled, then we must move the ring's dequeue pointer past the last TRB
799 * in the TD with a Set Dequeue Pointer Command.
800 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
801 * bit cleared) so that the HW will skip over them.
803 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
804 union xhci_trb *trb, struct xhci_event_cmd *event)
806 unsigned int slot_id;
807 unsigned int ep_index;
808 struct xhci_virt_device *virt_dev;
809 struct xhci_ring *ep_ring;
810 struct xhci_virt_ep *ep;
811 struct list_head *entry;
812 struct xhci_td *cur_td = NULL;
813 struct xhci_td *last_unlinked_td;
815 struct xhci_dequeue_state deq_state;
817 if (unlikely(TRB_TO_SUSPEND_PORT(
818 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
819 slot_id = TRB_TO_SLOT_ID(
820 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
821 virt_dev = xhci->devs[slot_id];
823 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
826 xhci_warn(xhci, "Stop endpoint command "
827 "completion for disabled slot %u\n",
832 memset(&deq_state, 0, sizeof(deq_state));
833 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
834 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
835 ep = &xhci->devs[slot_id]->eps[ep_index];
837 if (list_empty(&ep->cancelled_td_list)) {
838 xhci_stop_watchdog_timer_in_irq(xhci, ep);
839 ep->stopped_td = NULL;
840 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
844 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
845 * We have the xHCI lock, so nothing can modify this list until we drop
846 * it. We're also in the event handler, so we can't get re-interrupted
847 * if another Stop Endpoint command completes
849 list_for_each(entry, &ep->cancelled_td_list) {
850 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
851 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
853 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
854 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
856 /* This shouldn't happen unless a driver is mucking
857 * with the stream ID after submission. This will
858 * leave the TD on the hardware ring, and the hardware
859 * will try to execute it, and may access a buffer
860 * that has already been freed. In the best case, the
861 * hardware will execute it, and the event handler will
862 * ignore the completion event for that TD, since it was
863 * removed from the td_list for that endpoint. In
864 * short, don't muck with the stream ID after
867 xhci_warn(xhci, "WARN Cancelled URB %p "
868 "has invalid stream ID %u.\n",
870 cur_td->urb->stream_id);
871 goto remove_finished_td;
874 * If we stopped on the TD we need to cancel, then we have to
875 * move the xHC endpoint ring dequeue pointer past this TD.
877 if (cur_td == ep->stopped_td)
878 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
879 cur_td->urb->stream_id,
882 td_to_noop(xhci, ep_ring, cur_td, false);
885 * The event handler won't see a completion for this TD anymore,
886 * so remove it from the endpoint ring's TD list. Keep it in
887 * the cancelled TD list for URB completion later.
889 list_del_init(&cur_td->td_list);
891 last_unlinked_td = cur_td;
892 xhci_stop_watchdog_timer_in_irq(xhci, ep);
894 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
895 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
896 xhci_queue_new_dequeue_state(xhci,
898 ep->stopped_td->urb->stream_id,
900 xhci_ring_cmd_db(xhci);
902 /* Otherwise ring the doorbell(s) to restart queued transfers */
903 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
906 /* Clear stopped_td if endpoint is not halted */
907 if (!(ep->ep_state & EP_HALTED))
908 ep->stopped_td = NULL;
911 * Drop the lock and complete the URBs in the cancelled TD list.
912 * New TDs to be cancelled might be added to the end of the list before
913 * we can complete all the URBs for the TDs we already unlinked.
914 * So stop when we've completed the URB for the last TD we unlinked.
917 cur_td = list_entry(ep->cancelled_td_list.next,
918 struct xhci_td, cancelled_td_list);
919 list_del_init(&cur_td->cancelled_td_list);
921 /* Clean up the cancelled URB */
922 /* Doesn't matter what we pass for status, since the core will
923 * just overwrite it (because the URB has been unlinked).
925 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
927 /* Stop processing the cancelled list if the watchdog timer is
930 if (xhci->xhc_state & XHCI_STATE_DYING)
932 } while (cur_td != last_unlinked_td);
934 /* Return to the event handler with xhci->lock re-acquired */
937 /* Watchdog timer function for when a stop endpoint command fails to complete.
938 * In this case, we assume the host controller is broken or dying or dead. The
939 * host may still be completing some other events, so we have to be careful to
940 * let the event ring handler and the URB dequeueing/enqueueing functions know
941 * through xhci->state.
943 * The timer may also fire if the host takes a very long time to respond to the
944 * command, and the stop endpoint command completion handler cannot delete the
945 * timer before the timer function is called. Another endpoint cancellation may
946 * sneak in before the timer function can grab the lock, and that may queue
947 * another stop endpoint command and add the timer back. So we cannot use a
948 * simple flag to say whether there is a pending stop endpoint command for a
949 * particular endpoint.
951 * Instead we use a combination of that flag and a counter for the number of
952 * pending stop endpoint commands. If the timer is the tail end of the last
953 * stop endpoint command, and the endpoint's command is still pending, we assume
956 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
958 struct xhci_hcd *xhci;
959 struct xhci_virt_ep *ep;
960 struct xhci_virt_ep *temp_ep;
961 struct xhci_ring *ring;
962 struct xhci_td *cur_td;
966 ep = (struct xhci_virt_ep *) arg;
969 spin_lock_irqsave(&xhci->lock, flags);
971 ep->stop_cmds_pending--;
972 if (xhci->xhc_state & XHCI_STATE_DYING) {
973 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
974 "xHCI as DYING, exiting.\n");
975 spin_unlock_irqrestore(&xhci->lock, flags);
978 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
979 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
981 spin_unlock_irqrestore(&xhci->lock, flags);
985 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
986 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
987 /* Oops, HC is dead or dying or at least not responding to the stop
990 xhci->xhc_state |= XHCI_STATE_DYING;
991 /* Disable interrupts from the host controller and start halting it */
993 spin_unlock_irqrestore(&xhci->lock, flags);
995 ret = xhci_halt(xhci);
997 spin_lock_irqsave(&xhci->lock, flags);
999 /* This is bad; the host is not responding to commands and it's
1000 * not allowing itself to be halted. At least interrupts are
1001 * disabled. If we call usb_hc_died(), it will attempt to
1002 * disconnect all device drivers under this host. Those
1003 * disconnect() methods will wait for all URBs to be unlinked,
1004 * so we must complete them.
1006 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
1007 xhci_warn(xhci, "Completing active URBs anyway.\n");
1008 /* We could turn all TDs on the rings to no-ops. This won't
1009 * help if the host has cached part of the ring, and is slow if
1010 * we want to preserve the cycle bit. Skip it and hope the host
1011 * doesn't touch the memory.
1014 for (i = 0; i < MAX_HC_SLOTS; i++) {
1017 for (j = 0; j < 31; j++) {
1018 temp_ep = &xhci->devs[i]->eps[j];
1019 ring = temp_ep->ring;
1022 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
1023 "ep index %u\n", i, j);
1024 while (!list_empty(&ring->td_list)) {
1025 cur_td = list_first_entry(&ring->td_list,
1028 list_del_init(&cur_td->td_list);
1029 if (!list_empty(&cur_td->cancelled_td_list))
1030 list_del_init(&cur_td->cancelled_td_list);
1031 xhci_giveback_urb_in_irq(xhci, cur_td,
1032 -ESHUTDOWN, "killed");
1034 while (!list_empty(&temp_ep->cancelled_td_list)) {
1035 cur_td = list_first_entry(
1036 &temp_ep->cancelled_td_list,
1039 list_del_init(&cur_td->cancelled_td_list);
1040 xhci_giveback_urb_in_irq(xhci, cur_td,
1041 -ESHUTDOWN, "killed");
1045 spin_unlock_irqrestore(&xhci->lock, flags);
1046 xhci_dbg(xhci, "Calling usb_hc_died()\n");
1047 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1048 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1052 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1053 * we need to clear the set deq pending flag in the endpoint ring state, so that
1054 * the TD queueing code can ring the doorbell again. We also need to ring the
1055 * endpoint doorbell to restart the ring, but only if there aren't more
1056 * cancellations pending.
1058 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1059 struct xhci_event_cmd *event,
1060 union xhci_trb *trb)
1062 unsigned int slot_id;
1063 unsigned int ep_index;
1064 unsigned int stream_id;
1065 struct xhci_ring *ep_ring;
1066 struct xhci_virt_device *dev;
1067 struct xhci_ep_ctx *ep_ctx;
1068 struct xhci_slot_ctx *slot_ctx;
1070 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1071 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1072 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1073 dev = xhci->devs[slot_id];
1075 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1077 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1078 "freed stream ID %u\n",
1080 /* XXX: Harmless??? */
1081 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1085 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1086 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1088 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1089 unsigned int ep_state;
1090 unsigned int slot_state;
1092 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1094 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1095 "of stream ID configuration\n");
1097 case COMP_CTX_STATE:
1098 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1099 "to incorrect slot or ep state.\n");
1100 ep_state = le32_to_cpu(ep_ctx->ep_info);
1101 ep_state &= EP_STATE_MASK;
1102 slot_state = le32_to_cpu(slot_ctx->dev_state);
1103 slot_state = GET_SLOT_STATE(slot_state);
1104 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1105 slot_state, ep_state);
1108 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1109 "slot %u was not enabled.\n", slot_id);
1112 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1113 "completion code of %u.\n",
1114 GET_COMP_CODE(le32_to_cpu(event->status)));
1117 /* OK what do we do now? The endpoint state is hosed, and we
1118 * should never get to this point if the synchronization between
1119 * queueing, and endpoint state are correct. This might happen
1120 * if the device gets disconnected after we've finished
1121 * cancelling URBs, which might not be an error...
1124 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1125 le64_to_cpu(ep_ctx->deq));
1126 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1127 dev->eps[ep_index].queued_deq_ptr) ==
1128 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1129 /* Update the ring's dequeue segment and dequeue pointer
1130 * to reflect the new position.
1132 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1133 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1135 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1136 "Ptr command & xHCI internal state.\n");
1137 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1138 dev->eps[ep_index].queued_deq_seg,
1139 dev->eps[ep_index].queued_deq_ptr);
1143 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1144 dev->eps[ep_index].queued_deq_seg = NULL;
1145 dev->eps[ep_index].queued_deq_ptr = NULL;
1146 /* Restart any rings with pending URBs */
1147 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1150 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1151 struct xhci_event_cmd *event,
1152 union xhci_trb *trb)
1155 unsigned int ep_index;
1157 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1158 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1159 /* This command will only fail if the endpoint wasn't halted,
1160 * but we don't care.
1162 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1163 GET_COMP_CODE(le32_to_cpu(event->status)));
1165 /* HW with the reset endpoint quirk needs to have a configure endpoint
1166 * command complete before the endpoint can be used. Queue that here
1167 * because the HW can't handle two commands being queued in a row.
1169 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1170 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1171 xhci_queue_configure_endpoint(xhci,
1172 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1174 xhci_ring_cmd_db(xhci);
1176 /* Clear our internal halted state */
1177 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1181 /* Complete the command and detele it from the devcie's command queue.
1183 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1184 struct xhci_command *command, u32 status)
1186 command->status = status;
1187 list_del(&command->cmd_list);
1188 if (command->completion)
1189 complete(command->completion);
1191 xhci_free_command(xhci, command);
1195 /* Check to see if a command in the device's command queue matches this one.
1196 * Signal the completion or free the command, and return 1. Return 0 if the
1197 * completed command isn't at the head of the command list.
1199 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1200 struct xhci_virt_device *virt_dev,
1201 struct xhci_event_cmd *event)
1203 struct xhci_command *command;
1205 if (list_empty(&virt_dev->cmd_list))
1208 command = list_entry(virt_dev->cmd_list.next,
1209 struct xhci_command, cmd_list);
1210 if (xhci->cmd_ring->dequeue != command->command_trb)
1213 xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1214 GET_COMP_CODE(le32_to_cpu(event->status)));
1219 * Finding the command trb need to be cancelled and modifying it to
1220 * NO OP command. And if the command is in device's command wait
1221 * list, finishing and freeing it.
1223 * If we can't find the command trb, we think it had already been
1226 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1228 struct xhci_segment *cur_seg;
1229 union xhci_trb *cmd_trb;
1232 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1235 /* find the current segment of command ring */
1236 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1237 xhci->cmd_ring->dequeue, &cycle_state);
1240 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1241 xhci->cmd_ring->dequeue,
1242 (unsigned long long)
1243 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1244 xhci->cmd_ring->dequeue));
1245 xhci_debug_ring(xhci, xhci->cmd_ring);
1246 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1250 /* find the command trb matched by cd from command ring */
1251 for (cmd_trb = xhci->cmd_ring->dequeue;
1252 cmd_trb != xhci->cmd_ring->enqueue;
1253 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1254 /* If the trb is link trb, continue */
1255 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1258 if (cur_cd->cmd_trb == cmd_trb) {
1260 /* If the command in device's command list, we should
1261 * finish it and free the command structure.
1263 if (cur_cd->command)
1264 xhci_complete_cmd_in_cmd_wait_list(xhci,
1265 cur_cd->command, COMP_CMD_STOP);
1267 /* get cycle state from the origin command trb */
1268 cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1271 /* modify the command trb to NO OP command */
1272 cmd_trb->generic.field[0] = 0;
1273 cmd_trb->generic.field[1] = 0;
1274 cmd_trb->generic.field[2] = 0;
1275 cmd_trb->generic.field[3] = cpu_to_le32(
1276 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1282 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1284 struct xhci_cd *cur_cd, *next_cd;
1286 if (list_empty(&xhci->cancel_cmd_list))
1289 list_for_each_entry_safe(cur_cd, next_cd,
1290 &xhci->cancel_cmd_list, cancel_cmd_list) {
1291 xhci_cmd_to_noop(xhci, cur_cd);
1292 list_del(&cur_cd->cancel_cmd_list);
1298 * traversing the cancel_cmd_list. If the command descriptor according
1299 * to cmd_trb is found, the function free it and return 1, otherwise
1302 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1303 union xhci_trb *cmd_trb)
1305 struct xhci_cd *cur_cd, *next_cd;
1307 if (list_empty(&xhci->cancel_cmd_list))
1310 list_for_each_entry_safe(cur_cd, next_cd,
1311 &xhci->cancel_cmd_list, cancel_cmd_list) {
1312 if (cur_cd->cmd_trb == cmd_trb) {
1313 if (cur_cd->command)
1314 xhci_complete_cmd_in_cmd_wait_list(xhci,
1315 cur_cd->command, COMP_CMD_STOP);
1316 list_del(&cur_cd->cancel_cmd_list);
1326 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1327 * trb pointed by the command ring dequeue pointer is the trb we want to
1328 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1329 * traverse the cancel_cmd_list to trun the all of the commands according
1330 * to command descriptor to NO-OP trb.
1332 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1333 int cmd_trb_comp_code)
1335 int cur_trb_is_good = 0;
1337 /* Searching the cmd trb pointed by the command ring dequeue
1338 * pointer in command descriptor list. If it is found, free it.
1340 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1341 xhci->cmd_ring->dequeue);
1343 if (cmd_trb_comp_code == COMP_CMD_ABORT)
1344 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1345 else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1346 /* traversing the cancel_cmd_list and canceling
1347 * the command according to command descriptor
1349 xhci_cancel_cmd_in_cd_list(xhci);
1351 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1353 * ring command ring doorbell again to restart the
1356 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1357 xhci_ring_cmd_db(xhci);
1359 return cur_trb_is_good;
1362 static void handle_cmd_completion(struct xhci_hcd *xhci,
1363 struct xhci_event_cmd *event)
1365 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1367 dma_addr_t cmd_dequeue_dma;
1368 struct xhci_input_control_ctx *ctrl_ctx;
1369 struct xhci_virt_device *virt_dev;
1370 unsigned int ep_index;
1371 struct xhci_ring *ep_ring;
1372 unsigned int ep_state;
1374 cmd_dma = le64_to_cpu(event->cmd_trb);
1375 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1376 xhci->cmd_ring->dequeue);
1377 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1378 if (cmd_dequeue_dma == 0) {
1379 xhci->error_bitmask |= 1 << 4;
1382 /* Does the DMA address match our internal dequeue pointer address? */
1383 if (cmd_dma != (u64) cmd_dequeue_dma) {
1384 xhci->error_bitmask |= 1 << 5;
1388 if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1389 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1390 /* If the return value is 0, we think the trb pointed by
1391 * command ring dequeue pointer is a good trb. The good
1392 * trb means we don't want to cancel the trb, but it have
1393 * been stopped by host. So we should handle it normally.
1394 * Otherwise, driver should invoke inc_deq() and return.
1396 if (handle_stopped_cmd_ring(xhci,
1397 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1398 inc_deq(xhci, xhci->cmd_ring, false);
1403 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1404 & TRB_TYPE_BITMASK) {
1405 case TRB_TYPE(TRB_ENABLE_SLOT):
1406 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1407 xhci->slot_id = slot_id;
1410 complete(&xhci->addr_dev);
1412 case TRB_TYPE(TRB_DISABLE_SLOT):
1413 if (xhci->devs[slot_id]) {
1414 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1415 /* Delete default control endpoint resources */
1416 xhci_free_device_endpoint_resources(xhci,
1417 xhci->devs[slot_id], true);
1418 xhci_free_virt_device(xhci, slot_id);
1421 case TRB_TYPE(TRB_CONFIG_EP):
1422 virt_dev = xhci->devs[slot_id];
1423 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1426 * Configure endpoint commands can come from the USB core
1427 * configuration or alt setting changes, or because the HW
1428 * needed an extra configure endpoint command after a reset
1429 * endpoint command or streams were being configured.
1430 * If the command was for a halted endpoint, the xHCI driver
1431 * is not waiting on the configure endpoint command.
1433 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1435 /* Input ctx add_flags are the endpoint index plus one */
1436 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1437 /* A usb_set_interface() call directly after clearing a halted
1438 * condition may race on this quirky hardware. Not worth
1439 * worrying about, since this is prototype hardware. Not sure
1440 * if this will work for streams, but streams support was
1441 * untested on this prototype.
1443 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1444 ep_index != (unsigned int) -1 &&
1445 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1446 le32_to_cpu(ctrl_ctx->drop_flags)) {
1447 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1448 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1449 if (!(ep_state & EP_HALTED))
1450 goto bandwidth_change;
1451 xhci_dbg(xhci, "Completed config ep cmd - "
1452 "last ep index = %d, state = %d\n",
1453 ep_index, ep_state);
1454 /* Clear internal halted state and restart ring(s) */
1455 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1457 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1461 xhci_dbg(xhci, "Completed config ep cmd\n");
1462 xhci->devs[slot_id]->cmd_status =
1463 GET_COMP_CODE(le32_to_cpu(event->status));
1464 complete(&xhci->devs[slot_id]->cmd_completion);
1466 case TRB_TYPE(TRB_EVAL_CONTEXT):
1467 virt_dev = xhci->devs[slot_id];
1468 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1470 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1471 complete(&xhci->devs[slot_id]->cmd_completion);
1473 case TRB_TYPE(TRB_ADDR_DEV):
1474 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1475 complete(&xhci->addr_dev);
1477 case TRB_TYPE(TRB_STOP_RING):
1478 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1480 case TRB_TYPE(TRB_SET_DEQ):
1481 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1483 case TRB_TYPE(TRB_CMD_NOOP):
1485 case TRB_TYPE(TRB_RESET_EP):
1486 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1488 case TRB_TYPE(TRB_RESET_DEV):
1489 xhci_dbg(xhci, "Completed reset device command.\n");
1490 slot_id = TRB_TO_SLOT_ID(
1491 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1492 virt_dev = xhci->devs[slot_id];
1494 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1496 xhci_warn(xhci, "Reset device command completion "
1497 "for disabled slot %u\n", slot_id);
1499 case TRB_TYPE(TRB_NEC_GET_FW):
1500 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1501 xhci->error_bitmask |= 1 << 6;
1504 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1505 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1506 NEC_FW_MINOR(le32_to_cpu(event->status)));
1509 /* Skip over unknown commands on the event ring */
1510 xhci->error_bitmask |= 1 << 6;
1513 inc_deq(xhci, xhci->cmd_ring, false);
1516 static void handle_vendor_event(struct xhci_hcd *xhci,
1517 union xhci_trb *event)
1521 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1522 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1523 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1524 handle_cmd_completion(xhci, &event->event_cmd);
1527 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1528 * port registers -- USB 3.0 and USB 2.0).
1530 * Returns a zero-based port number, which is suitable for indexing into each of
1531 * the split roothubs' port arrays and bus state arrays.
1532 * Add one to it in order to call xhci_find_slot_id_by_port.
1534 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1535 struct xhci_hcd *xhci, u32 port_id)
1538 unsigned int num_similar_speed_ports = 0;
1540 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1541 * and usb2_ports are 0-based indexes. Count the number of similar
1542 * speed ports, up to 1 port before this port.
1544 for (i = 0; i < (port_id - 1); i++) {
1545 u8 port_speed = xhci->port_array[i];
1548 * Skip ports that don't have known speeds, or have duplicate
1549 * Extended Capabilities port speed entries.
1551 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1555 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1556 * 1.1 ports are under the USB 2.0 hub. If the port speed
1557 * matches the device speed, it's a similar speed port.
1559 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1560 num_similar_speed_ports++;
1562 return num_similar_speed_ports;
1565 static void handle_port_status(struct xhci_hcd *xhci,
1566 union xhci_trb *event)
1568 struct usb_hcd *hcd;
1573 unsigned int faked_port_index;
1575 struct xhci_bus_state *bus_state;
1576 __le32 __iomem **port_array;
1577 bool bogus_port_status = false;
1579 /* Port status change events always have a successful completion code */
1580 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1581 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1582 xhci->error_bitmask |= 1 << 8;
1584 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1585 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1587 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1588 if ((port_id <= 0) || (port_id > max_ports)) {
1589 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1590 bogus_port_status = true;
1594 /* Figure out which usb_hcd this port is attached to:
1595 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1597 major_revision = xhci->port_array[port_id - 1];
1598 if (major_revision == 0) {
1599 xhci_warn(xhci, "Event for port %u not in "
1600 "Extended Capabilities, ignoring.\n",
1602 bogus_port_status = true;
1605 if (major_revision == DUPLICATE_ENTRY) {
1606 xhci_warn(xhci, "Event for port %u duplicated in"
1607 "Extended Capabilities, ignoring.\n",
1609 bogus_port_status = true;
1614 * Hardware port IDs reported by a Port Status Change Event include USB
1615 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1616 * resume event, but we first need to translate the hardware port ID
1617 * into the index into the ports on the correct split roothub, and the
1618 * correct bus_state structure.
1620 /* Find the right roothub. */
1621 hcd = xhci_to_hcd(xhci);
1622 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1623 hcd = xhci->shared_hcd;
1624 bus_state = &xhci->bus_state[hcd_index(hcd)];
1625 if (hcd->speed == HCD_USB3)
1626 port_array = xhci->usb3_ports;
1628 port_array = xhci->usb2_ports;
1629 /* Find the faked port hub number */
1630 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1633 temp = xhci_readl(xhci, port_array[faked_port_index]);
1634 if (hcd->state == HC_STATE_SUSPENDED) {
1635 xhci_dbg(xhci, "resume root hub\n");
1636 usb_hcd_resume_root_hub(hcd);
1639 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1640 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1642 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1643 if (!(temp1 & CMD_RUN)) {
1644 xhci_warn(xhci, "xHC is not running.\n");
1648 if (DEV_SUPERSPEED(temp)) {
1649 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1650 xhci_set_link_state(xhci, port_array, faked_port_index,
1652 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1653 faked_port_index + 1);
1655 xhci_dbg(xhci, "slot_id is zero\n");
1658 xhci_ring_device(xhci, slot_id);
1659 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1660 /* Clear PORT_PLC */
1661 xhci_test_and_clear_bit(xhci, port_array,
1662 faked_port_index, PORT_PLC);
1664 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1665 bus_state->resume_done[faked_port_index] = jiffies +
1666 msecs_to_jiffies(20);
1667 mod_timer(&hcd->rh_timer,
1668 bus_state->resume_done[faked_port_index]);
1669 /* Do the rest in GetPortStatus */
1673 if (hcd->speed != HCD_USB3)
1674 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1678 /* Update event ring dequeue pointer before dropping the lock */
1679 inc_deq(xhci, xhci->event_ring, true);
1681 /* Don't make the USB core poll the roothub if we got a bad port status
1682 * change event. Besides, at that point we can't tell which roothub
1683 * (USB 2.0 or USB 3.0) to kick.
1685 if (bogus_port_status)
1689 * xHCI port-status-change events occur when the "or" of all the
1690 * status-change bits in the portsc register changes from 0 to 1.
1691 * New status changes won't cause an event if any other change
1692 * bits are still set. When an event occurs, switch over to
1693 * polling to avoid losing status changes.
1695 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1696 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1697 spin_unlock(&xhci->lock);
1698 /* Pass this up to the core */
1699 usb_hcd_poll_rh_status(hcd);
1700 spin_lock(&xhci->lock);
1704 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1705 * at end_trb, which may be in another segment. If the suspect DMA address is a
1706 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1709 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1710 union xhci_trb *start_trb,
1711 union xhci_trb *end_trb,
1712 dma_addr_t suspect_dma)
1714 dma_addr_t start_dma;
1715 dma_addr_t end_seg_dma;
1716 dma_addr_t end_trb_dma;
1717 struct xhci_segment *cur_seg;
1719 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1720 cur_seg = start_seg;
1725 /* We may get an event for a Link TRB in the middle of a TD */
1726 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1727 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1728 /* If the end TRB isn't in this segment, this is set to 0 */
1729 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1731 if (end_trb_dma > 0) {
1732 /* The end TRB is in this segment, so suspect should be here */
1733 if (start_dma <= end_trb_dma) {
1734 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1737 /* Case for one segment with
1738 * a TD wrapped around to the top
1740 if ((suspect_dma >= start_dma &&
1741 suspect_dma <= end_seg_dma) ||
1742 (suspect_dma >= cur_seg->dma &&
1743 suspect_dma <= end_trb_dma))
1748 /* Might still be somewhere in this segment */
1749 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1752 cur_seg = cur_seg->next;
1753 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1754 } while (cur_seg != start_seg);
1759 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1760 unsigned int slot_id, unsigned int ep_index,
1761 unsigned int stream_id,
1762 struct xhci_td *td, union xhci_trb *event_trb)
1764 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1765 ep->ep_state |= EP_HALTED;
1766 ep->stopped_td = td;
1767 ep->stopped_stream = stream_id;
1769 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1770 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1772 ep->stopped_td = NULL;
1773 ep->stopped_stream = 0;
1775 xhci_ring_cmd_db(xhci);
1778 /* Check if an error has halted the endpoint ring. The class driver will
1779 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1780 * However, a babble and other errors also halt the endpoint ring, and the class
1781 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1782 * Ring Dequeue Pointer command manually.
1784 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1785 struct xhci_ep_ctx *ep_ctx,
1786 unsigned int trb_comp_code)
1788 /* TRB completion codes that may require a manual halt cleanup */
1789 if (trb_comp_code == COMP_TX_ERR ||
1790 trb_comp_code == COMP_BABBLE ||
1791 trb_comp_code == COMP_SPLIT_ERR)
1792 /* The 0.96 spec says a babbling control endpoint
1793 * is not halted. The 0.96 spec says it is. Some HW
1794 * claims to be 0.95 compliant, but it halts the control
1795 * endpoint anyway. Check if a babble halted the
1798 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1799 cpu_to_le32(EP_STATE_HALTED))
1805 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1807 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1808 /* Vendor defined "informational" completion code,
1809 * treat as not-an-error.
1811 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1813 xhci_dbg(xhci, "Treating code as success.\n");
1820 * Finish the td processing, remove the td from td list;
1821 * Return 1 if the urb can be given back.
1823 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1824 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1825 struct xhci_virt_ep *ep, int *status, bool skip)
1827 struct xhci_virt_device *xdev;
1828 struct xhci_ring *ep_ring;
1829 unsigned int slot_id;
1831 struct urb *urb = NULL;
1832 struct xhci_ep_ctx *ep_ctx;
1834 struct urb_priv *urb_priv;
1837 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1838 xdev = xhci->devs[slot_id];
1839 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1840 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1841 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1842 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1847 if (trb_comp_code == COMP_STOP_INVAL ||
1848 trb_comp_code == COMP_STOP) {
1849 /* The Endpoint Stop Command completion will take care of any
1850 * stopped TDs. A stopped TD may be restarted, so don't update
1851 * the ring dequeue pointer or take this TD off any lists yet.
1853 ep->stopped_td = td;
1856 if (trb_comp_code == COMP_STALL ||
1857 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1859 /* Issue a reset endpoint command to clear the host side
1860 * halt, followed by a set dequeue command to move the
1861 * dequeue pointer past the TD.
1862 * The class driver clears the device side halt later.
1864 xhci_cleanup_halted_endpoint(xhci,
1865 slot_id, ep_index, ep_ring->stream_id,
1868 /* Update ring dequeue pointer */
1869 while (ep_ring->dequeue != td->last_trb)
1870 inc_deq(xhci, ep_ring, false);
1871 inc_deq(xhci, ep_ring, false);
1875 /* Clean up the endpoint's TD list */
1877 urb_priv = urb->hcpriv;
1879 /* Do one last check of the actual transfer length.
1880 * If the host controller said we transferred more data than
1881 * the buffer length, urb->actual_length will be a very big
1882 * number (since it's unsigned). Play it safe and say we didn't
1883 * transfer anything.
1885 if (urb->actual_length > urb->transfer_buffer_length) {
1886 xhci_warn(xhci, "URB transfer length is wrong, "
1887 "xHC issue? req. len = %u, "
1889 urb->transfer_buffer_length,
1890 urb->actual_length);
1891 urb->actual_length = 0;
1892 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1893 *status = -EREMOTEIO;
1897 list_del_init(&td->td_list);
1898 /* Was this TD slated to be cancelled but completed anyway? */
1899 if (!list_empty(&td->cancelled_td_list))
1900 list_del_init(&td->cancelled_td_list);
1903 /* Giveback the urb when all the tds are completed */
1904 if (urb_priv->td_cnt == urb_priv->length) {
1906 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1907 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1908 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1910 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1911 usb_amd_quirk_pll_enable();
1921 * Process control tds, update urb status and actual_length.
1923 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1924 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1925 struct xhci_virt_ep *ep, int *status)
1927 struct xhci_virt_device *xdev;
1928 struct xhci_ring *ep_ring;
1929 unsigned int slot_id;
1931 struct xhci_ep_ctx *ep_ctx;
1934 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1935 xdev = xhci->devs[slot_id];
1936 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1937 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1938 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1939 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1941 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1942 switch (trb_comp_code) {
1944 if (event_trb == ep_ring->dequeue) {
1945 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1946 "without IOC set??\n");
1947 *status = -ESHUTDOWN;
1948 } else if (event_trb != td->last_trb) {
1949 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1950 "without IOC set??\n");
1951 *status = -ESHUTDOWN;
1957 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1958 *status = -EREMOTEIO;
1962 case COMP_STOP_INVAL:
1964 return finish_td(xhci, td, event_trb, event, ep, status, false);
1966 if (!xhci_requires_manual_halt_cleanup(xhci,
1967 ep_ctx, trb_comp_code))
1969 xhci_dbg(xhci, "TRB error code %u, "
1970 "halted endpoint index = %u\n",
1971 trb_comp_code, ep_index);
1972 /* else fall through */
1974 /* Did we transfer part of the data (middle) phase? */
1975 if (event_trb != ep_ring->dequeue &&
1976 event_trb != td->last_trb)
1977 td->urb->actual_length =
1978 td->urb->transfer_buffer_length -
1979 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1981 td->urb->actual_length = 0;
1983 return finish_td(xhci, td, event_trb, event, ep, status, false);
1986 * Did we transfer any data, despite the errors that might have
1987 * happened? I.e. did we get past the setup stage?
1989 if (event_trb != ep_ring->dequeue) {
1990 /* The event was for the status stage */
1991 if (event_trb == td->last_trb) {
1992 if (td->urb_length_set) {
1993 /* Don't overwrite a previously set error code
1995 if ((*status == -EINPROGRESS || *status == 0) &&
1996 (td->urb->transfer_flags
1997 & URB_SHORT_NOT_OK))
1998 /* Did we already see a short data
2000 *status = -EREMOTEIO;
2002 td->urb->actual_length =
2003 td->urb->transfer_buffer_length;
2007 * Maybe the event was for the data stage? If so, update
2008 * already the actual_length of the URB and flag it as
2009 * set, so that it is not overwritten in the event for
2012 td->urb_length_set = true;
2013 td->urb->actual_length =
2014 td->urb->transfer_buffer_length -
2015 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2016 xhci_dbg(xhci, "Waiting for status "
2022 return finish_td(xhci, td, event_trb, event, ep, status, false);
2026 * Process isochronous tds, update urb packet status and actual_length.
2028 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2029 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2030 struct xhci_virt_ep *ep, int *status)
2032 struct xhci_ring *ep_ring;
2033 struct urb_priv *urb_priv;
2036 union xhci_trb *cur_trb;
2037 struct xhci_segment *cur_seg;
2038 struct usb_iso_packet_descriptor *frame;
2040 bool skip_td = false;
2042 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2043 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2044 urb_priv = td->urb->hcpriv;
2045 idx = urb_priv->td_cnt;
2046 frame = &td->urb->iso_frame_desc[idx];
2048 /* handle completion code */
2049 switch (trb_comp_code) {
2051 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2055 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2056 trb_comp_code = COMP_SHORT_TX;
2058 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2062 frame->status = -ECOMM;
2065 case COMP_BUFF_OVER:
2067 frame->status = -EOVERFLOW;
2072 frame->status = -EPROTO;
2076 frame->status = -EPROTO;
2077 if (event_trb != td->last_trb)
2082 case COMP_STOP_INVAL:
2089 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2090 frame->actual_length = frame->length;
2091 td->urb->actual_length += frame->length;
2093 for (cur_trb = ep_ring->dequeue,
2094 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2095 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2096 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2097 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2098 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2100 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2101 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2103 if (trb_comp_code != COMP_STOP_INVAL) {
2104 frame->actual_length = len;
2105 td->urb->actual_length += len;
2109 return finish_td(xhci, td, event_trb, event, ep, status, false);
2112 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2113 struct xhci_transfer_event *event,
2114 struct xhci_virt_ep *ep, int *status)
2116 struct xhci_ring *ep_ring;
2117 struct urb_priv *urb_priv;
2118 struct usb_iso_packet_descriptor *frame;
2121 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2122 urb_priv = td->urb->hcpriv;
2123 idx = urb_priv->td_cnt;
2124 frame = &td->urb->iso_frame_desc[idx];
2126 /* The transfer is partly done. */
2127 frame->status = -EXDEV;
2129 /* calc actual length */
2130 frame->actual_length = 0;
2132 /* Update ring dequeue pointer */
2133 while (ep_ring->dequeue != td->last_trb)
2134 inc_deq(xhci, ep_ring, false);
2135 inc_deq(xhci, ep_ring, false);
2137 return finish_td(xhci, td, NULL, event, ep, status, true);
2141 * Process bulk and interrupt tds, update urb status and actual_length.
2143 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2144 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2145 struct xhci_virt_ep *ep, int *status)
2147 struct xhci_ring *ep_ring;
2148 union xhci_trb *cur_trb;
2149 struct xhci_segment *cur_seg;
2152 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2153 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2155 switch (trb_comp_code) {
2157 /* Double check that the HW transferred everything. */
2158 if (event_trb != td->last_trb ||
2159 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2160 xhci_warn(xhci, "WARN Successful completion "
2162 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2163 *status = -EREMOTEIO;
2166 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2167 trb_comp_code = COMP_SHORT_TX;
2173 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2174 *status = -EREMOTEIO;
2179 /* Others already handled above */
2182 if (trb_comp_code == COMP_SHORT_TX)
2183 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2184 "%d bytes untransferred\n",
2185 td->urb->ep->desc.bEndpointAddress,
2186 td->urb->transfer_buffer_length,
2187 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2188 /* Fast path - was this the last TRB in the TD for this URB? */
2189 if (event_trb == td->last_trb) {
2190 if (td->urb_length_set && trb_comp_code == COMP_SHORT_TX)
2191 return finish_td(xhci, td, event_trb, event, ep,
2194 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2195 td->urb->actual_length =
2196 td->urb->transfer_buffer_length -
2197 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2198 if (td->urb->transfer_buffer_length <
2199 td->urb->actual_length) {
2200 xhci_warn(xhci, "HC gave bad length "
2201 "of %d bytes left\n",
2202 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2203 td->urb->actual_length = 0;
2204 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2205 *status = -EREMOTEIO;
2209 /* Don't overwrite a previously set error code */
2210 if (*status == -EINPROGRESS) {
2211 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2212 *status = -EREMOTEIO;
2217 td->urb->actual_length =
2218 td->urb->transfer_buffer_length;
2219 /* Ignore a short packet completion if the
2220 * untransferred length was zero.
2222 if (*status == -EREMOTEIO)
2226 /* Slow path - walk the list, starting from the dequeue
2227 * pointer, to get the actual length transferred.
2229 td->urb->actual_length = 0;
2230 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2231 cur_trb != event_trb;
2232 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2233 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2234 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2235 td->urb->actual_length +=
2236 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2238 /* If the ring didn't stop on a Link or No-op TRB, add
2239 * in the actual bytes transferred from the Normal TRB
2241 if (trb_comp_code != COMP_STOP_INVAL)
2242 td->urb->actual_length +=
2243 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2244 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2246 if (trb_comp_code == COMP_SHORT_TX) {
2247 xhci_dbg(xhci, "mid bulk/intr SP, wait for last TRB event\n");
2248 td->urb_length_set = true;
2253 return finish_td(xhci, td, event_trb, event, ep, status, false);
2257 * If this function returns an error condition, it means it got a Transfer
2258 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2259 * At this point, the host controller is probably hosed and should be reset.
2261 static int handle_tx_event(struct xhci_hcd *xhci,
2262 struct xhci_transfer_event *event)
2264 struct xhci_virt_device *xdev;
2265 struct xhci_virt_ep *ep;
2266 struct xhci_ring *ep_ring;
2267 unsigned int slot_id;
2269 struct xhci_td *td = NULL;
2270 dma_addr_t event_dma;
2271 struct xhci_segment *event_seg;
2272 union xhci_trb *event_trb;
2273 struct urb *urb = NULL;
2274 int status = -EINPROGRESS;
2275 struct urb_priv *urb_priv;
2276 struct xhci_ep_ctx *ep_ctx;
2277 struct list_head *tmp;
2281 bool handling_skipped_tds = false;
2283 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2284 xdev = xhci->devs[slot_id];
2286 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2290 /* Endpoint ID is 1 based, our index is zero based */
2291 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2292 ep = &xdev->eps[ep_index];
2293 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2294 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2296 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2297 EP_STATE_DISABLED) {
2298 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2299 "or incorrect stream ring\n");
2303 /* Count current td numbers if ep->skip is set */
2305 list_for_each(tmp, &ep_ring->td_list)
2309 event_dma = le64_to_cpu(event->buffer);
2310 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2311 /* Look for common error cases */
2312 switch (trb_comp_code) {
2313 /* Skip codes that require special handling depending on
2317 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2319 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2320 trb_comp_code = COMP_SHORT_TX;
2322 xhci_warn(xhci, "WARN Successful completion on short TX: "
2323 "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2327 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2329 case COMP_STOP_INVAL:
2330 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2333 xhci_dbg(xhci, "Stalled endpoint\n");
2334 ep->ep_state |= EP_HALTED;
2338 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2341 case COMP_SPLIT_ERR:
2343 xhci_dbg(xhci, "Transfer error on endpoint\n");
2347 xhci_dbg(xhci, "Babble error on endpoint\n");
2348 status = -EOVERFLOW;
2351 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2355 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2357 case COMP_BUFF_OVER:
2358 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2362 * When the Isoch ring is empty, the xHC will generate
2363 * a Ring Overrun Event for IN Isoch endpoint or Ring
2364 * Underrun Event for OUT Isoch endpoint.
2366 xhci_dbg(xhci, "underrun event on endpoint\n");
2367 if (!list_empty(&ep_ring->td_list))
2368 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2369 "still with TDs queued?\n",
2370 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2374 xhci_dbg(xhci, "overrun event on endpoint\n");
2375 if (!list_empty(&ep_ring->td_list))
2376 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2377 "still with TDs queued?\n",
2378 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2382 xhci_warn(xhci, "WARN: detect an incompatible device");
2385 case COMP_MISSED_INT:
2387 * When encounter missed service error, one or more isoc tds
2388 * may be missed by xHC.
2389 * Set skip flag of the ep_ring; Complete the missed tds as
2390 * short transfer when process the ep_ring next time.
2393 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2397 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2400 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2404 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2410 /* This TRB should be in the TD at the head of this ring's
2413 if (list_empty(&ep_ring->td_list)) {
2415 * A stopped endpoint may generate an extra completion
2416 * event if the device was suspended. Don't print
2419 if (!(trb_comp_code == COMP_STOP ||
2420 trb_comp_code == COMP_STOP_INVAL)) {
2421 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2422 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2424 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2425 (le32_to_cpu(event->flags) &
2426 TRB_TYPE_BITMASK)>>10);
2427 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2431 xhci_dbg(xhci, "td_list is empty while skip "
2432 "flag set. Clear skip flag.\n");
2438 /* We've skipped all the TDs on the ep ring when ep->skip set */
2439 if (ep->skip && td_num == 0) {
2441 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2442 "Clear skip flag.\n");
2447 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2451 /* Is this a TRB in the currently executing TD? */
2452 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2453 td->last_trb, event_dma);
2456 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2457 * is not in the current TD pointed by ep_ring->dequeue because
2458 * that the hardware dequeue pointer still at the previous TRB
2459 * of the current TD. The previous TRB maybe a Link TD or the
2460 * last TRB of the previous TD. The command completion handle
2461 * will take care the rest.
2463 if (!event_seg && (trb_comp_code == COMP_STOP ||
2464 trb_comp_code == COMP_STOP_INVAL)) {
2471 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2472 /* Some host controllers give a spurious
2473 * successful event after a short transfer.
2476 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2477 ep_ring->last_td_was_short) {
2478 ep_ring->last_td_was_short = false;
2482 /* HC is busted, give up! */
2484 "ERROR Transfer event TRB DMA ptr not "
2485 "part of current TD\n");
2489 ret = skip_isoc_td(xhci, td, event, ep, &status);
2492 if (trb_comp_code == COMP_SHORT_TX)
2493 ep_ring->last_td_was_short = true;
2495 ep_ring->last_td_was_short = false;
2498 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2502 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2503 sizeof(*event_trb)];
2505 * No-op TRB should not trigger interrupts.
2506 * If event_trb is a no-op TRB, it means the
2507 * corresponding TD has been cancelled. Just ignore
2510 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2512 "event_trb is a no-op TRB. Skip it\n");
2516 /* Now update the urb's actual_length and give back to
2519 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2520 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2522 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2523 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2526 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2532 handling_skipped_tds = ep->skip &&
2533 trb_comp_code != COMP_MISSED_INT &&
2534 trb_comp_code != COMP_PING_ERR;
2537 * Do not update event ring dequeue pointer if we're in a loop
2538 * processing missed tds.
2540 if (!handling_skipped_tds)
2541 inc_deq(xhci, xhci->event_ring, true);
2545 urb_priv = urb->hcpriv;
2547 xhci_urb_free_priv(xhci, urb_priv);
2549 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2550 if ((urb->actual_length != urb->transfer_buffer_length &&
2551 (urb->transfer_flags &
2552 URB_SHORT_NOT_OK)) ||
2554 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2555 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2556 "expected = %x, status = %d\n",
2557 urb, urb->actual_length,
2558 urb->transfer_buffer_length,
2560 spin_unlock(&xhci->lock);
2561 /* EHCI, UHCI, and OHCI always unconditionally set the
2562 * urb->status of an isochronous endpoint to 0.
2564 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2566 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2567 spin_lock(&xhci->lock);
2571 * If ep->skip is set, it means there are missed tds on the
2572 * endpoint ring need to take care of.
2573 * Process them as short transfer until reach the td pointed by
2576 } while (handling_skipped_tds);
2582 * This function handles all OS-owned events on the event ring. It may drop
2583 * xhci->lock between event processing (e.g. to pass up port status changes).
2584 * Returns >0 for "possibly more events to process" (caller should call again),
2585 * otherwise 0 if done. In future, <0 returns should indicate error code.
2587 static int xhci_handle_event(struct xhci_hcd *xhci)
2589 union xhci_trb *event;
2590 int update_ptrs = 1;
2593 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2594 xhci->error_bitmask |= 1 << 1;
2598 event = xhci->event_ring->dequeue;
2599 /* Does the HC or OS own the TRB? */
2600 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2601 xhci->event_ring->cycle_state) {
2602 xhci->error_bitmask |= 1 << 2;
2607 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2608 * speculative reads of the event's flags/data below.
2611 /* FIXME: Handle more event types. */
2612 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2613 case TRB_TYPE(TRB_COMPLETION):
2614 handle_cmd_completion(xhci, &event->event_cmd);
2616 case TRB_TYPE(TRB_PORT_STATUS):
2617 handle_port_status(xhci, event);
2620 case TRB_TYPE(TRB_TRANSFER):
2621 ret = handle_tx_event(xhci, &event->trans_event);
2623 xhci->error_bitmask |= 1 << 9;
2628 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2630 handle_vendor_event(xhci, event);
2632 xhci->error_bitmask |= 1 << 3;
2634 /* Any of the above functions may drop and re-acquire the lock, so check
2635 * to make sure a watchdog timer didn't mark the host as non-responsive.
2637 if (xhci->xhc_state & XHCI_STATE_DYING) {
2638 xhci_dbg(xhci, "xHCI host dying, returning from "
2639 "event handler.\n");
2644 /* Update SW event ring dequeue pointer */
2645 inc_deq(xhci, xhci->event_ring, true);
2647 /* Are there more items on the event ring? Caller will call us again to
2654 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2655 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2656 * indicators of an event TRB error, but we check the status *first* to be safe.
2658 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2660 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2662 union xhci_trb *trb;
2664 union xhci_trb *event_ring_deq;
2667 spin_lock(&xhci->lock);
2668 trb = xhci->event_ring->dequeue;
2669 /* Check if the xHC generated the interrupt, or the irq is shared */
2670 status = xhci_readl(xhci, &xhci->op_regs->status);
2671 if (status == 0xffffffff)
2674 if (!(status & STS_EINT)) {
2675 spin_unlock(&xhci->lock);
2678 if (status & STS_FATAL) {
2679 xhci_warn(xhci, "WARNING: Host System Error\n");
2682 spin_unlock(&xhci->lock);
2687 * Clear the op reg interrupt status first,
2688 * so we can receive interrupts from other MSI-X interrupters.
2689 * Write 1 to clear the interrupt status.
2692 xhci_writel(xhci, status, &xhci->op_regs->status);
2693 /* FIXME when MSI-X is supported and there are multiple vectors */
2694 /* Clear the MSI-X event interrupt status */
2696 if (hcd->irq != -1) {
2698 /* Acknowledge the PCI interrupt */
2699 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2700 irq_pending |= IMAN_IP;
2701 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2704 if (xhci->xhc_state & XHCI_STATE_DYING) {
2705 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2706 "Shouldn't IRQs be disabled?\n");
2707 /* Clear the event handler busy flag (RW1C);
2708 * the event ring should be empty.
2710 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2711 xhci_write_64(xhci, temp_64 | ERST_EHB,
2712 &xhci->ir_set->erst_dequeue);
2713 spin_unlock(&xhci->lock);
2718 event_ring_deq = xhci->event_ring->dequeue;
2719 /* FIXME this should be a delayed service routine
2720 * that clears the EHB.
2722 while (xhci_handle_event(xhci) > 0) {}
2724 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2725 /* If necessary, update the HW's version of the event ring deq ptr. */
2726 if (event_ring_deq != xhci->event_ring->dequeue) {
2727 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2728 xhci->event_ring->dequeue);
2730 xhci_warn(xhci, "WARN something wrong with SW event "
2731 "ring dequeue ptr.\n");
2732 /* Update HC event ring dequeue pointer */
2733 temp_64 &= ERST_PTR_MASK;
2734 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2737 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2738 temp_64 |= ERST_EHB;
2739 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2741 spin_unlock(&xhci->lock);
2746 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2749 struct xhci_hcd *xhci;
2751 xhci = hcd_to_xhci(hcd);
2752 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2753 if (xhci->shared_hcd)
2754 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2756 ret = xhci_irq(hcd);
2761 /**** Endpoint Ring Operations ****/
2764 * Generic function for queueing a TRB on a ring.
2765 * The caller must have checked to make sure there's room on the ring.
2767 * @more_trbs_coming: Will you enqueue more TRBs before calling
2768 * prepare_transfer()?
2770 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2771 bool consumer, bool more_trbs_coming, bool isoc,
2772 u32 field1, u32 field2, u32 field3, u32 field4)
2774 struct xhci_generic_trb *trb;
2776 trb = &ring->enqueue->generic;
2777 trb->field[0] = cpu_to_le32(field1);
2778 trb->field[1] = cpu_to_le32(field2);
2779 trb->field[2] = cpu_to_le32(field3);
2780 trb->field[3] = cpu_to_le32(field4);
2781 inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2785 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2786 * FIXME allocate segments if the ring is full.
2788 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2789 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2791 /* Make sure the endpoint has been added to xHC schedule */
2793 case EP_STATE_DISABLED:
2795 * USB core changed config/interfaces without notifying us,
2796 * or hardware is reporting the wrong state.
2798 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2800 case EP_STATE_ERROR:
2801 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2802 /* FIXME event handling code for error needs to clear it */
2803 /* XXX not sure if this should be -ENOENT or not */
2805 case EP_STATE_HALTED:
2806 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2807 case EP_STATE_STOPPED:
2808 case EP_STATE_RUNNING:
2811 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2813 * FIXME issue Configure Endpoint command to try to get the HC
2814 * back into a known state.
2818 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2819 /* FIXME allocate more room */
2820 xhci_err(xhci, "ERROR no room on ep ring\n");
2824 if (enqueue_is_link_trb(ep_ring)) {
2825 struct xhci_ring *ring = ep_ring;
2826 union xhci_trb *next;
2828 next = ring->enqueue;
2830 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2831 /* If we're not dealing with 0.95 hardware or isoc rings
2832 * on AMD 0.96 host, clear the chain bit.
2834 if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2835 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2836 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2838 next->link.control |= cpu_to_le32(TRB_CHAIN);
2841 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2843 /* Toggle the cycle bit after the last ring segment. */
2844 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2845 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2846 if (!in_interrupt()) {
2847 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2848 "state for ring %p = %i\n",
2849 ring, (unsigned int)ring->cycle_state);
2852 ring->enq_seg = ring->enq_seg->next;
2853 ring->enqueue = ring->enq_seg->trbs;
2854 next = ring->enqueue;
2861 static int prepare_transfer(struct xhci_hcd *xhci,
2862 struct xhci_virt_device *xdev,
2863 unsigned int ep_index,
2864 unsigned int stream_id,
2865 unsigned int num_trbs,
2867 unsigned int td_index,
2872 struct urb_priv *urb_priv;
2874 struct xhci_ring *ep_ring;
2875 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2877 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2879 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2884 ret = prepare_ring(xhci, ep_ring,
2885 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2886 num_trbs, isoc, mem_flags);
2890 urb_priv = urb->hcpriv;
2891 td = urb_priv->td[td_index];
2893 INIT_LIST_HEAD(&td->td_list);
2894 INIT_LIST_HEAD(&td->cancelled_td_list);
2896 if (td_index == 0) {
2897 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2903 /* Add this TD to the tail of the endpoint ring's TD list */
2904 list_add_tail(&td->td_list, &ep_ring->td_list);
2905 td->start_seg = ep_ring->enq_seg;
2906 td->first_trb = ep_ring->enqueue;
2908 urb_priv->td[td_index] = td;
2913 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2915 int num_sgs, num_trbs, running_total, temp, i;
2916 struct scatterlist *sg;
2919 num_sgs = urb->num_mapped_sgs;
2920 temp = urb->transfer_buffer_length;
2922 xhci_dbg(xhci, "count sg list trbs: \n");
2924 for_each_sg(urb->sg, sg, num_sgs, i) {
2925 unsigned int previous_total_trbs = num_trbs;
2926 unsigned int len = sg_dma_len(sg);
2928 /* Scatter gather list entries may cross 64KB boundaries */
2929 running_total = TRB_MAX_BUFF_SIZE -
2930 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2931 running_total &= TRB_MAX_BUFF_SIZE - 1;
2932 if (running_total != 0)
2935 /* How many more 64KB chunks to transfer, how many more TRBs? */
2936 while (running_total < sg_dma_len(sg) && running_total < temp) {
2938 running_total += TRB_MAX_BUFF_SIZE;
2940 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2941 i, (unsigned long long)sg_dma_address(sg),
2942 len, len, num_trbs - previous_total_trbs);
2944 len = min_t(int, len, temp);
2949 xhci_dbg(xhci, "\n");
2950 if (!in_interrupt())
2951 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2953 urb->ep->desc.bEndpointAddress,
2954 urb->transfer_buffer_length,
2959 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2962 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2963 "TRBs, %d left\n", __func__,
2964 urb->ep->desc.bEndpointAddress, num_trbs);
2965 if (running_total != urb->transfer_buffer_length)
2966 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2967 "queued %#x (%d), asked for %#x (%d)\n",
2969 urb->ep->desc.bEndpointAddress,
2970 running_total, running_total,
2971 urb->transfer_buffer_length,
2972 urb->transfer_buffer_length);
2975 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2976 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2977 struct xhci_generic_trb *start_trb)
2980 * Pass all the TRBs to the hardware at once and make sure this write
2985 start_trb->field[3] |= cpu_to_le32(start_cycle);
2987 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2988 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2992 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2993 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2994 * (comprised of sg list entries) can take several service intervals to
2997 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2998 struct urb *urb, int slot_id, unsigned int ep_index)
3000 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3001 xhci->devs[slot_id]->out_ctx, ep_index);
3005 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3006 ep_interval = urb->interval;
3007 /* Convert to microframes */
3008 if (urb->dev->speed == USB_SPEED_LOW ||
3009 urb->dev->speed == USB_SPEED_FULL)
3011 /* FIXME change this to a warning and a suggestion to use the new API
3012 * to set the polling interval (once the API is added).
3014 if (xhci_interval != ep_interval) {
3015 if (printk_ratelimit())
3016 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3017 " (%d microframe%s) than xHCI "
3018 "(%d microframe%s)\n",
3020 ep_interval == 1 ? "" : "s",
3022 xhci_interval == 1 ? "" : "s");
3023 urb->interval = xhci_interval;
3024 /* Convert back to frames for LS/FS devices */
3025 if (urb->dev->speed == USB_SPEED_LOW ||
3026 urb->dev->speed == USB_SPEED_FULL)
3029 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3033 * The TD size is the number of bytes remaining in the TD (including this TRB),
3034 * right shifted by 10.
3035 * It must fit in bits 21:17, so it can't be bigger than 31.
3037 static u32 xhci_td_remainder(unsigned int remainder)
3039 u32 max = (1 << (21 - 17 + 1)) - 1;
3041 if ((remainder >> 10) >= max)
3044 return (remainder >> 10) << 17;
3048 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3049 * packets remaining in the TD (*not* including this TRB).
3051 * Total TD packet count = total_packet_count =
3052 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3054 * Packets transferred up to and including this TRB = packets_transferred =
3055 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3057 * TD size = total_packet_count - packets_transferred
3059 * It must fit in bits 21:17, so it can't be bigger than 31.
3060 * The last TRB in a TD must have the TD size set to zero.
3062 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3063 unsigned int total_packet_count, struct urb *urb,
3064 unsigned int num_trbs_left)
3066 int packets_transferred;
3068 /* One TRB with a zero-length data packet. */
3069 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3072 /* All the TRB queueing functions don't count the current TRB in
3075 packets_transferred = (running_total + trb_buff_len) /
3076 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3078 if ((total_packet_count - packets_transferred) > 31)
3080 return (total_packet_count - packets_transferred) << 17;
3083 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3084 struct urb *urb, int slot_id, unsigned int ep_index)
3086 struct xhci_ring *ep_ring;
3087 unsigned int num_trbs;
3088 struct urb_priv *urb_priv;
3090 struct scatterlist *sg;
3092 int trb_buff_len, this_sg_len, running_total;
3093 unsigned int total_packet_count;
3096 bool more_trbs_coming;
3098 struct xhci_generic_trb *start_trb;
3101 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3105 num_trbs = count_sg_trbs_needed(xhci, urb);
3106 num_sgs = urb->num_mapped_sgs;
3107 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3108 usb_endpoint_maxp(&urb->ep->desc));
3110 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3111 ep_index, urb->stream_id,
3112 num_trbs, urb, 0, false, mem_flags);
3113 if (trb_buff_len < 0)
3114 return trb_buff_len;
3116 urb_priv = urb->hcpriv;
3117 td = urb_priv->td[0];
3120 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3121 * until we've finished creating all the other TRBs. The ring's cycle
3122 * state may change as we enqueue the other TRBs, so save it too.
3124 start_trb = &ep_ring->enqueue->generic;
3125 start_cycle = ep_ring->cycle_state;
3129 * How much data is in the first TRB?
3131 * There are three forces at work for TRB buffer pointers and lengths:
3132 * 1. We don't want to walk off the end of this sg-list entry buffer.
3133 * 2. The transfer length that the driver requested may be smaller than
3134 * the amount of memory allocated for this scatter-gather list.
3135 * 3. TRBs buffers can't cross 64KB boundaries.
3138 addr = (u64) sg_dma_address(sg);
3139 this_sg_len = sg_dma_len(sg);
3140 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3141 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3142 if (trb_buff_len > urb->transfer_buffer_length)
3143 trb_buff_len = urb->transfer_buffer_length;
3144 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3148 /* Queue the first TRB, even if it's zero-length */
3151 u32 length_field = 0;
3154 /* Don't change the cycle bit of the first TRB until later */
3157 if (start_cycle == 0)
3160 field |= ep_ring->cycle_state;
3162 /* Chain all the TRBs together; clear the chain bit in the last
3163 * TRB to indicate it's the last TRB in the chain.
3168 /* FIXME - add check for ZERO_PACKET flag before this */
3169 td->last_trb = ep_ring->enqueue;
3173 /* Only set interrupt on short packet for IN endpoints */
3174 if (usb_urb_dir_in(urb))
3177 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3178 "64KB boundary at %#x, end dma = %#x\n",
3179 (unsigned int) addr, trb_buff_len, trb_buff_len,
3180 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3181 (unsigned int) addr + trb_buff_len);
3182 if (TRB_MAX_BUFF_SIZE -
3183 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3184 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3185 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3186 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3187 (unsigned int) addr + trb_buff_len);
3190 /* Set the TRB length, TD size, and interrupter fields. */
3191 if (xhci->hci_version < 0x100) {
3192 remainder = xhci_td_remainder(
3193 urb->transfer_buffer_length -
3196 remainder = xhci_v1_0_td_remainder(running_total,
3197 trb_buff_len, total_packet_count, urb,
3200 length_field = TRB_LEN(trb_buff_len) |
3205 more_trbs_coming = true;
3207 more_trbs_coming = false;
3208 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3209 lower_32_bits(addr),
3210 upper_32_bits(addr),
3212 field | TRB_TYPE(TRB_NORMAL));
3214 running_total += trb_buff_len;
3216 /* Calculate length for next transfer --
3217 * Are we done queueing all the TRBs for this sg entry?
3219 this_sg_len -= trb_buff_len;
3220 if (this_sg_len == 0) {
3225 addr = (u64) sg_dma_address(sg);
3226 this_sg_len = sg_dma_len(sg);
3228 addr += trb_buff_len;
3231 trb_buff_len = TRB_MAX_BUFF_SIZE -
3232 (addr & (TRB_MAX_BUFF_SIZE - 1));
3233 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3234 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3236 urb->transfer_buffer_length - running_total;
3237 } while (running_total < urb->transfer_buffer_length);
3239 check_trb_math(urb, num_trbs, running_total);
3240 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3241 start_cycle, start_trb);
3245 /* This is very similar to what ehci-q.c qtd_fill() does */
3246 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3247 struct urb *urb, int slot_id, unsigned int ep_index)
3249 struct xhci_ring *ep_ring;
3250 struct urb_priv *urb_priv;
3253 struct xhci_generic_trb *start_trb;
3255 bool more_trbs_coming;
3257 u32 field, length_field;
3259 int running_total, trb_buff_len, ret;
3260 unsigned int total_packet_count;
3264 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3266 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3271 /* How much data is (potentially) left before the 64KB boundary? */
3272 running_total = TRB_MAX_BUFF_SIZE -
3273 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3274 running_total &= TRB_MAX_BUFF_SIZE - 1;
3276 /* If there's some data on this 64KB chunk, or we have to send a
3277 * zero-length transfer, we need at least one TRB
3279 if (running_total != 0 || urb->transfer_buffer_length == 0)
3281 /* How many more 64KB chunks to transfer, how many more TRBs? */
3282 while (running_total < urb->transfer_buffer_length) {
3284 running_total += TRB_MAX_BUFF_SIZE;
3286 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3288 if (!in_interrupt())
3289 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3290 "addr = %#llx, num_trbs = %d\n",
3291 urb->ep->desc.bEndpointAddress,
3292 urb->transfer_buffer_length,
3293 urb->transfer_buffer_length,
3294 (unsigned long long)urb->transfer_dma,
3297 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3298 ep_index, urb->stream_id,
3299 num_trbs, urb, 0, false, mem_flags);
3303 urb_priv = urb->hcpriv;
3304 td = urb_priv->td[0];
3307 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3308 * until we've finished creating all the other TRBs. The ring's cycle
3309 * state may change as we enqueue the other TRBs, so save it too.
3311 start_trb = &ep_ring->enqueue->generic;
3312 start_cycle = ep_ring->cycle_state;
3315 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3316 usb_endpoint_maxp(&urb->ep->desc));
3317 /* How much data is in the first TRB? */
3318 addr = (u64) urb->transfer_dma;
3319 trb_buff_len = TRB_MAX_BUFF_SIZE -
3320 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3321 if (trb_buff_len > urb->transfer_buffer_length)
3322 trb_buff_len = urb->transfer_buffer_length;
3326 /* Queue the first TRB, even if it's zero-length */
3331 /* Don't change the cycle bit of the first TRB until later */
3334 if (start_cycle == 0)
3337 field |= ep_ring->cycle_state;
3339 /* Chain all the TRBs together; clear the chain bit in the last
3340 * TRB to indicate it's the last TRB in the chain.
3345 /* FIXME - add check for ZERO_PACKET flag before this */
3346 td->last_trb = ep_ring->enqueue;
3350 /* Only set interrupt on short packet for IN endpoints */
3351 if (usb_urb_dir_in(urb))
3354 /* Set the TRB length, TD size, and interrupter fields. */
3355 if (xhci->hci_version < 0x100) {
3356 remainder = xhci_td_remainder(
3357 urb->transfer_buffer_length -
3360 remainder = xhci_v1_0_td_remainder(running_total,
3361 trb_buff_len, total_packet_count, urb,
3364 length_field = TRB_LEN(trb_buff_len) |
3369 more_trbs_coming = true;
3371 more_trbs_coming = false;
3372 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3373 lower_32_bits(addr),
3374 upper_32_bits(addr),
3376 field | TRB_TYPE(TRB_NORMAL));
3378 running_total += trb_buff_len;
3380 /* Calculate length for next transfer */
3381 addr += trb_buff_len;
3382 trb_buff_len = urb->transfer_buffer_length - running_total;
3383 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3384 trb_buff_len = TRB_MAX_BUFF_SIZE;
3385 } while (running_total < urb->transfer_buffer_length);
3387 check_trb_math(urb, num_trbs, running_total);
3388 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3389 start_cycle, start_trb);
3393 /* Caller must have locked xhci->lock */
3394 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3395 struct urb *urb, int slot_id, unsigned int ep_index)
3397 struct xhci_ring *ep_ring;
3400 struct usb_ctrlrequest *setup;
3401 struct xhci_generic_trb *start_trb;
3403 u32 field, length_field;
3404 struct urb_priv *urb_priv;
3407 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3412 * Need to copy setup packet into setup TRB, so we can't use the setup
3415 if (!urb->setup_packet)
3418 if (!in_interrupt())
3419 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3421 /* 1 TRB for setup, 1 for status */
3424 * Don't need to check if we need additional event data and normal TRBs,
3425 * since data in control transfers will never get bigger than 16MB
3426 * XXX: can we get a buffer that crosses 64KB boundaries?
3428 if (urb->transfer_buffer_length > 0)
3430 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3431 ep_index, urb->stream_id,
3432 num_trbs, urb, 0, false, mem_flags);
3436 urb_priv = urb->hcpriv;
3437 td = urb_priv->td[0];
3440 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3441 * until we've finished creating all the other TRBs. The ring's cycle
3442 * state may change as we enqueue the other TRBs, so save it too.
3444 start_trb = &ep_ring->enqueue->generic;
3445 start_cycle = ep_ring->cycle_state;
3447 /* Queue setup TRB - see section 6.4.1.2.1 */
3448 /* FIXME better way to translate setup_packet into two u32 fields? */
3449 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3451 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3452 if (start_cycle == 0)
3455 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3456 if (xhci->hci_version >= 0x100) {
3457 if (urb->transfer_buffer_length > 0) {
3458 if (setup->bRequestType & USB_DIR_IN)
3459 field |= TRB_TX_TYPE(TRB_DATA_IN);
3461 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3465 queue_trb(xhci, ep_ring, false, true, false,
3466 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3467 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3468 TRB_LEN(8) | TRB_INTR_TARGET(0),
3469 /* Immediate data in pointer */
3472 /* If there's data, queue data TRBs */
3473 /* Only set interrupt on short packet for IN endpoints */
3474 if (usb_urb_dir_in(urb))
3475 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3477 field = TRB_TYPE(TRB_DATA);
3479 length_field = TRB_LEN(urb->transfer_buffer_length) |
3480 xhci_td_remainder(urb->transfer_buffer_length) |
3482 if (urb->transfer_buffer_length > 0) {
3483 if (setup->bRequestType & USB_DIR_IN)
3484 field |= TRB_DIR_IN;
3485 queue_trb(xhci, ep_ring, false, true, false,
3486 lower_32_bits(urb->transfer_dma),
3487 upper_32_bits(urb->transfer_dma),
3489 field | ep_ring->cycle_state);
3492 /* Save the DMA address of the last TRB in the TD */
3493 td->last_trb = ep_ring->enqueue;
3495 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3496 /* If the device sent data, the status stage is an OUT transfer */
3497 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3501 queue_trb(xhci, ep_ring, false, false, false,
3505 /* Event on completion */
3506 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3508 giveback_first_trb(xhci, slot_id, ep_index, 0,
3509 start_cycle, start_trb);
3513 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3514 struct urb *urb, int i)
3519 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3520 td_len = urb->iso_frame_desc[i].length;
3522 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3531 * The transfer burst count field of the isochronous TRB defines the number of
3532 * bursts that are required to move all packets in this TD. Only SuperSpeed
3533 * devices can burst up to bMaxBurst number of packets per service interval.
3534 * This field is zero based, meaning a value of zero in the field means one
3535 * burst. Basically, for everything but SuperSpeed devices, this field will be
3536 * zero. Only xHCI 1.0 host controllers support this field.
3538 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3539 struct usb_device *udev,
3540 struct urb *urb, unsigned int total_packet_count)
3542 unsigned int max_burst;
3544 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3547 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3548 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3552 * Returns the number of packets in the last "burst" of packets. This field is
3553 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3554 * the last burst packet count is equal to the total number of packets in the
3555 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3556 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3557 * contain 1 to (bMaxBurst + 1) packets.
3559 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3560 struct usb_device *udev,
3561 struct urb *urb, unsigned int total_packet_count)
3563 unsigned int max_burst;
3564 unsigned int residue;
3566 if (xhci->hci_version < 0x100)
3569 switch (udev->speed) {
3570 case USB_SPEED_SUPER:
3571 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3572 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3573 residue = total_packet_count % (max_burst + 1);
3574 /* If residue is zero, the last burst contains (max_burst + 1)
3575 * number of packets, but the TLBPC field is zero-based.
3581 if (total_packet_count == 0)
3583 return total_packet_count - 1;
3587 /* This is for isoc transfer */
3588 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3589 struct urb *urb, int slot_id, unsigned int ep_index)
3591 struct xhci_ring *ep_ring;
3592 struct urb_priv *urb_priv;
3594 int num_tds, trbs_per_td;
3595 struct xhci_generic_trb *start_trb;
3598 u32 field, length_field;
3599 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3600 u64 start_addr, addr;
3602 bool more_trbs_coming;
3604 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3606 num_tds = urb->number_of_packets;
3608 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3612 if (!in_interrupt())
3613 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3614 " addr = %#llx, num_tds = %d\n",
3615 urb->ep->desc.bEndpointAddress,
3616 urb->transfer_buffer_length,
3617 urb->transfer_buffer_length,
3618 (unsigned long long)urb->transfer_dma,
3621 start_addr = (u64) urb->transfer_dma;
3622 start_trb = &ep_ring->enqueue->generic;
3623 start_cycle = ep_ring->cycle_state;
3625 urb_priv = urb->hcpriv;
3626 /* Queue the first TRB, even if it's zero-length */
3627 for (i = 0; i < num_tds; i++) {
3628 unsigned int total_packet_count;
3629 unsigned int burst_count;
3630 unsigned int residue;
3634 addr = start_addr + urb->iso_frame_desc[i].offset;
3635 td_len = urb->iso_frame_desc[i].length;
3636 td_remain_len = td_len;
3637 total_packet_count = DIV_ROUND_UP(td_len,
3639 usb_endpoint_maxp(&urb->ep->desc)));
3640 /* A zero-length transfer still involves at least one packet. */
3641 if (total_packet_count == 0)
3642 total_packet_count++;
3643 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3644 total_packet_count);
3645 residue = xhci_get_last_burst_packet_count(xhci,
3646 urb->dev, urb, total_packet_count);
3648 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3650 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3651 urb->stream_id, trbs_per_td, urb, i, true,
3659 td = urb_priv->td[i];
3660 for (j = 0; j < trbs_per_td; j++) {
3665 field = TRB_TBC(burst_count) |
3667 /* Queue the isoc TRB */
3668 field |= TRB_TYPE(TRB_ISOC);
3669 /* Assume URB_ISO_ASAP is set */
3672 if (start_cycle == 0)
3675 field |= ep_ring->cycle_state;
3678 /* Queue other normal TRBs */
3679 field |= TRB_TYPE(TRB_NORMAL);
3680 field |= ep_ring->cycle_state;
3683 /* Only set interrupt on short packet for IN EPs */
3684 if (usb_urb_dir_in(urb))
3687 /* Chain all the TRBs together; clear the chain bit in
3688 * the last TRB to indicate it's the last TRB in the
3691 if (j < trbs_per_td - 1) {
3693 more_trbs_coming = true;
3695 td->last_trb = ep_ring->enqueue;
3697 if (xhci->hci_version == 0x100 &&
3700 /* Set BEI bit except for the last td */
3701 if (i < num_tds - 1)
3704 more_trbs_coming = false;
3707 /* Calculate TRB length */
3708 trb_buff_len = TRB_MAX_BUFF_SIZE -
3709 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3710 if (trb_buff_len > td_remain_len)
3711 trb_buff_len = td_remain_len;
3713 /* Set the TRB length, TD size, & interrupter fields. */
3714 if (xhci->hci_version < 0x100) {
3715 remainder = xhci_td_remainder(
3716 td_len - running_total);
3718 remainder = xhci_v1_0_td_remainder(
3719 running_total, trb_buff_len,
3720 total_packet_count, urb,
3721 (trbs_per_td - j - 1));
3723 length_field = TRB_LEN(trb_buff_len) |
3727 queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3728 lower_32_bits(addr),
3729 upper_32_bits(addr),
3732 running_total += trb_buff_len;
3734 addr += trb_buff_len;
3735 td_remain_len -= trb_buff_len;
3738 /* Check TD length */
3739 if (running_total != td_len) {
3740 xhci_err(xhci, "ISOC TD length unmatch\n");
3746 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3747 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3748 usb_amd_quirk_pll_disable();
3750 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3752 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3753 start_cycle, start_trb);
3756 /* Clean up a partially enqueued isoc transfer. */
3758 for (i--; i >= 0; i--)
3759 list_del_init(&urb_priv->td[i]->td_list);
3761 /* Use the first TD as a temporary variable to turn the TDs we've queued
3762 * into No-ops with a software-owned cycle bit. That way the hardware
3763 * won't accidentally start executing bogus TDs when we partially
3764 * overwrite them. td->first_trb and td->start_seg are already set.
3766 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3767 /* Every TRB except the first & last will have its cycle bit flipped. */
3768 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3770 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3771 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3772 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3773 ep_ring->cycle_state = start_cycle;
3774 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3779 * Check transfer ring to guarantee there is enough room for the urb.
3780 * Update ISO URB start_frame and interval.
3781 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3782 * update the urb->start_frame by now.
3783 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3785 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3786 struct urb *urb, int slot_id, unsigned int ep_index)
3788 struct xhci_virt_device *xdev;
3789 struct xhci_ring *ep_ring;
3790 struct xhci_ep_ctx *ep_ctx;
3794 int num_tds, num_trbs, i;
3797 xdev = xhci->devs[slot_id];
3798 ep_ring = xdev->eps[ep_index].ring;
3799 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3802 num_tds = urb->number_of_packets;
3803 for (i = 0; i < num_tds; i++)
3804 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3806 /* Check the ring to guarantee there is enough room for the whole urb.
3807 * Do not insert any td of the urb to the ring if the check failed.
3809 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3810 num_trbs, true, mem_flags);
3814 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3815 start_frame &= 0x3fff;
3817 urb->start_frame = start_frame;
3818 if (urb->dev->speed == USB_SPEED_LOW ||
3819 urb->dev->speed == USB_SPEED_FULL)
3820 urb->start_frame >>= 3;
3822 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3823 ep_interval = urb->interval;
3824 /* Convert to microframes */
3825 if (urb->dev->speed == USB_SPEED_LOW ||
3826 urb->dev->speed == USB_SPEED_FULL)
3828 /* FIXME change this to a warning and a suggestion to use the new API
3829 * to set the polling interval (once the API is added).
3831 if (xhci_interval != ep_interval) {
3832 if (printk_ratelimit())
3833 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3834 " (%d microframe%s) than xHCI "
3835 "(%d microframe%s)\n",
3837 ep_interval == 1 ? "" : "s",
3839 xhci_interval == 1 ? "" : "s");
3840 urb->interval = xhci_interval;
3841 /* Convert back to frames for LS/FS devices */
3842 if (urb->dev->speed == USB_SPEED_LOW ||
3843 urb->dev->speed == USB_SPEED_FULL)
3846 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3849 /**** Command Ring Operations ****/
3851 /* Generic function for queueing a command TRB on the command ring.
3852 * Check to make sure there's room on the command ring for one command TRB.
3853 * Also check that there's room reserved for commands that must not fail.
3854 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3855 * then only check for the number of reserved spots.
3856 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3857 * because the command event handler may want to resubmit a failed command.
3859 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3860 u32 field3, u32 field4, bool command_must_succeed)
3862 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3865 if (!command_must_succeed)
3868 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3869 reserved_trbs, false, GFP_ATOMIC);
3871 xhci_err(xhci, "ERR: No room for command on command ring\n");
3872 if (command_must_succeed)
3873 xhci_err(xhci, "ERR: Reserved TRB counting for "
3874 "unfailable commands failed.\n");
3877 queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3878 field3, field4 | xhci->cmd_ring->cycle_state);
3882 /* Queue a slot enable or disable request on the command ring */
3883 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3885 return queue_command(xhci, 0, 0, 0,
3886 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3889 /* Queue an address device command TRB */
3890 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3893 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3894 upper_32_bits(in_ctx_ptr), 0,
3895 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3899 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3900 u32 field1, u32 field2, u32 field3, u32 field4)
3902 return queue_command(xhci, field1, field2, field3, field4, false);
3905 /* Queue a reset device command TRB */
3906 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3908 return queue_command(xhci, 0, 0, 0,
3909 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3913 /* Queue a configure endpoint command TRB */
3914 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3915 u32 slot_id, bool command_must_succeed)
3917 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3918 upper_32_bits(in_ctx_ptr), 0,
3919 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3920 command_must_succeed);
3923 /* Queue an evaluate context command TRB */
3924 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3927 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3928 upper_32_bits(in_ctx_ptr), 0,
3929 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3934 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3935 * activity on an endpoint that is about to be suspended.
3937 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3938 unsigned int ep_index, int suspend)
3940 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3941 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3942 u32 type = TRB_TYPE(TRB_STOP_RING);
3943 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3945 return queue_command(xhci, 0, 0, 0,
3946 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3949 /* Set Transfer Ring Dequeue Pointer command.
3950 * This should not be used for endpoints that have streams enabled.
3952 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3953 unsigned int ep_index, unsigned int stream_id,
3954 struct xhci_segment *deq_seg,
3955 union xhci_trb *deq_ptr, u32 cycle_state)
3958 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3959 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3960 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3961 u32 type = TRB_TYPE(TRB_SET_DEQ);
3962 struct xhci_virt_ep *ep;
3964 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3966 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3967 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3971 ep = &xhci->devs[slot_id]->eps[ep_index];
3972 if ((ep->ep_state & SET_DEQ_PENDING)) {
3973 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3974 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3977 ep->queued_deq_seg = deq_seg;
3978 ep->queued_deq_ptr = deq_ptr;
3979 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3980 upper_32_bits(addr), trb_stream_id,
3981 trb_slot_id | trb_ep_index | type, false);
3984 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3985 unsigned int ep_index)
3987 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3988 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3989 u32 type = TRB_TYPE(TRB_RESET_EP);
3991 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,