drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         union xhci_trb *next = ++(ring->dequeue);
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152         /* Update the dequeue pointer further if that was a link TRB or we're at
 153          * the end of an event ring segment (which doesn't have link TRBS)
 154          */
 155         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 156                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 157                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 158                         if (!in_interrupt())
 159                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 160                                                 ring,
 161                                                 (unsigned int) ring->cycle_state);
 162                 }
 163                 ring->deq_seg = ring->deq_seg->next;
 164                 ring->dequeue = ring->deq_seg->trbs;
 165                 next = ring->dequeue;
 166         }
 167         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 168 }
 169
 170 /*
 171  * See Cycle bit rules. SW is the consumer for the event ring only.
 172  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 173  *
 174  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 175  * chain bit is set), then set the chain bit in all the following link TRBs.
 176  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 177  * have their chain bit cleared (so that each Link TRB is a separate TD).
 178  *
 179  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 180  * set, but other sections talk about dealing with the chain bit set.  This was
 181  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 182  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 183  *
 184  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 185  *                      prepare_transfer()?
 186  */
 187 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 188                 bool consumer, bool more_trbs_coming, bool isoc)
 189 {
 190         u32 chain;
 191         union xhci_trb *next;
 192         unsigned long long addr;
 193
 194         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 195         next = ++(ring->enqueue);
 196
 197         ring->enq_updates++;
 198         /* Update the dequeue pointer further if that was a link TRB or we're at
 199          * the end of an event ring segment (which doesn't have link TRBS)
 200          */
 201         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 202                 if (!consumer) {
 203                         if (ring != xhci->event_ring) {
 204                                 /*
 205                                  * If the caller doesn't plan on enqueueing more
 206                                  * TDs before ringing the doorbell, then we
 207                                  * don't want to give the link TRB to the
 208                                  * hardware just yet.  We'll give the link TRB
 209                                  * back in prepare_ring() just before we enqueue
 210                                  * the TD at the top of the ring.
 211                                  */
 212                                 if (!chain && !more_trbs_coming)
 213                                         break;
 214
 215                                 /* If we're not dealing with 0.95 hardware or
 216                                  * isoc rings on AMD 0.96 host,
 217                                  * carry over the chain bit of the previous TRB
 218                                  * (which may mean the chain bit is cleared).
 219                                  */
 220                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 221                                                 && !xhci_link_trb_quirk(xhci)) {
 222                                         next->link.control &=
 223                                                 cpu_to_le32(~TRB_CHAIN);
 224                                         next->link.control |=
 225                                                 cpu_to_le32(chain);
 226                                 }
 227                                 /* Give this link TRB to the hardware */
 228                                 wmb();
 229                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 230                         }
 231                         /* Toggle the cycle bit after the last ring segment. */
 232                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 233                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 234                                 if (!in_interrupt())
 235                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 236                                                         ring,
 237                                                         (unsigned int) ring->cycle_state);
 238                         }
 239                 }
 240                 ring->enq_seg = ring->enq_seg->next;
 241                 ring->enqueue = ring->enq_seg->trbs;
 242                 next = ring->enqueue;
 243         }
 244         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 245 }
 246
 247 /*
 248  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 249  * above.
 250  * FIXME: this would be simpler and faster if we just kept track of the number
 251  * of free TRBs in a ring.
 252  */
 253 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 254                 unsigned int num_trbs)
 255 {
 256         int i;
 257         union xhci_trb *enq = ring->enqueue;
 258         struct xhci_segment *enq_seg = ring->enq_seg;
 259         struct xhci_segment *cur_seg;
 260         unsigned int left_on_ring;
 261
 262         /* If we are currently pointing to a link TRB, advance the
 263          * enqueue pointer before checking for space */
 264         while (last_trb(xhci, ring, enq_seg, enq)) {
 265                 enq_seg = enq_seg->next;
 266                 enq = enq_seg->trbs;
 267         }
 268
 269         /* Check if ring is empty */
 270         if (enq == ring->dequeue) {
 271                 /* Can't use link trbs */
 272                 left_on_ring = TRBS_PER_SEGMENT - 1;
 273                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 274                                 cur_seg = cur_seg->next)
 275                         left_on_ring += TRBS_PER_SEGMENT - 1;
 276
 277                 /* Always need one TRB free in the ring. */
 278                 left_on_ring -= 1;
 279                 if (num_trbs > left_on_ring) {
 280                         xhci_warn(xhci, "Not enough room on ring; "
 281                                         "need %u TRBs, %u TRBs left\n",
 282                                         num_trbs, left_on_ring);
 283                         return 0;
 284                 }
 285                 return 1;
 286         }
 287         /* Make sure there's an extra empty TRB available */
 288         for (i = 0; i <= num_trbs; ++i) {
 289                 if (enq == ring->dequeue)
 290                         return 0;
 291                 enq++;
 292                 while (last_trb(xhci, ring, enq_seg, enq)) {
 293                         enq_seg = enq_seg->next;
 294                         enq = enq_seg->trbs;
 295                 }
 296         }
 297         return 1;
 298 }
 299
 300 /* Ring the host controller doorbell after placing a command on the ring */
 301 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 302 {
 303         xhci_dbg(xhci, "// Ding dong!\n");
 304         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 305         /* Flush PCI posted writes */
 306         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 307 }
 308
 309 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 310                 unsigned int slot_id,
 311                 unsigned int ep_index,
 312                 unsigned int stream_id)
 313 {
 314         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 315         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 316         unsigned int ep_state = ep->ep_state;
 317
 318         /* Don't ring the doorbell for this endpoint if there are pending
 319          * cancellations because we don't want to interrupt processing.
 320          * We don't want to restart any stream rings if there's a set dequeue
 321          * pointer command pending because the device can choose to start any
 322          * stream once the endpoint is on the HW schedule.
 323          * FIXME - check all the stream rings for pending cancellations.
 324          */
 325         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 326             (ep_state & EP_HALTED))
 327                 return;
 328         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 329         /* The CPU has better things to do at this point than wait for a
 330          * write-posting flush.  It'll get there soon enough.
 331          */
 332 }
 333
 334 /* Ring the doorbell for any rings with pending URBs */
 335 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 336                 unsigned int slot_id,
 337                 unsigned int ep_index)
 338 {
 339         unsigned int stream_id;
 340         struct xhci_virt_ep *ep;
 341
 342         ep = &xhci->devs[slot_id]->eps[ep_index];
 343
 344         /* A ring has pending URBs if its TD list is not empty */
 345         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 346                 if (!(list_empty(&ep->ring->td_list)))
 347                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 348                 return;
 349         }
 350
 351         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 352                         stream_id++) {
 353                 struct xhci_stream_info *stream_info = ep->stream_info;
 354                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 355                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 356                                                 stream_id);
 357         }
 358 }
 359
 360 /*
 361  * Find the segment that trb is in.  Start searching in start_seg.
 362  * If we must move past a segment that has a link TRB with a toggle cycle state
 363  * bit set, then we will toggle the value pointed at by cycle_state.
 364  */
 365 static struct xhci_segment *find_trb_seg(
 366                 struct xhci_segment *start_seg,
 367                 union xhci_trb  *trb, int *cycle_state)
 368 {
 369         struct xhci_segment *cur_seg = start_seg;
 370         struct xhci_generic_trb *generic_trb;
 371
 372         while (cur_seg->trbs > trb ||
 373                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 374                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 375                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 376                         *cycle_state ^= 0x1;
 377                 cur_seg = cur_seg->next;
 378                 if (cur_seg == start_seg)
 379                         /* Looped over the entire list.  Oops! */
 380                         return NULL;
 381         }
 382         return cur_seg;
 383 }
 384
 385
 386 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 387                 unsigned int slot_id, unsigned int ep_index,
 388                 unsigned int stream_id)
 389 {
 390         struct xhci_virt_ep *ep;
 391
 392         ep = &xhci->devs[slot_id]->eps[ep_index];
 393         /* Common case: no streams */
 394         if (!(ep->ep_state & EP_HAS_STREAMS))
 395                 return ep->ring;
 396
 397         if (stream_id == 0) {
 398                 xhci_warn(xhci,
 399                                 "WARN: Slot ID %u, ep index %u has streams, "
 400                                 "but URB has no stream ID.\n",
 401                                 slot_id, ep_index);
 402                 return NULL;
 403         }
 404
 405         if (stream_id < ep->stream_info->num_streams)
 406                 return ep->stream_info->stream_rings[stream_id];
 407
 408         xhci_warn(xhci,
 409                         "WARN: Slot ID %u, ep index %u has "
 410                         "stream IDs 1 to %u allocated, "
 411                         "but stream ID %u is requested.\n",
 412                         slot_id, ep_index,
 413                         ep->stream_info->num_streams - 1,
 414                         stream_id);
 415         return NULL;
 416 }
 417
 418 /* Get the right ring for the given URB.
 419  * If the endpoint supports streams, boundary check the URB's stream ID.
 420  * If the endpoint doesn't support streams, return the singular endpoint ring.
 421  */
 422 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 423                 struct urb *urb)
 424 {
 425         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 426                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 427 }
 428
 429 /*
 430  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 431  * Record the new state of the xHC's endpoint ring dequeue segment,
 432  * dequeue pointer, and new consumer cycle state in state.
 433  * Update our internal representation of the ring's dequeue pointer.
 434  *
 435  * We do this in three jumps:
 436  *  - First we update our new ring state to be the same as when the xHC stopped.
 437  *  - Then we traverse the ring to find the segment that contains
 438  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 439  *    any link TRBs with the toggle cycle bit set.
 440  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 441  *    if we've moved it past a link TRB with the toggle cycle bit set.
 442  *
 443  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 444  * with correct __le32 accesses they should work fine.  Only users of this are
 445  * in here.
 446  */
 447 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 448                 unsigned int slot_id, unsigned int ep_index,
 449                 unsigned int stream_id, struct xhci_td *cur_td,
 450                 struct xhci_dequeue_state *state)
 451 {
 452         struct xhci_virt_device *dev = xhci->devs[slot_id];
 453         struct xhci_ring *ep_ring;
 454         struct xhci_generic_trb *trb;
 455         struct xhci_ep_ctx *ep_ctx;
 456         dma_addr_t addr;
 457
 458         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 459                         ep_index, stream_id);
 460         if (!ep_ring) {
 461                 xhci_warn(xhci, "WARN can't find new dequeue state "
 462                                 "for invalid stream ID %u.\n",
 463                                 stream_id);
 464                 return;
 465         }
 466         state->new_cycle_state = 0;
 467         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 468         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 469                         dev->eps[ep_index].stopped_trb,
 470                         &state->new_cycle_state);
 471         if (!state->new_deq_seg) {
 472                 WARN_ON(1);
 473                 return;
 474         }
 475
 476         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 477         xhci_dbg(xhci, "Finding endpoint context\n");
 478         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 479         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 480
 481         state->new_deq_ptr = cur_td->last_trb;
 482         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 483         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 484                         state->new_deq_ptr,
 485                         &state->new_cycle_state);
 486         if (!state->new_deq_seg) {
 487                 WARN_ON(1);
 488                 return;
 489         }
 490
 491         trb = &state->new_deq_ptr->generic;
 492         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 493             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 494                 state->new_cycle_state ^= 0x1;
 495         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 496
 497         /*
 498          * If there is only one segment in a ring, find_trb_seg()'s while loop
 499          * will not run, and it will return before it has a chance to see if it
 500          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 501          * ended just before the link TRB on a one-segment ring, or if the TD
 502          * wrapped around the top of the ring, because it doesn't have the TD in
 503          * question.  Look for the one-segment case where stalled TRB's address
 504          * is greater than the new dequeue pointer address.
 505          */
 506         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 507                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 508                 state->new_cycle_state ^= 0x1;
 509         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 510
 511         /* Don't update the ring cycle state for the producer (us). */
 512         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 513                         state->new_deq_seg);
 514         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 515         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 516                         (unsigned long long) addr);
 517 }
 518
 519 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 520  * (The last TRB actually points to the ring enqueue pointer, which is not part
 521  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 522  */
 523 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 524                 struct xhci_td *cur_td, bool flip_cycle)
 525 {
 526         struct xhci_segment *cur_seg;
 527         union xhci_trb *cur_trb;
 528
 529         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 530                         true;
 531                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 532                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 533                         /* Unchain any chained Link TRBs, but
 534                          * leave the pointers intact.
 535                          */
 536                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 537                         /* Flip the cycle bit (link TRBs can't be the first
 538                          * or last TRB).
 539                          */
 540                         if (flip_cycle)
 541                                 cur_trb->generic.field[3] ^=
 542                                         cpu_to_le32(TRB_CYCLE);
 543                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 544                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 545                                         "in seg %p (0x%llx dma)\n",
 546                                         cur_trb,
 547                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 548                                         cur_seg,
 549                                         (unsigned long long)cur_seg->dma);
 550                 } else {
 551                         cur_trb->generic.field[0] = 0;
 552                         cur_trb->generic.field[1] = 0;
 553                         cur_trb->generic.field[2] = 0;
 554                         /* Preserve only the cycle bit of this TRB */
 555                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 556                         /* Flip the cycle bit except on the first or last TRB */
 557                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 558                                         cur_trb != cur_td->last_trb)
 559                                 cur_trb->generic.field[3] ^=
 560                                         cpu_to_le32(TRB_CYCLE);
 561                         cur_trb->generic.field[3] |= cpu_to_le32(
 562                                 TRB_TYPE(TRB_TR_NOOP));
 563                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 564                                         "in seg %p (0x%llx dma)\n",
 565                                         cur_trb,
 566                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 567                                         cur_seg,
 568                                         (unsigned long long)cur_seg->dma);
 569                 }
 570                 if (cur_trb == cur_td->last_trb)
 571                         break;
 572         }
 573 }
 574
 575 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 576                 unsigned int ep_index, unsigned int stream_id,
 577                 struct xhci_segment *deq_seg,
 578                 union xhci_trb *deq_ptr, u32 cycle_state);
 579
 580 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 581                 unsigned int slot_id, unsigned int ep_index,
 582                 unsigned int stream_id,
 583                 struct xhci_dequeue_state *deq_state)
 584 {
 585         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 586
 587         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 588                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 589                         deq_state->new_deq_seg,
 590                         (unsigned long long)deq_state->new_deq_seg->dma,
 591                         deq_state->new_deq_ptr,
 592                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 593                         deq_state->new_cycle_state);
 594         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 595                         deq_state->new_deq_seg,
 596                         deq_state->new_deq_ptr,
 597                         (u32) deq_state->new_cycle_state);
 598         /* Stop the TD queueing code from ringing the doorbell until
 599          * this command completes.  The HC won't set the dequeue pointer
 600          * if the ring is running, and ringing the doorbell starts the
 601          * ring running.
 602          */
 603         ep->ep_state |= SET_DEQ_PENDING;
 604 }
 605
 606 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 607                 struct xhci_virt_ep *ep)
 608 {
 609         ep->ep_state &= ~EP_HALT_PENDING;
 610         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 611          * timer is running on another CPU, we don't decrement stop_cmds_pending
 612          * (since we didn't successfully stop the watchdog timer).
 613          */
 614         if (del_timer(&ep->stop_cmd_timer))
 615                 ep->stop_cmds_pending--;
 616 }
 617
 618 /* Must be called with xhci->lock held in interrupt context */
 619 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 620                 struct xhci_td *cur_td, int status, char *adjective)
 621 {
 622         struct usb_hcd *hcd;
 623         struct urb      *urb;
 624         struct urb_priv *urb_priv;
 625
 626         urb = cur_td->urb;
 627         urb_priv = urb->hcpriv;
 628         urb_priv->td_cnt++;
 629         hcd = bus_to_hcd(urb->dev->bus);
 630
 631         /* Only giveback urb when this is the last td in urb */
 632         if (urb_priv->td_cnt == urb_priv->length) {
 633                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 634                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 635                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 636                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 637                                         usb_amd_quirk_pll_enable();
 638                         }
 639                 }
 640                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 641
 642                 spin_unlock(&xhci->lock);
 643                 usb_hcd_giveback_urb(hcd, urb, status);
 644                 xhci_urb_free_priv(xhci, urb_priv);
 645                 spin_lock(&xhci->lock);
 646         }
 647 }
 648
 649 /*
 650  * When we get a command completion for a Stop Endpoint Command, we need to
 651  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 652  *
 653  *  1. If the HW was in the middle of processing the TD that needs to be
 654  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 655  *     in the TD with a Set Dequeue Pointer Command.
 656  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 657  *     bit cleared) so that the HW will skip over them.
 658  */
 659 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 660                 union xhci_trb *trb, struct xhci_event_cmd *event)
 661 {
 662         unsigned int slot_id;
 663         unsigned int ep_index;
 664         struct xhci_virt_device *virt_dev;
 665         struct xhci_ring *ep_ring;
 666         struct xhci_virt_ep *ep;
 667         struct list_head *entry;
 668         struct xhci_td *cur_td = NULL;
 669         struct xhci_td *last_unlinked_td;
 670
 671         struct xhci_dequeue_state deq_state;
 672
 673         if (unlikely(TRB_TO_SUSPEND_PORT(
 674                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 675                 slot_id = TRB_TO_SLOT_ID(
 676                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 677                 virt_dev = xhci->devs[slot_id];
 678                 if (virt_dev)
 679                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 680                                 event);
 681                 else
 682                         xhci_warn(xhci, "Stop endpoint command "
 683                                 "completion for disabled slot %u\n",
 684                                 slot_id);
 685                 return;
 686         }
 687
 688         memset(&deq_state, 0, sizeof(deq_state));
 689         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 690         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 691         ep = &xhci->devs[slot_id]->eps[ep_index];
 692
 693         if (list_empty(&ep->cancelled_td_list)) {
 694                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 695                 ep->stopped_td = NULL;
 696                 ep->stopped_trb = NULL;
 697                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 698                 return;
 699         }
 700
 701         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 702          * We have the xHCI lock, so nothing can modify this list until we drop
 703          * it.  We're also in the event handler, so we can't get re-interrupted
 704          * if another Stop Endpoint command completes
 705          */
 706         list_for_each(entry, &ep->cancelled_td_list) {
 707                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 708                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 709                                 cur_td->first_trb,
 710                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 711                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 712                 if (!ep_ring) {
 713                         /* This shouldn't happen unless a driver is mucking
 714                          * with the stream ID after submission.  This will
 715                          * leave the TD on the hardware ring, and the hardware
 716                          * will try to execute it, and may access a buffer
 717                          * that has already been freed.  In the best case, the
 718                          * hardware will execute it, and the event handler will
 719                          * ignore the completion event for that TD, since it was
 720                          * removed from the td_list for that endpoint.  In
 721                          * short, don't muck with the stream ID after
 722                          * submission.
 723                          */
 724                         xhci_warn(xhci, "WARN Cancelled URB %p "
 725                                         "has invalid stream ID %u.\n",
 726                                         cur_td->urb,
 727                                         cur_td->urb->stream_id);
 728                         goto remove_finished_td;
 729                 }
 730                 /*
 731                  * If we stopped on the TD we need to cancel, then we have to
 732                  * move the xHC endpoint ring dequeue pointer past this TD.
 733                  */
 734                 if (cur_td == ep->stopped_td)
 735                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 736                                         cur_td->urb->stream_id,
 737                                         cur_td, &deq_state);
 738                 else
 739                         td_to_noop(xhci, ep_ring, cur_td, false);
 740 remove_finished_td:
 741                 /*
 742                  * The event handler won't see a completion for this TD anymore,
 743                  * so remove it from the endpoint ring's TD list.  Keep it in
 744                  * the cancelled TD list for URB completion later.
 745                  */
 746                 list_del_init(&cur_td->td_list);
 747         }
 748         last_unlinked_td = cur_td;
 749         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 750
 751         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 752         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 753                 xhci_queue_new_dequeue_state(xhci,
 754                                 slot_id, ep_index,
 755                                 ep->stopped_td->urb->stream_id,
 756                                 &deq_state);
 757                 xhci_ring_cmd_db(xhci);
 758         } else {
 759                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 760                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 761         }
 762         ep->stopped_td = NULL;
 763         ep->stopped_trb = NULL;
 764
 765         /*
 766          * Drop the lock and complete the URBs in the cancelled TD list.
 767          * New TDs to be cancelled might be added to the end of the list before
 768          * we can complete all the URBs for the TDs we already unlinked.
 769          * So stop when we've completed the URB for the last TD we unlinked.
 770          */
 771         do {
 772                 cur_td = list_entry(ep->cancelled_td_list.next,
 773                                 struct xhci_td, cancelled_td_list);
 774                 list_del_init(&cur_td->cancelled_td_list);
 775
 776                 /* Clean up the cancelled URB */
 777                 /* Doesn't matter what we pass for status, since the core will
 778                  * just overwrite it (because the URB has been unlinked).
 779                  */
 780                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 781
 782                 /* Stop processing the cancelled list if the watchdog timer is
 783                  * running.
 784                  */
 785                 if (xhci->xhc_state & XHCI_STATE_DYING)
 786                         return;
 787         } while (cur_td != last_unlinked_td);
 788
 789         /* Return to the event handler with xhci->lock re-acquired */
 790 }
 791
 792 /* Watchdog timer function for when a stop endpoint command fails to complete.
 793  * In this case, we assume the host controller is broken or dying or dead.  The
 794  * host may still be completing some other events, so we have to be careful to
 795  * let the event ring handler and the URB dequeueing/enqueueing functions know
 796  * through xhci->state.
 797  *
 798  * The timer may also fire if the host takes a very long time to respond to the
 799  * command, and the stop endpoint command completion handler cannot delete the
 800  * timer before the timer function is called.  Another endpoint cancellation may
 801  * sneak in before the timer function can grab the lock, and that may queue
 802  * another stop endpoint command and add the timer back.  So we cannot use a
 803  * simple flag to say whether there is a pending stop endpoint command for a
 804  * particular endpoint.
 805  *
 806  * Instead we use a combination of that flag and a counter for the number of
 807  * pending stop endpoint commands.  If the timer is the tail end of the last
 808  * stop endpoint command, and the endpoint's command is still pending, we assume
 809  * the host is dying.
 810  */
 811 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 812 {
 813         struct xhci_hcd *xhci;
 814         struct xhci_virt_ep *ep;
 815         struct xhci_virt_ep *temp_ep;
 816         struct xhci_ring *ring;
 817         struct xhci_td *cur_td;
 818         int ret, i, j;
 819
 820         ep = (struct xhci_virt_ep *) arg;
 821         xhci = ep->xhci;
 822
 823         spin_lock(&xhci->lock);
 824
 825         ep->stop_cmds_pending--;
 826         if (xhci->xhc_state & XHCI_STATE_DYING) {
 827                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 828                                 "xHCI as DYING, exiting.\n");
 829                 spin_unlock(&xhci->lock);
 830                 return;
 831         }
 832         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 833                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 834                                 "exiting.\n");
 835                 spin_unlock(&xhci->lock);
 836                 return;
 837         }
 838
 839         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 840         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 841         /* Oops, HC is dead or dying or at least not responding to the stop
 842          * endpoint command.
 843          */
 844         xhci->xhc_state |= XHCI_STATE_DYING;
 845         /* Disable interrupts from the host controller and start halting it */
 846         xhci_quiesce(xhci);
 847         spin_unlock(&xhci->lock);
 848
 849         ret = xhci_halt(xhci);
 850
 851         spin_lock(&xhci->lock);
 852         if (ret < 0) {
 853                 /* This is bad; the host is not responding to commands and it's
 854                  * not allowing itself to be halted.  At least interrupts are
 855                  * disabled. If we call usb_hc_died(), it will attempt to
 856                  * disconnect all device drivers under this host.  Those
 857                  * disconnect() methods will wait for all URBs to be unlinked,
 858                  * so we must complete them.
 859                  */
 860                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 861                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 862                 /* We could turn all TDs on the rings to no-ops.  This won't
 863                  * help if the host has cached part of the ring, and is slow if
 864                  * we want to preserve the cycle bit.  Skip it and hope the host
 865                  * doesn't touch the memory.
 866                  */
 867         }
 868         for (i = 0; i < MAX_HC_SLOTS; i++) {
 869                 if (!xhci->devs[i])
 870                         continue;
 871                 for (j = 0; j < 31; j++) {
 872                         temp_ep = &xhci->devs[i]->eps[j];
 873                         ring = temp_ep->ring;
 874                         if (!ring)
 875                                 continue;
 876                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 877                                         "ep index %u\n", i, j);
 878                         while (!list_empty(&ring->td_list)) {
 879                                 cur_td = list_first_entry(&ring->td_list,
 880                                                 struct xhci_td,
 881                                                 td_list);
 882                                 list_del_init(&cur_td->td_list);
 883                                 if (!list_empty(&cur_td->cancelled_td_list))
 884                                         list_del_init(&cur_td->cancelled_td_list);
 885                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 886                                                 -ESHUTDOWN, "killed");
 887                         }
 888                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 889                                 cur_td = list_first_entry(
 890                                                 &temp_ep->cancelled_td_list,
 891                                                 struct xhci_td,
 892                                                 cancelled_td_list);
 893                                 list_del_init(&cur_td->cancelled_td_list);
 894                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 895                                                 -ESHUTDOWN, "killed");
 896                         }
 897                 }
 898         }
 899         spin_unlock(&xhci->lock);
 900         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 901         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 902         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 903 }
 904
 905 /*
 906  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 907  * we need to clear the set deq pending flag in the endpoint ring state, so that
 908  * the TD queueing code can ring the doorbell again.  We also need to ring the
 909  * endpoint doorbell to restart the ring, but only if there aren't more
 910  * cancellations pending.
 911  */
 912 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 913                 struct xhci_event_cmd *event,
 914                 union xhci_trb *trb)
 915 {
 916         unsigned int slot_id;
 917         unsigned int ep_index;
 918         unsigned int stream_id;
 919         struct xhci_ring *ep_ring;
 920         struct xhci_virt_device *dev;
 921         struct xhci_ep_ctx *ep_ctx;
 922         struct xhci_slot_ctx *slot_ctx;
 923
 924         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 925         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 926         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
 927         dev = xhci->devs[slot_id];
 928
 929         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 930         if (!ep_ring) {
 931                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 932                                 "freed stream ID %u\n",
 933                                 stream_id);
 934                 /* XXX: Harmless??? */
 935                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 936                 return;
 937         }
 938
 939         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 940         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 941
 942         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
 943                 unsigned int ep_state;
 944                 unsigned int slot_state;
 945
 946                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
 947                 case COMP_TRB_ERR:
 948                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 949                                         "of stream ID configuration\n");
 950                         break;
 951                 case COMP_CTX_STATE:
 952                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 953                                         "to incorrect slot or ep state.\n");
 954                         ep_state = le32_to_cpu(ep_ctx->ep_info);
 955                         ep_state &= EP_STATE_MASK;
 956                         slot_state = le32_to_cpu(slot_ctx->dev_state);
 957                         slot_state = GET_SLOT_STATE(slot_state);
 958                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 959                                         slot_state, ep_state);
 960                         break;
 961                 case COMP_EBADSLT:
 962                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 963                                         "slot %u was not enabled.\n", slot_id);
 964                         break;
 965                 default:
 966                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 967                                         "completion code of %u.\n",
 968                                   GET_COMP_CODE(le32_to_cpu(event->status)));
 969                         break;
 970                 }
 971                 /* OK what do we do now?  The endpoint state is hosed, and we
 972                  * should never get to this point if the synchronization between
 973                  * queueing, and endpoint state are correct.  This might happen
 974                  * if the device gets disconnected after we've finished
 975                  * cancelling URBs, which might not be an error...
 976                  */
 977         } else {
 978                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 979                          le64_to_cpu(ep_ctx->deq));
 980                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 981                                          dev->eps[ep_index].queued_deq_ptr) ==
 982                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
 983                         /* Update the ring's dequeue segment and dequeue pointer
 984                          * to reflect the new position.
 985                          */
 986                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
 987                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
 988                 } else {
 989                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 990                                         "Ptr command & xHCI internal state.\n");
 991                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 992                                         dev->eps[ep_index].queued_deq_seg,
 993                                         dev->eps[ep_index].queued_deq_ptr);
 994                 }
 995         }
 996
 997         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 998         dev->eps[ep_index].queued_deq_seg = NULL;
 999         dev->eps[ep_index].queued_deq_ptr = NULL;
1000         /* Restart any rings with pending URBs */
1001         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1002 }
1003
1004 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1005                 struct xhci_event_cmd *event,
1006                 union xhci_trb *trb)
1007 {
1008         int slot_id;
1009         unsigned int ep_index;
1010
1011         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1012         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1013         /* This command will only fail if the endpoint wasn't halted,
1014          * but we don't care.
1015          */
1016         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1017                  GET_COMP_CODE(le32_to_cpu(event->status)));
1018
1019         /* HW with the reset endpoint quirk needs to have a configure endpoint
1020          * command complete before the endpoint can be used.  Queue that here
1021          * because the HW can't handle two commands being queued in a row.
1022          */
1023         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1024                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1025                 xhci_queue_configure_endpoint(xhci,
1026                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1027                                 false);
1028                 xhci_ring_cmd_db(xhci);
1029         } else {
1030                 /* Clear our internal halted state and restart the ring(s) */
1031                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1032                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1033         }
1034 }
1035
1036 /* Check to see if a command in the device's command queue matches this one.
1037  * Signal the completion or free the command, and return 1.  Return 0 if the
1038  * completed command isn't at the head of the command list.
1039  */
1040 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1041                 struct xhci_virt_device *virt_dev,
1042                 struct xhci_event_cmd *event)
1043 {
1044         struct xhci_command *command;
1045
1046         if (list_empty(&virt_dev->cmd_list))
1047                 return 0;
1048
1049         command = list_entry(virt_dev->cmd_list.next,
1050                         struct xhci_command, cmd_list);
1051         if (xhci->cmd_ring->dequeue != command->command_trb)
1052                 return 0;
1053
1054         command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1055         list_del(&command->cmd_list);
1056         if (command->completion)
1057                 complete(command->completion);
1058         else
1059                 xhci_free_command(xhci, command);
1060         return 1;
1061 }
1062
1063 static void handle_cmd_completion(struct xhci_hcd *xhci,
1064                 struct xhci_event_cmd *event)
1065 {
1066         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1067         u64 cmd_dma;
1068         dma_addr_t cmd_dequeue_dma;
1069         struct xhci_input_control_ctx *ctrl_ctx;
1070         struct xhci_virt_device *virt_dev;
1071         unsigned int ep_index;
1072         struct xhci_ring *ep_ring;
1073         unsigned int ep_state;
1074
1075         cmd_dma = le64_to_cpu(event->cmd_trb);
1076         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1077                         xhci->cmd_ring->dequeue);
1078         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1079         if (cmd_dequeue_dma == 0) {
1080                 xhci->error_bitmask |= 1 << 4;
1081                 return;
1082         }
1083         /* Does the DMA address match our internal dequeue pointer address? */
1084         if (cmd_dma != (u64) cmd_dequeue_dma) {
1085                 xhci->error_bitmask |= 1 << 5;
1086                 return;
1087         }
1088         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1089                 & TRB_TYPE_BITMASK) {
1090         case TRB_TYPE(TRB_ENABLE_SLOT):
1091                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1092                         xhci->slot_id = slot_id;
1093                 else
1094                         xhci->slot_id = 0;
1095                 complete(&xhci->addr_dev);
1096                 break;
1097         case TRB_TYPE(TRB_DISABLE_SLOT):
1098                 if (xhci->devs[slot_id]) {
1099                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1100                                 /* Delete default control endpoint resources */
1101                                 xhci_free_device_endpoint_resources(xhci,
1102                                                 xhci->devs[slot_id], true);
1103                         xhci_free_virt_device(xhci, slot_id);
1104                 }
1105                 break;
1106         case TRB_TYPE(TRB_CONFIG_EP):
1107                 virt_dev = xhci->devs[slot_id];
1108                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1109                         break;
1110                 /*
1111                  * Configure endpoint commands can come from the USB core
1112                  * configuration or alt setting changes, or because the HW
1113                  * needed an extra configure endpoint command after a reset
1114                  * endpoint command or streams were being configured.
1115                  * If the command was for a halted endpoint, the xHCI driver
1116                  * is not waiting on the configure endpoint command.
1117                  */
1118                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1119                                 virt_dev->in_ctx);
1120                 /* Input ctx add_flags are the endpoint index plus one */
1121                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1122                 /* A usb_set_interface() call directly after clearing a halted
1123                  * condition may race on this quirky hardware.  Not worth
1124                  * worrying about, since this is prototype hardware.  Not sure
1125                  * if this will work for streams, but streams support was
1126                  * untested on this prototype.
1127                  */
1128                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1129                                 ep_index != (unsigned int) -1 &&
1130                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1131                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1132                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1133                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1134                         if (!(ep_state & EP_HALTED))
1135                                 goto bandwidth_change;
1136                         xhci_dbg(xhci, "Completed config ep cmd - "
1137                                         "last ep index = %d, state = %d\n",
1138                                         ep_index, ep_state);
1139                         /* Clear internal halted state and restart ring(s) */
1140                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1141                                 ~EP_HALTED;
1142                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1143                         break;
1144                 }
1145 bandwidth_change:
1146                 xhci_dbg(xhci, "Completed config ep cmd\n");
1147                 xhci->devs[slot_id]->cmd_status =
1148                         GET_COMP_CODE(le32_to_cpu(event->status));
1149                 complete(&xhci->devs[slot_id]->cmd_completion);
1150                 break;
1151         case TRB_TYPE(TRB_EVAL_CONTEXT):
1152                 virt_dev = xhci->devs[slot_id];
1153                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1154                         break;
1155                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1156                 complete(&xhci->devs[slot_id]->cmd_completion);
1157                 break;
1158         case TRB_TYPE(TRB_ADDR_DEV):
1159                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1160                 complete(&xhci->addr_dev);
1161                 break;
1162         case TRB_TYPE(TRB_STOP_RING):
1163                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1164                 break;
1165         case TRB_TYPE(TRB_SET_DEQ):
1166                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1167                 break;
1168         case TRB_TYPE(TRB_CMD_NOOP):
1169                 break;
1170         case TRB_TYPE(TRB_RESET_EP):
1171                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1172                 break;
1173         case TRB_TYPE(TRB_RESET_DEV):
1174                 xhci_dbg(xhci, "Completed reset device command.\n");
1175                 slot_id = TRB_TO_SLOT_ID(
1176                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1177                 virt_dev = xhci->devs[slot_id];
1178                 if (virt_dev)
1179                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1180                 else
1181                         xhci_warn(xhci, "Reset device command completion "
1182                                         "for disabled slot %u\n", slot_id);
1183                 break;
1184         case TRB_TYPE(TRB_NEC_GET_FW):
1185                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1186                         xhci->error_bitmask |= 1 << 6;
1187                         break;
1188                 }
1189                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1190                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1191                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1192                 break;
1193         default:
1194                 /* Skip over unknown commands on the event ring */
1195                 xhci->error_bitmask |= 1 << 6;
1196                 break;
1197         }
1198         inc_deq(xhci, xhci->cmd_ring, false);
1199 }
1200
1201 static void handle_vendor_event(struct xhci_hcd *xhci,
1202                 union xhci_trb *event)
1203 {
1204         u32 trb_type;
1205
1206         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1207         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1208         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1209                 handle_cmd_completion(xhci, &event->event_cmd);
1210 }
1211
1212 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1213  * port registers -- USB 3.0 and USB 2.0).
1214  *
1215  * Returns a zero-based port number, which is suitable for indexing into each of
1216  * the split roothubs' port arrays and bus state arrays.
1217  */
1218 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1219                 struct xhci_hcd *xhci, u32 port_id)
1220 {
1221         unsigned int i;
1222         unsigned int num_similar_speed_ports = 0;
1223
1224         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1225          * and usb2_ports are 0-based indexes.  Count the number of similar
1226          * speed ports, up to 1 port before this port.
1227          */
1228         for (i = 0; i < (port_id - 1); i++) {
1229                 u8 port_speed = xhci->port_array[i];
1230
1231                 /*
1232                  * Skip ports that don't have known speeds, or have duplicate
1233                  * Extended Capabilities port speed entries.
1234                  */
1235                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1236                         continue;
1237
1238                 /*
1239                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1240                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1241                  * matches the device speed, it's a similar speed port.
1242                  */
1243                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1244                         num_similar_speed_ports++;
1245         }
1246         return num_similar_speed_ports;
1247 }
1248
1249 static void handle_port_status(struct xhci_hcd *xhci,
1250                 union xhci_trb *event)
1251 {
1252         struct usb_hcd *hcd;
1253         u32 port_id;
1254         u32 temp, temp1;
1255         int max_ports;
1256         int slot_id;
1257         unsigned int faked_port_index;
1258         u8 major_revision;
1259         struct xhci_bus_state *bus_state;
1260         __le32 __iomem **port_array;
1261         bool bogus_port_status = false;
1262
1263         /* Port status change events always have a successful completion code */
1264         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1265                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1266                 xhci->error_bitmask |= 1 << 8;
1267         }
1268         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1269         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1270
1271         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1272         if ((port_id <= 0) || (port_id > max_ports)) {
1273                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1274                 bogus_port_status = true;
1275                 goto cleanup;
1276         }
1277
1278         /* Figure out which usb_hcd this port is attached to:
1279          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1280          */
1281         major_revision = xhci->port_array[port_id - 1];
1282         if (major_revision == 0) {
1283                 xhci_warn(xhci, "Event for port %u not in "
1284                                 "Extended Capabilities, ignoring.\n",
1285                                 port_id);
1286                 bogus_port_status = true;
1287                 goto cleanup;
1288         }
1289         if (major_revision == DUPLICATE_ENTRY) {
1290                 xhci_warn(xhci, "Event for port %u duplicated in"
1291                                 "Extended Capabilities, ignoring.\n",
1292                                 port_id);
1293                 bogus_port_status = true;
1294                 goto cleanup;
1295         }
1296
1297         /*
1298          * Hardware port IDs reported by a Port Status Change Event include USB
1299          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1300          * resume event, but we first need to translate the hardware port ID
1301          * into the index into the ports on the correct split roothub, and the
1302          * correct bus_state structure.
1303          */
1304         /* Find the right roothub. */
1305         hcd = xhci_to_hcd(xhci);
1306         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1307                 hcd = xhci->shared_hcd;
1308         bus_state = &xhci->bus_state[hcd_index(hcd)];
1309         if (hcd->speed == HCD_USB3)
1310                 port_array = xhci->usb3_ports;
1311         else
1312                 port_array = xhci->usb2_ports;
1313         /* Find the faked port hub number */
1314         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1315                         port_id);
1316
1317         temp = xhci_readl(xhci, port_array[faked_port_index]);
1318         if (hcd->state == HC_STATE_SUSPENDED) {
1319                 xhci_dbg(xhci, "resume root hub\n");
1320                 usb_hcd_resume_root_hub(hcd);
1321         }
1322
1323         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1324                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1325
1326                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1327                 if (!(temp1 & CMD_RUN)) {
1328                         xhci_warn(xhci, "xHC is not running.\n");
1329                         goto cleanup;
1330                 }
1331
1332                 if (DEV_SUPERSPEED(temp)) {
1333                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1334                         xhci_set_link_state(xhci, port_array, faked_port_index,
1335                                                 XDEV_U0);
1336                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1337                                         faked_port_index);
1338                         if (!slot_id) {
1339                                 xhci_dbg(xhci, "slot_id is zero\n");
1340                                 goto cleanup;
1341                         }
1342                         xhci_ring_device(xhci, slot_id);
1343                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1344                         /* Clear PORT_PLC */
1345                         xhci_test_and_clear_bit(xhci, port_array,
1346                                                 faked_port_index, PORT_PLC);
1347                 } else {
1348                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1349                         bus_state->resume_done[faked_port_index] = jiffies +
1350                                 msecs_to_jiffies(20);
1351                         mod_timer(&hcd->rh_timer,
1352                                   bus_state->resume_done[faked_port_index]);
1353                         /* Do the rest in GetPortStatus */
1354                 }
1355         }
1356
1357         if (hcd->speed != HCD_USB3)
1358                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1359                                         PORT_PLC);
1360
1361 cleanup:
1362         /* Update event ring dequeue pointer before dropping the lock */
1363         inc_deq(xhci, xhci->event_ring, true);
1364
1365         /* Don't make the USB core poll the roothub if we got a bad port status
1366          * change event.  Besides, at that point we can't tell which roothub
1367          * (USB 2.0 or USB 3.0) to kick.
1368          */
1369         if (bogus_port_status)
1370                 return;
1371
1372         spin_unlock(&xhci->lock);
1373         /* Pass this up to the core */
1374         usb_hcd_poll_rh_status(hcd);
1375         spin_lock(&xhci->lock);
1376 }
1377
1378 /*
1379  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1380  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1381  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1382  * returns 0.
1383  */
1384 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1385                 union xhci_trb  *start_trb,
1386                 union xhci_trb  *end_trb,
1387                 dma_addr_t      suspect_dma)
1388 {
1389         dma_addr_t start_dma;
1390         dma_addr_t end_seg_dma;
1391         dma_addr_t end_trb_dma;
1392         struct xhci_segment *cur_seg;
1393
1394         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1395         cur_seg = start_seg;
1396
1397         do {
1398                 if (start_dma == 0)
1399                         return NULL;
1400                 /* We may get an event for a Link TRB in the middle of a TD */
1401                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1402                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1403                 /* If the end TRB isn't in this segment, this is set to 0 */
1404                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1405
1406                 if (end_trb_dma > 0) {
1407                         /* The end TRB is in this segment, so suspect should be here */
1408                         if (start_dma <= end_trb_dma) {
1409                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1410                                         return cur_seg;
1411                         } else {
1412                                 /* Case for one segment with
1413                                  * a TD wrapped around to the top
1414                                  */
1415                                 if ((suspect_dma >= start_dma &&
1416                                                         suspect_dma <= end_seg_dma) ||
1417                                                 (suspect_dma >= cur_seg->dma &&
1418                                                  suspect_dma <= end_trb_dma))
1419                                         return cur_seg;
1420                         }
1421                         return NULL;
1422                 } else {
1423                         /* Might still be somewhere in this segment */
1424                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1425                                 return cur_seg;
1426                 }
1427                 cur_seg = cur_seg->next;
1428                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1429         } while (cur_seg != start_seg);
1430
1431         return NULL;
1432 }
1433
1434 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1435                 unsigned int slot_id, unsigned int ep_index,
1436                 unsigned int stream_id,
1437                 struct xhci_td *td, union xhci_trb *event_trb)
1438 {
1439         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1440         ep->ep_state |= EP_HALTED;
1441         ep->stopped_td = td;
1442         ep->stopped_trb = event_trb;
1443         ep->stopped_stream = stream_id;
1444
1445         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1446         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1447
1448         ep->stopped_td = NULL;
1449         ep->stopped_trb = NULL;
1450         ep->stopped_stream = 0;
1451
1452         xhci_ring_cmd_db(xhci);
1453 }
1454
1455 /* Check if an error has halted the endpoint ring.  The class driver will
1456  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1457  * However, a babble and other errors also halt the endpoint ring, and the class
1458  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1459  * Ring Dequeue Pointer command manually.
1460  */
1461 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1462                 struct xhci_ep_ctx *ep_ctx,
1463                 unsigned int trb_comp_code)
1464 {
1465         /* TRB completion codes that may require a manual halt cleanup */
1466         if (trb_comp_code == COMP_TX_ERR ||
1467                         trb_comp_code == COMP_BABBLE ||
1468                         trb_comp_code == COMP_SPLIT_ERR)
1469                 /* The 0.96 spec says a babbling control endpoint
1470                  * is not halted. The 0.96 spec says it is.  Some HW
1471                  * claims to be 0.95 compliant, but it halts the control
1472                  * endpoint anyway.  Check if a babble halted the
1473                  * endpoint.
1474                  */
1475                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1476                     cpu_to_le32(EP_STATE_HALTED))
1477                         return 1;
1478
1479         return 0;
1480 }
1481
1482 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1483 {
1484         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1485                 /* Vendor defined "informational" completion code,
1486                  * treat as not-an-error.
1487                  */
1488                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1489                                 trb_comp_code);
1490                 xhci_dbg(xhci, "Treating code as success.\n");
1491                 return 1;
1492         }
1493         return 0;
1494 }
1495
1496 /*
1497  * Finish the td processing, remove the td from td list;
1498  * Return 1 if the urb can be given back.
1499  */
1500 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1501         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1502         struct xhci_virt_ep *ep, int *status, bool skip)
1503 {
1504         struct xhci_virt_device *xdev;
1505         struct xhci_ring *ep_ring;
1506         unsigned int slot_id;
1507         int ep_index;
1508         struct urb *urb = NULL;
1509         struct xhci_ep_ctx *ep_ctx;
1510         int ret = 0;
1511         struct urb_priv *urb_priv;
1512         u32 trb_comp_code;
1513
1514         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1515         xdev = xhci->devs[slot_id];
1516         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1517         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1518         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1519         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1520
1521         if (skip)
1522                 goto td_cleanup;
1523
1524         if (trb_comp_code == COMP_STOP_INVAL ||
1525                         trb_comp_code == COMP_STOP) {
1526                 /* The Endpoint Stop Command completion will take care of any
1527                  * stopped TDs.  A stopped TD may be restarted, so don't update
1528                  * the ring dequeue pointer or take this TD off any lists yet.
1529                  */
1530                 ep->stopped_td = td;
1531                 ep->stopped_trb = event_trb;
1532                 return 0;
1533         } else {
1534                 if (trb_comp_code == COMP_STALL) {
1535                         /* The transfer is completed from the driver's
1536                          * perspective, but we need to issue a set dequeue
1537                          * command for this stalled endpoint to move the dequeue
1538                          * pointer past the TD.  We can't do that here because
1539                          * the halt condition must be cleared first.  Let the
1540                          * USB class driver clear the stall later.
1541                          */
1542                         ep->stopped_td = td;
1543                         ep->stopped_trb = event_trb;
1544                         ep->stopped_stream = ep_ring->stream_id;
1545                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1546                                         ep_ctx, trb_comp_code)) {
1547                         /* Other types of errors halt the endpoint, but the
1548                          * class driver doesn't call usb_reset_endpoint() unless
1549                          * the error is -EPIPE.  Clear the halted status in the
1550                          * xHCI hardware manually.
1551                          */
1552                         xhci_cleanup_halted_endpoint(xhci,
1553                                         slot_id, ep_index, ep_ring->stream_id,
1554                                         td, event_trb);
1555                 } else {
1556                         /* Update ring dequeue pointer */
1557                         while (ep_ring->dequeue != td->last_trb)
1558                                 inc_deq(xhci, ep_ring, false);
1559                         inc_deq(xhci, ep_ring, false);
1560                 }
1561
1562 td_cleanup:
1563                 /* Clean up the endpoint's TD list */
1564                 urb = td->urb;
1565                 urb_priv = urb->hcpriv;
1566
1567                 /* Do one last check of the actual transfer length.
1568                  * If the host controller said we transferred more data than
1569                  * the buffer length, urb->actual_length will be a very big
1570                  * number (since it's unsigned).  Play it safe and say we didn't
1571                  * transfer anything.
1572                  */
1573                 if (urb->actual_length > urb->transfer_buffer_length) {
1574                         xhci_warn(xhci, "URB transfer length is wrong, "
1575                                         "xHC issue? req. len = %u, "
1576                                         "act. len = %u\n",
1577                                         urb->transfer_buffer_length,
1578                                         urb->actual_length);
1579                         urb->actual_length = 0;
1580                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1581                                 *status = -EREMOTEIO;
1582                         else
1583                                 *status = 0;
1584                 }
1585                 list_del_init(&td->td_list);
1586                 /* Was this TD slated to be cancelled but completed anyway? */
1587                 if (!list_empty(&td->cancelled_td_list))
1588                         list_del_init(&td->cancelled_td_list);
1589
1590                 urb_priv->td_cnt++;
1591                 /* Giveback the urb when all the tds are completed */
1592                 if (urb_priv->td_cnt == urb_priv->length) {
1593                         ret = 1;
1594                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1595                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1596                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1597                                         == 0) {
1598                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1599                                                 usb_amd_quirk_pll_enable();
1600                                 }
1601                         }
1602                 }
1603         }
1604
1605         return ret;
1606 }
1607
1608 /*
1609  * Process control tds, update urb status and actual_length.
1610  */
1611 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1612         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1613         struct xhci_virt_ep *ep, int *status)
1614 {
1615         struct xhci_virt_device *xdev;
1616         struct xhci_ring *ep_ring;
1617         unsigned int slot_id;
1618         int ep_index;
1619         struct xhci_ep_ctx *ep_ctx;
1620         u32 trb_comp_code;
1621
1622         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1623         xdev = xhci->devs[slot_id];
1624         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1625         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1626         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1627         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1628
1629         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1630         switch (trb_comp_code) {
1631         case COMP_SUCCESS:
1632                 if (event_trb == ep_ring->dequeue) {
1633                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1634                                         "without IOC set??\n");
1635                         *status = -ESHUTDOWN;
1636                 } else if (event_trb != td->last_trb) {
1637                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1638                                         "without IOC set??\n");
1639                         *status = -ESHUTDOWN;
1640                 } else {
1641                         *status = 0;
1642                 }
1643                 break;
1644         case COMP_SHORT_TX:
1645                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1646                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1647                         *status = -EREMOTEIO;
1648                 else
1649                         *status = 0;
1650                 break;
1651         case COMP_STOP_INVAL:
1652         case COMP_STOP:
1653                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1654         default:
1655                 if (!xhci_requires_manual_halt_cleanup(xhci,
1656                                         ep_ctx, trb_comp_code))
1657                         break;
1658                 xhci_dbg(xhci, "TRB error code %u, "
1659                                 "halted endpoint index = %u\n",
1660                                 trb_comp_code, ep_index);
1661                 /* else fall through */
1662         case COMP_STALL:
1663                 /* Did we transfer part of the data (middle) phase? */
1664                 if (event_trb != ep_ring->dequeue &&
1665                                 event_trb != td->last_trb)
1666                         td->urb->actual_length =
1667                                 td->urb->transfer_buffer_length
1668                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
1669                 else
1670                         td->urb->actual_length = 0;
1671
1672                 xhci_cleanup_halted_endpoint(xhci,
1673                         slot_id, ep_index, 0, td, event_trb);
1674                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1675         }
1676         /*
1677          * Did we transfer any data, despite the errors that might have
1678          * happened?  I.e. did we get past the setup stage?
1679          */
1680         if (event_trb != ep_ring->dequeue) {
1681                 /* The event was for the status stage */
1682                 if (event_trb == td->last_trb) {
1683                         if (td->urb->actual_length != 0) {
1684                                 /* Don't overwrite a previously set error code
1685                                  */
1686                                 if ((*status == -EINPROGRESS || *status == 0) &&
1687                                                 (td->urb->transfer_flags
1688                                                  & URB_SHORT_NOT_OK))
1689                                         /* Did we already see a short data
1690                                          * stage? */
1691                                         *status = -EREMOTEIO;
1692                         } else {
1693                                 td->urb->actual_length =
1694                                         td->urb->transfer_buffer_length;
1695                         }
1696                 } else {
1697                 /* Maybe the event was for the data stage? */
1698                         td->urb->actual_length =
1699                                 td->urb->transfer_buffer_length -
1700                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1701                         xhci_dbg(xhci, "Waiting for status "
1702                                         "stage event\n");
1703                         return 0;
1704                 }
1705         }
1706
1707         return finish_td(xhci, td, event_trb, event, ep, status, false);
1708 }
1709
1710 /*
1711  * Process isochronous tds, update urb packet status and actual_length.
1712  */
1713 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1714         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1715         struct xhci_virt_ep *ep, int *status)
1716 {
1717         struct xhci_ring *ep_ring;
1718         struct urb_priv *urb_priv;
1719         int idx;
1720         int len = 0;
1721         union xhci_trb *cur_trb;
1722         struct xhci_segment *cur_seg;
1723         struct usb_iso_packet_descriptor *frame;
1724         u32 trb_comp_code;
1725         bool skip_td = false;
1726
1727         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1728         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1729         urb_priv = td->urb->hcpriv;
1730         idx = urb_priv->td_cnt;
1731         frame = &td->urb->iso_frame_desc[idx];
1732
1733         /* handle completion code */
1734         switch (trb_comp_code) {
1735         case COMP_SUCCESS:
1736                 frame->status = 0;
1737                 break;
1738         case COMP_SHORT_TX:
1739                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1740                                 -EREMOTEIO : 0;
1741                 break;
1742         case COMP_BW_OVER:
1743                 frame->status = -ECOMM;
1744                 skip_td = true;
1745                 break;
1746         case COMP_BUFF_OVER:
1747         case COMP_BABBLE:
1748                 frame->status = -EOVERFLOW;
1749                 skip_td = true;
1750                 break;
1751         case COMP_DEV_ERR:
1752         case COMP_STALL:
1753                 frame->status = -EPROTO;
1754                 skip_td = true;
1755                 break;
1756         case COMP_STOP:
1757         case COMP_STOP_INVAL:
1758                 break;
1759         default:
1760                 frame->status = -1;
1761                 break;
1762         }
1763
1764         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1765                 frame->actual_length = frame->length;
1766                 td->urb->actual_length += frame->length;
1767         } else {
1768                 for (cur_trb = ep_ring->dequeue,
1769                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1770                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1771                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1772                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1773                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1774                 }
1775                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1776                         TRB_LEN(le32_to_cpu(event->transfer_len));
1777
1778                 if (trb_comp_code != COMP_STOP_INVAL) {
1779                         frame->actual_length = len;
1780                         td->urb->actual_length += len;
1781                 }
1782         }
1783
1784         return finish_td(xhci, td, event_trb, event, ep, status, false);
1785 }
1786
1787 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1788                         struct xhci_transfer_event *event,
1789                         struct xhci_virt_ep *ep, int *status)
1790 {
1791         struct xhci_ring *ep_ring;
1792         struct urb_priv *urb_priv;
1793         struct usb_iso_packet_descriptor *frame;
1794         int idx;
1795
1796         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1797         urb_priv = td->urb->hcpriv;
1798         idx = urb_priv->td_cnt;
1799         frame = &td->urb->iso_frame_desc[idx];
1800
1801         /* The transfer is partly done. */
1802         frame->status = -EXDEV;
1803
1804         /* calc actual length */
1805         frame->actual_length = 0;
1806
1807         /* Update ring dequeue pointer */
1808         while (ep_ring->dequeue != td->last_trb)
1809                 inc_deq(xhci, ep_ring, false);
1810         inc_deq(xhci, ep_ring, false);
1811
1812         return finish_td(xhci, td, NULL, event, ep, status, true);
1813 }
1814
1815 /*
1816  * Process bulk and interrupt tds, update urb status and actual_length.
1817  */
1818 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1819         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1820         struct xhci_virt_ep *ep, int *status)
1821 {
1822         struct xhci_ring *ep_ring;
1823         union xhci_trb *cur_trb;
1824         struct xhci_segment *cur_seg;
1825         u32 trb_comp_code;
1826
1827         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1828         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1829
1830         switch (trb_comp_code) {
1831         case COMP_SUCCESS:
1832                 /* Double check that the HW transferred everything. */
1833                 if (event_trb != td->last_trb) {
1834                         xhci_warn(xhci, "WARN Successful completion "
1835                                         "on short TX\n");
1836                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1837                                 *status = -EREMOTEIO;
1838                         else
1839                                 *status = 0;
1840                 } else {
1841                         *status = 0;
1842                 }
1843                 break;
1844         case COMP_SHORT_TX:
1845                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1846                         *status = -EREMOTEIO;
1847                 else
1848                         *status = 0;
1849                 break;
1850         default:
1851                 /* Others already handled above */
1852                 break;
1853         }
1854         if (trb_comp_code == COMP_SHORT_TX)
1855                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1856                                 "%d bytes untransferred\n",
1857                                 td->urb->ep->desc.bEndpointAddress,
1858                                 td->urb->transfer_buffer_length,
1859                                 TRB_LEN(le32_to_cpu(event->transfer_len)));
1860         /* Fast path - was this the last TRB in the TD for this URB? */
1861         if (event_trb == td->last_trb) {
1862                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1863                         td->urb->actual_length =
1864                                 td->urb->transfer_buffer_length -
1865                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1866                         if (td->urb->transfer_buffer_length <
1867                                         td->urb->actual_length) {
1868                                 xhci_warn(xhci, "HC gave bad length "
1869                                                 "of %d bytes left\n",
1870                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
1871                                 td->urb->actual_length = 0;
1872                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1873                                         *status = -EREMOTEIO;
1874                                 else
1875                                         *status = 0;
1876                         }
1877                         /* Don't overwrite a previously set error code */
1878                         if (*status == -EINPROGRESS) {
1879                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1880                                         *status = -EREMOTEIO;
1881                                 else
1882                                         *status = 0;
1883                         }
1884                 } else {
1885                         td->urb->actual_length =
1886                                 td->urb->transfer_buffer_length;
1887                         /* Ignore a short packet completion if the
1888                          * untransferred length was zero.
1889                          */
1890                         if (*status == -EREMOTEIO)
1891                                 *status = 0;
1892                 }
1893         } else {
1894                 /* Slow path - walk the list, starting from the dequeue
1895                  * pointer, to get the actual length transferred.
1896                  */
1897                 td->urb->actual_length = 0;
1898                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1899                                 cur_trb != event_trb;
1900                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1901                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1902                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1903                                 td->urb->actual_length +=
1904                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1905                 }
1906                 /* If the ring didn't stop on a Link or No-op TRB, add
1907                  * in the actual bytes transferred from the Normal TRB
1908                  */
1909                 if (trb_comp_code != COMP_STOP_INVAL)
1910                         td->urb->actual_length +=
1911                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1912                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1913         }
1914
1915         return finish_td(xhci, td, event_trb, event, ep, status, false);
1916 }
1917
1918 /*
1919  * If this function returns an error condition, it means it got a Transfer
1920  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1921  * At this point, the host controller is probably hosed and should be reset.
1922  */
1923 static int handle_tx_event(struct xhci_hcd *xhci,
1924                 struct xhci_transfer_event *event)
1925 {
1926         struct xhci_virt_device *xdev;
1927         struct xhci_virt_ep *ep;
1928         struct xhci_ring *ep_ring;
1929         unsigned int slot_id;
1930         int ep_index;
1931         struct xhci_td *td = NULL;
1932         dma_addr_t event_dma;
1933         struct xhci_segment *event_seg;
1934         union xhci_trb *event_trb;
1935         struct urb *urb = NULL;
1936         int status = -EINPROGRESS;
1937         struct urb_priv *urb_priv;
1938         struct xhci_ep_ctx *ep_ctx;
1939         struct list_head *tmp;
1940         u32 trb_comp_code;
1941         int ret = 0;
1942         int td_num = 0;
1943
1944         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1945         xdev = xhci->devs[slot_id];
1946         if (!xdev) {
1947                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1948                 return -ENODEV;
1949         }
1950
1951         /* Endpoint ID is 1 based, our index is zero based */
1952         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1953         ep = &xdev->eps[ep_index];
1954         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1955         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1956         if (!ep_ring ||
1957             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1958             EP_STATE_DISABLED) {
1959                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1960                                 "or incorrect stream ring\n");
1961                 return -ENODEV;
1962         }
1963
1964         /* Count current td numbers if ep->skip is set */
1965         if (ep->skip) {
1966                 list_for_each(tmp, &ep_ring->td_list)
1967                         td_num++;
1968         }
1969
1970         event_dma = le64_to_cpu(event->buffer);
1971         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1972         /* Look for common error cases */
1973         switch (trb_comp_code) {
1974         /* Skip codes that require special handling depending on
1975          * transfer type
1976          */
1977         case COMP_SUCCESS:
1978         case COMP_SHORT_TX:
1979                 break;
1980         case COMP_STOP:
1981                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1982                 break;
1983         case COMP_STOP_INVAL:
1984                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1985                 break;
1986         case COMP_STALL:
1987                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1988                 ep->ep_state |= EP_HALTED;
1989                 status = -EPIPE;
1990                 break;
1991         case COMP_TRB_ERR:
1992                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1993                 status = -EILSEQ;
1994                 break;
1995         case COMP_SPLIT_ERR:
1996         case COMP_TX_ERR:
1997                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1998                 status = -EPROTO;
1999                 break;
2000         case COMP_BABBLE:
2001                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2002                 status = -EOVERFLOW;
2003                 break;
2004         case COMP_DB_ERR:
2005                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2006                 status = -ENOSR;
2007                 break;
2008         case COMP_BW_OVER:
2009                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2010                 break;
2011         case COMP_BUFF_OVER:
2012                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2013                 break;
2014         case COMP_UNDERRUN:
2015                 /*
2016                  * When the Isoch ring is empty, the xHC will generate
2017                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2018                  * Underrun Event for OUT Isoch endpoint.
2019                  */
2020                 xhci_dbg(xhci, "underrun event on endpoint\n");
2021                 if (!list_empty(&ep_ring->td_list))
2022                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2023                                         "still with TDs queued?\n",
2024                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2025                                  ep_index);
2026                 goto cleanup;
2027         case COMP_OVERRUN:
2028                 xhci_dbg(xhci, "overrun event on endpoint\n");
2029                 if (!list_empty(&ep_ring->td_list))
2030                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2031                                         "still with TDs queued?\n",
2032                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2033                                  ep_index);
2034                 goto cleanup;
2035         case COMP_DEV_ERR:
2036                 xhci_warn(xhci, "WARN: detect an incompatible device");
2037                 status = -EPROTO;
2038                 break;
2039         case COMP_MISSED_INT:
2040                 /*
2041                  * When encounter missed service error, one or more isoc tds
2042                  * may be missed by xHC.
2043                  * Set skip flag of the ep_ring; Complete the missed tds as
2044                  * short transfer when process the ep_ring next time.
2045                  */
2046                 ep->skip = true;
2047                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2048                 goto cleanup;
2049         default:
2050                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2051                         status = 0;
2052                         break;
2053                 }
2054                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2055                                 "busted\n");
2056                 goto cleanup;
2057         }
2058
2059         do {
2060                 /* This TRB should be in the TD at the head of this ring's
2061                  * TD list.
2062                  */
2063                 if (list_empty(&ep_ring->td_list)) {
2064                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2065                                         "with no TDs queued?\n",
2066                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2067                                   ep_index);
2068                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2069                                  (le32_to_cpu(event->flags) &
2070                                   TRB_TYPE_BITMASK)>>10);
2071                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2072                         if (ep->skip) {
2073                                 ep->skip = false;
2074                                 xhci_dbg(xhci, "td_list is empty while skip "
2075                                                 "flag set. Clear skip flag.\n");
2076                         }
2077                         ret = 0;
2078                         goto cleanup;
2079                 }
2080
2081                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2082                 if (ep->skip && td_num == 0) {
2083                         ep->skip = false;
2084                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2085                                                 "Clear skip flag.\n");
2086                         ret = 0;
2087                         goto cleanup;
2088                 }
2089
2090                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2091                 if (ep->skip)
2092                         td_num--;
2093
2094                 /* Is this a TRB in the currently executing TD? */
2095                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2096                                 td->last_trb, event_dma);
2097
2098                 /*
2099                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2100                  * is not in the current TD pointed by ep_ring->dequeue because
2101                  * that the hardware dequeue pointer still at the previous TRB
2102                  * of the current TD. The previous TRB maybe a Link TD or the
2103                  * last TRB of the previous TD. The command completion handle
2104                  * will take care the rest.
2105                  */
2106                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2107                         ret = 0;
2108                         goto cleanup;
2109                 }
2110
2111                 if (!event_seg) {
2112                         if (!ep->skip ||
2113                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2114                                 /* Some host controllers give a spurious
2115                                  * successful event after a short transfer.
2116                                  * Ignore it.
2117                                  */
2118                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2119                                                 ep_ring->last_td_was_short) {
2120                                         ep_ring->last_td_was_short = false;
2121                                         ret = 0;
2122                                         goto cleanup;
2123                                 }
2124                                 /* HC is busted, give up! */
2125                                 xhci_err(xhci,
2126                                         "ERROR Transfer event TRB DMA ptr not "
2127                                         "part of current TD\n");
2128                                 return -ESHUTDOWN;
2129                         }
2130
2131                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2132                         goto cleanup;
2133                 }
2134                 if (trb_comp_code == COMP_SHORT_TX)
2135                         ep_ring->last_td_was_short = true;
2136                 else
2137                         ep_ring->last_td_was_short = false;
2138
2139                 if (ep->skip) {
2140                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2141                         ep->skip = false;
2142                 }
2143
2144                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2145                                                 sizeof(*event_trb)];
2146                 /*
2147                  * No-op TRB should not trigger interrupts.
2148                  * If event_trb is a no-op TRB, it means the
2149                  * corresponding TD has been cancelled. Just ignore
2150                  * the TD.
2151                  */
2152                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2153                         xhci_dbg(xhci,
2154                                  "event_trb is a no-op TRB. Skip it\n");
2155                         goto cleanup;
2156                 }
2157
2158                 /* Now update the urb's actual_length and give back to
2159                  * the core
2160                  */
2161                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2162                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2163                                                  &status);
2164                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2165                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2166                                                  &status);
2167                 else
2168                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2169                                                  ep, &status);
2170
2171 cleanup:
2172                 /*
2173                  * Do not update event ring dequeue pointer if ep->skip is set.
2174                  * Will roll back to continue process missed tds.
2175                  */
2176                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2177                         inc_deq(xhci, xhci->event_ring, true);
2178                 }
2179
2180                 if (ret) {
2181                         urb = td->urb;
2182                         urb_priv = urb->hcpriv;
2183                         /* Leave the TD around for the reset endpoint function
2184                          * to use(but only if it's not a control endpoint,
2185                          * since we already queued the Set TR dequeue pointer
2186                          * command for stalled control endpoints).
2187                          */
2188                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2189                                 (trb_comp_code != COMP_STALL &&
2190                                         trb_comp_code != COMP_BABBLE))
2191                                 xhci_urb_free_priv(xhci, urb_priv);
2192
2193                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2194                         if ((urb->actual_length != urb->transfer_buffer_length &&
2195                                                 (urb->transfer_flags &
2196                                                  URB_SHORT_NOT_OK)) ||
2197                                         (status != 0 &&
2198                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2199                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2200                                                 "expected = %x, status = %d\n",
2201                                                 urb, urb->actual_length,
2202                                                 urb->transfer_buffer_length,
2203                                                 status);
2204                         spin_unlock(&xhci->lock);
2205                         /* EHCI, UHCI, and OHCI always unconditionally set the
2206                          * urb->status of an isochronous endpoint to 0.
2207                          */
2208                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2209                                 status = 0;
2210                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2211                         spin_lock(&xhci->lock);
2212                 }
2213
2214         /*
2215          * If ep->skip is set, it means there are missed tds on the
2216          * endpoint ring need to take care of.
2217          * Process them as short transfer until reach the td pointed by
2218          * the event.
2219          */
2220         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2221
2222         return 0;
2223 }
2224
2225 /*
2226  * This function handles all OS-owned events on the event ring.  It may drop
2227  * xhci->lock between event processing (e.g. to pass up port status changes).
2228  * Returns >0 for "possibly more events to process" (caller should call again),
2229  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2230  */
2231 static int xhci_handle_event(struct xhci_hcd *xhci)
2232 {
2233         union xhci_trb *event;
2234         int update_ptrs = 1;
2235         int ret;
2236
2237         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2238                 xhci->error_bitmask |= 1 << 1;
2239                 return 0;
2240         }
2241
2242         event = xhci->event_ring->dequeue;
2243         /* Does the HC or OS own the TRB? */
2244         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2245             xhci->event_ring->cycle_state) {
2246                 xhci->error_bitmask |= 1 << 2;
2247                 return 0;
2248         }
2249
2250         /*
2251          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2252          * speculative reads of the event's flags/data below.
2253          */
2254         rmb();
2255         /* FIXME: Handle more event types. */
2256         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2257         case TRB_TYPE(TRB_COMPLETION):
2258                 handle_cmd_completion(xhci, &event->event_cmd);
2259                 break;
2260         case TRB_TYPE(TRB_PORT_STATUS):
2261                 handle_port_status(xhci, event);
2262                 update_ptrs = 0;
2263                 break;
2264         case TRB_TYPE(TRB_TRANSFER):
2265                 ret = handle_tx_event(xhci, &event->trans_event);
2266                 if (ret < 0)
2267                         xhci->error_bitmask |= 1 << 9;
2268                 else
2269                         update_ptrs = 0;
2270                 break;
2271         default:
2272                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2273                     TRB_TYPE(48))
2274                         handle_vendor_event(xhci, event);
2275                 else
2276                         xhci->error_bitmask |= 1 << 3;
2277         }
2278         /* Any of the above functions may drop and re-acquire the lock, so check
2279          * to make sure a watchdog timer didn't mark the host as non-responsive.
2280          */
2281         if (xhci->xhc_state & XHCI_STATE_DYING) {
2282                 xhci_dbg(xhci, "xHCI host dying, returning from "
2283                                 "event handler.\n");
2284                 return 0;
2285         }
2286
2287         if (update_ptrs)
2288                 /* Update SW event ring dequeue pointer */
2289                 inc_deq(xhci, xhci->event_ring, true);
2290
2291         /* Are there more items on the event ring?  Caller will call us again to
2292          * check.
2293          */
2294         return 1;
2295 }
2296
2297 /*
2298  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2299  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2300  * indicators of an event TRB error, but we check the status *first* to be safe.
2301  */
2302 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2303 {
2304         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2305         u32 status;
2306         union xhci_trb *trb;
2307         u64 temp_64;
2308         union xhci_trb *event_ring_deq;
2309         dma_addr_t deq;
2310
2311         spin_lock(&xhci->lock);
2312         trb = xhci->event_ring->dequeue;
2313         /* Check if the xHC generated the interrupt, or the irq is shared */
2314         status = xhci_readl(xhci, &xhci->op_regs->status);
2315         if (status == 0xffffffff)
2316                 goto hw_died;
2317
2318         if (!(status & STS_EINT)) {
2319                 spin_unlock(&xhci->lock);
2320                 return IRQ_NONE;
2321         }
2322         if (status & STS_FATAL) {
2323                 xhci_warn(xhci, "WARNING: Host System Error\n");
2324                 xhci_halt(xhci);
2325 hw_died:
2326                 spin_unlock(&xhci->lock);
2327                 return -ESHUTDOWN;
2328         }
2329
2330         /*
2331          * Clear the op reg interrupt status first,
2332          * so we can receive interrupts from other MSI-X interrupters.
2333          * Write 1 to clear the interrupt status.
2334          */
2335         status |= STS_EINT;
2336         xhci_writel(xhci, status, &xhci->op_regs->status);
2337         /* FIXME when MSI-X is supported and there are multiple vectors */
2338         /* Clear the MSI-X event interrupt status */
2339
2340         if (hcd->irq != -1) {
2341                 u32 irq_pending;
2342                 /* Acknowledge the PCI interrupt */
2343                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2344                 irq_pending |= 0x3;
2345                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2346         }
2347
2348         if (xhci->xhc_state & XHCI_STATE_DYING) {
2349                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2350                                 "Shouldn't IRQs be disabled?\n");
2351                 /* Clear the event handler busy flag (RW1C);
2352                  * the event ring should be empty.
2353                  */
2354                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2355                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2356                                 &xhci->ir_set->erst_dequeue);
2357                 spin_unlock(&xhci->lock);
2358
2359                 return IRQ_HANDLED;
2360         }
2361
2362         event_ring_deq = xhci->event_ring->dequeue;
2363         /* FIXME this should be a delayed service routine
2364          * that clears the EHB.
2365          */
2366         while (xhci_handle_event(xhci) > 0) {}
2367
2368         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2369         /* If necessary, update the HW's version of the event ring deq ptr. */
2370         if (event_ring_deq != xhci->event_ring->dequeue) {
2371                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2372                                 xhci->event_ring->dequeue);
2373                 if (deq == 0)
2374                         xhci_warn(xhci, "WARN something wrong with SW event "
2375                                         "ring dequeue ptr.\n");
2376                 /* Update HC event ring dequeue pointer */
2377                 temp_64 &= ERST_PTR_MASK;
2378                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2379         }
2380
2381         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2382         temp_64 |= ERST_EHB;
2383         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2384
2385         spin_unlock(&xhci->lock);
2386
2387         return IRQ_HANDLED;
2388 }
2389
2390 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2391 {
2392         irqreturn_t ret;
2393         struct xhci_hcd *xhci;
2394
2395         xhci = hcd_to_xhci(hcd);
2396         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2397         if (xhci->shared_hcd)
2398                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2399
2400         ret = xhci_irq(hcd);
2401
2402         return ret;
2403 }
2404
2405 /****           Endpoint Ring Operations        ****/
2406
2407 /*
2408  * Generic function for queueing a TRB on a ring.
2409  * The caller must have checked to make sure there's room on the ring.
2410  *
2411  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2412  *                      prepare_transfer()?
2413  */
2414 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2415                 bool consumer, bool more_trbs_coming, bool isoc,
2416                 u32 field1, u32 field2, u32 field3, u32 field4)
2417 {
2418         struct xhci_generic_trb *trb;
2419
2420         trb = &ring->enqueue->generic;
2421         trb->field[0] = cpu_to_le32(field1);
2422         trb->field[1] = cpu_to_le32(field2);
2423         trb->field[2] = cpu_to_le32(field3);
2424         trb->field[3] = cpu_to_le32(field4);
2425         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2426 }
2427
2428 /*
2429  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2430  * FIXME allocate segments if the ring is full.
2431  */
2432 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2433                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2434 {
2435         /* Make sure the endpoint has been added to xHC schedule */
2436         switch (ep_state) {
2437         case EP_STATE_DISABLED:
2438                 /*
2439                  * USB core changed config/interfaces without notifying us,
2440                  * or hardware is reporting the wrong state.
2441                  */
2442                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2443                 return -ENOENT;
2444         case EP_STATE_ERROR:
2445                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2446                 /* FIXME event handling code for error needs to clear it */
2447                 /* XXX not sure if this should be -ENOENT or not */
2448                 return -EINVAL;
2449         case EP_STATE_HALTED:
2450                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2451         case EP_STATE_STOPPED:
2452         case EP_STATE_RUNNING:
2453                 break;
2454         default:
2455                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2456                 /*
2457                  * FIXME issue Configure Endpoint command to try to get the HC
2458                  * back into a known state.
2459                  */
2460                 return -EINVAL;
2461         }
2462         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2463                 /* FIXME allocate more room */
2464                 xhci_err(xhci, "ERROR no room on ep ring\n");
2465                 return -ENOMEM;
2466         }
2467
2468         if (enqueue_is_link_trb(ep_ring)) {
2469                 struct xhci_ring *ring = ep_ring;
2470                 union xhci_trb *next;
2471
2472                 next = ring->enqueue;
2473
2474                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2475                         /* If we're not dealing with 0.95 hardware or isoc rings
2476                          * on AMD 0.96 host, clear the chain bit.
2477                          */
2478                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2479                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2480                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2481                         else
2482                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2483
2484                         wmb();
2485                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2486
2487                         /* Toggle the cycle bit after the last ring segment. */
2488                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2489                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2490                                 if (!in_interrupt()) {
2491                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2492                                                 "state for ring %p = %i\n",
2493                                                 ring, (unsigned int)ring->cycle_state);
2494                                 }
2495                         }
2496                         ring->enq_seg = ring->enq_seg->next;
2497                         ring->enqueue = ring->enq_seg->trbs;
2498                         next = ring->enqueue;
2499                 }
2500         }
2501
2502         return 0;
2503 }
2504
2505 static int prepare_transfer(struct xhci_hcd *xhci,
2506                 struct xhci_virt_device *xdev,
2507                 unsigned int ep_index,
2508                 unsigned int stream_id,
2509                 unsigned int num_trbs,
2510                 struct urb *urb,
2511                 unsigned int td_index,
2512                 bool isoc,
2513                 gfp_t mem_flags)
2514 {
2515         int ret;
2516         struct urb_priv *urb_priv;
2517         struct xhci_td  *td;
2518         struct xhci_ring *ep_ring;
2519         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2520
2521         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2522         if (!ep_ring) {
2523                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2524                                 stream_id);
2525                 return -EINVAL;
2526         }
2527
2528         ret = prepare_ring(xhci, ep_ring,
2529                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2530                            num_trbs, isoc, mem_flags);
2531         if (ret)
2532                 return ret;
2533
2534         urb_priv = urb->hcpriv;
2535         td = urb_priv->td[td_index];
2536
2537         INIT_LIST_HEAD(&td->td_list);
2538         INIT_LIST_HEAD(&td->cancelled_td_list);
2539
2540         if (td_index == 0) {
2541                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2542                 if (unlikely(ret))
2543                         return ret;
2544         }
2545
2546         td->urb = urb;
2547         /* Add this TD to the tail of the endpoint ring's TD list */
2548         list_add_tail(&td->td_list, &ep_ring->td_list);
2549         td->start_seg = ep_ring->enq_seg;
2550         td->first_trb = ep_ring->enqueue;
2551
2552         urb_priv->td[td_index] = td;
2553
2554         return 0;
2555 }
2556
2557 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2558 {
2559         int num_sgs, num_trbs, running_total, temp, i;
2560         struct scatterlist *sg;
2561
2562         sg = NULL;
2563         num_sgs = urb->num_sgs;
2564         temp = urb->transfer_buffer_length;
2565
2566         xhci_dbg(xhci, "count sg list trbs: \n");
2567         num_trbs = 0;
2568         for_each_sg(urb->sg, sg, num_sgs, i) {
2569                 unsigned int previous_total_trbs = num_trbs;
2570                 unsigned int len = sg_dma_len(sg);
2571
2572                 /* Scatter gather list entries may cross 64KB boundaries */
2573                 running_total = TRB_MAX_BUFF_SIZE -
2574                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2575                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2576                 if (running_total != 0)
2577                         num_trbs++;
2578
2579                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2580                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2581                         num_trbs++;
2582                         running_total += TRB_MAX_BUFF_SIZE;
2583                 }
2584                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2585                                 i, (unsigned long long)sg_dma_address(sg),
2586                                 len, len, num_trbs - previous_total_trbs);
2587
2588                 len = min_t(int, len, temp);
2589                 temp -= len;
2590                 if (temp == 0)
2591                         break;
2592         }
2593         xhci_dbg(xhci, "\n");
2594         if (!in_interrupt())
2595                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2596                                 "num_trbs = %d\n",
2597                                 urb->ep->desc.bEndpointAddress,
2598                                 urb->transfer_buffer_length,
2599                                 num_trbs);
2600         return num_trbs;
2601 }
2602
2603 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2604 {
2605         if (num_trbs != 0)
2606                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2607                                 "TRBs, %d left\n", __func__,
2608                                 urb->ep->desc.bEndpointAddress, num_trbs);
2609         if (running_total != urb->transfer_buffer_length)
2610                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2611                                 "queued %#x (%d), asked for %#x (%d)\n",
2612                                 __func__,
2613                                 urb->ep->desc.bEndpointAddress,
2614                                 running_total, running_total,
2615                                 urb->transfer_buffer_length,
2616                                 urb->transfer_buffer_length);
2617 }
2618
2619 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2620                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2621                 struct xhci_generic_trb *start_trb)
2622 {
2623         /*
2624          * Pass all the TRBs to the hardware at once and make sure this write
2625          * isn't reordered.
2626          */
2627         wmb();
2628         if (start_cycle)
2629                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2630         else
2631                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2632         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2633 }
2634
2635 /*
2636  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2637  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2638  * (comprised of sg list entries) can take several service intervals to
2639  * transmit.
2640  */
2641 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2642                 struct urb *urb, int slot_id, unsigned int ep_index)
2643 {
2644         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2645                         xhci->devs[slot_id]->out_ctx, ep_index);
2646         int xhci_interval;
2647         int ep_interval;
2648
2649         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2650         ep_interval = urb->interval;
2651         /* Convert to microframes */
2652         if (urb->dev->speed == USB_SPEED_LOW ||
2653                         urb->dev->speed == USB_SPEED_FULL)
2654                 ep_interval *= 8;
2655         /* FIXME change this to a warning and a suggestion to use the new API
2656          * to set the polling interval (once the API is added).
2657          */
2658         if (xhci_interval != ep_interval) {
2659                 if (printk_ratelimit())
2660                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2661                                         " (%d microframe%s) than xHCI "
2662                                         "(%d microframe%s)\n",
2663                                         ep_interval,
2664                                         ep_interval == 1 ? "" : "s",
2665                                         xhci_interval,
2666                                         xhci_interval == 1 ? "" : "s");
2667                 urb->interval = xhci_interval;
2668                 /* Convert back to frames for LS/FS devices */
2669                 if (urb->dev->speed == USB_SPEED_LOW ||
2670                                 urb->dev->speed == USB_SPEED_FULL)
2671                         urb->interval /= 8;
2672         }
2673         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2674 }
2675
2676 /*
2677  * The TD size is the number of bytes remaining in the TD (including this TRB),
2678  * right shifted by 10.
2679  * It must fit in bits 21:17, so it can't be bigger than 31.
2680  */
2681 static u32 xhci_td_remainder(unsigned int remainder)
2682 {
2683         u32 max = (1 << (21 - 17 + 1)) - 1;
2684
2685         if ((remainder >> 10) >= max)
2686                 return max << 17;
2687         else
2688                 return (remainder >> 10) << 17;
2689 }
2690
2691 /*
2692  * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2693  * the TD (*not* including this TRB).
2694  *
2695  * Total TD packet count = total_packet_count =
2696  *     roundup(TD size in bytes / wMaxPacketSize)
2697  *
2698  * Packets transferred up to and including this TRB = packets_transferred =
2699  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2700  *
2701  * TD size = total_packet_count - packets_transferred
2702  *
2703  * It must fit in bits 21:17, so it can't be bigger than 31.
2704  */
2705
2706 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2707                 unsigned int total_packet_count, struct urb *urb)
2708 {
2709         int packets_transferred;
2710
2711         /* One TRB with a zero-length data packet. */
2712         if (running_total == 0 && trb_buff_len == 0)
2713                 return 0;
2714
2715         /* All the TRB queueing functions don't count the current TRB in
2716          * running_total.
2717          */
2718         packets_transferred = (running_total + trb_buff_len) /
2719                 usb_endpoint_maxp(&urb->ep->desc);
2720
2721         return xhci_td_remainder(total_packet_count - packets_transferred);
2722 }
2723
2724 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2725                 struct urb *urb, int slot_id, unsigned int ep_index)
2726 {
2727         struct xhci_ring *ep_ring;
2728         unsigned int num_trbs;
2729         struct urb_priv *urb_priv;
2730         struct xhci_td *td;
2731         struct scatterlist *sg;
2732         int num_sgs;
2733         int trb_buff_len, this_sg_len, running_total;
2734         unsigned int total_packet_count;
2735         bool first_trb;
2736         u64 addr;
2737         bool more_trbs_coming;
2738
2739         struct xhci_generic_trb *start_trb;
2740         int start_cycle;
2741
2742         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2743         if (!ep_ring)
2744                 return -EINVAL;
2745
2746         num_trbs = count_sg_trbs_needed(xhci, urb);
2747         num_sgs = urb->num_sgs;
2748         total_packet_count = roundup(urb->transfer_buffer_length,
2749                         usb_endpoint_maxp(&urb->ep->desc));
2750
2751         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2752                         ep_index, urb->stream_id,
2753                         num_trbs, urb, 0, false, mem_flags);
2754         if (trb_buff_len < 0)
2755                 return trb_buff_len;
2756
2757         urb_priv = urb->hcpriv;
2758         td = urb_priv->td[0];
2759
2760         /*
2761          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2762          * until we've finished creating all the other TRBs.  The ring's cycle
2763          * state may change as we enqueue the other TRBs, so save it too.
2764          */
2765         start_trb = &ep_ring->enqueue->generic;
2766         start_cycle = ep_ring->cycle_state;
2767
2768         running_total = 0;
2769         /*
2770          * How much data is in the first TRB?
2771          *
2772          * There are three forces at work for TRB buffer pointers and lengths:
2773          * 1. We don't want to walk off the end of this sg-list entry buffer.
2774          * 2. The transfer length that the driver requested may be smaller than
2775          *    the amount of memory allocated for this scatter-gather list.
2776          * 3. TRBs buffers can't cross 64KB boundaries.
2777          */
2778         sg = urb->sg;
2779         addr = (u64) sg_dma_address(sg);
2780         this_sg_len = sg_dma_len(sg);
2781         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2782         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2783         if (trb_buff_len > urb->transfer_buffer_length)
2784                 trb_buff_len = urb->transfer_buffer_length;
2785         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2786                         trb_buff_len);
2787
2788         first_trb = true;
2789         /* Queue the first TRB, even if it's zero-length */
2790         do {
2791                 u32 field = 0;
2792                 u32 length_field = 0;
2793                 u32 remainder = 0;
2794
2795                 /* Don't change the cycle bit of the first TRB until later */
2796                 if (first_trb) {
2797                         first_trb = false;
2798                         if (start_cycle == 0)
2799                                 field |= 0x1;
2800                 } else
2801                         field |= ep_ring->cycle_state;
2802
2803                 /* Chain all the TRBs together; clear the chain bit in the last
2804                  * TRB to indicate it's the last TRB in the chain.
2805                  */
2806                 if (num_trbs > 1) {
2807                         field |= TRB_CHAIN;
2808                 } else {
2809                         /* FIXME - add check for ZERO_PACKET flag before this */
2810                         td->last_trb = ep_ring->enqueue;
2811                         field |= TRB_IOC;
2812                 }
2813
2814                 /* Only set interrupt on short packet for IN endpoints */
2815                 if (usb_urb_dir_in(urb))
2816                         field |= TRB_ISP;
2817
2818                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2819                                 "64KB boundary at %#x, end dma = %#x\n",
2820                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2821                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2822                                 (unsigned int) addr + trb_buff_len);
2823                 if (TRB_MAX_BUFF_SIZE -
2824                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2825                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2826                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2827                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2828                                         (unsigned int) addr + trb_buff_len);
2829                 }
2830
2831                 /* Set the TRB length, TD size, and interrupter fields. */
2832                 if (xhci->hci_version < 0x100) {
2833                         remainder = xhci_td_remainder(
2834                                         urb->transfer_buffer_length -
2835                                         running_total);
2836                 } else {
2837                         remainder = xhci_v1_0_td_remainder(running_total,
2838                                         trb_buff_len, total_packet_count, urb);
2839                 }
2840                 length_field = TRB_LEN(trb_buff_len) |
2841                         remainder |
2842                         TRB_INTR_TARGET(0);
2843
2844                 if (num_trbs > 1)
2845                         more_trbs_coming = true;
2846                 else
2847                         more_trbs_coming = false;
2848                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2849                                 lower_32_bits(addr),
2850                                 upper_32_bits(addr),
2851                                 length_field,
2852                                 field | TRB_TYPE(TRB_NORMAL));
2853                 --num_trbs;
2854                 running_total += trb_buff_len;
2855
2856                 /* Calculate length for next transfer --
2857                  * Are we done queueing all the TRBs for this sg entry?
2858                  */
2859                 this_sg_len -= trb_buff_len;
2860                 if (this_sg_len == 0) {
2861                         --num_sgs;
2862                         if (num_sgs == 0)
2863                                 break;
2864                         sg = sg_next(sg);
2865                         addr = (u64) sg_dma_address(sg);
2866                         this_sg_len = sg_dma_len(sg);
2867                 } else {
2868                         addr += trb_buff_len;
2869                 }
2870
2871                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2872                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2873                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2874                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2875                         trb_buff_len =
2876                                 urb->transfer_buffer_length - running_total;
2877         } while (running_total < urb->transfer_buffer_length);
2878
2879         check_trb_math(urb, num_trbs, running_total);
2880         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2881                         start_cycle, start_trb);
2882         return 0;
2883 }
2884
2885 /* This is very similar to what ehci-q.c qtd_fill() does */
2886 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2887                 struct urb *urb, int slot_id, unsigned int ep_index)
2888 {
2889         struct xhci_ring *ep_ring;
2890         struct urb_priv *urb_priv;
2891         struct xhci_td *td;
2892         int num_trbs;
2893         struct xhci_generic_trb *start_trb;
2894         bool first_trb;
2895         bool more_trbs_coming;
2896         int start_cycle;
2897         u32 field, length_field;
2898
2899         int running_total, trb_buff_len, ret;
2900         unsigned int total_packet_count;
2901         u64 addr;
2902
2903         if (urb->num_sgs)
2904                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2905
2906         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2907         if (!ep_ring)
2908                 return -EINVAL;
2909
2910         num_trbs = 0;
2911         /* How much data is (potentially) left before the 64KB boundary? */
2912         running_total = TRB_MAX_BUFF_SIZE -
2913                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2914         running_total &= TRB_MAX_BUFF_SIZE - 1;
2915
2916         /* If there's some data on this 64KB chunk, or we have to send a
2917          * zero-length transfer, we need at least one TRB
2918          */
2919         if (running_total != 0 || urb->transfer_buffer_length == 0)
2920                 num_trbs++;
2921         /* How many more 64KB chunks to transfer, how many more TRBs? */
2922         while (running_total < urb->transfer_buffer_length) {
2923                 num_trbs++;
2924                 running_total += TRB_MAX_BUFF_SIZE;
2925         }
2926         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2927
2928         if (!in_interrupt())
2929                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2930                                 "addr = %#llx, num_trbs = %d\n",
2931                                 urb->ep->desc.bEndpointAddress,
2932                                 urb->transfer_buffer_length,
2933                                 urb->transfer_buffer_length,
2934                                 (unsigned long long)urb->transfer_dma,
2935                                 num_trbs);
2936
2937         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2938                         ep_index, urb->stream_id,
2939                         num_trbs, urb, 0, false, mem_flags);
2940         if (ret < 0)
2941                 return ret;
2942
2943         urb_priv = urb->hcpriv;
2944         td = urb_priv->td[0];
2945
2946         /*
2947          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2948          * until we've finished creating all the other TRBs.  The ring's cycle
2949          * state may change as we enqueue the other TRBs, so save it too.
2950          */
2951         start_trb = &ep_ring->enqueue->generic;
2952         start_cycle = ep_ring->cycle_state;
2953
2954         running_total = 0;
2955         total_packet_count = roundup(urb->transfer_buffer_length,
2956                         usb_endpoint_maxp(&urb->ep->desc));
2957         /* How much data is in the first TRB? */
2958         addr = (u64) urb->transfer_dma;
2959         trb_buff_len = TRB_MAX_BUFF_SIZE -
2960                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2961         if (trb_buff_len > urb->transfer_buffer_length)
2962                 trb_buff_len = urb->transfer_buffer_length;
2963
2964         first_trb = true;
2965
2966         /* Queue the first TRB, even if it's zero-length */
2967         do {
2968                 u32 remainder = 0;
2969                 field = 0;
2970
2971                 /* Don't change the cycle bit of the first TRB until later */
2972                 if (first_trb) {
2973                         first_trb = false;
2974                         if (start_cycle == 0)
2975                                 field |= 0x1;
2976                 } else
2977                         field |= ep_ring->cycle_state;
2978
2979                 /* Chain all the TRBs together; clear the chain bit in the last
2980                  * TRB to indicate it's the last TRB in the chain.
2981                  */
2982                 if (num_trbs > 1) {
2983                         field |= TRB_CHAIN;
2984                 } else {
2985                         /* FIXME - add check for ZERO_PACKET flag before this */
2986                         td->last_trb = ep_ring->enqueue;
2987                         field |= TRB_IOC;
2988                 }
2989
2990                 /* Only set interrupt on short packet for IN endpoints */
2991                 if (usb_urb_dir_in(urb))
2992                         field |= TRB_ISP;
2993
2994                 /* Set the TRB length, TD size, and interrupter fields. */
2995                 if (xhci->hci_version < 0x100) {
2996                         remainder = xhci_td_remainder(
2997                                         urb->transfer_buffer_length -
2998                                         running_total);
2999                 } else {
3000                         remainder = xhci_v1_0_td_remainder(running_total,
3001                                         trb_buff_len, total_packet_count, urb);
3002                 }
3003                 length_field = TRB_LEN(trb_buff_len) |
3004                         remainder |
3005                         TRB_INTR_TARGET(0);
3006
3007                 if (num_trbs > 1)
3008                         more_trbs_coming = true;
3009                 else
3010                         more_trbs_coming = false;
3011                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3012                                 lower_32_bits(addr),
3013                                 upper_32_bits(addr),
3014                                 length_field,
3015                                 field | TRB_TYPE(TRB_NORMAL));
3016                 --num_trbs;
3017                 running_total += trb_buff_len;
3018
3019                 /* Calculate length for next transfer */
3020                 addr += trb_buff_len;
3021                 trb_buff_len = urb->transfer_buffer_length - running_total;
3022                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3023                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3024         } while (running_total < urb->transfer_buffer_length);
3025
3026         check_trb_math(urb, num_trbs, running_total);
3027         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3028                         start_cycle, start_trb);
3029         return 0;
3030 }
3031
3032 /* Caller must have locked xhci->lock */
3033 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3034                 struct urb *urb, int slot_id, unsigned int ep_index)
3035 {
3036         struct xhci_ring *ep_ring;
3037         int num_trbs;
3038         int ret;
3039         struct usb_ctrlrequest *setup;
3040         struct xhci_generic_trb *start_trb;
3041         int start_cycle;
3042         u32 field, length_field;
3043         struct urb_priv *urb_priv;
3044         struct xhci_td *td;
3045
3046         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3047         if (!ep_ring)
3048                 return -EINVAL;
3049
3050         /*
3051          * Need to copy setup packet into setup TRB, so we can't use the setup
3052          * DMA address.
3053          */
3054         if (!urb->setup_packet)
3055                 return -EINVAL;
3056
3057         if (!in_interrupt())
3058                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3059                                 slot_id, ep_index);
3060         /* 1 TRB for setup, 1 for status */
3061         num_trbs = 2;
3062         /*
3063          * Don't need to check if we need additional event data and normal TRBs,
3064          * since data in control transfers will never get bigger than 16MB
3065          * XXX: can we get a buffer that crosses 64KB boundaries?
3066          */
3067         if (urb->transfer_buffer_length > 0)
3068                 num_trbs++;
3069         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3070                         ep_index, urb->stream_id,
3071                         num_trbs, urb, 0, false, mem_flags);
3072         if (ret < 0)
3073                 return ret;
3074
3075         urb_priv = urb->hcpriv;
3076         td = urb_priv->td[0];
3077
3078         /*
3079          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3080          * until we've finished creating all the other TRBs.  The ring's cycle
3081          * state may change as we enqueue the other TRBs, so save it too.
3082          */
3083         start_trb = &ep_ring->enqueue->generic;
3084         start_cycle = ep_ring->cycle_state;
3085
3086         /* Queue setup TRB - see section 6.4.1.2.1 */
3087         /* FIXME better way to translate setup_packet into two u32 fields? */
3088         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3089         field = 0;
3090         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3091         if (start_cycle == 0)
3092                 field |= 0x1;
3093
3094         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3095         if (xhci->hci_version == 0x100) {
3096                 if (urb->transfer_buffer_length > 0) {
3097                         if (setup->bRequestType & USB_DIR_IN)
3098                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3099                         else
3100                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3101                 }
3102         }
3103
3104         queue_trb(xhci, ep_ring, false, true, false,
3105                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3106                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3107                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3108                   /* Immediate data in pointer */
3109                   field);
3110
3111         /* If there's data, queue data TRBs */
3112         /* Only set interrupt on short packet for IN endpoints */
3113         if (usb_urb_dir_in(urb))
3114                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3115         else
3116                 field = TRB_TYPE(TRB_DATA);
3117
3118         length_field = TRB_LEN(urb->transfer_buffer_length) |
3119                 xhci_td_remainder(urb->transfer_buffer_length) |
3120                 TRB_INTR_TARGET(0);
3121         if (urb->transfer_buffer_length > 0) {
3122                 if (setup->bRequestType & USB_DIR_IN)
3123                         field |= TRB_DIR_IN;
3124                 queue_trb(xhci, ep_ring, false, true, false,
3125                                 lower_32_bits(urb->transfer_dma),
3126                                 upper_32_bits(urb->transfer_dma),
3127                                 length_field,
3128                                 field | ep_ring->cycle_state);
3129         }
3130
3131         /* Save the DMA address of the last TRB in the TD */
3132         td->last_trb = ep_ring->enqueue;
3133
3134         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3135         /* If the device sent data, the status stage is an OUT transfer */
3136         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3137                 field = 0;
3138         else
3139                 field = TRB_DIR_IN;
3140         queue_trb(xhci, ep_ring, false, false, false,
3141                         0,
3142                         0,
3143                         TRB_INTR_TARGET(0),
3144                         /* Event on completion */
3145                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3146
3147         giveback_first_trb(xhci, slot_id, ep_index, 0,
3148                         start_cycle, start_trb);
3149         return 0;
3150 }
3151
3152 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3153                 struct urb *urb, int i)
3154 {
3155         int num_trbs = 0;
3156         u64 addr, td_len;
3157
3158         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3159         td_len = urb->iso_frame_desc[i].length;
3160
3161         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3162                         TRB_MAX_BUFF_SIZE);
3163         if (num_trbs == 0)
3164                 num_trbs++;
3165
3166         return num_trbs;
3167 }
3168
3169 /*
3170  * The transfer burst count field of the isochronous TRB defines the number of
3171  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3172  * devices can burst up to bMaxBurst number of packets per service interval.
3173  * This field is zero based, meaning a value of zero in the field means one
3174  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3175  * zero.  Only xHCI 1.0 host controllers support this field.
3176  */
3177 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3178                 struct usb_device *udev,
3179                 struct urb *urb, unsigned int total_packet_count)
3180 {
3181         unsigned int max_burst;
3182
3183         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3184                 return 0;
3185
3186         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3187         return roundup(total_packet_count, max_burst + 1) - 1;
3188 }
3189
3190 /*
3191  * Returns the number of packets in the last "burst" of packets.  This field is
3192  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3193  * the last burst packet count is equal to the total number of packets in the
3194  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3195  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3196  * contain 1 to (bMaxBurst + 1) packets.
3197  */
3198 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3199                 struct usb_device *udev,
3200                 struct urb *urb, unsigned int total_packet_count)
3201 {
3202         unsigned int max_burst;
3203         unsigned int residue;
3204
3205         if (xhci->hci_version < 0x100)
3206                 return 0;
3207
3208         switch (udev->speed) {
3209         case USB_SPEED_SUPER:
3210                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3211                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3212                 residue = total_packet_count % (max_burst + 1);
3213                 /* If residue is zero, the last burst contains (max_burst + 1)
3214                  * number of packets, but the TLBPC field is zero-based.
3215                  */
3216                 if (residue == 0)
3217                         return max_burst;
3218                 return residue - 1;
3219         default:
3220                 if (total_packet_count == 0)
3221                         return 0;
3222                 return total_packet_count - 1;
3223         }
3224 }
3225
3226 /* This is for isoc transfer */
3227 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3228                 struct urb *urb, int slot_id, unsigned int ep_index)
3229 {
3230         struct xhci_ring *ep_ring;
3231         struct urb_priv *urb_priv;
3232         struct xhci_td *td;
3233         int num_tds, trbs_per_td;
3234         struct xhci_generic_trb *start_trb;
3235         bool first_trb;
3236         int start_cycle;
3237         u32 field, length_field;
3238         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3239         u64 start_addr, addr;
3240         int i, j;
3241         bool more_trbs_coming;
3242
3243         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3244
3245         num_tds = urb->number_of_packets;
3246         if (num_tds < 1) {
3247                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3248                 return -EINVAL;
3249         }
3250
3251         if (!in_interrupt())
3252                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3253                                 " addr = %#llx, num_tds = %d\n",
3254                                 urb->ep->desc.bEndpointAddress,
3255                                 urb->transfer_buffer_length,
3256                                 urb->transfer_buffer_length,
3257                                 (unsigned long long)urb->transfer_dma,
3258                                 num_tds);
3259
3260         start_addr = (u64) urb->transfer_dma;
3261         start_trb = &ep_ring->enqueue->generic;
3262         start_cycle = ep_ring->cycle_state;
3263
3264         urb_priv = urb->hcpriv;
3265         /* Queue the first TRB, even if it's zero-length */
3266         for (i = 0; i < num_tds; i++) {
3267                 unsigned int total_packet_count;
3268                 unsigned int burst_count;
3269                 unsigned int residue;
3270
3271                 first_trb = true;
3272                 running_total = 0;
3273                 addr = start_addr + urb->iso_frame_desc[i].offset;
3274                 td_len = urb->iso_frame_desc[i].length;
3275                 td_remain_len = td_len;
3276                 total_packet_count = roundup(td_len,
3277                                 usb_endpoint_maxp(&urb->ep->desc));
3278                 /* A zero-length transfer still involves at least one packet. */
3279                 if (total_packet_count == 0)
3280                         total_packet_count++;
3281                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3282                                 total_packet_count);
3283                 residue = xhci_get_last_burst_packet_count(xhci,
3284                                 urb->dev, urb, total_packet_count);
3285
3286                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3287
3288                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3289                                 urb->stream_id, trbs_per_td, urb, i, true,
3290                                 mem_flags);
3291                 if (ret < 0) {
3292                         if (i == 0)
3293                                 return ret;
3294                         goto cleanup;
3295                 }
3296
3297                 td = urb_priv->td[i];
3298                 for (j = 0; j < trbs_per_td; j++) {
3299                         u32 remainder = 0;
3300                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3301
3302                         if (first_trb) {
3303                                 /* Queue the isoc TRB */
3304                                 field |= TRB_TYPE(TRB_ISOC);
3305                                 /* Assume URB_ISO_ASAP is set */
3306                                 field |= TRB_SIA;
3307                                 if (i == 0) {
3308                                         if (start_cycle == 0)
3309                                                 field |= 0x1;
3310                                 } else
3311                                         field |= ep_ring->cycle_state;
3312                                 first_trb = false;
3313                         } else {
3314                                 /* Queue other normal TRBs */
3315                                 field |= TRB_TYPE(TRB_NORMAL);
3316                                 field |= ep_ring->cycle_state;
3317                         }
3318
3319                         /* Only set interrupt on short packet for IN EPs */
3320                         if (usb_urb_dir_in(urb))
3321                                 field |= TRB_ISP;
3322
3323                         /* Chain all the TRBs together; clear the chain bit in
3324                          * the last TRB to indicate it's the last TRB in the
3325                          * chain.
3326                          */
3327                         if (j < trbs_per_td - 1) {
3328                                 field |= TRB_CHAIN;
3329                                 more_trbs_coming = true;
3330                         } else {
3331                                 td->last_trb = ep_ring->enqueue;
3332                                 field |= TRB_IOC;
3333                                 if (xhci->hci_version == 0x100) {
3334                                         /* Set BEI bit except for the last td */
3335                                         if (i < num_tds - 1)
3336                                                 field |= TRB_BEI;
3337                                 }
3338                                 more_trbs_coming = false;
3339                         }
3340
3341                         /* Calculate TRB length */
3342                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3343                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3344                         if (trb_buff_len > td_remain_len)
3345                                 trb_buff_len = td_remain_len;
3346
3347                         /* Set the TRB length, TD size, & interrupter fields. */
3348                         if (xhci->hci_version < 0x100) {
3349                                 remainder = xhci_td_remainder(
3350                                                 td_len - running_total);
3351                         } else {
3352                                 remainder = xhci_v1_0_td_remainder(
3353                                                 running_total, trb_buff_len,
3354                                                 total_packet_count, urb);
3355                         }
3356                         length_field = TRB_LEN(trb_buff_len) |
3357                                 remainder |
3358                                 TRB_INTR_TARGET(0);
3359
3360                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3361                                 lower_32_bits(addr),
3362                                 upper_32_bits(addr),
3363                                 length_field,
3364                                 field);
3365                         running_total += trb_buff_len;
3366
3367                         addr += trb_buff_len;
3368                         td_remain_len -= trb_buff_len;
3369                 }
3370
3371                 /* Check TD length */
3372                 if (running_total != td_len) {
3373                         xhci_err(xhci, "ISOC TD length unmatch\n");
3374                         return -EINVAL;
3375                 }
3376         }
3377
3378         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3379                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3380                         usb_amd_quirk_pll_disable();
3381         }
3382         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3383
3384         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3385                         start_cycle, start_trb);
3386         return 0;
3387 cleanup:
3388         /* Clean up a partially enqueued isoc transfer. */
3389
3390         for (i--; i >= 0; i--)
3391                 list_del_init(&urb_priv->td[i]->td_list);
3392
3393         /* Use the first TD as a temporary variable to turn the TDs we've queued
3394          * into No-ops with a software-owned cycle bit. That way the hardware
3395          * won't accidentally start executing bogus TDs when we partially
3396          * overwrite them.  td->first_trb and td->start_seg are already set.
3397          */
3398         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3399         /* Every TRB except the first & last will have its cycle bit flipped. */
3400         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3401
3402         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3403         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3404         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3405         ep_ring->cycle_state = start_cycle;
3406         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3407         return ret;
3408 }
3409
3410 /*
3411  * Check transfer ring to guarantee there is enough room for the urb.
3412  * Update ISO URB start_frame and interval.
3413  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3414  * update the urb->start_frame by now.
3415  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3416  */
3417 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3418                 struct urb *urb, int slot_id, unsigned int ep_index)
3419 {
3420         struct xhci_virt_device *xdev;
3421         struct xhci_ring *ep_ring;
3422         struct xhci_ep_ctx *ep_ctx;
3423         int start_frame;
3424         int xhci_interval;
3425         int ep_interval;
3426         int num_tds, num_trbs, i;
3427         int ret;
3428
3429         xdev = xhci->devs[slot_id];
3430         ep_ring = xdev->eps[ep_index].ring;
3431         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3432
3433         num_trbs = 0;
3434         num_tds = urb->number_of_packets;
3435         for (i = 0; i < num_tds; i++)
3436                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3437
3438         /* Check the ring to guarantee there is enough room for the whole urb.
3439          * Do not insert any td of the urb to the ring if the check failed.
3440          */
3441         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3442                            num_trbs, true, mem_flags);
3443         if (ret)
3444                 return ret;
3445
3446         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3447         start_frame &= 0x3fff;
3448
3449         urb->start_frame = start_frame;
3450         if (urb->dev->speed == USB_SPEED_LOW ||
3451                         urb->dev->speed == USB_SPEED_FULL)
3452                 urb->start_frame >>= 3;
3453
3454         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3455         ep_interval = urb->interval;
3456         /* Convert to microframes */
3457         if (urb->dev->speed == USB_SPEED_LOW ||
3458                         urb->dev->speed == USB_SPEED_FULL)
3459                 ep_interval *= 8;
3460         /* FIXME change this to a warning and a suggestion to use the new API
3461          * to set the polling interval (once the API is added).
3462          */
3463         if (xhci_interval != ep_interval) {
3464                 if (printk_ratelimit())
3465                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3466                                         " (%d microframe%s) than xHCI "
3467                                         "(%d microframe%s)\n",
3468                                         ep_interval,
3469                                         ep_interval == 1 ? "" : "s",
3470                                         xhci_interval,
3471                                         xhci_interval == 1 ? "" : "s");
3472                 urb->interval = xhci_interval;
3473                 /* Convert back to frames for LS/FS devices */
3474                 if (urb->dev->speed == USB_SPEED_LOW ||
3475                                 urb->dev->speed == USB_SPEED_FULL)
3476                         urb->interval /= 8;
3477         }
3478         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3479 }
3480
3481 /****           Command Ring Operations         ****/
3482
3483 /* Generic function for queueing a command TRB on the command ring.
3484  * Check to make sure there's room on the command ring for one command TRB.
3485  * Also check that there's room reserved for commands that must not fail.
3486  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3487  * then only check for the number of reserved spots.
3488  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3489  * because the command event handler may want to resubmit a failed command.
3490  */
3491 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3492                 u32 field3, u32 field4, bool command_must_succeed)
3493 {
3494         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3495         int ret;
3496
3497         if (!command_must_succeed)
3498                 reserved_trbs++;
3499
3500         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3501                         reserved_trbs, false, GFP_ATOMIC);
3502         if (ret < 0) {
3503                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3504                 if (command_must_succeed)
3505                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3506                                         "unfailable commands failed.\n");
3507                 return ret;
3508         }
3509         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3510                         field3, field4 | xhci->cmd_ring->cycle_state);
3511         return 0;
3512 }
3513
3514 /* Queue a slot enable or disable request on the command ring */
3515 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3516 {
3517         return queue_command(xhci, 0, 0, 0,
3518                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3519 }
3520
3521 /* Queue an address device command TRB */
3522 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3523                 u32 slot_id)
3524 {
3525         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3526                         upper_32_bits(in_ctx_ptr), 0,
3527                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3528                         false);
3529 }
3530
3531 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3532                 u32 field1, u32 field2, u32 field3, u32 field4)
3533 {
3534         return queue_command(xhci, field1, field2, field3, field4, false);
3535 }
3536
3537 /* Queue a reset device command TRB */
3538 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3539 {
3540         return queue_command(xhci, 0, 0, 0,
3541                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3542                         false);
3543 }
3544
3545 /* Queue a configure endpoint command TRB */
3546 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3547                 u32 slot_id, bool command_must_succeed)
3548 {
3549         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3550                         upper_32_bits(in_ctx_ptr), 0,
3551                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3552                         command_must_succeed);
3553 }
3554
3555 /* Queue an evaluate context command TRB */
3556 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3557                 u32 slot_id)
3558 {
3559         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3560                         upper_32_bits(in_ctx_ptr), 0,
3561                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3562                         false);
3563 }
3564
3565 /*
3566  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3567  * activity on an endpoint that is about to be suspended.
3568  */
3569 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3570                 unsigned int ep_index, int suspend)
3571 {
3572         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3573         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3574         u32 type = TRB_TYPE(TRB_STOP_RING);
3575         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3576
3577         return queue_command(xhci, 0, 0, 0,
3578                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3579 }
3580
3581 /* Set Transfer Ring Dequeue Pointer command.
3582  * This should not be used for endpoints that have streams enabled.
3583  */
3584 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3585                 unsigned int ep_index, unsigned int stream_id,
3586                 struct xhci_segment *deq_seg,
3587                 union xhci_trb *deq_ptr, u32 cycle_state)
3588 {
3589         dma_addr_t addr;
3590         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3591         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3592         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3593         u32 type = TRB_TYPE(TRB_SET_DEQ);
3594         struct xhci_virt_ep *ep;
3595
3596         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3597         if (addr == 0) {
3598                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3599                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3600                                 deq_seg, deq_ptr);
3601                 return 0;
3602         }
3603         ep = &xhci->devs[slot_id]->eps[ep_index];
3604         if ((ep->ep_state & SET_DEQ_PENDING)) {
3605                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3606                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3607                 return 0;
3608         }
3609         ep->queued_deq_seg = deq_seg;
3610         ep->queued_deq_ptr = deq_ptr;
3611         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3612                         upper_32_bits(addr), trb_stream_id,
3613                         trb_slot_id | trb_ep_index | type, false);
3614 }
3615
3616 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3617                 unsigned int ep_index)
3618 {
3619         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3620         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3621         u32 type = TRB_TYPE(TRB_RESET_EP);
3622
3623         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3624                         false);
3625 }