drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return trb->link.control & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         union xhci_trb *next = ++(ring->dequeue);
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152         /* Update the dequeue pointer further if that was a link TRB or we're at
 153          * the end of an event ring segment (which doesn't have link TRBS)
 154          */
 155         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 156                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 157                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 158                         if (!in_interrupt())
 159                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 160                                                 ring,
 161                                                 (unsigned int) ring->cycle_state);
 162                 }
 163                 ring->deq_seg = ring->deq_seg->next;
 164                 ring->dequeue = ring->deq_seg->trbs;
 165                 next = ring->dequeue;
 166         }
 167         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 168         if (ring == xhci->event_ring)
 169                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 170         else if (ring == xhci->cmd_ring)
 171                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 172         else
 173                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 174 }
 175
 176 /*
 177  * See Cycle bit rules. SW is the consumer for the event ring only.
 178  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 179  *
 180  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 181  * chain bit is set), then set the chain bit in all the following link TRBs.
 182  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 183  * have their chain bit cleared (so that each Link TRB is a separate TD).
 184  *
 185  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 186  * set, but other sections talk about dealing with the chain bit set.  This was
 187  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 188  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 189  *
 190  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 191  *                      prepare_transfer()?
 192  */
 193 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 194                 bool consumer, bool more_trbs_coming)
 195 {
 196         u32 chain;
 197         union xhci_trb *next;
 198         unsigned long long addr;
 199
 200         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 201         next = ++(ring->enqueue);
 202
 203         ring->enq_updates++;
 204         /* Update the dequeue pointer further if that was a link TRB or we're at
 205          * the end of an event ring segment (which doesn't have link TRBS)
 206          */
 207         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 208                 if (!consumer) {
 209                         if (ring != xhci->event_ring) {
 210                                 /*
 211                                  * If the caller doesn't plan on enqueueing more
 212                                  * TDs before ringing the doorbell, then we
 213                                  * don't want to give the link TRB to the
 214                                  * hardware just yet.  We'll give the link TRB
 215                                  * back in prepare_ring() just before we enqueue
 216                                  * the TD at the top of the ring.
 217                                  */
 218                                 if (!chain && !more_trbs_coming)
 219                                         break;
 220
 221                                 /* If we're not dealing with 0.95 hardware,
 222                                  * carry over the chain bit of the previous TRB
 223                                  * (which may mean the chain bit is cleared).
 224                                  */
 225                                 if (!xhci_link_trb_quirk(xhci)) {
 226                                         next->link.control &= ~TRB_CHAIN;
 227                                         next->link.control |= chain;
 228                                 }
 229                                 /* Give this link TRB to the hardware */
 230                                 wmb();
 231                                 next->link.control ^= TRB_CYCLE;
 232                         }
 233                         /* Toggle the cycle bit after the last ring segment. */
 234                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 235                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 236                                 if (!in_interrupt())
 237                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 238                                                         ring,
 239                                                         (unsigned int) ring->cycle_state);
 240                         }
 241                 }
 242                 ring->enq_seg = ring->enq_seg->next;
 243                 ring->enqueue = ring->enq_seg->trbs;
 244                 next = ring->enqueue;
 245         }
 246         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 247         if (ring == xhci->event_ring)
 248                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 249         else if (ring == xhci->cmd_ring)
 250                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 251         else
 252                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 253 }
 254
 255 /*
 256  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 257  * above.
 258  * FIXME: this would be simpler and faster if we just kept track of the number
 259  * of free TRBs in a ring.
 260  */
 261 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 262                 unsigned int num_trbs)
 263 {
 264         int i;
 265         union xhci_trb *enq = ring->enqueue;
 266         struct xhci_segment *enq_seg = ring->enq_seg;
 267         struct xhci_segment *cur_seg;
 268         unsigned int left_on_ring;
 269
 270         /* If we are currently pointing to a link TRB, advance the
 271          * enqueue pointer before checking for space */
 272         while (last_trb(xhci, ring, enq_seg, enq)) {
 273                 enq_seg = enq_seg->next;
 274                 enq = enq_seg->trbs;
 275         }
 276
 277         /* Check if ring is empty */
 278         if (enq == ring->dequeue) {
 279                 /* Can't use link trbs */
 280                 left_on_ring = TRBS_PER_SEGMENT - 1;
 281                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 282                                 cur_seg = cur_seg->next)
 283                         left_on_ring += TRBS_PER_SEGMENT - 1;
 284
 285                 /* Always need one TRB free in the ring. */
 286                 left_on_ring -= 1;
 287                 if (num_trbs > left_on_ring) {
 288                         xhci_warn(xhci, "Not enough room on ring; "
 289                                         "need %u TRBs, %u TRBs left\n",
 290                                         num_trbs, left_on_ring);
 291                         return 0;
 292                 }
 293                 return 1;
 294         }
 295         /* Make sure there's an extra empty TRB available */
 296         for (i = 0; i <= num_trbs; ++i) {
 297                 if (enq == ring->dequeue)
 298                         return 0;
 299                 enq++;
 300                 while (last_trb(xhci, ring, enq_seg, enq)) {
 301                         enq_seg = enq_seg->next;
 302                         enq = enq_seg->trbs;
 303                 }
 304         }
 305         return 1;
 306 }
 307
 308 /* Ring the host controller doorbell after placing a command on the ring */
 309 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 310 {
 311         xhci_dbg(xhci, "// Ding dong!\n");
 312         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 313         /* Flush PCI posted writes */
 314         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 315 }
 316
 317 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 318                 unsigned int slot_id,
 319                 unsigned int ep_index,
 320                 unsigned int stream_id)
 321 {
 322         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 323         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 324         unsigned int ep_state = ep->ep_state;
 325
 326         /* Don't ring the doorbell for this endpoint if there are pending
 327          * cancellations because we don't want to interrupt processing.
 328          * We don't want to restart any stream rings if there's a set dequeue
 329          * pointer command pending because the device can choose to start any
 330          * stream once the endpoint is on the HW schedule.
 331          * FIXME - check all the stream rings for pending cancellations.
 332          */
 333         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 334             (ep_state & EP_HALTED))
 335                 return;
 336         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 337         /* The CPU has better things to do at this point than wait for a
 338          * write-posting flush.  It'll get there soon enough.
 339          */
 340 }
 341
 342 /* Ring the doorbell for any rings with pending URBs */
 343 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 344                 unsigned int slot_id,
 345                 unsigned int ep_index)
 346 {
 347         unsigned int stream_id;
 348         struct xhci_virt_ep *ep;
 349
 350         ep = &xhci->devs[slot_id]->eps[ep_index];
 351
 352         /* A ring has pending URBs if its TD list is not empty */
 353         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 354                 if (!(list_empty(&ep->ring->td_list)))
 355                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 356                 return;
 357         }
 358
 359         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 360                         stream_id++) {
 361                 struct xhci_stream_info *stream_info = ep->stream_info;
 362                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 363                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 364                                                 stream_id);
 365         }
 366 }
 367
 368 /*
 369  * Find the segment that trb is in.  Start searching in start_seg.
 370  * If we must move past a segment that has a link TRB with a toggle cycle state
 371  * bit set, then we will toggle the value pointed at by cycle_state.
 372  */
 373 static struct xhci_segment *find_trb_seg(
 374                 struct xhci_segment *start_seg,
 375                 union xhci_trb  *trb, int *cycle_state)
 376 {
 377         struct xhci_segment *cur_seg = start_seg;
 378         struct xhci_generic_trb *generic_trb;
 379
 380         while (cur_seg->trbs > trb ||
 381                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 382                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 383                 if (generic_trb->field[3] & LINK_TOGGLE)
 384                         *cycle_state ^= 0x1;
 385                 cur_seg = cur_seg->next;
 386                 if (cur_seg == start_seg)
 387                         /* Looped over the entire list.  Oops! */
 388                         return NULL;
 389         }
 390         return cur_seg;
 391 }
 392
 393
 394 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 395                 unsigned int slot_id, unsigned int ep_index,
 396                 unsigned int stream_id)
 397 {
 398         struct xhci_virt_ep *ep;
 399
 400         ep = &xhci->devs[slot_id]->eps[ep_index];
 401         /* Common case: no streams */
 402         if (!(ep->ep_state & EP_HAS_STREAMS))
 403                 return ep->ring;
 404
 405         if (stream_id == 0) {
 406                 xhci_warn(xhci,
 407                                 "WARN: Slot ID %u, ep index %u has streams, "
 408                                 "but URB has no stream ID.\n",
 409                                 slot_id, ep_index);
 410                 return NULL;
 411         }
 412
 413         if (stream_id < ep->stream_info->num_streams)
 414                 return ep->stream_info->stream_rings[stream_id];
 415
 416         xhci_warn(xhci,
 417                         "WARN: Slot ID %u, ep index %u has "
 418                         "stream IDs 1 to %u allocated, "
 419                         "but stream ID %u is requested.\n",
 420                         slot_id, ep_index,
 421                         ep->stream_info->num_streams - 1,
 422                         stream_id);
 423         return NULL;
 424 }
 425
 426 /* Get the right ring for the given URB.
 427  * If the endpoint supports streams, boundary check the URB's stream ID.
 428  * If the endpoint doesn't support streams, return the singular endpoint ring.
 429  */
 430 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 431                 struct urb *urb)
 432 {
 433         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 434                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 435 }
 436
 437 /*
 438  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 439  * Record the new state of the xHC's endpoint ring dequeue segment,
 440  * dequeue pointer, and new consumer cycle state in state.
 441  * Update our internal representation of the ring's dequeue pointer.
 442  *
 443  * We do this in three jumps:
 444  *  - First we update our new ring state to be the same as when the xHC stopped.
 445  *  - Then we traverse the ring to find the segment that contains
 446  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 447  *    any link TRBs with the toggle cycle bit set.
 448  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 449  *    if we've moved it past a link TRB with the toggle cycle bit set.
 450  */
 451 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 452                 unsigned int slot_id, unsigned int ep_index,
 453                 unsigned int stream_id, struct xhci_td *cur_td,
 454                 struct xhci_dequeue_state *state)
 455 {
 456         struct xhci_virt_device *dev = xhci->devs[slot_id];
 457         struct xhci_ring *ep_ring;
 458         struct xhci_generic_trb *trb;
 459         struct xhci_ep_ctx *ep_ctx;
 460         dma_addr_t addr;
 461
 462         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 463                         ep_index, stream_id);
 464         if (!ep_ring) {
 465                 xhci_warn(xhci, "WARN can't find new dequeue state "
 466                                 "for invalid stream ID %u.\n",
 467                                 stream_id);
 468                 return;
 469         }
 470         state->new_cycle_state = 0;
 471         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 472         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 473                         dev->eps[ep_index].stopped_trb,
 474                         &state->new_cycle_state);
 475         if (!state->new_deq_seg) {
 476                 WARN_ON(1);
 477                 return;
 478         }
 479
 480         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 481         xhci_dbg(xhci, "Finding endpoint context\n");
 482         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 483         state->new_cycle_state = 0x1 & ep_ctx->deq;
 484
 485         state->new_deq_ptr = cur_td->last_trb;
 486         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 487         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 488                         state->new_deq_ptr,
 489                         &state->new_cycle_state);
 490         if (!state->new_deq_seg) {
 491                 WARN_ON(1);
 492                 return;
 493         }
 494
 495         trb = &state->new_deq_ptr->generic;
 496         if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
 497                                 (trb->field[3] & LINK_TOGGLE))
 498                 state->new_cycle_state ^= 0x1;
 499         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 500
 501         /*
 502          * If there is only one segment in a ring, find_trb_seg()'s while loop
 503          * will not run, and it will return before it has a chance to see if it
 504          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 505          * ended just before the link TRB on a one-segment ring, or if the TD
 506          * wrapped around the top of the ring, because it doesn't have the TD in
 507          * question.  Look for the one-segment case where stalled TRB's address
 508          * is greater than the new dequeue pointer address.
 509          */
 510         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 511                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 512                 state->new_cycle_state ^= 0x1;
 513         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 514
 515         /* Don't update the ring cycle state for the producer (us). */
 516         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 517                         state->new_deq_seg);
 518         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 519         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 520                         (unsigned long long) addr);
 521 }
 522
 523 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 524                 struct xhci_td *cur_td)
 525 {
 526         struct xhci_segment *cur_seg;
 527         union xhci_trb *cur_trb;
 528
 529         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 530                         true;
 531                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 532                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 533                                 TRB_TYPE(TRB_LINK)) {
 534                         /* Unchain any chained Link TRBs, but
 535                          * leave the pointers intact.
 536                          */
 537                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 538                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 539                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 540                                         "in seg %p (0x%llx dma)\n",
 541                                         cur_trb,
 542                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 543                                         cur_seg,
 544                                         (unsigned long long)cur_seg->dma);
 545                 } else {
 546                         cur_trb->generic.field[0] = 0;
 547                         cur_trb->generic.field[1] = 0;
 548                         cur_trb->generic.field[2] = 0;
 549                         /* Preserve only the cycle bit of this TRB */
 550                         cur_trb->generic.field[3] &= TRB_CYCLE;
 551                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 552                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 553                                         "in seg %p (0x%llx dma)\n",
 554                                         cur_trb,
 555                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 556                                         cur_seg,
 557                                         (unsigned long long)cur_seg->dma);
 558                 }
 559                 if (cur_trb == cur_td->last_trb)
 560                         break;
 561         }
 562 }
 563
 564 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 565                 unsigned int ep_index, unsigned int stream_id,
 566                 struct xhci_segment *deq_seg,
 567                 union xhci_trb *deq_ptr, u32 cycle_state);
 568
 569 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 570                 unsigned int slot_id, unsigned int ep_index,
 571                 unsigned int stream_id,
 572                 struct xhci_dequeue_state *deq_state)
 573 {
 574         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 575
 576         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 577                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 578                         deq_state->new_deq_seg,
 579                         (unsigned long long)deq_state->new_deq_seg->dma,
 580                         deq_state->new_deq_ptr,
 581                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 582                         deq_state->new_cycle_state);
 583         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 584                         deq_state->new_deq_seg,
 585                         deq_state->new_deq_ptr,
 586                         (u32) deq_state->new_cycle_state);
 587         /* Stop the TD queueing code from ringing the doorbell until
 588          * this command completes.  The HC won't set the dequeue pointer
 589          * if the ring is running, and ringing the doorbell starts the
 590          * ring running.
 591          */
 592         ep->ep_state |= SET_DEQ_PENDING;
 593 }
 594
 595 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 596                 struct xhci_virt_ep *ep)
 597 {
 598         ep->ep_state &= ~EP_HALT_PENDING;
 599         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 600          * timer is running on another CPU, we don't decrement stop_cmds_pending
 601          * (since we didn't successfully stop the watchdog timer).
 602          */
 603         if (del_timer(&ep->stop_cmd_timer))
 604                 ep->stop_cmds_pending--;
 605 }
 606
 607 /* Must be called with xhci->lock held in interrupt context */
 608 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 609                 struct xhci_td *cur_td, int status, char *adjective)
 610 {
 611         struct usb_hcd *hcd;
 612         struct urb      *urb;
 613         struct urb_priv *urb_priv;
 614
 615         urb = cur_td->urb;
 616         urb_priv = urb->hcpriv;
 617         urb_priv->td_cnt++;
 618         hcd = bus_to_hcd(urb->dev->bus);
 619
 620         /* Only giveback urb when this is the last td in urb */
 621         if (urb_priv->td_cnt == urb_priv->length) {
 622                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 623                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 624                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 625                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 626                                         usb_amd_quirk_pll_enable();
 627                         }
 628                 }
 629                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 630                 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
 631
 632                 spin_unlock(&xhci->lock);
 633                 usb_hcd_giveback_urb(hcd, urb, status);
 634                 xhci_urb_free_priv(xhci, urb_priv);
 635                 spin_lock(&xhci->lock);
 636                 xhci_dbg(xhci, "%s URB given back\n", adjective);
 637         }
 638 }
 639
 640 /*
 641  * When we get a command completion for a Stop Endpoint Command, we need to
 642  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 643  *
 644  *  1. If the HW was in the middle of processing the TD that needs to be
 645  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 646  *     in the TD with a Set Dequeue Pointer Command.
 647  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 648  *     bit cleared) so that the HW will skip over them.
 649  */
 650 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 651                 union xhci_trb *trb, struct xhci_event_cmd *event)
 652 {
 653         unsigned int slot_id;
 654         unsigned int ep_index;
 655         struct xhci_virt_device *virt_dev;
 656         struct xhci_ring *ep_ring;
 657         struct xhci_virt_ep *ep;
 658         struct list_head *entry;
 659         struct xhci_td *cur_td = NULL;
 660         struct xhci_td *last_unlinked_td;
 661
 662         struct xhci_dequeue_state deq_state;
 663
 664         if (unlikely(TRB_TO_SUSPEND_PORT(
 665                         xhci->cmd_ring->dequeue->generic.field[3]))) {
 666                 slot_id = TRB_TO_SLOT_ID(
 667                         xhci->cmd_ring->dequeue->generic.field[3]);
 668                 virt_dev = xhci->devs[slot_id];
 669                 if (virt_dev)
 670                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 671                                 event);
 672                 else
 673                         xhci_warn(xhci, "Stop endpoint command "
 674                                 "completion for disabled slot %u\n",
 675                                 slot_id);
 676                 return;
 677         }
 678
 679         memset(&deq_state, 0, sizeof(deq_state));
 680         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 681         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 682         ep = &xhci->devs[slot_id]->eps[ep_index];
 683
 684         if (list_empty(&ep->cancelled_td_list)) {
 685                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 686                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 687                 return;
 688         }
 689
 690         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 691          * We have the xHCI lock, so nothing can modify this list until we drop
 692          * it.  We're also in the event handler, so we can't get re-interrupted
 693          * if another Stop Endpoint command completes
 694          */
 695         list_for_each(entry, &ep->cancelled_td_list) {
 696                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 697                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 698                                 cur_td->first_trb,
 699                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 700                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 701                 if (!ep_ring) {
 702                         /* This shouldn't happen unless a driver is mucking
 703                          * with the stream ID after submission.  This will
 704                          * leave the TD on the hardware ring, and the hardware
 705                          * will try to execute it, and may access a buffer
 706                          * that has already been freed.  In the best case, the
 707                          * hardware will execute it, and the event handler will
 708                          * ignore the completion event for that TD, since it was
 709                          * removed from the td_list for that endpoint.  In
 710                          * short, don't muck with the stream ID after
 711                          * submission.
 712                          */
 713                         xhci_warn(xhci, "WARN Cancelled URB %p "
 714                                         "has invalid stream ID %u.\n",
 715                                         cur_td->urb,
 716                                         cur_td->urb->stream_id);
 717                         goto remove_finished_td;
 718                 }
 719                 /*
 720                  * If we stopped on the TD we need to cancel, then we have to
 721                  * move the xHC endpoint ring dequeue pointer past this TD.
 722                  */
 723                 if (cur_td == ep->stopped_td)
 724                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 725                                         cur_td->urb->stream_id,
 726                                         cur_td, &deq_state);
 727                 else
 728                         td_to_noop(xhci, ep_ring, cur_td);
 729 remove_finished_td:
 730                 /*
 731                  * The event handler won't see a completion for this TD anymore,
 732                  * so remove it from the endpoint ring's TD list.  Keep it in
 733                  * the cancelled TD list for URB completion later.
 734                  */
 735                 list_del(&cur_td->td_list);
 736         }
 737         last_unlinked_td = cur_td;
 738         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 739
 740         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 741         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 742                 xhci_queue_new_dequeue_state(xhci,
 743                                 slot_id, ep_index,
 744                                 ep->stopped_td->urb->stream_id,
 745                                 &deq_state);
 746                 xhci_ring_cmd_db(xhci);
 747         } else {
 748                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 749                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 750         }
 751         ep->stopped_td = NULL;
 752         ep->stopped_trb = NULL;
 753
 754         /*
 755          * Drop the lock and complete the URBs in the cancelled TD list.
 756          * New TDs to be cancelled might be added to the end of the list before
 757          * we can complete all the URBs for the TDs we already unlinked.
 758          * So stop when we've completed the URB for the last TD we unlinked.
 759          */
 760         do {
 761                 cur_td = list_entry(ep->cancelled_td_list.next,
 762                                 struct xhci_td, cancelled_td_list);
 763                 list_del(&cur_td->cancelled_td_list);
 764
 765                 /* Clean up the cancelled URB */
 766                 /* Doesn't matter what we pass for status, since the core will
 767                  * just overwrite it (because the URB has been unlinked).
 768                  */
 769                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 770
 771                 /* Stop processing the cancelled list if the watchdog timer is
 772                  * running.
 773                  */
 774                 if (xhci->xhc_state & XHCI_STATE_DYING)
 775                         return;
 776         } while (cur_td != last_unlinked_td);
 777
 778         /* Return to the event handler with xhci->lock re-acquired */
 779 }
 780
 781 /* Watchdog timer function for when a stop endpoint command fails to complete.
 782  * In this case, we assume the host controller is broken or dying or dead.  The
 783  * host may still be completing some other events, so we have to be careful to
 784  * let the event ring handler and the URB dequeueing/enqueueing functions know
 785  * through xhci->state.
 786  *
 787  * The timer may also fire if the host takes a very long time to respond to the
 788  * command, and the stop endpoint command completion handler cannot delete the
 789  * timer before the timer function is called.  Another endpoint cancellation may
 790  * sneak in before the timer function can grab the lock, and that may queue
 791  * another stop endpoint command and add the timer back.  So we cannot use a
 792  * simple flag to say whether there is a pending stop endpoint command for a
 793  * particular endpoint.
 794  *
 795  * Instead we use a combination of that flag and a counter for the number of
 796  * pending stop endpoint commands.  If the timer is the tail end of the last
 797  * stop endpoint command, and the endpoint's command is still pending, we assume
 798  * the host is dying.
 799  */
 800 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 801 {
 802         struct xhci_hcd *xhci;
 803         struct xhci_virt_ep *ep;
 804         struct xhci_virt_ep *temp_ep;
 805         struct xhci_ring *ring;
 806         struct xhci_td *cur_td;
 807         int ret, i, j;
 808
 809         ep = (struct xhci_virt_ep *) arg;
 810         xhci = ep->xhci;
 811
 812         spin_lock(&xhci->lock);
 813
 814         ep->stop_cmds_pending--;
 815         if (xhci->xhc_state & XHCI_STATE_DYING) {
 816                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 817                                 "xHCI as DYING, exiting.\n");
 818                 spin_unlock(&xhci->lock);
 819                 return;
 820         }
 821         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 822                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 823                                 "exiting.\n");
 824                 spin_unlock(&xhci->lock);
 825                 return;
 826         }
 827
 828         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 829         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 830         /* Oops, HC is dead or dying or at least not responding to the stop
 831          * endpoint command.
 832          */
 833         xhci->xhc_state |= XHCI_STATE_DYING;
 834         /* Disable interrupts from the host controller and start halting it */
 835         xhci_quiesce(xhci);
 836         spin_unlock(&xhci->lock);
 837
 838         ret = xhci_halt(xhci);
 839
 840         spin_lock(&xhci->lock);
 841         if (ret < 0) {
 842                 /* This is bad; the host is not responding to commands and it's
 843                  * not allowing itself to be halted.  At least interrupts are
 844                  * disabled. If we call usb_hc_died(), it will attempt to
 845                  * disconnect all device drivers under this host.  Those
 846                  * disconnect() methods will wait for all URBs to be unlinked,
 847                  * so we must complete them.
 848                  */
 849                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 850                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 851                 /* We could turn all TDs on the rings to no-ops.  This won't
 852                  * help if the host has cached part of the ring, and is slow if
 853                  * we want to preserve the cycle bit.  Skip it and hope the host
 854                  * doesn't touch the memory.
 855                  */
 856         }
 857         for (i = 0; i < MAX_HC_SLOTS; i++) {
 858                 if (!xhci->devs[i])
 859                         continue;
 860                 for (j = 0; j < 31; j++) {
 861                         temp_ep = &xhci->devs[i]->eps[j];
 862                         ring = temp_ep->ring;
 863                         if (!ring)
 864                                 continue;
 865                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 866                                         "ep index %u\n", i, j);
 867                         while (!list_empty(&ring->td_list)) {
 868                                 cur_td = list_first_entry(&ring->td_list,
 869                                                 struct xhci_td,
 870                                                 td_list);
 871                                 list_del(&cur_td->td_list);
 872                                 if (!list_empty(&cur_td->cancelled_td_list))
 873                                         list_del(&cur_td->cancelled_td_list);
 874                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 875                                                 -ESHUTDOWN, "killed");
 876                         }
 877                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 878                                 cur_td = list_first_entry(
 879                                                 &temp_ep->cancelled_td_list,
 880                                                 struct xhci_td,
 881                                                 cancelled_td_list);
 882                                 list_del(&cur_td->cancelled_td_list);
 883                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 884                                                 -ESHUTDOWN, "killed");
 885                         }
 886                 }
 887         }
 888         spin_unlock(&xhci->lock);
 889         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 890         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 891         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 892 }
 893
 894 /*
 895  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 896  * we need to clear the set deq pending flag in the endpoint ring state, so that
 897  * the TD queueing code can ring the doorbell again.  We also need to ring the
 898  * endpoint doorbell to restart the ring, but only if there aren't more
 899  * cancellations pending.
 900  */
 901 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 902                 struct xhci_event_cmd *event,
 903                 union xhci_trb *trb)
 904 {
 905         unsigned int slot_id;
 906         unsigned int ep_index;
 907         unsigned int stream_id;
 908         struct xhci_ring *ep_ring;
 909         struct xhci_virt_device *dev;
 910         struct xhci_ep_ctx *ep_ctx;
 911         struct xhci_slot_ctx *slot_ctx;
 912
 913         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 914         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 915         stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
 916         dev = xhci->devs[slot_id];
 917
 918         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 919         if (!ep_ring) {
 920                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 921                                 "freed stream ID %u\n",
 922                                 stream_id);
 923                 /* XXX: Harmless??? */
 924                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 925                 return;
 926         }
 927
 928         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 929         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 930
 931         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 932                 unsigned int ep_state;
 933                 unsigned int slot_state;
 934
 935                 switch (GET_COMP_CODE(event->status)) {
 936                 case COMP_TRB_ERR:
 937                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 938                                         "of stream ID configuration\n");
 939                         break;
 940                 case COMP_CTX_STATE:
 941                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 942                                         "to incorrect slot or ep state.\n");
 943                         ep_state = ep_ctx->ep_info;
 944                         ep_state &= EP_STATE_MASK;
 945                         slot_state = slot_ctx->dev_state;
 946                         slot_state = GET_SLOT_STATE(slot_state);
 947                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 948                                         slot_state, ep_state);
 949                         break;
 950                 case COMP_EBADSLT:
 951                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 952                                         "slot %u was not enabled.\n", slot_id);
 953                         break;
 954                 default:
 955                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 956                                         "completion code of %u.\n",
 957                                         GET_COMP_CODE(event->status));
 958                         break;
 959                 }
 960                 /* OK what do we do now?  The endpoint state is hosed, and we
 961                  * should never get to this point if the synchronization between
 962                  * queueing, and endpoint state are correct.  This might happen
 963                  * if the device gets disconnected after we've finished
 964                  * cancelling URBs, which might not be an error...
 965                  */
 966         } else {
 967                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 968                                 ep_ctx->deq);
 969                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 970                                         dev->eps[ep_index].queued_deq_ptr) ==
 971                                 (ep_ctx->deq & ~(EP_CTX_CYCLE_MASK))) {
 972                         /* Update the ring's dequeue segment and dequeue pointer
 973                          * to reflect the new position.
 974                          */
 975                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
 976                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
 977                 } else {
 978                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 979                                         "Ptr command & xHCI internal state.\n");
 980                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 981                                         dev->eps[ep_index].queued_deq_seg,
 982                                         dev->eps[ep_index].queued_deq_ptr);
 983                 }
 984         }
 985
 986         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 987         dev->eps[ep_index].queued_deq_seg = NULL;
 988         dev->eps[ep_index].queued_deq_ptr = NULL;
 989         /* Restart any rings with pending URBs */
 990         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 991 }
 992
 993 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 994                 struct xhci_event_cmd *event,
 995                 union xhci_trb *trb)
 996 {
 997         int slot_id;
 998         unsigned int ep_index;
 999
1000         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
1001         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
1002         /* This command will only fail if the endpoint wasn't halted,
1003          * but we don't care.
1004          */
1005         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1006                         (unsigned int) GET_COMP_CODE(event->status));
1007
1008         /* HW with the reset endpoint quirk needs to have a configure endpoint
1009          * command complete before the endpoint can be used.  Queue that here
1010          * because the HW can't handle two commands being queued in a row.
1011          */
1012         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1013                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1014                 xhci_queue_configure_endpoint(xhci,
1015                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1016                                 false);
1017                 xhci_ring_cmd_db(xhci);
1018         } else {
1019                 /* Clear our internal halted state and restart the ring(s) */
1020                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1021                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1022         }
1023 }
1024
1025 /* Check to see if a command in the device's command queue matches this one.
1026  * Signal the completion or free the command, and return 1.  Return 0 if the
1027  * completed command isn't at the head of the command list.
1028  */
1029 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1030                 struct xhci_virt_device *virt_dev,
1031                 struct xhci_event_cmd *event)
1032 {
1033         struct xhci_command *command;
1034
1035         if (list_empty(&virt_dev->cmd_list))
1036                 return 0;
1037
1038         command = list_entry(virt_dev->cmd_list.next,
1039                         struct xhci_command, cmd_list);
1040         if (xhci->cmd_ring->dequeue != command->command_trb)
1041                 return 0;
1042
1043         command->status =
1044                 GET_COMP_CODE(event->status);
1045         list_del(&command->cmd_list);
1046         if (command->completion)
1047                 complete(command->completion);
1048         else
1049                 xhci_free_command(xhci, command);
1050         return 1;
1051 }
1052
1053 static void handle_cmd_completion(struct xhci_hcd *xhci,
1054                 struct xhci_event_cmd *event)
1055 {
1056         int slot_id = TRB_TO_SLOT_ID(event->flags);
1057         u64 cmd_dma;
1058         dma_addr_t cmd_dequeue_dma;
1059         struct xhci_input_control_ctx *ctrl_ctx;
1060         struct xhci_virt_device *virt_dev;
1061         unsigned int ep_index;
1062         struct xhci_ring *ep_ring;
1063         unsigned int ep_state;
1064
1065         cmd_dma = event->cmd_trb;
1066         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1067                         xhci->cmd_ring->dequeue);
1068         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1069         if (cmd_dequeue_dma == 0) {
1070                 xhci->error_bitmask |= 1 << 4;
1071                 return;
1072         }
1073         /* Does the DMA address match our internal dequeue pointer address? */
1074         if (cmd_dma != (u64) cmd_dequeue_dma) {
1075                 xhci->error_bitmask |= 1 << 5;
1076                 return;
1077         }
1078         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1079         case TRB_TYPE(TRB_ENABLE_SLOT):
1080                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1081                         xhci->slot_id = slot_id;
1082                 else
1083                         xhci->slot_id = 0;
1084                 complete(&xhci->addr_dev);
1085                 break;
1086         case TRB_TYPE(TRB_DISABLE_SLOT):
1087                 if (xhci->devs[slot_id])
1088                         xhci_free_virt_device(xhci, slot_id);
1089                 break;
1090         case TRB_TYPE(TRB_CONFIG_EP):
1091                 virt_dev = xhci->devs[slot_id];
1092                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1093                         break;
1094                 /*
1095                  * Configure endpoint commands can come from the USB core
1096                  * configuration or alt setting changes, or because the HW
1097                  * needed an extra configure endpoint command after a reset
1098                  * endpoint command or streams were being configured.
1099                  * If the command was for a halted endpoint, the xHCI driver
1100                  * is not waiting on the configure endpoint command.
1101                  */
1102                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1103                                 virt_dev->in_ctx);
1104                 /* Input ctx add_flags are the endpoint index plus one */
1105                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1106                 /* A usb_set_interface() call directly after clearing a halted
1107                  * condition may race on this quirky hardware.  Not worth
1108                  * worrying about, since this is prototype hardware.  Not sure
1109                  * if this will work for streams, but streams support was
1110                  * untested on this prototype.
1111                  */
1112                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1113                                 ep_index != (unsigned int) -1 &&
1114                                 ctrl_ctx->add_flags - SLOT_FLAG ==
1115                                         ctrl_ctx->drop_flags) {
1116                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1117                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1118                         if (!(ep_state & EP_HALTED))
1119                                 goto bandwidth_change;
1120                         xhci_dbg(xhci, "Completed config ep cmd - "
1121                                         "last ep index = %d, state = %d\n",
1122                                         ep_index, ep_state);
1123                         /* Clear internal halted state and restart ring(s) */
1124                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1125                                 ~EP_HALTED;
1126                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1127                         break;
1128                 }
1129 bandwidth_change:
1130                 xhci_dbg(xhci, "Completed config ep cmd\n");
1131                 xhci->devs[slot_id]->cmd_status =
1132                         GET_COMP_CODE(event->status);
1133                 complete(&xhci->devs[slot_id]->cmd_completion);
1134                 break;
1135         case TRB_TYPE(TRB_EVAL_CONTEXT):
1136                 virt_dev = xhci->devs[slot_id];
1137                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1138                         break;
1139                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1140                 complete(&xhci->devs[slot_id]->cmd_completion);
1141                 break;
1142         case TRB_TYPE(TRB_ADDR_DEV):
1143                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1144                 complete(&xhci->addr_dev);
1145                 break;
1146         case TRB_TYPE(TRB_STOP_RING):
1147                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1148                 break;
1149         case TRB_TYPE(TRB_SET_DEQ):
1150                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1151                 break;
1152         case TRB_TYPE(TRB_CMD_NOOP):
1153                 break;
1154         case TRB_TYPE(TRB_RESET_EP):
1155                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1156                 break;
1157         case TRB_TYPE(TRB_RESET_DEV):
1158                 xhci_dbg(xhci, "Completed reset device command.\n");
1159                 slot_id = TRB_TO_SLOT_ID(
1160                                 xhci->cmd_ring->dequeue->generic.field[3]);
1161                 virt_dev = xhci->devs[slot_id];
1162                 if (virt_dev)
1163                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1164                 else
1165                         xhci_warn(xhci, "Reset device command completion "
1166                                         "for disabled slot %u\n", slot_id);
1167                 break;
1168         case TRB_TYPE(TRB_NEC_GET_FW):
1169                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1170                         xhci->error_bitmask |= 1 << 6;
1171                         break;
1172                 }
1173                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1174                                 NEC_FW_MAJOR(event->status),
1175                                 NEC_FW_MINOR(event->status));
1176                 break;
1177         default:
1178                 /* Skip over unknown commands on the event ring */
1179                 xhci->error_bitmask |= 1 << 6;
1180                 break;
1181         }
1182         inc_deq(xhci, xhci->cmd_ring, false);
1183 }
1184
1185 static void handle_vendor_event(struct xhci_hcd *xhci,
1186                 union xhci_trb *event)
1187 {
1188         u32 trb_type;
1189
1190         trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1191         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1192         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1193                 handle_cmd_completion(xhci, &event->event_cmd);
1194 }
1195
1196 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1197  * port registers -- USB 3.0 and USB 2.0).
1198  *
1199  * Returns a zero-based port number, which is suitable for indexing into each of
1200  * the split roothubs' port arrays and bus state arrays.
1201  */
1202 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1203                 struct xhci_hcd *xhci, u32 port_id)
1204 {
1205         unsigned int i;
1206         unsigned int num_similar_speed_ports = 0;
1207
1208         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1209          * and usb2_ports are 0-based indexes.  Count the number of similar
1210          * speed ports, up to 1 port before this port.
1211          */
1212         for (i = 0; i < (port_id - 1); i++) {
1213                 u8 port_speed = xhci->port_array[i];
1214
1215                 /*
1216                  * Skip ports that don't have known speeds, or have duplicate
1217                  * Extended Capabilities port speed entries.
1218                  */
1219                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1220                         continue;
1221
1222                 /*
1223                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1224                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1225                  * matches the device speed, it's a similar speed port.
1226                  */
1227                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1228                         num_similar_speed_ports++;
1229         }
1230         return num_similar_speed_ports;
1231 }
1232
1233 static void handle_port_status(struct xhci_hcd *xhci,
1234                 union xhci_trb *event)
1235 {
1236         struct usb_hcd *hcd;
1237         u32 port_id;
1238         u32 temp, temp1;
1239         int max_ports;
1240         int slot_id;
1241         unsigned int faked_port_index;
1242         u8 major_revision;
1243         struct xhci_bus_state *bus_state;
1244         u32 __iomem **port_array;
1245         bool bogus_port_status = false;
1246
1247         /* Port status change events always have a successful completion code */
1248         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1249                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1250                 xhci->error_bitmask |= 1 << 8;
1251         }
1252         port_id = GET_PORT_ID(event->generic.field[0]);
1253         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1254
1255         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1256         if ((port_id <= 0) || (port_id > max_ports)) {
1257                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1258                 bogus_port_status = true;
1259                 goto cleanup;
1260         }
1261
1262         /* Figure out which usb_hcd this port is attached to:
1263          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1264          */
1265         major_revision = xhci->port_array[port_id - 1];
1266         if (major_revision == 0) {
1267                 xhci_warn(xhci, "Event for port %u not in "
1268                                 "Extended Capabilities, ignoring.\n",
1269                                 port_id);
1270                 bogus_port_status = true;
1271                 goto cleanup;
1272         }
1273         if (major_revision == DUPLICATE_ENTRY) {
1274                 xhci_warn(xhci, "Event for port %u duplicated in"
1275                                 "Extended Capabilities, ignoring.\n",
1276                                 port_id);
1277                 bogus_port_status = true;
1278                 goto cleanup;
1279         }
1280
1281         /*
1282          * Hardware port IDs reported by a Port Status Change Event include USB
1283          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1284          * resume event, but we first need to translate the hardware port ID
1285          * into the index into the ports on the correct split roothub, and the
1286          * correct bus_state structure.
1287          */
1288         /* Find the right roothub. */
1289         hcd = xhci_to_hcd(xhci);
1290         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1291                 hcd = xhci->shared_hcd;
1292         bus_state = &xhci->bus_state[hcd_index(hcd)];
1293         if (hcd->speed == HCD_USB3)
1294                 port_array = xhci->usb3_ports;
1295         else
1296                 port_array = xhci->usb2_ports;
1297         /* Find the faked port hub number */
1298         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1299                         port_id);
1300
1301         temp = xhci_readl(xhci, port_array[faked_port_index]);
1302         if (hcd->state == HC_STATE_SUSPENDED) {
1303                 xhci_dbg(xhci, "resume root hub\n");
1304                 usb_hcd_resume_root_hub(hcd);
1305         }
1306
1307         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1308                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1309
1310                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1311                 if (!(temp1 & CMD_RUN)) {
1312                         xhci_warn(xhci, "xHC is not running.\n");
1313                         goto cleanup;
1314                 }
1315
1316                 if (DEV_SUPERSPEED(temp)) {
1317                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1318                         temp = xhci_port_state_to_neutral(temp);
1319                         temp &= ~PORT_PLS_MASK;
1320                         temp |= PORT_LINK_STROBE | XDEV_U0;
1321                         xhci_writel(xhci, temp, port_array[faked_port_index]);
1322                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1323                                         faked_port_index);
1324                         if (!slot_id) {
1325                                 xhci_dbg(xhci, "slot_id is zero\n");
1326                                 goto cleanup;
1327                         }
1328                         xhci_ring_device(xhci, slot_id);
1329                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1330                         /* Clear PORT_PLC */
1331                         temp = xhci_readl(xhci, port_array[faked_port_index]);
1332                         temp = xhci_port_state_to_neutral(temp);
1333                         temp |= PORT_PLC;
1334                         xhci_writel(xhci, temp, port_array[faked_port_index]);
1335                 } else {
1336                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1337                         bus_state->resume_done[faked_port_index] = jiffies +
1338                                 msecs_to_jiffies(20);
1339                         mod_timer(&hcd->rh_timer,
1340                                   bus_state->resume_done[faked_port_index]);
1341                         /* Do the rest in GetPortStatus */
1342                 }
1343         }
1344
1345 cleanup:
1346         /* Update event ring dequeue pointer before dropping the lock */
1347         inc_deq(xhci, xhci->event_ring, true);
1348
1349         /* Don't make the USB core poll the roothub if we got a bad port status
1350          * change event.  Besides, at that point we can't tell which roothub
1351          * (USB 2.0 or USB 3.0) to kick.
1352          */
1353         if (bogus_port_status)
1354                 return;
1355
1356         spin_unlock(&xhci->lock);
1357         /* Pass this up to the core */
1358         usb_hcd_poll_rh_status(hcd);
1359         spin_lock(&xhci->lock);
1360 }
1361
1362 /*
1363  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1364  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1365  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1366  * returns 0.
1367  */
1368 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1369                 union xhci_trb  *start_trb,
1370                 union xhci_trb  *end_trb,
1371                 dma_addr_t      suspect_dma)
1372 {
1373         dma_addr_t start_dma;
1374         dma_addr_t end_seg_dma;
1375         dma_addr_t end_trb_dma;
1376         struct xhci_segment *cur_seg;
1377
1378         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1379         cur_seg = start_seg;
1380
1381         do {
1382                 if (start_dma == 0)
1383                         return NULL;
1384                 /* We may get an event for a Link TRB in the middle of a TD */
1385                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1386                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1387                 /* If the end TRB isn't in this segment, this is set to 0 */
1388                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1389
1390                 if (end_trb_dma > 0) {
1391                         /* The end TRB is in this segment, so suspect should be here */
1392                         if (start_dma <= end_trb_dma) {
1393                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1394                                         return cur_seg;
1395                         } else {
1396                                 /* Case for one segment with
1397                                  * a TD wrapped around to the top
1398                                  */
1399                                 if ((suspect_dma >= start_dma &&
1400                                                         suspect_dma <= end_seg_dma) ||
1401                                                 (suspect_dma >= cur_seg->dma &&
1402                                                  suspect_dma <= end_trb_dma))
1403                                         return cur_seg;
1404                         }
1405                         return NULL;
1406                 } else {
1407                         /* Might still be somewhere in this segment */
1408                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1409                                 return cur_seg;
1410                 }
1411                 cur_seg = cur_seg->next;
1412                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1413         } while (cur_seg != start_seg);
1414
1415         return NULL;
1416 }
1417
1418 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1419                 unsigned int slot_id, unsigned int ep_index,
1420                 unsigned int stream_id,
1421                 struct xhci_td *td, union xhci_trb *event_trb)
1422 {
1423         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1424         ep->ep_state |= EP_HALTED;
1425         ep->stopped_td = td;
1426         ep->stopped_trb = event_trb;
1427         ep->stopped_stream = stream_id;
1428
1429         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1430         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1431
1432         ep->stopped_td = NULL;
1433         ep->stopped_trb = NULL;
1434         ep->stopped_stream = 0;
1435
1436         xhci_ring_cmd_db(xhci);
1437 }
1438
1439 /* Check if an error has halted the endpoint ring.  The class driver will
1440  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1441  * However, a babble and other errors also halt the endpoint ring, and the class
1442  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1443  * Ring Dequeue Pointer command manually.
1444  */
1445 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1446                 struct xhci_ep_ctx *ep_ctx,
1447                 unsigned int trb_comp_code)
1448 {
1449         /* TRB completion codes that may require a manual halt cleanup */
1450         if (trb_comp_code == COMP_TX_ERR ||
1451                         trb_comp_code == COMP_BABBLE ||
1452                         trb_comp_code == COMP_SPLIT_ERR)
1453                 /* The 0.96 spec says a babbling control endpoint
1454                  * is not halted. The 0.96 spec says it is.  Some HW
1455                  * claims to be 0.95 compliant, but it halts the control
1456                  * endpoint anyway.  Check if a babble halted the
1457                  * endpoint.
1458                  */
1459                 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1460                         return 1;
1461
1462         return 0;
1463 }
1464
1465 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1466 {
1467         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1468                 /* Vendor defined "informational" completion code,
1469                  * treat as not-an-error.
1470                  */
1471                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1472                                 trb_comp_code);
1473                 xhci_dbg(xhci, "Treating code as success.\n");
1474                 return 1;
1475         }
1476         return 0;
1477 }
1478
1479 /*
1480  * Finish the td processing, remove the td from td list;
1481  * Return 1 if the urb can be given back.
1482  */
1483 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1484         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1485         struct xhci_virt_ep *ep, int *status, bool skip)
1486 {
1487         struct xhci_virt_device *xdev;
1488         struct xhci_ring *ep_ring;
1489         unsigned int slot_id;
1490         int ep_index;
1491         struct urb *urb = NULL;
1492         struct xhci_ep_ctx *ep_ctx;
1493         int ret = 0;
1494         struct urb_priv *urb_priv;
1495         u32 trb_comp_code;
1496
1497         slot_id = TRB_TO_SLOT_ID(event->flags);
1498         xdev = xhci->devs[slot_id];
1499         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1500         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1501         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1502         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1503
1504         if (skip)
1505                 goto td_cleanup;
1506
1507         if (trb_comp_code == COMP_STOP_INVAL ||
1508                         trb_comp_code == COMP_STOP) {
1509                 /* The Endpoint Stop Command completion will take care of any
1510                  * stopped TDs.  A stopped TD may be restarted, so don't update
1511                  * the ring dequeue pointer or take this TD off any lists yet.
1512                  */
1513                 ep->stopped_td = td;
1514                 ep->stopped_trb = event_trb;
1515                 return 0;
1516         } else {
1517                 if (trb_comp_code == COMP_STALL) {
1518                         /* The transfer is completed from the driver's
1519                          * perspective, but we need to issue a set dequeue
1520                          * command for this stalled endpoint to move the dequeue
1521                          * pointer past the TD.  We can't do that here because
1522                          * the halt condition must be cleared first.  Let the
1523                          * USB class driver clear the stall later.
1524                          */
1525                         ep->stopped_td = td;
1526                         ep->stopped_trb = event_trb;
1527                         ep->stopped_stream = ep_ring->stream_id;
1528                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1529                                         ep_ctx, trb_comp_code)) {
1530                         /* Other types of errors halt the endpoint, but the
1531                          * class driver doesn't call usb_reset_endpoint() unless
1532                          * the error is -EPIPE.  Clear the halted status in the
1533                          * xHCI hardware manually.
1534                          */
1535                         xhci_cleanup_halted_endpoint(xhci,
1536                                         slot_id, ep_index, ep_ring->stream_id,
1537                                         td, event_trb);
1538                 } else {
1539                         /* Update ring dequeue pointer */
1540                         while (ep_ring->dequeue != td->last_trb)
1541                                 inc_deq(xhci, ep_ring, false);
1542                         inc_deq(xhci, ep_ring, false);
1543                 }
1544
1545 td_cleanup:
1546                 /* Clean up the endpoint's TD list */
1547                 urb = td->urb;
1548                 urb_priv = urb->hcpriv;
1549
1550                 /* Do one last check of the actual transfer length.
1551                  * If the host controller said we transferred more data than
1552                  * the buffer length, urb->actual_length will be a very big
1553                  * number (since it's unsigned).  Play it safe and say we didn't
1554                  * transfer anything.
1555                  */
1556                 if (urb->actual_length > urb->transfer_buffer_length) {
1557                         xhci_warn(xhci, "URB transfer length is wrong, "
1558                                         "xHC issue? req. len = %u, "
1559                                         "act. len = %u\n",
1560                                         urb->transfer_buffer_length,
1561                                         urb->actual_length);
1562                         urb->actual_length = 0;
1563                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1564                                 *status = -EREMOTEIO;
1565                         else
1566                                 *status = 0;
1567                 }
1568                 list_del(&td->td_list);
1569                 /* Was this TD slated to be cancelled but completed anyway? */
1570                 if (!list_empty(&td->cancelled_td_list))
1571                         list_del(&td->cancelled_td_list);
1572
1573                 urb_priv->td_cnt++;
1574                 /* Giveback the urb when all the tds are completed */
1575                 if (urb_priv->td_cnt == urb_priv->length) {
1576                         ret = 1;
1577                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1578                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1579                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1580                                         == 0) {
1581                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1582                                                 usb_amd_quirk_pll_enable();
1583                                 }
1584                         }
1585                 }
1586         }
1587
1588         return ret;
1589 }
1590
1591 /*
1592  * Process control tds, update urb status and actual_length.
1593  */
1594 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1595         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1596         struct xhci_virt_ep *ep, int *status)
1597 {
1598         struct xhci_virt_device *xdev;
1599         struct xhci_ring *ep_ring;
1600         unsigned int slot_id;
1601         int ep_index;
1602         struct xhci_ep_ctx *ep_ctx;
1603         u32 trb_comp_code;
1604
1605         slot_id = TRB_TO_SLOT_ID(event->flags);
1606         xdev = xhci->devs[slot_id];
1607         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1608         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1609         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1610         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1611
1612         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1613         switch (trb_comp_code) {
1614         case COMP_SUCCESS:
1615                 if (event_trb == ep_ring->dequeue) {
1616                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1617                                         "without IOC set??\n");
1618                         *status = -ESHUTDOWN;
1619                 } else if (event_trb != td->last_trb) {
1620                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1621                                         "without IOC set??\n");
1622                         *status = -ESHUTDOWN;
1623                 } else {
1624                         xhci_dbg(xhci, "Successful control transfer!\n");
1625                         *status = 0;
1626                 }
1627                 break;
1628         case COMP_SHORT_TX:
1629                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1630                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1631                         *status = -EREMOTEIO;
1632                 else
1633                         *status = 0;
1634                 break;
1635         default:
1636                 if (!xhci_requires_manual_halt_cleanup(xhci,
1637                                         ep_ctx, trb_comp_code))
1638                         break;
1639                 xhci_dbg(xhci, "TRB error code %u, "
1640                                 "halted endpoint index = %u\n",
1641                                 trb_comp_code, ep_index);
1642                 /* else fall through */
1643         case COMP_STALL:
1644                 /* Did we transfer part of the data (middle) phase? */
1645                 if (event_trb != ep_ring->dequeue &&
1646                                 event_trb != td->last_trb)
1647                         td->urb->actual_length =
1648                                 td->urb->transfer_buffer_length
1649                                 - TRB_LEN(event->transfer_len);
1650                 else
1651                         td->urb->actual_length = 0;
1652
1653                 xhci_cleanup_halted_endpoint(xhci,
1654                         slot_id, ep_index, 0, td, event_trb);
1655                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1656         }
1657         /*
1658          * Did we transfer any data, despite the errors that might have
1659          * happened?  I.e. did we get past the setup stage?
1660          */
1661         if (event_trb != ep_ring->dequeue) {
1662                 /* The event was for the status stage */
1663                 if (event_trb == td->last_trb) {
1664                         if (td->urb->actual_length != 0) {
1665                                 /* Don't overwrite a previously set error code
1666                                  */
1667                                 if ((*status == -EINPROGRESS || *status == 0) &&
1668                                                 (td->urb->transfer_flags
1669                                                  & URB_SHORT_NOT_OK))
1670                                         /* Did we already see a short data
1671                                          * stage? */
1672                                         *status = -EREMOTEIO;
1673                         } else {
1674                                 td->urb->actual_length =
1675                                         td->urb->transfer_buffer_length;
1676                         }
1677                 } else {
1678                 /* Maybe the event was for the data stage? */
1679                         if (trb_comp_code != COMP_STOP_INVAL) {
1680                                 /* We didn't stop on a link TRB in the middle */
1681                                 td->urb->actual_length =
1682                                         td->urb->transfer_buffer_length -
1683                                         TRB_LEN(event->transfer_len);
1684                                 xhci_dbg(xhci, "Waiting for status "
1685                                                 "stage event\n");
1686                                 return 0;
1687                         }
1688                 }
1689         }
1690
1691         return finish_td(xhci, td, event_trb, event, ep, status, false);
1692 }
1693
1694 /*
1695  * Process isochronous tds, update urb packet status and actual_length.
1696  */
1697 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1698         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1699         struct xhci_virt_ep *ep, int *status)
1700 {
1701         struct xhci_ring *ep_ring;
1702         struct urb_priv *urb_priv;
1703         int idx;
1704         int len = 0;
1705         union xhci_trb *cur_trb;
1706         struct xhci_segment *cur_seg;
1707         struct usb_iso_packet_descriptor *frame;
1708         u32 trb_comp_code;
1709         bool skip_td = false;
1710
1711         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1712         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1713         urb_priv = td->urb->hcpriv;
1714         idx = urb_priv->td_cnt;
1715         frame = &td->urb->iso_frame_desc[idx];
1716
1717         /* handle completion code */
1718         switch (trb_comp_code) {
1719         case COMP_SUCCESS:
1720                 frame->status = 0;
1721                 xhci_dbg(xhci, "Successful isoc transfer!\n");
1722                 break;
1723         case COMP_SHORT_TX:
1724                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1725                                 -EREMOTEIO : 0;
1726                 break;
1727         case COMP_BW_OVER:
1728                 frame->status = -ECOMM;
1729                 skip_td = true;
1730                 break;
1731         case COMP_BUFF_OVER:
1732         case COMP_BABBLE:
1733                 frame->status = -EOVERFLOW;
1734                 skip_td = true;
1735                 break;
1736         case COMP_STALL:
1737                 frame->status = -EPROTO;
1738                 skip_td = true;
1739                 break;
1740         case COMP_STOP:
1741         case COMP_STOP_INVAL:
1742                 break;
1743         default:
1744                 frame->status = -1;
1745                 break;
1746         }
1747
1748         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1749                 frame->actual_length = frame->length;
1750                 td->urb->actual_length += frame->length;
1751         } else {
1752                 for (cur_trb = ep_ring->dequeue,
1753                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1754                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1755                         if ((cur_trb->generic.field[3] &
1756                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1757                             (cur_trb->generic.field[3] &
1758                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1759                                 len +=
1760                                     TRB_LEN(cur_trb->generic.field[2]);
1761                 }
1762                 len += TRB_LEN(cur_trb->generic.field[2]) -
1763                         TRB_LEN(event->transfer_len);
1764
1765                 if (trb_comp_code != COMP_STOP_INVAL) {
1766                         frame->actual_length = len;
1767                         td->urb->actual_length += len;
1768                 }
1769         }
1770
1771         if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1772                 *status = 0;
1773
1774         return finish_td(xhci, td, event_trb, event, ep, status, false);
1775 }
1776
1777 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1778                         struct xhci_transfer_event *event,
1779                         struct xhci_virt_ep *ep, int *status)
1780 {
1781         struct xhci_ring *ep_ring;
1782         struct urb_priv *urb_priv;
1783         struct usb_iso_packet_descriptor *frame;
1784         int idx;
1785
1786         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1787         urb_priv = td->urb->hcpriv;
1788         idx = urb_priv->td_cnt;
1789         frame = &td->urb->iso_frame_desc[idx];
1790
1791         /* The transfer is partly done */
1792         *status = -EXDEV;
1793         frame->status = -EXDEV;
1794
1795         /* calc actual length */
1796         frame->actual_length = 0;
1797
1798         /* Update ring dequeue pointer */
1799         while (ep_ring->dequeue != td->last_trb)
1800                 inc_deq(xhci, ep_ring, false);
1801         inc_deq(xhci, ep_ring, false);
1802
1803         return finish_td(xhci, td, NULL, event, ep, status, true);
1804 }
1805
1806 /*
1807  * Process bulk and interrupt tds, update urb status and actual_length.
1808  */
1809 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1810         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1811         struct xhci_virt_ep *ep, int *status)
1812 {
1813         struct xhci_ring *ep_ring;
1814         union xhci_trb *cur_trb;
1815         struct xhci_segment *cur_seg;
1816         u32 trb_comp_code;
1817
1818         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1819         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1820
1821         switch (trb_comp_code) {
1822         case COMP_SUCCESS:
1823                 /* Double check that the HW transferred everything. */
1824                 if (event_trb != td->last_trb) {
1825                         xhci_warn(xhci, "WARN Successful completion "
1826                                         "on short TX\n");
1827                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1828                                 *status = -EREMOTEIO;
1829                         else
1830                                 *status = 0;
1831                 } else {
1832                         if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1833                                 xhci_dbg(xhci, "Successful bulk "
1834                                                 "transfer!\n");
1835                         else
1836                                 xhci_dbg(xhci, "Successful interrupt "
1837                                                 "transfer!\n");
1838                         *status = 0;
1839                 }
1840                 break;
1841         case COMP_SHORT_TX:
1842                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1843                         *status = -EREMOTEIO;
1844                 else
1845                         *status = 0;
1846                 break;
1847         default:
1848                 /* Others already handled above */
1849                 break;
1850         }
1851         xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1852                         "%d bytes untransferred\n",
1853                         td->urb->ep->desc.bEndpointAddress,
1854                         td->urb->transfer_buffer_length,
1855                         TRB_LEN(event->transfer_len));
1856         /* Fast path - was this the last TRB in the TD for this URB? */
1857         if (event_trb == td->last_trb) {
1858                 if (TRB_LEN(event->transfer_len) != 0) {
1859                         td->urb->actual_length =
1860                                 td->urb->transfer_buffer_length -
1861                                 TRB_LEN(event->transfer_len);
1862                         if (td->urb->transfer_buffer_length <
1863                                         td->urb->actual_length) {
1864                                 xhci_warn(xhci, "HC gave bad length "
1865                                                 "of %d bytes left\n",
1866                                                 TRB_LEN(event->transfer_len));
1867                                 td->urb->actual_length = 0;
1868                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1869                                         *status = -EREMOTEIO;
1870                                 else
1871                                         *status = 0;
1872                         }
1873                         /* Don't overwrite a previously set error code */
1874                         if (*status == -EINPROGRESS) {
1875                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1876                                         *status = -EREMOTEIO;
1877                                 else
1878                                         *status = 0;
1879                         }
1880                 } else {
1881                         td->urb->actual_length =
1882                                 td->urb->transfer_buffer_length;
1883                         /* Ignore a short packet completion if the
1884                          * untransferred length was zero.
1885                          */
1886                         if (*status == -EREMOTEIO)
1887                                 *status = 0;
1888                 }
1889         } else {
1890                 /* Slow path - walk the list, starting from the dequeue
1891                  * pointer, to get the actual length transferred.
1892                  */
1893                 td->urb->actual_length = 0;
1894                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1895                                 cur_trb != event_trb;
1896                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1897                         if ((cur_trb->generic.field[3] &
1898                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1899                             (cur_trb->generic.field[3] &
1900                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1901                                 td->urb->actual_length +=
1902                                         TRB_LEN(cur_trb->generic.field[2]);
1903                 }
1904                 /* If the ring didn't stop on a Link or No-op TRB, add
1905                  * in the actual bytes transferred from the Normal TRB
1906                  */
1907                 if (trb_comp_code != COMP_STOP_INVAL)
1908                         td->urb->actual_length +=
1909                                 TRB_LEN(cur_trb->generic.field[2]) -
1910                                 TRB_LEN(event->transfer_len);
1911         }
1912
1913         return finish_td(xhci, td, event_trb, event, ep, status, false);
1914 }
1915
1916 /*
1917  * If this function returns an error condition, it means it got a Transfer
1918  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1919  * At this point, the host controller is probably hosed and should be reset.
1920  */
1921 static int handle_tx_event(struct xhci_hcd *xhci,
1922                 struct xhci_transfer_event *event)
1923 {
1924         struct xhci_virt_device *xdev;
1925         struct xhci_virt_ep *ep;
1926         struct xhci_ring *ep_ring;
1927         unsigned int slot_id;
1928         int ep_index;
1929         struct xhci_td *td = NULL;
1930         dma_addr_t event_dma;
1931         struct xhci_segment *event_seg;
1932         union xhci_trb *event_trb;
1933         struct urb *urb = NULL;
1934         int status = -EINPROGRESS;
1935         struct urb_priv *urb_priv;
1936         struct xhci_ep_ctx *ep_ctx;
1937         u32 trb_comp_code;
1938         int ret = 0;
1939
1940         slot_id = TRB_TO_SLOT_ID(event->flags);
1941         xdev = xhci->devs[slot_id];
1942         if (!xdev) {
1943                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1944                 return -ENODEV;
1945         }
1946
1947         /* Endpoint ID is 1 based, our index is zero based */
1948         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1949         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1950         ep = &xdev->eps[ep_index];
1951         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1952         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1953         if (!ep_ring ||
1954                 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1955                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1956                                 "or incorrect stream ring\n");
1957                 return -ENODEV;
1958         }
1959
1960         event_dma = event->buffer;
1961         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1962         /* Look for common error cases */
1963         switch (trb_comp_code) {
1964         /* Skip codes that require special handling depending on
1965          * transfer type
1966          */
1967         case COMP_SUCCESS:
1968         case COMP_SHORT_TX:
1969                 break;
1970         case COMP_STOP:
1971                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1972                 break;
1973         case COMP_STOP_INVAL:
1974                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1975                 break;
1976         case COMP_STALL:
1977                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1978                 ep->ep_state |= EP_HALTED;
1979                 status = -EPIPE;
1980                 break;
1981         case COMP_TRB_ERR:
1982                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1983                 status = -EILSEQ;
1984                 break;
1985         case COMP_SPLIT_ERR:
1986         case COMP_TX_ERR:
1987                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1988                 status = -EPROTO;
1989                 break;
1990         case COMP_BABBLE:
1991                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1992                 status = -EOVERFLOW;
1993                 break;
1994         case COMP_DB_ERR:
1995                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1996                 status = -ENOSR;
1997                 break;
1998         case COMP_BW_OVER:
1999                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2000                 break;
2001         case COMP_BUFF_OVER:
2002                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2003                 break;
2004         case COMP_UNDERRUN:
2005                 /*
2006                  * When the Isoch ring is empty, the xHC will generate
2007                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2008                  * Underrun Event for OUT Isoch endpoint.
2009                  */
2010                 xhci_dbg(xhci, "underrun event on endpoint\n");
2011                 if (!list_empty(&ep_ring->td_list))
2012                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2013                                         "still with TDs queued?\n",
2014                                 TRB_TO_SLOT_ID(event->flags), ep_index);
2015                 goto cleanup;
2016         case COMP_OVERRUN:
2017                 xhci_dbg(xhci, "overrun event on endpoint\n");
2018                 if (!list_empty(&ep_ring->td_list))
2019                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2020                                         "still with TDs queued?\n",
2021                                 TRB_TO_SLOT_ID(event->flags), ep_index);
2022                 goto cleanup;
2023         case COMP_MISSED_INT:
2024                 /*
2025                  * When encounter missed service error, one or more isoc tds
2026                  * may be missed by xHC.
2027                  * Set skip flag of the ep_ring; Complete the missed tds as
2028                  * short transfer when process the ep_ring next time.
2029                  */
2030                 ep->skip = true;
2031                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2032                 goto cleanup;
2033         default:
2034                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2035                         status = 0;
2036                         break;
2037                 }
2038                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2039                                 "busted\n");
2040                 goto cleanup;
2041         }
2042
2043         do {
2044                 /* This TRB should be in the TD at the head of this ring's
2045                  * TD list.
2046                  */
2047                 if (list_empty(&ep_ring->td_list)) {
2048                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2049                                         "with no TDs queued?\n",
2050                                   TRB_TO_SLOT_ID(event->flags), ep_index);
2051                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2052                           (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
2053                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2054                         if (ep->skip) {
2055                                 ep->skip = false;
2056                                 xhci_dbg(xhci, "td_list is empty while skip "
2057                                                 "flag set. Clear skip flag.\n");
2058                         }
2059                         ret = 0;
2060                         goto cleanup;
2061                 }
2062
2063                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2064
2065                 /* Is this a TRB in the currently executing TD? */
2066                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2067                                 td->last_trb, event_dma);
2068                 if (!event_seg) {
2069                         if (!ep->skip ||
2070                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2071                                 /* HC is busted, give up! */
2072                                 xhci_err(xhci,
2073                                         "ERROR Transfer event TRB DMA ptr not "
2074                                         "part of current TD\n");
2075                                 return -ESHUTDOWN;
2076                         }
2077
2078                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2079                         goto cleanup;
2080                 }
2081
2082                 if (ep->skip) {
2083                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2084                         ep->skip = false;
2085                 }
2086
2087                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2088                                                 sizeof(*event_trb)];
2089                 /*
2090                  * No-op TRB should not trigger interrupts.
2091                  * If event_trb is a no-op TRB, it means the
2092                  * corresponding TD has been cancelled. Just ignore
2093                  * the TD.
2094                  */
2095                 if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
2096                                  == TRB_TYPE(TRB_TR_NOOP)) {
2097                         xhci_dbg(xhci,
2098                                  "event_trb is a no-op TRB. Skip it\n");
2099                         goto cleanup;
2100                 }
2101
2102                 /* Now update the urb's actual_length and give back to
2103                  * the core
2104                  */
2105                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2106                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2107                                                  &status);
2108                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2109                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2110                                                  &status);
2111                 else
2112                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2113                                                  ep, &status);
2114
2115 cleanup:
2116                 /*
2117                  * Do not update event ring dequeue pointer if ep->skip is set.
2118                  * Will roll back to continue process missed tds.
2119                  */
2120                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2121                         inc_deq(xhci, xhci->event_ring, true);
2122                 }
2123
2124                 if (ret) {
2125                         urb = td->urb;
2126                         urb_priv = urb->hcpriv;
2127                         /* Leave the TD around for the reset endpoint function
2128                          * to use(but only if it's not a control endpoint,
2129                          * since we already queued the Set TR dequeue pointer
2130                          * command for stalled control endpoints).
2131                          */
2132                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2133                                 (trb_comp_code != COMP_STALL &&
2134                                         trb_comp_code != COMP_BABBLE))
2135                                 xhci_urb_free_priv(xhci, urb_priv);
2136
2137                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2138                         xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2139                                         "status = %d\n",
2140                                         urb, urb->actual_length, status);
2141                         spin_unlock(&xhci->lock);
2142                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2143                         spin_lock(&xhci->lock);
2144                 }
2145
2146         /*
2147          * If ep->skip is set, it means there are missed tds on the
2148          * endpoint ring need to take care of.
2149          * Process them as short transfer until reach the td pointed by
2150          * the event.
2151          */
2152         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2153
2154         return 0;
2155 }
2156
2157 /*
2158  * This function handles all OS-owned events on the event ring.  It may drop
2159  * xhci->lock between event processing (e.g. to pass up port status changes).
2160  */
2161 static void xhci_handle_event(struct xhci_hcd *xhci)
2162 {
2163         union xhci_trb *event;
2164         int update_ptrs = 1;
2165         int ret;
2166
2167         xhci_dbg(xhci, "In %s\n", __func__);
2168         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2169                 xhci->error_bitmask |= 1 << 1;
2170                 return;
2171         }
2172
2173         event = xhci->event_ring->dequeue;
2174         /* Does the HC or OS own the TRB? */
2175         if ((event->event_cmd.flags & TRB_CYCLE) !=
2176                         xhci->event_ring->cycle_state) {
2177                 xhci->error_bitmask |= 1 << 2;
2178                 return;
2179         }
2180         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
2181
2182         /* FIXME: Handle more event types. */
2183         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
2184         case TRB_TYPE(TRB_COMPLETION):
2185                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
2186                 handle_cmd_completion(xhci, &event->event_cmd);
2187                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
2188                 break;
2189         case TRB_TYPE(TRB_PORT_STATUS):
2190                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
2191                 handle_port_status(xhci, event);
2192                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
2193                 update_ptrs = 0;
2194                 break;
2195         case TRB_TYPE(TRB_TRANSFER):
2196                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
2197                 ret = handle_tx_event(xhci, &event->trans_event);
2198                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
2199                 if (ret < 0)
2200                         xhci->error_bitmask |= 1 << 9;
2201                 else
2202                         update_ptrs = 0;
2203                 break;
2204         default:
2205                 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
2206                         handle_vendor_event(xhci, event);
2207                 else
2208                         xhci->error_bitmask |= 1 << 3;
2209         }
2210         /* Any of the above functions may drop and re-acquire the lock, so check
2211          * to make sure a watchdog timer didn't mark the host as non-responsive.
2212          */
2213         if (xhci->xhc_state & XHCI_STATE_DYING) {
2214                 xhci_dbg(xhci, "xHCI host dying, returning from "
2215                                 "event handler.\n");
2216                 return;
2217         }
2218
2219         if (update_ptrs)
2220                 /* Update SW event ring dequeue pointer */
2221                 inc_deq(xhci, xhci->event_ring, true);
2222
2223         /* Are there more items on the event ring? */
2224         xhci_handle_event(xhci);
2225 }
2226
2227 /*
2228  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2229  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2230  * indicators of an event TRB error, but we check the status *first* to be safe.
2231  */
2232 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2233 {
2234         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2235         u32 status;
2236         union xhci_trb *trb;
2237         u64 temp_64;
2238         union xhci_trb *event_ring_deq;
2239         dma_addr_t deq;
2240
2241         spin_lock(&xhci->lock);
2242         trb = xhci->event_ring->dequeue;
2243         /* Check if the xHC generated the interrupt, or the irq is shared */
2244         status = xhci_readl(xhci, &xhci->op_regs->status);
2245         if (status == 0xffffffff)
2246                 goto hw_died;
2247
2248         if (!(status & STS_EINT)) {
2249                 spin_unlock(&xhci->lock);
2250                 return IRQ_NONE;
2251         }
2252         xhci_dbg(xhci, "op reg status = %08x\n", status);
2253         xhci_dbg(xhci, "Event ring dequeue ptr:\n");
2254         xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
2255                         (unsigned long long)
2256                         xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
2257                         lower_32_bits(trb->link.segment_ptr),
2258                         upper_32_bits(trb->link.segment_ptr),
2259                         (unsigned int) trb->link.intr_target,
2260                         (unsigned int) trb->link.control);
2261
2262         if (status & STS_FATAL) {
2263                 xhci_warn(xhci, "WARNING: Host System Error\n");
2264                 xhci_halt(xhci);
2265 hw_died:
2266                 spin_unlock(&xhci->lock);
2267                 return -ESHUTDOWN;
2268         }
2269
2270         /*
2271          * Clear the op reg interrupt status first,
2272          * so we can receive interrupts from other MSI-X interrupters.
2273          * Write 1 to clear the interrupt status.
2274          */
2275         status |= STS_EINT;
2276         xhci_writel(xhci, status, &xhci->op_regs->status);
2277         /* FIXME when MSI-X is supported and there are multiple vectors */
2278         /* Clear the MSI-X event interrupt status */
2279
2280         if (hcd->irq != -1) {
2281                 u32 irq_pending;
2282                 /* Acknowledge the PCI interrupt */
2283                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2284                 irq_pending |= 0x3;
2285                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2286         }
2287
2288         if (xhci->xhc_state & XHCI_STATE_DYING) {
2289                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2290                                 "Shouldn't IRQs be disabled?\n");
2291                 /* Clear the event handler busy flag (RW1C);
2292                  * the event ring should be empty.
2293                  */
2294                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2295                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2296                                 &xhci->ir_set->erst_dequeue);
2297                 spin_unlock(&xhci->lock);
2298
2299                 return IRQ_HANDLED;
2300         }
2301
2302         event_ring_deq = xhci->event_ring->dequeue;
2303         /* FIXME this should be a delayed service routine
2304          * that clears the EHB.
2305          */
2306         xhci_handle_event(xhci);
2307
2308         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2309         /* If necessary, update the HW's version of the event ring deq ptr. */
2310         if (event_ring_deq != xhci->event_ring->dequeue) {
2311                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2312                                 xhci->event_ring->dequeue);
2313                 if (deq == 0)
2314                         xhci_warn(xhci, "WARN something wrong with SW event "
2315                                         "ring dequeue ptr.\n");
2316                 /* Update HC event ring dequeue pointer */
2317                 temp_64 &= ERST_PTR_MASK;
2318                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2319         }
2320
2321         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2322         temp_64 |= ERST_EHB;
2323         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2324
2325         spin_unlock(&xhci->lock);
2326
2327         return IRQ_HANDLED;
2328 }
2329
2330 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2331 {
2332         irqreturn_t ret;
2333         struct xhci_hcd *xhci;
2334
2335         xhci = hcd_to_xhci(hcd);
2336         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2337         if (xhci->shared_hcd)
2338                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2339
2340         ret = xhci_irq(hcd);
2341
2342         return ret;
2343 }
2344
2345 /****           Endpoint Ring Operations        ****/
2346
2347 /*
2348  * Generic function for queueing a TRB on a ring.
2349  * The caller must have checked to make sure there's room on the ring.
2350  *
2351  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2352  *                      prepare_transfer()?
2353  */
2354 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2355                 bool consumer, bool more_trbs_coming,
2356                 u32 field1, u32 field2, u32 field3, u32 field4)
2357 {
2358         struct xhci_generic_trb *trb;
2359
2360         trb = &ring->enqueue->generic;
2361         trb->field[0] = field1;
2362         trb->field[1] = field2;
2363         trb->field[2] = field3;
2364         trb->field[3] = field4;
2365         inc_enq(xhci, ring, consumer, more_trbs_coming);
2366 }
2367
2368 /*
2369  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2370  * FIXME allocate segments if the ring is full.
2371  */
2372 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2373                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2374 {
2375         /* Make sure the endpoint has been added to xHC schedule */
2376         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2377         switch (ep_state) {
2378         case EP_STATE_DISABLED:
2379                 /*
2380                  * USB core changed config/interfaces without notifying us,
2381                  * or hardware is reporting the wrong state.
2382                  */
2383                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2384                 return -ENOENT;
2385         case EP_STATE_ERROR:
2386                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2387                 /* FIXME event handling code for error needs to clear it */
2388                 /* XXX not sure if this should be -ENOENT or not */
2389                 return -EINVAL;
2390         case EP_STATE_HALTED:
2391                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2392         case EP_STATE_STOPPED:
2393         case EP_STATE_RUNNING:
2394                 break;
2395         default:
2396                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2397                 /*
2398                  * FIXME issue Configure Endpoint command to try to get the HC
2399                  * back into a known state.
2400                  */
2401                 return -EINVAL;
2402         }
2403         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2404                 /* FIXME allocate more room */
2405                 xhci_err(xhci, "ERROR no room on ep ring\n");
2406                 return -ENOMEM;
2407         }
2408
2409         if (enqueue_is_link_trb(ep_ring)) {
2410                 struct xhci_ring *ring = ep_ring;
2411                 union xhci_trb *next;
2412
2413                 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2414                 next = ring->enqueue;
2415
2416                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2417
2418                         /* If we're not dealing with 0.95 hardware,
2419                          * clear the chain bit.
2420                          */
2421                         if (!xhci_link_trb_quirk(xhci))
2422                                 next->link.control &= ~TRB_CHAIN;
2423                         else
2424                                 next->link.control |= TRB_CHAIN;
2425
2426                         wmb();
2427                         next->link.control ^= (u32) TRB_CYCLE;
2428
2429                         /* Toggle the cycle bit after the last ring segment. */
2430                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2431                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2432                                 if (!in_interrupt()) {
2433                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2434                                                 "state for ring %p = %i\n",
2435                                                 ring, (unsigned int)ring->cycle_state);
2436                                 }
2437                         }
2438                         ring->enq_seg = ring->enq_seg->next;
2439                         ring->enqueue = ring->enq_seg->trbs;
2440                         next = ring->enqueue;
2441                 }
2442         }
2443
2444         return 0;
2445 }
2446
2447 static int prepare_transfer(struct xhci_hcd *xhci,
2448                 struct xhci_virt_device *xdev,
2449                 unsigned int ep_index,
2450                 unsigned int stream_id,
2451                 unsigned int num_trbs,
2452                 struct urb *urb,
2453                 unsigned int td_index,
2454                 gfp_t mem_flags)
2455 {
2456         int ret;
2457         struct urb_priv *urb_priv;
2458         struct xhci_td  *td;
2459         struct xhci_ring *ep_ring;
2460         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2461
2462         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2463         if (!ep_ring) {
2464                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2465                                 stream_id);
2466                 return -EINVAL;
2467         }
2468
2469         ret = prepare_ring(xhci, ep_ring,
2470                         ep_ctx->ep_info & EP_STATE_MASK,
2471                         num_trbs, mem_flags);
2472         if (ret)
2473                 return ret;
2474
2475         urb_priv = urb->hcpriv;
2476         td = urb_priv->td[td_index];
2477
2478         INIT_LIST_HEAD(&td->td_list);
2479         INIT_LIST_HEAD(&td->cancelled_td_list);
2480
2481         if (td_index == 0) {
2482                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2483                 if (unlikely(ret)) {
2484                         xhci_urb_free_priv(xhci, urb_priv);
2485                         urb->hcpriv = NULL;
2486                         return ret;
2487                 }
2488         }
2489
2490         td->urb = urb;
2491         /* Add this TD to the tail of the endpoint ring's TD list */
2492         list_add_tail(&td->td_list, &ep_ring->td_list);
2493         td->start_seg = ep_ring->enq_seg;
2494         td->first_trb = ep_ring->enqueue;
2495
2496         urb_priv->td[td_index] = td;
2497
2498         return 0;
2499 }
2500
2501 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2502 {
2503         int num_sgs, num_trbs, running_total, temp, i;
2504         struct scatterlist *sg;
2505
2506         sg = NULL;
2507         num_sgs = urb->num_sgs;
2508         temp = urb->transfer_buffer_length;
2509
2510         xhci_dbg(xhci, "count sg list trbs: \n");
2511         num_trbs = 0;
2512         for_each_sg(urb->sg, sg, num_sgs, i) {
2513                 unsigned int previous_total_trbs = num_trbs;
2514                 unsigned int len = sg_dma_len(sg);
2515
2516                 /* Scatter gather list entries may cross 64KB boundaries */
2517                 running_total = TRB_MAX_BUFF_SIZE -
2518                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2519                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2520                 if (running_total != 0)
2521                         num_trbs++;
2522
2523                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2524                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2525                         num_trbs++;
2526                         running_total += TRB_MAX_BUFF_SIZE;
2527                 }
2528                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2529                                 i, (unsigned long long)sg_dma_address(sg),
2530                                 len, len, num_trbs - previous_total_trbs);
2531
2532                 len = min_t(int, len, temp);
2533                 temp -= len;
2534                 if (temp == 0)
2535                         break;
2536         }
2537         xhci_dbg(xhci, "\n");
2538         if (!in_interrupt())
2539                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2540                                 "num_trbs = %d\n",
2541                                 urb->ep->desc.bEndpointAddress,
2542                                 urb->transfer_buffer_length,
2543                                 num_trbs);
2544         return num_trbs;
2545 }
2546
2547 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2548 {
2549         if (num_trbs != 0)
2550                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2551                                 "TRBs, %d left\n", __func__,
2552                                 urb->ep->desc.bEndpointAddress, num_trbs);
2553         if (running_total != urb->transfer_buffer_length)
2554                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2555                                 "queued %#x (%d), asked for %#x (%d)\n",
2556                                 __func__,
2557                                 urb->ep->desc.bEndpointAddress,
2558                                 running_total, running_total,
2559                                 urb->transfer_buffer_length,
2560                                 urb->transfer_buffer_length);
2561 }
2562
2563 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2564                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2565                 struct xhci_generic_trb *start_trb)
2566 {
2567         /*
2568          * Pass all the TRBs to the hardware at once and make sure this write
2569          * isn't reordered.
2570          */
2571         wmb();
2572         if (start_cycle)
2573                 start_trb->field[3] |= start_cycle;
2574         else
2575                 start_trb->field[3] &= ~0x1;
2576         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2577 }
2578
2579 /*
2580  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2581  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2582  * (comprised of sg list entries) can take several service intervals to
2583  * transmit.
2584  */
2585 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2586                 struct urb *urb, int slot_id, unsigned int ep_index)
2587 {
2588         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2589                         xhci->devs[slot_id]->out_ctx, ep_index);
2590         int xhci_interval;
2591         int ep_interval;
2592
2593         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2594         ep_interval = urb->interval;
2595         /* Convert to microframes */
2596         if (urb->dev->speed == USB_SPEED_LOW ||
2597                         urb->dev->speed == USB_SPEED_FULL)
2598                 ep_interval *= 8;
2599         /* FIXME change this to a warning and a suggestion to use the new API
2600          * to set the polling interval (once the API is added).
2601          */
2602         if (xhci_interval != ep_interval) {
2603                 if (printk_ratelimit())
2604                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2605                                         " (%d microframe%s) than xHCI "
2606                                         "(%d microframe%s)\n",
2607                                         ep_interval,
2608                                         ep_interval == 1 ? "" : "s",
2609                                         xhci_interval,
2610                                         xhci_interval == 1 ? "" : "s");
2611                 urb->interval = xhci_interval;
2612                 /* Convert back to frames for LS/FS devices */
2613                 if (urb->dev->speed == USB_SPEED_LOW ||
2614                                 urb->dev->speed == USB_SPEED_FULL)
2615                         urb->interval /= 8;
2616         }
2617         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2618 }
2619
2620 /*
2621  * The TD size is the number of bytes remaining in the TD (including this TRB),
2622  * right shifted by 10.
2623  * It must fit in bits 21:17, so it can't be bigger than 31.
2624  */
2625 static u32 xhci_td_remainder(unsigned int remainder)
2626 {
2627         u32 max = (1 << (21 - 17 + 1)) - 1;
2628
2629         if ((remainder >> 10) >= max)
2630                 return max << 17;
2631         else
2632                 return (remainder >> 10) << 17;
2633 }
2634
2635 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2636                 struct urb *urb, int slot_id, unsigned int ep_index)
2637 {
2638         struct xhci_ring *ep_ring;
2639         unsigned int num_trbs;
2640         struct urb_priv *urb_priv;
2641         struct xhci_td *td;
2642         struct scatterlist *sg;
2643         int num_sgs;
2644         int trb_buff_len, this_sg_len, running_total;
2645         bool first_trb;
2646         u64 addr;
2647         bool more_trbs_coming;
2648
2649         struct xhci_generic_trb *start_trb;
2650         int start_cycle;
2651
2652         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2653         if (!ep_ring)
2654                 return -EINVAL;
2655
2656         num_trbs = count_sg_trbs_needed(xhci, urb);
2657         num_sgs = urb->num_sgs;
2658
2659         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2660                         ep_index, urb->stream_id,
2661                         num_trbs, urb, 0, mem_flags);
2662         if (trb_buff_len < 0)
2663                 return trb_buff_len;
2664
2665         urb_priv = urb->hcpriv;
2666         td = urb_priv->td[0];
2667
2668         /*
2669          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2670          * until we've finished creating all the other TRBs.  The ring's cycle
2671          * state may change as we enqueue the other TRBs, so save it too.
2672          */
2673         start_trb = &ep_ring->enqueue->generic;
2674         start_cycle = ep_ring->cycle_state;
2675
2676         running_total = 0;
2677         /*
2678          * How much data is in the first TRB?
2679          *
2680          * There are three forces at work for TRB buffer pointers and lengths:
2681          * 1. We don't want to walk off the end of this sg-list entry buffer.
2682          * 2. The transfer length that the driver requested may be smaller than
2683          *    the amount of memory allocated for this scatter-gather list.
2684          * 3. TRBs buffers can't cross 64KB boundaries.
2685          */
2686         sg = urb->sg;
2687         addr = (u64) sg_dma_address(sg);
2688         this_sg_len = sg_dma_len(sg);
2689         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2690         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2691         if (trb_buff_len > urb->transfer_buffer_length)
2692                 trb_buff_len = urb->transfer_buffer_length;
2693         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2694                         trb_buff_len);
2695
2696         first_trb = true;
2697         /* Queue the first TRB, even if it's zero-length */
2698         do {
2699                 u32 field = 0;
2700                 u32 length_field = 0;
2701                 u32 remainder = 0;
2702
2703                 /* Don't change the cycle bit of the first TRB until later */
2704                 if (first_trb) {
2705                         first_trb = false;
2706                         if (start_cycle == 0)
2707                                 field |= 0x1;
2708                 } else
2709                         field |= ep_ring->cycle_state;
2710
2711                 /* Chain all the TRBs together; clear the chain bit in the last
2712                  * TRB to indicate it's the last TRB in the chain.
2713                  */
2714                 if (num_trbs > 1) {
2715                         field |= TRB_CHAIN;
2716                 } else {
2717                         /* FIXME - add check for ZERO_PACKET flag before this */
2718                         td->last_trb = ep_ring->enqueue;
2719                         field |= TRB_IOC;
2720                 }
2721                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2722                                 "64KB boundary at %#x, end dma = %#x\n",
2723                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2724                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2725                                 (unsigned int) addr + trb_buff_len);
2726                 if (TRB_MAX_BUFF_SIZE -
2727                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2728                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2729                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2730                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2731                                         (unsigned int) addr + trb_buff_len);
2732                 }
2733                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2734                                 running_total) ;
2735                 length_field = TRB_LEN(trb_buff_len) |
2736                         remainder |
2737                         TRB_INTR_TARGET(0);
2738                 if (num_trbs > 1)
2739                         more_trbs_coming = true;
2740                 else
2741                         more_trbs_coming = false;
2742                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2743                                 lower_32_bits(addr),
2744                                 upper_32_bits(addr),
2745                                 length_field,
2746                                 /* We always want to know if the TRB was short,
2747                                  * or we won't get an event when it completes.
2748                                  * (Unless we use event data TRBs, which are a
2749                                  * waste of space and HC resources.)
2750                                  */
2751                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2752                 --num_trbs;
2753                 running_total += trb_buff_len;
2754
2755                 /* Calculate length for next transfer --
2756                  * Are we done queueing all the TRBs for this sg entry?
2757                  */
2758                 this_sg_len -= trb_buff_len;
2759                 if (this_sg_len == 0) {
2760                         --num_sgs;
2761                         if (num_sgs == 0)
2762                                 break;
2763                         sg = sg_next(sg);
2764                         addr = (u64) sg_dma_address(sg);
2765                         this_sg_len = sg_dma_len(sg);
2766                 } else {
2767                         addr += trb_buff_len;
2768                 }
2769
2770                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2771                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2772                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2773                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2774                         trb_buff_len =
2775                                 urb->transfer_buffer_length - running_total;
2776         } while (running_total < urb->transfer_buffer_length);
2777
2778         check_trb_math(urb, num_trbs, running_total);
2779         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2780                         start_cycle, start_trb);
2781         return 0;
2782 }
2783
2784 /* This is very similar to what ehci-q.c qtd_fill() does */
2785 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2786                 struct urb *urb, int slot_id, unsigned int ep_index)
2787 {
2788         struct xhci_ring *ep_ring;
2789         struct urb_priv *urb_priv;
2790         struct xhci_td *td;
2791         int num_trbs;
2792         struct xhci_generic_trb *start_trb;
2793         bool first_trb;
2794         bool more_trbs_coming;
2795         int start_cycle;
2796         u32 field, length_field;
2797
2798         int running_total, trb_buff_len, ret;
2799         u64 addr;
2800
2801         if (urb->num_sgs)
2802                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2803
2804         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2805         if (!ep_ring)
2806                 return -EINVAL;
2807
2808         num_trbs = 0;
2809         /* How much data is (potentially) left before the 64KB boundary? */
2810         running_total = TRB_MAX_BUFF_SIZE -
2811                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2812         running_total &= TRB_MAX_BUFF_SIZE - 1;
2813
2814         /* If there's some data on this 64KB chunk, or we have to send a
2815          * zero-length transfer, we need at least one TRB
2816          */
2817         if (running_total != 0 || urb->transfer_buffer_length == 0)
2818                 num_trbs++;
2819         /* How many more 64KB chunks to transfer, how many more TRBs? */
2820         while (running_total < urb->transfer_buffer_length) {
2821                 num_trbs++;
2822                 running_total += TRB_MAX_BUFF_SIZE;
2823         }
2824         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2825
2826         if (!in_interrupt())
2827                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2828                                 "addr = %#llx, num_trbs = %d\n",
2829                                 urb->ep->desc.bEndpointAddress,
2830                                 urb->transfer_buffer_length,
2831                                 urb->transfer_buffer_length,
2832                                 (unsigned long long)urb->transfer_dma,
2833                                 num_trbs);
2834
2835         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2836                         ep_index, urb->stream_id,
2837                         num_trbs, urb, 0, mem_flags);
2838         if (ret < 0)
2839                 return ret;
2840
2841         urb_priv = urb->hcpriv;
2842         td = urb_priv->td[0];
2843
2844         /*
2845          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2846          * until we've finished creating all the other TRBs.  The ring's cycle
2847          * state may change as we enqueue the other TRBs, so save it too.
2848          */
2849         start_trb = &ep_ring->enqueue->generic;
2850         start_cycle = ep_ring->cycle_state;
2851
2852         running_total = 0;
2853         /* How much data is in the first TRB? */
2854         addr = (u64) urb->transfer_dma;
2855         trb_buff_len = TRB_MAX_BUFF_SIZE -
2856                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2857         if (trb_buff_len > urb->transfer_buffer_length)
2858                 trb_buff_len = urb->transfer_buffer_length;
2859
2860         first_trb = true;
2861
2862         /* Queue the first TRB, even if it's zero-length */
2863         do {
2864                 u32 remainder = 0;
2865                 field = 0;
2866
2867                 /* Don't change the cycle bit of the first TRB until later */
2868                 if (first_trb) {
2869                         first_trb = false;
2870                         if (start_cycle == 0)
2871                                 field |= 0x1;
2872                 } else
2873                         field |= ep_ring->cycle_state;
2874
2875                 /* Chain all the TRBs together; clear the chain bit in the last
2876                  * TRB to indicate it's the last TRB in the chain.
2877                  */
2878                 if (num_trbs > 1) {
2879                         field |= TRB_CHAIN;
2880                 } else {
2881                         /* FIXME - add check for ZERO_PACKET flag before this */
2882                         td->last_trb = ep_ring->enqueue;
2883                         field |= TRB_IOC;
2884                 }
2885                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2886                                 running_total);
2887                 length_field = TRB_LEN(trb_buff_len) |
2888                         remainder |
2889                         TRB_INTR_TARGET(0);
2890                 if (num_trbs > 1)
2891                         more_trbs_coming = true;
2892                 else
2893                         more_trbs_coming = false;
2894                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2895                                 lower_32_bits(addr),
2896                                 upper_32_bits(addr),
2897                                 length_field,
2898                                 /* We always want to know if the TRB was short,
2899                                  * or we won't get an event when it completes.
2900                                  * (Unless we use event data TRBs, which are a
2901                                  * waste of space and HC resources.)
2902                                  */
2903                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2904                 --num_trbs;
2905                 running_total += trb_buff_len;
2906
2907                 /* Calculate length for next transfer */
2908                 addr += trb_buff_len;
2909                 trb_buff_len = urb->transfer_buffer_length - running_total;
2910                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2911                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2912         } while (running_total < urb->transfer_buffer_length);
2913
2914         check_trb_math(urb, num_trbs, running_total);
2915         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2916                         start_cycle, start_trb);
2917         return 0;
2918 }
2919
2920 /* Caller must have locked xhci->lock */
2921 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2922                 struct urb *urb, int slot_id, unsigned int ep_index)
2923 {
2924         struct xhci_ring *ep_ring;
2925         int num_trbs;
2926         int ret;
2927         struct usb_ctrlrequest *setup;
2928         struct xhci_generic_trb *start_trb;
2929         int start_cycle;
2930         u32 field, length_field;
2931         struct urb_priv *urb_priv;
2932         struct xhci_td *td;
2933
2934         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2935         if (!ep_ring)
2936                 return -EINVAL;
2937
2938         /*
2939          * Need to copy setup packet into setup TRB, so we can't use the setup
2940          * DMA address.
2941          */
2942         if (!urb->setup_packet)
2943                 return -EINVAL;
2944
2945         if (!in_interrupt())
2946                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2947                                 slot_id, ep_index);
2948         /* 1 TRB for setup, 1 for status */
2949         num_trbs = 2;
2950         /*
2951          * Don't need to check if we need additional event data and normal TRBs,
2952          * since data in control transfers will never get bigger than 16MB
2953          * XXX: can we get a buffer that crosses 64KB boundaries?
2954          */
2955         if (urb->transfer_buffer_length > 0)
2956                 num_trbs++;
2957         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2958                         ep_index, urb->stream_id,
2959                         num_trbs, urb, 0, mem_flags);
2960         if (ret < 0)
2961                 return ret;
2962
2963         urb_priv = urb->hcpriv;
2964         td = urb_priv->td[0];
2965
2966         /*
2967          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2968          * until we've finished creating all the other TRBs.  The ring's cycle
2969          * state may change as we enqueue the other TRBs, so save it too.
2970          */
2971         start_trb = &ep_ring->enqueue->generic;
2972         start_cycle = ep_ring->cycle_state;
2973
2974         /* Queue setup TRB - see section 6.4.1.2.1 */
2975         /* FIXME better way to translate setup_packet into two u32 fields? */
2976         setup = (struct usb_ctrlrequest *) urb->setup_packet;
2977         field = 0;
2978         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
2979         if (start_cycle == 0)
2980                 field |= 0x1;
2981         queue_trb(xhci, ep_ring, false, true,
2982                         /* FIXME endianness is probably going to bite my ass here. */
2983                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2984                         setup->wIndex | setup->wLength << 16,
2985                         TRB_LEN(8) | TRB_INTR_TARGET(0),
2986                         /* Immediate data in pointer */
2987                         field);
2988
2989         /* If there's data, queue data TRBs */
2990         field = 0;
2991         length_field = TRB_LEN(urb->transfer_buffer_length) |
2992                 xhci_td_remainder(urb->transfer_buffer_length) |
2993                 TRB_INTR_TARGET(0);
2994         if (urb->transfer_buffer_length > 0) {
2995                 if (setup->bRequestType & USB_DIR_IN)
2996                         field |= TRB_DIR_IN;
2997                 queue_trb(xhci, ep_ring, false, true,
2998                                 lower_32_bits(urb->transfer_dma),
2999                                 upper_32_bits(urb->transfer_dma),
3000                                 length_field,
3001                                 /* Event on short tx */
3002                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
3003         }
3004
3005         /* Save the DMA address of the last TRB in the TD */
3006         td->last_trb = ep_ring->enqueue;
3007
3008         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3009         /* If the device sent data, the status stage is an OUT transfer */
3010         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3011                 field = 0;
3012         else
3013                 field = TRB_DIR_IN;
3014         queue_trb(xhci, ep_ring, false, false,
3015                         0,
3016                         0,
3017                         TRB_INTR_TARGET(0),
3018                         /* Event on completion */
3019                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3020
3021         giveback_first_trb(xhci, slot_id, ep_index, 0,
3022                         start_cycle, start_trb);
3023         return 0;
3024 }
3025
3026 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3027                 struct urb *urb, int i)
3028 {
3029         int num_trbs = 0;
3030         u64 addr, td_len, running_total;
3031
3032         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3033         td_len = urb->iso_frame_desc[i].length;
3034
3035         running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3036         running_total &= TRB_MAX_BUFF_SIZE - 1;
3037         if (running_total != 0)
3038                 num_trbs++;
3039
3040         while (running_total < td_len) {
3041                 num_trbs++;
3042                 running_total += TRB_MAX_BUFF_SIZE;
3043         }
3044
3045         return num_trbs;
3046 }
3047
3048 /* This is for isoc transfer */
3049 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3050                 struct urb *urb, int slot_id, unsigned int ep_index)
3051 {
3052         struct xhci_ring *ep_ring;
3053         struct urb_priv *urb_priv;
3054         struct xhci_td *td;
3055         int num_tds, trbs_per_td;
3056         struct xhci_generic_trb *start_trb;
3057         bool first_trb;
3058         int start_cycle;
3059         u32 field, length_field;
3060         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3061         u64 start_addr, addr;
3062         int i, j;
3063         bool more_trbs_coming;
3064
3065         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3066
3067         num_tds = urb->number_of_packets;
3068         if (num_tds < 1) {
3069                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3070                 return -EINVAL;
3071         }
3072
3073         if (!in_interrupt())
3074                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3075                                 " addr = %#llx, num_tds = %d\n",
3076                                 urb->ep->desc.bEndpointAddress,
3077                                 urb->transfer_buffer_length,
3078                                 urb->transfer_buffer_length,
3079                                 (unsigned long long)urb->transfer_dma,
3080                                 num_tds);
3081
3082         start_addr = (u64) urb->transfer_dma;
3083         start_trb = &ep_ring->enqueue->generic;
3084         start_cycle = ep_ring->cycle_state;
3085
3086         /* Queue the first TRB, even if it's zero-length */
3087         for (i = 0; i < num_tds; i++) {
3088                 first_trb = true;
3089
3090                 running_total = 0;
3091                 addr = start_addr + urb->iso_frame_desc[i].offset;
3092                 td_len = urb->iso_frame_desc[i].length;
3093                 td_remain_len = td_len;
3094
3095                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3096
3097                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3098                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3099                 if (ret < 0)
3100                         return ret;
3101
3102                 urb_priv = urb->hcpriv;
3103                 td = urb_priv->td[i];
3104
3105                 for (j = 0; j < trbs_per_td; j++) {
3106                         u32 remainder = 0;
3107                         field = 0;
3108
3109                         if (first_trb) {
3110                                 /* Queue the isoc TRB */
3111                                 field |= TRB_TYPE(TRB_ISOC);
3112                                 /* Assume URB_ISO_ASAP is set */
3113                                 field |= TRB_SIA;
3114                                 if (i == 0) {
3115                                         if (start_cycle == 0)
3116                                                 field |= 0x1;
3117                                 } else
3118                                         field |= ep_ring->cycle_state;
3119                                 first_trb = false;
3120                         } else {
3121                                 /* Queue other normal TRBs */
3122                                 field |= TRB_TYPE(TRB_NORMAL);
3123                                 field |= ep_ring->cycle_state;
3124                         }
3125
3126                         /* Chain all the TRBs together; clear the chain bit in
3127                          * the last TRB to indicate it's the last TRB in the
3128                          * chain.
3129                          */
3130                         if (j < trbs_per_td - 1) {
3131                                 field |= TRB_CHAIN;
3132                                 more_trbs_coming = true;
3133                         } else {
3134                                 td->last_trb = ep_ring->enqueue;
3135                                 field |= TRB_IOC;
3136                                 more_trbs_coming = false;
3137                         }
3138
3139                         /* Calculate TRB length */
3140                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3141                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3142                         if (trb_buff_len > td_remain_len)
3143                                 trb_buff_len = td_remain_len;
3144
3145                         remainder = xhci_td_remainder(td_len - running_total);
3146                         length_field = TRB_LEN(trb_buff_len) |
3147                                 remainder |
3148                                 TRB_INTR_TARGET(0);
3149                         queue_trb(xhci, ep_ring, false, more_trbs_coming,
3150                                 lower_32_bits(addr),
3151                                 upper_32_bits(addr),
3152                                 length_field,
3153                                 /* We always want to know if the TRB was short,
3154                                  * or we won't get an event when it completes.
3155                                  * (Unless we use event data TRBs, which are a
3156                                  * waste of space and HC resources.)
3157                                  */
3158                                 field | TRB_ISP);
3159                         running_total += trb_buff_len;
3160
3161                         addr += trb_buff_len;
3162                         td_remain_len -= trb_buff_len;
3163                 }
3164
3165                 /* Check TD length */
3166                 if (running_total != td_len) {
3167                         xhci_err(xhci, "ISOC TD length unmatch\n");
3168                         return -EINVAL;
3169                 }
3170         }
3171
3172         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3173                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3174                         usb_amd_quirk_pll_disable();
3175         }
3176         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3177
3178         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3179                         start_cycle, start_trb);
3180         return 0;
3181 }
3182
3183 /*
3184  * Check transfer ring to guarantee there is enough room for the urb.
3185  * Update ISO URB start_frame and interval.
3186  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3187  * update the urb->start_frame by now.
3188  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3189  */
3190 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3191                 struct urb *urb, int slot_id, unsigned int ep_index)
3192 {
3193         struct xhci_virt_device *xdev;
3194         struct xhci_ring *ep_ring;
3195         struct xhci_ep_ctx *ep_ctx;
3196         int start_frame;
3197         int xhci_interval;
3198         int ep_interval;
3199         int num_tds, num_trbs, i;
3200         int ret;
3201
3202         xdev = xhci->devs[slot_id];
3203         ep_ring = xdev->eps[ep_index].ring;
3204         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3205
3206         num_trbs = 0;
3207         num_tds = urb->number_of_packets;
3208         for (i = 0; i < num_tds; i++)
3209                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3210
3211         /* Check the ring to guarantee there is enough room for the whole urb.
3212          * Do not insert any td of the urb to the ring if the check failed.
3213          */
3214         ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
3215                                 num_trbs, mem_flags);
3216         if (ret)
3217                 return ret;
3218
3219         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3220         start_frame &= 0x3fff;
3221
3222         urb->start_frame = start_frame;
3223         if (urb->dev->speed == USB_SPEED_LOW ||
3224                         urb->dev->speed == USB_SPEED_FULL)
3225                 urb->start_frame >>= 3;
3226
3227         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
3228         ep_interval = urb->interval;
3229         /* Convert to microframes */
3230         if (urb->dev->speed == USB_SPEED_LOW ||
3231                         urb->dev->speed == USB_SPEED_FULL)
3232                 ep_interval *= 8;
3233         /* FIXME change this to a warning and a suggestion to use the new API
3234          * to set the polling interval (once the API is added).
3235          */
3236         if (xhci_interval != ep_interval) {
3237                 if (printk_ratelimit())
3238                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3239                                         " (%d microframe%s) than xHCI "
3240                                         "(%d microframe%s)\n",
3241                                         ep_interval,
3242                                         ep_interval == 1 ? "" : "s",
3243                                         xhci_interval,
3244                                         xhci_interval == 1 ? "" : "s");
3245                 urb->interval = xhci_interval;
3246                 /* Convert back to frames for LS/FS devices */
3247                 if (urb->dev->speed == USB_SPEED_LOW ||
3248                                 urb->dev->speed == USB_SPEED_FULL)
3249                         urb->interval /= 8;
3250         }
3251         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3252 }
3253
3254 /****           Command Ring Operations         ****/
3255
3256 /* Generic function for queueing a command TRB on the command ring.
3257  * Check to make sure there's room on the command ring for one command TRB.
3258  * Also check that there's room reserved for commands that must not fail.
3259  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3260  * then only check for the number of reserved spots.
3261  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3262  * because the command event handler may want to resubmit a failed command.
3263  */
3264 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3265                 u32 field3, u32 field4, bool command_must_succeed)
3266 {
3267         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3268         int ret;
3269
3270         if (!command_must_succeed)
3271                 reserved_trbs++;
3272
3273         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3274                         reserved_trbs, GFP_ATOMIC);
3275         if (ret < 0) {
3276                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3277                 if (command_must_succeed)
3278                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3279                                         "unfailable commands failed.\n");
3280                 return ret;
3281         }
3282         queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3283                         field4 | xhci->cmd_ring->cycle_state);
3284         return 0;
3285 }
3286
3287 /* Queue a slot enable or disable request on the command ring */
3288 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3289 {
3290         return queue_command(xhci, 0, 0, 0,
3291                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3292 }
3293
3294 /* Queue an address device command TRB */
3295 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3296                 u32 slot_id)
3297 {
3298         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3299                         upper_32_bits(in_ctx_ptr), 0,
3300                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3301                         false);
3302 }
3303
3304 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3305                 u32 field1, u32 field2, u32 field3, u32 field4)
3306 {
3307         return queue_command(xhci, field1, field2, field3, field4, false);
3308 }
3309
3310 /* Queue a reset device command TRB */
3311 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3312 {
3313         return queue_command(xhci, 0, 0, 0,
3314                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3315                         false);
3316 }
3317
3318 /* Queue a configure endpoint command TRB */
3319 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3320                 u32 slot_id, bool command_must_succeed)
3321 {
3322         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3323                         upper_32_bits(in_ctx_ptr), 0,
3324                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3325                         command_must_succeed);
3326 }
3327
3328 /* Queue an evaluate context command TRB */
3329 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3330                 u32 slot_id)
3331 {
3332         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3333                         upper_32_bits(in_ctx_ptr), 0,
3334                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3335                         false);
3336 }
3337
3338 /*
3339  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3340  * activity on an endpoint that is about to be suspended.
3341  */
3342 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3343                 unsigned int ep_index, int suspend)
3344 {
3345         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3346         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3347         u32 type = TRB_TYPE(TRB_STOP_RING);
3348         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3349
3350         return queue_command(xhci, 0, 0, 0,
3351                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3352 }
3353
3354 /* Set Transfer Ring Dequeue Pointer command.
3355  * This should not be used for endpoints that have streams enabled.
3356  */
3357 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3358                 unsigned int ep_index, unsigned int stream_id,
3359                 struct xhci_segment *deq_seg,
3360                 union xhci_trb *deq_ptr, u32 cycle_state)
3361 {
3362         dma_addr_t addr;
3363         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3364         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3365         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3366         u32 type = TRB_TYPE(TRB_SET_DEQ);
3367         struct xhci_virt_ep *ep;
3368
3369         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3370         if (addr == 0) {
3371                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3372                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3373                                 deq_seg, deq_ptr);
3374                 return 0;
3375         }
3376         ep = &xhci->devs[slot_id]->eps[ep_index];
3377         if ((ep->ep_state & SET_DEQ_PENDING)) {
3378                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3379                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3380                 return 0;
3381         }
3382         ep->queued_deq_seg = deq_seg;
3383         ep->queued_deq_ptr = deq_ptr;
3384         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3385                         upper_32_bits(addr), trb_stream_id,
3386                         trb_slot_id | trb_ep_index | type, false);
3387 }
3388
3389 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3390                 unsigned int ep_index)
3391 {
3392         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3393         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3394         u32 type = TRB_TYPE(TRB_RESET_EP);
3395
3396         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3397                         false);
3398 }