drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         do {
 153                 /*
 154                  * Update the dequeue pointer further if that was a link TRB or
 155                  * we're at the end of an event ring segment (which doesn't have
 156                  * link TRBS)
 157                  */
 158                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 159                         if (consumer && last_trb_on_last_seg(xhci, ring,
 160                                                 ring->deq_seg, ring->dequeue)) {
 161                                 if (!in_interrupt())
 162                                         xhci_dbg(xhci, "Toggle cycle state "
 163                                                         "for ring %p = %i\n",
 164                                                         ring,
 165                                                         (unsigned int)
 166                                                         ring->cycle_state);
 167                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 168                         }
 169                         ring->deq_seg = ring->deq_seg->next;
 170                         ring->dequeue = ring->deq_seg->trbs;
 171                 } else {
 172                         ring->dequeue++;
 173                 }
 174         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 175
 176         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 177 }
 178
 179 /*
 180  * See Cycle bit rules. SW is the consumer for the event ring only.
 181  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 182  *
 183  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 184  * chain bit is set), then set the chain bit in all the following link TRBs.
 185  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 186  * have their chain bit cleared (so that each Link TRB is a separate TD).
 187  *
 188  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 189  * set, but other sections talk about dealing with the chain bit set.  This was
 190  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 191  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 192  *
 193  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 194  *                      prepare_transfer()?
 195  */
 196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 197                 bool consumer, bool more_trbs_coming, bool isoc)
 198 {
 199         u32 chain;
 200         union xhci_trb *next;
 201         unsigned long long addr;
 202
 203         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 204         next = ++(ring->enqueue);
 205
 206         ring->enq_updates++;
 207         /* Update the dequeue pointer further if that was a link TRB or we're at
 208          * the end of an event ring segment (which doesn't have link TRBS)
 209          */
 210         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 211                 if (!consumer) {
 212                         if (ring != xhci->event_ring) {
 213                                 /*
 214                                  * If the caller doesn't plan on enqueueing more
 215                                  * TDs before ringing the doorbell, then we
 216                                  * don't want to give the link TRB to the
 217                                  * hardware just yet.  We'll give the link TRB
 218                                  * back in prepare_ring() just before we enqueue
 219                                  * the TD at the top of the ring.
 220                                  */
 221                                 if (!chain && !more_trbs_coming)
 222                                         break;
 223
 224                                 /* If we're not dealing with 0.95 hardware or
 225                                  * isoc rings on AMD 0.96 host,
 226                                  * carry over the chain bit of the previous TRB
 227                                  * (which may mean the chain bit is cleared).
 228                                  */
 229                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 230                                                 && !xhci_link_trb_quirk(xhci)) {
 231                                         next->link.control &=
 232                                                 cpu_to_le32(~TRB_CHAIN);
 233                                         next->link.control |=
 234                                                 cpu_to_le32(chain);
 235                                 }
 236                                 /* Give this link TRB to the hardware */
 237                                 wmb();
 238                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 239                         }
 240                         /* Toggle the cycle bit after the last ring segment. */
 241                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 242                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 243                                 if (!in_interrupt())
 244                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 245                                                         ring,
 246                                                         (unsigned int) ring->cycle_state);
 247                         }
 248                 }
 249                 ring->enq_seg = ring->enq_seg->next;
 250                 ring->enqueue = ring->enq_seg->trbs;
 251                 next = ring->enqueue;
 252         }
 253         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 254 }
 255
 256 /*
 257  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 258  * above.
 259  * FIXME: this would be simpler and faster if we just kept track of the number
 260  * of free TRBs in a ring.
 261  */
 262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 263                 unsigned int num_trbs)
 264 {
 265         int i;
 266         union xhci_trb *enq = ring->enqueue;
 267         struct xhci_segment *enq_seg = ring->enq_seg;
 268         struct xhci_segment *cur_seg;
 269         unsigned int left_on_ring;
 270
 271         /* If we are currently pointing to a link TRB, advance the
 272          * enqueue pointer before checking for space */
 273         while (last_trb(xhci, ring, enq_seg, enq)) {
 274                 enq_seg = enq_seg->next;
 275                 enq = enq_seg->trbs;
 276         }
 277
 278         /* Check if ring is empty */
 279         if (enq == ring->dequeue) {
 280                 /* Can't use link trbs */
 281                 left_on_ring = TRBS_PER_SEGMENT - 1;
 282                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 283                                 cur_seg = cur_seg->next)
 284                         left_on_ring += TRBS_PER_SEGMENT - 1;
 285
 286                 /* Always need one TRB free in the ring. */
 287                 left_on_ring -= 1;
 288                 if (num_trbs > left_on_ring) {
 289                         xhci_warn(xhci, "Not enough room on ring; "
 290                                         "need %u TRBs, %u TRBs left\n",
 291                                         num_trbs, left_on_ring);
 292                         return 0;
 293                 }
 294                 return 1;
 295         }
 296         /* Make sure there's an extra empty TRB available */
 297         for (i = 0; i <= num_trbs; ++i) {
 298                 if (enq == ring->dequeue)
 299                         return 0;
 300                 enq++;
 301                 while (last_trb(xhci, ring, enq_seg, enq)) {
 302                         enq_seg = enq_seg->next;
 303                         enq = enq_seg->trbs;
 304                 }
 305         }
 306         return 1;
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 313                 return;
 314
 315         xhci_dbg(xhci, "// Ding dong!\n");
 316         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 322 {
 323         u64 temp_64;
 324         int ret;
 325
 326         xhci_dbg(xhci, "Abort command ring\n");
 327
 328         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 329                 xhci_dbg(xhci, "The command ring isn't running, "
 330                                 "Have the command ring been stopped?\n");
 331                 return 0;
 332         }
 333
 334         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 335         if (!(temp_64 & CMD_RING_RUNNING)) {
 336                 xhci_dbg(xhci, "Command ring had been stopped\n");
 337                 return 0;
 338         }
 339         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 340         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 341                         &xhci->op_regs->cmd_ring);
 342
 343         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 344          * time the completion od all xHCI commands, including
 345          * the Command Abort operation. If software doesn't see
 346          * CRR negated in a timely manner (e.g. longer than 5
 347          * seconds), then it should assume that the there are
 348          * larger problems with the xHC and assert HCRST.
 349          */
 350         ret = handshake(xhci, &xhci->op_regs->cmd_ring,
 351                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 352         if (ret < 0) {
 353                 xhci_err(xhci, "Stopped the command ring failed, "
 354                                 "maybe the host is dead\n");
 355                 xhci->xhc_state |= XHCI_STATE_DYING;
 356                 xhci_quiesce(xhci);
 357                 xhci_halt(xhci);
 358                 return -ESHUTDOWN;
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int xhci_queue_cd(struct xhci_hcd *xhci,
 365                 struct xhci_command *command,
 366                 union xhci_trb *cmd_trb)
 367 {
 368         struct xhci_cd *cd;
 369         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 370         if (!cd)
 371                 return -ENOMEM;
 372         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 373
 374         cd->command = command;
 375         cd->cmd_trb = cmd_trb;
 376         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 377
 378         return 0;
 379 }
 380
 381 /*
 382  * Cancel the command which has issue.
 383  *
 384  * Some commands may hang due to waiting for acknowledgement from
 385  * usb device. It is outside of the xHC's ability to control and
 386  * will cause the command ring is blocked. When it occurs software
 387  * should intervene to recover the command ring.
 388  * See Section 4.6.1.1 and 4.6.1.2
 389  */
 390 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 391                 union xhci_trb *cmd_trb)
 392 {
 393         int retval = 0;
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&xhci->lock, flags);
 397
 398         if (xhci->xhc_state & XHCI_STATE_DYING) {
 399                 xhci_warn(xhci, "Abort the command ring,"
 400                                 " but the xHCI is dead.\n");
 401                 retval = -ESHUTDOWN;
 402                 goto fail;
 403         }
 404
 405         /* queue the cmd desriptor to cancel_cmd_list */
 406         retval = xhci_queue_cd(xhci, command, cmd_trb);
 407         if (retval) {
 408                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 409                 goto fail;
 410         }
 411
 412         /* abort command ring */
 413         retval = xhci_abort_cmd_ring(xhci);
 414         if (retval) {
 415                 xhci_err(xhci, "Abort command ring failed\n");
 416                 if (unlikely(retval == -ESHUTDOWN)) {
 417                         spin_unlock_irqrestore(&xhci->lock, flags);
 418                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 419                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 420                         return retval;
 421                 }
 422         }
 423
 424 fail:
 425         spin_unlock_irqrestore(&xhci->lock, flags);
 426         return retval;
 427 }
 428
 429 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 430                 unsigned int slot_id,
 431                 unsigned int ep_index,
 432                 unsigned int stream_id)
 433 {
 434         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 435         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 436         unsigned int ep_state = ep->ep_state;
 437
 438         /* Don't ring the doorbell for this endpoint if there are pending
 439          * cancellations because we don't want to interrupt processing.
 440          * We don't want to restart any stream rings if there's a set dequeue
 441          * pointer command pending because the device can choose to start any
 442          * stream once the endpoint is on the HW schedule.
 443          * FIXME - check all the stream rings for pending cancellations.
 444          */
 445         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 446             (ep_state & EP_HALTED))
 447                 return;
 448         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 449         /* The CPU has better things to do at this point than wait for a
 450          * write-posting flush.  It'll get there soon enough.
 451          */
 452 }
 453
 454 /* Ring the doorbell for any rings with pending URBs */
 455 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 456                 unsigned int slot_id,
 457                 unsigned int ep_index)
 458 {
 459         unsigned int stream_id;
 460         struct xhci_virt_ep *ep;
 461
 462         ep = &xhci->devs[slot_id]->eps[ep_index];
 463
 464         /* A ring has pending URBs if its TD list is not empty */
 465         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 466                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 467                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 468                 return;
 469         }
 470
 471         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 472                         stream_id++) {
 473                 struct xhci_stream_info *stream_info = ep->stream_info;
 474                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 475                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 476                                                 stream_id);
 477         }
 478 }
 479
 480 /*
 481  * Find the segment that trb is in.  Start searching in start_seg.
 482  * If we must move past a segment that has a link TRB with a toggle cycle state
 483  * bit set, then we will toggle the value pointed at by cycle_state.
 484  */
 485 static struct xhci_segment *find_trb_seg(
 486                 struct xhci_segment *start_seg,
 487                 union xhci_trb  *trb, int *cycle_state)
 488 {
 489         struct xhci_segment *cur_seg = start_seg;
 490         struct xhci_generic_trb *generic_trb;
 491
 492         while (cur_seg->trbs > trb ||
 493                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 494                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 495                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 496                         *cycle_state ^= 0x1;
 497                 cur_seg = cur_seg->next;
 498                 if (cur_seg == start_seg)
 499                         /* Looped over the entire list.  Oops! */
 500                         return NULL;
 501         }
 502         return cur_seg;
 503 }
 504
 505
 506 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 507                 unsigned int slot_id, unsigned int ep_index,
 508                 unsigned int stream_id)
 509 {
 510         struct xhci_virt_ep *ep;
 511
 512         ep = &xhci->devs[slot_id]->eps[ep_index];
 513         /* Common case: no streams */
 514         if (!(ep->ep_state & EP_HAS_STREAMS))
 515                 return ep->ring;
 516
 517         if (stream_id == 0) {
 518                 xhci_warn(xhci,
 519                                 "WARN: Slot ID %u, ep index %u has streams, "
 520                                 "but URB has no stream ID.\n",
 521                                 slot_id, ep_index);
 522                 return NULL;
 523         }
 524
 525         if (stream_id < ep->stream_info->num_streams)
 526                 return ep->stream_info->stream_rings[stream_id];
 527
 528         xhci_warn(xhci,
 529                         "WARN: Slot ID %u, ep index %u has "
 530                         "stream IDs 1 to %u allocated, "
 531                         "but stream ID %u is requested.\n",
 532                         slot_id, ep_index,
 533                         ep->stream_info->num_streams - 1,
 534                         stream_id);
 535         return NULL;
 536 }
 537
 538 /* Get the right ring for the given URB.
 539  * If the endpoint supports streams, boundary check the URB's stream ID.
 540  * If the endpoint doesn't support streams, return the singular endpoint ring.
 541  */
 542 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 543                 struct urb *urb)
 544 {
 545         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 546                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 547 }
 548
 549 /*
 550  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 551  * Record the new state of the xHC's endpoint ring dequeue segment,
 552  * dequeue pointer, and new consumer cycle state in state.
 553  * Update our internal representation of the ring's dequeue pointer.
 554  *
 555  * We do this in three jumps:
 556  *  - First we update our new ring state to be the same as when the xHC stopped.
 557  *  - Then we traverse the ring to find the segment that contains
 558  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 559  *    any link TRBs with the toggle cycle bit set.
 560  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 561  *    if we've moved it past a link TRB with the toggle cycle bit set.
 562  *
 563  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 564  * with correct __le32 accesses they should work fine.  Only users of this are
 565  * in here.
 566  */
 567 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 568                 unsigned int slot_id, unsigned int ep_index,
 569                 unsigned int stream_id, struct xhci_td *cur_td,
 570                 struct xhci_dequeue_state *state)
 571 {
 572         struct xhci_virt_device *dev = xhci->devs[slot_id];
 573         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 574         struct xhci_ring *ep_ring;
 575         struct xhci_segment *new_seg;
 576         union xhci_trb *new_deq;
 577         dma_addr_t addr;
 578         u64 hw_dequeue;
 579         bool cycle_found = false;
 580         bool td_last_trb_found = false;
 581
 582         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 583                         ep_index, stream_id);
 584         if (!ep_ring) {
 585                 xhci_warn(xhci, "WARN can't find new dequeue state "
 586                                 "for invalid stream ID %u.\n",
 587                                 stream_id);
 588                 return;
 589         }
 590
 591         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 592         xhci_dbg(xhci, "Finding endpoint context\n");
 593         /* 4.6.9 the css flag is written to the stream context for streams */
 594         if (ep->ep_state & EP_HAS_STREAMS) {
 595                 struct xhci_stream_ctx *ctx =
 596                         &ep->stream_info->stream_ctx_array[stream_id];
 597                 hw_dequeue = le64_to_cpu(ctx->stream_ring);
 598         } else {
 599                 struct xhci_ep_ctx *ep_ctx
 600                         = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 601                 hw_dequeue = le64_to_cpu(ep_ctx->deq);
 602         }
 603
 604         new_seg = ep_ring->deq_seg;
 605         new_deq = ep_ring->dequeue;
 606         state->new_cycle_state = hw_dequeue & 0x1;
 607
 608         /*
 609          * We want to find the pointer, segment and cycle state of the new trb
 610          * (the one after current TD's last_trb). We know the cycle state at
 611          * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
 612          * found.
 613          */
 614         do {
 615                 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 616                     == (dma_addr_t)(hw_dequeue & ~0xf)) {
 617                         cycle_found = true;
 618                         if (td_last_trb_found)
 619                                 break;
 620                 }
 621                 if (new_deq == cur_td->last_trb)
 622                         td_last_trb_found = true;
 623
 624                 if (cycle_found &&
 625                     TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
 626                     new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
 627                         state->new_cycle_state ^= 0x1;
 628
 629                 next_trb(xhci, ep_ring, &new_seg, &new_deq);
 630
 631                 /* Search wrapped around, bail out */
 632                 if (new_deq == ep->ring->dequeue) {
 633                         xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 634                         state->new_deq_seg = NULL;
 635                         state->new_deq_ptr = NULL;
 636                         return;
 637                 }
 638
 639         } while (!cycle_found || !td_last_trb_found);
 640
 641         state->new_deq_seg = new_seg;
 642         state->new_deq_ptr = new_deq;
 643
 644         /* Don't update the ring cycle state for the producer (us). */
 645         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 646
 647         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 648                         state->new_deq_seg);
 649         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 650         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 651                         (unsigned long long) addr);
 652 }
 653
 654 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 655  * (The last TRB actually points to the ring enqueue pointer, which is not part
 656  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 657  */
 658 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 659                 struct xhci_td *cur_td, bool flip_cycle)
 660 {
 661         struct xhci_segment *cur_seg;
 662         union xhci_trb *cur_trb;
 663
 664         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 665                         true;
 666                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 667                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 668                         /* Unchain any chained Link TRBs, but
 669                          * leave the pointers intact.
 670                          */
 671                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 672                         /* Flip the cycle bit (link TRBs can't be the first
 673                          * or last TRB).
 674                          */
 675                         if (flip_cycle)
 676                                 cur_trb->generic.field[3] ^=
 677                                         cpu_to_le32(TRB_CYCLE);
 678                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 679                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 680                                         "in seg %p (0x%llx dma)\n",
 681                                         cur_trb,
 682                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 683                                         cur_seg,
 684                                         (unsigned long long)cur_seg->dma);
 685                 } else {
 686                         cur_trb->generic.field[0] = 0;
 687                         cur_trb->generic.field[1] = 0;
 688                         cur_trb->generic.field[2] = 0;
 689                         /* Preserve only the cycle bit of this TRB */
 690                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 691                         /* Flip the cycle bit except on the first or last TRB */
 692                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 693                                         cur_trb != cur_td->last_trb)
 694                                 cur_trb->generic.field[3] ^=
 695                                         cpu_to_le32(TRB_CYCLE);
 696                         cur_trb->generic.field[3] |= cpu_to_le32(
 697                                 TRB_TYPE(TRB_TR_NOOP));
 698                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 699                                         "in seg %p (0x%llx dma)\n",
 700                                         cur_trb,
 701                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 702                                         cur_seg,
 703                                         (unsigned long long)cur_seg->dma);
 704                 }
 705                 if (cur_trb == cur_td->last_trb)
 706                         break;
 707         }
 708 }
 709
 710 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 711                 unsigned int ep_index, unsigned int stream_id,
 712                 struct xhci_segment *deq_seg,
 713                 union xhci_trb *deq_ptr, u32 cycle_state);
 714
 715 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 716                 unsigned int slot_id, unsigned int ep_index,
 717                 unsigned int stream_id,
 718                 struct xhci_dequeue_state *deq_state)
 719 {
 720         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 721
 722         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 723                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 724                         deq_state->new_deq_seg,
 725                         (unsigned long long)deq_state->new_deq_seg->dma,
 726                         deq_state->new_deq_ptr,
 727                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 728                         deq_state->new_cycle_state);
 729         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 730                         deq_state->new_deq_seg,
 731                         deq_state->new_deq_ptr,
 732                         (u32) deq_state->new_cycle_state);
 733         /* Stop the TD queueing code from ringing the doorbell until
 734          * this command completes.  The HC won't set the dequeue pointer
 735          * if the ring is running, and ringing the doorbell starts the
 736          * ring running.
 737          */
 738         ep->ep_state |= SET_DEQ_PENDING;
 739 }
 740
 741 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 742                 struct xhci_virt_ep *ep)
 743 {
 744         ep->ep_state &= ~EP_HALT_PENDING;
 745         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 746          * timer is running on another CPU, we don't decrement stop_cmds_pending
 747          * (since we didn't successfully stop the watchdog timer).
 748          */
 749         if (del_timer(&ep->stop_cmd_timer))
 750                 ep->stop_cmds_pending--;
 751 }
 752
 753 /* Must be called with xhci->lock held in interrupt context */
 754 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 755                 struct xhci_td *cur_td, int status, char *adjective)
 756 {
 757         struct usb_hcd *hcd;
 758         struct urb      *urb;
 759         struct urb_priv *urb_priv;
 760
 761         urb = cur_td->urb;
 762         urb_priv = urb->hcpriv;
 763         urb_priv->td_cnt++;
 764         hcd = bus_to_hcd(urb->dev->bus);
 765
 766         /* Only giveback urb when this is the last td in urb */
 767         if (urb_priv->td_cnt == urb_priv->length) {
 768                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 769                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 770                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 771                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 772                                         usb_amd_quirk_pll_enable();
 773                         }
 774                 }
 775                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 776
 777                 spin_unlock(&xhci->lock);
 778                 usb_hcd_giveback_urb(hcd, urb, status);
 779                 xhci_urb_free_priv(xhci, urb_priv);
 780                 spin_lock(&xhci->lock);
 781         }
 782 }
 783
 784 /*
 785  * When we get a command completion for a Stop Endpoint Command, we need to
 786  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 787  *
 788  *  1. If the HW was in the middle of processing the TD that needs to be
 789  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 790  *     in the TD with a Set Dequeue Pointer Command.
 791  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 792  *     bit cleared) so that the HW will skip over them.
 793  */
 794 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 795                 union xhci_trb *trb, struct xhci_event_cmd *event)
 796 {
 797         unsigned int slot_id;
 798         unsigned int ep_index;
 799         struct xhci_virt_device *virt_dev;
 800         struct xhci_ring *ep_ring;
 801         struct xhci_virt_ep *ep;
 802         struct list_head *entry;
 803         struct xhci_td *cur_td = NULL;
 804         struct xhci_td *last_unlinked_td;
 805
 806         struct xhci_dequeue_state deq_state;
 807
 808         if (unlikely(TRB_TO_SUSPEND_PORT(
 809                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 810                 slot_id = TRB_TO_SLOT_ID(
 811                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 812                 virt_dev = xhci->devs[slot_id];
 813                 if (virt_dev)
 814                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 815                                 event);
 816                 else
 817                         xhci_warn(xhci, "Stop endpoint command "
 818                                 "completion for disabled slot %u\n",
 819                                 slot_id);
 820                 return;
 821         }
 822
 823         memset(&deq_state, 0, sizeof(deq_state));
 824         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 825         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 826         ep = &xhci->devs[slot_id]->eps[ep_index];
 827
 828         if (list_empty(&ep->cancelled_td_list)) {
 829                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 830                 ep->stopped_td = NULL;
 831                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 832                 return;
 833         }
 834
 835         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 836          * We have the xHCI lock, so nothing can modify this list until we drop
 837          * it.  We're also in the event handler, so we can't get re-interrupted
 838          * if another Stop Endpoint command completes
 839          */
 840         list_for_each(entry, &ep->cancelled_td_list) {
 841                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 842                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 843                                 cur_td->first_trb,
 844                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 845                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 846                 if (!ep_ring) {
 847                         /* This shouldn't happen unless a driver is mucking
 848                          * with the stream ID after submission.  This will
 849                          * leave the TD on the hardware ring, and the hardware
 850                          * will try to execute it, and may access a buffer
 851                          * that has already been freed.  In the best case, the
 852                          * hardware will execute it, and the event handler will
 853                          * ignore the completion event for that TD, since it was
 854                          * removed from the td_list for that endpoint.  In
 855                          * short, don't muck with the stream ID after
 856                          * submission.
 857                          */
 858                         xhci_warn(xhci, "WARN Cancelled URB %p "
 859                                         "has invalid stream ID %u.\n",
 860                                         cur_td->urb,
 861                                         cur_td->urb->stream_id);
 862                         goto remove_finished_td;
 863                 }
 864                 /*
 865                  * If we stopped on the TD we need to cancel, then we have to
 866                  * move the xHC endpoint ring dequeue pointer past this TD.
 867                  */
 868                 if (cur_td == ep->stopped_td)
 869                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 870                                         cur_td->urb->stream_id,
 871                                         cur_td, &deq_state);
 872                 else
 873                         td_to_noop(xhci, ep_ring, cur_td, false);
 874 remove_finished_td:
 875                 /*
 876                  * The event handler won't see a completion for this TD anymore,
 877                  * so remove it from the endpoint ring's TD list.  Keep it in
 878                  * the cancelled TD list for URB completion later.
 879                  */
 880                 list_del_init(&cur_td->td_list);
 881         }
 882         last_unlinked_td = cur_td;
 883         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 884
 885         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 886         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 887                 xhci_queue_new_dequeue_state(xhci,
 888                                 slot_id, ep_index,
 889                                 ep->stopped_td->urb->stream_id,
 890                                 &deq_state);
 891                 xhci_ring_cmd_db(xhci);
 892         } else {
 893                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 894                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 895         }
 896
 897         /* Clear stopped_td if endpoint is not halted */
 898         if (!(ep->ep_state & EP_HALTED))
 899                 ep->stopped_td = NULL;
 900
 901         /*
 902          * Drop the lock and complete the URBs in the cancelled TD list.
 903          * New TDs to be cancelled might be added to the end of the list before
 904          * we can complete all the URBs for the TDs we already unlinked.
 905          * So stop when we've completed the URB for the last TD we unlinked.
 906          */
 907         do {
 908                 cur_td = list_entry(ep->cancelled_td_list.next,
 909                                 struct xhci_td, cancelled_td_list);
 910                 list_del_init(&cur_td->cancelled_td_list);
 911
 912                 /* Clean up the cancelled URB */
 913                 /* Doesn't matter what we pass for status, since the core will
 914                  * just overwrite it (because the URB has been unlinked).
 915                  */
 916                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 917
 918                 /* Stop processing the cancelled list if the watchdog timer is
 919                  * running.
 920                  */
 921                 if (xhci->xhc_state & XHCI_STATE_DYING)
 922                         return;
 923         } while (cur_td != last_unlinked_td);
 924
 925         /* Return to the event handler with xhci->lock re-acquired */
 926 }
 927
 928 /* Watchdog timer function for when a stop endpoint command fails to complete.
 929  * In this case, we assume the host controller is broken or dying or dead.  The
 930  * host may still be completing some other events, so we have to be careful to
 931  * let the event ring handler and the URB dequeueing/enqueueing functions know
 932  * through xhci->state.
 933  *
 934  * The timer may also fire if the host takes a very long time to respond to the
 935  * command, and the stop endpoint command completion handler cannot delete the
 936  * timer before the timer function is called.  Another endpoint cancellation may
 937  * sneak in before the timer function can grab the lock, and that may queue
 938  * another stop endpoint command and add the timer back.  So we cannot use a
 939  * simple flag to say whether there is a pending stop endpoint command for a
 940  * particular endpoint.
 941  *
 942  * Instead we use a combination of that flag and a counter for the number of
 943  * pending stop endpoint commands.  If the timer is the tail end of the last
 944  * stop endpoint command, and the endpoint's command is still pending, we assume
 945  * the host is dying.
 946  */
 947 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 948 {
 949         struct xhci_hcd *xhci;
 950         struct xhci_virt_ep *ep;
 951         struct xhci_virt_ep *temp_ep;
 952         struct xhci_ring *ring;
 953         struct xhci_td *cur_td;
 954         int ret, i, j;
 955         unsigned long flags;
 956
 957         ep = (struct xhci_virt_ep *) arg;
 958         xhci = ep->xhci;
 959
 960         spin_lock_irqsave(&xhci->lock, flags);
 961
 962         ep->stop_cmds_pending--;
 963         if (xhci->xhc_state & XHCI_STATE_DYING) {
 964                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 965                                 "xHCI as DYING, exiting.\n");
 966                 spin_unlock_irqrestore(&xhci->lock, flags);
 967                 return;
 968         }
 969         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 970                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 971                                 "exiting.\n");
 972                 spin_unlock_irqrestore(&xhci->lock, flags);
 973                 return;
 974         }
 975
 976         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 977         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 978         /* Oops, HC is dead or dying or at least not responding to the stop
 979          * endpoint command.
 980          */
 981         xhci->xhc_state |= XHCI_STATE_DYING;
 982         /* Disable interrupts from the host controller and start halting it */
 983         xhci_quiesce(xhci);
 984         spin_unlock_irqrestore(&xhci->lock, flags);
 985
 986         ret = xhci_halt(xhci);
 987
 988         spin_lock_irqsave(&xhci->lock, flags);
 989         if (ret < 0) {
 990                 /* This is bad; the host is not responding to commands and it's
 991                  * not allowing itself to be halted.  At least interrupts are
 992                  * disabled. If we call usb_hc_died(), it will attempt to
 993                  * disconnect all device drivers under this host.  Those
 994                  * disconnect() methods will wait for all URBs to be unlinked,
 995                  * so we must complete them.
 996                  */
 997                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 998                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 999                 /* We could turn all TDs on the rings to no-ops.  This won't
1000                  * help if the host has cached part of the ring, and is slow if
1001                  * we want to preserve the cycle bit.  Skip it and hope the host
1002                  * doesn't touch the memory.
1003                  */
1004         }
1005         for (i = 0; i < MAX_HC_SLOTS; i++) {
1006                 if (!xhci->devs[i])
1007                         continue;
1008                 for (j = 0; j < 31; j++) {
1009                         temp_ep = &xhci->devs[i]->eps[j];
1010                         ring = temp_ep->ring;
1011                         if (!ring)
1012                                 continue;
1013                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
1014                                         "ep index %u\n", i, j);
1015                         while (!list_empty(&ring->td_list)) {
1016                                 cur_td = list_first_entry(&ring->td_list,
1017                                                 struct xhci_td,
1018                                                 td_list);
1019                                 list_del_init(&cur_td->td_list);
1020                                 if (!list_empty(&cur_td->cancelled_td_list))
1021                                         list_del_init(&cur_td->cancelled_td_list);
1022                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1023                                                 -ESHUTDOWN, "killed");
1024                         }
1025                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1026                                 cur_td = list_first_entry(
1027                                                 &temp_ep->cancelled_td_list,
1028                                                 struct xhci_td,
1029                                                 cancelled_td_list);
1030                                 list_del_init(&cur_td->cancelled_td_list);
1031                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1032                                                 -ESHUTDOWN, "killed");
1033                         }
1034                 }
1035         }
1036         spin_unlock_irqrestore(&xhci->lock, flags);
1037         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1038         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1039         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1040 }
1041
1042 /*
1043  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1044  * we need to clear the set deq pending flag in the endpoint ring state, so that
1045  * the TD queueing code can ring the doorbell again.  We also need to ring the
1046  * endpoint doorbell to restart the ring, but only if there aren't more
1047  * cancellations pending.
1048  */
1049 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1050                 struct xhci_event_cmd *event,
1051                 union xhci_trb *trb)
1052 {
1053         unsigned int slot_id;
1054         unsigned int ep_index;
1055         unsigned int stream_id;
1056         struct xhci_ring *ep_ring;
1057         struct xhci_virt_device *dev;
1058         struct xhci_ep_ctx *ep_ctx;
1059         struct xhci_slot_ctx *slot_ctx;
1060
1061         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1062         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1063         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1064         dev = xhci->devs[slot_id];
1065
1066         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1067         if (!ep_ring) {
1068                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1069                                 "freed stream ID %u\n",
1070                                 stream_id);
1071                 /* XXX: Harmless??? */
1072                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1073                 return;
1074         }
1075
1076         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1077         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1078
1079         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1080                 unsigned int ep_state;
1081                 unsigned int slot_state;
1082
1083                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1084                 case COMP_TRB_ERR:
1085                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1086                                         "of stream ID configuration\n");
1087                         break;
1088                 case COMP_CTX_STATE:
1089                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1090                                         "to incorrect slot or ep state.\n");
1091                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1092                         ep_state &= EP_STATE_MASK;
1093                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1094                         slot_state = GET_SLOT_STATE(slot_state);
1095                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1096                                         slot_state, ep_state);
1097                         break;
1098                 case COMP_EBADSLT:
1099                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1100                                         "slot %u was not enabled.\n", slot_id);
1101                         break;
1102                 default:
1103                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1104                                         "completion code of %u.\n",
1105                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1106                         break;
1107                 }
1108                 /* OK what do we do now?  The endpoint state is hosed, and we
1109                  * should never get to this point if the synchronization between
1110                  * queueing, and endpoint state are correct.  This might happen
1111                  * if the device gets disconnected after we've finished
1112                  * cancelling URBs, which might not be an error...
1113                  */
1114         } else {
1115                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1116                          le64_to_cpu(ep_ctx->deq));
1117                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1118                                          dev->eps[ep_index].queued_deq_ptr) ==
1119                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1120                         /* Update the ring's dequeue segment and dequeue pointer
1121                          * to reflect the new position.
1122                          */
1123                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1124                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1125                 } else {
1126                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1127                                         "Ptr command & xHCI internal state.\n");
1128                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1129                                         dev->eps[ep_index].queued_deq_seg,
1130                                         dev->eps[ep_index].queued_deq_ptr);
1131                 }
1132         }
1133
1134         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1135         dev->eps[ep_index].queued_deq_seg = NULL;
1136         dev->eps[ep_index].queued_deq_ptr = NULL;
1137         /* Restart any rings with pending URBs */
1138         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1139 }
1140
1141 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1142                 struct xhci_event_cmd *event,
1143                 union xhci_trb *trb)
1144 {
1145         int slot_id;
1146         unsigned int ep_index;
1147
1148         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1149         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1150         /* This command will only fail if the endpoint wasn't halted,
1151          * but we don't care.
1152          */
1153         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1154                  GET_COMP_CODE(le32_to_cpu(event->status)));
1155
1156         /* HW with the reset endpoint quirk needs to have a configure endpoint
1157          * command complete before the endpoint can be used.  Queue that here
1158          * because the HW can't handle two commands being queued in a row.
1159          */
1160         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1161                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1162                 xhci_queue_configure_endpoint(xhci,
1163                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1164                                 false);
1165                 xhci_ring_cmd_db(xhci);
1166         } else {
1167                 /* Clear our internal halted state and restart the ring(s) */
1168                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1169                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1170         }
1171 }
1172
1173 /* Complete the command and detele it from the devcie's command queue.
1174  */
1175 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1176                 struct xhci_command *command, u32 status)
1177 {
1178         command->status = status;
1179         list_del(&command->cmd_list);
1180         if (command->completion)
1181                 complete(command->completion);
1182         else
1183                 xhci_free_command(xhci, command);
1184 }
1185
1186
1187 /* Check to see if a command in the device's command queue matches this one.
1188  * Signal the completion or free the command, and return 1.  Return 0 if the
1189  * completed command isn't at the head of the command list.
1190  */
1191 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1192                 struct xhci_virt_device *virt_dev,
1193                 struct xhci_event_cmd *event)
1194 {
1195         struct xhci_command *command;
1196
1197         if (list_empty(&virt_dev->cmd_list))
1198                 return 0;
1199
1200         command = list_entry(virt_dev->cmd_list.next,
1201                         struct xhci_command, cmd_list);
1202         if (xhci->cmd_ring->dequeue != command->command_trb)
1203                 return 0;
1204
1205         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1206                         GET_COMP_CODE(le32_to_cpu(event->status)));
1207         return 1;
1208 }
1209
1210 /*
1211  * Finding the command trb need to be cancelled and modifying it to
1212  * NO OP command. And if the command is in device's command wait
1213  * list, finishing and freeing it.
1214  *
1215  * If we can't find the command trb, we think it had already been
1216  * executed.
1217  */
1218 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1219 {
1220         struct xhci_segment *cur_seg;
1221         union xhci_trb *cmd_trb;
1222         u32 cycle_state;
1223
1224         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1225                 return;
1226
1227         /* find the current segment of command ring */
1228         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1229                         xhci->cmd_ring->dequeue, &cycle_state);
1230
1231         if (!cur_seg) {
1232                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1233                                 xhci->cmd_ring->dequeue,
1234                                 (unsigned long long)
1235                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1236                                         xhci->cmd_ring->dequeue));
1237                 xhci_debug_ring(xhci, xhci->cmd_ring);
1238                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1239                 return;
1240         }
1241
1242         /* find the command trb matched by cd from command ring */
1243         for (cmd_trb = xhci->cmd_ring->dequeue;
1244                         cmd_trb != xhci->cmd_ring->enqueue;
1245                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1246                 /* If the trb is link trb, continue */
1247                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1248                         continue;
1249
1250                 if (cur_cd->cmd_trb == cmd_trb) {
1251
1252                         /* If the command in device's command list, we should
1253                          * finish it and free the command structure.
1254                          */
1255                         if (cur_cd->command)
1256                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1257                                         cur_cd->command, COMP_CMD_STOP);
1258
1259                         /* get cycle state from the origin command trb */
1260                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1261                                 & TRB_CYCLE;
1262
1263                         /* modify the command trb to NO OP command */
1264                         cmd_trb->generic.field[0] = 0;
1265                         cmd_trb->generic.field[1] = 0;
1266                         cmd_trb->generic.field[2] = 0;
1267                         cmd_trb->generic.field[3] = cpu_to_le32(
1268                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1269                         break;
1270                 }
1271         }
1272 }
1273
1274 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1275 {
1276         struct xhci_cd *cur_cd, *next_cd;
1277
1278         if (list_empty(&xhci->cancel_cmd_list))
1279                 return;
1280
1281         list_for_each_entry_safe(cur_cd, next_cd,
1282                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1283                 xhci_cmd_to_noop(xhci, cur_cd);
1284                 list_del(&cur_cd->cancel_cmd_list);
1285                 kfree(cur_cd);
1286         }
1287 }
1288
1289 /*
1290  * traversing the cancel_cmd_list. If the command descriptor according
1291  * to cmd_trb is found, the function free it and return 1, otherwise
1292  * return 0.
1293  */
1294 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1295                 union xhci_trb *cmd_trb)
1296 {
1297         struct xhci_cd *cur_cd, *next_cd;
1298
1299         if (list_empty(&xhci->cancel_cmd_list))
1300                 return 0;
1301
1302         list_for_each_entry_safe(cur_cd, next_cd,
1303                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1304                 if (cur_cd->cmd_trb == cmd_trb) {
1305                         if (cur_cd->command)
1306                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1307                                         cur_cd->command, COMP_CMD_STOP);
1308                         list_del(&cur_cd->cancel_cmd_list);
1309                         kfree(cur_cd);
1310                         return 1;
1311                 }
1312         }
1313
1314         return 0;
1315 }
1316
1317 /*
1318  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1319  * trb pointed by the command ring dequeue pointer is the trb we want to
1320  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1321  * traverse the cancel_cmd_list to trun the all of the commands according
1322  * to command descriptor to NO-OP trb.
1323  */
1324 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1325                 int cmd_trb_comp_code)
1326 {
1327         int cur_trb_is_good = 0;
1328
1329         /* Searching the cmd trb pointed by the command ring dequeue
1330          * pointer in command descriptor list. If it is found, free it.
1331          */
1332         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1333                         xhci->cmd_ring->dequeue);
1334
1335         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1336                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1337         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1338                 /* traversing the cancel_cmd_list and canceling
1339                  * the command according to command descriptor
1340                  */
1341                 xhci_cancel_cmd_in_cd_list(xhci);
1342
1343                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1344                 /*
1345                  * ring command ring doorbell again to restart the
1346                  * command ring
1347                  */
1348                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1349                         xhci_ring_cmd_db(xhci);
1350         }
1351         return cur_trb_is_good;
1352 }
1353
1354 static void handle_cmd_completion(struct xhci_hcd *xhci,
1355                 struct xhci_event_cmd *event)
1356 {
1357         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1358         u64 cmd_dma;
1359         dma_addr_t cmd_dequeue_dma;
1360         struct xhci_input_control_ctx *ctrl_ctx;
1361         struct xhci_virt_device *virt_dev;
1362         unsigned int ep_index;
1363         struct xhci_ring *ep_ring;
1364         unsigned int ep_state;
1365
1366         cmd_dma = le64_to_cpu(event->cmd_trb);
1367         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1368                         xhci->cmd_ring->dequeue);
1369         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1370         if (cmd_dequeue_dma == 0) {
1371                 xhci->error_bitmask |= 1 << 4;
1372                 return;
1373         }
1374         /* Does the DMA address match our internal dequeue pointer address? */
1375         if (cmd_dma != (u64) cmd_dequeue_dma) {
1376                 xhci->error_bitmask |= 1 << 5;
1377                 return;
1378         }
1379
1380         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1381                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1382                 /* If the return value is 0, we think the trb pointed by
1383                  * command ring dequeue pointer is a good trb. The good
1384                  * trb means we don't want to cancel the trb, but it have
1385                  * been stopped by host. So we should handle it normally.
1386                  * Otherwise, driver should invoke inc_deq() and return.
1387                  */
1388                 if (handle_stopped_cmd_ring(xhci,
1389                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1390                         inc_deq(xhci, xhci->cmd_ring, false);
1391                         return;
1392                 }
1393         }
1394
1395         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1396                 & TRB_TYPE_BITMASK) {
1397         case TRB_TYPE(TRB_ENABLE_SLOT):
1398                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1399                         xhci->slot_id = slot_id;
1400                 else
1401                         xhci->slot_id = 0;
1402                 complete(&xhci->addr_dev);
1403                 break;
1404         case TRB_TYPE(TRB_DISABLE_SLOT):
1405                 if (xhci->devs[slot_id]) {
1406                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1407                                 /* Delete default control endpoint resources */
1408                                 xhci_free_device_endpoint_resources(xhci,
1409                                                 xhci->devs[slot_id], true);
1410                         xhci_free_virt_device(xhci, slot_id);
1411                 }
1412                 break;
1413         case TRB_TYPE(TRB_CONFIG_EP):
1414                 virt_dev = xhci->devs[slot_id];
1415                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1416                         break;
1417                 /*
1418                  * Configure endpoint commands can come from the USB core
1419                  * configuration or alt setting changes, or because the HW
1420                  * needed an extra configure endpoint command after a reset
1421                  * endpoint command or streams were being configured.
1422                  * If the command was for a halted endpoint, the xHCI driver
1423                  * is not waiting on the configure endpoint command.
1424                  */
1425                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1426                                 virt_dev->in_ctx);
1427                 /* Input ctx add_flags are the endpoint index plus one */
1428                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1429                 /* A usb_set_interface() call directly after clearing a halted
1430                  * condition may race on this quirky hardware.  Not worth
1431                  * worrying about, since this is prototype hardware.  Not sure
1432                  * if this will work for streams, but streams support was
1433                  * untested on this prototype.
1434                  */
1435                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1436                                 ep_index != (unsigned int) -1 &&
1437                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1438                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1439                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1440                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1441                         if (!(ep_state & EP_HALTED))
1442                                 goto bandwidth_change;
1443                         xhci_dbg(xhci, "Completed config ep cmd - "
1444                                         "last ep index = %d, state = %d\n",
1445                                         ep_index, ep_state);
1446                         /* Clear internal halted state and restart ring(s) */
1447                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1448                                 ~EP_HALTED;
1449                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1450                         break;
1451                 }
1452 bandwidth_change:
1453                 xhci_dbg(xhci, "Completed config ep cmd\n");
1454                 xhci->devs[slot_id]->cmd_status =
1455                         GET_COMP_CODE(le32_to_cpu(event->status));
1456                 complete(&xhci->devs[slot_id]->cmd_completion);
1457                 break;
1458         case TRB_TYPE(TRB_EVAL_CONTEXT):
1459                 virt_dev = xhci->devs[slot_id];
1460                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1461                         break;
1462                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1463                 complete(&xhci->devs[slot_id]->cmd_completion);
1464                 break;
1465         case TRB_TYPE(TRB_ADDR_DEV):
1466                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1467                 complete(&xhci->addr_dev);
1468                 break;
1469         case TRB_TYPE(TRB_STOP_RING):
1470                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1471                 break;
1472         case TRB_TYPE(TRB_SET_DEQ):
1473                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1474                 break;
1475         case TRB_TYPE(TRB_CMD_NOOP):
1476                 break;
1477         case TRB_TYPE(TRB_RESET_EP):
1478                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1479                 break;
1480         case TRB_TYPE(TRB_RESET_DEV):
1481                 xhci_dbg(xhci, "Completed reset device command.\n");
1482                 slot_id = TRB_TO_SLOT_ID(
1483                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1484                 virt_dev = xhci->devs[slot_id];
1485                 if (virt_dev)
1486                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1487                 else
1488                         xhci_warn(xhci, "Reset device command completion "
1489                                         "for disabled slot %u\n", slot_id);
1490                 break;
1491         case TRB_TYPE(TRB_NEC_GET_FW):
1492                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1493                         xhci->error_bitmask |= 1 << 6;
1494                         break;
1495                 }
1496                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1497                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1498                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1499                 break;
1500         default:
1501                 /* Skip over unknown commands on the event ring */
1502                 xhci->error_bitmask |= 1 << 6;
1503                 break;
1504         }
1505         inc_deq(xhci, xhci->cmd_ring, false);
1506 }
1507
1508 static void handle_vendor_event(struct xhci_hcd *xhci,
1509                 union xhci_trb *event)
1510 {
1511         u32 trb_type;
1512
1513         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1514         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1515         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1516                 handle_cmd_completion(xhci, &event->event_cmd);
1517 }
1518
1519 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1520  * port registers -- USB 3.0 and USB 2.0).
1521  *
1522  * Returns a zero-based port number, which is suitable for indexing into each of
1523  * the split roothubs' port arrays and bus state arrays.
1524  * Add one to it in order to call xhci_find_slot_id_by_port.
1525  */
1526 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1527                 struct xhci_hcd *xhci, u32 port_id)
1528 {
1529         unsigned int i;
1530         unsigned int num_similar_speed_ports = 0;
1531
1532         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1533          * and usb2_ports are 0-based indexes.  Count the number of similar
1534          * speed ports, up to 1 port before this port.
1535          */
1536         for (i = 0; i < (port_id - 1); i++) {
1537                 u8 port_speed = xhci->port_array[i];
1538
1539                 /*
1540                  * Skip ports that don't have known speeds, or have duplicate
1541                  * Extended Capabilities port speed entries.
1542                  */
1543                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1544                         continue;
1545
1546                 /*
1547                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1548                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1549                  * matches the device speed, it's a similar speed port.
1550                  */
1551                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1552                         num_similar_speed_ports++;
1553         }
1554         return num_similar_speed_ports;
1555 }
1556
1557 static void handle_port_status(struct xhci_hcd *xhci,
1558                 union xhci_trb *event)
1559 {
1560         struct usb_hcd *hcd;
1561         u32 port_id;
1562         u32 temp, temp1;
1563         int max_ports;
1564         int slot_id;
1565         unsigned int faked_port_index;
1566         u8 major_revision;
1567         struct xhci_bus_state *bus_state;
1568         __le32 __iomem **port_array;
1569         bool bogus_port_status = false;
1570
1571         /* Port status change events always have a successful completion code */
1572         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1573                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1574                 xhci->error_bitmask |= 1 << 8;
1575         }
1576         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1577         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1578
1579         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1580         if ((port_id <= 0) || (port_id > max_ports)) {
1581                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1582                 bogus_port_status = true;
1583                 goto cleanup;
1584         }
1585
1586         /* Figure out which usb_hcd this port is attached to:
1587          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1588          */
1589         major_revision = xhci->port_array[port_id - 1];
1590         if (major_revision == 0) {
1591                 xhci_warn(xhci, "Event for port %u not in "
1592                                 "Extended Capabilities, ignoring.\n",
1593                                 port_id);
1594                 bogus_port_status = true;
1595                 goto cleanup;
1596         }
1597         if (major_revision == DUPLICATE_ENTRY) {
1598                 xhci_warn(xhci, "Event for port %u duplicated in"
1599                                 "Extended Capabilities, ignoring.\n",
1600                                 port_id);
1601                 bogus_port_status = true;
1602                 goto cleanup;
1603         }
1604
1605         /*
1606          * Hardware port IDs reported by a Port Status Change Event include USB
1607          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1608          * resume event, but we first need to translate the hardware port ID
1609          * into the index into the ports on the correct split roothub, and the
1610          * correct bus_state structure.
1611          */
1612         /* Find the right roothub. */
1613         hcd = xhci_to_hcd(xhci);
1614         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1615                 hcd = xhci->shared_hcd;
1616         bus_state = &xhci->bus_state[hcd_index(hcd)];
1617         if (hcd->speed == HCD_USB3)
1618                 port_array = xhci->usb3_ports;
1619         else
1620                 port_array = xhci->usb2_ports;
1621         /* Find the faked port hub number */
1622         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1623                         port_id);
1624
1625         temp = xhci_readl(xhci, port_array[faked_port_index]);
1626         if (hcd->state == HC_STATE_SUSPENDED) {
1627                 xhci_dbg(xhci, "resume root hub\n");
1628                 usb_hcd_resume_root_hub(hcd);
1629         }
1630
1631         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1632                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1633
1634                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1635                 if (!(temp1 & CMD_RUN)) {
1636                         xhci_warn(xhci, "xHC is not running.\n");
1637                         goto cleanup;
1638                 }
1639
1640                 if (DEV_SUPERSPEED(temp)) {
1641                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1642                         xhci_set_link_state(xhci, port_array, faked_port_index,
1643                                                 XDEV_U0);
1644                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1645                                         faked_port_index + 1);
1646                         if (!slot_id) {
1647                                 xhci_dbg(xhci, "slot_id is zero\n");
1648                                 goto cleanup;
1649                         }
1650                         xhci_ring_device(xhci, slot_id);
1651                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1652                         /* Clear PORT_PLC */
1653                         xhci_test_and_clear_bit(xhci, port_array,
1654                                                 faked_port_index, PORT_PLC);
1655                 } else {
1656                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1657                         bus_state->resume_done[faked_port_index] = jiffies +
1658                                 msecs_to_jiffies(20);
1659                         mod_timer(&hcd->rh_timer,
1660                                   bus_state->resume_done[faked_port_index]);
1661                         /* Do the rest in GetPortStatus */
1662                 }
1663         }
1664
1665         if (hcd->speed != HCD_USB3)
1666                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1667                                         PORT_PLC);
1668
1669 cleanup:
1670         /* Update event ring dequeue pointer before dropping the lock */
1671         inc_deq(xhci, xhci->event_ring, true);
1672
1673         /* Don't make the USB core poll the roothub if we got a bad port status
1674          * change event.  Besides, at that point we can't tell which roothub
1675          * (USB 2.0 or USB 3.0) to kick.
1676          */
1677         if (bogus_port_status)
1678                 return;
1679
1680         /*
1681          * xHCI port-status-change events occur when the "or" of all the
1682          * status-change bits in the portsc register changes from 0 to 1.
1683          * New status changes won't cause an event if any other change
1684          * bits are still set.  When an event occurs, switch over to
1685          * polling to avoid losing status changes.
1686          */
1687         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1688         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1689         spin_unlock(&xhci->lock);
1690         /* Pass this up to the core */
1691         usb_hcd_poll_rh_status(hcd);
1692         spin_lock(&xhci->lock);
1693 }
1694
1695 /*
1696  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1697  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1698  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1699  * returns 0.
1700  */
1701 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1702                 union xhci_trb  *start_trb,
1703                 union xhci_trb  *end_trb,
1704                 dma_addr_t      suspect_dma)
1705 {
1706         dma_addr_t start_dma;
1707         dma_addr_t end_seg_dma;
1708         dma_addr_t end_trb_dma;
1709         struct xhci_segment *cur_seg;
1710
1711         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1712         cur_seg = start_seg;
1713
1714         do {
1715                 if (start_dma == 0)
1716                         return NULL;
1717                 /* We may get an event for a Link TRB in the middle of a TD */
1718                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1719                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1720                 /* If the end TRB isn't in this segment, this is set to 0 */
1721                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1722
1723                 if (end_trb_dma > 0) {
1724                         /* The end TRB is in this segment, so suspect should be here */
1725                         if (start_dma <= end_trb_dma) {
1726                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1727                                         return cur_seg;
1728                         } else {
1729                                 /* Case for one segment with
1730                                  * a TD wrapped around to the top
1731                                  */
1732                                 if ((suspect_dma >= start_dma &&
1733                                                         suspect_dma <= end_seg_dma) ||
1734                                                 (suspect_dma >= cur_seg->dma &&
1735                                                  suspect_dma <= end_trb_dma))
1736                                         return cur_seg;
1737                         }
1738                         return NULL;
1739                 } else {
1740                         /* Might still be somewhere in this segment */
1741                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1742                                 return cur_seg;
1743                 }
1744                 cur_seg = cur_seg->next;
1745                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1746         } while (cur_seg != start_seg);
1747
1748         return NULL;
1749 }
1750
1751 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1752                 unsigned int slot_id, unsigned int ep_index,
1753                 unsigned int stream_id,
1754                 struct xhci_td *td, union xhci_trb *event_trb)
1755 {
1756         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1757         ep->ep_state |= EP_HALTED;
1758         ep->stopped_td = td;
1759         ep->stopped_stream = stream_id;
1760
1761         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1762         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1763
1764         ep->stopped_td = NULL;
1765         ep->stopped_stream = 0;
1766
1767         xhci_ring_cmd_db(xhci);
1768 }
1769
1770 /* Check if an error has halted the endpoint ring.  The class driver will
1771  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1772  * However, a babble and other errors also halt the endpoint ring, and the class
1773  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1774  * Ring Dequeue Pointer command manually.
1775  */
1776 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1777                 struct xhci_ep_ctx *ep_ctx,
1778                 unsigned int trb_comp_code)
1779 {
1780         /* TRB completion codes that may require a manual halt cleanup */
1781         if (trb_comp_code == COMP_TX_ERR ||
1782                         trb_comp_code == COMP_BABBLE ||
1783                         trb_comp_code == COMP_SPLIT_ERR)
1784                 /* The 0.96 spec says a babbling control endpoint
1785                  * is not halted. The 0.96 spec says it is.  Some HW
1786                  * claims to be 0.95 compliant, but it halts the control
1787                  * endpoint anyway.  Check if a babble halted the
1788                  * endpoint.
1789                  */
1790                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1791                     cpu_to_le32(EP_STATE_HALTED))
1792                         return 1;
1793
1794         return 0;
1795 }
1796
1797 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1798 {
1799         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1800                 /* Vendor defined "informational" completion code,
1801                  * treat as not-an-error.
1802                  */
1803                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1804                                 trb_comp_code);
1805                 xhci_dbg(xhci, "Treating code as success.\n");
1806                 return 1;
1807         }
1808         return 0;
1809 }
1810
1811 /*
1812  * Finish the td processing, remove the td from td list;
1813  * Return 1 if the urb can be given back.
1814  */
1815 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1816         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1817         struct xhci_virt_ep *ep, int *status, bool skip)
1818 {
1819         struct xhci_virt_device *xdev;
1820         struct xhci_ring *ep_ring;
1821         unsigned int slot_id;
1822         int ep_index;
1823         struct urb *urb = NULL;
1824         struct xhci_ep_ctx *ep_ctx;
1825         int ret = 0;
1826         struct urb_priv *urb_priv;
1827         u32 trb_comp_code;
1828
1829         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1830         xdev = xhci->devs[slot_id];
1831         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1832         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1833         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1834         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1835
1836         if (skip)
1837                 goto td_cleanup;
1838
1839         if (trb_comp_code == COMP_STOP_INVAL ||
1840                         trb_comp_code == COMP_STOP) {
1841                 /* The Endpoint Stop Command completion will take care of any
1842                  * stopped TDs.  A stopped TD may be restarted, so don't update
1843                  * the ring dequeue pointer or take this TD off any lists yet.
1844                  */
1845                 ep->stopped_td = td;
1846                 return 0;
1847         } else {
1848                 if (trb_comp_code == COMP_STALL) {
1849                         /* The transfer is completed from the driver's
1850                          * perspective, but we need to issue a set dequeue
1851                          * command for this stalled endpoint to move the dequeue
1852                          * pointer past the TD.  We can't do that here because
1853                          * the halt condition must be cleared first.  Let the
1854                          * USB class driver clear the stall later.
1855                          */
1856                         ep->stopped_td = td;
1857                         ep->stopped_stream = ep_ring->stream_id;
1858                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1859                                         ep_ctx, trb_comp_code)) {
1860                         /* Other types of errors halt the endpoint, but the
1861                          * class driver doesn't call usb_reset_endpoint() unless
1862                          * the error is -EPIPE.  Clear the halted status in the
1863                          * xHCI hardware manually.
1864                          */
1865                         xhci_cleanup_halted_endpoint(xhci,
1866                                         slot_id, ep_index, ep_ring->stream_id,
1867                                         td, event_trb);
1868                 } else {
1869                         /* Update ring dequeue pointer */
1870                         while (ep_ring->dequeue != td->last_trb)
1871                                 inc_deq(xhci, ep_ring, false);
1872                         inc_deq(xhci, ep_ring, false);
1873                 }
1874
1875 td_cleanup:
1876                 /* Clean up the endpoint's TD list */
1877                 urb = td->urb;
1878                 urb_priv = urb->hcpriv;
1879
1880                 /* Do one last check of the actual transfer length.
1881                  * If the host controller said we transferred more data than
1882                  * the buffer length, urb->actual_length will be a very big
1883                  * number (since it's unsigned).  Play it safe and say we didn't
1884                  * transfer anything.
1885                  */
1886                 if (urb->actual_length > urb->transfer_buffer_length) {
1887                         xhci_warn(xhci, "URB transfer length is wrong, "
1888                                         "xHC issue? req. len = %u, "
1889                                         "act. len = %u\n",
1890                                         urb->transfer_buffer_length,
1891                                         urb->actual_length);
1892                         urb->actual_length = 0;
1893                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1894                                 *status = -EREMOTEIO;
1895                         else
1896                                 *status = 0;
1897                 }
1898                 list_del_init(&td->td_list);
1899                 /* Was this TD slated to be cancelled but completed anyway? */
1900                 if (!list_empty(&td->cancelled_td_list))
1901                         list_del_init(&td->cancelled_td_list);
1902
1903                 urb_priv->td_cnt++;
1904                 /* Giveback the urb when all the tds are completed */
1905                 if (urb_priv->td_cnt == urb_priv->length) {
1906                         ret = 1;
1907                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1908                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1909                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1910                                         == 0) {
1911                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1912                                                 usb_amd_quirk_pll_enable();
1913                                 }
1914                         }
1915                 }
1916         }
1917
1918         return ret;
1919 }
1920
1921 /*
1922  * Process control tds, update urb status and actual_length.
1923  */
1924 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1925         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1926         struct xhci_virt_ep *ep, int *status)
1927 {
1928         struct xhci_virt_device *xdev;
1929         struct xhci_ring *ep_ring;
1930         unsigned int slot_id;
1931         int ep_index;
1932         struct xhci_ep_ctx *ep_ctx;
1933         u32 trb_comp_code;
1934
1935         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1936         xdev = xhci->devs[slot_id];
1937         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1938         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1939         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1940         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1941
1942         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1943         switch (trb_comp_code) {
1944         case COMP_SUCCESS:
1945                 if (event_trb == ep_ring->dequeue) {
1946                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1947                                         "without IOC set??\n");
1948                         *status = -ESHUTDOWN;
1949                 } else if (event_trb != td->last_trb) {
1950                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1951                                         "without IOC set??\n");
1952                         *status = -ESHUTDOWN;
1953                 } else {
1954                         *status = 0;
1955                 }
1956                 break;
1957         case COMP_SHORT_TX:
1958                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1959                         *status = -EREMOTEIO;
1960                 else
1961                         *status = 0;
1962                 break;
1963         case COMP_STOP_INVAL:
1964         case COMP_STOP:
1965                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1966         default:
1967                 if (!xhci_requires_manual_halt_cleanup(xhci,
1968                                         ep_ctx, trb_comp_code))
1969                         break;
1970                 xhci_dbg(xhci, "TRB error code %u, "
1971                                 "halted endpoint index = %u\n",
1972                                 trb_comp_code, ep_index);
1973                 /* else fall through */
1974         case COMP_STALL:
1975                 /* Did we transfer part of the data (middle) phase? */
1976                 if (event_trb != ep_ring->dequeue &&
1977                                 event_trb != td->last_trb)
1978                         td->urb->actual_length =
1979                                 td->urb->transfer_buffer_length -
1980                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1981                 else
1982                         td->urb->actual_length = 0;
1983
1984                 xhci_cleanup_halted_endpoint(xhci,
1985                         slot_id, ep_index, 0, td, event_trb);
1986                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1987         }
1988         /*
1989          * Did we transfer any data, despite the errors that might have
1990          * happened?  I.e. did we get past the setup stage?
1991          */
1992         if (event_trb != ep_ring->dequeue) {
1993                 /* The event was for the status stage */
1994                 if (event_trb == td->last_trb) {
1995                         if (td->urb->actual_length != 0) {
1996                                 /* Don't overwrite a previously set error code
1997                                  */
1998                                 if ((*status == -EINPROGRESS || *status == 0) &&
1999                                                 (td->urb->transfer_flags
2000                                                  & URB_SHORT_NOT_OK))
2001                                         /* Did we already see a short data
2002                                          * stage? */
2003                                         *status = -EREMOTEIO;
2004                         } else {
2005                                 td->urb->actual_length =
2006                                         td->urb->transfer_buffer_length;
2007                         }
2008                 } else {
2009                 /* Maybe the event was for the data stage? */
2010                         td->urb->actual_length =
2011                                 td->urb->transfer_buffer_length -
2012                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2013                         xhci_dbg(xhci, "Waiting for status "
2014                                         "stage event\n");
2015                         return 0;
2016                 }
2017         }
2018
2019         return finish_td(xhci, td, event_trb, event, ep, status, false);
2020 }
2021
2022 /*
2023  * Process isochronous tds, update urb packet status and actual_length.
2024  */
2025 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2026         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2027         struct xhci_virt_ep *ep, int *status)
2028 {
2029         struct xhci_ring *ep_ring;
2030         struct urb_priv *urb_priv;
2031         int idx;
2032         int len = 0;
2033         union xhci_trb *cur_trb;
2034         struct xhci_segment *cur_seg;
2035         struct usb_iso_packet_descriptor *frame;
2036         u32 trb_comp_code;
2037         bool skip_td = false;
2038
2039         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2040         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2041         urb_priv = td->urb->hcpriv;
2042         idx = urb_priv->td_cnt;
2043         frame = &td->urb->iso_frame_desc[idx];
2044
2045         /* handle completion code */
2046         switch (trb_comp_code) {
2047         case COMP_SUCCESS:
2048                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2049                         frame->status = 0;
2050                         break;
2051                 }
2052                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2053                         trb_comp_code = COMP_SHORT_TX;
2054         case COMP_SHORT_TX:
2055                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2056                                 -EREMOTEIO : 0;
2057                 break;
2058         case COMP_BW_OVER:
2059                 frame->status = -ECOMM;
2060                 skip_td = true;
2061                 break;
2062         case COMP_BUFF_OVER:
2063         case COMP_BABBLE:
2064                 frame->status = -EOVERFLOW;
2065                 skip_td = true;
2066                 break;
2067         case COMP_DEV_ERR:
2068         case COMP_STALL:
2069         case COMP_TX_ERR:
2070                 frame->status = -EPROTO;
2071                 skip_td = true;
2072                 break;
2073         case COMP_STOP:
2074         case COMP_STOP_INVAL:
2075                 break;
2076         default:
2077                 frame->status = -1;
2078                 break;
2079         }
2080
2081         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2082                 frame->actual_length = frame->length;
2083                 td->urb->actual_length += frame->length;
2084         } else {
2085                 for (cur_trb = ep_ring->dequeue,
2086                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2087                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2088                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2089                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2090                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2091                 }
2092                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2093                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2094
2095                 if (trb_comp_code != COMP_STOP_INVAL) {
2096                         frame->actual_length = len;
2097                         td->urb->actual_length += len;
2098                 }
2099         }
2100
2101         return finish_td(xhci, td, event_trb, event, ep, status, false);
2102 }
2103
2104 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2105                         struct xhci_transfer_event *event,
2106                         struct xhci_virt_ep *ep, int *status)
2107 {
2108         struct xhci_ring *ep_ring;
2109         struct urb_priv *urb_priv;
2110         struct usb_iso_packet_descriptor *frame;
2111         int idx;
2112
2113         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2114         urb_priv = td->urb->hcpriv;
2115         idx = urb_priv->td_cnt;
2116         frame = &td->urb->iso_frame_desc[idx];
2117
2118         /* The transfer is partly done. */
2119         frame->status = -EXDEV;
2120
2121         /* calc actual length */
2122         frame->actual_length = 0;
2123
2124         /* Update ring dequeue pointer */
2125         while (ep_ring->dequeue != td->last_trb)
2126                 inc_deq(xhci, ep_ring, false);
2127         inc_deq(xhci, ep_ring, false);
2128
2129         return finish_td(xhci, td, NULL, event, ep, status, true);
2130 }
2131
2132 /*
2133  * Process bulk and interrupt tds, update urb status and actual_length.
2134  */
2135 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2136         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2137         struct xhci_virt_ep *ep, int *status)
2138 {
2139         struct xhci_ring *ep_ring;
2140         union xhci_trb *cur_trb;
2141         struct xhci_segment *cur_seg;
2142         u32 trb_comp_code;
2143
2144         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2145         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2146
2147         switch (trb_comp_code) {
2148         case COMP_SUCCESS:
2149                 /* Double check that the HW transferred everything. */
2150                 if (event_trb != td->last_trb ||
2151                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2152                         xhci_warn(xhci, "WARN Successful completion "
2153                                         "on short TX\n");
2154                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2155                                 *status = -EREMOTEIO;
2156                         else
2157                                 *status = 0;
2158                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2159                                 trb_comp_code = COMP_SHORT_TX;
2160                 } else {
2161                         *status = 0;
2162                 }
2163                 break;
2164         case COMP_SHORT_TX:
2165                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2166                         *status = -EREMOTEIO;
2167                 else
2168                         *status = 0;
2169                 break;
2170         default:
2171                 /* Others already handled above */
2172                 break;
2173         }
2174         if (trb_comp_code == COMP_SHORT_TX)
2175                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2176                                 "%d bytes untransferred\n",
2177                                 td->urb->ep->desc.bEndpointAddress,
2178                                 td->urb->transfer_buffer_length,
2179                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2180         /* Fast path - was this the last TRB in the TD for this URB? */
2181         if (event_trb == td->last_trb) {
2182                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2183                         td->urb->actual_length =
2184                                 td->urb->transfer_buffer_length -
2185                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2186                         if (td->urb->transfer_buffer_length <
2187                                         td->urb->actual_length) {
2188                                 xhci_warn(xhci, "HC gave bad length "
2189                                                 "of %d bytes left\n",
2190                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2191                                 td->urb->actual_length = 0;
2192                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2193                                         *status = -EREMOTEIO;
2194                                 else
2195                                         *status = 0;
2196                         }
2197                         /* Don't overwrite a previously set error code */
2198                         if (*status == -EINPROGRESS) {
2199                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2200                                         *status = -EREMOTEIO;
2201                                 else
2202                                         *status = 0;
2203                         }
2204                 } else {
2205                         td->urb->actual_length =
2206                                 td->urb->transfer_buffer_length;
2207                         /* Ignore a short packet completion if the
2208                          * untransferred length was zero.
2209                          */
2210                         if (*status == -EREMOTEIO)
2211                                 *status = 0;
2212                 }
2213         } else {
2214                 /* Slow path - walk the list, starting from the dequeue
2215                  * pointer, to get the actual length transferred.
2216                  */
2217                 td->urb->actual_length = 0;
2218                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2219                                 cur_trb != event_trb;
2220                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2221                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2222                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2223                                 td->urb->actual_length +=
2224                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2225                 }
2226                 /* If the ring didn't stop on a Link or No-op TRB, add
2227                  * in the actual bytes transferred from the Normal TRB
2228                  */
2229                 if (trb_comp_code != COMP_STOP_INVAL)
2230                         td->urb->actual_length +=
2231                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2232                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2233         }
2234
2235         return finish_td(xhci, td, event_trb, event, ep, status, false);
2236 }
2237
2238 /*
2239  * If this function returns an error condition, it means it got a Transfer
2240  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2241  * At this point, the host controller is probably hosed and should be reset.
2242  */
2243 static int handle_tx_event(struct xhci_hcd *xhci,
2244                 struct xhci_transfer_event *event)
2245 {
2246         struct xhci_virt_device *xdev;
2247         struct xhci_virt_ep *ep;
2248         struct xhci_ring *ep_ring;
2249         unsigned int slot_id;
2250         int ep_index;
2251         struct xhci_td *td = NULL;
2252         dma_addr_t event_dma;
2253         struct xhci_segment *event_seg;
2254         union xhci_trb *event_trb;
2255         struct urb *urb = NULL;
2256         int status = -EINPROGRESS;
2257         struct urb_priv *urb_priv;
2258         struct xhci_ep_ctx *ep_ctx;
2259         struct list_head *tmp;
2260         u32 trb_comp_code;
2261         int ret = 0;
2262         int td_num = 0;
2263
2264         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2265         xdev = xhci->devs[slot_id];
2266         if (!xdev) {
2267                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2268                 return -ENODEV;
2269         }
2270
2271         /* Endpoint ID is 1 based, our index is zero based */
2272         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2273         ep = &xdev->eps[ep_index];
2274         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2275         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2276         if (!ep_ring ||
2277             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2278             EP_STATE_DISABLED) {
2279                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2280                                 "or incorrect stream ring\n");
2281                 return -ENODEV;
2282         }
2283
2284         /* Count current td numbers if ep->skip is set */
2285         if (ep->skip) {
2286                 list_for_each(tmp, &ep_ring->td_list)
2287                         td_num++;
2288         }
2289
2290         event_dma = le64_to_cpu(event->buffer);
2291         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2292         /* Look for common error cases */
2293         switch (trb_comp_code) {
2294         /* Skip codes that require special handling depending on
2295          * transfer type
2296          */
2297         case COMP_SUCCESS:
2298                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2299                         break;
2300                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2301                         trb_comp_code = COMP_SHORT_TX;
2302                 else
2303                         xhci_warn(xhci, "WARN Successful completion on short TX: "
2304                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2305         case COMP_SHORT_TX:
2306                 break;
2307         case COMP_STOP:
2308                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2309                 break;
2310         case COMP_STOP_INVAL:
2311                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2312                 break;
2313         case COMP_STALL:
2314                 xhci_dbg(xhci, "Stalled endpoint\n");
2315                 ep->ep_state |= EP_HALTED;
2316                 status = -EPIPE;
2317                 break;
2318         case COMP_TRB_ERR:
2319                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2320                 status = -EILSEQ;
2321                 break;
2322         case COMP_SPLIT_ERR:
2323         case COMP_TX_ERR:
2324                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2325                 status = -EPROTO;
2326                 break;
2327         case COMP_BABBLE:
2328                 xhci_dbg(xhci, "Babble error on endpoint\n");
2329                 status = -EOVERFLOW;
2330                 break;
2331         case COMP_DB_ERR:
2332                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2333                 status = -ENOSR;
2334                 break;
2335         case COMP_BW_OVER:
2336                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2337                 break;
2338         case COMP_BUFF_OVER:
2339                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2340                 break;
2341         case COMP_UNDERRUN:
2342                 /*
2343                  * When the Isoch ring is empty, the xHC will generate
2344                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2345                  * Underrun Event for OUT Isoch endpoint.
2346                  */
2347                 xhci_dbg(xhci, "underrun event on endpoint\n");
2348                 if (!list_empty(&ep_ring->td_list))
2349                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2350                                         "still with TDs queued?\n",
2351                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2352                                  ep_index);
2353                 goto cleanup;
2354         case COMP_OVERRUN:
2355                 xhci_dbg(xhci, "overrun event on endpoint\n");
2356                 if (!list_empty(&ep_ring->td_list))
2357                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2358                                         "still with TDs queued?\n",
2359                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2360                                  ep_index);
2361                 goto cleanup;
2362         case COMP_DEV_ERR:
2363                 xhci_warn(xhci, "WARN: detect an incompatible device");
2364                 status = -EPROTO;
2365                 break;
2366         case COMP_MISSED_INT:
2367                 /*
2368                  * When encounter missed service error, one or more isoc tds
2369                  * may be missed by xHC.
2370                  * Set skip flag of the ep_ring; Complete the missed tds as
2371                  * short transfer when process the ep_ring next time.
2372                  */
2373                 ep->skip = true;
2374                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2375                 goto cleanup;
2376         default:
2377                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2378                         status = 0;
2379                         break;
2380                 }
2381                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2382                                 "busted\n");
2383                 goto cleanup;
2384         }
2385
2386         do {
2387                 /* This TRB should be in the TD at the head of this ring's
2388                  * TD list.
2389                  */
2390                 if (list_empty(&ep_ring->td_list)) {
2391                         /*
2392                          * A stopped endpoint may generate an extra completion
2393                          * event if the device was suspended.  Don't print
2394                          * warnings.
2395                          */
2396                         if (!(trb_comp_code == COMP_STOP ||
2397                                                 trb_comp_code == COMP_STOP_INVAL)) {
2398                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2399                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2400                                                 ep_index);
2401                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2402                                                 (le32_to_cpu(event->flags) &
2403                                                  TRB_TYPE_BITMASK)>>10);
2404                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2405                         }
2406                         if (ep->skip) {
2407                                 ep->skip = false;
2408                                 xhci_dbg(xhci, "td_list is empty while skip "
2409                                                 "flag set. Clear skip flag.\n");
2410                         }
2411                         ret = 0;
2412                         goto cleanup;
2413                 }
2414
2415                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2416                 if (ep->skip && td_num == 0) {
2417                         ep->skip = false;
2418                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2419                                                 "Clear skip flag.\n");
2420                         ret = 0;
2421                         goto cleanup;
2422                 }
2423
2424                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2425                 if (ep->skip)
2426                         td_num--;
2427
2428                 /* Is this a TRB in the currently executing TD? */
2429                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2430                                 td->last_trb, event_dma);
2431
2432                 /*
2433                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2434                  * is not in the current TD pointed by ep_ring->dequeue because
2435                  * that the hardware dequeue pointer still at the previous TRB
2436                  * of the current TD. The previous TRB maybe a Link TD or the
2437                  * last TRB of the previous TD. The command completion handle
2438                  * will take care the rest.
2439                  */
2440                 if (!event_seg && (trb_comp_code == COMP_STOP ||
2441                                    trb_comp_code == COMP_STOP_INVAL)) {
2442                         ret = 0;
2443                         goto cleanup;
2444                 }
2445
2446                 if (!event_seg) {
2447                         if (!ep->skip ||
2448                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2449                                 /* Some host controllers give a spurious
2450                                  * successful event after a short transfer.
2451                                  * Ignore it.
2452                                  */
2453                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2454                                                 ep_ring->last_td_was_short) {
2455                                         ep_ring->last_td_was_short = false;
2456                                         ret = 0;
2457                                         goto cleanup;
2458                                 }
2459                                 /* HC is busted, give up! */
2460                                 xhci_err(xhci,
2461                                         "ERROR Transfer event TRB DMA ptr not "
2462                                         "part of current TD\n");
2463                                 return -ESHUTDOWN;
2464                         }
2465
2466                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2467                         goto cleanup;
2468                 }
2469                 if (trb_comp_code == COMP_SHORT_TX)
2470                         ep_ring->last_td_was_short = true;
2471                 else
2472                         ep_ring->last_td_was_short = false;
2473
2474                 if (ep->skip) {
2475                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2476                         ep->skip = false;
2477                 }
2478
2479                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2480                                                 sizeof(*event_trb)];
2481                 /*
2482                  * No-op TRB should not trigger interrupts.
2483                  * If event_trb is a no-op TRB, it means the
2484                  * corresponding TD has been cancelled. Just ignore
2485                  * the TD.
2486                  */
2487                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2488                         xhci_dbg(xhci,
2489                                  "event_trb is a no-op TRB. Skip it\n");
2490                         goto cleanup;
2491                 }
2492
2493                 /* Now update the urb's actual_length and give back to
2494                  * the core
2495                  */
2496                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2497                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2498                                                  &status);
2499                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2500                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2501                                                  &status);
2502                 else
2503                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2504                                                  ep, &status);
2505
2506 cleanup:
2507                 /*
2508                  * Do not update event ring dequeue pointer if ep->skip is set.
2509                  * Will roll back to continue process missed tds.
2510                  */
2511                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2512                         inc_deq(xhci, xhci->event_ring, true);
2513                 }
2514
2515                 if (ret) {
2516                         urb = td->urb;
2517                         urb_priv = urb->hcpriv;
2518                         /* Leave the TD around for the reset endpoint function
2519                          * to use(but only if it's not a control endpoint,
2520                          * since we already queued the Set TR dequeue pointer
2521                          * command for stalled control endpoints).
2522                          */
2523                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2524                                 (trb_comp_code != COMP_STALL &&
2525                                         trb_comp_code != COMP_BABBLE))
2526                                 xhci_urb_free_priv(xhci, urb_priv);
2527                         else
2528                                 kfree(urb_priv);
2529
2530                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2531                         if ((urb->actual_length != urb->transfer_buffer_length &&
2532                                                 (urb->transfer_flags &
2533                                                  URB_SHORT_NOT_OK)) ||
2534                                         (status != 0 &&
2535                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2536                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2537                                                 "expected = %x, status = %d\n",
2538                                                 urb, urb->actual_length,
2539                                                 urb->transfer_buffer_length,
2540                                                 status);
2541                         spin_unlock(&xhci->lock);
2542                         /* EHCI, UHCI, and OHCI always unconditionally set the
2543                          * urb->status of an isochronous endpoint to 0.
2544                          */
2545                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2546                                 status = 0;
2547                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2548                         spin_lock(&xhci->lock);
2549                 }
2550
2551         /*
2552          * If ep->skip is set, it means there are missed tds on the
2553          * endpoint ring need to take care of.
2554          * Process them as short transfer until reach the td pointed by
2555          * the event.
2556          */
2557         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2558
2559         return 0;
2560 }
2561
2562 /*
2563  * This function handles all OS-owned events on the event ring.  It may drop
2564  * xhci->lock between event processing (e.g. to pass up port status changes).
2565  * Returns >0 for "possibly more events to process" (caller should call again),
2566  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2567  */
2568 static int xhci_handle_event(struct xhci_hcd *xhci)
2569 {
2570         union xhci_trb *event;
2571         int update_ptrs = 1;
2572         int ret;
2573
2574         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2575                 xhci->error_bitmask |= 1 << 1;
2576                 return 0;
2577         }
2578
2579         event = xhci->event_ring->dequeue;
2580         /* Does the HC or OS own the TRB? */
2581         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2582             xhci->event_ring->cycle_state) {
2583                 xhci->error_bitmask |= 1 << 2;
2584                 return 0;
2585         }
2586
2587         /*
2588          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2589          * speculative reads of the event's flags/data below.
2590          */
2591         rmb();
2592         /* FIXME: Handle more event types. */
2593         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2594         case TRB_TYPE(TRB_COMPLETION):
2595                 handle_cmd_completion(xhci, &event->event_cmd);
2596                 break;
2597         case TRB_TYPE(TRB_PORT_STATUS):
2598                 handle_port_status(xhci, event);
2599                 update_ptrs = 0;
2600                 break;
2601         case TRB_TYPE(TRB_TRANSFER):
2602                 ret = handle_tx_event(xhci, &event->trans_event);
2603                 if (ret < 0)
2604                         xhci->error_bitmask |= 1 << 9;
2605                 else
2606                         update_ptrs = 0;
2607                 break;
2608         default:
2609                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2610                     TRB_TYPE(48))
2611                         handle_vendor_event(xhci, event);
2612                 else
2613                         xhci->error_bitmask |= 1 << 3;
2614         }
2615         /* Any of the above functions may drop and re-acquire the lock, so check
2616          * to make sure a watchdog timer didn't mark the host as non-responsive.
2617          */
2618         if (xhci->xhc_state & XHCI_STATE_DYING) {
2619                 xhci_dbg(xhci, "xHCI host dying, returning from "
2620                                 "event handler.\n");
2621                 return 0;
2622         }
2623
2624         if (update_ptrs)
2625                 /* Update SW event ring dequeue pointer */
2626                 inc_deq(xhci, xhci->event_ring, true);
2627
2628         /* Are there more items on the event ring?  Caller will call us again to
2629          * check.
2630          */
2631         return 1;
2632 }
2633
2634 /*
2635  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2636  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2637  * indicators of an event TRB error, but we check the status *first* to be safe.
2638  */
2639 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2640 {
2641         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2642         u32 status;
2643         union xhci_trb *trb;
2644         u64 temp_64;
2645         union xhci_trb *event_ring_deq;
2646         dma_addr_t deq;
2647
2648         spin_lock(&xhci->lock);
2649         trb = xhci->event_ring->dequeue;
2650         /* Check if the xHC generated the interrupt, or the irq is shared */
2651         status = xhci_readl(xhci, &xhci->op_regs->status);
2652         if (status == 0xffffffff)
2653                 goto hw_died;
2654
2655         if (!(status & STS_EINT)) {
2656                 spin_unlock(&xhci->lock);
2657                 return IRQ_NONE;
2658         }
2659         if (status & STS_FATAL) {
2660                 xhci_warn(xhci, "WARNING: Host System Error\n");
2661                 xhci_halt(xhci);
2662 hw_died:
2663                 spin_unlock(&xhci->lock);
2664                 return -ESHUTDOWN;
2665         }
2666
2667         /*
2668          * Clear the op reg interrupt status first,
2669          * so we can receive interrupts from other MSI-X interrupters.
2670          * Write 1 to clear the interrupt status.
2671          */
2672         status |= STS_EINT;
2673         xhci_writel(xhci, status, &xhci->op_regs->status);
2674         /* FIXME when MSI-X is supported and there are multiple vectors */
2675         /* Clear the MSI-X event interrupt status */
2676
2677         if (hcd->irq != -1) {
2678                 u32 irq_pending;
2679                 /* Acknowledge the PCI interrupt */
2680                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2681                 irq_pending |= IMAN_IP;
2682                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2683         }
2684
2685         if (xhci->xhc_state & XHCI_STATE_DYING) {
2686                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2687                                 "Shouldn't IRQs be disabled?\n");
2688                 /* Clear the event handler busy flag (RW1C);
2689                  * the event ring should be empty.
2690                  */
2691                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2692                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2693                                 &xhci->ir_set->erst_dequeue);
2694                 spin_unlock(&xhci->lock);
2695
2696                 return IRQ_HANDLED;
2697         }
2698
2699         event_ring_deq = xhci->event_ring->dequeue;
2700         /* FIXME this should be a delayed service routine
2701          * that clears the EHB.
2702          */
2703         while (xhci_handle_event(xhci) > 0) {}
2704
2705         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2706         /* If necessary, update the HW's version of the event ring deq ptr. */
2707         if (event_ring_deq != xhci->event_ring->dequeue) {
2708                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2709                                 xhci->event_ring->dequeue);
2710                 if (deq == 0)
2711                         xhci_warn(xhci, "WARN something wrong with SW event "
2712                                         "ring dequeue ptr.\n");
2713                 /* Update HC event ring dequeue pointer */
2714                 temp_64 &= ERST_PTR_MASK;
2715                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2716         }
2717
2718         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2719         temp_64 |= ERST_EHB;
2720         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2721
2722         spin_unlock(&xhci->lock);
2723
2724         return IRQ_HANDLED;
2725 }
2726
2727 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2728 {
2729         irqreturn_t ret;
2730         struct xhci_hcd *xhci;
2731
2732         xhci = hcd_to_xhci(hcd);
2733         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2734         if (xhci->shared_hcd)
2735                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2736
2737         ret = xhci_irq(hcd);
2738
2739         return ret;
2740 }
2741
2742 /****           Endpoint Ring Operations        ****/
2743
2744 /*
2745  * Generic function for queueing a TRB on a ring.
2746  * The caller must have checked to make sure there's room on the ring.
2747  *
2748  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2749  *                      prepare_transfer()?
2750  */
2751 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2752                 bool consumer, bool more_trbs_coming, bool isoc,
2753                 u32 field1, u32 field2, u32 field3, u32 field4)
2754 {
2755         struct xhci_generic_trb *trb;
2756
2757         trb = &ring->enqueue->generic;
2758         trb->field[0] = cpu_to_le32(field1);
2759         trb->field[1] = cpu_to_le32(field2);
2760         trb->field[2] = cpu_to_le32(field3);
2761         trb->field[3] = cpu_to_le32(field4);
2762         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2763 }
2764
2765 /*
2766  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2767  * FIXME allocate segments if the ring is full.
2768  */
2769 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2770                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2771 {
2772         /* Make sure the endpoint has been added to xHC schedule */
2773         switch (ep_state) {
2774         case EP_STATE_DISABLED:
2775                 /*
2776                  * USB core changed config/interfaces without notifying us,
2777                  * or hardware is reporting the wrong state.
2778                  */
2779                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2780                 return -ENOENT;
2781         case EP_STATE_ERROR:
2782                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2783                 /* FIXME event handling code for error needs to clear it */
2784                 /* XXX not sure if this should be -ENOENT or not */
2785                 return -EINVAL;
2786         case EP_STATE_HALTED:
2787                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2788         case EP_STATE_STOPPED:
2789         case EP_STATE_RUNNING:
2790                 break;
2791         default:
2792                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2793                 /*
2794                  * FIXME issue Configure Endpoint command to try to get the HC
2795                  * back into a known state.
2796                  */
2797                 return -EINVAL;
2798         }
2799         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2800                 /* FIXME allocate more room */
2801                 xhci_err(xhci, "ERROR no room on ep ring\n");
2802                 return -ENOMEM;
2803         }
2804
2805         if (enqueue_is_link_trb(ep_ring)) {
2806                 struct xhci_ring *ring = ep_ring;
2807                 union xhci_trb *next;
2808
2809                 next = ring->enqueue;
2810
2811                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2812                         /* If we're not dealing with 0.95 hardware or isoc rings
2813                          * on AMD 0.96 host, clear the chain bit.
2814                          */
2815                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2816                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2817                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2818                         else
2819                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2820
2821                         wmb();
2822                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2823
2824                         /* Toggle the cycle bit after the last ring segment. */
2825                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2826                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2827                                 if (!in_interrupt()) {
2828                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2829                                                 "state for ring %p = %i\n",
2830                                                 ring, (unsigned int)ring->cycle_state);
2831                                 }
2832                         }
2833                         ring->enq_seg = ring->enq_seg->next;
2834                         ring->enqueue = ring->enq_seg->trbs;
2835                         next = ring->enqueue;
2836                 }
2837         }
2838
2839         return 0;
2840 }
2841
2842 static int prepare_transfer(struct xhci_hcd *xhci,
2843                 struct xhci_virt_device *xdev,
2844                 unsigned int ep_index,
2845                 unsigned int stream_id,
2846                 unsigned int num_trbs,
2847                 struct urb *urb,
2848                 unsigned int td_index,
2849                 bool isoc,
2850                 gfp_t mem_flags)
2851 {
2852         int ret;
2853         struct urb_priv *urb_priv;
2854         struct xhci_td  *td;
2855         struct xhci_ring *ep_ring;
2856         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2857
2858         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2859         if (!ep_ring) {
2860                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2861                                 stream_id);
2862                 return -EINVAL;
2863         }
2864
2865         ret = prepare_ring(xhci, ep_ring,
2866                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2867                            num_trbs, isoc, mem_flags);
2868         if (ret)
2869                 return ret;
2870
2871         urb_priv = urb->hcpriv;
2872         td = urb_priv->td[td_index];
2873
2874         INIT_LIST_HEAD(&td->td_list);
2875         INIT_LIST_HEAD(&td->cancelled_td_list);
2876
2877         if (td_index == 0) {
2878                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2879                 if (unlikely(ret))
2880                         return ret;
2881         }
2882
2883         td->urb = urb;
2884         /* Add this TD to the tail of the endpoint ring's TD list */
2885         list_add_tail(&td->td_list, &ep_ring->td_list);
2886         td->start_seg = ep_ring->enq_seg;
2887         td->first_trb = ep_ring->enqueue;
2888
2889         urb_priv->td[td_index] = td;
2890
2891         return 0;
2892 }
2893
2894 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2895 {
2896         int num_sgs, num_trbs, running_total, temp, i;
2897         struct scatterlist *sg;
2898
2899         sg = NULL;
2900         num_sgs = urb->num_mapped_sgs;
2901         temp = urb->transfer_buffer_length;
2902
2903         xhci_dbg(xhci, "count sg list trbs: \n");
2904         num_trbs = 0;
2905         for_each_sg(urb->sg, sg, num_sgs, i) {
2906                 unsigned int previous_total_trbs = num_trbs;
2907                 unsigned int len = sg_dma_len(sg);
2908
2909                 /* Scatter gather list entries may cross 64KB boundaries */
2910                 running_total = TRB_MAX_BUFF_SIZE -
2911                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2912                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2913                 if (running_total != 0)
2914                         num_trbs++;
2915
2916                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2917                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2918                         num_trbs++;
2919                         running_total += TRB_MAX_BUFF_SIZE;
2920                 }
2921                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2922                                 i, (unsigned long long)sg_dma_address(sg),
2923                                 len, len, num_trbs - previous_total_trbs);
2924
2925                 len = min_t(int, len, temp);
2926                 temp -= len;
2927                 if (temp == 0)
2928                         break;
2929         }
2930         xhci_dbg(xhci, "\n");
2931         if (!in_interrupt())
2932                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2933                                 "num_trbs = %d\n",
2934                                 urb->ep->desc.bEndpointAddress,
2935                                 urb->transfer_buffer_length,
2936                                 num_trbs);
2937         return num_trbs;
2938 }
2939
2940 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2941 {
2942         if (num_trbs != 0)
2943                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2944                                 "TRBs, %d left\n", __func__,
2945                                 urb->ep->desc.bEndpointAddress, num_trbs);
2946         if (running_total != urb->transfer_buffer_length)
2947                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2948                                 "queued %#x (%d), asked for %#x (%d)\n",
2949                                 __func__,
2950                                 urb->ep->desc.bEndpointAddress,
2951                                 running_total, running_total,
2952                                 urb->transfer_buffer_length,
2953                                 urb->transfer_buffer_length);
2954 }
2955
2956 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2957                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2958                 struct xhci_generic_trb *start_trb)
2959 {
2960         /*
2961          * Pass all the TRBs to the hardware at once and make sure this write
2962          * isn't reordered.
2963          */
2964         wmb();
2965         if (start_cycle)
2966                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2967         else
2968                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2969         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2970 }
2971
2972 /*
2973  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2974  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2975  * (comprised of sg list entries) can take several service intervals to
2976  * transmit.
2977  */
2978 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2979                 struct urb *urb, int slot_id, unsigned int ep_index)
2980 {
2981         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2982                         xhci->devs[slot_id]->out_ctx, ep_index);
2983         int xhci_interval;
2984         int ep_interval;
2985
2986         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2987         ep_interval = urb->interval;
2988         /* Convert to microframes */
2989         if (urb->dev->speed == USB_SPEED_LOW ||
2990                         urb->dev->speed == USB_SPEED_FULL)
2991                 ep_interval *= 8;
2992         /* FIXME change this to a warning and a suggestion to use the new API
2993          * to set the polling interval (once the API is added).
2994          */
2995         if (xhci_interval != ep_interval) {
2996                 if (printk_ratelimit())
2997                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2998                                         " (%d microframe%s) than xHCI "
2999                                         "(%d microframe%s)\n",
3000                                         ep_interval,
3001                                         ep_interval == 1 ? "" : "s",
3002                                         xhci_interval,
3003                                         xhci_interval == 1 ? "" : "s");
3004                 urb->interval = xhci_interval;
3005                 /* Convert back to frames for LS/FS devices */
3006                 if (urb->dev->speed == USB_SPEED_LOW ||
3007                                 urb->dev->speed == USB_SPEED_FULL)
3008                         urb->interval /= 8;
3009         }
3010         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3011 }
3012
3013 /*
3014  * The TD size is the number of bytes remaining in the TD (including this TRB),
3015  * right shifted by 10.
3016  * It must fit in bits 21:17, so it can't be bigger than 31.
3017  */
3018 static u32 xhci_td_remainder(unsigned int remainder)
3019 {
3020         u32 max = (1 << (21 - 17 + 1)) - 1;
3021
3022         if ((remainder >> 10) >= max)
3023                 return max << 17;
3024         else
3025                 return (remainder >> 10) << 17;
3026 }
3027
3028 /*
3029  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3030  * packets remaining in the TD (*not* including this TRB).
3031  *
3032  * Total TD packet count = total_packet_count =
3033  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3034  *
3035  * Packets transferred up to and including this TRB = packets_transferred =
3036  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3037  *
3038  * TD size = total_packet_count - packets_transferred
3039  *
3040  * It must fit in bits 21:17, so it can't be bigger than 31.
3041  * The last TRB in a TD must have the TD size set to zero.
3042  */
3043 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3044                 unsigned int total_packet_count, struct urb *urb,
3045                 unsigned int num_trbs_left)
3046 {
3047         int packets_transferred;
3048
3049         /* One TRB with a zero-length data packet. */
3050         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3051                 return 0;
3052
3053         /* All the TRB queueing functions don't count the current TRB in
3054          * running_total.
3055          */
3056         packets_transferred = (running_total + trb_buff_len) /
3057                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3058
3059         if ((total_packet_count - packets_transferred) > 31)
3060                 return 31 << 17;
3061         return (total_packet_count - packets_transferred) << 17;
3062 }
3063
3064 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3065                 struct urb *urb, int slot_id, unsigned int ep_index)
3066 {
3067         struct xhci_ring *ep_ring;
3068         unsigned int num_trbs;
3069         struct urb_priv *urb_priv;
3070         struct xhci_td *td;
3071         struct scatterlist *sg;
3072         int num_sgs;
3073         int trb_buff_len, this_sg_len, running_total;
3074         unsigned int total_packet_count;
3075         bool first_trb;
3076         u64 addr;
3077         bool more_trbs_coming;
3078
3079         struct xhci_generic_trb *start_trb;
3080         int start_cycle;
3081
3082         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3083         if (!ep_ring)
3084                 return -EINVAL;
3085
3086         num_trbs = count_sg_trbs_needed(xhci, urb);
3087         num_sgs = urb->num_mapped_sgs;
3088         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3089                         usb_endpoint_maxp(&urb->ep->desc));
3090
3091         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3092                         ep_index, urb->stream_id,
3093                         num_trbs, urb, 0, false, mem_flags);
3094         if (trb_buff_len < 0)
3095                 return trb_buff_len;
3096
3097         urb_priv = urb->hcpriv;
3098         td = urb_priv->td[0];
3099
3100         /*
3101          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3102          * until we've finished creating all the other TRBs.  The ring's cycle
3103          * state may change as we enqueue the other TRBs, so save it too.
3104          */
3105         start_trb = &ep_ring->enqueue->generic;
3106         start_cycle = ep_ring->cycle_state;
3107
3108         running_total = 0;
3109         /*
3110          * How much data is in the first TRB?
3111          *
3112          * There are three forces at work for TRB buffer pointers and lengths:
3113          * 1. We don't want to walk off the end of this sg-list entry buffer.
3114          * 2. The transfer length that the driver requested may be smaller than
3115          *    the amount of memory allocated for this scatter-gather list.
3116          * 3. TRBs buffers can't cross 64KB boundaries.
3117          */
3118         sg = urb->sg;
3119         addr = (u64) sg_dma_address(sg);
3120         this_sg_len = sg_dma_len(sg);
3121         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3122         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3123         if (trb_buff_len > urb->transfer_buffer_length)
3124                 trb_buff_len = urb->transfer_buffer_length;
3125         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3126                         trb_buff_len);
3127
3128         first_trb = true;
3129         /* Queue the first TRB, even if it's zero-length */
3130         do {
3131                 u32 field = 0;
3132                 u32 length_field = 0;
3133                 u32 remainder = 0;
3134
3135                 /* Don't change the cycle bit of the first TRB until later */
3136                 if (first_trb) {
3137                         first_trb = false;
3138                         if (start_cycle == 0)
3139                                 field |= 0x1;
3140                 } else
3141                         field |= ep_ring->cycle_state;
3142
3143                 /* Chain all the TRBs together; clear the chain bit in the last
3144                  * TRB to indicate it's the last TRB in the chain.
3145                  */
3146                 if (num_trbs > 1) {
3147                         field |= TRB_CHAIN;
3148                 } else {
3149                         /* FIXME - add check for ZERO_PACKET flag before this */
3150                         td->last_trb = ep_ring->enqueue;
3151                         field |= TRB_IOC;
3152                 }
3153
3154                 /* Only set interrupt on short packet for IN endpoints */
3155                 if (usb_urb_dir_in(urb))
3156                         field |= TRB_ISP;
3157
3158                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3159                                 "64KB boundary at %#x, end dma = %#x\n",
3160                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
3161                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3162                                 (unsigned int) addr + trb_buff_len);
3163                 if (TRB_MAX_BUFF_SIZE -
3164                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3165                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3166                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3167                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3168                                         (unsigned int) addr + trb_buff_len);
3169                 }
3170
3171                 /* Set the TRB length, TD size, and interrupter fields. */
3172                 if (xhci->hci_version < 0x100) {
3173                         remainder = xhci_td_remainder(
3174                                         urb->transfer_buffer_length -
3175                                         running_total);
3176                 } else {
3177                         remainder = xhci_v1_0_td_remainder(running_total,
3178                                         trb_buff_len, total_packet_count, urb,
3179                                         num_trbs - 1);
3180                 }
3181                 length_field = TRB_LEN(trb_buff_len) |
3182                         remainder |
3183                         TRB_INTR_TARGET(0);
3184
3185                 if (num_trbs > 1)
3186                         more_trbs_coming = true;
3187                 else
3188                         more_trbs_coming = false;
3189                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3190                                 lower_32_bits(addr),
3191                                 upper_32_bits(addr),
3192                                 length_field,
3193                                 field | TRB_TYPE(TRB_NORMAL));
3194                 --num_trbs;
3195                 running_total += trb_buff_len;
3196
3197                 /* Calculate length for next transfer --
3198                  * Are we done queueing all the TRBs for this sg entry?
3199                  */
3200                 this_sg_len -= trb_buff_len;
3201                 if (this_sg_len == 0) {
3202                         --num_sgs;
3203                         if (num_sgs == 0)
3204                                 break;
3205                         sg = sg_next(sg);
3206                         addr = (u64) sg_dma_address(sg);
3207                         this_sg_len = sg_dma_len(sg);
3208                 } else {
3209                         addr += trb_buff_len;
3210                 }
3211
3212                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3213                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3214                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3215                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3216                         trb_buff_len =
3217                                 urb->transfer_buffer_length - running_total;
3218         } while (running_total < urb->transfer_buffer_length);
3219
3220         check_trb_math(urb, num_trbs, running_total);
3221         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3222                         start_cycle, start_trb);
3223         return 0;
3224 }
3225
3226 /* This is very similar to what ehci-q.c qtd_fill() does */
3227 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3228                 struct urb *urb, int slot_id, unsigned int ep_index)
3229 {
3230         struct xhci_ring *ep_ring;
3231         struct urb_priv *urb_priv;
3232         struct xhci_td *td;
3233         int num_trbs;
3234         struct xhci_generic_trb *start_trb;
3235         bool first_trb;
3236         bool more_trbs_coming;
3237         int start_cycle;
3238         u32 field, length_field;
3239
3240         int running_total, trb_buff_len, ret;
3241         unsigned int total_packet_count;
3242         u64 addr;
3243
3244         if (urb->num_sgs)
3245                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3246
3247         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3248         if (!ep_ring)
3249                 return -EINVAL;
3250
3251         num_trbs = 0;
3252         /* How much data is (potentially) left before the 64KB boundary? */
3253         running_total = TRB_MAX_BUFF_SIZE -
3254                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3255         running_total &= TRB_MAX_BUFF_SIZE - 1;
3256
3257         /* If there's some data on this 64KB chunk, or we have to send a
3258          * zero-length transfer, we need at least one TRB
3259          */
3260         if (running_total != 0 || urb->transfer_buffer_length == 0)
3261                 num_trbs++;
3262         /* How many more 64KB chunks to transfer, how many more TRBs? */
3263         while (running_total < urb->transfer_buffer_length) {
3264                 num_trbs++;
3265                 running_total += TRB_MAX_BUFF_SIZE;
3266         }
3267         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3268
3269         if (!in_interrupt())
3270                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3271                                 "addr = %#llx, num_trbs = %d\n",
3272                                 urb->ep->desc.bEndpointAddress,
3273                                 urb->transfer_buffer_length,
3274                                 urb->transfer_buffer_length,
3275                                 (unsigned long long)urb->transfer_dma,
3276                                 num_trbs);
3277
3278         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3279                         ep_index, urb->stream_id,
3280                         num_trbs, urb, 0, false, mem_flags);
3281         if (ret < 0)
3282                 return ret;
3283
3284         urb_priv = urb->hcpriv;
3285         td = urb_priv->td[0];
3286
3287         /*
3288          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3289          * until we've finished creating all the other TRBs.  The ring's cycle
3290          * state may change as we enqueue the other TRBs, so save it too.
3291          */
3292         start_trb = &ep_ring->enqueue->generic;
3293         start_cycle = ep_ring->cycle_state;
3294
3295         running_total = 0;
3296         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3297                         usb_endpoint_maxp(&urb->ep->desc));
3298         /* How much data is in the first TRB? */
3299         addr = (u64) urb->transfer_dma;
3300         trb_buff_len = TRB_MAX_BUFF_SIZE -
3301                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3302         if (trb_buff_len > urb->transfer_buffer_length)
3303                 trb_buff_len = urb->transfer_buffer_length;
3304
3305         first_trb = true;
3306
3307         /* Queue the first TRB, even if it's zero-length */
3308         do {
3309                 u32 remainder = 0;
3310                 field = 0;
3311
3312                 /* Don't change the cycle bit of the first TRB until later */
3313                 if (first_trb) {
3314                         first_trb = false;
3315                         if (start_cycle == 0)
3316                                 field |= 0x1;
3317                 } else
3318                         field |= ep_ring->cycle_state;
3319
3320                 /* Chain all the TRBs together; clear the chain bit in the last
3321                  * TRB to indicate it's the last TRB in the chain.
3322                  */
3323                 if (num_trbs > 1) {
3324                         field |= TRB_CHAIN;
3325                 } else {
3326                         /* FIXME - add check for ZERO_PACKET flag before this */
3327                         td->last_trb = ep_ring->enqueue;
3328                         field |= TRB_IOC;
3329                 }
3330
3331                 /* Only set interrupt on short packet for IN endpoints */
3332                 if (usb_urb_dir_in(urb))
3333                         field |= TRB_ISP;
3334
3335                 /* Set the TRB length, TD size, and interrupter fields. */
3336                 if (xhci->hci_version < 0x100) {
3337                         remainder = xhci_td_remainder(
3338                                         urb->transfer_buffer_length -
3339                                         running_total);
3340                 } else {
3341                         remainder = xhci_v1_0_td_remainder(running_total,
3342                                         trb_buff_len, total_packet_count, urb,
3343                                         num_trbs - 1);
3344                 }
3345                 length_field = TRB_LEN(trb_buff_len) |
3346                         remainder |
3347                         TRB_INTR_TARGET(0);
3348
3349                 if (num_trbs > 1)
3350                         more_trbs_coming = true;
3351                 else
3352                         more_trbs_coming = false;
3353                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3354                                 lower_32_bits(addr),
3355                                 upper_32_bits(addr),
3356                                 length_field,
3357                                 field | TRB_TYPE(TRB_NORMAL));
3358                 --num_trbs;
3359                 running_total += trb_buff_len;
3360
3361                 /* Calculate length for next transfer */
3362                 addr += trb_buff_len;
3363                 trb_buff_len = urb->transfer_buffer_length - running_total;
3364                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3365                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3366         } while (running_total < urb->transfer_buffer_length);
3367
3368         check_trb_math(urb, num_trbs, running_total);
3369         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3370                         start_cycle, start_trb);
3371         return 0;
3372 }
3373
3374 /* Caller must have locked xhci->lock */
3375 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3376                 struct urb *urb, int slot_id, unsigned int ep_index)
3377 {
3378         struct xhci_ring *ep_ring;
3379         int num_trbs;
3380         int ret;
3381         struct usb_ctrlrequest *setup;
3382         struct xhci_generic_trb *start_trb;
3383         int start_cycle;
3384         u32 field, length_field;
3385         struct urb_priv *urb_priv;
3386         struct xhci_td *td;
3387
3388         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3389         if (!ep_ring)
3390                 return -EINVAL;
3391
3392         /*
3393          * Need to copy setup packet into setup TRB, so we can't use the setup
3394          * DMA address.
3395          */
3396         if (!urb->setup_packet)
3397                 return -EINVAL;
3398
3399         if (!in_interrupt())
3400                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3401                                 slot_id, ep_index);
3402         /* 1 TRB for setup, 1 for status */
3403         num_trbs = 2;
3404         /*
3405          * Don't need to check if we need additional event data and normal TRBs,
3406          * since data in control transfers will never get bigger than 16MB
3407          * XXX: can we get a buffer that crosses 64KB boundaries?
3408          */
3409         if (urb->transfer_buffer_length > 0)
3410                 num_trbs++;
3411         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3412                         ep_index, urb->stream_id,
3413                         num_trbs, urb, 0, false, mem_flags);
3414         if (ret < 0)
3415                 return ret;
3416
3417         urb_priv = urb->hcpriv;
3418         td = urb_priv->td[0];
3419
3420         /*
3421          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3422          * until we've finished creating all the other TRBs.  The ring's cycle
3423          * state may change as we enqueue the other TRBs, so save it too.
3424          */
3425         start_trb = &ep_ring->enqueue->generic;
3426         start_cycle = ep_ring->cycle_state;
3427
3428         /* Queue setup TRB - see section 6.4.1.2.1 */
3429         /* FIXME better way to translate setup_packet into two u32 fields? */
3430         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3431         field = 0;
3432         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3433         if (start_cycle == 0)
3434                 field |= 0x1;
3435
3436         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3437         if (xhci->hci_version == 0x100) {
3438                 if (urb->transfer_buffer_length > 0) {
3439                         if (setup->bRequestType & USB_DIR_IN)
3440                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3441                         else
3442                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3443                 }
3444         }
3445
3446         queue_trb(xhci, ep_ring, false, true, false,
3447                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3448                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3449                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3450                   /* Immediate data in pointer */
3451                   field);
3452
3453         /* If there's data, queue data TRBs */
3454         /* Only set interrupt on short packet for IN endpoints */
3455         if (usb_urb_dir_in(urb))
3456                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3457         else
3458                 field = TRB_TYPE(TRB_DATA);
3459
3460         length_field = TRB_LEN(urb->transfer_buffer_length) |
3461                 xhci_td_remainder(urb->transfer_buffer_length) |
3462                 TRB_INTR_TARGET(0);
3463         if (urb->transfer_buffer_length > 0) {
3464                 if (setup->bRequestType & USB_DIR_IN)
3465                         field |= TRB_DIR_IN;
3466                 queue_trb(xhci, ep_ring, false, true, false,
3467                                 lower_32_bits(urb->transfer_dma),
3468                                 upper_32_bits(urb->transfer_dma),
3469                                 length_field,
3470                                 field | ep_ring->cycle_state);
3471         }
3472
3473         /* Save the DMA address of the last TRB in the TD */
3474         td->last_trb = ep_ring->enqueue;
3475
3476         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3477         /* If the device sent data, the status stage is an OUT transfer */
3478         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3479                 field = 0;
3480         else
3481                 field = TRB_DIR_IN;
3482         queue_trb(xhci, ep_ring, false, false, false,
3483                         0,
3484                         0,
3485                         TRB_INTR_TARGET(0),
3486                         /* Event on completion */
3487                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3488
3489         giveback_first_trb(xhci, slot_id, ep_index, 0,
3490                         start_cycle, start_trb);
3491         return 0;
3492 }
3493
3494 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3495                 struct urb *urb, int i)
3496 {
3497         int num_trbs = 0;
3498         u64 addr, td_len;
3499
3500         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3501         td_len = urb->iso_frame_desc[i].length;
3502
3503         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3504                         TRB_MAX_BUFF_SIZE);
3505         if (num_trbs == 0)
3506                 num_trbs++;
3507
3508         return num_trbs;
3509 }
3510
3511 /*
3512  * The transfer burst count field of the isochronous TRB defines the number of
3513  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3514  * devices can burst up to bMaxBurst number of packets per service interval.
3515  * This field is zero based, meaning a value of zero in the field means one
3516  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3517  * zero.  Only xHCI 1.0 host controllers support this field.
3518  */
3519 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3520                 struct usb_device *udev,
3521                 struct urb *urb, unsigned int total_packet_count)
3522 {
3523         unsigned int max_burst;
3524
3525         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3526                 return 0;
3527
3528         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3529         return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3530 }
3531
3532 /*
3533  * Returns the number of packets in the last "burst" of packets.  This field is
3534  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3535  * the last burst packet count is equal to the total number of packets in the
3536  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3537  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3538  * contain 1 to (bMaxBurst + 1) packets.
3539  */
3540 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3541                 struct usb_device *udev,
3542                 struct urb *urb, unsigned int total_packet_count)
3543 {
3544         unsigned int max_burst;
3545         unsigned int residue;
3546
3547         if (xhci->hci_version < 0x100)
3548                 return 0;
3549
3550         switch (udev->speed) {
3551         case USB_SPEED_SUPER:
3552                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3553                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3554                 residue = total_packet_count % (max_burst + 1);
3555                 /* If residue is zero, the last burst contains (max_burst + 1)
3556                  * number of packets, but the TLBPC field is zero-based.
3557                  */
3558                 if (residue == 0)
3559                         return max_burst;
3560                 return residue - 1;
3561         default:
3562                 if (total_packet_count == 0)
3563                         return 0;
3564                 return total_packet_count - 1;
3565         }
3566 }
3567
3568 /* This is for isoc transfer */
3569 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3570                 struct urb *urb, int slot_id, unsigned int ep_index)
3571 {
3572         struct xhci_ring *ep_ring;
3573         struct urb_priv *urb_priv;
3574         struct xhci_td *td;
3575         int num_tds, trbs_per_td;
3576         struct xhci_generic_trb *start_trb;
3577         bool first_trb;
3578         int start_cycle;
3579         u32 field, length_field;
3580         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3581         u64 start_addr, addr;
3582         int i, j;
3583         bool more_trbs_coming;
3584
3585         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3586
3587         num_tds = urb->number_of_packets;
3588         if (num_tds < 1) {
3589                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3590                 return -EINVAL;
3591         }
3592
3593         if (!in_interrupt())
3594                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3595                                 " addr = %#llx, num_tds = %d\n",
3596                                 urb->ep->desc.bEndpointAddress,
3597                                 urb->transfer_buffer_length,
3598                                 urb->transfer_buffer_length,
3599                                 (unsigned long long)urb->transfer_dma,
3600                                 num_tds);
3601
3602         start_addr = (u64) urb->transfer_dma;
3603         start_trb = &ep_ring->enqueue->generic;
3604         start_cycle = ep_ring->cycle_state;
3605
3606         urb_priv = urb->hcpriv;
3607         /* Queue the first TRB, even if it's zero-length */
3608         for (i = 0; i < num_tds; i++) {
3609                 unsigned int total_packet_count;
3610                 unsigned int burst_count;
3611                 unsigned int residue;
3612
3613                 first_trb = true;
3614                 running_total = 0;
3615                 addr = start_addr + urb->iso_frame_desc[i].offset;
3616                 td_len = urb->iso_frame_desc[i].length;
3617                 td_remain_len = td_len;
3618                 total_packet_count = DIV_ROUND_UP(td_len,
3619                                 GET_MAX_PACKET(
3620                                         usb_endpoint_maxp(&urb->ep->desc)));
3621                 /* A zero-length transfer still involves at least one packet. */
3622                 if (total_packet_count == 0)
3623                         total_packet_count++;
3624                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3625                                 total_packet_count);
3626                 residue = xhci_get_last_burst_packet_count(xhci,
3627                                 urb->dev, urb, total_packet_count);
3628
3629                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3630
3631                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3632                                 urb->stream_id, trbs_per_td, urb, i, true,
3633                                 mem_flags);
3634                 if (ret < 0) {
3635                         if (i == 0)
3636                                 return ret;
3637                         goto cleanup;
3638                 }
3639
3640                 td = urb_priv->td[i];
3641                 for (j = 0; j < trbs_per_td; j++) {
3642                         u32 remainder = 0;
3643                         field = 0;
3644
3645                         if (first_trb) {
3646                                 field = TRB_TBC(burst_count) |
3647                                         TRB_TLBPC(residue);
3648                                 /* Queue the isoc TRB */
3649                                 field |= TRB_TYPE(TRB_ISOC);
3650                                 /* Assume URB_ISO_ASAP is set */
3651                                 field |= TRB_SIA;
3652                                 if (i == 0) {
3653                                         if (start_cycle == 0)
3654                                                 field |= 0x1;
3655                                 } else
3656                                         field |= ep_ring->cycle_state;
3657                                 first_trb = false;
3658                         } else {
3659                                 /* Queue other normal TRBs */
3660                                 field |= TRB_TYPE(TRB_NORMAL);
3661                                 field |= ep_ring->cycle_state;
3662                         }
3663
3664                         /* Only set interrupt on short packet for IN EPs */
3665                         if (usb_urb_dir_in(urb))
3666                                 field |= TRB_ISP;
3667
3668                         /* Chain all the TRBs together; clear the chain bit in
3669                          * the last TRB to indicate it's the last TRB in the
3670                          * chain.
3671                          */
3672                         if (j < trbs_per_td - 1) {
3673                                 field |= TRB_CHAIN;
3674                                 more_trbs_coming = true;
3675                         } else {
3676                                 td->last_trb = ep_ring->enqueue;
3677                                 field |= TRB_IOC;
3678                                 if (xhci->hci_version == 0x100 &&
3679                                                 !(xhci->quirks &
3680                                                         XHCI_AVOID_BEI)) {
3681                                         /* Set BEI bit except for the last td */
3682                                         if (i < num_tds - 1)
3683                                                 field |= TRB_BEI;
3684                                 }
3685                                 more_trbs_coming = false;
3686                         }
3687
3688                         /* Calculate TRB length */
3689                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3690                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3691                         if (trb_buff_len > td_remain_len)
3692                                 trb_buff_len = td_remain_len;
3693
3694                         /* Set the TRB length, TD size, & interrupter fields. */
3695                         if (xhci->hci_version < 0x100) {
3696                                 remainder = xhci_td_remainder(
3697                                                 td_len - running_total);
3698                         } else {
3699                                 remainder = xhci_v1_0_td_remainder(
3700                                                 running_total, trb_buff_len,
3701                                                 total_packet_count, urb,
3702                                                 (trbs_per_td - j - 1));
3703                         }
3704                         length_field = TRB_LEN(trb_buff_len) |
3705                                 remainder |
3706                                 TRB_INTR_TARGET(0);
3707
3708                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3709                                 lower_32_bits(addr),
3710                                 upper_32_bits(addr),
3711                                 length_field,
3712                                 field);
3713                         running_total += trb_buff_len;
3714
3715                         addr += trb_buff_len;
3716                         td_remain_len -= trb_buff_len;
3717                 }
3718
3719                 /* Check TD length */
3720                 if (running_total != td_len) {
3721                         xhci_err(xhci, "ISOC TD length unmatch\n");
3722                         ret = -EINVAL;
3723                         goto cleanup;
3724                 }
3725         }
3726
3727         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3728                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3729                         usb_amd_quirk_pll_disable();
3730         }
3731         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3732
3733         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3734                         start_cycle, start_trb);
3735         return 0;
3736 cleanup:
3737         /* Clean up a partially enqueued isoc transfer. */
3738
3739         for (i--; i >= 0; i--)
3740                 list_del_init(&urb_priv->td[i]->td_list);
3741
3742         /* Use the first TD as a temporary variable to turn the TDs we've queued
3743          * into No-ops with a software-owned cycle bit. That way the hardware
3744          * won't accidentally start executing bogus TDs when we partially
3745          * overwrite them.  td->first_trb and td->start_seg are already set.
3746          */
3747         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3748         /* Every TRB except the first & last will have its cycle bit flipped. */
3749         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3750
3751         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3752         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3753         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3754         ep_ring->cycle_state = start_cycle;
3755         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3756         return ret;
3757 }
3758
3759 /*
3760  * Check transfer ring to guarantee there is enough room for the urb.
3761  * Update ISO URB start_frame and interval.
3762  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3763  * update the urb->start_frame by now.
3764  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3765  */
3766 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3767                 struct urb *urb, int slot_id, unsigned int ep_index)
3768 {
3769         struct xhci_virt_device *xdev;
3770         struct xhci_ring *ep_ring;
3771         struct xhci_ep_ctx *ep_ctx;
3772         int start_frame;
3773         int xhci_interval;
3774         int ep_interval;
3775         int num_tds, num_trbs, i;
3776         int ret;
3777
3778         xdev = xhci->devs[slot_id];
3779         ep_ring = xdev->eps[ep_index].ring;
3780         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3781
3782         num_trbs = 0;
3783         num_tds = urb->number_of_packets;
3784         for (i = 0; i < num_tds; i++)
3785                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3786
3787         /* Check the ring to guarantee there is enough room for the whole urb.
3788          * Do not insert any td of the urb to the ring if the check failed.
3789          */
3790         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3791                            num_trbs, true, mem_flags);
3792         if (ret)
3793                 return ret;
3794
3795         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3796         start_frame &= 0x3fff;
3797
3798         urb->start_frame = start_frame;
3799         if (urb->dev->speed == USB_SPEED_LOW ||
3800                         urb->dev->speed == USB_SPEED_FULL)
3801                 urb->start_frame >>= 3;
3802
3803         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3804         ep_interval = urb->interval;
3805         /* Convert to microframes */
3806         if (urb->dev->speed == USB_SPEED_LOW ||
3807                         urb->dev->speed == USB_SPEED_FULL)
3808                 ep_interval *= 8;
3809         /* FIXME change this to a warning and a suggestion to use the new API
3810          * to set the polling interval (once the API is added).
3811          */
3812         if (xhci_interval != ep_interval) {
3813                 if (printk_ratelimit())
3814                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3815                                         " (%d microframe%s) than xHCI "
3816                                         "(%d microframe%s)\n",
3817                                         ep_interval,
3818                                         ep_interval == 1 ? "" : "s",
3819                                         xhci_interval,
3820                                         xhci_interval == 1 ? "" : "s");
3821                 urb->interval = xhci_interval;
3822                 /* Convert back to frames for LS/FS devices */
3823                 if (urb->dev->speed == USB_SPEED_LOW ||
3824                                 urb->dev->speed == USB_SPEED_FULL)
3825                         urb->interval /= 8;
3826         }
3827         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3828 }
3829
3830 /****           Command Ring Operations         ****/
3831
3832 /* Generic function for queueing a command TRB on the command ring.
3833  * Check to make sure there's room on the command ring for one command TRB.
3834  * Also check that there's room reserved for commands that must not fail.
3835  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3836  * then only check for the number of reserved spots.
3837  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3838  * because the command event handler may want to resubmit a failed command.
3839  */
3840 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3841                 u32 field3, u32 field4, bool command_must_succeed)
3842 {
3843         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3844         int ret;
3845
3846         if (!command_must_succeed)
3847                 reserved_trbs++;
3848
3849         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3850                         reserved_trbs, false, GFP_ATOMIC);
3851         if (ret < 0) {
3852                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3853                 if (command_must_succeed)
3854                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3855                                         "unfailable commands failed.\n");
3856                 return ret;
3857         }
3858         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3859                         field3, field4 | xhci->cmd_ring->cycle_state);
3860         return 0;
3861 }
3862
3863 /* Queue a slot enable or disable request on the command ring */
3864 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3865 {
3866         return queue_command(xhci, 0, 0, 0,
3867                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3868 }
3869
3870 /* Queue an address device command TRB */
3871 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3872                 u32 slot_id)
3873 {
3874         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3875                         upper_32_bits(in_ctx_ptr), 0,
3876                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3877                         false);
3878 }
3879
3880 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3881                 u32 field1, u32 field2, u32 field3, u32 field4)
3882 {
3883         return queue_command(xhci, field1, field2, field3, field4, false);
3884 }
3885
3886 /* Queue a reset device command TRB */
3887 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3888 {
3889         return queue_command(xhci, 0, 0, 0,
3890                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3891                         false);
3892 }
3893
3894 /* Queue a configure endpoint command TRB */
3895 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3896                 u32 slot_id, bool command_must_succeed)
3897 {
3898         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3899                         upper_32_bits(in_ctx_ptr), 0,
3900                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3901                         command_must_succeed);
3902 }
3903
3904 /* Queue an evaluate context command TRB */
3905 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3906                 u32 slot_id)
3907 {
3908         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3909                         upper_32_bits(in_ctx_ptr), 0,
3910                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3911                         false);
3912 }
3913
3914 /*
3915  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3916  * activity on an endpoint that is about to be suspended.
3917  */
3918 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3919                 unsigned int ep_index, int suspend)
3920 {
3921         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3922         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3923         u32 type = TRB_TYPE(TRB_STOP_RING);
3924         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3925
3926         return queue_command(xhci, 0, 0, 0,
3927                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3928 }
3929
3930 /* Set Transfer Ring Dequeue Pointer command.
3931  * This should not be used for endpoints that have streams enabled.
3932  */
3933 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3934                 unsigned int ep_index, unsigned int stream_id,
3935                 struct xhci_segment *deq_seg,
3936                 union xhci_trb *deq_ptr, u32 cycle_state)
3937 {
3938         dma_addr_t addr;
3939         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3940         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3941         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3942         u32 type = TRB_TYPE(TRB_SET_DEQ);
3943         struct xhci_virt_ep *ep;
3944
3945         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3946         if (addr == 0) {
3947                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3948                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3949                                 deq_seg, deq_ptr);
3950                 return 0;
3951         }
3952         ep = &xhci->devs[slot_id]->eps[ep_index];
3953         if ((ep->ep_state & SET_DEQ_PENDING)) {
3954                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3955                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3956                 return 0;
3957         }
3958         ep->queued_deq_seg = deq_seg;
3959         ep->queued_deq_ptr = deq_ptr;
3960         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3961                         upper_32_bits(addr), trb_stream_id,
3962                         trb_slot_id | trb_ep_index | type, false);
3963 }
3964
3965 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3966                 unsigned int ep_index)
3967 {
3968         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3969         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3970         u32 type = TRB_TYPE(TRB_RESET_EP);
3971
3972         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3973                         false);
3974 }