2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
29 /* Device for a quirk */
30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
34 #define PCI_VENDOR_ID_ETRON 0x1b6f
35 #define PCI_DEVICE_ID_ASROCK_P67 0x7023
37 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
39 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
40 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
42 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
43 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
44 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
45 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
46 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
48 static const char hcd_name[] = "xhci_hcd";
50 /* called after powerup, by probe or system-pm "wakeup" */
51 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
54 * TODO: Implement finding debug ports later.
55 * TODO: see if there are any quirks that need to be added to handle
56 * new extended capabilities.
59 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
60 if (!pci_set_mwi(pdev))
61 xhci_dbg(xhci, "MWI active\n");
63 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
67 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
69 struct pci_dev *pdev = to_pci_dev(dev);
71 /* Look for vendor-specific quirks */
72 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
73 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
74 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
75 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
76 pdev->revision == 0x0) {
77 xhci->quirks |= XHCI_RESET_EP_QUIRK;
78 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
79 " endpoint cmd after reset endpoint\n");
81 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
82 pdev->revision == 0x4) {
83 xhci->quirks |= XHCI_SLOW_SUSPEND;
85 "QUIRK: Fresco Logic xHC revision %u"
86 "must be suspended extra slowly",
89 /* Fresco Logic confirms: all revisions of this chip do not
90 * support MSI, even though some of them claim to in their PCI
93 xhci->quirks |= XHCI_BROKEN_MSI;
94 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
95 "has broken MSI implementation\n",
97 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
100 if (pdev->vendor == PCI_VENDOR_ID_NEC)
101 xhci->quirks |= XHCI_NEC_HOST;
103 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
104 xhci->quirks |= XHCI_AMD_0x96_HOST;
107 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
108 xhci->quirks |= XHCI_AMD_PLL_FIX;
110 if (pdev->vendor == PCI_VENDOR_ID_AMD)
111 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
113 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
114 xhci->quirks |= XHCI_INTEL_HOST;
115 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
116 xhci->quirks |= XHCI_AVOID_BEI;
117 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
118 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
119 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
120 xhci->limit_active_eps = 64;
121 xhci->quirks |= XHCI_SW_BW_CHECKING;
123 * PPT desktop boards DH77EB and DH77DF will power back on after
124 * a few seconds of being shutdown. The fix for this is to
125 * switch the ports from xHCI to EHCI on shutdown. We can't use
126 * DMI information to find those particular boards (since each
127 * vendor will change the board name), so we have to key off all
130 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
132 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
133 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
134 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
135 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
136 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
138 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
139 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
140 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
141 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
142 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
143 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
144 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
145 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
146 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
148 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
149 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
150 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
151 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
152 xhci->quirks |= XHCI_MISSING_CAS;
154 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
155 pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
156 xhci->quirks |= XHCI_RESET_ON_RESUME;
157 xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
158 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
160 if (pdev->vendor == PCI_VENDOR_ID_VIA)
161 xhci->quirks |= XHCI_RESET_ON_RESUME;
163 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
164 pdev->device == 0x1142)
165 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
169 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
170 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
172 static void xhci_pme_quirk(struct xhci_hcd *xhci)
177 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
179 writel(val | BIT(28), reg);
183 /* called during probe() after chip reset completes */
184 static int xhci_pci_setup(struct usb_hcd *hcd)
186 struct xhci_hcd *xhci;
187 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
190 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
194 xhci = hcd_to_xhci(hcd);
195 if (!usb_hcd_is_primary_hcd(hcd))
198 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
199 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
201 /* Find any debug ports */
202 retval = xhci_pci_reinit(xhci, pdev);
211 * We need to register our own PCI probe function (instead of the USB core's
212 * function) in order to create a second roothub under xHCI.
214 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
217 struct xhci_hcd *xhci;
218 struct hc_driver *driver;
221 driver = (struct hc_driver *)id->driver_data;
222 /* Register the USB 2.0 roothub.
223 * FIXME: USB core must know to register the USB 2.0 roothub first.
224 * This is sort of silly, because we could just set the HCD driver flags
225 * to say USB 2.0, but I'm not sure what the implications would be in
226 * the other parts of the HCD code.
228 retval = usb_hcd_pci_probe(dev, id);
233 /* USB 2.0 roothub is stored in the PCI device now. */
234 hcd = dev_get_drvdata(&dev->dev);
235 xhci = hcd_to_xhci(hcd);
236 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
238 if (!xhci->shared_hcd) {
240 goto dealloc_usb2_hcd;
243 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
244 * is called by usb_add_hcd().
246 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
248 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
252 /* Roothub already marked as USB 3.0 speed */
256 usb_put_hcd(xhci->shared_hcd);
258 usb_hcd_pci_remove(dev);
262 static void xhci_pci_remove(struct pci_dev *dev)
264 struct xhci_hcd *xhci;
266 xhci = hcd_to_xhci(pci_get_drvdata(dev));
267 if (xhci->shared_hcd) {
268 usb_remove_hcd(xhci->shared_hcd);
269 usb_put_hcd(xhci->shared_hcd);
272 /* Workaround for spurious wakeups at shutdown with HSW */
273 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
274 pci_set_power_state(dev, PCI_D3hot);
276 usb_hcd_pci_remove(dev);
282 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
284 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
287 if (hcd->state != HC_STATE_SUSPENDED ||
288 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
291 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
292 xhci_pme_quirk(xhci);
294 retval = xhci_suspend(xhci, do_wakeup);
299 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
301 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
302 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
305 /* The BIOS on systems with the Intel Panther Point chipset may or may
306 * not support xHCI natively. That means that during system resume, it
307 * may switch the ports back to EHCI so that users can use their
308 * keyboard to select a kernel from GRUB after resume from hibernate.
310 * The BIOS is supposed to remember whether the OS had xHCI ports
311 * enabled before resume, and switch the ports back to xHCI when the
312 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
315 * Unconditionally switch the ports back to xHCI after a system resume.
316 * We can't tell whether the EHCI or xHCI controller will be resumed
317 * first, so we have to do the port switchover in both drivers. Writing
318 * a '1' to the port switchover registers should have no effect if the
319 * port was already switched over.
321 if (usb_is_intel_switchable_xhci(pdev))
322 usb_enable_xhci_ports(pdev);
324 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
325 xhci_pme_quirk(xhci);
327 retval = xhci_resume(xhci, hibernated);
330 #endif /* CONFIG_PM */
332 static const struct hc_driver xhci_pci_hc_driver = {
333 .description = hcd_name,
334 .product_desc = "xHCI Host Controller",
335 .hcd_priv_size = sizeof(struct xhci_hcd *),
338 * generic hardware linkage
341 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
344 * basic lifecycle operations
346 .reset = xhci_pci_setup,
349 .pci_suspend = xhci_pci_suspend,
350 .pci_resume = xhci_pci_resume,
353 .shutdown = xhci_shutdown,
356 * managing i/o requests and associated device resources
358 .urb_enqueue = xhci_urb_enqueue,
359 .urb_dequeue = xhci_urb_dequeue,
360 .alloc_dev = xhci_alloc_dev,
361 .free_dev = xhci_free_dev,
362 .alloc_streams = xhci_alloc_streams,
363 .free_streams = xhci_free_streams,
364 .add_endpoint = xhci_add_endpoint,
365 .drop_endpoint = xhci_drop_endpoint,
366 .endpoint_reset = xhci_endpoint_reset,
367 .check_bandwidth = xhci_check_bandwidth,
368 .reset_bandwidth = xhci_reset_bandwidth,
369 .address_device = xhci_address_device,
370 .update_hub_device = xhci_update_hub_device,
371 .reset_device = xhci_discover_or_reset_device,
376 .get_frame_number = xhci_get_frame,
378 /* Root hub support */
379 .hub_control = xhci_hub_control,
380 .hub_status_data = xhci_hub_status_data,
381 .bus_suspend = xhci_bus_suspend,
382 .bus_resume = xhci_bus_resume,
384 * call back when device connected and addressed
386 .update_device = xhci_update_device,
387 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
390 /*-------------------------------------------------------------------------*/
392 /* PCI driver selection metadata; PCI hotplugging uses this */
393 static const struct pci_device_id pci_ids[] = { {
394 /* handle any USB 3.0 xHCI controller */
395 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
396 .driver_data = (unsigned long) &xhci_pci_hc_driver,
398 { /* end: all zeroes */ }
400 MODULE_DEVICE_TABLE(pci, pci_ids);
402 /* pci driver glue; this is a "new style" PCI driver module */
403 static struct pci_driver xhci_pci_driver = {
404 .name = (char *) hcd_name,
407 .probe = xhci_pci_probe,
408 .remove = xhci_pci_remove,
409 /* suspend and resume implemented later */
411 .shutdown = usb_hcd_pci_shutdown,
414 .pm = &usb_hcd_pci_pm_ops
419 int __init xhci_register_pci(void)
421 return pci_register_driver(&xhci_pci_driver);
424 void __exit xhci_unregister_pci(void)
426 pci_unregister_driver(&xhci_pci_driver);