drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  38 {
  39         struct xhci_segment *seg;
  40         dma_addr_t      dma;
  41
  42         seg = kzalloc(sizeof *seg, flags);
  43         if (!seg)
  44                 return NULL;
  45         xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
  46
  47         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  48         if (!seg->trbs) {
  49                 kfree(seg);
  50                 return NULL;
  51         }
  52         xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
  53                         seg->trbs, (unsigned long long)dma);
  54
  55         memset(seg->trbs, 0, SEGMENT_SIZE);
  56         seg->dma = dma;
  57         seg->next = NULL;
  58
  59         return seg;
  60 }
  61
  62 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  63 {
  64         if (seg->trbs) {
  65                 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
  66                                 seg->trbs, (unsigned long long)seg->dma);
  67                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  68                 seg->trbs = NULL;
  69         }
  70         xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
  71         kfree(seg);
  72 }
  73
  74 /*
  75  * Make the prev segment point to the next segment.
  76  *
  77  * Change the last TRB in the prev segment to be a Link TRB which points to the
  78  * DMA address of the next segment.  The caller needs to set any Link TRB
  79  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  80  */
  81 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  82                 struct xhci_segment *next, bool link_trbs, bool isoc)
  83 {
  84         u32 val;
  85
  86         if (!prev || !next)
  87                 return;
  88         prev->next = next;
  89         if (link_trbs) {
  90                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
  91                         cpu_to_le64(next->dma);
  92
  93                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  94                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  95                 val &= ~TRB_TYPE_BITMASK;
  96                 val |= TRB_TYPE(TRB_LINK);
  97                 /* Always set the chain bit with 0.95 hardware */
  98                 /* Set chain bit for isoc rings on AMD 0.96 host */
  99                 if (xhci_link_trb_quirk(xhci) ||
 100                                 (isoc && (xhci->quirks & XHCI_AMD_0x96_HOST)))
 101                         val |= TRB_CHAIN;
 102                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 103         }
 104         xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
 105                         (unsigned long long)prev->dma,
 106                         (unsigned long long)next->dma);
 107 }
 108
 109 /* XXX: Do we need the hcd structure in all these functions? */
 110 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 111 {
 112         struct xhci_segment *seg;
 113         struct xhci_segment *first_seg;
 114
 115         if (!ring)
 116                 return;
 117         if (ring->first_seg) {
 118                 first_seg = ring->first_seg;
 119                 seg = first_seg->next;
 120                 xhci_dbg(xhci, "Freeing ring at %p\n", ring);
 121                 while (seg != first_seg) {
 122                         struct xhci_segment *next = seg->next;
 123                         xhci_segment_free(xhci, seg);
 124                         seg = next;
 125                 }
 126                 xhci_segment_free(xhci, first_seg);
 127                 ring->first_seg = NULL;
 128         }
 129         kfree(ring);
 130 }
 131
 132 static void xhci_initialize_ring_info(struct xhci_ring *ring)
 133 {
 134         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 135         ring->enqueue = ring->first_seg->trbs;
 136         ring->enq_seg = ring->first_seg;
 137         ring->dequeue = ring->enqueue;
 138         ring->deq_seg = ring->first_seg;
 139         /* The ring is initialized to 0. The producer must write 1 to the cycle
 140          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 141          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 142          */
 143         ring->cycle_state = 1;
 144         /* Not necessary for new rings, but needed for re-initialized rings */
 145         ring->enq_updates = 0;
 146         ring->deq_updates = 0;
 147 }
 148
 149 /**
 150  * Create a new ring with zero or more segments.
 151  *
 152  * Link each segment together into a ring.
 153  * Set the end flag and the cycle toggle bit on the last segment.
 154  * See section 4.9.1 and figures 15 and 16.
 155  */
 156 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 157                 unsigned int num_segs, bool link_trbs, bool isoc, gfp_t flags)
 158 {
 159         struct xhci_ring        *ring;
 160         struct xhci_segment     *prev;
 161
 162         ring = kzalloc(sizeof *(ring), flags);
 163         xhci_dbg(xhci, "Allocating ring at %p\n", ring);
 164         if (!ring)
 165                 return NULL;
 166
 167         INIT_LIST_HEAD(&ring->td_list);
 168         if (num_segs == 0)
 169                 return ring;
 170
 171         ring->first_seg = xhci_segment_alloc(xhci, flags);
 172         if (!ring->first_seg)
 173                 goto fail;
 174         num_segs--;
 175
 176         prev = ring->first_seg;
 177         while (num_segs > 0) {
 178                 struct xhci_segment     *next;
 179
 180                 next = xhci_segment_alloc(xhci, flags);
 181                 if (!next)
 182                         goto fail;
 183                 xhci_link_segments(xhci, prev, next, link_trbs, isoc);
 184
 185                 prev = next;
 186                 num_segs--;
 187         }
 188         xhci_link_segments(xhci, prev, ring->first_seg, link_trbs, isoc);
 189
 190         if (link_trbs) {
 191                 /* See section 4.9.2.1 and 6.4.4.1 */
 192                 prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
 193                         cpu_to_le32(LINK_TOGGLE);
 194                 xhci_dbg(xhci, "Wrote link toggle flag to"
 195                                 " segment %p (virtual), 0x%llx (DMA)\n",
 196                                 prev, (unsigned long long)prev->dma);
 197         }
 198         xhci_initialize_ring_info(ring);
 199         return ring;
 200
 201 fail:
 202         xhci_ring_free(xhci, ring);
 203         return NULL;
 204 }
 205
 206 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 207                 struct xhci_virt_device *virt_dev,
 208                 unsigned int ep_index)
 209 {
 210         int rings_cached;
 211
 212         rings_cached = virt_dev->num_rings_cached;
 213         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 214                 virt_dev->ring_cache[rings_cached] =
 215                         virt_dev->eps[ep_index].ring;
 216                 virt_dev->num_rings_cached++;
 217                 xhci_dbg(xhci, "Cached old ring, "
 218                                 "%d ring%s cached\n",
 219                                 virt_dev->num_rings_cached,
 220                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 221         } else {
 222                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 223                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 224                                 "freeing ring\n",
 225                                 virt_dev->num_rings_cached);
 226         }
 227         virt_dev->eps[ep_index].ring = NULL;
 228 }
 229
 230 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 231  * pointers to the beginning of the ring.
 232  */
 233 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 234                 struct xhci_ring *ring, bool isoc)
 235 {
 236         struct xhci_segment     *seg = ring->first_seg;
 237         do {
 238                 memset(seg->trbs, 0,
 239                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 240                 /* All endpoint rings have link TRBs */
 241                 xhci_link_segments(xhci, seg, seg->next, 1, isoc);
 242                 seg = seg->next;
 243         } while (seg != ring->first_seg);
 244         xhci_initialize_ring_info(ring);
 245         /* td list should be empty since all URBs have been cancelled,
 246          * but just in case...
 247          */
 248         INIT_LIST_HEAD(&ring->td_list);
 249 }
 250
 251 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 252
 253 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 254                                                     int type, gfp_t flags)
 255 {
 256         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 257         if (!ctx)
 258                 return NULL;
 259
 260         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 261         ctx->type = type;
 262         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 263         if (type == XHCI_CTX_TYPE_INPUT)
 264                 ctx->size += CTX_SIZE(xhci->hcc_params);
 265
 266         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 267         memset(ctx->bytes, 0, ctx->size);
 268         return ctx;
 269 }
 270
 271 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 272                              struct xhci_container_ctx *ctx)
 273 {
 274         if (!ctx)
 275                 return;
 276         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 277         kfree(ctx);
 278 }
 279
 280 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 281                                               struct xhci_container_ctx *ctx)
 282 {
 283         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 284         return (struct xhci_input_control_ctx *)ctx->bytes;
 285 }
 286
 287 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 288                                         struct xhci_container_ctx *ctx)
 289 {
 290         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 291                 return (struct xhci_slot_ctx *)ctx->bytes;
 292
 293         return (struct xhci_slot_ctx *)
 294                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 295 }
 296
 297 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 298                                     struct xhci_container_ctx *ctx,
 299                                     unsigned int ep_index)
 300 {
 301         /* increment ep index by offset of start of ep ctx array */
 302         ep_index++;
 303         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 304                 ep_index++;
 305
 306         return (struct xhci_ep_ctx *)
 307                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 308 }
 309
 310
 311 /***************** Streams structures manipulation *************************/
 312
 313 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 314                 unsigned int num_stream_ctxs,
 315                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 316 {
 317         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 318
 319         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 320                 dma_free_coherent(&pdev->dev,
 321                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 322                                 stream_ctx, dma);
 323         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 324                 return dma_pool_free(xhci->small_streams_pool,
 325                                 stream_ctx, dma);
 326         else
 327                 return dma_pool_free(xhci->medium_streams_pool,
 328                                 stream_ctx, dma);
 329 }
 330
 331 /*
 332  * The stream context array for each endpoint with bulk streams enabled can
 333  * vary in size, based on:
 334  *  - how many streams the endpoint supports,
 335  *  - the maximum primary stream array size the host controller supports,
 336  *  - and how many streams the device driver asks for.
 337  *
 338  * The stream context array must be a power of 2, and can be as small as
 339  * 64 bytes or as large as 1MB.
 340  */
 341 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 342                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 343                 gfp_t mem_flags)
 344 {
 345         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 346
 347         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 348                 return dma_alloc_coherent(&pdev->dev,
 349                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 350                                 dma, mem_flags);
 351         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 352                 return dma_pool_alloc(xhci->small_streams_pool,
 353                                 mem_flags, dma);
 354         else
 355                 return dma_pool_alloc(xhci->medium_streams_pool,
 356                                 mem_flags, dma);
 357 }
 358
 359 struct xhci_ring *xhci_dma_to_transfer_ring(
 360                 struct xhci_virt_ep *ep,
 361                 u64 address)
 362 {
 363         if (ep->ep_state & EP_HAS_STREAMS)
 364                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 365                                 address >> SEGMENT_SHIFT);
 366         return ep->ring;
 367 }
 368
 369 /* Only use this when you know stream_info is valid */
 370 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 371 static struct xhci_ring *dma_to_stream_ring(
 372                 struct xhci_stream_info *stream_info,
 373                 u64 address)
 374 {
 375         return radix_tree_lookup(&stream_info->trb_address_map,
 376                         address >> SEGMENT_SHIFT);
 377 }
 378 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 379
 380 struct xhci_ring *xhci_stream_id_to_ring(
 381                 struct xhci_virt_device *dev,
 382                 unsigned int ep_index,
 383                 unsigned int stream_id)
 384 {
 385         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 386
 387         if (stream_id == 0)
 388                 return ep->ring;
 389         if (!ep->stream_info)
 390                 return NULL;
 391
 392         if (stream_id > ep->stream_info->num_streams)
 393                 return NULL;
 394         return ep->stream_info->stream_rings[stream_id];
 395 }
 396
 397 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 398 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 399                 unsigned int num_streams,
 400                 struct xhci_stream_info *stream_info)
 401 {
 402         u32 cur_stream;
 403         struct xhci_ring *cur_ring;
 404         u64 addr;
 405
 406         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 407                 struct xhci_ring *mapped_ring;
 408                 int trb_size = sizeof(union xhci_trb);
 409
 410                 cur_ring = stream_info->stream_rings[cur_stream];
 411                 for (addr = cur_ring->first_seg->dma;
 412                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
 413                                 addr += trb_size) {
 414                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 415                         if (cur_ring != mapped_ring) {
 416                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 417                                                 "didn't map to stream ID %u; "
 418                                                 "mapped to ring %p\n",
 419                                                 (unsigned long long) addr,
 420                                                 cur_stream,
 421                                                 mapped_ring);
 422                                 return -EINVAL;
 423                         }
 424                 }
 425                 /* One TRB after the end of the ring segment shouldn't return a
 426                  * pointer to the current ring (although it may be a part of a
 427                  * different ring).
 428                  */
 429                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 430                 if (mapped_ring != cur_ring) {
 431                         /* One TRB before should also fail */
 432                         addr = cur_ring->first_seg->dma - trb_size;
 433                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 434                 }
 435                 if (mapped_ring == cur_ring) {
 436                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 437                                         "mapped to valid stream ID %u; "
 438                                         "mapped ring = %p\n",
 439                                         (unsigned long long) addr,
 440                                         cur_stream,
 441                                         mapped_ring);
 442                         return -EINVAL;
 443                 }
 444         }
 445         return 0;
 446 }
 447 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 448
 449 /*
 450  * Change an endpoint's internal structure so it supports stream IDs.  The
 451  * number of requested streams includes stream 0, which cannot be used by device
 452  * drivers.
 453  *
 454  * The number of stream contexts in the stream context array may be bigger than
 455  * the number of streams the driver wants to use.  This is because the number of
 456  * stream context array entries must be a power of two.
 457  *
 458  * We need a radix tree for mapping physical addresses of TRBs to which stream
 459  * ID they belong to.  We need to do this because the host controller won't tell
 460  * us which stream ring the TRB came from.  We could store the stream ID in an
 461  * event data TRB, but that doesn't help us for the cancellation case, since the
 462  * endpoint may stop before it reaches that event data TRB.
 463  *
 464  * The radix tree maps the upper portion of the TRB DMA address to a ring
 465  * segment that has the same upper portion of DMA addresses.  For example, say I
 466  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 467  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 468  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 469  * pass the radix tree a key to get the right stream ID:
 470  *
 471  *      0x10c90fff >> 10 = 0x43243
 472  *      0x10c912c0 >> 10 = 0x43244
 473  *      0x10c91400 >> 10 = 0x43245
 474  *
 475  * Obviously, only those TRBs with DMA addresses that are within the segment
 476  * will make the radix tree return the stream ID for that ring.
 477  *
 478  * Caveats for the radix tree:
 479  *
 480  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 481  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 482  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 483  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 484  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 485  * extended systems (where the DMA address can be bigger than 32-bits),
 486  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 487  */
 488 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 489                 unsigned int num_stream_ctxs,
 490                 unsigned int num_streams, gfp_t mem_flags)
 491 {
 492         struct xhci_stream_info *stream_info;
 493         u32 cur_stream;
 494         struct xhci_ring *cur_ring;
 495         unsigned long key;
 496         u64 addr;
 497         int ret;
 498
 499         xhci_dbg(xhci, "Allocating %u streams and %u "
 500                         "stream context array entries.\n",
 501                         num_streams, num_stream_ctxs);
 502         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 503                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 504                 return NULL;
 505         }
 506         xhci->cmd_ring_reserved_trbs++;
 507
 508         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 509         if (!stream_info)
 510                 goto cleanup_trbs;
 511
 512         stream_info->num_streams = num_streams;
 513         stream_info->num_stream_ctxs = num_stream_ctxs;
 514
 515         /* Initialize the array of virtual pointers to stream rings. */
 516         stream_info->stream_rings = kzalloc(
 517                         sizeof(struct xhci_ring *)*num_streams,
 518                         mem_flags);
 519         if (!stream_info->stream_rings)
 520                 goto cleanup_info;
 521
 522         /* Initialize the array of DMA addresses for stream rings for the HW. */
 523         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 524                         num_stream_ctxs, &stream_info->ctx_array_dma,
 525                         mem_flags);
 526         if (!stream_info->stream_ctx_array)
 527                 goto cleanup_ctx;
 528         memset(stream_info->stream_ctx_array, 0,
 529                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 530
 531         /* Allocate everything needed to free the stream rings later */
 532         stream_info->free_streams_command =
 533                 xhci_alloc_command(xhci, true, true, mem_flags);
 534         if (!stream_info->free_streams_command)
 535                 goto cleanup_ctx;
 536
 537         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 538
 539         /* Allocate rings for all the streams that the driver will use,
 540          * and add their segment DMA addresses to the radix tree.
 541          * Stream 0 is reserved.
 542          */
 543         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 544                 stream_info->stream_rings[cur_stream] =
 545                         xhci_ring_alloc(xhci, 1, true, false, mem_flags);
 546                 cur_ring = stream_info->stream_rings[cur_stream];
 547                 if (!cur_ring)
 548                         goto cleanup_rings;
 549                 cur_ring->stream_id = cur_stream;
 550                 /* Set deq ptr, cycle bit, and stream context type */
 551                 addr = cur_ring->first_seg->dma |
 552                         SCT_FOR_CTX(SCT_PRI_TR) |
 553                         cur_ring->cycle_state;
 554                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 555                         cpu_to_le64(addr);
 556                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 557                                 cur_stream, (unsigned long long) addr);
 558
 559                 key = (unsigned long)
 560                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
 561                 ret = radix_tree_insert(&stream_info->trb_address_map,
 562                                 key, cur_ring);
 563                 if (ret) {
 564                         xhci_ring_free(xhci, cur_ring);
 565                         stream_info->stream_rings[cur_stream] = NULL;
 566                         goto cleanup_rings;
 567                 }
 568         }
 569         /* Leave the other unused stream ring pointers in the stream context
 570          * array initialized to zero.  This will cause the xHC to give us an
 571          * error if the device asks for a stream ID we don't have setup (if it
 572          * was any other way, the host controller would assume the ring is
 573          * "empty" and wait forever for data to be queued to that stream ID).
 574          */
 575 #if XHCI_DEBUG
 576         /* Do a little test on the radix tree to make sure it returns the
 577          * correct values.
 578          */
 579         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 580                 goto cleanup_rings;
 581 #endif
 582
 583         return stream_info;
 584
 585 cleanup_rings:
 586         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 587                 cur_ring = stream_info->stream_rings[cur_stream];
 588                 if (cur_ring) {
 589                         addr = cur_ring->first_seg->dma;
 590                         radix_tree_delete(&stream_info->trb_address_map,
 591                                         addr >> SEGMENT_SHIFT);
 592                         xhci_ring_free(xhci, cur_ring);
 593                         stream_info->stream_rings[cur_stream] = NULL;
 594                 }
 595         }
 596         xhci_free_command(xhci, stream_info->free_streams_command);
 597 cleanup_ctx:
 598         kfree(stream_info->stream_rings);
 599 cleanup_info:
 600         kfree(stream_info);
 601 cleanup_trbs:
 602         xhci->cmd_ring_reserved_trbs--;
 603         return NULL;
 604 }
 605 /*
 606  * Sets the MaxPStreams field and the Linear Stream Array field.
 607  * Sets the dequeue pointer to the stream context array.
 608  */
 609 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 610                 struct xhci_ep_ctx *ep_ctx,
 611                 struct xhci_stream_info *stream_info)
 612 {
 613         u32 max_primary_streams;
 614         /* MaxPStreams is the number of stream context array entries, not the
 615          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 616          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 617          */
 618         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 619         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 620                         1 << (max_primary_streams + 1));
 621         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 622         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 623                                        | EP_HAS_LSA);
 624         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 625 }
 626
 627 /*
 628  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 629  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 630  * not at the beginning of the ring).
 631  */
 632 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 633                 struct xhci_ep_ctx *ep_ctx,
 634                 struct xhci_virt_ep *ep)
 635 {
 636         dma_addr_t addr;
 637         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 638         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 639         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 640 }
 641
 642 /* Frees all stream contexts associated with the endpoint,
 643  *
 644  * Caller should fix the endpoint context streams fields.
 645  */
 646 void xhci_free_stream_info(struct xhci_hcd *xhci,
 647                 struct xhci_stream_info *stream_info)
 648 {
 649         int cur_stream;
 650         struct xhci_ring *cur_ring;
 651         dma_addr_t addr;
 652
 653         if (!stream_info)
 654                 return;
 655
 656         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 657                         cur_stream++) {
 658                 cur_ring = stream_info->stream_rings[cur_stream];
 659                 if (cur_ring) {
 660                         addr = cur_ring->first_seg->dma;
 661                         radix_tree_delete(&stream_info->trb_address_map,
 662                                         addr >> SEGMENT_SHIFT);
 663                         xhci_ring_free(xhci, cur_ring);
 664                         stream_info->stream_rings[cur_stream] = NULL;
 665                 }
 666         }
 667         xhci_free_command(xhci, stream_info->free_streams_command);
 668         xhci->cmd_ring_reserved_trbs--;
 669         if (stream_info->stream_ctx_array)
 670                 xhci_free_stream_ctx(xhci,
 671                                 stream_info->num_stream_ctxs,
 672                                 stream_info->stream_ctx_array,
 673                                 stream_info->ctx_array_dma);
 674
 675         if (stream_info)
 676                 kfree(stream_info->stream_rings);
 677         kfree(stream_info);
 678 }
 679
 680
 681 /***************** Device context manipulation *************************/
 682
 683 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 684                 struct xhci_virt_ep *ep)
 685 {
 686         init_timer(&ep->stop_cmd_timer);
 687         ep->stop_cmd_timer.data = (unsigned long) ep;
 688         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 689         ep->xhci = xhci;
 690 }
 691
 692 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 693                 struct xhci_virt_device *virt_dev,
 694                 int slot_id)
 695 {
 696         struct list_head *tt_list_head;
 697         struct xhci_tt_bw_info *tt_info, *next;
 698         bool slot_found = false;
 699
 700         /* If the device never made it past the Set Address stage,
 701          * it may not have the real_port set correctly.
 702          */
 703         if (virt_dev->real_port == 0 ||
 704                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 705                 xhci_dbg(xhci, "Bad real port.\n");
 706                 return;
 707         }
 708
 709         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 710         list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 711                 /* Multi-TT hubs will have more than one entry */
 712                 if (tt_info->slot_id == slot_id) {
 713                         slot_found = true;
 714                         list_del(&tt_info->tt_list);
 715                         kfree(tt_info);
 716                 } else if (slot_found) {
 717                         break;
 718                 }
 719         }
 720 }
 721
 722 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 723                 struct xhci_virt_device *virt_dev,
 724                 struct usb_device *hdev,
 725                 struct usb_tt *tt, gfp_t mem_flags)
 726 {
 727         struct xhci_tt_bw_info          *tt_info;
 728         unsigned int                    num_ports;
 729         int                             i, j;
 730
 731         if (!tt->multi)
 732                 num_ports = 1;
 733         else
 734                 num_ports = hdev->maxchild;
 735
 736         for (i = 0; i < num_ports; i++, tt_info++) {
 737                 struct xhci_interval_bw_table *bw_table;
 738
 739                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 740                 if (!tt_info)
 741                         goto free_tts;
 742                 INIT_LIST_HEAD(&tt_info->tt_list);
 743                 list_add(&tt_info->tt_list,
 744                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 745                 tt_info->slot_id = virt_dev->udev->slot_id;
 746                 if (tt->multi)
 747                         tt_info->ttport = i+1;
 748                 bw_table = &tt_info->bw_table;
 749                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 750                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 751         }
 752         return 0;
 753
 754 free_tts:
 755         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 756         return -ENOMEM;
 757 }
 758
 759
 760 /* All the xhci_tds in the ring's TD list should be freed at this point.
 761  * Should be called with xhci->lock held if there is any chance the TT lists
 762  * will be manipulated by the configure endpoint, allocate device, or update
 763  * hub functions while this function is removing the TT entries from the list.
 764  */
 765 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 766 {
 767         struct xhci_virt_device *dev;
 768         int i;
 769         int old_active_eps = 0;
 770
 771         /* Slot ID 0 is reserved */
 772         if (slot_id == 0 || !xhci->devs[slot_id])
 773                 return;
 774
 775         dev = xhci->devs[slot_id];
 776         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 777         if (!dev)
 778                 return;
 779
 780         if (dev->tt_info)
 781                 old_active_eps = dev->tt_info->active_eps;
 782
 783         for (i = 0; i < 31; ++i) {
 784                 if (dev->eps[i].ring)
 785                         xhci_ring_free(xhci, dev->eps[i].ring);
 786                 if (dev->eps[i].stream_info)
 787                         xhci_free_stream_info(xhci,
 788                                         dev->eps[i].stream_info);
 789                 /* Endpoints on the TT/root port lists should have been removed
 790                  * when usb_disable_device() was called for the device.
 791                  * We can't drop them anyway, because the udev might have gone
 792                  * away by this point, and we can't tell what speed it was.
 793                  */
 794                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 795                         xhci_warn(xhci, "Slot %u endpoint %u "
 796                                         "not removed from BW list!\n",
 797                                         slot_id, i);
 798         }
 799         /* If this is a hub, free the TT(s) from the TT list */
 800         xhci_free_tt_info(xhci, dev, slot_id);
 801         /* If necessary, update the number of active TTs on this root port */
 802         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 803
 804         if (dev->ring_cache) {
 805                 for (i = 0; i < dev->num_rings_cached; i++)
 806                         xhci_ring_free(xhci, dev->ring_cache[i]);
 807                 kfree(dev->ring_cache);
 808         }
 809
 810         if (dev->in_ctx)
 811                 xhci_free_container_ctx(xhci, dev->in_ctx);
 812         if (dev->out_ctx)
 813                 xhci_free_container_ctx(xhci, dev->out_ctx);
 814
 815         kfree(xhci->devs[slot_id]);
 816         xhci->devs[slot_id] = NULL;
 817 }
 818
 819 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 820                 struct usb_device *udev, gfp_t flags)
 821 {
 822         struct xhci_virt_device *dev;
 823         int i;
 824
 825         /* Slot ID 0 is reserved */
 826         if (slot_id == 0 || xhci->devs[slot_id]) {
 827                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 828                 return 0;
 829         }
 830
 831         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 832         if (!xhci->devs[slot_id])
 833                 return 0;
 834         dev = xhci->devs[slot_id];
 835
 836         /* Allocate the (output) device context that will be used in the HC. */
 837         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 838         if (!dev->out_ctx)
 839                 goto fail;
 840
 841         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 842                         (unsigned long long)dev->out_ctx->dma);
 843
 844         /* Allocate the (input) device context for address device command */
 845         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 846         if (!dev->in_ctx)
 847                 goto fail;
 848
 849         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 850                         (unsigned long long)dev->in_ctx->dma);
 851
 852         /* Initialize the cancellation list and watchdog timers for each ep */
 853         for (i = 0; i < 31; i++) {
 854                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 855                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 856                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
 857         }
 858
 859         /* Allocate endpoint 0 ring */
 860         dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, false, flags);
 861         if (!dev->eps[0].ring)
 862                 goto fail;
 863
 864         /* Allocate pointers to the ring cache */
 865         dev->ring_cache = kzalloc(
 866                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 867                         flags);
 868         if (!dev->ring_cache)
 869                 goto fail;
 870         dev->num_rings_cached = 0;
 871
 872         init_completion(&dev->cmd_completion);
 873         INIT_LIST_HEAD(&dev->cmd_list);
 874         dev->udev = udev;
 875
 876         /* Point to output device context in dcbaa. */
 877         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 878         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 879                  slot_id,
 880                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 881                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 882
 883         return 1;
 884 fail:
 885         xhci_free_virt_device(xhci, slot_id);
 886         return 0;
 887 }
 888
 889 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 890                 struct usb_device *udev)
 891 {
 892         struct xhci_virt_device *virt_dev;
 893         struct xhci_ep_ctx      *ep0_ctx;
 894         struct xhci_ring        *ep_ring;
 895
 896         virt_dev = xhci->devs[udev->slot_id];
 897         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
 898         ep_ring = virt_dev->eps[0].ring;
 899         /*
 900          * FIXME we don't keep track of the dequeue pointer very well after a
 901          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
 902          * host to our enqueue pointer.  This should only be called after a
 903          * configured device has reset, so all control transfers should have
 904          * been completed or cancelled before the reset.
 905          */
 906         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
 907                                                         ep_ring->enqueue)
 908                                    | ep_ring->cycle_state);
 909 }
 910
 911 /*
 912  * The xHCI roothub may have ports of differing speeds in any order in the port
 913  * status registers.  xhci->port_array provides an array of the port speed for
 914  * each offset into the port status registers.
 915  *
 916  * The xHCI hardware wants to know the roothub port number that the USB device
 917  * is attached to (or the roothub port its ancestor hub is attached to).  All we
 918  * know is the index of that port under either the USB 2.0 or the USB 3.0
 919  * roothub, but that doesn't give us the real index into the HW port status
 920  * registers.  Scan through the xHCI roothub port array, looking for the Nth
 921  * entry of the correct port speed.  Return the port number of that entry.
 922  */
 923 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
 924                 struct usb_device *udev)
 925 {
 926         struct usb_device *top_dev;
 927         unsigned int num_similar_speed_ports;
 928         unsigned int faked_port_num;
 929         int i;
 930
 931         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 932                         top_dev = top_dev->parent)
 933                 /* Found device below root hub */;
 934         faked_port_num = top_dev->portnum;
 935         for (i = 0, num_similar_speed_ports = 0;
 936                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
 937                 u8 port_speed = xhci->port_array[i];
 938
 939                 /*
 940                  * Skip ports that don't have known speeds, or have duplicate
 941                  * Extended Capabilities port speed entries.
 942                  */
 943                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
 944                         continue;
 945
 946                 /*
 947                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
 948                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
 949                  * matches the device speed, it's a similar speed port.
 950                  */
 951                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
 952                         num_similar_speed_ports++;
 953                 if (num_similar_speed_ports == faked_port_num)
 954                         /* Roothub ports are numbered from 1 to N */
 955                         return i+1;
 956         }
 957         return 0;
 958 }
 959
 960 /* Setup an xHCI virtual device for a Set Address command */
 961 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
 962 {
 963         struct xhci_virt_device *dev;
 964         struct xhci_ep_ctx      *ep0_ctx;
 965         struct xhci_slot_ctx    *slot_ctx;
 966         u32                     port_num;
 967         struct usb_device *top_dev;
 968
 969         dev = xhci->devs[udev->slot_id];
 970         /* Slot ID 0 is reserved */
 971         if (udev->slot_id == 0 || !dev) {
 972                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
 973                                 udev->slot_id);
 974                 return -EINVAL;
 975         }
 976         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
 977         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
 978
 979         /* 3) Only the control endpoint is valid - one endpoint context */
 980         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
 981         switch (udev->speed) {
 982         case USB_SPEED_SUPER:
 983                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
 984                 break;
 985         case USB_SPEED_HIGH:
 986                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
 987                 break;
 988         case USB_SPEED_FULL:
 989                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
 990                 break;
 991         case USB_SPEED_LOW:
 992                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
 993                 break;
 994         case USB_SPEED_WIRELESS:
 995                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
 996                 return -EINVAL;
 997                 break;
 998         default:
 999                 /* Speed was set earlier, this shouldn't happen. */
1000                 BUG();
1001         }
1002         /* Find the root hub port this device is under */
1003         port_num = xhci_find_real_port_number(xhci, udev);
1004         if (!port_num)
1005                 return -EINVAL;
1006         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1007         /* Set the port number in the virtual_device to the faked port number */
1008         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1009                         top_dev = top_dev->parent)
1010                 /* Found device below root hub */;
1011         dev->fake_port = top_dev->portnum;
1012         dev->real_port = port_num;
1013         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1014         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1015
1016         /* Find the right bandwidth table that this device will be a part of.
1017          * If this is a full speed device attached directly to a root port (or a
1018          * decendent of one), it counts as a primary bandwidth domain, not a
1019          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1020          * will never be created for the HS root hub.
1021          */
1022         if (!udev->tt || !udev->tt->hub->parent) {
1023                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1024         } else {
1025                 struct xhci_root_port_bw_info *rh_bw;
1026                 struct xhci_tt_bw_info *tt_bw;
1027
1028                 rh_bw = &xhci->rh_bw[port_num - 1];
1029                 /* Find the right TT. */
1030                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1031                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1032                                 continue;
1033
1034                         if (!dev->udev->tt->multi ||
1035                                         (udev->tt->multi &&
1036                                          tt_bw->ttport == dev->udev->ttport)) {
1037                                 dev->bw_table = &tt_bw->bw_table;
1038                                 dev->tt_info = tt_bw;
1039                                 break;
1040                         }
1041                 }
1042                 if (!dev->tt_info)
1043                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1044         }
1045
1046         /* Is this a LS/FS device under an external HS hub? */
1047         if (udev->tt && udev->tt->hub->parent) {
1048                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1049                                                 (udev->ttport << 8));
1050                 if (udev->tt->multi)
1051                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1052         }
1053         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1054         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1055
1056         /* Step 4 - ring already allocated */
1057         /* Step 5 */
1058         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1059         /*
1060          * XXX: Not sure about wireless USB devices.
1061          */
1062         switch (udev->speed) {
1063         case USB_SPEED_SUPER:
1064                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1065                 break;
1066         case USB_SPEED_HIGH:
1067         /* USB core guesses at a 64-byte max packet first for FS devices */
1068         case USB_SPEED_FULL:
1069                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1070                 break;
1071         case USB_SPEED_LOW:
1072                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1073                 break;
1074         case USB_SPEED_WIRELESS:
1075                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1076                 return -EINVAL;
1077                 break;
1078         default:
1079                 /* New speed? */
1080                 BUG();
1081         }
1082         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1083         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1084
1085         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1086                                    dev->eps[0].ring->cycle_state);
1087
1088         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1089
1090         return 0;
1091 }
1092
1093 /*
1094  * Convert interval expressed as 2^(bInterval - 1) == interval into
1095  * straight exponent value 2^n == interval.
1096  *
1097  */
1098 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1099                 struct usb_host_endpoint *ep)
1100 {
1101         unsigned int interval;
1102
1103         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1104         if (interval != ep->desc.bInterval - 1)
1105                 dev_warn(&udev->dev,
1106                          "ep %#x - rounding interval to %d %sframes\n",
1107                          ep->desc.bEndpointAddress,
1108                          1 << interval,
1109                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1110
1111         if (udev->speed == USB_SPEED_FULL) {
1112                 /*
1113                  * Full speed isoc endpoints specify interval in frames,
1114                  * not microframes. We are using microframes everywhere,
1115                  * so adjust accordingly.
1116                  */
1117                 interval += 3;  /* 1 frame = 2^3 uframes */
1118         }
1119
1120         return interval;
1121 }
1122
1123 /*
1124  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1125  * microframes, rounded down to nearest power of 2.
1126  */
1127 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1128                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1129                 unsigned int min_exponent, unsigned int max_exponent)
1130 {
1131         unsigned int interval;
1132
1133         interval = fls(desc_interval) - 1;
1134         interval = clamp_val(interval, min_exponent, max_exponent);
1135         if ((1 << interval) != desc_interval)
1136                 dev_warn(&udev->dev,
1137                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1138                          ep->desc.bEndpointAddress,
1139                          1 << interval,
1140                          desc_interval);
1141
1142         return interval;
1143 }
1144
1145 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1146                 struct usb_host_endpoint *ep)
1147 {
1148         return xhci_microframes_to_exponent(udev, ep,
1149                         ep->desc.bInterval, 0, 15);
1150 }
1151
1152
1153 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1154                 struct usb_host_endpoint *ep)
1155 {
1156         return xhci_microframes_to_exponent(udev, ep,
1157                         ep->desc.bInterval * 8, 3, 10);
1158 }
1159
1160 /* Return the polling or NAK interval.
1161  *
1162  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1163  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1164  *
1165  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1166  * is set to 0.
1167  */
1168 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1169                 struct usb_host_endpoint *ep)
1170 {
1171         unsigned int interval = 0;
1172
1173         switch (udev->speed) {
1174         case USB_SPEED_HIGH:
1175                 /* Max NAK rate */
1176                 if (usb_endpoint_xfer_control(&ep->desc) ||
1177                     usb_endpoint_xfer_bulk(&ep->desc)) {
1178                         interval = xhci_parse_microframe_interval(udev, ep);
1179                         break;
1180                 }
1181                 /* Fall through - SS and HS isoc/int have same decoding */
1182
1183         case USB_SPEED_SUPER:
1184                 if (usb_endpoint_xfer_int(&ep->desc) ||
1185                     usb_endpoint_xfer_isoc(&ep->desc)) {
1186                         interval = xhci_parse_exponent_interval(udev, ep);
1187                 }
1188                 break;
1189
1190         case USB_SPEED_FULL:
1191                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1192                         interval = xhci_parse_exponent_interval(udev, ep);
1193                         break;
1194                 }
1195                 /*
1196                  * Fall through for interrupt endpoint interval decoding
1197                  * since it uses the same rules as low speed interrupt
1198                  * endpoints.
1199                  */
1200
1201         case USB_SPEED_LOW:
1202                 if (usb_endpoint_xfer_int(&ep->desc) ||
1203                     usb_endpoint_xfer_isoc(&ep->desc)) {
1204
1205                         interval = xhci_parse_frame_interval(udev, ep);
1206                 }
1207                 break;
1208
1209         default:
1210                 BUG();
1211         }
1212         return EP_INTERVAL(interval);
1213 }
1214
1215 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1216  * High speed endpoint descriptors can define "the number of additional
1217  * transaction opportunities per microframe", but that goes in the Max Burst
1218  * endpoint context field.
1219  */
1220 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1221                 struct usb_host_endpoint *ep)
1222 {
1223         if (udev->speed != USB_SPEED_SUPER ||
1224                         !usb_endpoint_xfer_isoc(&ep->desc))
1225                 return 0;
1226         return ep->ss_ep_comp.bmAttributes;
1227 }
1228
1229 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1230                 struct usb_host_endpoint *ep)
1231 {
1232         int in;
1233         u32 type;
1234
1235         in = usb_endpoint_dir_in(&ep->desc);
1236         if (usb_endpoint_xfer_control(&ep->desc)) {
1237                 type = EP_TYPE(CTRL_EP);
1238         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1239                 if (in)
1240                         type = EP_TYPE(BULK_IN_EP);
1241                 else
1242                         type = EP_TYPE(BULK_OUT_EP);
1243         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1244                 if (in)
1245                         type = EP_TYPE(ISOC_IN_EP);
1246                 else
1247                         type = EP_TYPE(ISOC_OUT_EP);
1248         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1249                 if (in)
1250                         type = EP_TYPE(INT_IN_EP);
1251                 else
1252                         type = EP_TYPE(INT_OUT_EP);
1253         } else {
1254                 BUG();
1255         }
1256         return type;
1257 }
1258
1259 /* Return the maximum endpoint service interval time (ESIT) payload.
1260  * Basically, this is the maxpacket size, multiplied by the burst size
1261  * and mult size.
1262  */
1263 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1264                 struct usb_device *udev,
1265                 struct usb_host_endpoint *ep)
1266 {
1267         int max_burst;
1268         int max_packet;
1269
1270         /* Only applies for interrupt or isochronous endpoints */
1271         if (usb_endpoint_xfer_control(&ep->desc) ||
1272                         usb_endpoint_xfer_bulk(&ep->desc))
1273                 return 0;
1274
1275         if (udev->speed == USB_SPEED_SUPER)
1276                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1277
1278         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1279         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1280         /* A 0 in max burst means 1 transfer per ESIT */
1281         return max_packet * (max_burst + 1);
1282 }
1283
1284 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1285  * Drivers will have to call usb_alloc_streams() to do that.
1286  */
1287 int xhci_endpoint_init(struct xhci_hcd *xhci,
1288                 struct xhci_virt_device *virt_dev,
1289                 struct usb_device *udev,
1290                 struct usb_host_endpoint *ep,
1291                 gfp_t mem_flags)
1292 {
1293         unsigned int ep_index;
1294         struct xhci_ep_ctx *ep_ctx;
1295         struct xhci_ring *ep_ring;
1296         unsigned int max_packet;
1297         unsigned int max_burst;
1298         u32 max_esit_payload;
1299
1300         ep_index = xhci_get_endpoint_index(&ep->desc);
1301         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1302
1303         /* Set up the endpoint ring */
1304         /*
1305          * Isochronous endpoint ring needs bigger size because one isoc URB
1306          * carries multiple packets and it will insert multiple tds to the
1307          * ring.
1308          * This should be replaced with dynamic ring resizing in the future.
1309          */
1310         if (usb_endpoint_xfer_isoc(&ep->desc))
1311                 virt_dev->eps[ep_index].new_ring =
1312                         xhci_ring_alloc(xhci, 8, true, true, mem_flags);
1313         else
1314                 virt_dev->eps[ep_index].new_ring =
1315                         xhci_ring_alloc(xhci, 1, true, false, mem_flags);
1316         if (!virt_dev->eps[ep_index].new_ring) {
1317                 /* Attempt to use the ring cache */
1318                 if (virt_dev->num_rings_cached == 0)
1319                         return -ENOMEM;
1320                 virt_dev->eps[ep_index].new_ring =
1321                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1322                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1323                 virt_dev->num_rings_cached--;
1324                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1325                         usb_endpoint_xfer_isoc(&ep->desc) ? true : false);
1326         }
1327         virt_dev->eps[ep_index].skip = false;
1328         ep_ring = virt_dev->eps[ep_index].new_ring;
1329         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1330
1331         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1332                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1333
1334         /* FIXME dig Mult and streams info out of ep companion desc */
1335
1336         /* Allow 3 retries for everything but isoc;
1337          * CErr shall be set to 0 for Isoch endpoints.
1338          */
1339         if (!usb_endpoint_xfer_isoc(&ep->desc))
1340                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1341         else
1342                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1343
1344         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1345
1346         /* Set the max packet size and max burst */
1347         switch (udev->speed) {
1348         case USB_SPEED_SUPER:
1349                 max_packet = usb_endpoint_maxp(&ep->desc);
1350                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1351                 /* dig out max burst from ep companion desc */
1352                 max_packet = ep->ss_ep_comp.bMaxBurst;
1353                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1354                 break;
1355         case USB_SPEED_HIGH:
1356                 /* bits 11:12 specify the number of additional transaction
1357                  * opportunities per microframe (USB 2.0, section 9.6.6)
1358                  */
1359                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1360                                 usb_endpoint_xfer_int(&ep->desc)) {
1361                         max_burst = (usb_endpoint_maxp(&ep->desc)
1362                                      & 0x1800) >> 11;
1363                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1364                 }
1365                 /* Fall through */
1366         case USB_SPEED_FULL:
1367         case USB_SPEED_LOW:
1368                 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1369                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1370                 break;
1371         default:
1372                 BUG();
1373         }
1374         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1375         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1376
1377         /*
1378          * XXX no idea how to calculate the average TRB buffer length for bulk
1379          * endpoints, as the driver gives us no clue how big each scatter gather
1380          * list entry (or buffer) is going to be.
1381          *
1382          * For isochronous and interrupt endpoints, we set it to the max
1383          * available, until we have new API in the USB core to allow drivers to
1384          * declare how much bandwidth they actually need.
1385          *
1386          * Normally, it would be calculated by taking the total of the buffer
1387          * lengths in the TD and then dividing by the number of TRBs in a TD,
1388          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1389          * use Event Data TRBs, and we don't chain in a link TRB on short
1390          * transfers, we're basically dividing by 1.
1391          *
1392          * xHCI 1.0 specification indicates that the Average TRB Length should
1393          * be set to 8 for control endpoints.
1394          */
1395         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1396                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1397         else
1398                 ep_ctx->tx_info |=
1399                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1400
1401         /* FIXME Debug endpoint context */
1402         return 0;
1403 }
1404
1405 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1406                 struct xhci_virt_device *virt_dev,
1407                 struct usb_host_endpoint *ep)
1408 {
1409         unsigned int ep_index;
1410         struct xhci_ep_ctx *ep_ctx;
1411
1412         ep_index = xhci_get_endpoint_index(&ep->desc);
1413         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1414
1415         ep_ctx->ep_info = 0;
1416         ep_ctx->ep_info2 = 0;
1417         ep_ctx->deq = 0;
1418         ep_ctx->tx_info = 0;
1419         /* Don't free the endpoint ring until the set interface or configuration
1420          * request succeeds.
1421          */
1422 }
1423
1424 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1425 {
1426         bw_info->ep_interval = 0;
1427         bw_info->mult = 0;
1428         bw_info->num_packets = 0;
1429         bw_info->max_packet_size = 0;
1430         bw_info->type = 0;
1431         bw_info->max_esit_payload = 0;
1432 }
1433
1434 void xhci_update_bw_info(struct xhci_hcd *xhci,
1435                 struct xhci_container_ctx *in_ctx,
1436                 struct xhci_input_control_ctx *ctrl_ctx,
1437                 struct xhci_virt_device *virt_dev)
1438 {
1439         struct xhci_bw_info *bw_info;
1440         struct xhci_ep_ctx *ep_ctx;
1441         unsigned int ep_type;
1442         int i;
1443
1444         for (i = 1; i < 31; ++i) {
1445                 bw_info = &virt_dev->eps[i].bw_info;
1446
1447                 /* We can't tell what endpoint type is being dropped, but
1448                  * unconditionally clearing the bandwidth info for non-periodic
1449                  * endpoints should be harmless because the info will never be
1450                  * set in the first place.
1451                  */
1452                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1453                         /* Dropped endpoint */
1454                         xhci_clear_endpoint_bw_info(bw_info);
1455                         continue;
1456                 }
1457
1458                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1459                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1460                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1461
1462                         /* Ignore non-periodic endpoints */
1463                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1464                                         ep_type != ISOC_IN_EP &&
1465                                         ep_type != INT_IN_EP)
1466                                 continue;
1467
1468                         /* Added or changed endpoint */
1469                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1470                                         le32_to_cpu(ep_ctx->ep_info));
1471                         /* Number of packets and mult are zero-based in the
1472                          * input context, but we want one-based for the
1473                          * interval table.
1474                          */
1475                         bw_info->mult = CTX_TO_EP_MULT(
1476                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1477                         bw_info->num_packets = CTX_TO_MAX_BURST(
1478                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1479                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1480                                         le32_to_cpu(ep_ctx->ep_info2));
1481                         bw_info->type = ep_type;
1482                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1483                                         le32_to_cpu(ep_ctx->tx_info));
1484                 }
1485         }
1486 }
1487
1488 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1489  * Useful when you want to change one particular aspect of the endpoint and then
1490  * issue a configure endpoint command.
1491  */
1492 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1493                 struct xhci_container_ctx *in_ctx,
1494                 struct xhci_container_ctx *out_ctx,
1495                 unsigned int ep_index)
1496 {
1497         struct xhci_ep_ctx *out_ep_ctx;
1498         struct xhci_ep_ctx *in_ep_ctx;
1499
1500         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1501         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1502
1503         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1504         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1505         in_ep_ctx->deq = out_ep_ctx->deq;
1506         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1507 }
1508
1509 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1510  * Useful when you want to change one particular aspect of the endpoint and then
1511  * issue a configure endpoint command.  Only the context entries field matters,
1512  * but we'll copy the whole thing anyway.
1513  */
1514 void xhci_slot_copy(struct xhci_hcd *xhci,
1515                 struct xhci_container_ctx *in_ctx,
1516                 struct xhci_container_ctx *out_ctx)
1517 {
1518         struct xhci_slot_ctx *in_slot_ctx;
1519         struct xhci_slot_ctx *out_slot_ctx;
1520
1521         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1522         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1523
1524         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1525         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1526         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1527         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1528 }
1529
1530 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1531 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1532 {
1533         int i;
1534         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1535         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1536
1537         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1538
1539         if (!num_sp)
1540                 return 0;
1541
1542         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1543         if (!xhci->scratchpad)
1544                 goto fail_sp;
1545
1546         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1547                                      num_sp * sizeof(u64),
1548                                      &xhci->scratchpad->sp_dma, flags);
1549         if (!xhci->scratchpad->sp_array)
1550                 goto fail_sp2;
1551
1552         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1553         if (!xhci->scratchpad->sp_buffers)
1554                 goto fail_sp3;
1555
1556         xhci->scratchpad->sp_dma_buffers =
1557                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1558
1559         if (!xhci->scratchpad->sp_dma_buffers)
1560                 goto fail_sp4;
1561
1562         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1563         for (i = 0; i < num_sp; i++) {
1564                 dma_addr_t dma;
1565                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1566                                 flags);
1567                 if (!buf)
1568                         goto fail_sp5;
1569
1570                 xhci->scratchpad->sp_array[i] = dma;
1571                 xhci->scratchpad->sp_buffers[i] = buf;
1572                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1573         }
1574
1575         return 0;
1576
1577  fail_sp5:
1578         for (i = i - 1; i >= 0; i--) {
1579                 dma_free_coherent(dev, xhci->page_size,
1580                                     xhci->scratchpad->sp_buffers[i],
1581                                     xhci->scratchpad->sp_dma_buffers[i]);
1582         }
1583         kfree(xhci->scratchpad->sp_dma_buffers);
1584
1585  fail_sp4:
1586         kfree(xhci->scratchpad->sp_buffers);
1587
1588  fail_sp3:
1589         dma_free_coherent(dev, num_sp * sizeof(u64),
1590                             xhci->scratchpad->sp_array,
1591                             xhci->scratchpad->sp_dma);
1592
1593  fail_sp2:
1594         kfree(xhci->scratchpad);
1595         xhci->scratchpad = NULL;
1596
1597  fail_sp:
1598         return -ENOMEM;
1599 }
1600
1601 static void scratchpad_free(struct xhci_hcd *xhci)
1602 {
1603         int num_sp;
1604         int i;
1605         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1606
1607         if (!xhci->scratchpad)
1608                 return;
1609
1610         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1611
1612         for (i = 0; i < num_sp; i++) {
1613                 dma_free_coherent(&pdev->dev, xhci->page_size,
1614                                     xhci->scratchpad->sp_buffers[i],
1615                                     xhci->scratchpad->sp_dma_buffers[i]);
1616         }
1617         kfree(xhci->scratchpad->sp_dma_buffers);
1618         kfree(xhci->scratchpad->sp_buffers);
1619         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1620                             xhci->scratchpad->sp_array,
1621                             xhci->scratchpad->sp_dma);
1622         kfree(xhci->scratchpad);
1623         xhci->scratchpad = NULL;
1624 }
1625
1626 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1627                 bool allocate_in_ctx, bool allocate_completion,
1628                 gfp_t mem_flags)
1629 {
1630         struct xhci_command *command;
1631
1632         command = kzalloc(sizeof(*command), mem_flags);
1633         if (!command)
1634                 return NULL;
1635
1636         if (allocate_in_ctx) {
1637                 command->in_ctx =
1638                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1639                                         mem_flags);
1640                 if (!command->in_ctx) {
1641                         kfree(command);
1642                         return NULL;
1643                 }
1644         }
1645
1646         if (allocate_completion) {
1647                 command->completion =
1648                         kzalloc(sizeof(struct completion), mem_flags);
1649                 if (!command->completion) {
1650                         xhci_free_container_ctx(xhci, command->in_ctx);
1651                         kfree(command);
1652                         return NULL;
1653                 }
1654                 init_completion(command->completion);
1655         }
1656
1657         command->status = 0;
1658         INIT_LIST_HEAD(&command->cmd_list);
1659         return command;
1660 }
1661
1662 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1663 {
1664         if (urb_priv) {
1665                 kfree(urb_priv->td[0]);
1666                 kfree(urb_priv);
1667         }
1668 }
1669
1670 void xhci_free_command(struct xhci_hcd *xhci,
1671                 struct xhci_command *command)
1672 {
1673         xhci_free_container_ctx(xhci,
1674                         command->in_ctx);
1675         kfree(command->completion);
1676         kfree(command);
1677 }
1678
1679 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1680 {
1681         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1682         struct dev_info *dev_info, *next;
1683         struct xhci_cd  *cur_cd, *next_cd;
1684         unsigned long   flags;
1685         int size;
1686         int i, j, num_ports;
1687
1688         /* Free the Event Ring Segment Table and the actual Event Ring */
1689         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1690         if (xhci->erst.entries)
1691                 dma_free_coherent(&pdev->dev, size,
1692                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1693         xhci->erst.entries = NULL;
1694         xhci_dbg(xhci, "Freed ERST\n");
1695         if (xhci->event_ring)
1696                 xhci_ring_free(xhci, xhci->event_ring);
1697         xhci->event_ring = NULL;
1698         xhci_dbg(xhci, "Freed event ring\n");
1699
1700         xhci->cmd_ring_reserved_trbs = 0;
1701         if (xhci->cmd_ring)
1702                 xhci_ring_free(xhci, xhci->cmd_ring);
1703         xhci->cmd_ring = NULL;
1704         xhci_dbg(xhci, "Freed command ring\n");
1705         list_for_each_entry_safe(cur_cd, next_cd,
1706                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1707                 list_del(&cur_cd->cancel_cmd_list);
1708                 kfree(cur_cd);
1709         }
1710
1711         for (i = 1; i < MAX_HC_SLOTS; ++i)
1712                 xhci_free_virt_device(xhci, i);
1713
1714         if (xhci->segment_pool)
1715                 dma_pool_destroy(xhci->segment_pool);
1716         xhci->segment_pool = NULL;
1717         xhci_dbg(xhci, "Freed segment pool\n");
1718
1719         if (xhci->device_pool)
1720                 dma_pool_destroy(xhci->device_pool);
1721         xhci->device_pool = NULL;
1722         xhci_dbg(xhci, "Freed device context pool\n");
1723
1724         if (xhci->small_streams_pool)
1725                 dma_pool_destroy(xhci->small_streams_pool);
1726         xhci->small_streams_pool = NULL;
1727         xhci_dbg(xhci, "Freed small stream array pool\n");
1728
1729         if (xhci->medium_streams_pool)
1730                 dma_pool_destroy(xhci->medium_streams_pool);
1731         xhci->medium_streams_pool = NULL;
1732         xhci_dbg(xhci, "Freed medium stream array pool\n");
1733
1734         if (xhci->dcbaa)
1735                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1736                                 xhci->dcbaa, xhci->dcbaa->dma);
1737         xhci->dcbaa = NULL;
1738
1739         scratchpad_free(xhci);
1740
1741         spin_lock_irqsave(&xhci->lock, flags);
1742         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1743                 list_del(&dev_info->list);
1744                 kfree(dev_info);
1745         }
1746         spin_unlock_irqrestore(&xhci->lock, flags);
1747
1748         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1749         for (i = 0; i < num_ports; i++) {
1750                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1751                 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1752                         struct list_head *ep = &bwt->interval_bw[j].endpoints;
1753                         while (!list_empty(ep))
1754                                 list_del_init(ep->next);
1755                 }
1756         }
1757
1758         for (i = 0; i < num_ports; i++) {
1759                 struct xhci_tt_bw_info *tt, *n;
1760                 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1761                         list_del(&tt->tt_list);
1762                         kfree(tt);
1763                 }
1764         }
1765
1766         xhci->num_usb2_ports = 0;
1767         xhci->num_usb3_ports = 0;
1768         xhci->num_active_eps = 0;
1769         kfree(xhci->usb2_ports);
1770         kfree(xhci->usb3_ports);
1771         kfree(xhci->port_array);
1772         kfree(xhci->rh_bw);
1773
1774         xhci->page_size = 0;
1775         xhci->page_shift = 0;
1776         xhci->bus_state[0].bus_suspended = 0;
1777         xhci->bus_state[1].bus_suspended = 0;
1778 }
1779
1780 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1781                 struct xhci_segment *input_seg,
1782                 union xhci_trb *start_trb,
1783                 union xhci_trb *end_trb,
1784                 dma_addr_t input_dma,
1785                 struct xhci_segment *result_seg,
1786                 char *test_name, int test_number)
1787 {
1788         unsigned long long start_dma;
1789         unsigned long long end_dma;
1790         struct xhci_segment *seg;
1791
1792         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1793         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1794
1795         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1796         if (seg != result_seg) {
1797                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1798                                 test_name, test_number);
1799                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1800                                 "input DMA 0x%llx\n",
1801                                 input_seg,
1802                                 (unsigned long long) input_dma);
1803                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1804                                 "ending TRB %p (0x%llx DMA)\n",
1805                                 start_trb, start_dma,
1806                                 end_trb, end_dma);
1807                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1808                                 result_seg, seg);
1809                 return -1;
1810         }
1811         return 0;
1812 }
1813
1814 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1815 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1816 {
1817         struct {
1818                 dma_addr_t              input_dma;
1819                 struct xhci_segment     *result_seg;
1820         } simple_test_vector [] = {
1821                 /* A zeroed DMA field should fail */
1822                 { 0, NULL },
1823                 /* One TRB before the ring start should fail */
1824                 { xhci->event_ring->first_seg->dma - 16, NULL },
1825                 /* One byte before the ring start should fail */
1826                 { xhci->event_ring->first_seg->dma - 1, NULL },
1827                 /* Starting TRB should succeed */
1828                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1829                 /* Ending TRB should succeed */
1830                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1831                         xhci->event_ring->first_seg },
1832                 /* One byte after the ring end should fail */
1833                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1834                 /* One TRB after the ring end should fail */
1835                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1836                 /* An address of all ones should fail */
1837                 { (dma_addr_t) (~0), NULL },
1838         };
1839         struct {
1840                 struct xhci_segment     *input_seg;
1841                 union xhci_trb          *start_trb;
1842                 union xhci_trb          *end_trb;
1843                 dma_addr_t              input_dma;
1844                 struct xhci_segment     *result_seg;
1845         } complex_test_vector [] = {
1846                 /* Test feeding a valid DMA address from a different ring */
1847                 {       .input_seg = xhci->event_ring->first_seg,
1848                         .start_trb = xhci->event_ring->first_seg->trbs,
1849                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1850                         .input_dma = xhci->cmd_ring->first_seg->dma,
1851                         .result_seg = NULL,
1852                 },
1853                 /* Test feeding a valid end TRB from a different ring */
1854                 {       .input_seg = xhci->event_ring->first_seg,
1855                         .start_trb = xhci->event_ring->first_seg->trbs,
1856                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1857                         .input_dma = xhci->cmd_ring->first_seg->dma,
1858                         .result_seg = NULL,
1859                 },
1860                 /* Test feeding a valid start and end TRB from a different ring */
1861                 {       .input_seg = xhci->event_ring->first_seg,
1862                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1863                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1864                         .input_dma = xhci->cmd_ring->first_seg->dma,
1865                         .result_seg = NULL,
1866                 },
1867                 /* TRB in this ring, but after this TD */
1868                 {       .input_seg = xhci->event_ring->first_seg,
1869                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1870                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1871                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1872                         .result_seg = NULL,
1873                 },
1874                 /* TRB in this ring, but before this TD */
1875                 {       .input_seg = xhci->event_ring->first_seg,
1876                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1877                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1878                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1879                         .result_seg = NULL,
1880                 },
1881                 /* TRB in this ring, but after this wrapped TD */
1882                 {       .input_seg = xhci->event_ring->first_seg,
1883                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1884                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1885                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1886                         .result_seg = NULL,
1887                 },
1888                 /* TRB in this ring, but before this wrapped TD */
1889                 {       .input_seg = xhci->event_ring->first_seg,
1890                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1891                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1892                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1893                         .result_seg = NULL,
1894                 },
1895                 /* TRB not in this ring, and we have a wrapped TD */
1896                 {       .input_seg = xhci->event_ring->first_seg,
1897                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1898                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1899                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1900                         .result_seg = NULL,
1901                 },
1902         };
1903
1904         unsigned int num_tests;
1905         int i, ret;
1906
1907         num_tests = ARRAY_SIZE(simple_test_vector);
1908         for (i = 0; i < num_tests; i++) {
1909                 ret = xhci_test_trb_in_td(xhci,
1910                                 xhci->event_ring->first_seg,
1911                                 xhci->event_ring->first_seg->trbs,
1912                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1913                                 simple_test_vector[i].input_dma,
1914                                 simple_test_vector[i].result_seg,
1915                                 "Simple", i);
1916                 if (ret < 0)
1917                         return ret;
1918         }
1919
1920         num_tests = ARRAY_SIZE(complex_test_vector);
1921         for (i = 0; i < num_tests; i++) {
1922                 ret = xhci_test_trb_in_td(xhci,
1923                                 complex_test_vector[i].input_seg,
1924                                 complex_test_vector[i].start_trb,
1925                                 complex_test_vector[i].end_trb,
1926                                 complex_test_vector[i].input_dma,
1927                                 complex_test_vector[i].result_seg,
1928                                 "Complex", i);
1929                 if (ret < 0)
1930                         return ret;
1931         }
1932         xhci_dbg(xhci, "TRB math tests passed.\n");
1933         return 0;
1934 }
1935
1936 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1937 {
1938         u64 temp;
1939         dma_addr_t deq;
1940
1941         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
1942                         xhci->event_ring->dequeue);
1943         if (deq == 0 && !in_interrupt())
1944                 xhci_warn(xhci, "WARN something wrong with SW event ring "
1945                                 "dequeue ptr.\n");
1946         /* Update HC event ring dequeue pointer */
1947         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1948         temp &= ERST_PTR_MASK;
1949         /* Don't clear the EHB bit (which is RW1C) because
1950          * there might be more events to service.
1951          */
1952         temp &= ~ERST_EHB;
1953         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
1954                         "preserving EHB bit\n");
1955         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1956                         &xhci->ir_set->erst_dequeue);
1957 }
1958
1959 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
1960                 __le32 __iomem *addr, u8 major_revision)
1961 {
1962         u32 temp, port_offset, port_count;
1963         int i;
1964
1965         if (major_revision > 0x03) {
1966                 xhci_warn(xhci, "Ignoring unknown port speed, "
1967                                 "Ext Cap %p, revision = 0x%x\n",
1968                                 addr, major_revision);
1969                 /* Ignoring port protocol we can't understand. FIXME */
1970                 return;
1971         }
1972
1973         /* Port offset and count in the third dword, see section 7.2 */
1974         temp = xhci_readl(xhci, addr + 2);
1975         port_offset = XHCI_EXT_PORT_OFF(temp);
1976         port_count = XHCI_EXT_PORT_COUNT(temp);
1977         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
1978                         "count = %u, revision = 0x%x\n",
1979                         addr, port_offset, port_count, major_revision);
1980         /* Port count includes the current port offset */
1981         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
1982                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
1983                 return;
1984
1985         /* Check the host's USB2 LPM capability */
1986         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
1987                         (temp & XHCI_L1C)) {
1988                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
1989                 xhci->sw_lpm_support = 1;
1990         }
1991
1992         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
1993                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
1994                 xhci->sw_lpm_support = 1;
1995                 if (temp & XHCI_HLC) {
1996                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
1997                         xhci->hw_lpm_support = 1;
1998                 }
1999         }
2000
2001         port_offset--;
2002         for (i = port_offset; i < (port_offset + port_count); i++) {
2003                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2004                 if (xhci->port_array[i] != 0) {
2005                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2006                                         " port %u\n", addr, i);
2007                         xhci_warn(xhci, "Port was marked as USB %u, "
2008                                         "duplicated as USB %u\n",
2009                                         xhci->port_array[i], major_revision);
2010                         /* Only adjust the roothub port counts if we haven't
2011                          * found a similar duplicate.
2012                          */
2013                         if (xhci->port_array[i] != major_revision &&
2014                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2015                                 if (xhci->port_array[i] == 0x03)
2016                                         xhci->num_usb3_ports--;
2017                                 else
2018                                         xhci->num_usb2_ports--;
2019                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2020                         }
2021                         /* FIXME: Should we disable the port? */
2022                         continue;
2023                 }
2024                 xhci->port_array[i] = major_revision;
2025                 if (major_revision == 0x03)
2026                         xhci->num_usb3_ports++;
2027                 else
2028                         xhci->num_usb2_ports++;
2029         }
2030         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2031 }
2032
2033 /*
2034  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2035  * specify what speeds each port is supposed to be.  We can't count on the port
2036  * speed bits in the PORTSC register being correct until a device is connected,
2037  * but we need to set up the two fake roothubs with the correct number of USB
2038  * 3.0 and USB 2.0 ports at host controller initialization time.
2039  */
2040 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2041 {
2042         __le32 __iomem *addr;
2043         u32 offset;
2044         unsigned int num_ports;
2045         int i, j, port_index;
2046
2047         addr = &xhci->cap_regs->hcc_params;
2048         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2049         if (offset == 0) {
2050                 xhci_err(xhci, "No Extended Capability registers, "
2051                                 "unable to set up roothub.\n");
2052                 return -ENODEV;
2053         }
2054
2055         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2056         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2057         if (!xhci->port_array)
2058                 return -ENOMEM;
2059
2060         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2061         if (!xhci->rh_bw)
2062                 return -ENOMEM;
2063         for (i = 0; i < num_ports; i++) {
2064                 struct xhci_interval_bw_table *bw_table;
2065
2066                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2067                 bw_table = &xhci->rh_bw[i].bw_table;
2068                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2069                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2070         }
2071
2072         /*
2073          * For whatever reason, the first capability offset is from the
2074          * capability register base, not from the HCCPARAMS register.
2075          * See section 5.3.6 for offset calculation.
2076          */
2077         addr = &xhci->cap_regs->hc_capbase + offset;
2078         while (1) {
2079                 u32 cap_id;
2080
2081                 cap_id = xhci_readl(xhci, addr);
2082                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2083                         xhci_add_in_port(xhci, num_ports, addr,
2084                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2085                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2086                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2087                                 == num_ports)
2088                         break;
2089                 /*
2090                  * Once you're into the Extended Capabilities, the offset is
2091                  * always relative to the register holding the offset.
2092                  */
2093                 addr += offset;
2094         }
2095
2096         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2097                 xhci_warn(xhci, "No ports on the roothubs?\n");
2098                 return -ENODEV;
2099         }
2100         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2101                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2102
2103         /* Place limits on the number of roothub ports so that the hub
2104          * descriptors aren't longer than the USB core will allocate.
2105          */
2106         if (xhci->num_usb3_ports > 15) {
2107                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2108                 xhci->num_usb3_ports = 15;
2109         }
2110         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2111                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2112                                 USB_MAXCHILDREN);
2113                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2114         }
2115
2116         /*
2117          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2118          * Not sure how the USB core will handle a hub with no ports...
2119          */
2120         if (xhci->num_usb2_ports) {
2121                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2122                                 xhci->num_usb2_ports, flags);
2123                 if (!xhci->usb2_ports)
2124                         return -ENOMEM;
2125
2126                 port_index = 0;
2127                 for (i = 0; i < num_ports; i++) {
2128                         if (xhci->port_array[i] == 0x03 ||
2129                                         xhci->port_array[i] == 0 ||
2130                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2131                                 continue;
2132
2133                         xhci->usb2_ports[port_index] =
2134                                 &xhci->op_regs->port_status_base +
2135                                 NUM_PORT_REGS*i;
2136                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2137                                         "addr = %p\n", i,
2138                                         xhci->usb2_ports[port_index]);
2139                         port_index++;
2140                         if (port_index == xhci->num_usb2_ports)
2141                                 break;
2142                 }
2143         }
2144         if (xhci->num_usb3_ports) {
2145                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2146                                 xhci->num_usb3_ports, flags);
2147                 if (!xhci->usb3_ports)
2148                         return -ENOMEM;
2149
2150                 port_index = 0;
2151                 for (i = 0; i < num_ports; i++)
2152                         if (xhci->port_array[i] == 0x03) {
2153                                 xhci->usb3_ports[port_index] =
2154                                         &xhci->op_regs->port_status_base +
2155                                         NUM_PORT_REGS*i;
2156                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2157                                                 "addr = %p\n", i,
2158                                                 xhci->usb3_ports[port_index]);
2159                                 port_index++;
2160                                 if (port_index == xhci->num_usb3_ports)
2161                                         break;
2162                         }
2163         }
2164         return 0;
2165 }
2166
2167 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2168 {
2169         dma_addr_t      dma;
2170         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2171         unsigned int    val, val2;
2172         u64             val_64;
2173         struct xhci_segment     *seg;
2174         u32 page_size;
2175         int i;
2176
2177         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2178         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2179         for (i = 0; i < 16; i++) {
2180                 if ((0x1 & page_size) != 0)
2181                         break;
2182                 page_size = page_size >> 1;
2183         }
2184         if (i < 16)
2185                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2186         else
2187                 xhci_warn(xhci, "WARN: no supported page size\n");
2188         /* Use 4K pages, since that's common and the minimum the HC supports */
2189         xhci->page_shift = 12;
2190         xhci->page_size = 1 << xhci->page_shift;
2191         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2192
2193         /*
2194          * Program the Number of Device Slots Enabled field in the CONFIG
2195          * register with the max value of slots the HC can handle.
2196          */
2197         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2198         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2199                         (unsigned int) val);
2200         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2201         val |= (val2 & ~HCS_SLOTS_MASK);
2202         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2203                         (unsigned int) val);
2204         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2205
2206         /*
2207          * Section 5.4.8 - doorbell array must be
2208          * "physically contiguous and 64-byte (cache line) aligned".
2209          */
2210         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2211                         GFP_KERNEL);
2212         if (!xhci->dcbaa)
2213                 goto fail;
2214         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2215         xhci->dcbaa->dma = dma;
2216         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2217                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2218         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2219
2220         /*
2221          * Initialize the ring segment pool.  The ring must be a contiguous
2222          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2223          * however, the command ring segment needs 64-byte aligned segments,
2224          * so we pick the greater alignment need.
2225          */
2226         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2227                         SEGMENT_SIZE, 64, xhci->page_size);
2228
2229         /* See Table 46 and Note on Figure 55 */
2230         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2231                         2112, 64, xhci->page_size);
2232         if (!xhci->segment_pool || !xhci->device_pool)
2233                 goto fail;
2234
2235         /* Linear stream context arrays don't have any boundary restrictions,
2236          * and only need to be 16-byte aligned.
2237          */
2238         xhci->small_streams_pool =
2239                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2240                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2241         xhci->medium_streams_pool =
2242                 dma_pool_create("xHCI 1KB stream ctx arrays",
2243                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2244         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2245          * will be allocated with dma_alloc_coherent()
2246          */
2247
2248         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2249                 goto fail;
2250
2251         /* Set up the command ring to have one segments for now. */
2252         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, false, flags);
2253         if (!xhci->cmd_ring)
2254                 goto fail;
2255         INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2256         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2257         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2258                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2259
2260         /* Set the address in the Command Ring Control register */
2261         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2262         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2263                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2264                 xhci->cmd_ring->cycle_state;
2265         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2266         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2267         xhci_dbg_cmd_ptrs(xhci);
2268
2269         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2270         val &= DBOFF_MASK;
2271         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2272                         " from cap regs base addr\n", val);
2273         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2274         xhci_dbg_regs(xhci);
2275         xhci_print_run_regs(xhci);
2276         /* Set ir_set to interrupt register set 0 */
2277         xhci->ir_set = &xhci->run_regs->ir_set[0];
2278
2279         /*
2280          * Event ring setup: Allocate a normal ring, but also setup
2281          * the event ring segment table (ERST).  Section 4.9.3.
2282          */
2283         xhci_dbg(xhci, "// Allocating event ring\n");
2284         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, false,
2285                                                 flags);
2286         if (!xhci->event_ring)
2287                 goto fail;
2288         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2289                 goto fail;
2290
2291         xhci->erst.entries = dma_alloc_coherent(dev,
2292                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2293                         GFP_KERNEL);
2294         if (!xhci->erst.entries)
2295                 goto fail;
2296         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2297                         (unsigned long long)dma);
2298
2299         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2300         xhci->erst.num_entries = ERST_NUM_SEGS;
2301         xhci->erst.erst_dma_addr = dma;
2302         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2303                         xhci->erst.num_entries,
2304                         xhci->erst.entries,
2305                         (unsigned long long)xhci->erst.erst_dma_addr);
2306
2307         /* set ring base address and size for each segment table entry */
2308         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2309                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2310                 entry->seg_addr = cpu_to_le64(seg->dma);
2311                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2312                 entry->rsvd = 0;
2313                 seg = seg->next;
2314         }
2315
2316         /* set ERST count with the number of entries in the segment table */
2317         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2318         val &= ERST_SIZE_MASK;
2319         val |= ERST_NUM_SEGS;
2320         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2321                         val);
2322         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2323
2324         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2325         /* set the segment table base address */
2326         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2327                         (unsigned long long)xhci->erst.erst_dma_addr);
2328         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2329         val_64 &= ERST_PTR_MASK;
2330         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2331         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2332
2333         /* Set the event ring dequeue address */
2334         xhci_set_hc_event_deq(xhci);
2335         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2336         xhci_print_ir_set(xhci, 0);
2337
2338         /*
2339          * XXX: Might need to set the Interrupter Moderation Register to
2340          * something other than the default (~1ms minimum between interrupts).
2341          * See section 5.5.1.2.
2342          */
2343         init_completion(&xhci->addr_dev);
2344         for (i = 0; i < MAX_HC_SLOTS; ++i)
2345                 xhci->devs[i] = NULL;
2346         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2347                 xhci->bus_state[0].resume_done[i] = 0;
2348                 xhci->bus_state[1].resume_done[i] = 0;
2349         }
2350
2351         if (scratchpad_alloc(xhci, flags))
2352                 goto fail;
2353         if (xhci_setup_port_arrays(xhci, flags))
2354                 goto fail;
2355
2356         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2357
2358         return 0;
2359
2360 fail:
2361         xhci_warn(xhci, "Couldn't initialize memory\n");
2362         xhci_halt(xhci);
2363         xhci_reset(xhci);
2364         xhci_mem_cleanup(xhci);
2365         return -ENOMEM;
2366 }