drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  38 {
  39         struct xhci_segment *seg;
  40         dma_addr_t      dma;
  41
  42         seg = kzalloc(sizeof *seg, flags);
  43         if (!seg)
  44                 return NULL;
  45         xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
  46
  47         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  48         if (!seg->trbs) {
  49                 kfree(seg);
  50                 return NULL;
  51         }
  52         xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
  53                         seg->trbs, (unsigned long long)dma);
  54
  55         memset(seg->trbs, 0, SEGMENT_SIZE);
  56         seg->dma = dma;
  57         seg->next = NULL;
  58
  59         return seg;
  60 }
  61
  62 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  63 {
  64         if (seg->trbs) {
  65                 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
  66                                 seg->trbs, (unsigned long long)seg->dma);
  67                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  68                 seg->trbs = NULL;
  69         }
  70         xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
  71         kfree(seg);
  72 }
  73
  74 /*
  75  * Make the prev segment point to the next segment.
  76  *
  77  * Change the last TRB in the prev segment to be a Link TRB which points to the
  78  * DMA address of the next segment.  The caller needs to set any Link TRB
  79  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  80  */
  81 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  82                 struct xhci_segment *next, bool link_trbs, bool isoc)
  83 {
  84         u32 val;
  85
  86         if (!prev || !next)
  87                 return;
  88         prev->next = next;
  89         if (link_trbs) {
  90                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
  91                         cpu_to_le64(next->dma);
  92
  93                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  94                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  95                 val &= ~TRB_TYPE_BITMASK;
  96                 val |= TRB_TYPE(TRB_LINK);
  97                 /* Always set the chain bit with 0.95 hardware */
  98                 /* Set chain bit for isoc rings on AMD 0.96 host */
  99                 if (xhci_link_trb_quirk(xhci) ||
 100                                 (isoc && (xhci->quirks & XHCI_AMD_0x96_HOST)))
 101                         val |= TRB_CHAIN;
 102                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 103         }
 104         xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
 105                         (unsigned long long)prev->dma,
 106                         (unsigned long long)next->dma);
 107 }
 108
 109 /* XXX: Do we need the hcd structure in all these functions? */
 110 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 111 {
 112         struct xhci_segment *seg;
 113         struct xhci_segment *first_seg;
 114
 115         if (!ring)
 116                 return;
 117         if (ring->first_seg) {
 118                 first_seg = ring->first_seg;
 119                 seg = first_seg->next;
 120                 xhci_dbg(xhci, "Freeing ring at %p\n", ring);
 121                 while (seg != first_seg) {
 122                         struct xhci_segment *next = seg->next;
 123                         xhci_segment_free(xhci, seg);
 124                         seg = next;
 125                 }
 126                 xhci_segment_free(xhci, first_seg);
 127                 ring->first_seg = NULL;
 128         }
 129         kfree(ring);
 130 }
 131
 132 static void xhci_initialize_ring_info(struct xhci_ring *ring)
 133 {
 134         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 135         ring->enqueue = ring->first_seg->trbs;
 136         ring->enq_seg = ring->first_seg;
 137         ring->dequeue = ring->enqueue;
 138         ring->deq_seg = ring->first_seg;
 139         /* The ring is initialized to 0. The producer must write 1 to the cycle
 140          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 141          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 142          */
 143         ring->cycle_state = 1;
 144         /* Not necessary for new rings, but needed for re-initialized rings */
 145         ring->enq_updates = 0;
 146         ring->deq_updates = 0;
 147 }
 148
 149 /**
 150  * Create a new ring with zero or more segments.
 151  *
 152  * Link each segment together into a ring.
 153  * Set the end flag and the cycle toggle bit on the last segment.
 154  * See section 4.9.1 and figures 15 and 16.
 155  */
 156 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 157                 unsigned int num_segs, bool link_trbs, bool isoc, gfp_t flags)
 158 {
 159         struct xhci_ring        *ring;
 160         struct xhci_segment     *prev;
 161
 162         ring = kzalloc(sizeof *(ring), flags);
 163         xhci_dbg(xhci, "Allocating ring at %p\n", ring);
 164         if (!ring)
 165                 return NULL;
 166
 167         INIT_LIST_HEAD(&ring->td_list);
 168         if (num_segs == 0)
 169                 return ring;
 170
 171         ring->first_seg = xhci_segment_alloc(xhci, flags);
 172         if (!ring->first_seg)
 173                 goto fail;
 174         num_segs--;
 175
 176         prev = ring->first_seg;
 177         while (num_segs > 0) {
 178                 struct xhci_segment     *next;
 179
 180                 next = xhci_segment_alloc(xhci, flags);
 181                 if (!next) {
 182                         prev = ring->first_seg;
 183                         while (prev) {
 184                                 next = prev->next;
 185                                 xhci_segment_free(xhci, prev);
 186                                 prev = next;
 187                         }
 188                         goto fail;
 189                 }
 190                 xhci_link_segments(xhci, prev, next, link_trbs, isoc);
 191
 192                 prev = next;
 193                 num_segs--;
 194         }
 195         xhci_link_segments(xhci, prev, ring->first_seg, link_trbs, isoc);
 196
 197         if (link_trbs) {
 198                 /* See section 4.9.2.1 and 6.4.4.1 */
 199                 prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
 200                         cpu_to_le32(LINK_TOGGLE);
 201                 xhci_dbg(xhci, "Wrote link toggle flag to"
 202                                 " segment %p (virtual), 0x%llx (DMA)\n",
 203                                 prev, (unsigned long long)prev->dma);
 204         }
 205         xhci_initialize_ring_info(ring);
 206         return ring;
 207
 208 fail:
 209         kfree(ring);
 210         return NULL;
 211 }
 212
 213 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 214                 struct xhci_virt_device *virt_dev,
 215                 unsigned int ep_index)
 216 {
 217         int rings_cached;
 218
 219         rings_cached = virt_dev->num_rings_cached;
 220         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 221                 virt_dev->ring_cache[rings_cached] =
 222                         virt_dev->eps[ep_index].ring;
 223                 virt_dev->num_rings_cached++;
 224                 xhci_dbg(xhci, "Cached old ring, "
 225                                 "%d ring%s cached\n",
 226                                 virt_dev->num_rings_cached,
 227                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 228         } else {
 229                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 230                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 231                                 "freeing ring\n",
 232                                 virt_dev->num_rings_cached);
 233         }
 234         virt_dev->eps[ep_index].ring = NULL;
 235 }
 236
 237 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 238  * pointers to the beginning of the ring.
 239  */
 240 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 241                 struct xhci_ring *ring, bool isoc)
 242 {
 243         struct xhci_segment     *seg = ring->first_seg;
 244         do {
 245                 memset(seg->trbs, 0,
 246                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 247                 /* All endpoint rings have link TRBs */
 248                 xhci_link_segments(xhci, seg, seg->next, 1, isoc);
 249                 seg = seg->next;
 250         } while (seg != ring->first_seg);
 251         xhci_initialize_ring_info(ring);
 252         /* td list should be empty since all URBs have been cancelled,
 253          * but just in case...
 254          */
 255         INIT_LIST_HEAD(&ring->td_list);
 256 }
 257
 258 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 259
 260 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 261                                                     int type, gfp_t flags)
 262 {
 263         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 264         if (!ctx)
 265                 return NULL;
 266
 267         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 268         ctx->type = type;
 269         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 270         if (type == XHCI_CTX_TYPE_INPUT)
 271                 ctx->size += CTX_SIZE(xhci->hcc_params);
 272
 273         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 274         memset(ctx->bytes, 0, ctx->size);
 275         return ctx;
 276 }
 277
 278 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 279                              struct xhci_container_ctx *ctx)
 280 {
 281         if (!ctx)
 282                 return;
 283         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 284         kfree(ctx);
 285 }
 286
 287 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 288                                               struct xhci_container_ctx *ctx)
 289 {
 290         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 291         return (struct xhci_input_control_ctx *)ctx->bytes;
 292 }
 293
 294 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 295                                         struct xhci_container_ctx *ctx)
 296 {
 297         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 298                 return (struct xhci_slot_ctx *)ctx->bytes;
 299
 300         return (struct xhci_slot_ctx *)
 301                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 302 }
 303
 304 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 305                                     struct xhci_container_ctx *ctx,
 306                                     unsigned int ep_index)
 307 {
 308         /* increment ep index by offset of start of ep ctx array */
 309         ep_index++;
 310         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 311                 ep_index++;
 312
 313         return (struct xhci_ep_ctx *)
 314                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 315 }
 316
 317
 318 /***************** Streams structures manipulation *************************/
 319
 320 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 321                 unsigned int num_stream_ctxs,
 322                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 323 {
 324         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 325
 326         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 327                 dma_free_coherent(&pdev->dev,
 328                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 329                                 stream_ctx, dma);
 330         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 331                 return dma_pool_free(xhci->small_streams_pool,
 332                                 stream_ctx, dma);
 333         else
 334                 return dma_pool_free(xhci->medium_streams_pool,
 335                                 stream_ctx, dma);
 336 }
 337
 338 /*
 339  * The stream context array for each endpoint with bulk streams enabled can
 340  * vary in size, based on:
 341  *  - how many streams the endpoint supports,
 342  *  - the maximum primary stream array size the host controller supports,
 343  *  - and how many streams the device driver asks for.
 344  *
 345  * The stream context array must be a power of 2, and can be as small as
 346  * 64 bytes or as large as 1MB.
 347  */
 348 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 349                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 350                 gfp_t mem_flags)
 351 {
 352         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 353
 354         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 355                 return dma_alloc_coherent(&pdev->dev,
 356                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 357                                 dma, mem_flags);
 358         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 359                 return dma_pool_alloc(xhci->small_streams_pool,
 360                                 mem_flags, dma);
 361         else
 362                 return dma_pool_alloc(xhci->medium_streams_pool,
 363                                 mem_flags, dma);
 364 }
 365
 366 struct xhci_ring *xhci_dma_to_transfer_ring(
 367                 struct xhci_virt_ep *ep,
 368                 u64 address)
 369 {
 370         if (ep->ep_state & EP_HAS_STREAMS)
 371                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 372                                 address >> SEGMENT_SHIFT);
 373         return ep->ring;
 374 }
 375
 376 /* Only use this when you know stream_info is valid */
 377 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 378 static struct xhci_ring *dma_to_stream_ring(
 379                 struct xhci_stream_info *stream_info,
 380                 u64 address)
 381 {
 382         return radix_tree_lookup(&stream_info->trb_address_map,
 383                         address >> SEGMENT_SHIFT);
 384 }
 385 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 386
 387 struct xhci_ring *xhci_stream_id_to_ring(
 388                 struct xhci_virt_device *dev,
 389                 unsigned int ep_index,
 390                 unsigned int stream_id)
 391 {
 392         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 393
 394         if (stream_id == 0)
 395                 return ep->ring;
 396         if (!ep->stream_info)
 397                 return NULL;
 398
 399         if (stream_id > ep->stream_info->num_streams)
 400                 return NULL;
 401         return ep->stream_info->stream_rings[stream_id];
 402 }
 403
 404 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 405 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 406                 unsigned int num_streams,
 407                 struct xhci_stream_info *stream_info)
 408 {
 409         u32 cur_stream;
 410         struct xhci_ring *cur_ring;
 411         u64 addr;
 412
 413         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 414                 struct xhci_ring *mapped_ring;
 415                 int trb_size = sizeof(union xhci_trb);
 416
 417                 cur_ring = stream_info->stream_rings[cur_stream];
 418                 for (addr = cur_ring->first_seg->dma;
 419                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
 420                                 addr += trb_size) {
 421                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 422                         if (cur_ring != mapped_ring) {
 423                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 424                                                 "didn't map to stream ID %u; "
 425                                                 "mapped to ring %p\n",
 426                                                 (unsigned long long) addr,
 427                                                 cur_stream,
 428                                                 mapped_ring);
 429                                 return -EINVAL;
 430                         }
 431                 }
 432                 /* One TRB after the end of the ring segment shouldn't return a
 433                  * pointer to the current ring (although it may be a part of a
 434                  * different ring).
 435                  */
 436                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 437                 if (mapped_ring != cur_ring) {
 438                         /* One TRB before should also fail */
 439                         addr = cur_ring->first_seg->dma - trb_size;
 440                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 441                 }
 442                 if (mapped_ring == cur_ring) {
 443                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 444                                         "mapped to valid stream ID %u; "
 445                                         "mapped ring = %p\n",
 446                                         (unsigned long long) addr,
 447                                         cur_stream,
 448                                         mapped_ring);
 449                         return -EINVAL;
 450                 }
 451         }
 452         return 0;
 453 }
 454 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 455
 456 /*
 457  * Change an endpoint's internal structure so it supports stream IDs.  The
 458  * number of requested streams includes stream 0, which cannot be used by device
 459  * drivers.
 460  *
 461  * The number of stream contexts in the stream context array may be bigger than
 462  * the number of streams the driver wants to use.  This is because the number of
 463  * stream context array entries must be a power of two.
 464  *
 465  * We need a radix tree for mapping physical addresses of TRBs to which stream
 466  * ID they belong to.  We need to do this because the host controller won't tell
 467  * us which stream ring the TRB came from.  We could store the stream ID in an
 468  * event data TRB, but that doesn't help us for the cancellation case, since the
 469  * endpoint may stop before it reaches that event data TRB.
 470  *
 471  * The radix tree maps the upper portion of the TRB DMA address to a ring
 472  * segment that has the same upper portion of DMA addresses.  For example, say I
 473  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 474  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 475  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 476  * pass the radix tree a key to get the right stream ID:
 477  *
 478  *      0x10c90fff >> 10 = 0x43243
 479  *      0x10c912c0 >> 10 = 0x43244
 480  *      0x10c91400 >> 10 = 0x43245
 481  *
 482  * Obviously, only those TRBs with DMA addresses that are within the segment
 483  * will make the radix tree return the stream ID for that ring.
 484  *
 485  * Caveats for the radix tree:
 486  *
 487  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 488  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 489  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 490  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 491  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 492  * extended systems (where the DMA address can be bigger than 32-bits),
 493  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 494  */
 495 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 496                 unsigned int num_stream_ctxs,
 497                 unsigned int num_streams, gfp_t mem_flags)
 498 {
 499         struct xhci_stream_info *stream_info;
 500         u32 cur_stream;
 501         struct xhci_ring *cur_ring;
 502         unsigned long key;
 503         u64 addr;
 504         int ret;
 505
 506         xhci_dbg(xhci, "Allocating %u streams and %u "
 507                         "stream context array entries.\n",
 508                         num_streams, num_stream_ctxs);
 509         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 510                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 511                 return NULL;
 512         }
 513         xhci->cmd_ring_reserved_trbs++;
 514
 515         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 516         if (!stream_info)
 517                 goto cleanup_trbs;
 518
 519         stream_info->num_streams = num_streams;
 520         stream_info->num_stream_ctxs = num_stream_ctxs;
 521
 522         /* Initialize the array of virtual pointers to stream rings. */
 523         stream_info->stream_rings = kzalloc(
 524                         sizeof(struct xhci_ring *)*num_streams,
 525                         mem_flags);
 526         if (!stream_info->stream_rings)
 527                 goto cleanup_info;
 528
 529         /* Initialize the array of DMA addresses for stream rings for the HW. */
 530         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 531                         num_stream_ctxs, &stream_info->ctx_array_dma,
 532                         mem_flags);
 533         if (!stream_info->stream_ctx_array)
 534                 goto cleanup_ctx;
 535         memset(stream_info->stream_ctx_array, 0,
 536                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 537
 538         /* Allocate everything needed to free the stream rings later */
 539         stream_info->free_streams_command =
 540                 xhci_alloc_command(xhci, true, true, mem_flags);
 541         if (!stream_info->free_streams_command)
 542                 goto cleanup_ctx;
 543
 544         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 545
 546         /* Allocate rings for all the streams that the driver will use,
 547          * and add their segment DMA addresses to the radix tree.
 548          * Stream 0 is reserved.
 549          */
 550         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 551                 stream_info->stream_rings[cur_stream] =
 552                         xhci_ring_alloc(xhci, 1, true, false, mem_flags);
 553                 cur_ring = stream_info->stream_rings[cur_stream];
 554                 if (!cur_ring)
 555                         goto cleanup_rings;
 556                 cur_ring->stream_id = cur_stream;
 557                 /* Set deq ptr, cycle bit, and stream context type */
 558                 addr = cur_ring->first_seg->dma |
 559                         SCT_FOR_CTX(SCT_PRI_TR) |
 560                         cur_ring->cycle_state;
 561                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 562                         cpu_to_le64(addr);
 563                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 564                                 cur_stream, (unsigned long long) addr);
 565
 566                 key = (unsigned long)
 567                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
 568                 ret = radix_tree_insert(&stream_info->trb_address_map,
 569                                 key, cur_ring);
 570                 if (ret) {
 571                         xhci_ring_free(xhci, cur_ring);
 572                         stream_info->stream_rings[cur_stream] = NULL;
 573                         goto cleanup_rings;
 574                 }
 575         }
 576         /* Leave the other unused stream ring pointers in the stream context
 577          * array initialized to zero.  This will cause the xHC to give us an
 578          * error if the device asks for a stream ID we don't have setup (if it
 579          * was any other way, the host controller would assume the ring is
 580          * "empty" and wait forever for data to be queued to that stream ID).
 581          */
 582 #if XHCI_DEBUG
 583         /* Do a little test on the radix tree to make sure it returns the
 584          * correct values.
 585          */
 586         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 587                 goto cleanup_rings;
 588 #endif
 589
 590         return stream_info;
 591
 592 cleanup_rings:
 593         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 594                 cur_ring = stream_info->stream_rings[cur_stream];
 595                 if (cur_ring) {
 596                         addr = cur_ring->first_seg->dma;
 597                         radix_tree_delete(&stream_info->trb_address_map,
 598                                         addr >> SEGMENT_SHIFT);
 599                         xhci_ring_free(xhci, cur_ring);
 600                         stream_info->stream_rings[cur_stream] = NULL;
 601                 }
 602         }
 603         xhci_free_command(xhci, stream_info->free_streams_command);
 604 cleanup_ctx:
 605         kfree(stream_info->stream_rings);
 606 cleanup_info:
 607         kfree(stream_info);
 608 cleanup_trbs:
 609         xhci->cmd_ring_reserved_trbs--;
 610         return NULL;
 611 }
 612 /*
 613  * Sets the MaxPStreams field and the Linear Stream Array field.
 614  * Sets the dequeue pointer to the stream context array.
 615  */
 616 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 617                 struct xhci_ep_ctx *ep_ctx,
 618                 struct xhci_stream_info *stream_info)
 619 {
 620         u32 max_primary_streams;
 621         /* MaxPStreams is the number of stream context array entries, not the
 622          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 623          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 624          */
 625         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 626         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 627                         1 << (max_primary_streams + 1));
 628         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 629         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 630                                        | EP_HAS_LSA);
 631         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 632 }
 633
 634 /*
 635  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 636  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 637  * not at the beginning of the ring).
 638  */
 639 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 640                 struct xhci_ep_ctx *ep_ctx,
 641                 struct xhci_virt_ep *ep)
 642 {
 643         dma_addr_t addr;
 644         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 645         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 646         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 647 }
 648
 649 /* Frees all stream contexts associated with the endpoint,
 650  *
 651  * Caller should fix the endpoint context streams fields.
 652  */
 653 void xhci_free_stream_info(struct xhci_hcd *xhci,
 654                 struct xhci_stream_info *stream_info)
 655 {
 656         int cur_stream;
 657         struct xhci_ring *cur_ring;
 658         dma_addr_t addr;
 659
 660         if (!stream_info)
 661                 return;
 662
 663         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 664                         cur_stream++) {
 665                 cur_ring = stream_info->stream_rings[cur_stream];
 666                 if (cur_ring) {
 667                         addr = cur_ring->first_seg->dma;
 668                         radix_tree_delete(&stream_info->trb_address_map,
 669                                         addr >> SEGMENT_SHIFT);
 670                         xhci_ring_free(xhci, cur_ring);
 671                         stream_info->stream_rings[cur_stream] = NULL;
 672                 }
 673         }
 674         xhci_free_command(xhci, stream_info->free_streams_command);
 675         xhci->cmd_ring_reserved_trbs--;
 676         if (stream_info->stream_ctx_array)
 677                 xhci_free_stream_ctx(xhci,
 678                                 stream_info->num_stream_ctxs,
 679                                 stream_info->stream_ctx_array,
 680                                 stream_info->ctx_array_dma);
 681
 682         if (stream_info)
 683                 kfree(stream_info->stream_rings);
 684         kfree(stream_info);
 685 }
 686
 687
 688 /***************** Device context manipulation *************************/
 689
 690 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 691                 struct xhci_virt_ep *ep)
 692 {
 693         init_timer(&ep->stop_cmd_timer);
 694         ep->stop_cmd_timer.data = (unsigned long) ep;
 695         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 696         ep->xhci = xhci;
 697 }
 698
 699 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 700                 struct xhci_virt_device *virt_dev,
 701                 int slot_id)
 702 {
 703         struct list_head *tt_list_head;
 704         struct xhci_tt_bw_info *tt_info, *next;
 705         bool slot_found = false;
 706
 707         /* If the device never made it past the Set Address stage,
 708          * it may not have the real_port set correctly.
 709          */
 710         if (virt_dev->real_port == 0 ||
 711                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 712                 xhci_dbg(xhci, "Bad real port.\n");
 713                 return;
 714         }
 715
 716         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 717         list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 718                 /* Multi-TT hubs will have more than one entry */
 719                 if (tt_info->slot_id == slot_id) {
 720                         slot_found = true;
 721                         list_del(&tt_info->tt_list);
 722                         kfree(tt_info);
 723                 } else if (slot_found) {
 724                         break;
 725                 }
 726         }
 727 }
 728
 729 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 730                 struct xhci_virt_device *virt_dev,
 731                 struct usb_device *hdev,
 732                 struct usb_tt *tt, gfp_t mem_flags)
 733 {
 734         struct xhci_tt_bw_info          *tt_info;
 735         unsigned int                    num_ports;
 736         int                             i, j;
 737
 738         if (!tt->multi)
 739                 num_ports = 1;
 740         else
 741                 num_ports = hdev->maxchild;
 742
 743         for (i = 0; i < num_ports; i++, tt_info++) {
 744                 struct xhci_interval_bw_table *bw_table;
 745
 746                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 747                 if (!tt_info)
 748                         goto free_tts;
 749                 INIT_LIST_HEAD(&tt_info->tt_list);
 750                 list_add(&tt_info->tt_list,
 751                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 752                 tt_info->slot_id = virt_dev->udev->slot_id;
 753                 if (tt->multi)
 754                         tt_info->ttport = i+1;
 755                 bw_table = &tt_info->bw_table;
 756                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 757                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 758         }
 759         return 0;
 760
 761 free_tts:
 762         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 763         return -ENOMEM;
 764 }
 765
 766
 767 /* All the xhci_tds in the ring's TD list should be freed at this point.
 768  * Should be called with xhci->lock held if there is any chance the TT lists
 769  * will be manipulated by the configure endpoint, allocate device, or update
 770  * hub functions while this function is removing the TT entries from the list.
 771  */
 772 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 773 {
 774         struct xhci_virt_device *dev;
 775         int i;
 776         int old_active_eps = 0;
 777
 778         /* Slot ID 0 is reserved */
 779         if (slot_id == 0 || !xhci->devs[slot_id])
 780                 return;
 781
 782         dev = xhci->devs[slot_id];
 783         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 784         if (!dev)
 785                 return;
 786
 787         if (dev->tt_info)
 788                 old_active_eps = dev->tt_info->active_eps;
 789
 790         for (i = 0; i < 31; ++i) {
 791                 if (dev->eps[i].ring)
 792                         xhci_ring_free(xhci, dev->eps[i].ring);
 793                 if (dev->eps[i].stream_info)
 794                         xhci_free_stream_info(xhci,
 795                                         dev->eps[i].stream_info);
 796                 /* Endpoints on the TT/root port lists should have been removed
 797                  * when usb_disable_device() was called for the device.
 798                  * We can't drop them anyway, because the udev might have gone
 799                  * away by this point, and we can't tell what speed it was.
 800                  */
 801                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 802                         xhci_warn(xhci, "Slot %u endpoint %u "
 803                                         "not removed from BW list!\n",
 804                                         slot_id, i);
 805         }
 806         /* If this is a hub, free the TT(s) from the TT list */
 807         xhci_free_tt_info(xhci, dev, slot_id);
 808         /* If necessary, update the number of active TTs on this root port */
 809         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 810
 811         if (dev->ring_cache) {
 812                 for (i = 0; i < dev->num_rings_cached; i++)
 813                         xhci_ring_free(xhci, dev->ring_cache[i]);
 814                 kfree(dev->ring_cache);
 815         }
 816
 817         if (dev->in_ctx)
 818                 xhci_free_container_ctx(xhci, dev->in_ctx);
 819         if (dev->out_ctx)
 820                 xhci_free_container_ctx(xhci, dev->out_ctx);
 821
 822         kfree(xhci->devs[slot_id]);
 823         xhci->devs[slot_id] = NULL;
 824 }
 825
 826 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 827                 struct usb_device *udev, gfp_t flags)
 828 {
 829         struct xhci_virt_device *dev;
 830         int i;
 831
 832         /* Slot ID 0 is reserved */
 833         if (slot_id == 0 || xhci->devs[slot_id]) {
 834                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 835                 return 0;
 836         }
 837
 838         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 839         if (!xhci->devs[slot_id])
 840                 return 0;
 841         dev = xhci->devs[slot_id];
 842
 843         /* Allocate the (output) device context that will be used in the HC. */
 844         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 845         if (!dev->out_ctx)
 846                 goto fail;
 847
 848         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 849                         (unsigned long long)dev->out_ctx->dma);
 850
 851         /* Allocate the (input) device context for address device command */
 852         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 853         if (!dev->in_ctx)
 854                 goto fail;
 855
 856         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 857                         (unsigned long long)dev->in_ctx->dma);
 858
 859         /* Initialize the cancellation list and watchdog timers for each ep */
 860         for (i = 0; i < 31; i++) {
 861                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 862                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 863                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
 864         }
 865
 866         /* Allocate endpoint 0 ring */
 867         dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, false, flags);
 868         if (!dev->eps[0].ring)
 869                 goto fail;
 870
 871         /* Allocate pointers to the ring cache */
 872         dev->ring_cache = kzalloc(
 873                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 874                         flags);
 875         if (!dev->ring_cache)
 876                 goto fail;
 877         dev->num_rings_cached = 0;
 878
 879         init_completion(&dev->cmd_completion);
 880         INIT_LIST_HEAD(&dev->cmd_list);
 881         dev->udev = udev;
 882
 883         /* Point to output device context in dcbaa. */
 884         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 885         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 886                  slot_id,
 887                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 888                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 889
 890         return 1;
 891 fail:
 892         xhci_free_virt_device(xhci, slot_id);
 893         return 0;
 894 }
 895
 896 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 897                 struct usb_device *udev)
 898 {
 899         struct xhci_virt_device *virt_dev;
 900         struct xhci_ep_ctx      *ep0_ctx;
 901         struct xhci_ring        *ep_ring;
 902
 903         virt_dev = xhci->devs[udev->slot_id];
 904         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
 905         ep_ring = virt_dev->eps[0].ring;
 906         /*
 907          * FIXME we don't keep track of the dequeue pointer very well after a
 908          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
 909          * host to our enqueue pointer.  This should only be called after a
 910          * configured device has reset, so all control transfers should have
 911          * been completed or cancelled before the reset.
 912          */
 913         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
 914                                                         ep_ring->enqueue)
 915                                    | ep_ring->cycle_state);
 916 }
 917
 918 /*
 919  * The xHCI roothub may have ports of differing speeds in any order in the port
 920  * status registers.  xhci->port_array provides an array of the port speed for
 921  * each offset into the port status registers.
 922  *
 923  * The xHCI hardware wants to know the roothub port number that the USB device
 924  * is attached to (or the roothub port its ancestor hub is attached to).  All we
 925  * know is the index of that port under either the USB 2.0 or the USB 3.0
 926  * roothub, but that doesn't give us the real index into the HW port status
 927  * registers.  Scan through the xHCI roothub port array, looking for the Nth
 928  * entry of the correct port speed.  Return the port number of that entry.
 929  */
 930 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
 931                 struct usb_device *udev)
 932 {
 933         struct usb_device *top_dev;
 934         unsigned int num_similar_speed_ports;
 935         unsigned int faked_port_num;
 936         int i;
 937
 938         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 939                         top_dev = top_dev->parent)
 940                 /* Found device below root hub */;
 941         faked_port_num = top_dev->portnum;
 942         for (i = 0, num_similar_speed_ports = 0;
 943                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
 944                 u8 port_speed = xhci->port_array[i];
 945
 946                 /*
 947                  * Skip ports that don't have known speeds, or have duplicate
 948                  * Extended Capabilities port speed entries.
 949                  */
 950                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
 951                         continue;
 952
 953                 /*
 954                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
 955                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
 956                  * matches the device speed, it's a similar speed port.
 957                  */
 958                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
 959                         num_similar_speed_ports++;
 960                 if (num_similar_speed_ports == faked_port_num)
 961                         /* Roothub ports are numbered from 1 to N */
 962                         return i+1;
 963         }
 964         return 0;
 965 }
 966
 967 /* Setup an xHCI virtual device for a Set Address command */
 968 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
 969 {
 970         struct xhci_virt_device *dev;
 971         struct xhci_ep_ctx      *ep0_ctx;
 972         struct xhci_slot_ctx    *slot_ctx;
 973         u32                     port_num;
 974         struct usb_device *top_dev;
 975
 976         dev = xhci->devs[udev->slot_id];
 977         /* Slot ID 0 is reserved */
 978         if (udev->slot_id == 0 || !dev) {
 979                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
 980                                 udev->slot_id);
 981                 return -EINVAL;
 982         }
 983         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
 984         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
 985
 986         /* 3) Only the control endpoint is valid - one endpoint context */
 987         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
 988         switch (udev->speed) {
 989         case USB_SPEED_SUPER:
 990                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
 991                 break;
 992         case USB_SPEED_HIGH:
 993                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
 994                 break;
 995         case USB_SPEED_FULL:
 996                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
 997                 break;
 998         case USB_SPEED_LOW:
 999                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1000                 break;
1001         case USB_SPEED_WIRELESS:
1002                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1003                 return -EINVAL;
1004                 break;
1005         default:
1006                 /* Speed was set earlier, this shouldn't happen. */
1007                 BUG();
1008         }
1009         /* Find the root hub port this device is under */
1010         port_num = xhci_find_real_port_number(xhci, udev);
1011         if (!port_num)
1012                 return -EINVAL;
1013         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1014         /* Set the port number in the virtual_device to the faked port number */
1015         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1016                         top_dev = top_dev->parent)
1017                 /* Found device below root hub */;
1018         dev->fake_port = top_dev->portnum;
1019         dev->real_port = port_num;
1020         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1021         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1022
1023         /* Find the right bandwidth table that this device will be a part of.
1024          * If this is a full speed device attached directly to a root port (or a
1025          * decendent of one), it counts as a primary bandwidth domain, not a
1026          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1027          * will never be created for the HS root hub.
1028          */
1029         if (!udev->tt || !udev->tt->hub->parent) {
1030                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1031         } else {
1032                 struct xhci_root_port_bw_info *rh_bw;
1033                 struct xhci_tt_bw_info *tt_bw;
1034
1035                 rh_bw = &xhci->rh_bw[port_num - 1];
1036                 /* Find the right TT. */
1037                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1038                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1039                                 continue;
1040
1041                         if (!dev->udev->tt->multi ||
1042                                         (udev->tt->multi &&
1043                                          tt_bw->ttport == dev->udev->ttport)) {
1044                                 dev->bw_table = &tt_bw->bw_table;
1045                                 dev->tt_info = tt_bw;
1046                                 break;
1047                         }
1048                 }
1049                 if (!dev->tt_info)
1050                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1051         }
1052
1053         /* Is this a LS/FS device under an external HS hub? */
1054         if (udev->tt && udev->tt->hub->parent) {
1055                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1056                                                 (udev->ttport << 8));
1057                 if (udev->tt->multi)
1058                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1059         }
1060         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1061         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1062
1063         /* Step 4 - ring already allocated */
1064         /* Step 5 */
1065         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1066         /*
1067          * XXX: Not sure about wireless USB devices.
1068          */
1069         switch (udev->speed) {
1070         case USB_SPEED_SUPER:
1071                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1072                 break;
1073         case USB_SPEED_HIGH:
1074         /* USB core guesses at a 64-byte max packet first for FS devices */
1075         case USB_SPEED_FULL:
1076                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1077                 break;
1078         case USB_SPEED_LOW:
1079                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1080                 break;
1081         case USB_SPEED_WIRELESS:
1082                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1083                 return -EINVAL;
1084                 break;
1085         default:
1086                 /* New speed? */
1087                 BUG();
1088         }
1089         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1090         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1091
1092         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1093                                    dev->eps[0].ring->cycle_state);
1094
1095         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1096
1097         return 0;
1098 }
1099
1100 /*
1101  * Convert interval expressed as 2^(bInterval - 1) == interval into
1102  * straight exponent value 2^n == interval.
1103  *
1104  */
1105 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1106                 struct usb_host_endpoint *ep)
1107 {
1108         unsigned int interval;
1109
1110         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1111         if (interval != ep->desc.bInterval - 1)
1112                 dev_warn(&udev->dev,
1113                          "ep %#x - rounding interval to %d %sframes\n",
1114                          ep->desc.bEndpointAddress,
1115                          1 << interval,
1116                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1117
1118         if (udev->speed == USB_SPEED_FULL) {
1119                 /*
1120                  * Full speed isoc endpoints specify interval in frames,
1121                  * not microframes. We are using microframes everywhere,
1122                  * so adjust accordingly.
1123                  */
1124                 interval += 3;  /* 1 frame = 2^3 uframes */
1125         }
1126
1127         return interval;
1128 }
1129
1130 /*
1131  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1132  * microframes, rounded down to nearest power of 2.
1133  */
1134 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1135                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1136                 unsigned int min_exponent, unsigned int max_exponent)
1137 {
1138         unsigned int interval;
1139
1140         interval = fls(desc_interval) - 1;
1141         interval = clamp_val(interval, min_exponent, max_exponent);
1142         if ((1 << interval) != desc_interval)
1143                 dev_warn(&udev->dev,
1144                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1145                          ep->desc.bEndpointAddress,
1146                          1 << interval,
1147                          desc_interval);
1148
1149         return interval;
1150 }
1151
1152 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1153                 struct usb_host_endpoint *ep)
1154 {
1155         if (ep->desc.bInterval == 0)
1156                 return 0;
1157         return xhci_microframes_to_exponent(udev, ep,
1158                         ep->desc.bInterval, 0, 15);
1159 }
1160
1161
1162 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1163                 struct usb_host_endpoint *ep)
1164 {
1165         return xhci_microframes_to_exponent(udev, ep,
1166                         ep->desc.bInterval * 8, 3, 10);
1167 }
1168
1169 /* Return the polling or NAK interval.
1170  *
1171  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1172  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1173  *
1174  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1175  * is set to 0.
1176  */
1177 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1178                 struct usb_host_endpoint *ep)
1179 {
1180         unsigned int interval = 0;
1181
1182         switch (udev->speed) {
1183         case USB_SPEED_HIGH:
1184                 /* Max NAK rate */
1185                 if (usb_endpoint_xfer_control(&ep->desc) ||
1186                     usb_endpoint_xfer_bulk(&ep->desc)) {
1187                         interval = xhci_parse_microframe_interval(udev, ep);
1188                         break;
1189                 }
1190                 /* Fall through - SS and HS isoc/int have same decoding */
1191
1192         case USB_SPEED_SUPER:
1193                 if (usb_endpoint_xfer_int(&ep->desc) ||
1194                     usb_endpoint_xfer_isoc(&ep->desc)) {
1195                         interval = xhci_parse_exponent_interval(udev, ep);
1196                 }
1197                 break;
1198
1199         case USB_SPEED_FULL:
1200                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1201                         interval = xhci_parse_exponent_interval(udev, ep);
1202                         break;
1203                 }
1204                 /*
1205                  * Fall through for interrupt endpoint interval decoding
1206                  * since it uses the same rules as low speed interrupt
1207                  * endpoints.
1208                  */
1209
1210         case USB_SPEED_LOW:
1211                 if (usb_endpoint_xfer_int(&ep->desc) ||
1212                     usb_endpoint_xfer_isoc(&ep->desc)) {
1213
1214                         interval = xhci_parse_frame_interval(udev, ep);
1215                 }
1216                 break;
1217
1218         default:
1219                 BUG();
1220         }
1221         return EP_INTERVAL(interval);
1222 }
1223
1224 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1225  * High speed endpoint descriptors can define "the number of additional
1226  * transaction opportunities per microframe", but that goes in the Max Burst
1227  * endpoint context field.
1228  */
1229 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1230                 struct usb_host_endpoint *ep)
1231 {
1232         if (udev->speed != USB_SPEED_SUPER ||
1233                         !usb_endpoint_xfer_isoc(&ep->desc))
1234                 return 0;
1235         return ep->ss_ep_comp.bmAttributes;
1236 }
1237
1238 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1239                 struct usb_host_endpoint *ep)
1240 {
1241         int in;
1242         u32 type;
1243
1244         in = usb_endpoint_dir_in(&ep->desc);
1245         if (usb_endpoint_xfer_control(&ep->desc)) {
1246                 type = EP_TYPE(CTRL_EP);
1247         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1248                 if (in)
1249                         type = EP_TYPE(BULK_IN_EP);
1250                 else
1251                         type = EP_TYPE(BULK_OUT_EP);
1252         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1253                 if (in)
1254                         type = EP_TYPE(ISOC_IN_EP);
1255                 else
1256                         type = EP_TYPE(ISOC_OUT_EP);
1257         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1258                 if (in)
1259                         type = EP_TYPE(INT_IN_EP);
1260                 else
1261                         type = EP_TYPE(INT_OUT_EP);
1262         } else {
1263                 BUG();
1264         }
1265         return type;
1266 }
1267
1268 /* Return the maximum endpoint service interval time (ESIT) payload.
1269  * Basically, this is the maxpacket size, multiplied by the burst size
1270  * and mult size.
1271  */
1272 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1273                 struct usb_device *udev,
1274                 struct usb_host_endpoint *ep)
1275 {
1276         int max_burst;
1277         int max_packet;
1278
1279         /* Only applies for interrupt or isochronous endpoints */
1280         if (usb_endpoint_xfer_control(&ep->desc) ||
1281                         usb_endpoint_xfer_bulk(&ep->desc))
1282                 return 0;
1283
1284         if (udev->speed == USB_SPEED_SUPER)
1285                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1286
1287         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1288         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1289         /* A 0 in max burst means 1 transfer per ESIT */
1290         return max_packet * (max_burst + 1);
1291 }
1292
1293 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1294  * Drivers will have to call usb_alloc_streams() to do that.
1295  */
1296 int xhci_endpoint_init(struct xhci_hcd *xhci,
1297                 struct xhci_virt_device *virt_dev,
1298                 struct usb_device *udev,
1299                 struct usb_host_endpoint *ep,
1300                 gfp_t mem_flags)
1301 {
1302         unsigned int ep_index;
1303         struct xhci_ep_ctx *ep_ctx;
1304         struct xhci_ring *ep_ring;
1305         unsigned int max_packet;
1306         unsigned int max_burst;
1307         u32 max_esit_payload;
1308
1309         ep_index = xhci_get_endpoint_index(&ep->desc);
1310         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1311
1312         /* Set up the endpoint ring */
1313         /*
1314          * Isochronous endpoint ring needs bigger size because one isoc URB
1315          * carries multiple packets and it will insert multiple tds to the
1316          * ring.
1317          * This should be replaced with dynamic ring resizing in the future.
1318          */
1319         if (usb_endpoint_xfer_isoc(&ep->desc))
1320                 virt_dev->eps[ep_index].new_ring =
1321                         xhci_ring_alloc(xhci, 8, true, true, mem_flags);
1322         else
1323                 virt_dev->eps[ep_index].new_ring =
1324                         xhci_ring_alloc(xhci, 1, true, false, mem_flags);
1325         if (!virt_dev->eps[ep_index].new_ring) {
1326                 /* Attempt to use the ring cache */
1327                 if (virt_dev->num_rings_cached == 0)
1328                         return -ENOMEM;
1329                 virt_dev->eps[ep_index].new_ring =
1330                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1331                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1332                 virt_dev->num_rings_cached--;
1333                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1334                         usb_endpoint_xfer_isoc(&ep->desc) ? true : false);
1335         }
1336         virt_dev->eps[ep_index].skip = false;
1337         ep_ring = virt_dev->eps[ep_index].new_ring;
1338         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1339
1340         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1341                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1342
1343         /* FIXME dig Mult and streams info out of ep companion desc */
1344
1345         /* Allow 3 retries for everything but isoc;
1346          * CErr shall be set to 0 for Isoch endpoints.
1347          */
1348         if (!usb_endpoint_xfer_isoc(&ep->desc))
1349                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1350         else
1351                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1352
1353         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1354
1355         /* Set the max packet size and max burst */
1356         switch (udev->speed) {
1357         case USB_SPEED_SUPER:
1358                 max_packet = usb_endpoint_maxp(&ep->desc);
1359                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1360                 /* dig out max burst from ep companion desc */
1361                 max_packet = ep->ss_ep_comp.bMaxBurst;
1362                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1363                 break;
1364         case USB_SPEED_HIGH:
1365                 /* bits 11:12 specify the number of additional transaction
1366                  * opportunities per microframe (USB 2.0, section 9.6.6)
1367                  */
1368                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1369                                 usb_endpoint_xfer_int(&ep->desc)) {
1370                         max_burst = (usb_endpoint_maxp(&ep->desc)
1371                                      & 0x1800) >> 11;
1372                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1373                 }
1374                 /* Fall through */
1375         case USB_SPEED_FULL:
1376         case USB_SPEED_LOW:
1377                 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1378                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1379                 break;
1380         default:
1381                 BUG();
1382         }
1383         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1384         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1385
1386         /*
1387          * XXX no idea how to calculate the average TRB buffer length for bulk
1388          * endpoints, as the driver gives us no clue how big each scatter gather
1389          * list entry (or buffer) is going to be.
1390          *
1391          * For isochronous and interrupt endpoints, we set it to the max
1392          * available, until we have new API in the USB core to allow drivers to
1393          * declare how much bandwidth they actually need.
1394          *
1395          * Normally, it would be calculated by taking the total of the buffer
1396          * lengths in the TD and then dividing by the number of TRBs in a TD,
1397          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1398          * use Event Data TRBs, and we don't chain in a link TRB on short
1399          * transfers, we're basically dividing by 1.
1400          *
1401          * xHCI 1.0 specification indicates that the Average TRB Length should
1402          * be set to 8 for control endpoints.
1403          */
1404         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1405                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1406         else
1407                 ep_ctx->tx_info |=
1408                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1409
1410         /* FIXME Debug endpoint context */
1411         return 0;
1412 }
1413
1414 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1415                 struct xhci_virt_device *virt_dev,
1416                 struct usb_host_endpoint *ep)
1417 {
1418         unsigned int ep_index;
1419         struct xhci_ep_ctx *ep_ctx;
1420
1421         ep_index = xhci_get_endpoint_index(&ep->desc);
1422         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1423
1424         ep_ctx->ep_info = 0;
1425         ep_ctx->ep_info2 = 0;
1426         ep_ctx->deq = 0;
1427         ep_ctx->tx_info = 0;
1428         /* Don't free the endpoint ring until the set interface or configuration
1429          * request succeeds.
1430          */
1431 }
1432
1433 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1434 {
1435         bw_info->ep_interval = 0;
1436         bw_info->mult = 0;
1437         bw_info->num_packets = 0;
1438         bw_info->max_packet_size = 0;
1439         bw_info->type = 0;
1440         bw_info->max_esit_payload = 0;
1441 }
1442
1443 void xhci_update_bw_info(struct xhci_hcd *xhci,
1444                 struct xhci_container_ctx *in_ctx,
1445                 struct xhci_input_control_ctx *ctrl_ctx,
1446                 struct xhci_virt_device *virt_dev)
1447 {
1448         struct xhci_bw_info *bw_info;
1449         struct xhci_ep_ctx *ep_ctx;
1450         unsigned int ep_type;
1451         int i;
1452
1453         for (i = 1; i < 31; ++i) {
1454                 bw_info = &virt_dev->eps[i].bw_info;
1455
1456                 /* We can't tell what endpoint type is being dropped, but
1457                  * unconditionally clearing the bandwidth info for non-periodic
1458                  * endpoints should be harmless because the info will never be
1459                  * set in the first place.
1460                  */
1461                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1462                         /* Dropped endpoint */
1463                         xhci_clear_endpoint_bw_info(bw_info);
1464                         continue;
1465                 }
1466
1467                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1468                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1469                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1470
1471                         /* Ignore non-periodic endpoints */
1472                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1473                                         ep_type != ISOC_IN_EP &&
1474                                         ep_type != INT_IN_EP)
1475                                 continue;
1476
1477                         /* Added or changed endpoint */
1478                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1479                                         le32_to_cpu(ep_ctx->ep_info));
1480                         /* Number of packets and mult are zero-based in the
1481                          * input context, but we want one-based for the
1482                          * interval table.
1483                          */
1484                         bw_info->mult = CTX_TO_EP_MULT(
1485                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1486                         bw_info->num_packets = CTX_TO_MAX_BURST(
1487                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1488                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1489                                         le32_to_cpu(ep_ctx->ep_info2));
1490                         bw_info->type = ep_type;
1491                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1492                                         le32_to_cpu(ep_ctx->tx_info));
1493                 }
1494         }
1495 }
1496
1497 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1498  * Useful when you want to change one particular aspect of the endpoint and then
1499  * issue a configure endpoint command.
1500  */
1501 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1502                 struct xhci_container_ctx *in_ctx,
1503                 struct xhci_container_ctx *out_ctx,
1504                 unsigned int ep_index)
1505 {
1506         struct xhci_ep_ctx *out_ep_ctx;
1507         struct xhci_ep_ctx *in_ep_ctx;
1508
1509         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1510         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1511
1512         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1513         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1514         in_ep_ctx->deq = out_ep_ctx->deq;
1515         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1516 }
1517
1518 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1519  * Useful when you want to change one particular aspect of the endpoint and then
1520  * issue a configure endpoint command.  Only the context entries field matters,
1521  * but we'll copy the whole thing anyway.
1522  */
1523 void xhci_slot_copy(struct xhci_hcd *xhci,
1524                 struct xhci_container_ctx *in_ctx,
1525                 struct xhci_container_ctx *out_ctx)
1526 {
1527         struct xhci_slot_ctx *in_slot_ctx;
1528         struct xhci_slot_ctx *out_slot_ctx;
1529
1530         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1531         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1532
1533         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1534         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1535         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1536         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1537 }
1538
1539 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1540 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1541 {
1542         int i;
1543         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1544         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1545
1546         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1547
1548         if (!num_sp)
1549                 return 0;
1550
1551         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1552         if (!xhci->scratchpad)
1553                 goto fail_sp;
1554
1555         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1556                                      num_sp * sizeof(u64),
1557                                      &xhci->scratchpad->sp_dma, flags);
1558         if (!xhci->scratchpad->sp_array)
1559                 goto fail_sp2;
1560
1561         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1562         if (!xhci->scratchpad->sp_buffers)
1563                 goto fail_sp3;
1564
1565         xhci->scratchpad->sp_dma_buffers =
1566                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1567
1568         if (!xhci->scratchpad->sp_dma_buffers)
1569                 goto fail_sp4;
1570
1571         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1572         for (i = 0; i < num_sp; i++) {
1573                 dma_addr_t dma;
1574                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1575                                 flags);
1576                 if (!buf)
1577                         goto fail_sp5;
1578
1579                 xhci->scratchpad->sp_array[i] = dma;
1580                 xhci->scratchpad->sp_buffers[i] = buf;
1581                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1582         }
1583
1584         return 0;
1585
1586  fail_sp5:
1587         for (i = i - 1; i >= 0; i--) {
1588                 dma_free_coherent(dev, xhci->page_size,
1589                                     xhci->scratchpad->sp_buffers[i],
1590                                     xhci->scratchpad->sp_dma_buffers[i]);
1591         }
1592         kfree(xhci->scratchpad->sp_dma_buffers);
1593
1594  fail_sp4:
1595         kfree(xhci->scratchpad->sp_buffers);
1596
1597  fail_sp3:
1598         dma_free_coherent(dev, num_sp * sizeof(u64),
1599                             xhci->scratchpad->sp_array,
1600                             xhci->scratchpad->sp_dma);
1601
1602  fail_sp2:
1603         kfree(xhci->scratchpad);
1604         xhci->scratchpad = NULL;
1605
1606  fail_sp:
1607         return -ENOMEM;
1608 }
1609
1610 static void scratchpad_free(struct xhci_hcd *xhci)
1611 {
1612         int num_sp;
1613         int i;
1614         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1615
1616         if (!xhci->scratchpad)
1617                 return;
1618
1619         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1620
1621         for (i = 0; i < num_sp; i++) {
1622                 dma_free_coherent(&pdev->dev, xhci->page_size,
1623                                     xhci->scratchpad->sp_buffers[i],
1624                                     xhci->scratchpad->sp_dma_buffers[i]);
1625         }
1626         kfree(xhci->scratchpad->sp_dma_buffers);
1627         kfree(xhci->scratchpad->sp_buffers);
1628         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1629                             xhci->scratchpad->sp_array,
1630                             xhci->scratchpad->sp_dma);
1631         kfree(xhci->scratchpad);
1632         xhci->scratchpad = NULL;
1633 }
1634
1635 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1636                 bool allocate_in_ctx, bool allocate_completion,
1637                 gfp_t mem_flags)
1638 {
1639         struct xhci_command *command;
1640
1641         command = kzalloc(sizeof(*command), mem_flags);
1642         if (!command)
1643                 return NULL;
1644
1645         if (allocate_in_ctx) {
1646                 command->in_ctx =
1647                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1648                                         mem_flags);
1649                 if (!command->in_ctx) {
1650                         kfree(command);
1651                         return NULL;
1652                 }
1653         }
1654
1655         if (allocate_completion) {
1656                 command->completion =
1657                         kzalloc(sizeof(struct completion), mem_flags);
1658                 if (!command->completion) {
1659                         xhci_free_container_ctx(xhci, command->in_ctx);
1660                         kfree(command);
1661                         return NULL;
1662                 }
1663                 init_completion(command->completion);
1664         }
1665
1666         command->status = 0;
1667         INIT_LIST_HEAD(&command->cmd_list);
1668         return command;
1669 }
1670
1671 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1672 {
1673         if (urb_priv) {
1674                 kfree(urb_priv->td[0]);
1675                 kfree(urb_priv);
1676         }
1677 }
1678
1679 void xhci_free_command(struct xhci_hcd *xhci,
1680                 struct xhci_command *command)
1681 {
1682         xhci_free_container_ctx(xhci,
1683                         command->in_ctx);
1684         kfree(command->completion);
1685         kfree(command);
1686 }
1687
1688 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1689 {
1690         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1691         struct dev_info *dev_info, *next;
1692         struct xhci_cd  *cur_cd, *next_cd;
1693         unsigned long   flags;
1694         int size;
1695         int i, j, num_ports;
1696
1697         /* Free the Event Ring Segment Table and the actual Event Ring */
1698         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1699         if (xhci->erst.entries)
1700                 dma_free_coherent(&pdev->dev, size,
1701                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1702         xhci->erst.entries = NULL;
1703         xhci_dbg(xhci, "Freed ERST\n");
1704         if (xhci->event_ring)
1705                 xhci_ring_free(xhci, xhci->event_ring);
1706         xhci->event_ring = NULL;
1707         xhci_dbg(xhci, "Freed event ring\n");
1708
1709         xhci->cmd_ring_reserved_trbs = 0;
1710         if (xhci->cmd_ring)
1711                 xhci_ring_free(xhci, xhci->cmd_ring);
1712         xhci->cmd_ring = NULL;
1713         xhci_dbg(xhci, "Freed command ring\n");
1714         list_for_each_entry_safe(cur_cd, next_cd,
1715                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1716                 list_del(&cur_cd->cancel_cmd_list);
1717                 kfree(cur_cd);
1718         }
1719
1720         for (i = 1; i < MAX_HC_SLOTS; ++i)
1721                 xhci_free_virt_device(xhci, i);
1722
1723         if (xhci->segment_pool)
1724                 dma_pool_destroy(xhci->segment_pool);
1725         xhci->segment_pool = NULL;
1726         xhci_dbg(xhci, "Freed segment pool\n");
1727
1728         if (xhci->device_pool)
1729                 dma_pool_destroy(xhci->device_pool);
1730         xhci->device_pool = NULL;
1731         xhci_dbg(xhci, "Freed device context pool\n");
1732
1733         if (xhci->small_streams_pool)
1734                 dma_pool_destroy(xhci->small_streams_pool);
1735         xhci->small_streams_pool = NULL;
1736         xhci_dbg(xhci, "Freed small stream array pool\n");
1737
1738         if (xhci->medium_streams_pool)
1739                 dma_pool_destroy(xhci->medium_streams_pool);
1740         xhci->medium_streams_pool = NULL;
1741         xhci_dbg(xhci, "Freed medium stream array pool\n");
1742
1743         if (xhci->dcbaa)
1744                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1745                                 xhci->dcbaa, xhci->dcbaa->dma);
1746         xhci->dcbaa = NULL;
1747
1748         scratchpad_free(xhci);
1749
1750         spin_lock_irqsave(&xhci->lock, flags);
1751         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1752                 list_del(&dev_info->list);
1753                 kfree(dev_info);
1754         }
1755         spin_unlock_irqrestore(&xhci->lock, flags);
1756
1757         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1758         for (i = 0; i < num_ports; i++) {
1759                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1760                 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1761                         struct list_head *ep = &bwt->interval_bw[j].endpoints;
1762                         while (!list_empty(ep))
1763                                 list_del_init(ep->next);
1764                 }
1765         }
1766
1767         for (i = 0; i < num_ports; i++) {
1768                 struct xhci_tt_bw_info *tt, *n;
1769                 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1770                         list_del(&tt->tt_list);
1771                         kfree(tt);
1772                 }
1773         }
1774
1775         xhci->num_usb2_ports = 0;
1776         xhci->num_usb3_ports = 0;
1777         xhci->num_active_eps = 0;
1778         kfree(xhci->usb2_ports);
1779         kfree(xhci->usb3_ports);
1780         kfree(xhci->port_array);
1781         kfree(xhci->rh_bw);
1782
1783         xhci->page_size = 0;
1784         xhci->page_shift = 0;
1785         xhci->bus_state[0].bus_suspended = 0;
1786         xhci->bus_state[1].bus_suspended = 0;
1787 }
1788
1789 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1790                 struct xhci_segment *input_seg,
1791                 union xhci_trb *start_trb,
1792                 union xhci_trb *end_trb,
1793                 dma_addr_t input_dma,
1794                 struct xhci_segment *result_seg,
1795                 char *test_name, int test_number)
1796 {
1797         unsigned long long start_dma;
1798         unsigned long long end_dma;
1799         struct xhci_segment *seg;
1800
1801         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1802         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1803
1804         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1805         if (seg != result_seg) {
1806                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1807                                 test_name, test_number);
1808                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1809                                 "input DMA 0x%llx\n",
1810                                 input_seg,
1811                                 (unsigned long long) input_dma);
1812                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1813                                 "ending TRB %p (0x%llx DMA)\n",
1814                                 start_trb, start_dma,
1815                                 end_trb, end_dma);
1816                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1817                                 result_seg, seg);
1818                 return -1;
1819         }
1820         return 0;
1821 }
1822
1823 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1824 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1825 {
1826         struct {
1827                 dma_addr_t              input_dma;
1828                 struct xhci_segment     *result_seg;
1829         } simple_test_vector [] = {
1830                 /* A zeroed DMA field should fail */
1831                 { 0, NULL },
1832                 /* One TRB before the ring start should fail */
1833                 { xhci->event_ring->first_seg->dma - 16, NULL },
1834                 /* One byte before the ring start should fail */
1835                 { xhci->event_ring->first_seg->dma - 1, NULL },
1836                 /* Starting TRB should succeed */
1837                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1838                 /* Ending TRB should succeed */
1839                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1840                         xhci->event_ring->first_seg },
1841                 /* One byte after the ring end should fail */
1842                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1843                 /* One TRB after the ring end should fail */
1844                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1845                 /* An address of all ones should fail */
1846                 { (dma_addr_t) (~0), NULL },
1847         };
1848         struct {
1849                 struct xhci_segment     *input_seg;
1850                 union xhci_trb          *start_trb;
1851                 union xhci_trb          *end_trb;
1852                 dma_addr_t              input_dma;
1853                 struct xhci_segment     *result_seg;
1854         } complex_test_vector [] = {
1855                 /* Test feeding a valid DMA address from a different ring */
1856                 {       .input_seg = xhci->event_ring->first_seg,
1857                         .start_trb = xhci->event_ring->first_seg->trbs,
1858                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1859                         .input_dma = xhci->cmd_ring->first_seg->dma,
1860                         .result_seg = NULL,
1861                 },
1862                 /* Test feeding a valid end TRB from a different ring */
1863                 {       .input_seg = xhci->event_ring->first_seg,
1864                         .start_trb = xhci->event_ring->first_seg->trbs,
1865                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1866                         .input_dma = xhci->cmd_ring->first_seg->dma,
1867                         .result_seg = NULL,
1868                 },
1869                 /* Test feeding a valid start and end TRB from a different ring */
1870                 {       .input_seg = xhci->event_ring->first_seg,
1871                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1872                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1873                         .input_dma = xhci->cmd_ring->first_seg->dma,
1874                         .result_seg = NULL,
1875                 },
1876                 /* TRB in this ring, but after this TD */
1877                 {       .input_seg = xhci->event_ring->first_seg,
1878                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1879                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1880                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1881                         .result_seg = NULL,
1882                 },
1883                 /* TRB in this ring, but before this TD */
1884                 {       .input_seg = xhci->event_ring->first_seg,
1885                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1886                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1887                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1888                         .result_seg = NULL,
1889                 },
1890                 /* TRB in this ring, but after this wrapped TD */
1891                 {       .input_seg = xhci->event_ring->first_seg,
1892                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1893                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1894                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1895                         .result_seg = NULL,
1896                 },
1897                 /* TRB in this ring, but before this wrapped TD */
1898                 {       .input_seg = xhci->event_ring->first_seg,
1899                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1900                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1901                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1902                         .result_seg = NULL,
1903                 },
1904                 /* TRB not in this ring, and we have a wrapped TD */
1905                 {       .input_seg = xhci->event_ring->first_seg,
1906                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1907                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1908                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1909                         .result_seg = NULL,
1910                 },
1911         };
1912
1913         unsigned int num_tests;
1914         int i, ret;
1915
1916         num_tests = ARRAY_SIZE(simple_test_vector);
1917         for (i = 0; i < num_tests; i++) {
1918                 ret = xhci_test_trb_in_td(xhci,
1919                                 xhci->event_ring->first_seg,
1920                                 xhci->event_ring->first_seg->trbs,
1921                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1922                                 simple_test_vector[i].input_dma,
1923                                 simple_test_vector[i].result_seg,
1924                                 "Simple", i);
1925                 if (ret < 0)
1926                         return ret;
1927         }
1928
1929         num_tests = ARRAY_SIZE(complex_test_vector);
1930         for (i = 0; i < num_tests; i++) {
1931                 ret = xhci_test_trb_in_td(xhci,
1932                                 complex_test_vector[i].input_seg,
1933                                 complex_test_vector[i].start_trb,
1934                                 complex_test_vector[i].end_trb,
1935                                 complex_test_vector[i].input_dma,
1936                                 complex_test_vector[i].result_seg,
1937                                 "Complex", i);
1938                 if (ret < 0)
1939                         return ret;
1940         }
1941         xhci_dbg(xhci, "TRB math tests passed.\n");
1942         return 0;
1943 }
1944
1945 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1946 {
1947         u64 temp;
1948         dma_addr_t deq;
1949
1950         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
1951                         xhci->event_ring->dequeue);
1952         if (deq == 0 && !in_interrupt())
1953                 xhci_warn(xhci, "WARN something wrong with SW event ring "
1954                                 "dequeue ptr.\n");
1955         /* Update HC event ring dequeue pointer */
1956         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1957         temp &= ERST_PTR_MASK;
1958         /* Don't clear the EHB bit (which is RW1C) because
1959          * there might be more events to service.
1960          */
1961         temp &= ~ERST_EHB;
1962         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
1963                         "preserving EHB bit\n");
1964         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1965                         &xhci->ir_set->erst_dequeue);
1966 }
1967
1968 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
1969                 __le32 __iomem *addr, u8 major_revision)
1970 {
1971         u32 temp, port_offset, port_count;
1972         int i;
1973
1974         if (major_revision > 0x03) {
1975                 xhci_warn(xhci, "Ignoring unknown port speed, "
1976                                 "Ext Cap %p, revision = 0x%x\n",
1977                                 addr, major_revision);
1978                 /* Ignoring port protocol we can't understand. FIXME */
1979                 return;
1980         }
1981
1982         /* Port offset and count in the third dword, see section 7.2 */
1983         temp = xhci_readl(xhci, addr + 2);
1984         port_offset = XHCI_EXT_PORT_OFF(temp);
1985         port_count = XHCI_EXT_PORT_COUNT(temp);
1986         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
1987                         "count = %u, revision = 0x%x\n",
1988                         addr, port_offset, port_count, major_revision);
1989         /* Port count includes the current port offset */
1990         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
1991                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
1992                 return;
1993
1994         /* Check the host's USB2 LPM capability */
1995         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
1996                         (temp & XHCI_L1C)) {
1997                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
1998                 xhci->sw_lpm_support = 1;
1999         }
2000
2001         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2002                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2003                 xhci->sw_lpm_support = 1;
2004                 if (temp & XHCI_HLC) {
2005                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2006                         xhci->hw_lpm_support = 1;
2007                 }
2008         }
2009
2010         port_offset--;
2011         for (i = port_offset; i < (port_offset + port_count); i++) {
2012                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2013                 if (xhci->port_array[i] != 0) {
2014                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2015                                         " port %u\n", addr, i);
2016                         xhci_warn(xhci, "Port was marked as USB %u, "
2017                                         "duplicated as USB %u\n",
2018                                         xhci->port_array[i], major_revision);
2019                         /* Only adjust the roothub port counts if we haven't
2020                          * found a similar duplicate.
2021                          */
2022                         if (xhci->port_array[i] != major_revision &&
2023                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2024                                 if (xhci->port_array[i] == 0x03)
2025                                         xhci->num_usb3_ports--;
2026                                 else
2027                                         xhci->num_usb2_ports--;
2028                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2029                         }
2030                         /* FIXME: Should we disable the port? */
2031                         continue;
2032                 }
2033                 xhci->port_array[i] = major_revision;
2034                 if (major_revision == 0x03)
2035                         xhci->num_usb3_ports++;
2036                 else
2037                         xhci->num_usb2_ports++;
2038         }
2039         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2040 }
2041
2042 /*
2043  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2044  * specify what speeds each port is supposed to be.  We can't count on the port
2045  * speed bits in the PORTSC register being correct until a device is connected,
2046  * but we need to set up the two fake roothubs with the correct number of USB
2047  * 3.0 and USB 2.0 ports at host controller initialization time.
2048  */
2049 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2050 {
2051         __le32 __iomem *addr;
2052         u32 offset;
2053         unsigned int num_ports;
2054         int i, j, port_index;
2055
2056         addr = &xhci->cap_regs->hcc_params;
2057         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2058         if (offset == 0) {
2059                 xhci_err(xhci, "No Extended Capability registers, "
2060                                 "unable to set up roothub.\n");
2061                 return -ENODEV;
2062         }
2063
2064         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2065         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2066         if (!xhci->port_array)
2067                 return -ENOMEM;
2068
2069         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2070         if (!xhci->rh_bw)
2071                 return -ENOMEM;
2072         for (i = 0; i < num_ports; i++) {
2073                 struct xhci_interval_bw_table *bw_table;
2074
2075                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2076                 bw_table = &xhci->rh_bw[i].bw_table;
2077                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2078                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2079         }
2080
2081         /*
2082          * For whatever reason, the first capability offset is from the
2083          * capability register base, not from the HCCPARAMS register.
2084          * See section 5.3.6 for offset calculation.
2085          */
2086         addr = &xhci->cap_regs->hc_capbase + offset;
2087         while (1) {
2088                 u32 cap_id;
2089
2090                 cap_id = xhci_readl(xhci, addr);
2091                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2092                         xhci_add_in_port(xhci, num_ports, addr,
2093                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2094                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2095                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2096                                 == num_ports)
2097                         break;
2098                 /*
2099                  * Once you're into the Extended Capabilities, the offset is
2100                  * always relative to the register holding the offset.
2101                  */
2102                 addr += offset;
2103         }
2104
2105         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2106                 xhci_warn(xhci, "No ports on the roothubs?\n");
2107                 return -ENODEV;
2108         }
2109         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2110                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2111
2112         /* Place limits on the number of roothub ports so that the hub
2113          * descriptors aren't longer than the USB core will allocate.
2114          */
2115         if (xhci->num_usb3_ports > 15) {
2116                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2117                 xhci->num_usb3_ports = 15;
2118         }
2119         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2120                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2121                                 USB_MAXCHILDREN);
2122                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2123         }
2124
2125         /*
2126          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2127          * Not sure how the USB core will handle a hub with no ports...
2128          */
2129         if (xhci->num_usb2_ports) {
2130                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2131                                 xhci->num_usb2_ports, flags);
2132                 if (!xhci->usb2_ports)
2133                         return -ENOMEM;
2134
2135                 port_index = 0;
2136                 for (i = 0; i < num_ports; i++) {
2137                         if (xhci->port_array[i] == 0x03 ||
2138                                         xhci->port_array[i] == 0 ||
2139                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2140                                 continue;
2141
2142                         xhci->usb2_ports[port_index] =
2143                                 &xhci->op_regs->port_status_base +
2144                                 NUM_PORT_REGS*i;
2145                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2146                                         "addr = %p\n", i,
2147                                         xhci->usb2_ports[port_index]);
2148                         port_index++;
2149                         if (port_index == xhci->num_usb2_ports)
2150                                 break;
2151                 }
2152         }
2153         if (xhci->num_usb3_ports) {
2154                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2155                                 xhci->num_usb3_ports, flags);
2156                 if (!xhci->usb3_ports)
2157                         return -ENOMEM;
2158
2159                 port_index = 0;
2160                 for (i = 0; i < num_ports; i++)
2161                         if (xhci->port_array[i] == 0x03) {
2162                                 xhci->usb3_ports[port_index] =
2163                                         &xhci->op_regs->port_status_base +
2164                                         NUM_PORT_REGS*i;
2165                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2166                                                 "addr = %p\n", i,
2167                                                 xhci->usb3_ports[port_index]);
2168                                 port_index++;
2169                                 if (port_index == xhci->num_usb3_ports)
2170                                         break;
2171                         }
2172         }
2173         return 0;
2174 }
2175
2176 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2177 {
2178         dma_addr_t      dma;
2179         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2180         unsigned int    val, val2;
2181         u64             val_64;
2182         struct xhci_segment     *seg;
2183         u32 page_size;
2184         int i;
2185
2186         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2187         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2188         for (i = 0; i < 16; i++) {
2189                 if ((0x1 & page_size) != 0)
2190                         break;
2191                 page_size = page_size >> 1;
2192         }
2193         if (i < 16)
2194                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2195         else
2196                 xhci_warn(xhci, "WARN: no supported page size\n");
2197         /* Use 4K pages, since that's common and the minimum the HC supports */
2198         xhci->page_shift = 12;
2199         xhci->page_size = 1 << xhci->page_shift;
2200         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2201
2202         /*
2203          * Program the Number of Device Slots Enabled field in the CONFIG
2204          * register with the max value of slots the HC can handle.
2205          */
2206         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2207         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2208                         (unsigned int) val);
2209         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2210         val |= (val2 & ~HCS_SLOTS_MASK);
2211         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2212                         (unsigned int) val);
2213         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2214
2215         /*
2216          * Section 5.4.8 - doorbell array must be
2217          * "physically contiguous and 64-byte (cache line) aligned".
2218          */
2219         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2220                         GFP_KERNEL);
2221         if (!xhci->dcbaa)
2222                 goto fail;
2223         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2224         xhci->dcbaa->dma = dma;
2225         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2226                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2227         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2228
2229         /*
2230          * Initialize the ring segment pool.  The ring must be a contiguous
2231          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2232          * however, the command ring segment needs 64-byte aligned segments,
2233          * so we pick the greater alignment need.
2234          */
2235         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2236                         SEGMENT_SIZE, 64, xhci->page_size);
2237
2238         /* See Table 46 and Note on Figure 55 */
2239         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2240                         2112, 64, xhci->page_size);
2241         if (!xhci->segment_pool || !xhci->device_pool)
2242                 goto fail;
2243
2244         /* Linear stream context arrays don't have any boundary restrictions,
2245          * and only need to be 16-byte aligned.
2246          */
2247         xhci->small_streams_pool =
2248                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2249                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2250         xhci->medium_streams_pool =
2251                 dma_pool_create("xHCI 1KB stream ctx arrays",
2252                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2253         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2254          * will be allocated with dma_alloc_coherent()
2255          */
2256
2257         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2258                 goto fail;
2259
2260         /* Set up the command ring to have one segments for now. */
2261         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, false, flags);
2262         if (!xhci->cmd_ring)
2263                 goto fail;
2264         INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2265         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2266         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2267                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2268
2269         /* Set the address in the Command Ring Control register */
2270         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2271         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2272                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2273                 xhci->cmd_ring->cycle_state;
2274         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2275         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2276         xhci_dbg_cmd_ptrs(xhci);
2277
2278         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2279         val &= DBOFF_MASK;
2280         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2281                         " from cap regs base addr\n", val);
2282         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2283         xhci_dbg_regs(xhci);
2284         xhci_print_run_regs(xhci);
2285         /* Set ir_set to interrupt register set 0 */
2286         xhci->ir_set = &xhci->run_regs->ir_set[0];
2287
2288         /*
2289          * Event ring setup: Allocate a normal ring, but also setup
2290          * the event ring segment table (ERST).  Section 4.9.3.
2291          */
2292         xhci_dbg(xhci, "// Allocating event ring\n");
2293         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, false,
2294                                                 flags);
2295         if (!xhci->event_ring)
2296                 goto fail;
2297         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2298                 goto fail;
2299
2300         xhci->erst.entries = dma_alloc_coherent(dev,
2301                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2302                         GFP_KERNEL);
2303         if (!xhci->erst.entries)
2304                 goto fail;
2305         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2306                         (unsigned long long)dma);
2307
2308         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2309         xhci->erst.num_entries = ERST_NUM_SEGS;
2310         xhci->erst.erst_dma_addr = dma;
2311         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2312                         xhci->erst.num_entries,
2313                         xhci->erst.entries,
2314                         (unsigned long long)xhci->erst.erst_dma_addr);
2315
2316         /* set ring base address and size for each segment table entry */
2317         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2318                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2319                 entry->seg_addr = cpu_to_le64(seg->dma);
2320                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2321                 entry->rsvd = 0;
2322                 seg = seg->next;
2323         }
2324
2325         /* set ERST count with the number of entries in the segment table */
2326         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2327         val &= ERST_SIZE_MASK;
2328         val |= ERST_NUM_SEGS;
2329         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2330                         val);
2331         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2332
2333         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2334         /* set the segment table base address */
2335         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2336                         (unsigned long long)xhci->erst.erst_dma_addr);
2337         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2338         val_64 &= ERST_PTR_MASK;
2339         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2340         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2341
2342         /* Set the event ring dequeue address */
2343         xhci_set_hc_event_deq(xhci);
2344         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2345         xhci_print_ir_set(xhci, 0);
2346
2347         /*
2348          * XXX: Might need to set the Interrupter Moderation Register to
2349          * something other than the default (~1ms minimum between interrupts).
2350          * See section 5.5.1.2.
2351          */
2352         init_completion(&xhci->addr_dev);
2353         for (i = 0; i < MAX_HC_SLOTS; ++i)
2354                 xhci->devs[i] = NULL;
2355         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2356                 xhci->bus_state[0].resume_done[i] = 0;
2357                 xhci->bus_state[1].resume_done[i] = 0;
2358         }
2359
2360         if (scratchpad_alloc(xhci, flags))
2361                 goto fail;
2362         if (xhci_setup_port_arrays(xhci, flags))
2363                 goto fail;
2364
2365         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2366
2367         return 0;
2368
2369 fail:
2370         xhci_warn(xhci, "Couldn't initialize memory\n");
2371         xhci_halt(xhci);
2372         xhci_reset(xhci);
2373         xhci_mem_cleanup(xhci);
2374         return -ENOMEM;
2375 }