2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/gfp.h>
24 #include <asm/unaligned.h>
28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
32 /* usb 1.1 root hub device descriptor */
33 static u8 usb_bos_descriptor [] = {
34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
52 struct usb_hub_descriptor *desc, int ports)
56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
57 desc->bHubContrCurrent = 0;
59 desc->bNbrPorts = ports;
60 /* Ugh, these should be #defines, FIXME */
61 /* Using table 11-13 in USB 2.0 spec. */
63 /* Bits 1:0 - support port power switching, or power always on */
64 if (HCC_PPC(xhci->hcc_params))
68 /* Bit 2 - root hubs are not part of a compound device */
69 /* Bits 4:3 - individual port over current protection */
71 /* Bits 6:5 - no TTs in root ports */
72 /* Bit 7 - no port indicators */
73 desc->wHubCharacteristics = cpu_to_le16(temp);
76 /* Fill in the USB 2.0 roothub descriptor */
77 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
78 struct usb_hub_descriptor *desc)
82 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
86 ports = xhci->num_usb2_ports;
88 xhci_common_hub_descriptor(xhci, desc, ports);
89 desc->bDescriptorType = 0x29;
90 temp = 1 + (ports / 8);
91 desc->bDescLength = 7 + 2 * temp;
93 /* The Device Removable bits are reported on a byte granularity.
94 * If the port doesn't exist within that byte, the bit is set to 0.
96 memset(port_removable, 0, sizeof(port_removable));
97 for (i = 0; i < ports; i++) {
98 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
99 /* If a device is removable, PORTSC reports a 0, same as in the
100 * hub descriptor DeviceRemovable bits.
102 if (portsc & PORT_DEV_REMOVE)
103 /* This math is hairy because bit 0 of DeviceRemovable
104 * is reserved, and bit 1 is for port 1, etc.
106 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
109 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
110 * ports on it. The USB 2.0 specification says that there are two
111 * variable length fields at the end of the hub descriptor:
112 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
113 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
114 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
115 * 0xFF, so we initialize the both arrays (DeviceRemovable and
116 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
117 * set of ports that actually exist.
119 memset(desc->u.hs.DeviceRemovable, 0xff,
120 sizeof(desc->u.hs.DeviceRemovable));
121 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
122 sizeof(desc->u.hs.PortPwrCtrlMask));
124 for (i = 0; i < (ports + 1 + 7) / 8; i++)
125 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
129 /* Fill in the USB 3.0 roothub descriptor */
130 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
131 struct usb_hub_descriptor *desc)
138 ports = xhci->num_usb3_ports;
139 xhci_common_hub_descriptor(xhci, desc, ports);
140 desc->bDescriptorType = 0x2a;
141 desc->bDescLength = 12;
143 /* header decode latency should be zero for roothubs,
144 * see section 4.23.5.2.
146 desc->u.ss.bHubHdrDecLat = 0;
147 desc->u.ss.wHubDelay = 0;
150 /* bit 0 is reserved, bit 1 is for port 1, etc. */
151 for (i = 0; i < ports; i++) {
152 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
153 if (portsc & PORT_DEV_REMOVE)
154 port_removable |= 1 << (i + 1);
156 memset(&desc->u.ss.DeviceRemovable,
157 (__force __u16) cpu_to_le16(port_removable),
161 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
162 struct usb_hub_descriptor *desc)
165 if (hcd->speed == HCD_USB3)
166 xhci_usb3_hub_descriptor(hcd, xhci, desc);
168 xhci_usb2_hub_descriptor(hcd, xhci, desc);
172 static unsigned int xhci_port_speed(unsigned int port_status)
174 if (DEV_LOWSPEED(port_status))
175 return USB_PORT_STAT_LOW_SPEED;
176 if (DEV_HIGHSPEED(port_status))
177 return USB_PORT_STAT_HIGH_SPEED;
179 * FIXME: Yes, we should check for full speed, but the core uses that as
180 * a default in portspeed() in usb/core/hub.c (which is the only place
181 * USB_PORT_STAT_*_SPEED is used).
187 * These bits are Read Only (RO) and should be saved and written to the
188 * registers: 0, 3, 10:13, 30
189 * connect status, over-current status, port speed, and device removable.
190 * connect status and port speed are also sticky - meaning they're in
191 * the AUX well and they aren't changed by a hot, warm, or cold reset.
193 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
195 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
196 * bits 5:8, 9, 14:15, 25:27
197 * link state, port power, port indicator state, "wake on" enable state
199 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
201 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
204 #define XHCI_PORT_RW1S ((1<<4))
206 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
207 * bits 1, 17, 18, 19, 20, 21, 22, 23
208 * port enable/disable, and
209 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
210 * over-current, reset, link state, and L1 change
212 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
214 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
217 #define XHCI_PORT_RW ((1<<16))
219 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
222 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
225 * Given a port state, this function returns a value that would result in the
226 * port being in the same state, if the value was written to the port status
228 * Save Read Only (RO) bits and save read/write bits where
229 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
230 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
232 u32 xhci_port_state_to_neutral(u32 state)
234 /* Save read-only status and port state */
235 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
239 * find slot id based on port number.
240 * @port: The one-based port number from one of the two split roothubs.
242 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
247 enum usb_device_speed speed;
250 for (i = 0; i < MAX_HC_SLOTS; i++) {
253 speed = xhci->devs[i]->udev->speed;
254 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
255 && xhci->devs[i]->fake_port == port) {
266 * It issues stop endpoint command for EP 0 to 30. And wait the last command
268 * suspend will set to 1, if suspend bit need to set in command.
270 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
272 struct xhci_virt_device *virt_dev;
273 struct xhci_command *cmd;
280 virt_dev = xhci->devs[slot_id];
281 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
283 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
287 spin_lock_irqsave(&xhci->lock, flags);
288 for (i = LAST_EP_INDEX; i > 0; i--) {
289 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
290 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
292 cmd->command_trb = xhci->cmd_ring->enqueue;
293 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
294 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
295 xhci_ring_cmd_db(xhci);
296 spin_unlock_irqrestore(&xhci->lock, flags);
298 /* Wait for last stop endpoint command to finish */
299 timeleft = wait_for_completion_interruptible_timeout(
301 USB_CTRL_SET_TIMEOUT);
303 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
304 timeleft == 0 ? "Timeout" : "Signal");
305 spin_lock_irqsave(&xhci->lock, flags);
306 /* The timeout might have raced with the event ring handler, so
307 * only delete from the list if the item isn't poisoned.
309 if (cmd->cmd_list.next != LIST_POISON1)
310 list_del(&cmd->cmd_list);
311 spin_unlock_irqrestore(&xhci->lock, flags);
313 goto command_cleanup;
317 xhci_free_command(xhci, cmd);
322 * Ring device, it rings the all doorbells unconditionally.
324 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
328 for (i = 0; i < LAST_EP_INDEX + 1; i++)
329 if (xhci->devs[slot_id]->eps[i].ring &&
330 xhci->devs[slot_id]->eps[i].ring->dequeue)
331 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
336 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
337 u16 wIndex, __le32 __iomem *addr, u32 port_status)
339 /* Don't allow the USB core to disable SuperSpeed ports. */
340 if (hcd->speed == HCD_USB3) {
341 xhci_dbg(xhci, "Ignoring request to disable "
342 "SuperSpeed port.\n");
346 /* Write 1 to disable the port */
347 xhci_writel(xhci, port_status | PORT_PE, addr);
348 port_status = xhci_readl(xhci, addr);
349 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
350 wIndex, port_status);
353 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
354 u16 wIndex, __le32 __iomem *addr, u32 port_status)
356 char *port_change_bit;
360 case USB_PORT_FEAT_C_RESET:
362 port_change_bit = "reset";
364 case USB_PORT_FEAT_C_BH_PORT_RESET:
366 port_change_bit = "warm(BH) reset";
368 case USB_PORT_FEAT_C_CONNECTION:
370 port_change_bit = "connect";
372 case USB_PORT_FEAT_C_OVER_CURRENT:
374 port_change_bit = "over-current";
376 case USB_PORT_FEAT_C_ENABLE:
378 port_change_bit = "enable/disable";
380 case USB_PORT_FEAT_C_SUSPEND:
382 port_change_bit = "suspend/resume";
384 case USB_PORT_FEAT_C_PORT_LINK_STATE:
386 port_change_bit = "link state";
389 /* Should never happen */
392 /* Change bits are all write 1 to clear */
393 xhci_writel(xhci, port_status | status, addr);
394 port_status = xhci_readl(xhci, addr);
395 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
396 port_change_bit, wIndex, port_status);
399 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
402 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
404 if (hcd->speed == HCD_USB3) {
405 max_ports = xhci->num_usb3_ports;
406 *port_array = xhci->usb3_ports;
408 max_ports = xhci->num_usb2_ports;
409 *port_array = xhci->usb2_ports;
415 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
416 int port_id, u32 link_state)
420 temp = xhci_readl(xhci, port_array[port_id]);
421 temp = xhci_port_state_to_neutral(temp);
422 temp &= ~PORT_PLS_MASK;
423 temp |= PORT_LINK_STROBE | link_state;
424 xhci_writel(xhci, temp, port_array[port_id]);
427 /* Test and clear port RWC bit */
428 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
429 int port_id, u32 port_bit)
433 temp = xhci_readl(xhci, port_array[port_id]);
434 if (temp & port_bit) {
435 temp = xhci_port_state_to_neutral(temp);
437 xhci_writel(xhci, temp, port_array[port_id]);
441 /* Updates Link Status for super Speed port */
442 static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
444 u32 pls = status_reg & PORT_PLS_MASK;
446 /* resume state is a xHCI internal state.
447 * Do not report it to usb core.
449 if (pls == XDEV_RESUME)
452 /* When the CAS bit is set then warm reset
453 * should be performed on port
455 if (status_reg & PORT_CAS) {
456 /* The CAS bit can be set while the port is
458 * Only roothubs have CAS bit, so we
459 * pretend to be in compliance mode
460 * unless we're already in compliance
461 * or the inactive state.
463 if (pls != USB_SS_PORT_LS_COMP_MOD &&
464 pls != USB_SS_PORT_LS_SS_INACTIVE) {
465 pls = USB_SS_PORT_LS_COMP_MOD;
467 /* Return also connection bit -
468 * hub state machine resets port
469 * when this bit is set.
471 pls |= USB_PORT_STAT_CONNECTION;
474 * If CAS bit isn't set but the Port is already at
475 * Compliance Mode, fake a connection so the USB core
476 * notices the Compliance state and resets the port.
477 * This resolves an issue generated by the SN65LVPE502CP
478 * in which sometimes the port enters compliance mode
479 * caused by a delay on the host-device negotiation.
481 if (pls == USB_SS_PORT_LS_COMP_MOD)
482 pls |= USB_PORT_STAT_CONNECTION;
485 /* update status field */
490 * Function for Compliance Mode Quirk.
492 * This Function verifies if all xhc USB3 ports have entered U0, if so,
493 * the compliance mode timer is deleted. A port won't enter
494 * compliance mode if it has previously entered U0.
496 void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
498 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
499 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
501 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
504 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
505 xhci->port_status_u0 |= 1 << wIndex;
506 if (xhci->port_status_u0 == all_ports_seen_u0) {
507 del_timer_sync(&xhci->comp_mode_recovery_timer);
508 xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n");
509 xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n");
514 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
515 u16 wIndex, char *buf, u16 wLength)
517 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
522 __le32 __iomem **port_array;
524 struct xhci_bus_state *bus_state;
527 max_ports = xhci_get_ports(hcd, &port_array);
528 bus_state = &xhci->bus_state[hcd_index(hcd)];
530 spin_lock_irqsave(&xhci->lock, flags);
533 /* No power source, over-current reported per port */
536 case GetHubDescriptor:
537 /* Check to make sure userspace is asking for the USB 3.0 hub
538 * descriptor for the USB 3.0 roothub. If not, we stall the
539 * endpoint, like external hubs do.
541 if (hcd->speed == HCD_USB3 &&
542 (wLength < USB_DT_SS_HUB_SIZE ||
543 wValue != (USB_DT_SS_HUB << 8))) {
544 xhci_dbg(xhci, "Wrong hub descriptor type for "
545 "USB 3.0 roothub.\n");
548 xhci_hub_descriptor(hcd, xhci,
549 (struct usb_hub_descriptor *) buf);
551 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
552 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
555 if (hcd->speed != HCD_USB3)
558 memcpy(buf, &usb_bos_descriptor,
559 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
560 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
561 buf[12] = HCS_U1_LATENCY(temp);
562 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
564 spin_unlock_irqrestore(&xhci->lock, flags);
565 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
567 if (!wIndex || wIndex > max_ports)
571 temp = xhci_readl(xhci, port_array[wIndex]);
572 if (temp == 0xffffffff) {
576 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
578 /* wPortChange bits */
580 status |= USB_PORT_STAT_C_CONNECTION << 16;
582 status |= USB_PORT_STAT_C_ENABLE << 16;
583 if ((temp & PORT_OCC))
584 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
585 if ((temp & PORT_RC))
586 status |= USB_PORT_STAT_C_RESET << 16;
588 if (hcd->speed == HCD_USB3) {
589 if ((temp & PORT_PLC))
590 status |= USB_PORT_STAT_C_LINK_STATE << 16;
591 if ((temp & PORT_WRC))
592 status |= USB_PORT_STAT_C_BH_RESET << 16;
595 if (hcd->speed != HCD_USB3) {
596 if ((temp & PORT_PLS_MASK) == XDEV_U3
597 && (temp & PORT_POWER))
598 status |= USB_PORT_STAT_SUSPEND;
600 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
601 !DEV_SUPERSPEED(temp)) {
602 if ((temp & PORT_RESET) || !(temp & PORT_PE))
604 if (time_after_eq(jiffies,
605 bus_state->resume_done[wIndex])) {
606 xhci_dbg(xhci, "Resume USB2 port %d\n",
608 bus_state->resume_done[wIndex] = 0;
609 xhci_set_link_state(xhci, port_array, wIndex,
611 xhci_dbg(xhci, "set port %d resume\n",
613 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
616 xhci_dbg(xhci, "slot_id is zero\n");
619 xhci_ring_device(xhci, slot_id);
620 bus_state->port_c_suspend |= 1 << wIndex;
621 bus_state->suspended_ports &= ~(1 << wIndex);
624 * The resume has been signaling for less than
625 * 20ms. Report the port status as SUSPEND,
626 * let the usbcore check port status again
627 * and clear resume signaling later.
629 status |= USB_PORT_STAT_SUSPEND;
632 if ((temp & PORT_PLS_MASK) == XDEV_U0
633 && (temp & PORT_POWER)
634 && (bus_state->suspended_ports & (1 << wIndex))) {
635 bus_state->suspended_ports &= ~(1 << wIndex);
636 if (hcd->speed != HCD_USB3)
637 bus_state->port_c_suspend |= 1 << wIndex;
639 if (temp & PORT_CONNECT) {
640 status |= USB_PORT_STAT_CONNECTION;
641 status |= xhci_port_speed(temp);
644 status |= USB_PORT_STAT_ENABLE;
646 status |= USB_PORT_STAT_OVERCURRENT;
647 if (temp & PORT_RESET)
648 status |= USB_PORT_STAT_RESET;
649 if (temp & PORT_POWER) {
650 if (hcd->speed == HCD_USB3)
651 status |= USB_SS_PORT_STAT_POWER;
653 status |= USB_PORT_STAT_POWER;
655 /* Update Port Link State for super speed ports*/
656 if (hcd->speed == HCD_USB3) {
657 xhci_hub_report_link_state(&status, temp);
659 * Verify if all USB3 Ports Have entered U0 already.
660 * Delete Compliance Mode Timer if so.
662 xhci_del_comp_mod_timer(xhci, temp, wIndex);
664 if (bus_state->port_c_suspend & (1 << wIndex))
665 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
666 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
667 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
670 if (wValue == USB_PORT_FEAT_LINK_STATE)
671 link_state = (wIndex & 0xff00) >> 3;
673 if (!wIndex || wIndex > max_ports)
676 temp = xhci_readl(xhci, port_array[wIndex]);
677 if (temp == 0xffffffff) {
681 temp = xhci_port_state_to_neutral(temp);
682 /* FIXME: What new port features do we need to support? */
684 case USB_PORT_FEAT_SUSPEND:
685 temp = xhci_readl(xhci, port_array[wIndex]);
686 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
687 /* Resume the port to U0 first */
688 xhci_set_link_state(xhci, port_array, wIndex,
690 spin_unlock_irqrestore(&xhci->lock, flags);
692 spin_lock_irqsave(&xhci->lock, flags);
694 /* In spec software should not attempt to suspend
695 * a port unless the port reports that it is in the
696 * enabled (PED = ‘1’,PLS < ‘3’) state.
698 temp = xhci_readl(xhci, port_array[wIndex]);
699 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
700 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
701 xhci_warn(xhci, "USB core suspending device "
702 "not in U0/U1/U2.\n");
706 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
709 xhci_warn(xhci, "slot_id is zero\n");
712 /* unlock to execute stop endpoint commands */
713 spin_unlock_irqrestore(&xhci->lock, flags);
714 xhci_stop_device(xhci, slot_id, 1);
715 spin_lock_irqsave(&xhci->lock, flags);
717 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
719 spin_unlock_irqrestore(&xhci->lock, flags);
720 msleep(10); /* wait device to enter */
721 spin_lock_irqsave(&xhci->lock, flags);
723 temp = xhci_readl(xhci, port_array[wIndex]);
724 bus_state->suspended_ports |= 1 << wIndex;
726 case USB_PORT_FEAT_LINK_STATE:
727 temp = xhci_readl(xhci, port_array[wIndex]);
730 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
731 xhci_dbg(xhci, "Disable port %d\n", wIndex);
732 temp = xhci_port_state_to_neutral(temp);
734 * Clear all change bits, so that we get a new
737 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
738 PORT_OCC | PORT_RC | PORT_PLC |
740 xhci_writel(xhci, temp | PORT_PE,
742 temp = xhci_readl(xhci, port_array[wIndex]);
746 /* Put link in RxDetect (enable port) */
747 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
748 xhci_dbg(xhci, "Enable port %d\n", wIndex);
749 xhci_set_link_state(xhci, port_array, wIndex,
751 temp = xhci_readl(xhci, port_array[wIndex]);
755 /* Software should not attempt to set
756 * port link state above '3' (U3) and the port
759 if ((temp & PORT_PE) == 0 ||
760 (link_state > USB_SS_PORT_LS_U3)) {
761 xhci_warn(xhci, "Cannot set link state.\n");
765 if (link_state == USB_SS_PORT_LS_U3) {
766 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
769 /* unlock to execute stop endpoint
771 spin_unlock_irqrestore(&xhci->lock,
773 xhci_stop_device(xhci, slot_id, 1);
774 spin_lock_irqsave(&xhci->lock, flags);
778 xhci_set_link_state(xhci, port_array, wIndex,
781 spin_unlock_irqrestore(&xhci->lock, flags);
782 msleep(20); /* wait device to enter */
783 spin_lock_irqsave(&xhci->lock, flags);
785 temp = xhci_readl(xhci, port_array[wIndex]);
786 if (link_state == USB_SS_PORT_LS_U3)
787 bus_state->suspended_ports |= 1 << wIndex;
789 case USB_PORT_FEAT_POWER:
791 * Turn on ports, even if there isn't per-port switching.
792 * HC will report connect events even before this is set.
793 * However, khubd will ignore the roothub events until
794 * the roothub is registered.
796 xhci_writel(xhci, temp | PORT_POWER,
799 temp = xhci_readl(xhci, port_array[wIndex]);
800 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
802 case USB_PORT_FEAT_RESET:
803 temp = (temp | PORT_RESET);
804 xhci_writel(xhci, temp, port_array[wIndex]);
806 temp = xhci_readl(xhci, port_array[wIndex]);
807 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
809 case USB_PORT_FEAT_BH_PORT_RESET:
811 xhci_writel(xhci, temp, port_array[wIndex]);
813 temp = xhci_readl(xhci, port_array[wIndex]);
818 /* unblock any posted writes */
819 temp = xhci_readl(xhci, port_array[wIndex]);
821 case ClearPortFeature:
822 if (!wIndex || wIndex > max_ports)
825 temp = xhci_readl(xhci, port_array[wIndex]);
826 if (temp == 0xffffffff) {
830 /* FIXME: What new port features do we need to support? */
831 temp = xhci_port_state_to_neutral(temp);
833 case USB_PORT_FEAT_SUSPEND:
834 temp = xhci_readl(xhci, port_array[wIndex]);
835 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
836 xhci_dbg(xhci, "PORTSC %04x\n", temp);
837 if (temp & PORT_RESET)
839 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
840 if ((temp & PORT_PE) == 0)
843 xhci_set_link_state(xhci, port_array, wIndex,
845 spin_unlock_irqrestore(&xhci->lock, flags);
847 spin_lock_irqsave(&xhci->lock, flags);
848 xhci_set_link_state(xhci, port_array, wIndex,
851 bus_state->port_c_suspend |= 1 << wIndex;
853 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
856 xhci_dbg(xhci, "slot_id is zero\n");
859 xhci_ring_device(xhci, slot_id);
861 case USB_PORT_FEAT_C_SUSPEND:
862 bus_state->port_c_suspend &= ~(1 << wIndex);
863 case USB_PORT_FEAT_C_RESET:
864 case USB_PORT_FEAT_C_BH_PORT_RESET:
865 case USB_PORT_FEAT_C_CONNECTION:
866 case USB_PORT_FEAT_C_OVER_CURRENT:
867 case USB_PORT_FEAT_C_ENABLE:
868 case USB_PORT_FEAT_C_PORT_LINK_STATE:
869 xhci_clear_port_change_bit(xhci, wValue, wIndex,
870 port_array[wIndex], temp);
872 case USB_PORT_FEAT_ENABLE:
873 xhci_disable_port(hcd, xhci, wIndex,
874 port_array[wIndex], temp);
882 /* "stall" on error */
885 spin_unlock_irqrestore(&xhci->lock, flags);
890 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
891 * Ports are 0-indexed from the HCD point of view,
892 * and 1-indexed from the USB core pointer of view.
894 * Note that the status change bits will be cleared as soon as a port status
895 * change event is generated, so we use the saved status from that event.
897 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
903 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
905 __le32 __iomem **port_array;
906 struct xhci_bus_state *bus_state;
907 bool reset_change = false;
909 max_ports = xhci_get_ports(hcd, &port_array);
910 bus_state = &xhci->bus_state[hcd_index(hcd)];
912 /* Initial status is no changes */
913 retval = (max_ports + 8) / 8;
914 memset(buf, 0, retval);
917 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
919 spin_lock_irqsave(&xhci->lock, flags);
920 /* For each port, did anything change? If so, set that bit in buf. */
921 for (i = 0; i < max_ports; i++) {
922 temp = xhci_readl(xhci, port_array[i]);
923 if (temp == 0xffffffff) {
927 if ((temp & mask) != 0 ||
928 (bus_state->port_c_suspend & 1 << i) ||
929 (bus_state->resume_done[i] && time_after_eq(
930 jiffies, bus_state->resume_done[i]))) {
931 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
934 if ((temp & PORT_RC))
937 if (!status && !reset_change) {
938 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
939 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
941 spin_unlock_irqrestore(&xhci->lock, flags);
942 return status ? retval : 0;
947 int xhci_bus_suspend(struct usb_hcd *hcd)
949 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
950 int max_ports, port_index;
951 __le32 __iomem **port_array;
952 struct xhci_bus_state *bus_state;
955 max_ports = xhci_get_ports(hcd, &port_array);
956 bus_state = &xhci->bus_state[hcd_index(hcd)];
958 spin_lock_irqsave(&xhci->lock, flags);
960 if (hcd->self.root_hub->do_remote_wakeup) {
961 port_index = max_ports;
962 while (port_index--) {
963 if (bus_state->resume_done[port_index] != 0) {
964 spin_unlock_irqrestore(&xhci->lock, flags);
965 xhci_dbg(xhci, "suspend failed because "
966 "port %d is resuming\n",
973 port_index = max_ports;
974 bus_state->bus_suspended = 0;
975 while (port_index--) {
976 /* suspend the port if the port is not suspended */
980 t1 = xhci_readl(xhci, port_array[port_index]);
981 t2 = xhci_port_state_to_neutral(t1);
983 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
984 xhci_dbg(xhci, "port %d not suspended\n", port_index);
985 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
988 spin_unlock_irqrestore(&xhci->lock, flags);
989 xhci_stop_device(xhci, slot_id, 1);
990 spin_lock_irqsave(&xhci->lock, flags);
992 t2 &= ~PORT_PLS_MASK;
993 t2 |= PORT_LINK_STROBE | XDEV_U3;
994 set_bit(port_index, &bus_state->bus_suspended);
996 if (hcd->self.root_hub->do_remote_wakeup) {
997 if (t1 & PORT_CONNECT) {
998 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
999 t2 &= ~PORT_WKCONN_E;
1001 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1002 t2 &= ~PORT_WKDISC_E;
1005 t2 &= ~PORT_WAKE_BITS;
1007 t1 = xhci_port_state_to_neutral(t1);
1009 xhci_writel(xhci, t2, port_array[port_index]);
1011 if (hcd->speed != HCD_USB3) {
1012 /* enable remote wake up for USB 2.0 */
1013 __le32 __iomem *addr;
1016 /* Add one to the port status register address to get
1017 * the port power control register address.
1019 addr = port_array[port_index] + 1;
1020 tmp = xhci_readl(xhci, addr);
1022 xhci_writel(xhci, tmp, addr);
1025 hcd->state = HC_STATE_SUSPENDED;
1026 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1027 spin_unlock_irqrestore(&xhci->lock, flags);
1031 int xhci_bus_resume(struct usb_hcd *hcd)
1033 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1034 int max_ports, port_index;
1035 __le32 __iomem **port_array;
1036 struct xhci_bus_state *bus_state;
1038 unsigned long flags;
1040 max_ports = xhci_get_ports(hcd, &port_array);
1041 bus_state = &xhci->bus_state[hcd_index(hcd)];
1043 if (time_before(jiffies, bus_state->next_statechange))
1046 spin_lock_irqsave(&xhci->lock, flags);
1047 if (!HCD_HW_ACCESSIBLE(hcd)) {
1048 spin_unlock_irqrestore(&xhci->lock, flags);
1052 /* delay the irqs */
1053 temp = xhci_readl(xhci, &xhci->op_regs->command);
1055 xhci_writel(xhci, temp, &xhci->op_regs->command);
1057 port_index = max_ports;
1058 while (port_index--) {
1059 /* Check whether need resume ports. If needed
1060 resume port and disable remote wakeup */
1064 temp = xhci_readl(xhci, port_array[port_index]);
1065 if (DEV_SUPERSPEED(temp))
1066 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1068 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1069 if (test_bit(port_index, &bus_state->bus_suspended) &&
1070 (temp & PORT_PLS_MASK)) {
1071 if (DEV_SUPERSPEED(temp)) {
1072 xhci_set_link_state(xhci, port_array,
1073 port_index, XDEV_U0);
1075 xhci_set_link_state(xhci, port_array,
1076 port_index, XDEV_RESUME);
1078 spin_unlock_irqrestore(&xhci->lock, flags);
1080 spin_lock_irqsave(&xhci->lock, flags);
1082 xhci_set_link_state(xhci, port_array,
1083 port_index, XDEV_U0);
1085 /* wait for the port to enter U0 and report port link
1088 spin_unlock_irqrestore(&xhci->lock, flags);
1090 spin_lock_irqsave(&xhci->lock, flags);
1093 xhci_test_and_clear_bit(xhci, port_array, port_index,
1096 slot_id = xhci_find_slot_id_by_port(hcd,
1097 xhci, port_index + 1);
1099 xhci_ring_device(xhci, slot_id);
1101 xhci_writel(xhci, temp, port_array[port_index]);
1103 if (hcd->speed != HCD_USB3) {
1104 /* disable remote wake up for USB 2.0 */
1105 __le32 __iomem *addr;
1108 /* Add one to the port status register address to get
1109 * the port power control register address.
1111 addr = port_array[port_index] + 1;
1112 tmp = xhci_readl(xhci, addr);
1114 xhci_writel(xhci, tmp, addr);
1118 (void) xhci_readl(xhci, &xhci->op_regs->command);
1120 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1121 /* re-enable irqs */
1122 temp = xhci_readl(xhci, &xhci->op_regs->command);
1124 xhci_writel(xhci, temp, &xhci->op_regs->command);
1125 temp = xhci_readl(xhci, &xhci->op_regs->command);
1127 spin_unlock_irqrestore(&xhci->lock, flags);
1131 #endif /* CONFIG_PM */