drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11 #include <linux/slab.h>
  12
  13 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  14 {
  15         int             last = urb_priv->length - 1;
  16
  17         if (last >= 0) {
  18                 int             i;
  19                 struct td       *td;
  20
  21                 for (i = 0; i <= last; i++) {
  22                         td = urb_priv->td [i];
  23                         if (td)
  24                                 td_free (hc, td);
  25                 }
  26         }
  27
  28         list_del (&urb_priv->pending);
  29         kfree (urb_priv);
  30 }
  31
  32 /*-------------------------------------------------------------------------*/
  33
  34 /*
  35  * URB goes back to driver, and isn't reissued.
  36  * It's completely gone from HC data structures.
  37  * PRECONDITION:  ohci lock held, irqs blocked.
  38  */
  39 static void
  40 finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
  41 __releases(ohci->lock)
  42 __acquires(ohci->lock)
  43 {
  44         // ASSERT (urb->hcpriv != 0);
  45
  46         urb_free_priv (ohci, urb->hcpriv);
  47         if (likely(status == -EINPROGRESS))
  48                 status = 0;
  49
  50         switch (usb_pipetype (urb->pipe)) {
  51         case PIPE_ISOCHRONOUS:
  52                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  53                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
  54                         if (quirk_amdiso(ohci))
  55                                 usb_amd_quirk_pll_enable();
  56                         if (quirk_amdprefetch(ohci))
  57                                 sb800_prefetch(ohci, 0);
  58                 }
  59                 break;
  60         case PIPE_INTERRUPT:
  61                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  62                 break;
  63         }
  64
  65 #ifdef OHCI_VERBOSE_DEBUG
  66         urb_print(urb, "RET", usb_pipeout (urb->pipe), status);
  67 #endif
  68
  69         /* urb->complete() can reenter this HCD */
  70         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  71         spin_unlock (&ohci->lock);
  72         usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
  73         spin_lock (&ohci->lock);
  74
  75         /* stop periodic dma if it's not needed */
  76         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  77                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  78                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  79                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  80         }
  81 }
  82
  83
  84 /*-------------------------------------------------------------------------*
  85  * ED handling functions
  86  *-------------------------------------------------------------------------*/
  87
  88 /* search for the right schedule branch to use for a periodic ed.
  89  * does some load balancing; returns the branch, or negative errno.
  90  */
  91 static int balance (struct ohci_hcd *ohci, int interval, int load)
  92 {
  93         int     i, branch = -ENOSPC;
  94
  95         /* iso periods can be huge; iso tds specify frame numbers */
  96         if (interval > NUM_INTS)
  97                 interval = NUM_INTS;
  98
  99         /* search for the least loaded schedule branch of that period
 100          * that has enough bandwidth left unreserved.
 101          */
 102         for (i = 0; i < interval ; i++) {
 103                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 104                         int     j;
 105
 106                         /* usb 1.1 says 90% of one frame */
 107                         for (j = i; j < NUM_INTS; j += interval) {
 108                                 if ((ohci->load [j] + load) > 900)
 109                                         break;
 110                         }
 111                         if (j < NUM_INTS)
 112                                 continue;
 113                         branch = i;
 114                 }
 115         }
 116         return branch;
 117 }
 118
 119 /*-------------------------------------------------------------------------*/
 120
 121 /* both iso and interrupt requests have periods; this routine puts them
 122  * into the schedule tree in the apppropriate place.  most iso devices use
 123  * 1msec periods, but that's not required.
 124  */
 125 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 126 {
 127         unsigned        i;
 128
 129         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 130                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 131                 ed, ed->branch, ed->load, ed->interval);
 132
 133         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 134                 struct ed       **prev = &ohci->periodic [i];
 135                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 136                 struct ed       *here = *prev;
 137
 138                 /* sorting each branch by period (slow before fast)
 139                  * lets us share the faster parts of the tree.
 140                  * (plus maybe: put interrupt eds before iso)
 141                  */
 142                 while (here && ed != here) {
 143                         if (ed->interval > here->interval)
 144                                 break;
 145                         prev = &here->ed_next;
 146                         prev_p = &here->hwNextED;
 147                         here = *prev;
 148                 }
 149                 if (ed != here) {
 150                         ed->ed_next = here;
 151                         if (here)
 152                                 ed->hwNextED = *prev_p;
 153                         wmb ();
 154                         *prev = ed;
 155                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 156                         wmb();
 157                 }
 158                 ohci->load [i] += ed->load;
 159         }
 160         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 161 }
 162
 163 /* link an ed into one of the HC chains */
 164
 165 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 166 {
 167         int     branch;
 168
 169         ed->state = ED_OPER;
 170         ed->ed_prev = NULL;
 171         ed->ed_next = NULL;
 172         ed->hwNextED = 0;
 173         if (quirk_zfmicro(ohci)
 174                         && (ed->type == PIPE_INTERRUPT)
 175                         && !(ohci->eds_scheduled++))
 176                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 177         wmb ();
 178
 179         /* we care about rm_list when setting CLE/BLE in case the HC was at
 180          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 181          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 182          *
 183          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 184          * periodic ones are singly linked (ed_next). that's because the
 185          * periodic schedule encodes a tree like figure 3-5 in the ohci
 186          * spec:  each qh can have several "previous" nodes, and the tree
 187          * doesn't have unused/idle descriptors.
 188          */
 189         switch (ed->type) {
 190         case PIPE_CONTROL:
 191                 if (ohci->ed_controltail == NULL) {
 192                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 193                         ohci_writel (ohci, ed->dma,
 194                                         &ohci->regs->ed_controlhead);
 195                 } else {
 196                         ohci->ed_controltail->ed_next = ed;
 197                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 198                                                                 ed->dma);
 199                 }
 200                 ed->ed_prev = ohci->ed_controltail;
 201                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 202                         wmb();
 203                         ohci->hc_control |= OHCI_CTRL_CLE;
 204                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 205                         ohci_writel (ohci, ohci->hc_control,
 206                                         &ohci->regs->control);
 207                 }
 208                 ohci->ed_controltail = ed;
 209                 break;
 210
 211         case PIPE_BULK:
 212                 if (ohci->ed_bulktail == NULL) {
 213                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 214                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 215                 } else {
 216                         ohci->ed_bulktail->ed_next = ed;
 217                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 218                                                                 ed->dma);
 219                 }
 220                 ed->ed_prev = ohci->ed_bulktail;
 221                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 222                         wmb();
 223                         ohci->hc_control |= OHCI_CTRL_BLE;
 224                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 225                         ohci_writel (ohci, ohci->hc_control,
 226                                         &ohci->regs->control);
 227                 }
 228                 ohci->ed_bulktail = ed;
 229                 break;
 230
 231         // case PIPE_INTERRUPT:
 232         // case PIPE_ISOCHRONOUS:
 233         default:
 234                 branch = balance (ohci, ed->interval, ed->load);
 235                 if (branch < 0) {
 236                         ohci_dbg (ohci,
 237                                 "ERR %d, interval %d msecs, load %d\n",
 238                                 branch, ed->interval, ed->load);
 239                         // FIXME if there are TDs queued, fail them!
 240                         return branch;
 241                 }
 242                 ed->branch = branch;
 243                 periodic_link (ohci, ed);
 244         }
 245
 246         /* the HC may not see the schedule updates yet, but if it does
 247          * then they'll be properly ordered.
 248          */
 249         return 0;
 250 }
 251
 252 /*-------------------------------------------------------------------------*/
 253
 254 /* scan the periodic table to find and unlink this ED */
 255 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 256 {
 257         int     i;
 258
 259         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 260                 struct ed       *temp;
 261                 struct ed       **prev = &ohci->periodic [i];
 262                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 263
 264                 while (*prev && (temp = *prev) != ed) {
 265                         prev_p = &temp->hwNextED;
 266                         prev = &temp->ed_next;
 267                 }
 268                 if (*prev) {
 269                         *prev_p = ed->hwNextED;
 270                         *prev = ed->ed_next;
 271                 }
 272                 ohci->load [i] -= ed->load;
 273         }
 274         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 275
 276         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 277                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 278                 ed, ed->branch, ed->load, ed->interval);
 279 }
 280
 281 /* unlink an ed from one of the HC chains.
 282  * just the link to the ed is unlinked.
 283  * the link from the ed still points to another operational ed or 0
 284  * so the HC can eventually finish the processing of the unlinked ed
 285  * (assuming it already started that, which needn't be true).
 286  *
 287  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 288  * it won't.  ED_SKIP means the HC will finish its current transaction,
 289  * but won't start anything new.  The TD queue may still grow; device
 290  * drivers don't know about this HCD-internal state.
 291  *
 292  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 293  *
 294  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 295  *    immediately.  HC should be working on them.
 296  *
 297  *  - ED_IDLE: when there's no TD queue or the HC isn't running.
 298  *
 299  * When finish_unlinks() runs later, after SOF interrupt, it will often
 300  * complete one or more URB unlinks before making that state change.
 301  */
 302 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 303 {
 304         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 305         wmb ();
 306         ed->state = ED_UNLINK;
 307
 308         /* To deschedule something from the control or bulk list, just
 309          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 310          * head/current registers until later, and "later" isn't very
 311          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 312          * the HC is reading the ED queues (while we modify them).
 313          *
 314          * For now, ed_schedule() is "later".  It might be good paranoia
 315          * to scrub those registers in finish_unlinks(), in case of bugs
 316          * that make the HC try to use them.
 317          */
 318         switch (ed->type) {
 319         case PIPE_CONTROL:
 320                 /* remove ED from the HC's list: */
 321                 if (ed->ed_prev == NULL) {
 322                         if (!ed->hwNextED) {
 323                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 324                                 ohci_writel (ohci, ohci->hc_control,
 325                                                 &ohci->regs->control);
 326                                 // a ohci_readl() later syncs CLE with the HC
 327                         } else
 328                                 ohci_writel (ohci,
 329                                         hc32_to_cpup (ohci, &ed->hwNextED),
 330                                         &ohci->regs->ed_controlhead);
 331                 } else {
 332                         ed->ed_prev->ed_next = ed->ed_next;
 333                         ed->ed_prev->hwNextED = ed->hwNextED;
 334                 }
 335                 /* remove ED from the HCD's list: */
 336                 if (ohci->ed_controltail == ed) {
 337                         ohci->ed_controltail = ed->ed_prev;
 338                         if (ohci->ed_controltail)
 339                                 ohci->ed_controltail->ed_next = NULL;
 340                 } else if (ed->ed_next) {
 341                         ed->ed_next->ed_prev = ed->ed_prev;
 342                 }
 343                 break;
 344
 345         case PIPE_BULK:
 346                 /* remove ED from the HC's list: */
 347                 if (ed->ed_prev == NULL) {
 348                         if (!ed->hwNextED) {
 349                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 350                                 ohci_writel (ohci, ohci->hc_control,
 351                                                 &ohci->regs->control);
 352                                 // a ohci_readl() later syncs BLE with the HC
 353                         } else
 354                                 ohci_writel (ohci,
 355                                         hc32_to_cpup (ohci, &ed->hwNextED),
 356                                         &ohci->regs->ed_bulkhead);
 357                 } else {
 358                         ed->ed_prev->ed_next = ed->ed_next;
 359                         ed->ed_prev->hwNextED = ed->hwNextED;
 360                 }
 361                 /* remove ED from the HCD's list: */
 362                 if (ohci->ed_bulktail == ed) {
 363                         ohci->ed_bulktail = ed->ed_prev;
 364                         if (ohci->ed_bulktail)
 365                                 ohci->ed_bulktail->ed_next = NULL;
 366                 } else if (ed->ed_next) {
 367                         ed->ed_next->ed_prev = ed->ed_prev;
 368                 }
 369                 break;
 370
 371         // case PIPE_INTERRUPT:
 372         // case PIPE_ISOCHRONOUS:
 373         default:
 374                 periodic_unlink (ohci, ed);
 375                 break;
 376         }
 377 }
 378
 379
 380 /*-------------------------------------------------------------------------*/
 381
 382 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 383  * of enumeration, usb_set_configuration() or usb_set_interface().
 384  */
 385 static struct ed *ed_get (
 386         struct ohci_hcd         *ohci,
 387         struct usb_host_endpoint *ep,
 388         struct usb_device       *udev,
 389         unsigned int            pipe,
 390         int                     interval
 391 ) {
 392         struct ed               *ed;
 393         unsigned long           flags;
 394
 395         spin_lock_irqsave (&ohci->lock, flags);
 396
 397         if (!(ed = ep->hcpriv)) {
 398                 struct td       *td;
 399                 int             is_out;
 400                 u32             info;
 401
 402                 ed = ed_alloc (ohci, GFP_ATOMIC);
 403                 if (!ed) {
 404                         /* out of memory */
 405                         goto done;
 406                 }
 407
 408                 /* dummy td; end of td list for ed */
 409                 td = td_alloc (ohci, GFP_ATOMIC);
 410                 if (!td) {
 411                         /* out of memory */
 412                         ed_free (ohci, ed);
 413                         ed = NULL;
 414                         goto done;
 415                 }
 416                 ed->dummy = td;
 417                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 418                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 419                 ed->state = ED_IDLE;
 420
 421                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 422
 423                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 424                  * succeeds ... otherwise we wouldn't need "pipe".
 425                  */
 426                 info = usb_pipedevice (pipe);
 427                 ed->type = usb_pipetype(pipe);
 428
 429                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 430                 info |= usb_endpoint_maxp(&ep->desc) << 16;
 431                 if (udev->speed == USB_SPEED_LOW)
 432                         info |= ED_LOWSPEED;
 433                 /* only control transfers store pids in tds */
 434                 if (ed->type != PIPE_CONTROL) {
 435                         info |= is_out ? ED_OUT : ED_IN;
 436                         if (ed->type != PIPE_BULK) {
 437                                 /* periodic transfers... */
 438                                 if (ed->type == PIPE_ISOCHRONOUS)
 439                                         info |= ED_ISO;
 440                                 else if (interval > 32) /* iso can be bigger */
 441                                         interval = 32;
 442                                 ed->interval = interval;
 443                                 ed->load = usb_calc_bus_time (
 444                                         udev->speed, !is_out,
 445                                         ed->type == PIPE_ISOCHRONOUS,
 446                                         usb_endpoint_maxp(&ep->desc))
 447                                                 / 1000;
 448                         }
 449                 }
 450                 ed->hwINFO = cpu_to_hc32(ohci, info);
 451
 452                 ep->hcpriv = ed;
 453         }
 454
 455 done:
 456         spin_unlock_irqrestore (&ohci->lock, flags);
 457         return ed;
 458 }
 459
 460 /*-------------------------------------------------------------------------*/
 461
 462 /* request unlinking of an endpoint from an operational HC.
 463  * put the ep on the rm_list
 464  * real work is done at the next start frame (SF) hardware interrupt
 465  * caller guarantees HCD is running, so hardware access is safe,
 466  * and that ed->state is ED_OPER
 467  */
 468 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 469 {
 470         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 471         ed_deschedule (ohci, ed);
 472
 473         /* rm_list is just singly linked, for simplicity */
 474         ed->ed_next = ohci->ed_rm_list;
 475         ed->ed_prev = NULL;
 476         ohci->ed_rm_list = ed;
 477
 478         /* enable SOF interrupt */
 479         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 480         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 481         // flush those writes, and get latest HCCA contents
 482         (void) ohci_readl (ohci, &ohci->regs->control);
 483
 484         /* SF interrupt might get delayed; record the frame counter value that
 485          * indicates when the HC isn't looking at it, so concurrent unlinks
 486          * behave.  frame_no wraps every 2^16 msec, and changes right before
 487          * SF is triggered.
 488          */
 489         ed->tick = ohci_frame_no(ohci) + 1;
 490
 491 }
 492
 493 /*-------------------------------------------------------------------------*
 494  * TD handling functions
 495  *-------------------------------------------------------------------------*/
 496
 497 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 498
 499 static void
 500 td_fill (struct ohci_hcd *ohci, u32 info,
 501         dma_addr_t data, int len,
 502         struct urb *urb, int index)
 503 {
 504         struct td               *td, *td_pt;
 505         struct urb_priv         *urb_priv = urb->hcpriv;
 506         int                     is_iso = info & TD_ISO;
 507         int                     hash;
 508
 509         // ASSERT (index < urb_priv->length);
 510
 511         /* aim for only one interrupt per urb.  mostly applies to control
 512          * and iso; other urbs rarely need more than one TD per urb.
 513          * this way, only final tds (or ones with an error) cause IRQs.
 514          * at least immediately; use DI=6 in case any control request is
 515          * tempted to die part way through.  (and to force the hc to flush
 516          * its donelist soonish, even on unlink paths.)
 517          *
 518          * NOTE: could delay interrupts even for the last TD, and get fewer
 519          * interrupts ... increasing per-urb latency by sharing interrupts.
 520          * Drivers that queue bulk urbs may request that behavior.
 521          */
 522         if (index != (urb_priv->length - 1)
 523                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 524                 info |= TD_DI_SET (6);
 525
 526         /* use this td as the next dummy */
 527         td_pt = urb_priv->td [index];
 528
 529         /* fill the old dummy TD */
 530         td = urb_priv->td [index] = urb_priv->ed->dummy;
 531         urb_priv->ed->dummy = td_pt;
 532
 533         td->ed = urb_priv->ed;
 534         td->next_dl_td = NULL;
 535         td->index = index;
 536         td->urb = urb;
 537         td->data_dma = data;
 538         if (!len)
 539                 data = 0;
 540
 541         td->hwINFO = cpu_to_hc32 (ohci, info);
 542         if (is_iso) {
 543                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 544                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 545                                                 (data & 0x0FFF) | 0xE000);
 546                 td->ed->last_iso = info & 0xffff;
 547         } else {
 548                 td->hwCBP = cpu_to_hc32 (ohci, data);
 549         }
 550         if (data)
 551                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 552         else
 553                 td->hwBE = 0;
 554         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 555
 556         /* append to queue */
 557         list_add_tail (&td->td_list, &td->ed->td_list);
 558
 559         /* hash it for later reverse mapping */
 560         hash = TD_HASH_FUNC (td->td_dma);
 561         td->td_hash = ohci->td_hash [hash];
 562         ohci->td_hash [hash] = td;
 563
 564         /* HC might read the TD (or cachelines) right away ... */
 565         wmb ();
 566         td->ed->hwTailP = td->hwNextTD;
 567 }
 568
 569 /*-------------------------------------------------------------------------*/
 570
 571 /* Prepare all TDs of a transfer, and queue them onto the ED.
 572  * Caller guarantees HC is active.
 573  * Usually the ED is already on the schedule, so TDs might be
 574  * processed as soon as they're queued.
 575  */
 576 static void td_submit_urb (
 577         struct ohci_hcd *ohci,
 578         struct urb      *urb
 579 ) {
 580         struct urb_priv *urb_priv = urb->hcpriv;
 581         dma_addr_t      data;
 582         int             data_len = urb->transfer_buffer_length;
 583         int             cnt = 0;
 584         u32             info = 0;
 585         int             is_out = usb_pipeout (urb->pipe);
 586         int             periodic = 0;
 587
 588         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 589          * use the device toggle bits for resetting, and rely on the fact
 590          * that resetting toggle is meaningless if the endpoint is active.
 591          */
 592         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 593                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 594                         is_out, 1);
 595                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 596         }
 597
 598         urb_priv->td_cnt = 0;
 599         list_add (&urb_priv->pending, &ohci->pending);
 600
 601         if (data_len)
 602                 data = urb->transfer_dma;
 603         else
 604                 data = 0;
 605
 606         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 607          * using TD_CC_GET, as well as by seeing them on the done list.
 608          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 609          */
 610         switch (urb_priv->ed->type) {
 611
 612         /* Bulk and interrupt are identical except for where in the schedule
 613          * their EDs live.
 614          */
 615         case PIPE_INTERRUPT:
 616                 /* ... and periodic urbs have extra accounting */
 617                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 618                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 619                 /* FALLTHROUGH */
 620         case PIPE_BULK:
 621                 info = is_out
 622                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 623                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 624                 /* TDs _could_ transfer up to 8K each */
 625                 while (data_len > 4096) {
 626                         td_fill (ohci, info, data, 4096, urb, cnt);
 627                         data += 4096;
 628                         data_len -= 4096;
 629                         cnt++;
 630                 }
 631                 /* maybe avoid ED halt on final TD short read */
 632                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 633                         info |= TD_R;
 634                 td_fill (ohci, info, data, data_len, urb, cnt);
 635                 cnt++;
 636                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 637                                 && cnt < urb_priv->length) {
 638                         td_fill (ohci, info, 0, 0, urb, cnt);
 639                         cnt++;
 640                 }
 641                 /* maybe kickstart bulk list */
 642                 if (urb_priv->ed->type == PIPE_BULK) {
 643                         wmb ();
 644                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 645                 }
 646                 break;
 647
 648         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 649          * any DATA phase works normally, and the STATUS ack is special.
 650          */
 651         case PIPE_CONTROL:
 652                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 653                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 654                 if (data_len > 0) {
 655                         info = TD_CC | TD_R | TD_T_DATA1;
 656                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 657                         /* NOTE:  mishandles transfers >8K, some >4K */
 658                         td_fill (ohci, info, data, data_len, urb, cnt++);
 659                 }
 660                 info = (is_out || data_len == 0)
 661                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 662                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 663                 td_fill (ohci, info, data, 0, urb, cnt++);
 664                 /* maybe kickstart control list */
 665                 wmb ();
 666                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 667                 break;
 668
 669         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 670          * Each TD could handle multiple consecutive frames (interval 1);
 671          * we could often reduce the number of TDs here.
 672          */
 673         case PIPE_ISOCHRONOUS:
 674                 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
 675                         int     frame = urb->start_frame;
 676
 677                         // FIXME scheduling should handle frame counter
 678                         // roll-around ... exotic case (and OHCI has
 679                         // a 2^16 iso range, vs other HCs max of 2^10)
 680                         frame += cnt * urb->interval;
 681                         frame &= 0xffff;
 682                         td_fill (ohci, TD_CC | TD_ISO | frame,
 683                                 data + urb->iso_frame_desc [cnt].offset,
 684                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 685                 }
 686                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
 687                         if (quirk_amdiso(ohci))
 688                                 usb_amd_quirk_pll_disable();
 689                         if (quirk_amdprefetch(ohci))
 690                                 sb800_prefetch(ohci, 1);
 691                 }
 692                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 693                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 694                 break;
 695         }
 696
 697         /* start periodic dma if needed */
 698         if (periodic) {
 699                 wmb ();
 700                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 701                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 702         }
 703
 704         // ASSERT (urb_priv->length == cnt);
 705 }
 706
 707 /*-------------------------------------------------------------------------*
 708  * Done List handling functions
 709  *-------------------------------------------------------------------------*/
 710
 711 /* calculate transfer length/status and update the urb */
 712 static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 713 {
 714         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 715         int     cc = 0;
 716         int     status = -EINPROGRESS;
 717
 718         list_del (&td->td_list);
 719
 720         /* ISO ... drivers see per-TD length/status */
 721         if (tdINFO & TD_ISO) {
 722                 u16     tdPSW = ohci_hwPSW(ohci, td, 0);
 723                 int     dlen = 0;
 724
 725                 /* NOTE:  assumes FC in tdINFO == 0, and that
 726                  * only the first of 0..MAXPSW psws is used.
 727                  */
 728
 729                 cc = (tdPSW >> 12) & 0xF;
 730                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 731                         return status;
 732
 733                 if (usb_pipeout (urb->pipe))
 734                         dlen = urb->iso_frame_desc [td->index].length;
 735                 else {
 736                         /* short reads are always OK for ISO */
 737                         if (cc == TD_DATAUNDERRUN)
 738                                 cc = TD_CC_NOERROR;
 739                         dlen = tdPSW & 0x3ff;
 740                 }
 741                 urb->actual_length += dlen;
 742                 urb->iso_frame_desc [td->index].actual_length = dlen;
 743                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 744
 745                 if (cc != TD_CC_NOERROR)
 746                         ohci_vdbg (ohci,
 747                                 "urb %p iso td %p (%d) len %d cc %d\n",
 748                                 urb, td, 1 + td->index, dlen, cc);
 749
 750         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 751          * except that "setup" bytes aren't counted and "short" transfers
 752          * might not be reported as errors.
 753          */
 754         } else {
 755                 int     type = usb_pipetype (urb->pipe);
 756                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 757
 758                 cc = TD_CC_GET (tdINFO);
 759
 760                 /* update packet status if needed (short is normally ok) */
 761                 if (cc == TD_DATAUNDERRUN
 762                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 763                         cc = TD_CC_NOERROR;
 764                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 765                         status = cc_to_error[cc];
 766
 767                 /* count all non-empty packets except control SETUP packet */
 768                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 769                         if (td->hwCBP == 0)
 770                                 urb->actual_length += tdBE - td->data_dma + 1;
 771                         else
 772                                 urb->actual_length +=
 773                                           hc32_to_cpup (ohci, &td->hwCBP)
 774                                         - td->data_dma;
 775                 }
 776
 777                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 778                         ohci_vdbg (ohci,
 779                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 780                                 urb, td, 1 + td->index, cc,
 781                                 urb->actual_length,
 782                                 urb->transfer_buffer_length);
 783         }
 784         return status;
 785 }
 786
 787 /*-------------------------------------------------------------------------*/
 788
 789 static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
 790 {
 791         struct urb              *urb = td->urb;
 792         urb_priv_t              *urb_priv = urb->hcpriv;
 793         struct ed               *ed = td->ed;
 794         struct list_head        *tmp = td->td_list.next;
 795         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 796
 797         /* clear ed halt; this is the td that caused it, but keep it inactive
 798          * until its urb->complete() has a chance to clean up.
 799          */
 800         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 801         wmb ();
 802         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 803
 804         /* Get rid of all later tds from this urb.  We don't have
 805          * to be careful: no errors and nothing was transferred.
 806          * Also patch the ed so it looks as if those tds completed normally.
 807          */
 808         while (tmp != &ed->td_list) {
 809                 struct td       *next;
 810
 811                 next = list_entry (tmp, struct td, td_list);
 812                 tmp = next->td_list.next;
 813
 814                 if (next->urb != urb)
 815                         break;
 816
 817                 /* NOTE: if multi-td control DATA segments get supported,
 818                  * this urb had one of them, this td wasn't the last td
 819                  * in that segment (TD_R clear), this ed halted because
 820                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 821                  * then we need to leave the control STATUS packet queued
 822                  * and clear ED_SKIP.
 823                  */
 824
 825                 list_del(&next->td_list);
 826                 urb_priv->td_cnt++;
 827                 ed->hwHeadP = next->hwNextTD | toggle;
 828         }
 829
 830         /* help for troubleshooting:  report anything that
 831          * looks odd ... that doesn't include protocol stalls
 832          * (or maybe some other things)
 833          */
 834         switch (cc) {
 835         case TD_DATAUNDERRUN:
 836                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 837                         break;
 838                 /* fallthrough */
 839         case TD_CC_STALL:
 840                 if (usb_pipecontrol (urb->pipe))
 841                         break;
 842                 /* fallthrough */
 843         default:
 844                 ohci_dbg (ohci,
 845                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 846                         urb, urb->dev->devpath,
 847                         usb_pipeendpoint (urb->pipe),
 848                         usb_pipein (urb->pipe) ? "in" : "out",
 849                         hc32_to_cpu (ohci, td->hwINFO),
 850                         cc, cc_to_error [cc]);
 851         }
 852 }
 853
 854 /* replies to the request have to be on a FIFO basis so
 855  * we unreverse the hc-reversed done-list
 856  */
 857 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 858 {
 859         u32             td_dma;
 860         struct td       *td_rev = NULL;
 861         struct td       *td = NULL;
 862
 863         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 864         ohci->hcca->done_head = 0;
 865         wmb();
 866
 867         /* get TD from hc's singly linked list, and
 868          * prepend to ours.  ed->td_list changes later.
 869          */
 870         while (td_dma) {
 871                 int             cc;
 872
 873                 td = dma_to_td (ohci, td_dma);
 874                 if (!td) {
 875                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 876                         break;
 877                 }
 878
 879                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 880                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 881
 882                 /* Non-iso endpoints can halt on error; un-halt,
 883                  * and dequeue any other TDs from this urb.
 884                  * No other TD could have caused the halt.
 885                  */
 886                 if (cc != TD_CC_NOERROR
 887                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 888                         ed_halted(ohci, td, cc);
 889
 890                 td->next_dl_td = td_rev;
 891                 td_rev = td;
 892                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 893         }
 894         return td_rev;
 895 }
 896
 897 /*-------------------------------------------------------------------------*/
 898
 899 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 900 static void
 901 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 902 {
 903         struct ed       *ed, **last;
 904
 905 rescan_all:
 906         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 907                 struct list_head        *entry, *tmp;
 908                 int                     completed, modified;
 909                 __hc32                  *prev;
 910
 911                 /* Is this ED already invisible to the hardware? */
 912                 if (ed->state == ED_IDLE)
 913                         goto ed_idle;
 914
 915                 /* only take off EDs that the HC isn't using, accounting for
 916                  * frame counter wraps and EDs with partially retired TDs
 917                  */
 918                 if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) {
 919                         if (tick_before (tick, ed->tick)) {
 920 skip_ed:
 921                                 last = &ed->ed_next;
 922                                 continue;
 923                         }
 924
 925                         if (!list_empty (&ed->td_list)) {
 926                                 struct td       *td;
 927                                 u32             head;
 928
 929                                 td = list_entry (ed->td_list.next, struct td,
 930                                                         td_list);
 931                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 932                                                                 TD_MASK;
 933
 934                                 /* INTR_WDH may need to clean up first */
 935                                 if (td->td_dma != head) {
 936                                         if (ed == ohci->ed_to_check)
 937                                                 ohci->ed_to_check = NULL;
 938                                         else
 939                                                 goto skip_ed;
 940                                 }
 941                         }
 942                 }
 943
 944                 /* ED's now officially unlinked, hc doesn't see */
 945                 ed->state = ED_IDLE;
 946                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
 947                         ohci->eds_scheduled--;
 948                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
 949                 ed->hwNextED = 0;
 950                 wmb();
 951                 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE);
 952 ed_idle:
 953
 954                 /* reentrancy:  if we drop the schedule lock, someone might
 955                  * have modified this list.  normally it's just prepending
 956                  * entries (which we'd ignore), but paranoia won't hurt.
 957                  */
 958                 modified = 0;
 959
 960                 /* unlink urbs as requested, but rescan the list after
 961                  * we call a completion since it might have unlinked
 962                  * another (earlier) urb
 963                  *
 964                  * When we get here, the HC doesn't see this ed.  But it
 965                  * must not be rescheduled until all completed URBs have
 966                  * been given back to the driver.
 967                  */
 968 rescan_this:
 969                 completed = 0;
 970                 prev = &ed->hwHeadP;
 971                 list_for_each_safe (entry, tmp, &ed->td_list) {
 972                         struct td       *td;
 973                         struct urb      *urb;
 974                         urb_priv_t      *urb_priv;
 975                         __hc32          savebits;
 976                         u32             tdINFO;
 977
 978                         td = list_entry (entry, struct td, td_list);
 979                         urb = td->urb;
 980                         urb_priv = td->urb->hcpriv;
 981
 982                         if (!urb->unlinked) {
 983                                 prev = &td->hwNextTD;
 984                                 continue;
 985                         }
 986
 987                         /* patch pointer hc uses */
 988                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 989                         *prev = td->hwNextTD | savebits;
 990
 991                         /* If this was unlinked, the TD may not have been
 992                          * retired ... so manually save the data toggle.
 993                          * The controller ignores the value we save for
 994                          * control and ISO endpoints.
 995                          */
 996                         tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
 997                         if ((tdINFO & TD_T) == TD_T_DATA0)
 998                                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
 999                         else if ((tdINFO & TD_T) == TD_T_DATA1)
1000                                 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
1001
1002                         /* HC may have partly processed this TD */
1003                         td_done (ohci, urb, td);
1004                         urb_priv->td_cnt++;
1005
1006                         /* if URB is done, clean up */
1007                         if (urb_priv->td_cnt == urb_priv->length) {
1008                                 modified = completed = 1;
1009                                 finish_urb(ohci, urb, 0);
1010                         }
1011                 }
1012                 if (completed && !list_empty (&ed->td_list))
1013                         goto rescan_this;
1014
1015                 /*
1016                  * If no TDs are queued, take ED off the ed_rm_list.
1017                  * Otherwise, if the HC is running, reschedule.
1018                  * If not, leave it on the list for further dequeues.
1019                  */
1020                 if (list_empty(&ed->td_list)) {
1021                         *last = ed->ed_next;
1022                         ed->ed_next = NULL;
1023                 } else if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)) {
1024                         *last = ed->ed_next;
1025                         ed->ed_next = NULL;
1026                         ed_schedule(ohci, ed);
1027                 } else {
1028                         last = &ed->ed_next;
1029                 }
1030
1031                 if (modified)
1032                         goto rescan_all;
1033         }
1034
1035         /* maybe reenable control and bulk lists */
1036         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)
1037                         && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING
1038                         && !ohci->ed_rm_list) {
1039                 u32     command = 0, control = 0;
1040
1041                 if (ohci->ed_controltail) {
1042                         command |= OHCI_CLF;
1043                         if (quirk_zfmicro(ohci))
1044                                 mdelay(1);
1045                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1046                                 control |= OHCI_CTRL_CLE;
1047                                 ohci_writel (ohci, 0,
1048                                         &ohci->regs->ed_controlcurrent);
1049                         }
1050                 }
1051                 if (ohci->ed_bulktail) {
1052                         command |= OHCI_BLF;
1053                         if (quirk_zfmicro(ohci))
1054                                 mdelay(1);
1055                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1056                                 control |= OHCI_CTRL_BLE;
1057                                 ohci_writel (ohci, 0,
1058                                         &ohci->regs->ed_bulkcurrent);
1059                         }
1060                 }
1061
1062                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1063                 if (control) {
1064                         ohci->hc_control |= control;
1065                         if (quirk_zfmicro(ohci))
1066                                 mdelay(1);
1067                         ohci_writel (ohci, ohci->hc_control,
1068                                         &ohci->regs->control);
1069                 }
1070                 if (command) {
1071                         if (quirk_zfmicro(ohci))
1072                                 mdelay(1);
1073                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1074                 }
1075         }
1076 }
1077
1078
1079
1080 /*-------------------------------------------------------------------------*/
1081
1082 /*
1083  * Used to take back a TD from the host controller. This would normally be
1084  * called from within dl_done_list, however it may be called directly if the
1085  * HC no longer sees the TD and it has not appeared on the donelist (after
1086  * two frames).  This bug has been observed on ZF Micro systems.
1087  */
1088 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1089 {
1090         struct urb      *urb = td->urb;
1091         urb_priv_t      *urb_priv = urb->hcpriv;
1092         struct ed       *ed = td->ed;
1093         int             status;
1094
1095         /* update URB's length and status from TD */
1096         status = td_done(ohci, urb, td);
1097         urb_priv->td_cnt++;
1098
1099         /* If all this urb's TDs are done, call complete() */
1100         if (urb_priv->td_cnt == urb_priv->length)
1101                 finish_urb(ohci, urb, status);
1102
1103         /* clean schedule:  unlink EDs that are no longer busy */
1104         if (list_empty(&ed->td_list)) {
1105                 if (ed->state == ED_OPER)
1106                         start_ed_unlink(ohci, ed);
1107
1108         /* ... reenabling halted EDs only after fault cleanup */
1109         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1110                         == cpu_to_hc32(ohci, ED_SKIP)) {
1111                 td = list_entry(ed->td_list.next, struct td, td_list);
1112                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1113                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1114                         /* ... hc may need waking-up */
1115                         switch (ed->type) {
1116                         case PIPE_CONTROL:
1117                                 ohci_writel(ohci, OHCI_CLF,
1118                                                 &ohci->regs->cmdstatus);
1119                                 break;
1120                         case PIPE_BULK:
1121                                 ohci_writel(ohci, OHCI_BLF,
1122                                                 &ohci->regs->cmdstatus);
1123                                 break;
1124                         }
1125                 }
1126         }
1127 }
1128
1129 /*
1130  * Process normal completions (error or success) and clean the schedules.
1131  *
1132  * This is the main path for handing urbs back to drivers.  The only other
1133  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1134  * instead of scanning the (re-reversed) donelist as this does.  There's
1135  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1136  * with TDs that appear to be orphaned are directly reclaimed.
1137  */
1138 static void
1139 dl_done_list (struct ohci_hcd *ohci)
1140 {
1141         struct td       *td = dl_reverse_done_list (ohci);
1142
1143         while (td) {
1144                 struct td       *td_next = td->next_dl_td;
1145                 struct ed       *ed = td->ed;
1146
1147                 /*
1148                  * Some OHCI controllers (NVIDIA for sure, maybe others)
1149                  * occasionally forget to add TDs to the done queue.  Since
1150                  * TDs for a given endpoint are always processed in order,
1151                  * if we find a TD on the donelist then all of its
1152                  * predecessors must be finished as well.
1153                  */
1154                 for (;;) {
1155                         struct td       *td2;
1156
1157                         td2 = list_first_entry(&ed->td_list, struct td,
1158                                         td_list);
1159                         if (td2 == td)
1160                                 break;
1161                         takeback_td(ohci, td2);
1162                 }
1163
1164                 takeback_td(ohci, td);
1165                 td = td_next;
1166         }
1167 }