drivers/usb/host/ohci-hcd.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * [ Initialisation is based on Linus'  ]
   8  * [ uhci code and gregs ohci fragments ]
   9  * [ (C) Copyright 1999 Linus Torvalds  ]
  10  * [ (C) Copyright 1999 Gregory P. Smith]
  11  *
  12  *
  13  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  14  * interfaces (though some non-x86 Intel chips use it).  It supports
  15  * smarter hardware than UHCI.  A download link for the spec available
  16  * through the http://www.usb.org website.
  17  *
  18  * This file is licenced under the GPL.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/pci.h>
  24 #include <linux/kernel.h>
  25 #include <linux/delay.h>
  26 #include <linux/ioport.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/errno.h>
  31 #include <linux/init.h>
  32 #include <linux/timer.h>
  33 #include <linux/list.h>
  34 #include <linux/usb.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/dmapool.h>
  38 #include <linux/reboot.h>
  39
  40 #include <asm/io.h>
  41 #include <asm/irq.h>
  42 #include <asm/system.h>
  43 #include <asm/unaligned.h>
  44 #include <asm/byteorder.h>
  45
  46 #include "../core/hcd.h"
  47
  48 #define DRIVER_VERSION "2006 August 04"
  49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  51
  52 /*-------------------------------------------------------------------------*/
  53
  54 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
  55
  56 /* For initializing controller (mask in an HCFS mode too) */
  57 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  58 #define OHCI_INTR_INIT \
  59                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  60                 | OHCI_INTR_RD | OHCI_INTR_WDH)
  61
  62 #ifdef __hppa__
  63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  64 #define IR_DISABLE
  65 #endif
  66
  67 #ifdef CONFIG_ARCH_OMAP
  68 /* OMAP doesn't support IR (no SMM; not needed) */
  69 #define IR_DISABLE
  70 #endif
  71
  72 /*-------------------------------------------------------------------------*/
  73
  74 static const char       hcd_name [] = "ohci_hcd";
  75
  76 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  77
  78 #include "ohci.h"
  79
  80 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
  81 static int ohci_init (struct ohci_hcd *ohci);
  82 static void ohci_stop (struct usb_hcd *hcd);
  83
  84 #include "ohci-hub.c"
  85 #include "ohci-dbg.c"
  86 #include "ohci-mem.c"
  87 #include "ohci-q.c"
  88
  89
  90 /*
  91  * On architectures with edge-triggered interrupts we must never return
  92  * IRQ_NONE.
  93  */
  94 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
  95 #define IRQ_NOTMINE     IRQ_HANDLED
  96 #else
  97 #define IRQ_NOTMINE     IRQ_NONE
  98 #endif
  99
 100
 101 /* Some boards misreport power switching/overcurrent */
 102 static int distrust_firmware = 1;
 103 module_param (distrust_firmware, bool, 0);
 104 MODULE_PARM_DESC (distrust_firmware,
 105         "true to distrust firmware power/overcurrent setup");
 106
 107 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
 108 static int no_handshake = 0;
 109 module_param (no_handshake, bool, 0);
 110 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
 111
 112 /*-------------------------------------------------------------------------*/
 113
 114 /*
 115  * queue up an urb for anything except the root hub
 116  */
 117 static int ohci_urb_enqueue (
 118         struct usb_hcd  *hcd,
 119         struct usb_host_endpoint *ep,
 120         struct urb      *urb,
 121         gfp_t           mem_flags
 122 ) {
 123         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 124         struct ed       *ed;
 125         urb_priv_t      *urb_priv;
 126         unsigned int    pipe = urb->pipe;
 127         int             i, size = 0;
 128         unsigned long   flags;
 129         int             retval = 0;
 130
 131 #ifdef OHCI_VERBOSE_DEBUG
 132         urb_print (urb, "SUB", usb_pipein (pipe));
 133 #endif
 134
 135         /* every endpoint has a ed, locate and maybe (re)initialize it */
 136         if (! (ed = ed_get (ohci, ep, urb->dev, pipe, urb->interval)))
 137                 return -ENOMEM;
 138
 139         /* for the private part of the URB we need the number of TDs (size) */
 140         switch (ed->type) {
 141                 case PIPE_CONTROL:
 142                         /* td_submit_urb() doesn't yet handle these */
 143                         if (urb->transfer_buffer_length > 4096)
 144                                 return -EMSGSIZE;
 145
 146                         /* 1 TD for setup, 1 for ACK, plus ... */
 147                         size = 2;
 148                         /* FALLTHROUGH */
 149                 // case PIPE_INTERRUPT:
 150                 // case PIPE_BULK:
 151                 default:
 152                         /* one TD for every 4096 Bytes (can be upto 8K) */
 153                         size += urb->transfer_buffer_length / 4096;
 154                         /* ... and for any remaining bytes ... */
 155                         if ((urb->transfer_buffer_length % 4096) != 0)
 156                                 size++;
 157                         /* ... and maybe a zero length packet to wrap it up */
 158                         if (size == 0)
 159                                 size++;
 160                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 161                                 && (urb->transfer_buffer_length
 162                                         % usb_maxpacket (urb->dev, pipe,
 163                                                 usb_pipeout (pipe))) == 0)
 164                                 size++;
 165                         break;
 166                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
 167                         size = urb->number_of_packets;
 168                         break;
 169         }
 170
 171         /* allocate the private part of the URB */
 172         urb_priv = kmalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
 173                         mem_flags);
 174         if (!urb_priv)
 175                 return -ENOMEM;
 176         memset (urb_priv, 0, sizeof (urb_priv_t) + size * sizeof (struct td *));
 177         INIT_LIST_HEAD (&urb_priv->pending);
 178         urb_priv->length = size;
 179         urb_priv->ed = ed;
 180
 181         /* allocate the TDs (deferring hash chain updates) */
 182         for (i = 0; i < size; i++) {
 183                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
 184                 if (!urb_priv->td [i]) {
 185                         urb_priv->length = i;
 186                         urb_free_priv (ohci, urb_priv);
 187                         return -ENOMEM;
 188                 }
 189         }
 190
 191         spin_lock_irqsave (&ohci->lock, flags);
 192
 193         /* don't submit to a dead HC */
 194         if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
 195                 retval = -ENODEV;
 196                 goto fail;
 197         }
 198         if (!HC_IS_RUNNING(hcd->state)) {
 199                 retval = -ENODEV;
 200                 goto fail;
 201         }
 202
 203         /* in case of unlink-during-submit */
 204         spin_lock (&urb->lock);
 205         if (urb->status != -EINPROGRESS) {
 206                 spin_unlock (&urb->lock);
 207                 urb->hcpriv = urb_priv;
 208                 finish_urb (ohci, urb);
 209                 retval = 0;
 210                 goto fail;
 211         }
 212
 213         /* schedule the ed if needed */
 214         if (ed->state == ED_IDLE) {
 215                 retval = ed_schedule (ohci, ed);
 216                 if (retval < 0)
 217                         goto fail0;
 218                 if (ed->type == PIPE_ISOCHRONOUS) {
 219                         u16     frame = ohci_frame_no(ohci);
 220
 221                         /* delay a few frames before the first TD */
 222                         frame += max_t (u16, 8, ed->interval);
 223                         frame &= ~(ed->interval - 1);
 224                         frame |= ed->branch;
 225                         urb->start_frame = frame;
 226
 227                         /* yes, only URB_ISO_ASAP is supported, and
 228                          * urb->start_frame is never used as input.
 229                          */
 230                 }
 231         } else if (ed->type == PIPE_ISOCHRONOUS)
 232                 urb->start_frame = ed->last_iso + ed->interval;
 233
 234         /* fill the TDs and link them to the ed; and
 235          * enable that part of the schedule, if needed
 236          * and update count of queued periodic urbs
 237          */
 238         urb->hcpriv = urb_priv;
 239         td_submit_urb (ohci, urb);
 240
 241 fail0:
 242         spin_unlock (&urb->lock);
 243 fail:
 244         if (retval)
 245                 urb_free_priv (ohci, urb_priv);
 246         spin_unlock_irqrestore (&ohci->lock, flags);
 247         return retval;
 248 }
 249
 250 /*
 251  * decouple the URB from the HC queues (TDs, urb_priv); it's
 252  * already marked using urb->status.  reporting is always done
 253  * asynchronously, and we might be dealing with an urb that's
 254  * partially transferred, or an ED with other urbs being unlinked.
 255  */
 256 static int ohci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
 257 {
 258         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 259         unsigned long           flags;
 260
 261 #ifdef OHCI_VERBOSE_DEBUG
 262         urb_print (urb, "UNLINK", 1);
 263 #endif
 264
 265         spin_lock_irqsave (&ohci->lock, flags);
 266         if (HC_IS_RUNNING(hcd->state)) {
 267                 urb_priv_t  *urb_priv;
 268
 269                 /* Unless an IRQ completed the unlink while it was being
 270                  * handed to us, flag it for unlink and giveback, and force
 271                  * some upcoming INTR_SF to call finish_unlinks()
 272                  */
 273                 urb_priv = urb->hcpriv;
 274                 if (urb_priv) {
 275                         if (urb_priv->ed->state == ED_OPER)
 276                                 start_ed_unlink (ohci, urb_priv->ed);
 277                 }
 278         } else {
 279                 /*
 280                  * with HC dead, we won't respect hc queue pointers
 281                  * any more ... just clean up every urb's memory.
 282                  */
 283                 if (urb->hcpriv)
 284                         finish_urb (ohci, urb);
 285         }
 286         spin_unlock_irqrestore (&ohci->lock, flags);
 287         return 0;
 288 }
 289
 290 /*-------------------------------------------------------------------------*/
 291
 292 /* frees config/altsetting state for endpoints,
 293  * including ED memory, dummy TD, and bulk/intr data toggle
 294  */
 295
 296 static void
 297 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 298 {
 299         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 300         unsigned long           flags;
 301         struct ed               *ed = ep->hcpriv;
 302         unsigned                limit = 1000;
 303
 304         /* ASSERT:  any requests/urbs are being unlinked */
 305         /* ASSERT:  nobody can be submitting urbs for this any more */
 306
 307         if (!ed)
 308                 return;
 309
 310 rescan:
 311         spin_lock_irqsave (&ohci->lock, flags);
 312
 313         if (!HC_IS_RUNNING (hcd->state)) {
 314 sanitize:
 315                 ed->state = ED_IDLE;
 316                 finish_unlinks (ohci, 0);
 317         }
 318
 319         switch (ed->state) {
 320         case ED_UNLINK:         /* wait for hw to finish? */
 321                 /* major IRQ delivery trouble loses INTR_SF too... */
 322                 if (limit-- == 0) {
 323                         ohci_warn (ohci, "IRQ INTR_SF lossage\n");
 324                         goto sanitize;
 325                 }
 326                 spin_unlock_irqrestore (&ohci->lock, flags);
 327                 schedule_timeout_uninterruptible(1);
 328                 goto rescan;
 329         case ED_IDLE:           /* fully unlinked */
 330                 if (list_empty (&ed->td_list)) {
 331                         td_free (ohci, ed->dummy);
 332                         ed_free (ohci, ed);
 333                         break;
 334                 }
 335                 /* else FALL THROUGH */
 336         default:
 337                 /* caller was supposed to have unlinked any requests;
 338                  * that's not our job.  can't recover; must leak ed.
 339                  */
 340                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
 341                         ed, ep->desc.bEndpointAddress, ed->state,
 342                         list_empty (&ed->td_list) ? "" : " (has tds)");
 343                 td_free (ohci, ed->dummy);
 344                 break;
 345         }
 346         ep->hcpriv = NULL;
 347         spin_unlock_irqrestore (&ohci->lock, flags);
 348         return;
 349 }
 350
 351 static int ohci_get_frame (struct usb_hcd *hcd)
 352 {
 353         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 354
 355         return ohci_frame_no(ohci);
 356 }
 357
 358 static void ohci_usb_reset (struct ohci_hcd *ohci)
 359 {
 360         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
 361         ohci->hc_control &= OHCI_CTRL_RWC;
 362         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 363 }
 364
 365 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
 366  * other cases where the next software may expect clean state from the
 367  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 368  */
 369 static void
 370 ohci_shutdown (struct usb_hcd *hcd)
 371 {
 372         struct ohci_hcd *ohci;
 373
 374         ohci = hcd_to_ohci (hcd);
 375         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 376         ohci_usb_reset (ohci);
 377         /* flush the writes */
 378         (void) ohci_readl (ohci, &ohci->regs->control);
 379 }
 380
 381 /*-------------------------------------------------------------------------*
 382  * HC functions
 383  *-------------------------------------------------------------------------*/
 384
 385 /* init memory, and kick BIOS/SMM off */
 386
 387 static int ohci_init (struct ohci_hcd *ohci)
 388 {
 389         int ret;
 390         struct usb_hcd *hcd = ohci_to_hcd(ohci);
 391
 392         disable (ohci);
 393         ohci->regs = hcd->regs;
 394
 395         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
 396          * was never needed for most non-PCI systems ... remove the code?
 397          */
 398
 399 #ifndef IR_DISABLE
 400         /* SMM owns the HC?  not for long! */
 401         if (!no_handshake && ohci_readl (ohci,
 402                                         &ohci->regs->control) & OHCI_CTRL_IR) {
 403                 u32 temp;
 404
 405                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
 406
 407                 /* this timeout is arbitrary.  we make it long, so systems
 408                  * depending on usb keyboards may be usable even if the
 409                  * BIOS/SMM code seems pretty broken.
 410                  */
 411                 temp = 500;     /* arbitrary: five seconds */
 412
 413                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
 414                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
 415                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
 416                         msleep (10);
 417                         if (--temp == 0) {
 418                                 ohci_err (ohci, "USB HC takeover failed!"
 419                                         "  (BIOS/SMM bug)\n");
 420                                 return -EBUSY;
 421                         }
 422                 }
 423                 ohci_usb_reset (ohci);
 424         }
 425 #endif
 426
 427         /* Disable HC interrupts */
 428         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 429
 430         /* flush the writes, and save key bits like RWC */
 431         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
 432                 ohci->hc_control |= OHCI_CTRL_RWC;
 433
 434         /* Read the number of ports unless overridden */
 435         if (ohci->num_ports == 0)
 436                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
 437
 438         if (ohci->hcca)
 439                 return 0;
 440
 441         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
 442                         sizeof *ohci->hcca, &ohci->hcca_dma, 0);
 443         if (!ohci->hcca)
 444                 return -ENOMEM;
 445
 446         if ((ret = ohci_mem_init (ohci)) < 0)
 447                 ohci_stop (hcd);
 448         else {
 449                 create_debug_files (ohci);
 450         }
 451
 452         return ret;
 453 }
 454
 455 /*-------------------------------------------------------------------------*/
 456
 457 /* Start an OHCI controller, set the BUS operational
 458  * resets USB and controller
 459  * enable interrupts
 460  */
 461 static int ohci_run (struct ohci_hcd *ohci)
 462 {
 463         u32                     mask, temp;
 464         int                     first = ohci->fminterval == 0;
 465         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 466
 467         disable (ohci);
 468
 469         /* boot firmware should have set this up (5.1.1.3.1) */
 470         if (first) {
 471
 472                 temp = ohci_readl (ohci, &ohci->regs->fminterval);
 473                 ohci->fminterval = temp & 0x3fff;
 474                 if (ohci->fminterval != FI)
 475                         ohci_dbg (ohci, "fminterval delta %d\n",
 476                                 ohci->fminterval - FI);
 477                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
 478                 /* also: power/overcurrent flags in roothub.a */
 479         }
 480
 481         /* Reset USB nearly "by the book".  RemoteWakeupConnected was
 482          * saved if boot firmware (BIOS/SMM/...) told us it's connected,
 483          * or if bus glue did the same (e.g. for PCI add-in cards with
 484          * PCI PM support).
 485          */
 486         ohci_dbg (ohci, "resetting from state '%s', control = 0x%x\n",
 487                         hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS),
 488                         ohci_readl (ohci, &ohci->regs->control));
 489         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0
 490                         && !device_may_wakeup(hcd->self.controller))
 491                 device_init_wakeup(hcd->self.controller, 1);
 492
 493         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 494         case OHCI_USB_OPER:
 495                 temp = 0;
 496                 break;
 497         case OHCI_USB_SUSPEND:
 498         case OHCI_USB_RESUME:
 499                 ohci->hc_control &= OHCI_CTRL_RWC;
 500                 ohci->hc_control |= OHCI_USB_RESUME;
 501                 temp = 10 /* msec wait */;
 502                 break;
 503         // case OHCI_USB_RESET:
 504         default:
 505                 ohci->hc_control &= OHCI_CTRL_RWC;
 506                 ohci->hc_control |= OHCI_USB_RESET;
 507                 temp = 50 /* msec wait */;
 508                 break;
 509         }
 510         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 511         // flush the writes
 512         (void) ohci_readl (ohci, &ohci->regs->control);
 513         msleep(temp);
 514         temp = roothub_a (ohci);
 515         if (!(temp & RH_A_NPS)) {
 516                 /* power down each port */
 517                 for (temp = 0; temp < ohci->num_ports; temp++)
 518                         ohci_writel (ohci, RH_PS_LSDA,
 519                                 &ohci->regs->roothub.portstatus [temp]);
 520         }
 521         // flush those writes
 522         (void) ohci_readl (ohci, &ohci->regs->control);
 523         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 524
 525         /* 2msec timelimit here means no irqs/preempt */
 526         spin_lock_irq (&ohci->lock);
 527
 528 retry:
 529         /* HC Reset requires max 10 us delay */
 530         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
 531         temp = 30;      /* ... allow extra time */
 532         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 533                 if (--temp == 0) {
 534                         spin_unlock_irq (&ohci->lock);
 535                         ohci_err (ohci, "USB HC reset timed out!\n");
 536                         return -1;
 537                 }
 538                 udelay (1);
 539         }
 540
 541         /* now we're in the SUSPEND state ... must go OPERATIONAL
 542          * within 2msec else HC enters RESUME
 543          *
 544          * ... but some hardware won't init fmInterval "by the book"
 545          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
 546          * this if we write fmInterval after we're OPERATIONAL.
 547          * Unclear about ALi, ServerWorks, and others ... this could
 548          * easily be a longstanding bug in chip init on Linux.
 549          */
 550         if (ohci->flags & OHCI_QUIRK_INITRESET) {
 551                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 552                 // flush those writes
 553                 (void) ohci_readl (ohci, &ohci->regs->control);
 554         }
 555
 556         /* Tell the controller where the control and bulk lists are
 557          * The lists are empty now. */
 558         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
 559         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
 560
 561         /* a reset clears this */
 562         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
 563
 564         periodic_reinit (ohci);
 565
 566         /* some OHCI implementations are finicky about how they init.
 567          * bogus values here mean not even enumeration could work.
 568          */
 569         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
 570                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
 571                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
 572                         ohci->flags |= OHCI_QUIRK_INITRESET;
 573                         ohci_dbg (ohci, "enabling initreset quirk\n");
 574                         goto retry;
 575                 }
 576                 spin_unlock_irq (&ohci->lock);
 577                 ohci_err (ohci, "init err (%08x %04x)\n",
 578                         ohci_readl (ohci, &ohci->regs->fminterval),
 579                         ohci_readl (ohci, &ohci->regs->periodicstart));
 580                 return -EOVERFLOW;
 581         }
 582
 583         /* use rhsc irqs after khubd is fully initialized */
 584         hcd->poll_rh = 1;
 585         hcd->uses_new_polling = 1;
 586
 587         /* start controller operations */
 588         ohci->hc_control &= OHCI_CTRL_RWC;
 589         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
 590         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 591         hcd->state = HC_STATE_RUNNING;
 592
 593         /* wake on ConnectStatusChange, matching external hubs */
 594         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
 595
 596         /* Choose the interrupts we care about now, others later on demand */
 597         mask = OHCI_INTR_INIT;
 598         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
 599         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 600
 601         /* handle root hub init quirks ... */
 602         temp = roothub_a (ohci);
 603         temp &= ~(RH_A_PSM | RH_A_OCPM);
 604         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
 605                 /* NSC 87560 and maybe others */
 606                 temp |= RH_A_NOCP;
 607                 temp &= ~(RH_A_POTPGT | RH_A_NPS);
 608                 ohci_writel (ohci, temp, &ohci->regs->roothub.a);
 609         } else if ((ohci->flags & OHCI_QUIRK_AMD756) || distrust_firmware) {
 610                 /* hub power always on; required for AMD-756 and some
 611                  * Mac platforms.  ganged overcurrent reporting, if any.
 612                  */
 613                 temp |= RH_A_NPS;
 614                 ohci_writel (ohci, temp, &ohci->regs->roothub.a);
 615         }
 616         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
 617         ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM,
 618                                                 &ohci->regs->roothub.b);
 619         // flush those writes
 620         (void) ohci_readl (ohci, &ohci->regs->control);
 621
 622         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 623         spin_unlock_irq (&ohci->lock);
 624
 625         // POTPGT delay is bits 24-31, in 2 ms units.
 626         mdelay ((temp >> 23) & 0x1fe);
 627         hcd->state = HC_STATE_RUNNING;
 628
 629         ohci_dump (ohci, 1);
 630
 631         return 0;
 632 }
 633
 634 /*-------------------------------------------------------------------------*/
 635
 636 /* an interrupt happens */
 637
 638 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
 639 {
 640         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 641         struct ohci_regs __iomem *regs = ohci->regs;
 642         int                     ints;
 643
 644         /* we can eliminate a (slow) ohci_readl()
 645            if _only_ WDH caused this irq */
 646         if ((ohci->hcca->done_head != 0)
 647                         && ! (hc32_to_cpup (ohci, &ohci->hcca->done_head)
 648                                 & 0x01)) {
 649                 ints =  OHCI_INTR_WDH;
 650
 651         /* cardbus/... hardware gone before remove() */
 652         } else if ((ints = ohci_readl (ohci, &regs->intrstatus)) == ~(u32)0) {
 653                 disable (ohci);
 654                 ohci_dbg (ohci, "device removed!\n");
 655                 return IRQ_HANDLED;
 656
 657         /* interrupt for some other device? */
 658         } else if ((ints &= ohci_readl (ohci, &regs->intrenable)) == 0) {
 659                 return IRQ_NOTMINE;
 660         }
 661
 662         if (ints & OHCI_INTR_UE) {
 663                 disable (ohci);
 664                 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
 665                 // e.g. due to PCI Master/Target Abort
 666
 667                 ohci_dump (ohci, 1);
 668                 ohci_usb_reset (ohci);
 669         }
 670
 671         if (ints & OHCI_INTR_RHSC) {
 672                 ohci_vdbg(ohci, "rhsc\n");
 673                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 674                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
 675                                 &regs->intrstatus);
 676
 677                 /* NOTE: Vendors didn't always make the same implementation
 678                  * choices for RHSC.  Many followed the spec; RHSC triggers
 679                  * on an edge, like setting and maybe clearing a port status
 680                  * change bit.  With others it's level-triggered, active
 681                  * until khubd clears all the port status change bits.  We'll
 682                  * always disable it here and rely on polling until khubd
 683                  * re-enables it.
 684                  */
 685                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
 686                 usb_hcd_poll_rh_status(hcd);
 687         }
 688
 689         /* For connect and disconnect events, we expect the controller
 690          * to turn on RHSC along with RD.  But for remote wakeup events
 691          * this might not happen.
 692          */
 693         else if (ints & OHCI_INTR_RD) {
 694                 ohci_vdbg(ohci, "resume detect\n");
 695                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
 696                 hcd->poll_rh = 1;
 697                 if (ohci->autostop) {
 698                         spin_lock (&ohci->lock);
 699                         ohci_rh_resume (ohci);
 700                         spin_unlock (&ohci->lock);
 701                 } else
 702                         usb_hcd_resume_root_hub(hcd);
 703         }
 704
 705         if (ints & OHCI_INTR_WDH) {
 706                 if (HC_IS_RUNNING(hcd->state))
 707                         ohci_writel (ohci, OHCI_INTR_WDH, &regs->intrdisable);
 708                 spin_lock (&ohci->lock);
 709                 dl_done_list (ohci);
 710                 spin_unlock (&ohci->lock);
 711                 if (HC_IS_RUNNING(hcd->state))
 712                         ohci_writel (ohci, OHCI_INTR_WDH, &regs->intrenable);
 713         }
 714
 715         /* could track INTR_SO to reduce available PCI/... bandwidth */
 716
 717         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
 718          * when there's still unlinking to be done (next frame).
 719          */
 720         spin_lock (&ohci->lock);
 721         if (ohci->ed_rm_list)
 722                 finish_unlinks (ohci, ohci_frame_no(ohci));
 723         if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
 724                         && HC_IS_RUNNING(hcd->state))
 725                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
 726         spin_unlock (&ohci->lock);
 727
 728         if (HC_IS_RUNNING(hcd->state)) {
 729                 ohci_writel (ohci, ints, &regs->intrstatus);
 730                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
 731                 // flush those writes
 732                 (void) ohci_readl (ohci, &ohci->regs->control);
 733         }
 734
 735         return IRQ_HANDLED;
 736 }
 737
 738 /*-------------------------------------------------------------------------*/
 739
 740 static void ohci_stop (struct usb_hcd *hcd)
 741 {
 742         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 743
 744         ohci_dbg (ohci, "stop %s controller (state 0x%02x)\n",
 745                 hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS),
 746                 hcd->state);
 747         ohci_dump (ohci, 1);
 748
 749         flush_scheduled_work();
 750
 751         ohci_usb_reset (ohci);
 752         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 753         free_irq(hcd->irq, hcd);
 754         hcd->irq = -1;
 755
 756         remove_debug_files (ohci);
 757         ohci_mem_cleanup (ohci);
 758         if (ohci->hcca) {
 759                 dma_free_coherent (hcd->self.controller,
 760                                 sizeof *ohci->hcca,
 761                                 ohci->hcca, ohci->hcca_dma);
 762                 ohci->hcca = NULL;
 763                 ohci->hcca_dma = 0;
 764         }
 765 }
 766
 767 /*-------------------------------------------------------------------------*/
 768
 769 /* must not be called from interrupt context */
 770
 771 #ifdef  CONFIG_PM
 772
 773 static int ohci_restart (struct ohci_hcd *ohci)
 774 {
 775         int temp;
 776         int i;
 777         struct urb_priv *priv;
 778
 779         /* mark any devices gone, so they do nothing till khubd disconnects.
 780          * recycle any "live" eds/tds (and urbs) right away.
 781          * later, khubd disconnect processing will recycle the other state,
 782          * (either as disconnect/reconnect, or maybe someday as a reset).
 783          */
 784         spin_lock_irq(&ohci->lock);
 785         disable (ohci);
 786         usb_root_hub_lost_power(ohci_to_hcd(ohci)->self.root_hub);
 787         if (!list_empty (&ohci->pending))
 788                 ohci_dbg(ohci, "abort schedule...\n");
 789         list_for_each_entry (priv, &ohci->pending, pending) {
 790                 struct urb      *urb = priv->td[0]->urb;
 791                 struct ed       *ed = priv->ed;
 792
 793                 switch (ed->state) {
 794                 case ED_OPER:
 795                         ed->state = ED_UNLINK;
 796                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
 797                         ed_deschedule (ohci, ed);
 798
 799                         ed->ed_next = ohci->ed_rm_list;
 800                         ed->ed_prev = NULL;
 801                         ohci->ed_rm_list = ed;
 802                         /* FALLTHROUGH */
 803                 case ED_UNLINK:
 804                         break;
 805                 default:
 806                         ohci_dbg(ohci, "bogus ed %p state %d\n",
 807                                         ed, ed->state);
 808                 }
 809
 810                 spin_lock (&urb->lock);
 811                 urb->status = -ESHUTDOWN;
 812                 spin_unlock (&urb->lock);
 813         }
 814         finish_unlinks (ohci, 0);
 815         spin_unlock_irq(&ohci->lock);
 816
 817         /* paranoia, in case that didn't work: */
 818
 819         /* empty the interrupt branches */
 820         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
 821         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
 822
 823         /* no EDs to remove */
 824         ohci->ed_rm_list = NULL;
 825
 826         /* empty control and bulk lists */
 827         ohci->ed_controltail = NULL;
 828         ohci->ed_bulktail    = NULL;
 829
 830         if ((temp = ohci_run (ohci)) < 0) {
 831                 ohci_err (ohci, "can't restart, %d\n", temp);
 832                 return temp;
 833         } else {
 834                 /* here we "know" root ports should always stay powered,
 835                  * and that if we try to turn them back on the root hub
 836                  * will respond to CSC processing.
 837                  */
 838                 i = ohci->num_ports;
 839                 while (i--)
 840                         ohci_writel (ohci, RH_PS_PSS,
 841                                 &ohci->regs->roothub.portstatus [i]);
 842                 ohci_dbg (ohci, "restart complete\n");
 843         }
 844         return 0;
 845 }
 846 #endif
 847
 848 /*-------------------------------------------------------------------------*/
 849
 850 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
 851
 852 MODULE_AUTHOR (DRIVER_AUTHOR);
 853 MODULE_DESCRIPTION (DRIVER_INFO);
 854 MODULE_LICENSE ("GPL");
 855
 856 #ifdef CONFIG_PCI
 857 #include "ohci-pci.c"
 858 #endif
 859
 860 #ifdef CONFIG_SA1111
 861 #include "ohci-sa1111.c"
 862 #endif
 863
 864 #ifdef CONFIG_ARCH_S3C2410
 865 #include "ohci-s3c2410.c"
 866 #endif
 867
 868 #ifdef CONFIG_ARCH_OMAP
 869 #include "ohci-omap.c"
 870 #endif
 871
 872 #ifdef CONFIG_ARCH_LH7A404
 873 #include "ohci-lh7a404.c"
 874 #endif
 875
 876 #ifdef CONFIG_PXA27x
 877 #include "ohci-pxa27x.c"
 878 #endif
 879
 880 #ifdef CONFIG_ARCH_EP93XX
 881 #include "ohci-ep93xx.c"
 882 #endif
 883
 884 #ifdef CONFIG_SOC_AU1X00
 885 #include "ohci-au1xxx.c"
 886 #endif
 887
 888 #ifdef CONFIG_PNX8550
 889 #include "ohci-pnx8550.c"
 890 #endif
 891
 892 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
 893 #include "ohci-ppc-soc.c"
 894 #endif
 895
 896 #ifdef CONFIG_ARCH_AT91
 897 #include "ohci-at91.c"
 898 #endif
 899
 900 #ifdef CONFIG_ARCH_PNX4008
 901 #include "ohci-pnx4008.c"
 902 #endif
 903
 904 #if !(defined(CONFIG_PCI) \
 905       || defined(CONFIG_SA1111) \
 906       || defined(CONFIG_ARCH_S3C2410) \
 907       || defined(CONFIG_ARCH_OMAP) \
 908       || defined (CONFIG_ARCH_LH7A404) \
 909       || defined (CONFIG_PXA27x) \
 910       || defined (CONFIG_ARCH_EP93XX) \
 911       || defined (CONFIG_SOC_AU1X00) \
 912       || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \
 913       || defined (CONFIG_ARCH_AT91) \
 914       || defined (CONFIG_ARCH_PNX4008) \
 915         )
 916 #error "missing bus glue for ohci-hcd"
 917 #endif