drivers/usb/host/isp1760-hcd.c

   1 /*
   2  * Driver for the NXP ISP1760 chip
   3  *
   4  * However, the code might contain some bugs. What doesn't work for sure is:
   5  * - ISO
   6  * - OTG
   7  e The interrupt line is configured as active low, level.
   8  *
   9  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10  *
  11  */
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/list.h>
  16 #include <linux/usb.h>
  17 #include <linux/usb/hcd.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/uaccess.h>
  20 #include <linux/io.h>
  21 #include <linux/mm.h>
  22 #include <asm/unaligned.h>
  23 #include <asm/cacheflush.h>
  24
  25 #include "isp1760-hcd.h"
  26
  27 static struct kmem_cache *qtd_cachep;
  28 static struct kmem_cache *qh_cachep;
  29
  30 struct isp1760_hcd {
  31         u32 hcs_params;
  32         spinlock_t              lock;
  33         struct inter_packet_info atl_ints[32];
  34         struct inter_packet_info int_ints[32];
  35         struct memory_chunk memory_pool[BLOCKS];
  36         u32 atl_queued;
  37
  38         /* periodic schedule support */
  39 #define DEFAULT_I_TDPS          1024
  40         unsigned                periodic_size;
  41         unsigned                i_thresh;
  42         unsigned long           reset_done;
  43         unsigned long           next_statechange;
  44         unsigned int            devflags;
  45 };
  46
  47 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  48 {
  49         return (struct isp1760_hcd *) (hcd->hcd_priv);
  50 }
  51
  52 /* Section 2.2 Host Controller Capability Registers */
  53 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
  54 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
  55 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
  56 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
  57 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
  58 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
  59 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
  60
  61 /* Section 2.3 Host Controller Operational Registers */
  62 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
  63 #define CMD_RESET       (1<<1)          /* reset HC not bus */
  64 #define CMD_RUN         (1<<0)          /* start/stop HC */
  65 #define STS_PCD         (1<<2)          /* port change detect */
  66 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
  67
  68 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
  69 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
  70 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10))  /* USB 1.1 device */
  71 #define PORT_RESET      (1<<8)          /* reset port */
  72 #define PORT_SUSPEND    (1<<7)          /* suspend port */
  73 #define PORT_RESUME     (1<<6)          /* resume it */
  74 #define PORT_PE         (1<<2)          /* port enable */
  75 #define PORT_CSC        (1<<1)          /* connect status change */
  76 #define PORT_CONNECT    (1<<0)          /* device connected */
  77 #define PORT_RWC_BITS   (PORT_CSC)
  78
  79 struct isp1760_qtd {
  80         u8 packet_type;
  81         void *data_buffer;
  82         u32 payload_addr;
  83
  84         /* the rest is HCD-private */
  85         struct list_head qtd_list;
  86         struct urb *urb;
  87         size_t length;
  88
  89         /* isp special*/
  90         u32 status;
  91 #define URB_ENQUEUED            (1 << 1)
  92 };
  93
  94 struct isp1760_qh {
  95         /* first part defined by EHCI spec */
  96         struct list_head qtd_list;
  97
  98         u32 toggle;
  99         u32 ping;
 100 };
 101
 102 /*
 103  * Access functions for isp176x registers (addresses 0..0x03FF).
 104  */
 105 static u32 reg_read32(void __iomem *base, u32 reg)
 106 {
 107         return readl(base + reg);
 108 }
 109
 110 static void reg_write32(void __iomem *base, u32 reg, u32 val)
 111 {
 112         writel(val, base + reg);
 113 }
 114
 115 /*
 116  * Access functions for isp176x memory (offset >= 0x0400).
 117  *
 118  * bank_reads8() reads memory locations prefetched by an earlier write to
 119  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
 120  * bank optimizations, you should use the more generic mem_reads8() below.
 121  *
 122  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
 123  * below.
 124  *
 125  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
 126  * doesn't quite work because some people have to enforce 32-bit access
 127  */
 128 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
 129                                                         __u32 *dst, u32 bytes)
 130 {
 131         __u32 __iomem *src;
 132         u32 val;
 133         __u8 *src_byteptr;
 134         __u8 *dst_byteptr;
 135
 136         src = src_base + (bank_addr | src_offset);
 137
 138         if (src_offset < PAYLOAD_OFFSET) {
 139                 while (bytes >= 4) {
 140                         *dst = le32_to_cpu(__raw_readl(src));
 141                         bytes -= 4;
 142                         src++;
 143                         dst++;
 144                 }
 145         } else {
 146                 while (bytes >= 4) {
 147                         *dst = __raw_readl(src);
 148                         bytes -= 4;
 149                         src++;
 150                         dst++;
 151                 }
 152         }
 153
 154         if (!bytes)
 155                 return;
 156
 157         /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
 158          * allocated.
 159          */
 160         if (src_offset < PAYLOAD_OFFSET)
 161                 val = le32_to_cpu(__raw_readl(src));
 162         else
 163                 val = __raw_readl(src);
 164
 165         dst_byteptr = (void *) dst;
 166         src_byteptr = (void *) &val;
 167         while (bytes > 0) {
 168                 *dst_byteptr = *src_byteptr;
 169                 dst_byteptr++;
 170                 src_byteptr++;
 171                 bytes--;
 172         }
 173 }
 174
 175 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
 176                                                                 u32 bytes)
 177 {
 178         reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
 179         ndelay(90);
 180         bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
 181 }
 182
 183 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
 184                                                 __u32 const *src, u32 bytes)
 185 {
 186         __u32 __iomem *dst;
 187
 188         dst = dst_base + dst_offset;
 189
 190         if (dst_offset < PAYLOAD_OFFSET) {
 191                 while (bytes >= 4) {
 192                         __raw_writel(cpu_to_le32(*src), dst);
 193                         bytes -= 4;
 194                         src++;
 195                         dst++;
 196                 }
 197         } else {
 198                 while (bytes >= 4) {
 199                         __raw_writel(*src, dst);
 200                         bytes -= 4;
 201                         src++;
 202                         dst++;
 203                 }
 204         }
 205
 206         if (!bytes)
 207                 return;
 208         /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
 209          * extra bytes should not be read by the HW.
 210          */
 211
 212         if (dst_offset < PAYLOAD_OFFSET)
 213                 __raw_writel(cpu_to_le32(*src), dst);
 214         else
 215                 __raw_writel(*src, dst);
 216 }
 217
 218 /*
 219  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
 220  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
 221  */
 222 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
 223                                                                 struct ptd *ptd)
 224 {
 225         reg_write32(base, HC_MEMORY_REG,
 226                                 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
 227         ndelay(90);
 228         bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
 229                                                 (void *) ptd, sizeof(*ptd));
 230 }
 231
 232 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
 233                                                                 struct ptd *ptd)
 234 {
 235         mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
 236                                                 &ptd->dw1, 7*sizeof(ptd->dw1));
 237         /* Make sure dw0 gets written last (after other dw's and after payload)
 238            since it contains the enable bit */
 239         wmb();
 240         mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
 241                                                         sizeof(ptd->dw0));
 242 }
 243
 244
 245 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
 246 static void init_memory(struct isp1760_hcd *priv)
 247 {
 248         int i, curr;
 249         u32 payload_addr;
 250
 251         payload_addr = PAYLOAD_OFFSET;
 252         for (i = 0; i < BLOCK_1_NUM; i++) {
 253                 priv->memory_pool[i].start = payload_addr;
 254                 priv->memory_pool[i].size = BLOCK_1_SIZE;
 255                 priv->memory_pool[i].free = 1;
 256                 payload_addr += priv->memory_pool[i].size;
 257         }
 258
 259         curr = i;
 260         for (i = 0; i < BLOCK_2_NUM; i++) {
 261                 priv->memory_pool[curr + i].start = payload_addr;
 262                 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
 263                 priv->memory_pool[curr + i].free = 1;
 264                 payload_addr += priv->memory_pool[curr + i].size;
 265         }
 266
 267         curr = i;
 268         for (i = 0; i < BLOCK_3_NUM; i++) {
 269                 priv->memory_pool[curr + i].start = payload_addr;
 270                 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
 271                 priv->memory_pool[curr + i].free = 1;
 272                 payload_addr += priv->memory_pool[curr + i].size;
 273         }
 274
 275         BUG_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
 276 }
 277
 278 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 279 {
 280         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 281         int i;
 282
 283         BUG_ON(qtd->payload_addr);
 284
 285         if (!qtd->length)
 286                 return;
 287
 288         for (i = 0; i < BLOCKS; i++) {
 289                 if (priv->memory_pool[i].size >= qtd->length &&
 290                                 priv->memory_pool[i].free) {
 291                         priv->memory_pool[i].free = 0;
 292                         qtd->payload_addr = priv->memory_pool[i].start;
 293                         return;
 294                 }
 295         }
 296
 297         dev_err(hcd->self.controller,
 298                                 "%s: Cannot allocate %zu bytes of memory\n"
 299                                 "Current memory map:\n",
 300                                 __func__, qtd->length);
 301         for (i = 0; i < BLOCKS; i++) {
 302                 dev_err(hcd->self.controller, "Pool %2d size %4d status: %d\n",
 303                                 i, priv->memory_pool[i].size,
 304                                 priv->memory_pool[i].free);
 305         }
 306         /* XXX maybe -ENOMEM could be possible */
 307         BUG();
 308         return;
 309 }
 310
 311 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 312 {
 313         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 314         int i;
 315
 316         if (!qtd->payload_addr)
 317                 return;
 318
 319         for (i = 0; i < BLOCKS; i++) {
 320                 if (priv->memory_pool[i].start == qtd->payload_addr) {
 321                         BUG_ON(priv->memory_pool[i].free);
 322                         priv->memory_pool[i].free = 1;
 323                         qtd->payload_addr = 0;
 324                         return;
 325                 }
 326         }
 327
 328         dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
 329                                                 __func__, qtd->payload_addr);
 330         BUG();
 331 }
 332
 333 static void isp1760_init_regs(struct usb_hcd *hcd)
 334 {
 335         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
 336         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 337         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 338         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 339
 340         reg_write32(hcd->regs, HC_ATL_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
 341         reg_write32(hcd->regs, HC_INT_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
 342         reg_write32(hcd->regs, HC_ISO_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
 343 }
 344
 345 static int handshake(struct usb_hcd *hcd, u32 reg,
 346                       u32 mask, u32 done, int usec)
 347 {
 348         u32 result;
 349
 350         do {
 351                 result = reg_read32(hcd->regs, reg);
 352                 if (result == ~0)
 353                         return -ENODEV;
 354                 result &= mask;
 355                 if (result == done)
 356                         return 0;
 357                 udelay(1);
 358                 usec--;
 359         } while (usec > 0);
 360         return -ETIMEDOUT;
 361 }
 362
 363 /* reset a non-running (STS_HALT == 1) controller */
 364 static int ehci_reset(struct usb_hcd *hcd)
 365 {
 366         int retval;
 367         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 368
 369         u32 command = reg_read32(hcd->regs, HC_USBCMD);
 370
 371         command |= CMD_RESET;
 372         reg_write32(hcd->regs, HC_USBCMD, command);
 373         hcd->state = HC_STATE_HALT;
 374         priv->next_statechange = jiffies;
 375         retval = handshake(hcd, HC_USBCMD,
 376                             CMD_RESET, 0, 250 * 1000);
 377         return retval;
 378 }
 379
 380 static void qh_destroy(struct isp1760_qh *qh)
 381 {
 382         BUG_ON(!list_empty(&qh->qtd_list));
 383         kmem_cache_free(qh_cachep, qh);
 384 }
 385
 386 static struct isp1760_qh *isp1760_qh_alloc(gfp_t flags)
 387 {
 388         struct isp1760_qh *qh;
 389
 390         qh = kmem_cache_zalloc(qh_cachep, flags);
 391         if (!qh)
 392                 return qh;
 393
 394         INIT_LIST_HEAD(&qh->qtd_list);
 395         return qh;
 396 }
 397
 398 /* magic numbers that can affect system performance */
 399 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
 400 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
 401 #define EHCI_TUNE_RL_TT         0
 402 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
 403 #define EHCI_TUNE_MULT_TT       1
 404 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
 405
 406 /* one-time init, only for memory state */
 407 static int priv_init(struct usb_hcd *hcd)
 408 {
 409         struct isp1760_hcd              *priv = hcd_to_priv(hcd);
 410         u32                     hcc_params;
 411
 412         spin_lock_init(&priv->lock);
 413
 414         /*
 415          * hw default: 1K periodic list heads, one per frame.
 416          * periodic_size can shrink by USBCMD update if hcc_params allows.
 417          */
 418         priv->periodic_size = DEFAULT_I_TDPS;
 419
 420         /* controllers may cache some of the periodic schedule ... */
 421         hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
 422         /* full frame cache */
 423         if (HCC_ISOC_CACHE(hcc_params))
 424                 priv->i_thresh = 8;
 425         else /* N microframes cached */
 426                 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 427
 428         return 0;
 429 }
 430
 431 static int isp1760_hc_setup(struct usb_hcd *hcd)
 432 {
 433         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 434         int result;
 435         u32 scratch, hwmode;
 436
 437         /* Setup HW Mode Control: This assumes a level active-low interrupt */
 438         hwmode = HW_DATA_BUS_32BIT;
 439
 440         if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
 441                 hwmode &= ~HW_DATA_BUS_32BIT;
 442         if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
 443                 hwmode |= HW_ANA_DIGI_OC;
 444         if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
 445                 hwmode |= HW_DACK_POL_HIGH;
 446         if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
 447                 hwmode |= HW_DREQ_POL_HIGH;
 448         if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
 449                 hwmode |= HW_INTR_HIGH_ACT;
 450         if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
 451                 hwmode |= HW_INTR_EDGE_TRIG;
 452
 453         /*
 454          * We have to set this first in case we're in 16-bit mode.
 455          * Write it twice to ensure correct upper bits if switching
 456          * to 16-bit mode.
 457          */
 458         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 459         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 460
 461         reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
 462         /* Change bus pattern */
 463         scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 464         scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
 465         if (scratch != 0xdeadbabe) {
 466                 dev_err(hcd->self.controller, "Scratch test failed.\n");
 467                 return -ENODEV;
 468         }
 469
 470         /* pre reset */
 471         isp1760_init_regs(hcd);
 472
 473         /* reset */
 474         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
 475         mdelay(100);
 476
 477         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
 478         mdelay(100);
 479
 480         result = ehci_reset(hcd);
 481         if (result)
 482                 return result;
 483
 484         /* Step 11 passed */
 485
 486         dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
 487                            (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
 488                            16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
 489                            "analog" : "digital");
 490
 491         /* ATL reset */
 492         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
 493         mdelay(10);
 494         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 495
 496         reg_write32(hcd->regs, HC_INTERRUPT_REG, INTERRUPT_ENABLE_MASK);
 497         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
 498
 499         /*
 500          * PORT 1 Control register of the ISP1760 is the OTG control
 501          * register on ISP1761. Since there is no OTG or device controller
 502          * support in this driver, we use port 1 as a "normal" USB host port on
 503          * both chips.
 504          */
 505         reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
 506         mdelay(10);
 507
 508         priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
 509
 510         return priv_init(hcd);
 511 }
 512
 513 static void isp1760_init_maps(struct usb_hcd *hcd)
 514 {
 515         /*set last maps, for iso its only 1, else 32 tds bitmap*/
 516         reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
 517         reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
 518         reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
 519 }
 520
 521 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
 522 {
 523         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
 524         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0);
 525         reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
 526         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0);
 527         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
 528         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
 529         /* step 23 passed */
 530 }
 531
 532 static int isp1760_run(struct usb_hcd *hcd)
 533 {
 534         int retval;
 535         u32 temp;
 536         u32 command;
 537         u32 chipid;
 538
 539         hcd->uses_new_polling = 1;
 540
 541         hcd->state = HC_STATE_RUNNING;
 542         isp1760_enable_interrupts(hcd);
 543         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
 544         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
 545
 546         command = reg_read32(hcd->regs, HC_USBCMD);
 547         command &= ~(CMD_LRESET|CMD_RESET);
 548         command |= CMD_RUN;
 549         reg_write32(hcd->regs, HC_USBCMD, command);
 550
 551         retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN,
 552                         250 * 1000);
 553         if (retval)
 554                 return retval;
 555
 556         /*
 557          * XXX
 558          * Spec says to write FLAG_CF as last config action, priv code grabs
 559          * the semaphore while doing so.
 560          */
 561         down_write(&ehci_cf_port_reset_rwsem);
 562         reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
 563
 564         retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
 565         up_write(&ehci_cf_port_reset_rwsem);
 566         if (retval)
 567                 return retval;
 568
 569         chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 570         dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
 571                                         chipid & 0xffff, chipid >> 16);
 572
 573         /* PTD Register Init Part 2, Step 28 */
 574         /* enable INTs */
 575         isp1760_init_maps(hcd);
 576
 577         /* GRR this is run-once init(), being done every time the HC starts.
 578          * So long as they're part of class devices, we can't do it init()
 579          * since the class device isn't created that early.
 580          */
 581         return 0;
 582 }
 583
 584 static u32 base_to_chip(u32 base)
 585 {
 586         return ((base - 0x400) >> 3);
 587 }
 588
 589 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
 590 {
 591         struct urb *urb;
 592
 593         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 594                 return 1;
 595
 596         urb = qtd->urb;
 597         qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
 598         return (qtd->urb != urb);
 599 }
 600
 601 static void transform_into_atl(struct isp1760_qh *qh,
 602                         struct isp1760_qtd *qtd, struct ptd *ptd)
 603 {
 604         u32 maxpacket;
 605         u32 multi;
 606         u32 pid_code;
 607         u32 rl = RL_COUNTER;
 608         u32 nak = NAK_COUNTER;
 609
 610         memset(ptd, 0, sizeof(*ptd));
 611
 612         /* according to 3.6.2, max packet len can not be > 0x400 */
 613         maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
 614                                                 usb_pipeout(qtd->urb->pipe));
 615         multi =  1 + ((maxpacket >> 11) & 0x3);
 616         maxpacket &= 0x7ff;
 617
 618         /* DW0 */
 619         ptd->dw0 = PTD_VALID;
 620         ptd->dw0 |= PTD_LENGTH(qtd->length);
 621         ptd->dw0 |= PTD_MAXPACKET(maxpacket);
 622         ptd->dw0 |= PTD_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
 623
 624         /* DW1 */
 625         ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
 626         ptd->dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
 627
 628         pid_code = qtd->packet_type;
 629         ptd->dw1 |= PTD_PID_TOKEN(pid_code);
 630
 631         if (usb_pipebulk(qtd->urb->pipe))
 632                 ptd->dw1 |= PTD_TRANS_BULK;
 633         else if  (usb_pipeint(qtd->urb->pipe))
 634                 ptd->dw1 |= PTD_TRANS_INT;
 635
 636         if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
 637                 /* split transaction */
 638
 639                 ptd->dw1 |= PTD_TRANS_SPLIT;
 640                 if (qtd->urb->dev->speed == USB_SPEED_LOW)
 641                         ptd->dw1 |= PTD_SE_USB_LOSPEED;
 642
 643                 ptd->dw1 |= PTD_PORT_NUM(qtd->urb->dev->ttport);
 644                 ptd->dw1 |= PTD_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
 645
 646                 /* SE bit for Split INT transfers */
 647                 if (usb_pipeint(qtd->urb->pipe) &&
 648                                 (qtd->urb->dev->speed == USB_SPEED_LOW))
 649                         ptd->dw1 |= 2 << 16;
 650
 651                 ptd->dw3 = 0;
 652                 rl = 0;
 653                 nak = 0;
 654         } else {
 655                 ptd->dw0 |= PTD_MULTI(multi);
 656                 if (usb_pipecontrol(qtd->urb->pipe) ||
 657                                                 usb_pipebulk(qtd->urb->pipe))
 658                         ptd->dw3 = qh->ping;
 659                 else
 660                         ptd->dw3 = 0;
 661         }
 662         /* DW2 */
 663         ptd->dw2 = 0;
 664         ptd->dw2 |= PTD_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
 665         ptd->dw2 |= PTD_RL_CNT(rl);
 666         ptd->dw3 |= PTD_NAC_CNT(nak);
 667
 668         /* DW3 */
 669         ptd->dw3 |= qh->toggle;
 670         if (usb_pipecontrol(qtd->urb->pipe)) {
 671                 if (qtd->data_buffer == qtd->urb->setup_packet)
 672                         ptd->dw3 &= ~PTD_DATA_TOGGLE(1);
 673                 else if (last_qtd_of_urb(qtd, qh))
 674                         ptd->dw3 |= PTD_DATA_TOGGLE(1);
 675         }
 676
 677         ptd->dw3 |= PTD_ACTIVE;
 678         /* Cerr */
 679         ptd->dw3 |= PTD_CERR(ERR_COUNTER);
 680 }
 681
 682 static void transform_add_int(struct isp1760_qh *qh,
 683                         struct isp1760_qtd *qtd, struct ptd *ptd)
 684 {
 685         u32 usof;
 686         u32 period;
 687
 688         /*
 689          * Most of this is guessing. ISP1761 datasheet is quite unclear, and
 690          * the algorithm from the original Philips driver code, which was
 691          * pretty much used in this driver before as well, is quite horrendous
 692          * and, i believe, incorrect. The code below follows the datasheet and
 693          * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
 694          * more reliable this way (fingers crossed...).
 695          */
 696
 697         if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
 698                 /* urb->interval is in units of microframes (1/8 ms) */
 699                 period = qtd->urb->interval >> 3;
 700
 701                 if (qtd->urb->interval > 4)
 702                         usof = 0x01; /* One bit set =>
 703                                                 interval 1 ms * uFrame-match */
 704                 else if (qtd->urb->interval > 2)
 705                         usof = 0x22; /* Two bits set => interval 1/2 ms */
 706                 else if (qtd->urb->interval > 1)
 707                         usof = 0x55; /* Four bits set => interval 1/4 ms */
 708                 else
 709                         usof = 0xff; /* All bits set => interval 1/8 ms */
 710         } else {
 711                 /* urb->interval is in units of frames (1 ms) */
 712                 period = qtd->urb->interval;
 713                 usof = 0x0f;            /* Execute Start Split on any of the
 714                                            four first uFrames */
 715
 716                 /*
 717                  * First 8 bits in dw5 is uSCS and "specifies which uSOF the
 718                  * complete split needs to be sent. Valid only for IN." Also,
 719                  * "All bits can be set to one for every transfer." (p 82,
 720                  * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
 721                  * that number come from? 0xff seems to work fine...
 722                  */
 723                 /* ptd->dw5 = 0x1c; */
 724                 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
 725         }
 726
 727         period = period >> 1;/* Ensure equal or shorter period than requested */
 728         period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
 729
 730         ptd->dw2 |= period;
 731         ptd->dw4 = usof;
 732 }
 733
 734 static void transform_into_int(struct isp1760_qh *qh,
 735                         struct isp1760_qtd *qtd, struct ptd *ptd)
 736 {
 737         transform_into_atl(qh, qtd, ptd);
 738         transform_add_int(qh, qtd, ptd);
 739 }
 740
 741 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
 742                 u32 token)
 743 {
 744         int count;
 745
 746         qtd->data_buffer = databuffer;
 747         qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
 748
 749         if (len > MAX_PAYLOAD_SIZE)
 750                 count = MAX_PAYLOAD_SIZE;
 751         else
 752                 count = len;
 753
 754         qtd->length = count;
 755         return count;
 756 }
 757
 758 static int check_error(struct usb_hcd *hcd, struct ptd *ptd)
 759 {
 760         int error = 0;
 761
 762         if (ptd->dw3 & DW3_HALT_BIT) {
 763                 error = -EPIPE;
 764
 765                 if (ptd->dw3 & DW3_ERROR_BIT)
 766                         pr_err("error bit is set in DW3\n");
 767         }
 768
 769         if (ptd->dw3 & DW3_QTD_ACTIVE) {
 770                 dev_err(hcd->self.controller, "Transfer active bit is set DW3\n"
 771                         "nak counter: %d, rl: %d\n",
 772                         (ptd->dw3 >> 19) & 0xf, (ptd->dw2 >> 25) & 0xf);
 773         }
 774
 775         return error;
 776 }
 777
 778 static void check_int_err_status(struct usb_hcd *hcd, u32 dw4)
 779 {
 780         u32 i;
 781
 782         dw4 >>= 8;
 783
 784         for (i = 0; i < 8; i++) {
 785                 switch (dw4 & 0x7) {
 786                 case INT_UNDERRUN:
 787                         dev_err(hcd->self.controller, "Underrun (%d)\n", i);
 788                         break;
 789
 790                 case INT_EXACT:
 791                         dev_err(hcd->self.controller,
 792                                                 "Transaction error (%d)\n", i);
 793                         break;
 794
 795                 case INT_BABBLE:
 796                         dev_err(hcd->self.controller, "Babble error (%d)\n", i);
 797                         break;
 798                 }
 799                 dw4 >>= 3;
 800         }
 801 }
 802
 803 static void enqueue_one_qtd(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 804 {
 805         if (qtd->length && (qtd->length <= MAX_PAYLOAD_SIZE)) {
 806                 switch (qtd->packet_type) {
 807                 case IN_PID:
 808                         break;
 809                 case OUT_PID:
 810                 case SETUP_PID:
 811                         mem_writes8(hcd->regs, qtd->payload_addr,
 812                                                 qtd->data_buffer, qtd->length);
 813                 }
 814         }
 815 }
 816
 817 static void enqueue_one_atl_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
 818                                         u32 slot, struct isp1760_qtd *qtd)
 819 {
 820         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 821         struct ptd ptd;
 822
 823         alloc_mem(hcd, qtd);
 824         transform_into_atl(qh, qtd, &ptd);
 825         ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
 826         enqueue_one_qtd(hcd, qtd);
 827
 828         priv->atl_ints[slot].qh = qh;
 829         priv->atl_ints[slot].qtd = qtd;
 830         qtd->status |= URB_ENQUEUED;
 831         qtd->status |= slot << 16;
 832 }
 833
 834 static void enqueue_one_int_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
 835                                         u32 slot, struct isp1760_qtd *qtd)
 836 {
 837         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 838         struct ptd ptd;
 839
 840         alloc_mem(hcd, qtd);
 841         transform_into_int(qh, qtd, &ptd);
 842         ptd_write(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
 843         enqueue_one_qtd(hcd, qtd);
 844
 845         priv->int_ints[slot].qh = qh;
 846         priv->int_ints[slot].qtd = qtd;
 847         qtd->status |= URB_ENQUEUED;
 848         qtd->status |= slot << 16;
 849 }
 850
 851 static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
 852                                   struct isp1760_qtd *qtd)
 853 {
 854         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 855         u32 skip_map, or_map;
 856         u32 slot;
 857         u32 buffstatus;
 858
 859         /*
 860          * When this function is called from the interrupt handler to enqueue
 861          * a follow-up packet, the SKIP register gets written and read back
 862          * almost immediately. With ISP1761, this register requires a delay of
 863          * 195ns between a write and subsequent read (see section 15.1.1.3).
 864          */
 865         mmiowb();
 866         ndelay(195);
 867         skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
 868
 869         BUG_ON(!skip_map);
 870         slot = __ffs(skip_map);
 871
 872         enqueue_one_atl_qtd(hcd, qh, slot, qtd);
 873
 874         or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
 875         or_map |= (1 << slot);
 876         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
 877
 878         skip_map &= ~(1 << slot);
 879         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
 880
 881         priv->atl_queued++;
 882         if (priv->atl_queued == 2)
 883                 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
 884                                 INTERRUPT_ENABLE_SOT_MASK);
 885
 886         buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
 887         buffstatus |= ATL_BUFFER;
 888         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
 889 }
 890
 891 static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
 892                                   struct isp1760_qtd *qtd)
 893 {
 894         u32 skip_map, or_map;
 895         u32 slot;
 896         u32 buffstatus;
 897
 898         /*
 899          * When this function is called from the interrupt handler to enqueue
 900          * a follow-up packet, the SKIP register gets written and read back
 901          * almost immediately. With ISP1761, this register requires a delay of
 902          * 195ns between a write and subsequent read (see section 15.1.1.3).
 903          */
 904         mmiowb();
 905         ndelay(195);
 906         skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
 907
 908         BUG_ON(!skip_map);
 909         slot = __ffs(skip_map);
 910
 911         enqueue_one_int_qtd(hcd, qh, slot, qtd);
 912
 913         or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
 914         or_map |= (1 << slot);
 915         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
 916
 917         skip_map &= ~(1 << slot);
 918         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
 919
 920         buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
 921         buffstatus |= INT_BUFFER;
 922         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
 923 }
 924
 925 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
 926 __releases(priv->lock)
 927 __acquires(priv->lock)
 928 {
 929         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 930
 931         if (!urb->unlinked) {
 932                 if (urb->status == -EINPROGRESS)
 933                         urb->status = 0;
 934         }
 935
 936         if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
 937                 void *ptr;
 938                 for (ptr = urb->transfer_buffer;
 939                      ptr < urb->transfer_buffer + urb->transfer_buffer_length;
 940                      ptr += PAGE_SIZE)
 941                         flush_dcache_page(virt_to_page(ptr));
 942         }
 943
 944         /* complete() can reenter this HCD */
 945         usb_hcd_unlink_urb_from_ep(hcd, urb);
 946         spin_unlock(&priv->lock);
 947         usb_hcd_giveback_urb(hcd, urb, urb->status);
 948         spin_lock(&priv->lock);
 949 }
 950
 951 static void isp1760_qtd_free(struct isp1760_qtd *qtd)
 952 {
 953         BUG_ON(qtd->payload_addr);
 954         kmem_cache_free(qtd_cachep, qtd);
 955 }
 956
 957 static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd,
 958                                                         struct isp1760_qh *qh)
 959 {
 960         struct isp1760_qtd *tmp_qtd;
 961
 962         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 963                 tmp_qtd = NULL;
 964         else
 965                 tmp_qtd = list_entry(qtd->qtd_list.next, struct isp1760_qtd,
 966                                                                 qtd_list);
 967         list_del(&qtd->qtd_list);
 968         isp1760_qtd_free(qtd);
 969         return tmp_qtd;
 970 }
 971
 972 /*
 973  * Remove this QTD from the QH list and free its memory. If this QTD
 974  * isn't the last one than remove also his successor(s).
 975  * Returns the QTD which is part of an new URB and should be enqueued.
 976  */
 977 static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd,
 978                                                         struct isp1760_qh *qh)
 979 {
 980         struct urb *urb;
 981
 982         urb = qtd->urb;
 983         do {
 984                 qtd = clean_this_qtd(qtd, qh);
 985         } while (qtd && (qtd->urb == urb));
 986
 987         return qtd;
 988 }
 989
 990 static void do_atl_int(struct usb_hcd *hcd)
 991 {
 992         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 993         u32 done_map, skip_map;
 994         struct ptd ptd;
 995         struct urb *urb;
 996         u32 slot;
 997         u32 length;
 998         u32 or_map;
 999         u32 status = -EINVAL;
1000         int error;
1001         struct isp1760_qtd *qtd;
1002         struct isp1760_qh *qh;
1003         u32 rl;
1004         u32 nakcount;
1005
1006         done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1007         skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1008
1009         or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1010         or_map &= ~done_map;
1011         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1012
1013         while (done_map) {
1014                 status = 0;
1015                 priv->atl_queued--;
1016
1017                 slot = __ffs(done_map);
1018                 done_map &= ~(1 << slot);
1019                 skip_map |= (1 << slot);
1020
1021                 qtd = priv->atl_ints[slot].qtd;
1022                 qh = priv->atl_ints[slot].qh;
1023
1024                 if (!qh) {
1025                         dev_err(hcd->self.controller, "qh is 0\n");
1026                         continue;
1027                 }
1028                 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1029
1030                 rl = (ptd.dw2 >> 25) & 0x0f;
1031                 nakcount = (ptd.dw3 >> 19) & 0xf;
1032
1033                 /* Transfer Error, *but* active and no HALT -> reload */
1034                 if ((ptd.dw3 & DW3_ERROR_BIT) && (ptd.dw3 & DW3_QTD_ACTIVE) &&
1035                                 !(ptd.dw3 & DW3_HALT_BIT)) {
1036
1037                         /* according to ppriv code, we have to
1038                          * reload this one if trasfered bytes != requested bytes
1039                          * else act like everything went smooth..
1040                          * XXX This just doesn't feel right and hasn't
1041                          * triggered so far.
1042                          */
1043
1044                         length = PTD_XFERRED_LENGTH(ptd.dw3);
1045                         dev_err(hcd->self.controller,
1046                                         "Should reload now... transferred %d "
1047                                         "of %zu\n", length, qtd->length);
1048                         BUG();
1049                 }
1050
1051                 if (!nakcount && (ptd.dw3 & DW3_QTD_ACTIVE)) {
1052                         u32 buffstatus;
1053
1054                         /*
1055                          * NAKs are handled in HW by the chip. Usually if the
1056                          * device is not able to send data fast enough.
1057                          * This happens mostly on slower hardware.
1058                          */
1059
1060                         /* RL counter = ERR counter */
1061                         ptd.dw3 &= ~(0xf << 19);
1062                         ptd.dw3 |= rl << 19;
1063                         ptd.dw3 &= ~(3 << (55 - 32));
1064                         ptd.dw3 |= ERR_COUNTER << (55 - 32);
1065
1066                         /*
1067                          * It is not needed to write skip map back because it
1068                          * is unchanged. Just make sure that this entry is
1069                          * unskipped once it gets written to the HW.
1070                          */
1071                         skip_map &= ~(1 << slot);
1072                         or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1073                         or_map |= 1 << slot;
1074                         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1075
1076                         ptd.dw0 |= PTD_VALID;
1077                         ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1078
1079                         priv->atl_queued++;
1080                         if (priv->atl_queued == 2)
1081                                 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1082                                                 INTERRUPT_ENABLE_SOT_MASK);
1083
1084                         buffstatus = reg_read32(hcd->regs,
1085                                                         HC_BUFFER_STATUS_REG);
1086                         buffstatus |= ATL_BUFFER;
1087                         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1088                                                                 buffstatus);
1089                         continue;
1090                 }
1091
1092                 error = check_error(hcd, &ptd);
1093                 if (error) {
1094                         status = error;
1095                         priv->atl_ints[slot].qh->toggle = 0;
1096                         priv->atl_ints[slot].qh->ping = 0;
1097                         qtd->urb->status = -EPIPE;
1098
1099 #if 0
1100                         printk(KERN_ERR "Error in %s().\n", __func__);
1101                         printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1102                                         "dw3: %08x dw4: %08x dw5: %08x dw6: "
1103                                         "%08x dw7: %08x\n",
1104                                         ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1105                                         ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1106 #endif
1107                 } else {
1108                         priv->atl_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
1109                         priv->atl_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
1110                 }
1111
1112                 length = PTD_XFERRED_LENGTH(ptd.dw3);
1113                 if (length) {
1114                         switch (DW1_GET_PID(ptd.dw1)) {
1115                         case IN_PID:
1116                                 mem_reads8(hcd->regs, qtd->payload_addr,
1117                                                 qtd->data_buffer, length);
1118
1119                         case OUT_PID:
1120
1121                                 qtd->urb->actual_length += length;
1122
1123                         case SETUP_PID:
1124                                 break;
1125                         }
1126                 }
1127
1128                 priv->atl_ints[slot].qtd = NULL;
1129                 priv->atl_ints[slot].qh = NULL;
1130
1131                 free_mem(hcd, qtd);
1132
1133                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1134
1135                 if (qtd->urb->status == -EPIPE) {
1136                         /* HALT was received */
1137
1138                         urb = qtd->urb;
1139                         qtd = clean_up_qtdlist(qtd, qh);
1140                         isp1760_urb_done(hcd, urb);
1141
1142                 } else if (usb_pipebulk(qtd->urb->pipe) &&
1143                                                 (length < qtd->length)) {
1144                         /* short BULK received */
1145
1146                         if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) {
1147                                 qtd->urb->status = -EREMOTEIO;
1148                                 dev_dbg(hcd->self.controller,
1149                                                 "short bulk, %d instead %zu "
1150                                                 "with URB_SHORT_NOT_OK flag.\n",
1151                                                 length, qtd->length);
1152                         }
1153
1154                         if (qtd->urb->status == -EINPROGRESS)
1155                                 qtd->urb->status = 0;
1156
1157                         urb = qtd->urb;
1158                         qtd = clean_up_qtdlist(qtd, qh);
1159                         isp1760_urb_done(hcd, urb);
1160
1161                 } else if (last_qtd_of_urb(qtd, qh)) {
1162                         /* that was the last qtd of that URB */
1163
1164                         if (qtd->urb->status == -EINPROGRESS)
1165                                 qtd->urb->status = 0;
1166
1167                         urb = qtd->urb;
1168                         qtd = clean_up_qtdlist(qtd, qh);
1169                         isp1760_urb_done(hcd, urb);
1170
1171                 } else {
1172                         /* next QTD of this URB */
1173
1174                         qtd = clean_this_qtd(qtd, qh);
1175                         BUG_ON(!qtd);
1176                 }
1177
1178                 if (qtd)
1179                         enqueue_an_ATL_packet(hcd, qh, qtd);
1180
1181                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1182         }
1183         if (priv->atl_queued <= 1)
1184                 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1185                                                         INTERRUPT_ENABLE_MASK);
1186 }
1187
1188 static void do_intl_int(struct usb_hcd *hcd)
1189 {
1190         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1191         u32 done_map, skip_map;
1192         struct ptd ptd;
1193         struct urb *urb;
1194         u32 length;
1195         u32 or_map;
1196         int error;
1197         u32 slot;
1198         struct isp1760_qtd *qtd;
1199         struct isp1760_qh *qh;
1200
1201         done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1202         skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1203
1204         or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
1205         or_map &= ~done_map;
1206         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
1207
1208         while (done_map) {
1209                 slot = __ffs(done_map);
1210                 done_map &= ~(1 << slot);
1211                 skip_map |= (1 << slot);
1212
1213                 qtd = priv->int_ints[slot].qtd;
1214                 qh = priv->int_ints[slot].qh;
1215
1216                 if (!qh) {
1217                         dev_err(hcd->self.controller, "(INT) qh is 0\n");
1218                         continue;
1219                 }
1220
1221                 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1222                 check_int_err_status(hcd, ptd.dw4);
1223
1224                 error = check_error(hcd, &ptd);
1225                 if (error) {
1226 #if 0
1227                         printk(KERN_ERR "Error in %s().\n", __func__);
1228                         printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1229                                         "dw3: %08x dw4: %08x dw5: %08x dw6: "
1230                                         "%08x dw7: %08x\n",
1231                                         ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1232                                         ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1233 #endif
1234                         qtd->urb->status = -EPIPE;
1235                         priv->int_ints[slot].qh->toggle = 0;
1236                         priv->int_ints[slot].qh->ping = 0;
1237
1238                 } else {
1239                         priv->int_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
1240                         priv->int_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
1241                 }
1242
1243                 if (qtd->urb->dev->speed != USB_SPEED_HIGH)
1244                         length = PTD_XFERRED_LENGTH_LO(ptd.dw3);
1245                 else
1246                         length = PTD_XFERRED_LENGTH(ptd.dw3);
1247
1248                 if (length) {
1249                         switch (DW1_GET_PID(ptd.dw1)) {
1250                         case IN_PID:
1251                                 mem_reads8(hcd->regs, qtd->payload_addr,
1252                                                 qtd->data_buffer, length);
1253                         case OUT_PID:
1254
1255                                 qtd->urb->actual_length += length;
1256
1257                         case SETUP_PID:
1258                                 break;
1259                         }
1260                 }
1261
1262                 priv->int_ints[slot].qtd = NULL;
1263                 priv->int_ints[slot].qh = NULL;
1264
1265                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1266                 free_mem(hcd, qtd);
1267
1268                 if (qtd->urb->status == -EPIPE) {
1269                         /* HALT received */
1270
1271                         urb = qtd->urb;
1272                         qtd = clean_up_qtdlist(qtd, qh);
1273                         isp1760_urb_done(hcd, urb);
1274
1275                 } else if (last_qtd_of_urb(qtd, qh)) {
1276
1277                         if (qtd->urb->status == -EINPROGRESS)
1278                                 qtd->urb->status = 0;
1279
1280                         urb = qtd->urb;
1281                         qtd = clean_up_qtdlist(qtd, qh);
1282                         isp1760_urb_done(hcd, urb);
1283
1284                 } else {
1285                         /* next QTD of this URB */
1286
1287                         qtd = clean_this_qtd(qtd, qh);
1288                         BUG_ON(!qtd);
1289                 }
1290
1291                 if (qtd)
1292                         enqueue_an_INT_packet(hcd, qh, qtd);
1293
1294                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1295         }
1296 }
1297
1298 static struct isp1760_qh *qh_make(struct usb_hcd *hcd, struct urb *urb,
1299                 gfp_t flags)
1300 {
1301         struct isp1760_qh *qh;
1302         int is_input, type;
1303
1304         qh = isp1760_qh_alloc(flags);
1305         if (!qh)
1306                 return qh;
1307
1308         /*
1309          * init endpoint/device data for this QH
1310          */
1311         is_input = usb_pipein(urb->pipe);
1312         type = usb_pipetype(urb->pipe);
1313
1314         if (!usb_pipecontrol(urb->pipe))
1315                 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1316                                 1);
1317         return qh;
1318 }
1319
1320 /*
1321  * For control/bulk/interrupt, return QH with these TDs appended.
1322  * Allocates and initializes the QH if necessary.
1323  * Returns null if it can't allocate a QH it needs to.
1324  * If the QH has TDs (urbs) already, that's great.
1325  */
1326 static struct isp1760_qh *qh_append_tds(struct usb_hcd *hcd,
1327                 struct urb *urb, struct list_head *qtd_list, int epnum,
1328                 void **ptr)
1329 {
1330         struct isp1760_qh *qh;
1331
1332         qh = (struct isp1760_qh *)*ptr;
1333         if (!qh) {
1334                 /* can't sleep here, we have priv->lock... */
1335                 qh = qh_make(hcd, urb, GFP_ATOMIC);
1336                 if (!qh)
1337                         return qh;
1338                 *ptr = qh;
1339         }
1340
1341         list_splice(qtd_list, qh->qtd_list.prev);
1342
1343         return qh;
1344 }
1345
1346 static void qtd_list_free(struct urb *urb, struct list_head *qtd_list)
1347 {
1348         struct list_head *entry, *temp;
1349
1350         list_for_each_safe(entry, temp, qtd_list) {
1351                 struct isp1760_qtd      *qtd;
1352
1353                 qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
1354                 list_del(&qtd->qtd_list);
1355                 isp1760_qtd_free(qtd);
1356         }
1357 }
1358
1359 static int isp1760_prepare_enqueue(struct usb_hcd *hcd, struct urb *urb,
1360                 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1361 {
1362         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1363         struct isp1760_qtd         *qtd;
1364         int                     epnum;
1365         unsigned long           flags;
1366         struct isp1760_qh          *qh = NULL;
1367         int                     rc;
1368         int qh_busy;
1369
1370         qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
1371         epnum = urb->ep->desc.bEndpointAddress;
1372
1373         spin_lock_irqsave(&priv->lock, flags);
1374         if (!HCD_HW_ACCESSIBLE(hcd)) {
1375                 rc = -ESHUTDOWN;
1376                 goto done;
1377         }
1378         rc = usb_hcd_link_urb_to_ep(hcd, urb);
1379         if (rc)
1380                 goto done;
1381
1382         qh = urb->ep->hcpriv;
1383         if (qh)
1384                 qh_busy = !list_empty(&qh->qtd_list);
1385         else
1386                 qh_busy = 0;
1387
1388         qh = qh_append_tds(hcd, urb, qtd_list, epnum, &urb->ep->hcpriv);
1389         if (!qh) {
1390                 usb_hcd_unlink_urb_from_ep(hcd, urb);
1391                 rc = -ENOMEM;
1392                 goto done;
1393         }
1394
1395         if (!qh_busy)
1396                 p(hcd, qh, qtd);
1397
1398 done:
1399         spin_unlock_irqrestore(&priv->lock, flags);
1400         if (!qh)
1401                 qtd_list_free(urb, qtd_list);
1402         return rc;
1403 }
1404
1405 static struct isp1760_qtd *isp1760_qtd_alloc(gfp_t flags)
1406 {
1407         struct isp1760_qtd *qtd;
1408
1409         qtd = kmem_cache_zalloc(qtd_cachep, flags);
1410         if (qtd)
1411                 INIT_LIST_HEAD(&qtd->qtd_list);
1412
1413         return qtd;
1414 }
1415
1416 /*
1417  * create a list of filled qtds for this URB; won't link into qh.
1418  */
1419 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1420 static struct list_head *qh_urb_transaction(struct usb_hcd *hcd,
1421                 struct urb *urb, struct list_head *head, gfp_t flags)
1422 {
1423         struct isp1760_qtd *qtd;
1424         void *buf;
1425         int len, maxpacket;
1426         int is_input;
1427         u32 token;
1428
1429         /*
1430          * URBs map to sequences of QTDs:  one logical transaction
1431          */
1432         qtd = isp1760_qtd_alloc(flags);
1433         if (!qtd)
1434                 return NULL;
1435
1436         list_add_tail(&qtd->qtd_list, head);
1437         qtd->urb = urb;
1438         urb->status = -EINPROGRESS;
1439
1440         token = 0;
1441         /* for split transactions, SplitXState initialized to zero */
1442
1443         len = urb->transfer_buffer_length;
1444         is_input = usb_pipein(urb->pipe);
1445         if (usb_pipecontrol(urb->pipe)) {
1446                 /* SETUP pid */
1447                 qtd_fill(qtd, urb->setup_packet,
1448                                 sizeof(struct usb_ctrlrequest),
1449                                 token | SETUP_PID);
1450
1451                 /* ... and always at least one more pid */
1452                 qtd = isp1760_qtd_alloc(flags);
1453                 if (!qtd)
1454                         goto cleanup;
1455                 qtd->urb = urb;
1456                 list_add_tail(&qtd->qtd_list, head);
1457
1458                 /* for zero length DATA stages, STATUS is always IN */
1459                 if (len == 0)
1460                         token |= IN_PID;
1461         }
1462
1463         /*
1464          * data transfer stage:  buffer setup
1465          */
1466         buf = urb->transfer_buffer;
1467
1468         if (is_input)
1469                 token |= IN_PID;
1470         else
1471                 token |= OUT_PID;
1472
1473         maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1474
1475         /*
1476          * buffer gets wrapped in one or more qtds;
1477          * last one may be "short" (including zero len)
1478          * and may serve as a control status ack
1479          */
1480         for (;;) {
1481                 int this_qtd_len;
1482
1483                 if (!buf && len) {
1484                         /* XXX This looks like usb storage / SCSI bug */
1485                         dev_err(hcd->self.controller, "buf is null, dma is %08lx len is %d\n",
1486                                         (long unsigned)urb->transfer_dma, len);
1487                         WARN_ON(1);
1488                 }
1489
1490                 this_qtd_len = qtd_fill(qtd, buf, len, token);
1491                 len -= this_qtd_len;
1492                 buf += this_qtd_len;
1493
1494                 if (len <= 0)
1495                         break;
1496
1497                 qtd = isp1760_qtd_alloc(flags);
1498                 if (!qtd)
1499                         goto cleanup;
1500                 qtd->urb = urb;
1501                 list_add_tail(&qtd->qtd_list, head);
1502         }
1503
1504         /*
1505          * control requests may need a terminating data "status" ack;
1506          * bulk ones may need a terminating short packet (zero length).
1507          */
1508         if (urb->transfer_buffer_length != 0) {
1509                 int one_more = 0;
1510
1511                 if (usb_pipecontrol(urb->pipe)) {
1512                         one_more = 1;
1513                         /* "in" <--> "out"  */
1514                         token ^= IN_PID;
1515                 } else if (usb_pipebulk(urb->pipe)
1516                                 && (urb->transfer_flags & URB_ZERO_PACKET)
1517                                 && !(urb->transfer_buffer_length % maxpacket)) {
1518                         one_more = 1;
1519                 }
1520                 if (one_more) {
1521                         qtd = isp1760_qtd_alloc(flags);
1522                         if (!qtd)
1523                                 goto cleanup;
1524                         qtd->urb = urb;
1525                         list_add_tail(&qtd->qtd_list, head);
1526
1527                         /* never any data in such packets */
1528                         qtd_fill(qtd, NULL, 0, token);
1529                 }
1530         }
1531
1532         qtd->status = 0;
1533         return head;
1534
1535 cleanup:
1536         qtd_list_free(urb, head);
1537         return NULL;
1538 }
1539
1540 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1541                 gfp_t mem_flags)
1542 {
1543         struct list_head qtd_list;
1544         packet_enqueue *pe;
1545
1546         INIT_LIST_HEAD(&qtd_list);
1547
1548         switch (usb_pipetype(urb->pipe)) {
1549         case PIPE_CONTROL:
1550         case PIPE_BULK:
1551                 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1552                         return -ENOMEM;
1553                 pe =  enqueue_an_ATL_packet;
1554                 break;
1555
1556         case PIPE_INTERRUPT:
1557                 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1558                         return -ENOMEM;
1559                 pe = enqueue_an_INT_packet;
1560                 break;
1561
1562         case PIPE_ISOCHRONOUS:
1563                 dev_err(hcd->self.controller, "PIPE_ISOCHRONOUS ain't supported\n");
1564         default:
1565                 return -EPIPE;
1566         }
1567
1568         return isp1760_prepare_enqueue(hcd, urb, &qtd_list, mem_flags, pe);
1569 }
1570
1571 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1572 {
1573         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1574         struct inter_packet_info *ints;
1575         u32 i;
1576         u32 reg_base, or_reg, skip_reg;
1577         unsigned long flags;
1578         struct ptd ptd;
1579         packet_enqueue *pe;
1580
1581         switch (usb_pipetype(urb->pipe)) {
1582         case PIPE_ISOCHRONOUS:
1583                 return -EPIPE;
1584                 break;
1585
1586         case PIPE_INTERRUPT:
1587                 ints = priv->int_ints;
1588                 reg_base = INT_PTD_OFFSET;
1589                 or_reg = HC_INT_IRQ_MASK_OR_REG;
1590                 skip_reg = HC_INT_PTD_SKIPMAP_REG;
1591                 pe = enqueue_an_INT_packet;
1592                 break;
1593
1594         default:
1595                 ints = priv->atl_ints;
1596                 reg_base = ATL_PTD_OFFSET;
1597                 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1598                 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
1599                 pe =  enqueue_an_ATL_packet;
1600                 break;
1601         }
1602
1603         memset(&ptd, 0, sizeof(ptd));
1604         spin_lock_irqsave(&priv->lock, flags);
1605
1606         for (i = 0; i < 32; i++) {
1607                 if (!ints[i].qh)
1608                         continue;
1609                 BUG_ON(!ints[i].qtd);
1610
1611                 if (ints[i].qtd->urb == urb) {
1612                         u32 skip_map;
1613                         u32 or_map;
1614                         struct isp1760_qtd *qtd;
1615                         struct isp1760_qh *qh;
1616
1617                         skip_map = reg_read32(hcd->regs, skip_reg);
1618                         skip_map |= 1 << i;
1619                         reg_write32(hcd->regs, skip_reg, skip_map);
1620
1621                         or_map = reg_read32(hcd->regs, or_reg);
1622                         or_map &= ~(1 << i);
1623                         reg_write32(hcd->regs, or_reg, or_map);
1624
1625                         ptd_write(hcd->regs, reg_base, i, &ptd);
1626
1627                         qtd = ints[i].qtd;
1628                         qh = ints[i].qh;
1629
1630                         free_mem(hcd, qtd);
1631                         qtd = clean_up_qtdlist(qtd, qh);
1632
1633                         ints[i].qh = NULL;
1634                         ints[i].qtd = NULL;
1635
1636                         isp1760_urb_done(hcd, urb);
1637                         if (qtd)
1638                                 pe(hcd, qh, qtd);
1639                         break;
1640
1641                 } else {
1642                         struct isp1760_qtd *qtd;
1643
1644                         list_for_each_entry(qtd, &ints[i].qtd->qtd_list,
1645                                                                 qtd_list) {
1646                                 if (qtd->urb == urb) {
1647                                         clean_up_qtdlist(qtd, ints[i].qh);
1648                                         isp1760_urb_done(hcd, urb);
1649                                         qtd = NULL;
1650                                         break;
1651                                 }
1652                         }
1653
1654                         /* We found the urb before the last slot */
1655                         if (!qtd)
1656                                 break;
1657                 }
1658         }
1659
1660         spin_unlock_irqrestore(&priv->lock, flags);
1661         return 0;
1662 }
1663
1664 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1665 {
1666         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1667         u32 imask;
1668         irqreturn_t irqret = IRQ_NONE;
1669
1670         spin_lock(&priv->lock);
1671
1672         if (!(hcd->state & HC_STATE_RUNNING))
1673                 goto leave;
1674
1675         imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1676         if (unlikely(!imask))
1677                 goto leave;
1678
1679         reg_write32(hcd->regs, HC_INTERRUPT_REG, imask);
1680         if (imask & (HC_ATL_INT | HC_SOT_INT))
1681                 do_atl_int(hcd);
1682
1683         if (imask & HC_INTL_INT)
1684                 do_intl_int(hcd);
1685
1686         irqret = IRQ_HANDLED;
1687 leave:
1688         spin_unlock(&priv->lock);
1689         return irqret;
1690 }
1691
1692 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1693 {
1694         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1695         u32 temp, status = 0;
1696         u32 mask;
1697         int retval = 1;
1698         unsigned long flags;
1699
1700         /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1701         if (!HC_IS_RUNNING(hcd->state))
1702                 return 0;
1703
1704         /* init status to no-changes */
1705         buf[0] = 0;
1706         mask = PORT_CSC;
1707
1708         spin_lock_irqsave(&priv->lock, flags);
1709         temp = reg_read32(hcd->regs, HC_PORTSC1);
1710
1711         if (temp & PORT_OWNER) {
1712                 if (temp & PORT_CSC) {
1713                         temp &= ~PORT_CSC;
1714                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1715                         goto done;
1716                 }
1717         }
1718
1719         /*
1720          * Return status information even for ports with OWNER set.
1721          * Otherwise khubd wouldn't see the disconnect event when a
1722          * high-speed device is switched over to the companion
1723          * controller by the user.
1724          */
1725
1726         if ((temp & mask) != 0
1727                         || ((temp & PORT_RESUME) != 0
1728                                 && time_after_eq(jiffies,
1729                                         priv->reset_done))) {
1730                 buf [0] |= 1 << (0 + 1);
1731                 status = STS_PCD;
1732         }
1733         /* FIXME autosuspend idle root hubs */
1734 done:
1735         spin_unlock_irqrestore(&priv->lock, flags);
1736         return status ? retval : 0;
1737 }
1738
1739 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1740                 struct usb_hub_descriptor *desc)
1741 {
1742         int ports = HCS_N_PORTS(priv->hcs_params);
1743         u16 temp;
1744
1745         desc->bDescriptorType = 0x29;
1746         /* priv 1.0, 2.3.9 says 20ms max */
1747         desc->bPwrOn2PwrGood = 10;
1748         desc->bHubContrCurrent = 0;
1749
1750         desc->bNbrPorts = ports;
1751         temp = 1 + (ports / 8);
1752         desc->bDescLength = 7 + 2 * temp;
1753
1754         /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1755         memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1756         memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1757
1758         /* per-port overcurrent reporting */
1759         temp = 0x0008;
1760         if (HCS_PPC(priv->hcs_params))
1761                 /* per-port power control */
1762                 temp |= 0x0001;
1763         else
1764                 /* no power switching */
1765                 temp |= 0x0002;
1766         desc->wHubCharacteristics = cpu_to_le16(temp);
1767 }
1768
1769 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1770
1771 static int check_reset_complete(struct usb_hcd *hcd, int index,
1772                 int port_status)
1773 {
1774         if (!(port_status & PORT_CONNECT))
1775                 return port_status;
1776
1777         /* if reset finished and it's still not enabled -- handoff */
1778         if (!(port_status & PORT_PE)) {
1779
1780                 dev_err(hcd->self.controller,
1781                                         "port %d full speed --> companion\n",
1782                                         index + 1);
1783
1784                 port_status |= PORT_OWNER;
1785                 port_status &= ~PORT_RWC_BITS;
1786                 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1787
1788         } else
1789                 dev_err(hcd->self.controller, "port %d high speed\n",
1790                                                                 index + 1);
1791
1792         return port_status;
1793 }
1794
1795 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1796                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1797 {
1798         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1799         int ports = HCS_N_PORTS(priv->hcs_params);
1800         u32 temp, status;
1801         unsigned long flags;
1802         int retval = 0;
1803         unsigned selector;
1804
1805         /*
1806          * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1807          * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1808          * (track current state ourselves) ... blink for diagnostics,
1809          * power, "this is the one", etc.  EHCI spec supports this.
1810          */
1811
1812         spin_lock_irqsave(&priv->lock, flags);
1813         switch (typeReq) {
1814         case ClearHubFeature:
1815                 switch (wValue) {
1816                 case C_HUB_LOCAL_POWER:
1817                 case C_HUB_OVER_CURRENT:
1818                         /* no hub-wide feature/status flags */
1819                         break;
1820                 default:
1821                         goto error;
1822                 }
1823                 break;
1824         case ClearPortFeature:
1825                 if (!wIndex || wIndex > ports)
1826                         goto error;
1827                 wIndex--;
1828                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1829
1830                 /*
1831                  * Even if OWNER is set, so the port is owned by the
1832                  * companion controller, khubd needs to be able to clear
1833                  * the port-change status bits (especially
1834                  * USB_PORT_STAT_C_CONNECTION).
1835                  */
1836
1837                 switch (wValue) {
1838                 case USB_PORT_FEAT_ENABLE:
1839                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1840                         break;
1841                 case USB_PORT_FEAT_C_ENABLE:
1842                         /* XXX error? */
1843                         break;
1844                 case USB_PORT_FEAT_SUSPEND:
1845                         if (temp & PORT_RESET)
1846                                 goto error;
1847
1848                         if (temp & PORT_SUSPEND) {
1849                                 if ((temp & PORT_PE) == 0)
1850                                         goto error;
1851                                 /* resume signaling for 20 msec */
1852                                 temp &= ~(PORT_RWC_BITS);
1853                                 reg_write32(hcd->regs, HC_PORTSC1,
1854                                                         temp | PORT_RESUME);
1855                                 priv->reset_done = jiffies +
1856                                         msecs_to_jiffies(20);
1857                         }
1858                         break;
1859                 case USB_PORT_FEAT_C_SUSPEND:
1860                         /* we auto-clear this feature */
1861                         break;
1862                 case USB_PORT_FEAT_POWER:
1863                         if (HCS_PPC(priv->hcs_params))
1864                                 reg_write32(hcd->regs, HC_PORTSC1,
1865                                                         temp & ~PORT_POWER);
1866                         break;
1867                 case USB_PORT_FEAT_C_CONNECTION:
1868                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1869                         break;
1870                 case USB_PORT_FEAT_C_OVER_CURRENT:
1871                         /* XXX error ?*/
1872                         break;
1873                 case USB_PORT_FEAT_C_RESET:
1874                         /* GetPortStatus clears reset */
1875                         break;
1876                 default:
1877                         goto error;
1878                 }
1879                 reg_read32(hcd->regs, HC_USBCMD);
1880                 break;
1881         case GetHubDescriptor:
1882                 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1883                         buf);
1884                 break;
1885         case GetHubStatus:
1886                 /* no hub-wide feature/status flags */
1887                 memset(buf, 0, 4);
1888                 break;
1889         case GetPortStatus:
1890                 if (!wIndex || wIndex > ports)
1891                         goto error;
1892                 wIndex--;
1893                 status = 0;
1894                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1895
1896                 /* wPortChange bits */
1897                 if (temp & PORT_CSC)
1898                         status |= USB_PORT_STAT_C_CONNECTION << 16;
1899
1900
1901                 /* whoever resumes must GetPortStatus to complete it!! */
1902                 if (temp & PORT_RESUME) {
1903                         dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1904
1905                         /* Remote Wakeup received? */
1906                         if (!priv->reset_done) {
1907                                 /* resume signaling for 20 msec */
1908                                 priv->reset_done = jiffies
1909                                                 + msecs_to_jiffies(20);
1910                                 /* check the port again */
1911                                 mod_timer(&hcd->rh_timer, priv->reset_done);
1912                         }
1913
1914                         /* resume completed? */
1915                         else if (time_after_eq(jiffies,
1916                                         priv->reset_done)) {
1917                                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1918                                 priv->reset_done = 0;
1919
1920                                 /* stop resume signaling */
1921                                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1922                                 reg_write32(hcd->regs, HC_PORTSC1,
1923                                         temp & ~(PORT_RWC_BITS | PORT_RESUME));
1924                                 retval = handshake(hcd, HC_PORTSC1,
1925                                            PORT_RESUME, 0, 2000 /* 2msec */);
1926                                 if (retval != 0) {
1927                                         dev_err(hcd->self.controller,
1928                                                 "port %d resume error %d\n",
1929                                                 wIndex + 1, retval);
1930                                         goto error;
1931                                 }
1932                                 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1933                         }
1934                 }
1935
1936                 /* whoever resets must GetPortStatus to complete it!! */
1937                 if ((temp & PORT_RESET)
1938                                 && time_after_eq(jiffies,
1939                                         priv->reset_done)) {
1940                         status |= USB_PORT_STAT_C_RESET << 16;
1941                         priv->reset_done = 0;
1942
1943                         /* force reset to complete */
1944                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1945                         /* REVISIT:  some hardware needs 550+ usec to clear
1946                          * this bit; seems too long to spin routinely...
1947                          */
1948                         retval = handshake(hcd, HC_PORTSC1,
1949                                         PORT_RESET, 0, 750);
1950                         if (retval != 0) {
1951                                 dev_err(hcd->self.controller, "port %d reset error %d\n",
1952                                                 wIndex + 1, retval);
1953                                 goto error;
1954                         }
1955
1956                         /* see what we found out */
1957                         temp = check_reset_complete(hcd, wIndex,
1958                                         reg_read32(hcd->regs, HC_PORTSC1));
1959                 }
1960                 /*
1961                  * Even if OWNER is set, there's no harm letting khubd
1962                  * see the wPortStatus values (they should all be 0 except
1963                  * for PORT_POWER anyway).
1964                  */
1965
1966                 if (temp & PORT_OWNER)
1967                         dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1968
1969                 if (temp & PORT_CONNECT) {
1970                         status |= USB_PORT_STAT_CONNECTION;
1971                         /* status may be from integrated TT */
1972                         status |= USB_PORT_STAT_HIGH_SPEED;
1973                 }
1974                 if (temp & PORT_PE)
1975                         status |= USB_PORT_STAT_ENABLE;
1976                 if (temp & (PORT_SUSPEND|PORT_RESUME))
1977                         status |= USB_PORT_STAT_SUSPEND;
1978                 if (temp & PORT_RESET)
1979                         status |= USB_PORT_STAT_RESET;
1980                 if (temp & PORT_POWER)
1981                         status |= USB_PORT_STAT_POWER;
1982
1983                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1984                 break;
1985         case SetHubFeature:
1986                 switch (wValue) {
1987                 case C_HUB_LOCAL_POWER:
1988                 case C_HUB_OVER_CURRENT:
1989                         /* no hub-wide feature/status flags */
1990                         break;
1991                 default:
1992                         goto error;
1993                 }
1994                 break;
1995         case SetPortFeature:
1996                 selector = wIndex >> 8;
1997                 wIndex &= 0xff;
1998                 if (!wIndex || wIndex > ports)
1999                         goto error;
2000                 wIndex--;
2001                 temp = reg_read32(hcd->regs, HC_PORTSC1);
2002                 if (temp & PORT_OWNER)
2003                         break;
2004
2005 /*              temp &= ~PORT_RWC_BITS; */
2006                 switch (wValue) {
2007                 case USB_PORT_FEAT_ENABLE:
2008                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2009                         break;
2010
2011                 case USB_PORT_FEAT_SUSPEND:
2012                         if ((temp & PORT_PE) == 0
2013                                         || (temp & PORT_RESET) != 0)
2014                                 goto error;
2015
2016                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2017                         break;
2018                 case USB_PORT_FEAT_POWER:
2019                         if (HCS_PPC(priv->hcs_params))
2020                                 reg_write32(hcd->regs, HC_PORTSC1,
2021                                                         temp | PORT_POWER);
2022                         break;
2023                 case USB_PORT_FEAT_RESET:
2024                         if (temp & PORT_RESUME)
2025                                 goto error;
2026                         /* line status bits may report this as low speed,
2027                          * which can be fine if this root hub has a
2028                          * transaction translator built in.
2029                          */
2030                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2031                                         && PORT_USB11(temp)) {
2032                                 temp |= PORT_OWNER;
2033                         } else {
2034                                 temp |= PORT_RESET;
2035                                 temp &= ~PORT_PE;
2036
2037                                 /*
2038                                  * caller must wait, then call GetPortStatus
2039                                  * usb 2.0 spec says 50 ms resets on root
2040                                  */
2041                                 priv->reset_done = jiffies +
2042                                         msecs_to_jiffies(50);
2043                         }
2044                         reg_write32(hcd->regs, HC_PORTSC1, temp);
2045                         break;
2046                 default:
2047                         goto error;
2048                 }
2049                 reg_read32(hcd->regs, HC_USBCMD);
2050                 break;
2051
2052         default:
2053 error:
2054                 /* "stall" on error */
2055                 retval = -EPIPE;
2056         }
2057         spin_unlock_irqrestore(&priv->lock, flags);
2058         return retval;
2059 }
2060
2061 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
2062                 struct usb_host_endpoint *ep)
2063 {
2064         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2065         struct isp1760_qh *qh;
2066         struct isp1760_qtd *qtd;
2067         unsigned long flags;
2068
2069         spin_lock_irqsave(&priv->lock, flags);
2070         qh = ep->hcpriv;
2071         if (!qh)
2072                 goto out;
2073
2074         ep->hcpriv = NULL;
2075         do {
2076                 /* more than entry might get removed */
2077                 if (list_empty(&qh->qtd_list))
2078                         break;
2079
2080                 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
2081                                 qtd_list);
2082
2083                 if (qtd->status & URB_ENQUEUED) {
2084                         spin_unlock_irqrestore(&priv->lock, flags);
2085                         isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET);
2086                         spin_lock_irqsave(&priv->lock, flags);
2087                 } else {
2088                         struct urb *urb;
2089
2090                         urb = qtd->urb;
2091                         clean_up_qtdlist(qtd, qh);
2092                         urb->status = -ECONNRESET;
2093                         isp1760_urb_done(hcd, urb);
2094                 }
2095         } while (1);
2096
2097         qh_destroy(qh);
2098         /* remove requests and leak them.
2099          * ATL are pretty fast done, INT could take a while...
2100          * The latter shoule be removed
2101          */
2102 out:
2103         spin_unlock_irqrestore(&priv->lock, flags);
2104 }
2105
2106 static int isp1760_get_frame(struct usb_hcd *hcd)
2107 {
2108         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2109         u32 fr;
2110
2111         fr = reg_read32(hcd->regs, HC_FRINDEX);
2112         return (fr >> 3) % priv->periodic_size;
2113 }
2114
2115 static void isp1760_stop(struct usb_hcd *hcd)
2116 {
2117         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2118         u32 temp;
2119
2120         isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2121                         NULL, 0);
2122         mdelay(20);
2123
2124         spin_lock_irq(&priv->lock);
2125         ehci_reset(hcd);
2126         /* Disable IRQ */
2127         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2128         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2129         spin_unlock_irq(&priv->lock);
2130
2131         reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2132 }
2133
2134 static void isp1760_shutdown(struct usb_hcd *hcd)
2135 {
2136         u32 command, temp;
2137
2138         isp1760_stop(hcd);
2139         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2140         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2141
2142         command = reg_read32(hcd->regs, HC_USBCMD);
2143         command &= ~CMD_RUN;
2144         reg_write32(hcd->regs, HC_USBCMD, command);
2145 }
2146
2147 static const struct hc_driver isp1760_hc_driver = {
2148         .description            = "isp1760-hcd",
2149         .product_desc           = "NXP ISP1760 USB Host Controller",
2150         .hcd_priv_size          = sizeof(struct isp1760_hcd),
2151         .irq                    = isp1760_irq,
2152         .flags                  = HCD_MEMORY | HCD_USB2,
2153         .reset                  = isp1760_hc_setup,
2154         .start                  = isp1760_run,
2155         .stop                   = isp1760_stop,
2156         .shutdown               = isp1760_shutdown,
2157         .urb_enqueue            = isp1760_urb_enqueue,
2158         .urb_dequeue            = isp1760_urb_dequeue,
2159         .endpoint_disable       = isp1760_endpoint_disable,
2160         .get_frame_number       = isp1760_get_frame,
2161         .hub_status_data        = isp1760_hub_status_data,
2162         .hub_control            = isp1760_hub_control,
2163 };
2164
2165 int __init init_kmem_once(void)
2166 {
2167         qtd_cachep = kmem_cache_create("isp1760_qtd",
2168                         sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2169                         SLAB_MEM_SPREAD, NULL);
2170
2171         if (!qtd_cachep)
2172                 return -ENOMEM;
2173
2174         qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2175                         0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2176
2177         if (!qh_cachep) {
2178                 kmem_cache_destroy(qtd_cachep);
2179                 return -ENOMEM;
2180         }
2181
2182         return 0;
2183 }
2184
2185 void deinit_kmem_cache(void)
2186 {
2187         kmem_cache_destroy(qtd_cachep);
2188         kmem_cache_destroy(qh_cachep);
2189 }
2190
2191 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2192                                  int irq, unsigned long irqflags,
2193                                  struct device *dev, const char *busname,
2194                                  unsigned int devflags)
2195 {
2196         struct usb_hcd *hcd;
2197         struct isp1760_hcd *priv;
2198         int ret;
2199
2200         if (usb_disabled())
2201                 return ERR_PTR(-ENODEV);
2202
2203         /* prevent usb-core allocating DMA pages */
2204         dev->dma_mask = NULL;
2205
2206         hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2207         if (!hcd)
2208                 return ERR_PTR(-ENOMEM);
2209
2210         priv = hcd_to_priv(hcd);
2211         priv->devflags = devflags;
2212         init_memory(priv);
2213         hcd->regs = ioremap(res_start, res_len);
2214         if (!hcd->regs) {
2215                 ret = -EIO;
2216                 goto err_put;
2217         }
2218
2219         hcd->irq = irq;
2220         hcd->rsrc_start = res_start;
2221         hcd->rsrc_len = res_len;
2222
2223         ret = usb_add_hcd(hcd, irq, irqflags);
2224         if (ret)
2225                 goto err_unmap;
2226
2227         return hcd;
2228
2229 err_unmap:
2230          iounmap(hcd->regs);
2231
2232 err_put:
2233          usb_put_hcd(hcd);
2234
2235          return ERR_PTR(ret);
2236 }
2237
2238 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2239 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2240 MODULE_LICENSE("GPL v2");