drivers/usb/host/ehci-sched.c

   1 /*
   2  * Copyright (c) 2001-2004 by David Brownell
   3  * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /* this file is part of ehci-hcd.c */
  21
  22 /*-------------------------------------------------------------------------*/
  23
  24 /*
  25  * EHCI scheduled transaction support:  interrupt, iso, split iso
  26  * These are called "periodic" transactions in the EHCI spec.
  27  *
  28  * Note that for interrupt transfers, the QH/QTD manipulation is shared
  29  * with the "asynchronous" transaction support (control/bulk transfers).
  30  * The only real difference is in how interrupt transfers are scheduled.
  31  *
  32  * For ISO, we make an "iso_stream" head to serve the same role as a QH.
  33  * It keeps track of every ITD (or SITD) that's linked, and holds enough
  34  * pre-calculated schedule data to make appending to the queue be quick.
  35  */
  36
  37 static int ehci_get_frame (struct usb_hcd *hcd);
  38
  39 /*-------------------------------------------------------------------------*/
  40
  41 /*
  42  * periodic_next_shadow - return "next" pointer on shadow list
  43  * @periodic: host pointer to qh/itd/sitd
  44  * @tag: hardware tag for type of this record
  45  */
  46 static union ehci_shadow *
  47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
  48                 __hc32 tag)
  49 {
  50         switch (hc32_to_cpu(ehci, tag)) {
  51         case Q_TYPE_QH:
  52                 return &periodic->qh->qh_next;
  53         case Q_TYPE_FSTN:
  54                 return &periodic->fstn->fstn_next;
  55         case Q_TYPE_ITD:
  56                 return &periodic->itd->itd_next;
  57         // case Q_TYPE_SITD:
  58         default:
  59                 return &periodic->sitd->sitd_next;
  60         }
  61 }
  62
  63 /* caller must hold ehci->lock */
  64 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
  65 {
  66         union ehci_shadow       *prev_p = &ehci->pshadow[frame];
  67         __hc32                  *hw_p = &ehci->periodic[frame];
  68         union ehci_shadow       here = *prev_p;
  69
  70         /* find predecessor of "ptr"; hw and shadow lists are in sync */
  71         while (here.ptr && here.ptr != ptr) {
  72                 prev_p = periodic_next_shadow(ehci, prev_p,
  73                                 Q_NEXT_TYPE(ehci, *hw_p));
  74                 hw_p = here.hw_next;
  75                 here = *prev_p;
  76         }
  77         /* an interrupt entry (at list end) could have been shared */
  78         if (!here.ptr)
  79                 return;
  80
  81         /* update shadow and hardware lists ... the old "next" pointers
  82          * from ptr may still be in use, the caller updates them.
  83          */
  84         *prev_p = *periodic_next_shadow(ehci, &here,
  85                         Q_NEXT_TYPE(ehci, *hw_p));
  86         *hw_p = *here.hw_next;
  87 }
  88
  89 /* how many of the uframe's 125 usecs are allocated? */
  90 static unsigned short
  91 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
  92 {
  93         __hc32                  *hw_p = &ehci->periodic [frame];
  94         union ehci_shadow       *q = &ehci->pshadow [frame];
  95         unsigned                usecs = 0;
  96
  97         while (q->ptr) {
  98                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
  99                 case Q_TYPE_QH:
 100                         /* is it in the S-mask? */
 101                         if (q->qh->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
 102                                 usecs += q->qh->usecs;
 103                         /* ... or C-mask? */
 104                         if (q->qh->hw_info2 & cpu_to_hc32(ehci,
 105                                         1 << (8 + uframe)))
 106                                 usecs += q->qh->c_usecs;
 107                         hw_p = &q->qh->hw_next;
 108                         q = &q->qh->qh_next;
 109                         break;
 110                 // case Q_TYPE_FSTN:
 111                 default:
 112                         /* for "save place" FSTNs, count the relevant INTR
 113                          * bandwidth from the previous frame
 114                          */
 115                         if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
 116                                 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
 117                         }
 118                         hw_p = &q->fstn->hw_next;
 119                         q = &q->fstn->fstn_next;
 120                         break;
 121                 case Q_TYPE_ITD:
 122                         if (q->itd->hw_transaction[uframe])
 123                                 usecs += q->itd->stream->usecs;
 124                         hw_p = &q->itd->hw_next;
 125                         q = &q->itd->itd_next;
 126                         break;
 127                 case Q_TYPE_SITD:
 128                         /* is it in the S-mask?  (count SPLIT, DATA) */
 129                         if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
 130                                         1 << uframe)) {
 131                                 if (q->sitd->hw_fullspeed_ep &
 132                                                 cpu_to_hc32(ehci, 1<<31))
 133                                         usecs += q->sitd->stream->usecs;
 134                                 else    /* worst case for OUT start-split */
 135                                         usecs += HS_USECS_ISO (188);
 136                         }
 137
 138                         /* ... C-mask?  (count CSPLIT, DATA) */
 139                         if (q->sitd->hw_uframe &
 140                                         cpu_to_hc32(ehci, 1 << (8 + uframe))) {
 141                                 /* worst case for IN complete-split */
 142                                 usecs += q->sitd->stream->c_usecs;
 143                         }
 144
 145                         hw_p = &q->sitd->hw_next;
 146                         q = &q->sitd->sitd_next;
 147                         break;
 148                 }
 149         }
 150 #ifdef  DEBUG
 151         if (usecs > 100)
 152                 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
 153                         frame * 8 + uframe, usecs);
 154 #endif
 155         return usecs;
 156 }
 157
 158 /*-------------------------------------------------------------------------*/
 159
 160 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
 161 {
 162         if (!dev1->tt || !dev2->tt)
 163                 return 0;
 164         if (dev1->tt != dev2->tt)
 165                 return 0;
 166         if (dev1->tt->multi)
 167                 return dev1->ttport == dev2->ttport;
 168         else
 169                 return 1;
 170 }
 171
 172 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
 173
 174 /* Which uframe does the low/fullspeed transfer start in?
 175  *
 176  * The parameter is the mask of ssplits in "H-frame" terms
 177  * and this returns the transfer start uframe in "B-frame" terms,
 178  * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
 179  * will cause a transfer in "B-frame" uframe 0.  "B-frames" lag
 180  * "H-frames" by 1 uframe.  See the EHCI spec sec 4.5 and figure 4.7.
 181  */
 182 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
 183 {
 184         unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
 185         if (!smask) {
 186                 ehci_err(ehci, "invalid empty smask!\n");
 187                 /* uframe 7 can't have bw so this will indicate failure */
 188                 return 7;
 189         }
 190         return ffs(smask) - 1;
 191 }
 192
 193 static const unsigned char
 194 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
 195
 196 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
 197 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
 198 {
 199         int i;
 200         for (i=0; i<7; i++) {
 201                 if (max_tt_usecs[i] < tt_usecs[i]) {
 202                         tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
 203                         tt_usecs[i] = max_tt_usecs[i];
 204                 }
 205         }
 206 }
 207
 208 /* How many of the tt's periodic downstream 1000 usecs are allocated?
 209  *
 210  * While this measures the bandwidth in terms of usecs/uframe,
 211  * the low/fullspeed bus has no notion of uframes, so any particular
 212  * low/fullspeed transfer can "carry over" from one uframe to the next,
 213  * since the TT just performs downstream transfers in sequence.
 214  *
 215  * For example two separate 100 usec transfers can start in the same uframe,
 216  * and the second one would "carry over" 75 usecs into the next uframe.
 217  */
 218 static void
 219 periodic_tt_usecs (
 220         struct ehci_hcd *ehci,
 221         struct usb_device *dev,
 222         unsigned frame,
 223         unsigned short tt_usecs[8]
 224 )
 225 {
 226         __hc32                  *hw_p = &ehci->periodic [frame];
 227         union ehci_shadow       *q = &ehci->pshadow [frame];
 228         unsigned char           uf;
 229
 230         memset(tt_usecs, 0, 16);
 231
 232         while (q->ptr) {
 233                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
 234                 case Q_TYPE_ITD:
 235                         hw_p = &q->itd->hw_next;
 236                         q = &q->itd->itd_next;
 237                         continue;
 238                 case Q_TYPE_QH:
 239                         if (same_tt(dev, q->qh->dev)) {
 240                                 uf = tt_start_uframe(ehci, q->qh->hw_info2);
 241                                 tt_usecs[uf] += q->qh->tt_usecs;
 242                         }
 243                         hw_p = &q->qh->hw_next;
 244                         q = &q->qh->qh_next;
 245                         continue;
 246                 case Q_TYPE_SITD:
 247                         if (same_tt(dev, q->sitd->urb->dev)) {
 248                                 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
 249                                 tt_usecs[uf] += q->sitd->stream->tt_usecs;
 250                         }
 251                         hw_p = &q->sitd->hw_next;
 252                         q = &q->sitd->sitd_next;
 253                         continue;
 254                 // case Q_TYPE_FSTN:
 255                 default:
 256                         ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
 257                                         frame);
 258                         hw_p = &q->fstn->hw_next;
 259                         q = &q->fstn->fstn_next;
 260                 }
 261         }
 262
 263         carryover_tt_bandwidth(tt_usecs);
 264
 265         if (max_tt_usecs[7] < tt_usecs[7])
 266                 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
 267                         frame, tt_usecs[7] - max_tt_usecs[7]);
 268 }
 269
 270 /*
 271  * Return true if the device's tt's downstream bus is available for a
 272  * periodic transfer of the specified length (usecs), starting at the
 273  * specified frame/uframe.  Note that (as summarized in section 11.19
 274  * of the usb 2.0 spec) TTs can buffer multiple transactions for each
 275  * uframe.
 276  *
 277  * The uframe parameter is when the fullspeed/lowspeed transfer
 278  * should be executed in "B-frame" terms, which is the same as the
 279  * highspeed ssplit's uframe (which is in "H-frame" terms).  For example
 280  * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
 281  * See the EHCI spec sec 4.5 and fig 4.7.
 282  *
 283  * This checks if the full/lowspeed bus, at the specified starting uframe,
 284  * has the specified bandwidth available, according to rules listed
 285  * in USB 2.0 spec section 11.18.1 fig 11-60.
 286  *
 287  * This does not check if the transfer would exceed the max ssplit
 288  * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
 289  * since proper scheduling limits ssplits to less than 16 per uframe.
 290  */
 291 static int tt_available (
 292         struct ehci_hcd         *ehci,
 293         unsigned                period,
 294         struct usb_device       *dev,
 295         unsigned                frame,
 296         unsigned                uframe,
 297         u16                     usecs
 298 )
 299 {
 300         if ((period == 0) || (uframe >= 7))     /* error */
 301                 return 0;
 302
 303         for (; frame < ehci->periodic_size; frame += period) {
 304                 unsigned short tt_usecs[8];
 305
 306                 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
 307
 308                 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
 309                         " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
 310                         frame, usecs, uframe,
 311                         tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
 312                         tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
 313
 314                 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
 315                         ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
 316                                 frame, uframe);
 317                         return 0;
 318                 }
 319
 320                 /* special case for isoc transfers larger than 125us:
 321                  * the first and each subsequent fully used uframe
 322                  * must be empty, so as to not illegally delay
 323                  * already scheduled transactions
 324                  */
 325                 if (125 < usecs) {
 326                         int ufs = (usecs / 125);
 327                         int i;
 328                         for (i = uframe; i < (uframe + ufs) && i < 8; i++)
 329                                 if (0 < tt_usecs[i]) {
 330                                         ehci_vdbg(ehci,
 331                                                 "multi-uframe xfer can't fit "
 332                                                 "in frame %d uframe %d\n",
 333                                                 frame, i);
 334                                         return 0;
 335                                 }
 336                 }
 337
 338                 tt_usecs[uframe] += usecs;
 339
 340                 carryover_tt_bandwidth(tt_usecs);
 341
 342                 /* fail if the carryover pushed bw past the last uframe's limit */
 343                 if (max_tt_usecs[7] < tt_usecs[7]) {
 344                         ehci_vdbg(ehci,
 345                                 "tt unavailable usecs %d frame %d uframe %d\n",
 346                                 usecs, frame, uframe);
 347                         return 0;
 348                 }
 349         }
 350
 351         return 1;
 352 }
 353
 354 #else
 355
 356 /* return true iff the device's transaction translator is available
 357  * for a periodic transfer starting at the specified frame, using
 358  * all the uframes in the mask.
 359  */
 360 static int tt_no_collision (
 361         struct ehci_hcd         *ehci,
 362         unsigned                period,
 363         struct usb_device       *dev,
 364         unsigned                frame,
 365         u32                     uf_mask
 366 )
 367 {
 368         if (period == 0)        /* error */
 369                 return 0;
 370
 371         /* note bandwidth wastage:  split never follows csplit
 372          * (different dev or endpoint) until the next uframe.
 373          * calling convention doesn't make that distinction.
 374          */
 375         for (; frame < ehci->periodic_size; frame += period) {
 376                 union ehci_shadow       here;
 377                 __hc32                  type;
 378
 379                 here = ehci->pshadow [frame];
 380                 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
 381                 while (here.ptr) {
 382                         switch (hc32_to_cpu(ehci, type)) {
 383                         case Q_TYPE_ITD:
 384                                 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
 385                                 here = here.itd->itd_next;
 386                                 continue;
 387                         case Q_TYPE_QH:
 388                                 if (same_tt (dev, here.qh->dev)) {
 389                                         u32             mask;
 390
 391                                         mask = hc32_to_cpu(ehci,
 392                                                         here.qh->hw_info2);
 393                                         /* "knows" no gap is needed */
 394                                         mask |= mask >> 8;
 395                                         if (mask & uf_mask)
 396                                                 break;
 397                                 }
 398                                 type = Q_NEXT_TYPE(ehci, here.qh->hw_next);
 399                                 here = here.qh->qh_next;
 400                                 continue;
 401                         case Q_TYPE_SITD:
 402                                 if (same_tt (dev, here.sitd->urb->dev)) {
 403                                         u16             mask;
 404
 405                                         mask = hc32_to_cpu(ehci, here.sitd
 406                                                                 ->hw_uframe);
 407                                         /* FIXME assumes no gap for IN! */
 408                                         mask |= mask >> 8;
 409                                         if (mask & uf_mask)
 410                                                 break;
 411                                 }
 412                                 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
 413                                 here = here.sitd->sitd_next;
 414                                 continue;
 415                         // case Q_TYPE_FSTN:
 416                         default:
 417                                 ehci_dbg (ehci,
 418                                         "periodic frame %d bogus type %d\n",
 419                                         frame, type);
 420                         }
 421
 422                         /* collision or error */
 423                         return 0;
 424                 }
 425         }
 426
 427         /* no collision */
 428         return 1;
 429 }
 430
 431 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
 432
 433 /*-------------------------------------------------------------------------*/
 434
 435 static int enable_periodic (struct ehci_hcd *ehci)
 436 {
 437         u32     cmd;
 438         int     status;
 439
 440         if (ehci->periodic_sched++)
 441                 return 0;
 442
 443         /* did clearing PSE did take effect yet?
 444          * takes effect only at frame boundaries...
 445          */
 446         status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
 447                                              STS_PSS, 0, 9 * 125);
 448         if (status)
 449                 return status;
 450
 451         cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
 452         ehci_writel(ehci, cmd, &ehci->regs->command);
 453         /* posted write ... PSS happens later */
 454         ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
 455
 456         /* make sure ehci_work scans these */
 457         ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
 458                 % (ehci->periodic_size << 3);
 459         return 0;
 460 }
 461
 462 static int disable_periodic (struct ehci_hcd *ehci)
 463 {
 464         u32     cmd;
 465         int     status;
 466
 467         if (--ehci->periodic_sched)
 468                 return 0;
 469
 470         /* did setting PSE not take effect yet?
 471          * takes effect only at frame boundaries...
 472          */
 473         status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
 474                                              STS_PSS, STS_PSS, 9 * 125);
 475         if (status)
 476                 return status;
 477
 478         cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
 479         ehci_writel(ehci, cmd, &ehci->regs->command);
 480         /* posted write ... */
 481
 482         ehci->next_uframe = -1;
 483         return 0;
 484 }
 485
 486 /*-------------------------------------------------------------------------*/
 487
 488 /* periodic schedule slots have iso tds (normal or split) first, then a
 489  * sparse tree for active interrupt transfers.
 490  *
 491  * this just links in a qh; caller guarantees uframe masks are set right.
 492  * no FSTN support (yet; ehci 0.96+)
 493  */
 494 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 495 {
 496         unsigned        i;
 497         unsigned        period = qh->period;
 498
 499         dev_dbg (&qh->dev->dev,
 500                 "link qh%d-%04x/%p start %d [%d/%d us]\n",
 501                 period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
 502                 qh, qh->start, qh->usecs, qh->c_usecs);
 503
 504         /* high bandwidth, or otherwise every microframe */
 505         if (period == 0)
 506                 period = 1;
 507
 508         for (i = qh->start; i < ehci->periodic_size; i += period) {
 509                 union ehci_shadow       *prev = &ehci->pshadow[i];
 510                 __hc32                  *hw_p = &ehci->periodic[i];
 511                 union ehci_shadow       here = *prev;
 512                 __hc32                  type = 0;
 513
 514                 /* skip the iso nodes at list head */
 515                 while (here.ptr) {
 516                         type = Q_NEXT_TYPE(ehci, *hw_p);
 517                         if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
 518                                 break;
 519                         prev = periodic_next_shadow(ehci, prev, type);
 520                         hw_p = &here.qh->hw_next;
 521                         here = *prev;
 522                 }
 523
 524                 /* sorting each branch by period (slow-->fast)
 525                  * enables sharing interior tree nodes
 526                  */
 527                 while (here.ptr && qh != here.qh) {
 528                         if (qh->period > here.qh->period)
 529                                 break;
 530                         prev = &here.qh->qh_next;
 531                         hw_p = &here.qh->hw_next;
 532                         here = *prev;
 533                 }
 534                 /* link in this qh, unless some earlier pass did that */
 535                 if (qh != here.qh) {
 536                         qh->qh_next = here;
 537                         if (here.qh)
 538                                 qh->hw_next = *hw_p;
 539                         wmb ();
 540                         prev->qh = qh;
 541                         *hw_p = QH_NEXT (ehci, qh->qh_dma);
 542                 }
 543         }
 544         qh->qh_state = QH_STATE_LINKED;
 545         qh->xacterrs = 0;
 546         qh_get (qh);
 547
 548         /* update per-qh bandwidth for usbfs */
 549         ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
 550                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 551                 : (qh->usecs * 8);
 552
 553         /* maybe enable periodic schedule processing */
 554         return enable_periodic(ehci);
 555 }
 556
 557 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
 558 {
 559         unsigned        i;
 560         unsigned        period;
 561
 562         // FIXME:
 563         // IF this isn't high speed
 564         //   and this qh is active in the current uframe
 565         //   (and overlay token SplitXstate is false?)
 566         // THEN
 567         //   qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
 568
 569         /* high bandwidth, or otherwise part of every microframe */
 570         if ((period = qh->period) == 0)
 571                 period = 1;
 572
 573         for (i = qh->start; i < ehci->periodic_size; i += period)
 574                 periodic_unlink (ehci, i, qh);
 575
 576         /* update per-qh bandwidth for usbfs */
 577         ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
 578                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 579                 : (qh->usecs * 8);
 580
 581         dev_dbg (&qh->dev->dev,
 582                 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
 583                 qh->period,
 584                 hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
 585                 qh, qh->start, qh->usecs, qh->c_usecs);
 586
 587         /* qh->qh_next still "live" to HC */
 588         qh->qh_state = QH_STATE_UNLINK;
 589         qh->qh_next.ptr = NULL;
 590         qh_put (qh);
 591
 592         /* maybe turn off periodic schedule */
 593         return disable_periodic(ehci);
 594 }
 595
 596 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 597 {
 598         unsigned        wait;
 599
 600         qh_unlink_periodic (ehci, qh);
 601
 602         /* simple/paranoid:  always delay, expecting the HC needs to read
 603          * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
 604          * expect khubd to clean up after any CSPLITs we won't issue.
 605          * active high speed queues may need bigger delays...
 606          */
 607         if (list_empty (&qh->qtd_list)
 608                         || (cpu_to_hc32(ehci, QH_CMASK)
 609                                         & qh->hw_info2) != 0)
 610                 wait = 2;
 611         else
 612                 wait = 55;      /* worst case: 3 * 1024 */
 613
 614         udelay (wait);
 615         qh->qh_state = QH_STATE_IDLE;
 616         qh->hw_next = EHCI_LIST_END(ehci);
 617         wmb ();
 618 }
 619
 620 /*-------------------------------------------------------------------------*/
 621
 622 static int check_period (
 623         struct ehci_hcd *ehci,
 624         unsigned        frame,
 625         unsigned        uframe,
 626         unsigned        period,
 627         unsigned        usecs
 628 ) {
 629         int             claimed;
 630
 631         /* complete split running into next frame?
 632          * given FSTN support, we could sometimes check...
 633          */
 634         if (uframe >= 8)
 635                 return 0;
 636
 637         /*
 638          * 80% periodic == 100 usec/uframe available
 639          * convert "usecs we need" to "max already claimed"
 640          */
 641         usecs = 100 - usecs;
 642
 643         /* we "know" 2 and 4 uframe intervals were rejected; so
 644          * for period 0, check _every_ microframe in the schedule.
 645          */
 646         if (unlikely (period == 0)) {
 647                 do {
 648                         for (uframe = 0; uframe < 7; uframe++) {
 649                                 claimed = periodic_usecs (ehci, frame, uframe);
 650                                 if (claimed > usecs)
 651                                         return 0;
 652                         }
 653                 } while ((frame += 1) < ehci->periodic_size);
 654
 655         /* just check the specified uframe, at that period */
 656         } else {
 657                 do {
 658                         claimed = periodic_usecs (ehci, frame, uframe);
 659                         if (claimed > usecs)
 660                                 return 0;
 661                 } while ((frame += period) < ehci->periodic_size);
 662         }
 663
 664         // success!
 665         return 1;
 666 }
 667
 668 static int check_intr_schedule (
 669         struct ehci_hcd         *ehci,
 670         unsigned                frame,
 671         unsigned                uframe,
 672         const struct ehci_qh    *qh,
 673         __hc32                  *c_maskp
 674 )
 675 {
 676         int             retval = -ENOSPC;
 677         u8              mask = 0;
 678
 679         if (qh->c_usecs && uframe >= 6)         /* FSTN territory? */
 680                 goto done;
 681
 682         if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
 683                 goto done;
 684         if (!qh->c_usecs) {
 685                 retval = 0;
 686                 *c_maskp = 0;
 687                 goto done;
 688         }
 689
 690 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
 691         if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
 692                                 qh->tt_usecs)) {
 693                 unsigned i;
 694
 695                 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
 696                 for (i=uframe+1; i<8 && i<uframe+4; i++)
 697                         if (!check_period (ehci, frame, i,
 698                                                 qh->period, qh->c_usecs))
 699                                 goto done;
 700                         else
 701                                 mask |= 1 << i;
 702
 703                 retval = 0;
 704
 705                 *c_maskp = cpu_to_hc32(ehci, mask << 8);
 706         }
 707 #else
 708         /* Make sure this tt's buffer is also available for CSPLITs.
 709          * We pessimize a bit; probably the typical full speed case
 710          * doesn't need the second CSPLIT.
 711          *
 712          * NOTE:  both SPLIT and CSPLIT could be checked in just
 713          * one smart pass...
 714          */
 715         mask = 0x03 << (uframe + qh->gap_uf);
 716         *c_maskp = cpu_to_hc32(ehci, mask << 8);
 717
 718         mask |= 1 << uframe;
 719         if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
 720                 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
 721                                         qh->period, qh->c_usecs))
 722                         goto done;
 723                 if (!check_period (ehci, frame, uframe + qh->gap_uf,
 724                                         qh->period, qh->c_usecs))
 725                         goto done;
 726                 retval = 0;
 727         }
 728 #endif
 729 done:
 730         return retval;
 731 }
 732
 733 /* "first fit" scheduling policy used the first time through,
 734  * or when the previous schedule slot can't be re-used.
 735  */
 736 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
 737 {
 738         int             status;
 739         unsigned        uframe;
 740         __hc32          c_mask;
 741         unsigned        frame;          /* 0..(qh->period - 1), or NO_FRAME */
 742
 743         qh_refresh(ehci, qh);
 744         qh->hw_next = EHCI_LIST_END(ehci);
 745         frame = qh->start;
 746
 747         /* reuse the previous schedule slots, if we can */
 748         if (frame < qh->period) {
 749                 uframe = ffs(hc32_to_cpup(ehci, &qh->hw_info2) & QH_SMASK);
 750                 status = check_intr_schedule (ehci, frame, --uframe,
 751                                 qh, &c_mask);
 752         } else {
 753                 uframe = 0;
 754                 c_mask = 0;
 755                 status = -ENOSPC;
 756         }
 757
 758         /* else scan the schedule to find a group of slots such that all
 759          * uframes have enough periodic bandwidth available.
 760          */
 761         if (status) {
 762                 /* "normal" case, uframing flexible except with splits */
 763                 if (qh->period) {
 764                         int             i;
 765
 766                         for (i = qh->period; status && i > 0; --i) {
 767                                 frame = ++ehci->random_frame % qh->period;
 768                                 for (uframe = 0; uframe < 8; uframe++) {
 769                                         status = check_intr_schedule (ehci,
 770                                                         frame, uframe, qh,
 771                                                         &c_mask);
 772                                         if (status == 0)
 773                                                 break;
 774                                 }
 775                         }
 776
 777                 /* qh->period == 0 means every uframe */
 778                 } else {
 779                         frame = 0;
 780                         status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
 781                 }
 782                 if (status)
 783                         goto done;
 784                 qh->start = frame;
 785
 786                 /* reset S-frame and (maybe) C-frame masks */
 787                 qh->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
 788                 qh->hw_info2 |= qh->period
 789                         ? cpu_to_hc32(ehci, 1 << uframe)
 790                         : cpu_to_hc32(ehci, QH_SMASK);
 791                 qh->hw_info2 |= c_mask;
 792         } else
 793                 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
 794
 795         /* stuff into the periodic schedule */
 796         status = qh_link_periodic (ehci, qh);
 797 done:
 798         return status;
 799 }
 800
 801 static int intr_submit (
 802         struct ehci_hcd         *ehci,
 803         struct urb              *urb,
 804         struct list_head        *qtd_list,
 805         gfp_t                   mem_flags
 806 ) {
 807         unsigned                epnum;
 808         unsigned long           flags;
 809         struct ehci_qh          *qh;
 810         int                     status;
 811         struct list_head        empty;
 812
 813         /* get endpoint and transfer/schedule data */
 814         epnum = urb->ep->desc.bEndpointAddress;
 815
 816         spin_lock_irqsave (&ehci->lock, flags);
 817
 818         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
 819                         &ehci_to_hcd(ehci)->flags))) {
 820                 status = -ESHUTDOWN;
 821                 goto done_not_linked;
 822         }
 823         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
 824         if (unlikely(status))
 825                 goto done_not_linked;
 826
 827         /* get qh and force any scheduling errors */
 828         INIT_LIST_HEAD (&empty);
 829         qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
 830         if (qh == NULL) {
 831                 status = -ENOMEM;
 832                 goto done;
 833         }
 834         if (qh->qh_state == QH_STATE_IDLE) {
 835                 if ((status = qh_schedule (ehci, qh)) != 0)
 836                         goto done;
 837         }
 838
 839         /* then queue the urb's tds to the qh */
 840         qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
 841         BUG_ON (qh == NULL);
 842
 843         /* ... update usbfs periodic stats */
 844         ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
 845
 846 done:
 847         if (unlikely(status))
 848                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
 849 done_not_linked:
 850         spin_unlock_irqrestore (&ehci->lock, flags);
 851         if (status)
 852                 qtd_list_free (ehci, urb, qtd_list);
 853
 854         return status;
 855 }
 856
 857 /*-------------------------------------------------------------------------*/
 858
 859 /* ehci_iso_stream ops work with both ITD and SITD */
 860
 861 static struct ehci_iso_stream *
 862 iso_stream_alloc (gfp_t mem_flags)
 863 {
 864         struct ehci_iso_stream *stream;
 865
 866         stream = kzalloc(sizeof *stream, mem_flags);
 867         if (likely (stream != NULL)) {
 868                 INIT_LIST_HEAD(&stream->td_list);
 869                 INIT_LIST_HEAD(&stream->free_list);
 870                 stream->next_uframe = -1;
 871                 stream->refcount = 1;
 872         }
 873         return stream;
 874 }
 875
 876 static void
 877 iso_stream_init (
 878         struct ehci_hcd         *ehci,
 879         struct ehci_iso_stream  *stream,
 880         struct usb_device       *dev,
 881         int                     pipe,
 882         unsigned                interval
 883 )
 884 {
 885         static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
 886
 887         u32                     buf1;
 888         unsigned                epnum, maxp;
 889         int                     is_input;
 890         long                    bandwidth;
 891
 892         /*
 893          * this might be a "high bandwidth" highspeed endpoint,
 894          * as encoded in the ep descriptor's wMaxPacket field
 895          */
 896         epnum = usb_pipeendpoint (pipe);
 897         is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
 898         maxp = usb_maxpacket(dev, pipe, !is_input);
 899         if (is_input) {
 900                 buf1 = (1 << 11);
 901         } else {
 902                 buf1 = 0;
 903         }
 904
 905         /* knows about ITD vs SITD */
 906         if (dev->speed == USB_SPEED_HIGH) {
 907                 unsigned multi = hb_mult(maxp);
 908
 909                 stream->highspeed = 1;
 910
 911                 maxp = max_packet(maxp);
 912                 buf1 |= maxp;
 913                 maxp *= multi;
 914
 915                 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
 916                 stream->buf1 = cpu_to_hc32(ehci, buf1);
 917                 stream->buf2 = cpu_to_hc32(ehci, multi);
 918
 919                 /* usbfs wants to report the average usecs per frame tied up
 920                  * when transfers on this endpoint are scheduled ...
 921                  */
 922                 stream->usecs = HS_USECS_ISO (maxp);
 923                 bandwidth = stream->usecs * 8;
 924                 bandwidth /= interval;
 925
 926         } else {
 927                 u32             addr;
 928                 int             think_time;
 929                 int             hs_transfers;
 930
 931                 addr = dev->ttport << 24;
 932                 if (!ehci_is_TDI(ehci)
 933                                 || (dev->tt->hub !=
 934                                         ehci_to_hcd(ehci)->self.root_hub))
 935                         addr |= dev->tt->hub->devnum << 16;
 936                 addr |= epnum << 8;
 937                 addr |= dev->devnum;
 938                 stream->usecs = HS_USECS_ISO (maxp);
 939                 think_time = dev->tt ? dev->tt->think_time : 0;
 940                 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
 941                                 dev->speed, is_input, 1, maxp));
 942                 hs_transfers = max (1u, (maxp + 187) / 188);
 943                 if (is_input) {
 944                         u32     tmp;
 945
 946                         addr |= 1 << 31;
 947                         stream->c_usecs = stream->usecs;
 948                         stream->usecs = HS_USECS_ISO (1);
 949                         stream->raw_mask = 1;
 950
 951                         /* c-mask as specified in USB 2.0 11.18.4 3.c */
 952                         tmp = (1 << (hs_transfers + 2)) - 1;
 953                         stream->raw_mask |= tmp << (8 + 2);
 954                 } else
 955                         stream->raw_mask = smask_out [hs_transfers - 1];
 956                 bandwidth = stream->usecs + stream->c_usecs;
 957                 bandwidth /= interval << 3;
 958
 959                 /* stream->splits gets created from raw_mask later */
 960                 stream->address = cpu_to_hc32(ehci, addr);
 961         }
 962         stream->bandwidth = bandwidth;
 963
 964         stream->udev = dev;
 965
 966         stream->bEndpointAddress = is_input | epnum;
 967         stream->interval = interval;
 968         stream->maxp = maxp;
 969 }
 970
 971 static void
 972 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
 973 {
 974         stream->refcount--;
 975
 976         /* free whenever just a dev->ep reference remains.
 977          * not like a QH -- no persistent state (toggle, halt)
 978          */
 979         if (stream->refcount == 1) {
 980                 int             is_in;
 981
 982                 // BUG_ON (!list_empty(&stream->td_list));
 983
 984                 while (!list_empty (&stream->free_list)) {
 985                         struct list_head        *entry;
 986
 987                         entry = stream->free_list.next;
 988                         list_del (entry);
 989
 990                         /* knows about ITD vs SITD */
 991                         if (stream->highspeed) {
 992                                 struct ehci_itd         *itd;
 993
 994                                 itd = list_entry (entry, struct ehci_itd,
 995                                                 itd_list);
 996                                 dma_pool_free (ehci->itd_pool, itd,
 997                                                 itd->itd_dma);
 998                         } else {
 999                                 struct ehci_sitd        *sitd;
1000
1001                                 sitd = list_entry (entry, struct ehci_sitd,
1002                                                 sitd_list);
1003                                 dma_pool_free (ehci->sitd_pool, sitd,
1004                                                 sitd->sitd_dma);
1005                         }
1006                 }
1007
1008                 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1009                 stream->bEndpointAddress &= 0x0f;
1010                 if (stream->ep)
1011                         stream->ep->hcpriv = NULL;
1012
1013                 if (stream->rescheduled) {
1014                         ehci_info (ehci, "ep%d%s-iso rescheduled "
1015                                 "%lu times in %lu seconds\n",
1016                                 stream->bEndpointAddress, is_in ? "in" : "out",
1017                                 stream->rescheduled,
1018                                 ((jiffies - stream->start)/HZ)
1019                                 );
1020                 }
1021
1022                 kfree(stream);
1023         }
1024 }
1025
1026 static inline struct ehci_iso_stream *
1027 iso_stream_get (struct ehci_iso_stream *stream)
1028 {
1029         if (likely (stream != NULL))
1030                 stream->refcount++;
1031         return stream;
1032 }
1033
1034 static struct ehci_iso_stream *
1035 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1036 {
1037         unsigned                epnum;
1038         struct ehci_iso_stream  *stream;
1039         struct usb_host_endpoint *ep;
1040         unsigned long           flags;
1041
1042         epnum = usb_pipeendpoint (urb->pipe);
1043         if (usb_pipein(urb->pipe))
1044                 ep = urb->dev->ep_in[epnum];
1045         else
1046                 ep = urb->dev->ep_out[epnum];
1047
1048         spin_lock_irqsave (&ehci->lock, flags);
1049         stream = ep->hcpriv;
1050
1051         if (unlikely (stream == NULL)) {
1052                 stream = iso_stream_alloc(GFP_ATOMIC);
1053                 if (likely (stream != NULL)) {
1054                         /* dev->ep owns the initial refcount */
1055                         ep->hcpriv = stream;
1056                         stream->ep = ep;
1057                         iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1058                                         urb->interval);
1059                 }
1060
1061         /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
1062         } else if (unlikely (stream->hw_info1 != 0)) {
1063                 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1064                         urb->dev->devpath, epnum,
1065                         usb_pipein(urb->pipe) ? "in" : "out");
1066                 stream = NULL;
1067         }
1068
1069         /* caller guarantees an eventual matching iso_stream_put */
1070         stream = iso_stream_get (stream);
1071
1072         spin_unlock_irqrestore (&ehci->lock, flags);
1073         return stream;
1074 }
1075
1076 /*-------------------------------------------------------------------------*/
1077
1078 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1079
1080 static struct ehci_iso_sched *
1081 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1082 {
1083         struct ehci_iso_sched   *iso_sched;
1084         int                     size = sizeof *iso_sched;
1085
1086         size += packets * sizeof (struct ehci_iso_packet);
1087         iso_sched = kzalloc(size, mem_flags);
1088         if (likely (iso_sched != NULL)) {
1089                 INIT_LIST_HEAD (&iso_sched->td_list);
1090         }
1091         return iso_sched;
1092 }
1093
1094 static inline void
1095 itd_sched_init(
1096         struct ehci_hcd         *ehci,
1097         struct ehci_iso_sched   *iso_sched,
1098         struct ehci_iso_stream  *stream,
1099         struct urb              *urb
1100 )
1101 {
1102         unsigned        i;
1103         dma_addr_t      dma = urb->transfer_dma;
1104
1105         /* how many uframes are needed for these transfers */
1106         iso_sched->span = urb->number_of_packets * stream->interval;
1107
1108         /* figure out per-uframe itd fields that we'll need later
1109          * when we fit new itds into the schedule.
1110          */
1111         for (i = 0; i < urb->number_of_packets; i++) {
1112                 struct ehci_iso_packet  *uframe = &iso_sched->packet [i];
1113                 unsigned                length;
1114                 dma_addr_t              buf;
1115                 u32                     trans;
1116
1117                 length = urb->iso_frame_desc [i].length;
1118                 buf = dma + urb->iso_frame_desc [i].offset;
1119
1120                 trans = EHCI_ISOC_ACTIVE;
1121                 trans |= buf & 0x0fff;
1122                 if (unlikely (((i + 1) == urb->number_of_packets))
1123                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1124                         trans |= EHCI_ITD_IOC;
1125                 trans |= length << 16;
1126                 uframe->transaction = cpu_to_hc32(ehci, trans);
1127
1128                 /* might need to cross a buffer page within a uframe */
1129                 uframe->bufp = (buf & ~(u64)0x0fff);
1130                 buf += length;
1131                 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1132                         uframe->cross = 1;
1133         }
1134 }
1135
1136 static void
1137 iso_sched_free (
1138         struct ehci_iso_stream  *stream,
1139         struct ehci_iso_sched   *iso_sched
1140 )
1141 {
1142         if (!iso_sched)
1143                 return;
1144         // caller must hold ehci->lock!
1145         list_splice (&iso_sched->td_list, &stream->free_list);
1146         kfree (iso_sched);
1147 }
1148
1149 static int
1150 itd_urb_transaction (
1151         struct ehci_iso_stream  *stream,
1152         struct ehci_hcd         *ehci,
1153         struct urb              *urb,
1154         gfp_t                   mem_flags
1155 )
1156 {
1157         struct ehci_itd         *itd;
1158         dma_addr_t              itd_dma;
1159         int                     i;
1160         unsigned                num_itds;
1161         struct ehci_iso_sched   *sched;
1162         unsigned long           flags;
1163
1164         sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1165         if (unlikely (sched == NULL))
1166                 return -ENOMEM;
1167
1168         itd_sched_init(ehci, sched, stream, urb);
1169
1170         if (urb->interval < 8)
1171                 num_itds = 1 + (sched->span + 7) / 8;
1172         else
1173                 num_itds = urb->number_of_packets;
1174
1175         /* allocate/init ITDs */
1176         spin_lock_irqsave (&ehci->lock, flags);
1177         for (i = 0; i < num_itds; i++) {
1178
1179                 /* free_list.next might be cache-hot ... but maybe
1180                  * the HC caches it too. avoid that issue for now.
1181                  */
1182
1183                 /* prefer previously-allocated itds */
1184                 if (likely (!list_empty(&stream->free_list))) {
1185                         itd = list_entry (stream->free_list.prev,
1186                                         struct ehci_itd, itd_list);
1187                         list_del (&itd->itd_list);
1188                         itd_dma = itd->itd_dma;
1189                 } else {
1190                         spin_unlock_irqrestore (&ehci->lock, flags);
1191                         itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1192                                         &itd_dma);
1193                         spin_lock_irqsave (&ehci->lock, flags);
1194                         if (!itd) {
1195                                 iso_sched_free(stream, sched);
1196                                 spin_unlock_irqrestore(&ehci->lock, flags);
1197                                 return -ENOMEM;
1198                         }
1199                 }
1200
1201                 memset (itd, 0, sizeof *itd);
1202                 itd->itd_dma = itd_dma;
1203                 list_add (&itd->itd_list, &sched->td_list);
1204         }
1205         spin_unlock_irqrestore (&ehci->lock, flags);
1206
1207         /* temporarily store schedule info in hcpriv */
1208         urb->hcpriv = sched;
1209         urb->error_count = 0;
1210         return 0;
1211 }
1212
1213 /*-------------------------------------------------------------------------*/
1214
1215 static inline int
1216 itd_slot_ok (
1217         struct ehci_hcd         *ehci,
1218         u32                     mod,
1219         u32                     uframe,
1220         u8                      usecs,
1221         u32                     period
1222 )
1223 {
1224         uframe %= period;
1225         do {
1226                 /* can't commit more than 80% periodic == 100 usec */
1227                 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1228                                 > (100 - usecs))
1229                         return 0;
1230
1231                 /* we know urb->interval is 2^N uframes */
1232                 uframe += period;
1233         } while (uframe < mod);
1234         return 1;
1235 }
1236
1237 static inline int
1238 sitd_slot_ok (
1239         struct ehci_hcd         *ehci,
1240         u32                     mod,
1241         struct ehci_iso_stream  *stream,
1242         u32                     uframe,
1243         struct ehci_iso_sched   *sched,
1244         u32                     period_uframes
1245 )
1246 {
1247         u32                     mask, tmp;
1248         u32                     frame, uf;
1249
1250         mask = stream->raw_mask << (uframe & 7);
1251
1252         /* for IN, don't wrap CSPLIT into the next frame */
1253         if (mask & ~0xffff)
1254                 return 0;
1255
1256         /* this multi-pass logic is simple, but performance may
1257          * suffer when the schedule data isn't cached.
1258          */
1259
1260         /* check bandwidth */
1261         uframe %= period_uframes;
1262         do {
1263                 u32             max_used;
1264
1265                 frame = uframe >> 3;
1266                 uf = uframe & 7;
1267
1268 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1269                 /* The tt's fullspeed bus bandwidth must be available.
1270                  * tt_available scheduling guarantees 10+% for control/bulk.
1271                  */
1272                 if (!tt_available (ehci, period_uframes << 3,
1273                                 stream->udev, frame, uf, stream->tt_usecs))
1274                         return 0;
1275 #else
1276                 /* tt must be idle for start(s), any gap, and csplit.
1277                  * assume scheduling slop leaves 10+% for control/bulk.
1278                  */
1279                 if (!tt_no_collision (ehci, period_uframes << 3,
1280                                 stream->udev, frame, mask))
1281                         return 0;
1282 #endif
1283
1284                 /* check starts (OUT uses more than one) */
1285                 max_used = 100 - stream->usecs;
1286                 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1287                         if (periodic_usecs (ehci, frame, uf) > max_used)
1288                                 return 0;
1289                 }
1290
1291                 /* for IN, check CSPLIT */
1292                 if (stream->c_usecs) {
1293                         uf = uframe & 7;
1294                         max_used = 100 - stream->c_usecs;
1295                         do {
1296                                 tmp = 1 << uf;
1297                                 tmp <<= 8;
1298                                 if ((stream->raw_mask & tmp) == 0)
1299                                         continue;
1300                                 if (periodic_usecs (ehci, frame, uf)
1301                                                 > max_used)
1302                                         return 0;
1303                         } while (++uf < 8);
1304                 }
1305
1306                 /* we know urb->interval is 2^N uframes */
1307                 uframe += period_uframes;
1308         } while (uframe < mod);
1309
1310         stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1311         return 1;
1312 }
1313
1314 /*
1315  * This scheduler plans almost as far into the future as it has actual
1316  * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
1317  * "as small as possible" to be cache-friendlier.)  That limits the size
1318  * transfers you can stream reliably; avoid more than 64 msec per urb.
1319  * Also avoid queue depths of less than ehci's worst irq latency (affected
1320  * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1321  * and other factors); or more than about 230 msec total (for portability,
1322  * given EHCI_TUNE_FLS and the slop).  Or, write a smarter scheduler!
1323  */
1324
1325 #define SCHEDULE_SLOP   10      /* frames */
1326
1327 static int
1328 iso_stream_schedule (
1329         struct ehci_hcd         *ehci,
1330         struct urb              *urb,
1331         struct ehci_iso_stream  *stream
1332 )
1333 {
1334         u32                     now, start, max, period;
1335         int                     status;
1336         unsigned                mod = ehci->periodic_size << 3;
1337         struct ehci_iso_sched   *sched = urb->hcpriv;
1338
1339         if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1340                 ehci_dbg (ehci, "iso request %p too long\n", urb);
1341                 status = -EFBIG;
1342                 goto fail;
1343         }
1344
1345         if ((stream->depth + sched->span) > mod) {
1346                 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1347                         urb, stream->depth, sched->span, mod);
1348                 status = -EFBIG;
1349                 goto fail;
1350         }
1351
1352         now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1353
1354         /* when's the last uframe this urb could start? */
1355         max = now + mod;
1356
1357         /* Typical case: reuse current schedule, stream is still active.
1358          * Hopefully there are no gaps from the host falling behind
1359          * (irq delays etc), but if there are we'll take the next
1360          * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1361          */
1362         if (likely (!list_empty (&stream->td_list))) {
1363                 start = stream->next_uframe;
1364                 if (start < now)
1365                         start += mod;
1366
1367                 /* Fell behind (by up to twice the slop amount)? */
1368                 if (start >= max - 2 * 8 * SCHEDULE_SLOP)
1369                         start += stream->interval * DIV_ROUND_UP(
1370                                         max - start, stream->interval) - mod;
1371
1372                 /* Tried to schedule too far into the future? */
1373                 if (unlikely((start + sched->span) >= max)) {
1374                         status = -EFBIG;
1375                         goto fail;
1376                 }
1377                 goto ready;
1378         }
1379
1380         /* need to schedule; when's the next (u)frame we could start?
1381          * this is bigger than ehci->i_thresh allows; scheduling itself
1382          * isn't free, the slop should handle reasonably slow cpus.  it
1383          * can also help high bandwidth if the dma and irq loads don't
1384          * jump until after the queue is primed.
1385          */
1386         start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1387         start %= mod;
1388         stream->next_uframe = start;
1389
1390         /* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
1391
1392         period = urb->interval;
1393         if (!stream->highspeed)
1394                 period <<= 3;
1395
1396         /* find a uframe slot with enough bandwidth */
1397         for (; start < (stream->next_uframe + period); start++) {
1398                 int             enough_space;
1399
1400                 /* check schedule: enough space? */
1401                 if (stream->highspeed)
1402                         enough_space = itd_slot_ok (ehci, mod, start,
1403                                         stream->usecs, period);
1404                 else {
1405                         if ((start % 8) >= 6)
1406                                 continue;
1407                         enough_space = sitd_slot_ok (ehci, mod, stream,
1408                                         start, sched, period);
1409                 }
1410
1411                 /* schedule it here if there's enough bandwidth */
1412                 if (enough_space) {
1413                         stream->next_uframe = start % mod;
1414                         goto ready;
1415                 }
1416         }
1417
1418         /* no room in the schedule */
1419         ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1420                 list_empty (&stream->td_list) ? "" : "re",
1421                 urb, now, max);
1422         status = -ENOSPC;
1423
1424 fail:
1425         iso_sched_free (stream, sched);
1426         urb->hcpriv = NULL;
1427         return status;
1428
1429 ready:
1430         /* report high speed start in uframes; full speed, in frames */
1431         urb->start_frame = stream->next_uframe;
1432         if (!stream->highspeed)
1433                 urb->start_frame >>= 3;
1434         return 0;
1435 }
1436
1437 /*-------------------------------------------------------------------------*/
1438
1439 static inline void
1440 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1441                 struct ehci_itd *itd)
1442 {
1443         int i;
1444
1445         /* it's been recently zeroed */
1446         itd->hw_next = EHCI_LIST_END(ehci);
1447         itd->hw_bufp [0] = stream->buf0;
1448         itd->hw_bufp [1] = stream->buf1;
1449         itd->hw_bufp [2] = stream->buf2;
1450
1451         for (i = 0; i < 8; i++)
1452                 itd->index[i] = -1;
1453
1454         /* All other fields are filled when scheduling */
1455 }
1456
1457 static inline void
1458 itd_patch(
1459         struct ehci_hcd         *ehci,
1460         struct ehci_itd         *itd,
1461         struct ehci_iso_sched   *iso_sched,
1462         unsigned                index,
1463         u16                     uframe
1464 )
1465 {
1466         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1467         unsigned                pg = itd->pg;
1468
1469         // BUG_ON (pg == 6 && uf->cross);
1470
1471         uframe &= 0x07;
1472         itd->index [uframe] = index;
1473
1474         itd->hw_transaction[uframe] = uf->transaction;
1475         itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1476         itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1477         itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1478
1479         /* iso_frame_desc[].offset must be strictly increasing */
1480         if (unlikely (uf->cross)) {
1481                 u64     bufp = uf->bufp + 4096;
1482
1483                 itd->pg = ++pg;
1484                 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1485                 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1486         }
1487 }
1488
1489 static inline void
1490 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1491 {
1492         /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1493         itd->itd_next = ehci->pshadow [frame];
1494         itd->hw_next = ehci->periodic [frame];
1495         ehci->pshadow [frame].itd = itd;
1496         itd->frame = frame;
1497         wmb ();
1498         ehci->periodic[frame] = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1499 }
1500
1501 /* fit urb's itds into the selected schedule slot; activate as needed */
1502 static int
1503 itd_link_urb (
1504         struct ehci_hcd         *ehci,
1505         struct urb              *urb,
1506         unsigned                mod,
1507         struct ehci_iso_stream  *stream
1508 )
1509 {
1510         int                     packet;
1511         unsigned                next_uframe, uframe, frame;
1512         struct ehci_iso_sched   *iso_sched = urb->hcpriv;
1513         struct ehci_itd         *itd;
1514
1515         next_uframe = stream->next_uframe % mod;
1516
1517         if (unlikely (list_empty(&stream->td_list))) {
1518                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1519                                 += stream->bandwidth;
1520                 ehci_vdbg (ehci,
1521                         "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1522                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1523                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1524                         urb->interval,
1525                         next_uframe >> 3, next_uframe & 0x7);
1526                 stream->start = jiffies;
1527         }
1528         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1529
1530         /* fill iTDs uframe by uframe */
1531         for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1532                 if (itd == NULL) {
1533                         /* ASSERT:  we have all necessary itds */
1534                         // BUG_ON (list_empty (&iso_sched->td_list));
1535
1536                         /* ASSERT:  no itds for this endpoint in this uframe */
1537
1538                         itd = list_entry (iso_sched->td_list.next,
1539                                         struct ehci_itd, itd_list);
1540                         list_move_tail (&itd->itd_list, &stream->td_list);
1541                         itd->stream = iso_stream_get (stream);
1542                         itd->urb = urb;
1543                         itd_init (ehci, stream, itd);
1544                 }
1545
1546                 uframe = next_uframe & 0x07;
1547                 frame = next_uframe >> 3;
1548
1549                 itd_patch(ehci, itd, iso_sched, packet, uframe);
1550
1551                 next_uframe += stream->interval;
1552                 stream->depth += stream->interval;
1553                 next_uframe %= mod;
1554                 packet++;
1555
1556                 /* link completed itds into the schedule */
1557                 if (((next_uframe >> 3) != frame)
1558                                 || packet == urb->number_of_packets) {
1559                         itd_link (ehci, frame % ehci->periodic_size, itd);
1560                         itd = NULL;
1561                 }
1562         }
1563         stream->next_uframe = next_uframe;
1564
1565         /* don't need that schedule data any more */
1566         iso_sched_free (stream, iso_sched);
1567         urb->hcpriv = NULL;
1568
1569         timer_action (ehci, TIMER_IO_WATCHDOG);
1570         return enable_periodic(ehci);
1571 }
1572
1573 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1574
1575 /* Process and recycle a completed ITD.  Return true iff its urb completed,
1576  * and hence its completion callback probably added things to the hardware
1577  * schedule.
1578  *
1579  * Note that we carefully avoid recycling this descriptor until after any
1580  * completion callback runs, so that it won't be reused quickly.  That is,
1581  * assuming (a) no more than two urbs per frame on this endpoint, and also
1582  * (b) only this endpoint's completions submit URBs.  It seems some silicon
1583  * corrupts things if you reuse completed descriptors very quickly...
1584  */
1585 static unsigned
1586 itd_complete (
1587         struct ehci_hcd *ehci,
1588         struct ehci_itd *itd
1589 ) {
1590         struct urb                              *urb = itd->urb;
1591         struct usb_iso_packet_descriptor        *desc;
1592         u32                                     t;
1593         unsigned                                uframe;
1594         int                                     urb_index = -1;
1595         struct ehci_iso_stream                  *stream = itd->stream;
1596         struct usb_device                       *dev;
1597         unsigned                                retval = false;
1598
1599         /* for each uframe with a packet */
1600         for (uframe = 0; uframe < 8; uframe++) {
1601                 if (likely (itd->index[uframe] == -1))
1602                         continue;
1603                 urb_index = itd->index[uframe];
1604                 desc = &urb->iso_frame_desc [urb_index];
1605
1606                 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1607                 itd->hw_transaction [uframe] = 0;
1608                 stream->depth -= stream->interval;
1609
1610                 /* report transfer status */
1611                 if (unlikely (t & ISO_ERRS)) {
1612                         urb->error_count++;
1613                         if (t & EHCI_ISOC_BUF_ERR)
1614                                 desc->status = usb_pipein (urb->pipe)
1615                                         ? -ENOSR  /* hc couldn't read */
1616                                         : -ECOMM; /* hc couldn't write */
1617                         else if (t & EHCI_ISOC_BABBLE)
1618                                 desc->status = -EOVERFLOW;
1619                         else /* (t & EHCI_ISOC_XACTERR) */
1620                                 desc->status = -EPROTO;
1621
1622                         /* HC need not update length with this error */
1623                         if (!(t & EHCI_ISOC_BABBLE)) {
1624                                 desc->actual_length = EHCI_ITD_LENGTH(t);
1625                                 urb->actual_length += desc->actual_length;
1626                         }
1627                 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1628                         desc->status = 0;
1629                         desc->actual_length = EHCI_ITD_LENGTH(t);
1630                         urb->actual_length += desc->actual_length;
1631                 } else {
1632                         /* URB was too late */
1633                         desc->status = -EXDEV;
1634                 }
1635         }
1636
1637         /* handle completion now? */
1638         if (likely ((urb_index + 1) != urb->number_of_packets))
1639                 goto done;
1640
1641         /* ASSERT: it's really the last itd for this urb
1642         list_for_each_entry (itd, &stream->td_list, itd_list)
1643                 BUG_ON (itd->urb == urb);
1644          */
1645
1646         /* give urb back to the driver; completion often (re)submits */
1647         dev = urb->dev;
1648         ehci_urb_done(ehci, urb, 0);
1649         retval = true;
1650         urb = NULL;
1651         (void) disable_periodic(ehci);
1652         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1653
1654         if (unlikely(list_is_singular(&stream->td_list))) {
1655                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1656                                 -= stream->bandwidth;
1657                 ehci_vdbg (ehci,
1658                         "deschedule devp %s ep%d%s-iso\n",
1659                         dev->devpath, stream->bEndpointAddress & 0x0f,
1660                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1661         }
1662         iso_stream_put (ehci, stream);
1663
1664 done:
1665         itd->urb = NULL;
1666         if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1667                 /* OK to recycle this ITD now. */
1668                 itd->stream = NULL;
1669                 list_move(&itd->itd_list, &stream->free_list);
1670                 iso_stream_put(ehci, stream);
1671         } else {
1672                 /* HW might remember this ITD, so we can't recycle it yet.
1673                  * Move it to a safe place until a new frame starts.
1674                  */
1675                 list_move(&itd->itd_list, &ehci->cached_itd_list);
1676                 if (stream->refcount == 2) {
1677                         /* If iso_stream_put() were called here, stream
1678                          * would be freed.  Instead, just prevent reuse.
1679                          */
1680                         stream->ep->hcpriv = NULL;
1681                         stream->ep = NULL;
1682                 }
1683         }
1684         return retval;
1685 }
1686
1687 /*-------------------------------------------------------------------------*/
1688
1689 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1690         gfp_t mem_flags)
1691 {
1692         int                     status = -EINVAL;
1693         unsigned long           flags;
1694         struct ehci_iso_stream  *stream;
1695
1696         /* Get iso_stream head */
1697         stream = iso_stream_find (ehci, urb);
1698         if (unlikely (stream == NULL)) {
1699                 ehci_dbg (ehci, "can't get iso stream\n");
1700                 return -ENOMEM;
1701         }
1702         if (unlikely (urb->interval != stream->interval)) {
1703                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1704                         stream->interval, urb->interval);
1705                 goto done;
1706         }
1707
1708 #ifdef EHCI_URB_TRACE
1709         ehci_dbg (ehci,
1710                 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1711                 __func__, urb->dev->devpath, urb,
1712                 usb_pipeendpoint (urb->pipe),
1713                 usb_pipein (urb->pipe) ? "in" : "out",
1714                 urb->transfer_buffer_length,
1715                 urb->number_of_packets, urb->interval,
1716                 stream);
1717 #endif
1718
1719         /* allocate ITDs w/o locking anything */
1720         status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1721         if (unlikely (status < 0)) {
1722                 ehci_dbg (ehci, "can't init itds\n");
1723                 goto done;
1724         }
1725
1726         /* schedule ... need to lock */
1727         spin_lock_irqsave (&ehci->lock, flags);
1728         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1729                                &ehci_to_hcd(ehci)->flags))) {
1730                 status = -ESHUTDOWN;
1731                 goto done_not_linked;
1732         }
1733         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1734         if (unlikely(status))
1735                 goto done_not_linked;
1736         status = iso_stream_schedule(ehci, urb, stream);
1737         if (likely (status == 0))
1738                 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1739         else
1740                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1741 done_not_linked:
1742         spin_unlock_irqrestore (&ehci->lock, flags);
1743
1744 done:
1745         if (unlikely (status < 0))
1746                 iso_stream_put (ehci, stream);
1747         return status;
1748 }
1749
1750 /*-------------------------------------------------------------------------*/
1751
1752 /*
1753  * "Split ISO TDs" ... used for USB 1.1 devices going through the
1754  * TTs in USB 2.0 hubs.  These need microframe scheduling.
1755  */
1756
1757 static inline void
1758 sitd_sched_init(
1759         struct ehci_hcd         *ehci,
1760         struct ehci_iso_sched   *iso_sched,
1761         struct ehci_iso_stream  *stream,
1762         struct urb              *urb
1763 )
1764 {
1765         unsigned        i;
1766         dma_addr_t      dma = urb->transfer_dma;
1767
1768         /* how many frames are needed for these transfers */
1769         iso_sched->span = urb->number_of_packets * stream->interval;
1770
1771         /* figure out per-frame sitd fields that we'll need later
1772          * when we fit new sitds into the schedule.
1773          */
1774         for (i = 0; i < urb->number_of_packets; i++) {
1775                 struct ehci_iso_packet  *packet = &iso_sched->packet [i];
1776                 unsigned                length;
1777                 dma_addr_t              buf;
1778                 u32                     trans;
1779
1780                 length = urb->iso_frame_desc [i].length & 0x03ff;
1781                 buf = dma + urb->iso_frame_desc [i].offset;
1782
1783                 trans = SITD_STS_ACTIVE;
1784                 if (((i + 1) == urb->number_of_packets)
1785                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1786                         trans |= SITD_IOC;
1787                 trans |= length << 16;
1788                 packet->transaction = cpu_to_hc32(ehci, trans);
1789
1790                 /* might need to cross a buffer page within a td */
1791                 packet->bufp = buf;
1792                 packet->buf1 = (buf + length) & ~0x0fff;
1793                 if (packet->buf1 != (buf & ~(u64)0x0fff))
1794                         packet->cross = 1;
1795
1796                 /* OUT uses multiple start-splits */
1797                 if (stream->bEndpointAddress & USB_DIR_IN)
1798                         continue;
1799                 length = (length + 187) / 188;
1800                 if (length > 1) /* BEGIN vs ALL */
1801                         length |= 1 << 3;
1802                 packet->buf1 |= length;
1803         }
1804 }
1805
1806 static int
1807 sitd_urb_transaction (
1808         struct ehci_iso_stream  *stream,
1809         struct ehci_hcd         *ehci,
1810         struct urb              *urb,
1811         gfp_t                   mem_flags
1812 )
1813 {
1814         struct ehci_sitd        *sitd;
1815         dma_addr_t              sitd_dma;
1816         int                     i;
1817         struct ehci_iso_sched   *iso_sched;
1818         unsigned long           flags;
1819
1820         iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1821         if (iso_sched == NULL)
1822                 return -ENOMEM;
1823
1824         sitd_sched_init(ehci, iso_sched, stream, urb);
1825
1826         /* allocate/init sITDs */
1827         spin_lock_irqsave (&ehci->lock, flags);
1828         for (i = 0; i < urb->number_of_packets; i++) {
1829
1830                 /* NOTE:  for now, we don't try to handle wraparound cases
1831                  * for IN (using sitd->hw_backpointer, like a FSTN), which
1832                  * means we never need two sitds for full speed packets.
1833                  */
1834
1835                 /* free_list.next might be cache-hot ... but maybe
1836                  * the HC caches it too. avoid that issue for now.
1837                  */
1838
1839                 /* prefer previously-allocated sitds */
1840                 if (!list_empty(&stream->free_list)) {
1841                         sitd = list_entry (stream->free_list.prev,
1842                                          struct ehci_sitd, sitd_list);
1843                         list_del (&sitd->sitd_list);
1844                         sitd_dma = sitd->sitd_dma;
1845                 } else {
1846                         spin_unlock_irqrestore (&ehci->lock, flags);
1847                         sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1848                                         &sitd_dma);
1849                         spin_lock_irqsave (&ehci->lock, flags);
1850                         if (!sitd) {
1851                                 iso_sched_free(stream, iso_sched);
1852                                 spin_unlock_irqrestore(&ehci->lock, flags);
1853                                 return -ENOMEM;
1854                         }
1855                 }
1856
1857                 memset (sitd, 0, sizeof *sitd);
1858                 sitd->sitd_dma = sitd_dma;
1859                 list_add (&sitd->sitd_list, &iso_sched->td_list);
1860         }
1861
1862         /* temporarily store schedule info in hcpriv */
1863         urb->hcpriv = iso_sched;
1864         urb->error_count = 0;
1865
1866         spin_unlock_irqrestore (&ehci->lock, flags);
1867         return 0;
1868 }
1869
1870 /*-------------------------------------------------------------------------*/
1871
1872 static inline void
1873 sitd_patch(
1874         struct ehci_hcd         *ehci,
1875         struct ehci_iso_stream  *stream,
1876         struct ehci_sitd        *sitd,
1877         struct ehci_iso_sched   *iso_sched,
1878         unsigned                index
1879 )
1880 {
1881         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1882         u64                     bufp = uf->bufp;
1883
1884         sitd->hw_next = EHCI_LIST_END(ehci);
1885         sitd->hw_fullspeed_ep = stream->address;
1886         sitd->hw_uframe = stream->splits;
1887         sitd->hw_results = uf->transaction;
1888         sitd->hw_backpointer = EHCI_LIST_END(ehci);
1889
1890         bufp = uf->bufp;
1891         sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1892         sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1893
1894         sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1895         if (uf->cross)
1896                 bufp += 4096;
1897         sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1898         sitd->index = index;
1899 }
1900
1901 static inline void
1902 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1903 {
1904         /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1905         sitd->sitd_next = ehci->pshadow [frame];
1906         sitd->hw_next = ehci->periodic [frame];
1907         ehci->pshadow [frame].sitd = sitd;
1908         sitd->frame = frame;
1909         wmb ();
1910         ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1911 }
1912
1913 /* fit urb's sitds into the selected schedule slot; activate as needed */
1914 static int
1915 sitd_link_urb (
1916         struct ehci_hcd         *ehci,
1917         struct urb              *urb,
1918         unsigned                mod,
1919         struct ehci_iso_stream  *stream
1920 )
1921 {
1922         int                     packet;
1923         unsigned                next_uframe;
1924         struct ehci_iso_sched   *sched = urb->hcpriv;
1925         struct ehci_sitd        *sitd;
1926
1927         next_uframe = stream->next_uframe;
1928
1929         if (list_empty(&stream->td_list)) {
1930                 /* usbfs ignores TT bandwidth */
1931                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1932                                 += stream->bandwidth;
1933                 ehci_vdbg (ehci,
1934                         "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
1935                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1936                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1937                         (next_uframe >> 3) % ehci->periodic_size,
1938                         stream->interval, hc32_to_cpu(ehci, stream->splits));
1939                 stream->start = jiffies;
1940         }
1941         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1942
1943         /* fill sITDs frame by frame */
1944         for (packet = 0, sitd = NULL;
1945                         packet < urb->number_of_packets;
1946                         packet++) {
1947
1948                 /* ASSERT:  we have all necessary sitds */
1949                 BUG_ON (list_empty (&sched->td_list));
1950
1951                 /* ASSERT:  no itds for this endpoint in this frame */
1952
1953                 sitd = list_entry (sched->td_list.next,
1954                                 struct ehci_sitd, sitd_list);
1955                 list_move_tail (&sitd->sitd_list, &stream->td_list);
1956                 sitd->stream = iso_stream_get (stream);
1957                 sitd->urb = urb;
1958
1959                 sitd_patch(ehci, stream, sitd, sched, packet);
1960                 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
1961                                 sitd);
1962
1963                 next_uframe += stream->interval << 3;
1964                 stream->depth += stream->interval << 3;
1965         }
1966         stream->next_uframe = next_uframe % mod;
1967
1968         /* don't need that schedule data any more */
1969         iso_sched_free (stream, sched);
1970         urb->hcpriv = NULL;
1971
1972         timer_action (ehci, TIMER_IO_WATCHDOG);
1973         return enable_periodic(ehci);
1974 }
1975
1976 /*-------------------------------------------------------------------------*/
1977
1978 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
1979                                 | SITD_STS_XACT | SITD_STS_MMF)
1980
1981 /* Process and recycle a completed SITD.  Return true iff its urb completed,
1982  * and hence its completion callback probably added things to the hardware
1983  * schedule.
1984  *
1985  * Note that we carefully avoid recycling this descriptor until after any
1986  * completion callback runs, so that it won't be reused quickly.  That is,
1987  * assuming (a) no more than two urbs per frame on this endpoint, and also
1988  * (b) only this endpoint's completions submit URBs.  It seems some silicon
1989  * corrupts things if you reuse completed descriptors very quickly...
1990  */
1991 static unsigned
1992 sitd_complete (
1993         struct ehci_hcd         *ehci,
1994         struct ehci_sitd        *sitd
1995 ) {
1996         struct urb                              *urb = sitd->urb;
1997         struct usb_iso_packet_descriptor        *desc;
1998         u32                                     t;
1999         int                                     urb_index = -1;
2000         struct ehci_iso_stream                  *stream = sitd->stream;
2001         struct usb_device                       *dev;
2002         unsigned                                retval = false;
2003
2004         urb_index = sitd->index;
2005         desc = &urb->iso_frame_desc [urb_index];
2006         t = hc32_to_cpup(ehci, &sitd->hw_results);
2007
2008         /* report transfer status */
2009         if (t & SITD_ERRS) {
2010                 urb->error_count++;
2011                 if (t & SITD_STS_DBE)
2012                         desc->status = usb_pipein (urb->pipe)
2013                                 ? -ENOSR  /* hc couldn't read */
2014                                 : -ECOMM; /* hc couldn't write */
2015                 else if (t & SITD_STS_BABBLE)
2016                         desc->status = -EOVERFLOW;
2017                 else /* XACT, MMF, etc */
2018                         desc->status = -EPROTO;
2019         } else {
2020                 desc->status = 0;
2021                 desc->actual_length = desc->length - SITD_LENGTH(t);
2022                 urb->actual_length += desc->actual_length;
2023         }
2024         stream->depth -= stream->interval << 3;
2025
2026         /* handle completion now? */
2027         if ((urb_index + 1) != urb->number_of_packets)
2028                 goto done;
2029
2030         /* ASSERT: it's really the last sitd for this urb
2031         list_for_each_entry (sitd, &stream->td_list, sitd_list)
2032                 BUG_ON (sitd->urb == urb);
2033          */
2034
2035         /* give urb back to the driver; completion often (re)submits */
2036         dev = urb->dev;
2037         ehci_urb_done(ehci, urb, 0);
2038         retval = true;
2039         urb = NULL;
2040         (void) disable_periodic(ehci);
2041         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2042
2043         if (list_is_singular(&stream->td_list)) {
2044                 ehci_to_hcd(ehci)->self.bandwidth_allocated
2045                                 -= stream->bandwidth;
2046                 ehci_vdbg (ehci,
2047                         "deschedule devp %s ep%d%s-iso\n",
2048                         dev->devpath, stream->bEndpointAddress & 0x0f,
2049                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2050         }
2051         iso_stream_put (ehci, stream);
2052         /* OK to recycle this SITD now that its completion callback ran. */
2053 done:
2054         sitd->urb = NULL;
2055         sitd->stream = NULL;
2056         list_move(&sitd->sitd_list, &stream->free_list);
2057         iso_stream_put(ehci, stream);
2058
2059         return retval;
2060 }
2061
2062
2063 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2064         gfp_t mem_flags)
2065 {
2066         int                     status = -EINVAL;
2067         unsigned long           flags;
2068         struct ehci_iso_stream  *stream;
2069
2070         /* Get iso_stream head */
2071         stream = iso_stream_find (ehci, urb);
2072         if (stream == NULL) {
2073                 ehci_dbg (ehci, "can't get iso stream\n");
2074                 return -ENOMEM;
2075         }
2076         if (urb->interval != stream->interval) {
2077                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2078                         stream->interval, urb->interval);
2079                 goto done;
2080         }
2081
2082 #ifdef EHCI_URB_TRACE
2083         ehci_dbg (ehci,
2084                 "submit %p dev%s ep%d%s-iso len %d\n",
2085                 urb, urb->dev->devpath,
2086                 usb_pipeendpoint (urb->pipe),
2087                 usb_pipein (urb->pipe) ? "in" : "out",
2088                 urb->transfer_buffer_length);
2089 #endif
2090
2091         /* allocate SITDs */
2092         status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2093         if (status < 0) {
2094                 ehci_dbg (ehci, "can't init sitds\n");
2095                 goto done;
2096         }
2097
2098         /* schedule ... need to lock */
2099         spin_lock_irqsave (&ehci->lock, flags);
2100         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
2101                                &ehci_to_hcd(ehci)->flags))) {
2102                 status = -ESHUTDOWN;
2103                 goto done_not_linked;
2104         }
2105         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2106         if (unlikely(status))
2107                 goto done_not_linked;
2108         status = iso_stream_schedule(ehci, urb, stream);
2109         if (status == 0)
2110                 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2111         else
2112                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2113 done_not_linked:
2114         spin_unlock_irqrestore (&ehci->lock, flags);
2115
2116 done:
2117         if (status < 0)
2118                 iso_stream_put (ehci, stream);
2119         return status;
2120 }
2121
2122 /*-------------------------------------------------------------------------*/
2123
2124 static void free_cached_itd_list(struct ehci_hcd *ehci)
2125 {
2126         struct ehci_itd *itd, *n;
2127
2128         list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2129                 struct ehci_iso_stream  *stream = itd->stream;
2130                 itd->stream = NULL;
2131                 list_move(&itd->itd_list, &stream->free_list);
2132                 iso_stream_put(ehci, stream);
2133         }
2134 }
2135
2136 /*-------------------------------------------------------------------------*/
2137
2138 static void
2139 scan_periodic (struct ehci_hcd *ehci)
2140 {
2141         unsigned        now_uframe, frame, clock, clock_frame, mod;
2142         unsigned        modified;
2143
2144         mod = ehci->periodic_size << 3;
2145
2146         /*
2147          * When running, scan from last scan point up to "now"
2148          * else clean up by scanning everything that's left.
2149          * Touches as few pages as possible:  cache-friendly.
2150          */
2151         now_uframe = ehci->next_uframe;
2152         if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2153                 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2154                 clock_frame = (clock >> 3) % ehci->periodic_size;
2155         } else  {
2156                 clock = now_uframe + mod - 1;
2157                 clock_frame = -1;
2158         }
2159         if (ehci->clock_frame != clock_frame) {
2160                 free_cached_itd_list(ehci);
2161                 ehci->clock_frame = clock_frame;
2162         }
2163         clock %= mod;
2164         clock_frame = clock >> 3;
2165
2166         for (;;) {
2167                 union ehci_shadow       q, *q_p;
2168                 __hc32                  type, *hw_p;
2169                 unsigned                incomplete = false;
2170
2171                 frame = now_uframe >> 3;
2172
2173 restart:
2174                 /* scan each element in frame's queue for completions */
2175                 q_p = &ehci->pshadow [frame];
2176                 hw_p = &ehci->periodic [frame];
2177                 q.ptr = q_p->ptr;
2178                 type = Q_NEXT_TYPE(ehci, *hw_p);
2179                 modified = 0;
2180
2181                 while (q.ptr != NULL) {
2182                         unsigned                uf;
2183                         union ehci_shadow       temp;
2184                         int                     live;
2185
2186                         live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2187                         switch (hc32_to_cpu(ehci, type)) {
2188                         case Q_TYPE_QH:
2189                                 /* handle any completions */
2190                                 temp.qh = qh_get (q.qh);
2191                                 type = Q_NEXT_TYPE(ehci, q.qh->hw_next);
2192                                 q = q.qh->qh_next;
2193                                 modified = qh_completions (ehci, temp.qh);
2194                                 if (unlikely (list_empty (&temp.qh->qtd_list)))
2195                                         intr_deschedule (ehci, temp.qh);
2196                                 qh_put (temp.qh);
2197                                 break;
2198                         case Q_TYPE_FSTN:
2199                                 /* for "save place" FSTNs, look at QH entries
2200                                  * in the previous frame for completions.
2201                                  */
2202                                 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2203                                         dbg ("ignoring completions from FSTNs");
2204                                 }
2205                                 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2206                                 q = q.fstn->fstn_next;
2207                                 break;
2208                         case Q_TYPE_ITD:
2209                                 /* If this ITD is still active, leave it for
2210                                  * later processing ... check the next entry.
2211                                  * No need to check for activity unless the
2212                                  * frame is current.
2213                                  */
2214                                 if (frame == clock_frame && live) {
2215                                         rmb();
2216                                         for (uf = 0; uf < 8; uf++) {
2217                                                 if (q.itd->hw_transaction[uf] &
2218                                                             ITD_ACTIVE(ehci))
2219                                                         break;
2220                                         }
2221                                         if (uf < 8) {
2222                                                 incomplete = true;
2223                                                 q_p = &q.itd->itd_next;
2224                                                 hw_p = &q.itd->hw_next;
2225                                                 type = Q_NEXT_TYPE(ehci,
2226                                                         q.itd->hw_next);
2227                                                 q = *q_p;
2228                                                 break;
2229                                         }
2230                                 }
2231
2232                                 /* Take finished ITDs out of the schedule
2233                                  * and process them:  recycle, maybe report
2234                                  * URB completion.  HC won't cache the
2235                                  * pointer for much longer, if at all.
2236                                  */
2237                                 *q_p = q.itd->itd_next;
2238                                 *hw_p = q.itd->hw_next;
2239                                 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2240                                 wmb();
2241                                 modified = itd_complete (ehci, q.itd);
2242                                 q = *q_p;
2243                                 break;
2244                         case Q_TYPE_SITD:
2245                                 /* If this SITD is still active, leave it for
2246                                  * later processing ... check the next entry.
2247                                  * No need to check for activity unless the
2248                                  * frame is current.
2249                                  */
2250                                 if (frame == clock_frame && live &&
2251                                                 (q.sitd->hw_results &
2252                                                         SITD_ACTIVE(ehci))) {
2253                                         incomplete = true;
2254                                         q_p = &q.sitd->sitd_next;
2255                                         hw_p = &q.sitd->hw_next;
2256                                         type = Q_NEXT_TYPE(ehci,
2257                                                         q.sitd->hw_next);
2258                                         q = *q_p;
2259                                         break;
2260                                 }
2261
2262                                 /* Take finished SITDs out of the schedule
2263                                  * and process them:  recycle, maybe report
2264                                  * URB completion.
2265                                  */
2266                                 *q_p = q.sitd->sitd_next;
2267                                 *hw_p = q.sitd->hw_next;
2268                                 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2269                                 wmb();
2270                                 modified = sitd_complete (ehci, q.sitd);
2271                                 q = *q_p;
2272                                 break;
2273                         default:
2274                                 dbg ("corrupt type %d frame %d shadow %p",
2275                                         type, frame, q.ptr);
2276                                 // BUG ();
2277                                 q.ptr = NULL;
2278                         }
2279
2280                         /* assume completion callbacks modify the queue */
2281                         if (unlikely (modified)) {
2282                                 if (likely(ehci->periodic_sched > 0))
2283                                         goto restart;
2284                                 /* short-circuit this scan */
2285                                 now_uframe = clock;
2286                                 break;
2287                         }
2288                 }
2289
2290                 /* If we can tell we caught up to the hardware, stop now.
2291                  * We can't advance our scan without collecting the ISO
2292                  * transfers that are still pending in this frame.
2293                  */
2294                 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2295                         ehci->next_uframe = now_uframe;
2296                         break;
2297                 }
2298
2299                 // FIXME:  this assumes we won't get lapped when
2300                 // latencies climb; that should be rare, but...
2301                 // detect it, and just go all the way around.
2302                 // FLR might help detect this case, so long as latencies
2303                 // don't exceed periodic_size msec (default 1.024 sec).
2304
2305                 // FIXME:  likewise assumes HC doesn't halt mid-scan
2306
2307                 if (now_uframe == clock) {
2308                         unsigned        now;
2309
2310                         if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2311                                         || ehci->periodic_sched == 0)
2312                                 break;
2313                         ehci->next_uframe = now_uframe;
2314                         now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
2315                         if (now_uframe == now)
2316                                 break;
2317
2318                         /* rescan the rest of this frame, then ... */
2319                         clock = now;
2320                         clock_frame = clock >> 3;
2321                         if (ehci->clock_frame != clock_frame) {
2322                                 free_cached_itd_list(ehci);
2323                                 ehci->clock_frame = clock_frame;
2324                         }
2325                 } else {
2326                         now_uframe++;
2327                         now_uframe %= mod;
2328                 }
2329         }
2330 }