2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 /* this file is part of ehci-hcd.c */
22 /*-------------------------------------------------------------------------*/
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
37 static int ehci_get_frame (struct usb_hcd *hcd);
39 /*-------------------------------------------------------------------------*/
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
46 static union ehci_shadow *
47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
50 switch (hc32_to_cpu(ehci, tag)) {
52 return &periodic->qh->qh_next;
54 return &periodic->fstn->fstn_next;
56 return &periodic->itd->itd_next;
59 return &periodic->sitd->sitd_next;
64 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
67 switch (hc32_to_cpu(ehci, tag)) {
68 /* our ehci_shadow.qh is actually software part */
70 return &periodic->qh->hw->hw_next;
71 /* others are hw parts */
73 return periodic->hw_next;
77 /* caller must hold ehci->lock */
78 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
80 union ehci_shadow *prev_p = &ehci->pshadow[frame];
81 __hc32 *hw_p = &ehci->periodic[frame];
82 union ehci_shadow here = *prev_p;
84 /* find predecessor of "ptr"; hw and shadow lists are in sync */
85 while (here.ptr && here.ptr != ptr) {
86 prev_p = periodic_next_shadow(ehci, prev_p,
87 Q_NEXT_TYPE(ehci, *hw_p));
88 hw_p = shadow_next_periodic(ehci, &here,
89 Q_NEXT_TYPE(ehci, *hw_p));
92 /* an interrupt entry (at list end) could have been shared */
96 /* update shadow and hardware lists ... the old "next" pointers
97 * from ptr may still be in use, the caller updates them.
99 *prev_p = *periodic_next_shadow(ehci, &here,
100 Q_NEXT_TYPE(ehci, *hw_p));
102 if (!ehci->use_dummy_qh ||
103 *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
104 != EHCI_LIST_END(ehci))
105 *hw_p = *shadow_next_periodic(ehci, &here,
106 Q_NEXT_TYPE(ehci, *hw_p));
108 *hw_p = ehci->dummy->qh_dma;
111 /* how many of the uframe's 125 usecs are allocated? */
112 static unsigned short
113 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
115 __hc32 *hw_p = &ehci->periodic [frame];
116 union ehci_shadow *q = &ehci->pshadow [frame];
118 struct ehci_qh_hw *hw;
121 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
124 /* is it in the S-mask? */
125 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
126 usecs += q->qh->usecs;
128 if (hw->hw_info2 & cpu_to_hc32(ehci,
130 usecs += q->qh->c_usecs;
136 /* for "save place" FSTNs, count the relevant INTR
137 * bandwidth from the previous frame
139 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
140 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
142 hw_p = &q->fstn->hw_next;
143 q = &q->fstn->fstn_next;
146 if (q->itd->hw_transaction[uframe])
147 usecs += q->itd->stream->usecs;
148 hw_p = &q->itd->hw_next;
149 q = &q->itd->itd_next;
152 /* is it in the S-mask? (count SPLIT, DATA) */
153 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
155 if (q->sitd->hw_fullspeed_ep &
156 cpu_to_hc32(ehci, 1<<31))
157 usecs += q->sitd->stream->usecs;
158 else /* worst case for OUT start-split */
159 usecs += HS_USECS_ISO (188);
162 /* ... C-mask? (count CSPLIT, DATA) */
163 if (q->sitd->hw_uframe &
164 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
165 /* worst case for IN complete-split */
166 usecs += q->sitd->stream->c_usecs;
169 hw_p = &q->sitd->hw_next;
170 q = &q->sitd->sitd_next;
176 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
177 frame * 8 + uframe, usecs);
182 /*-------------------------------------------------------------------------*/
184 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
186 if (!dev1->tt || !dev2->tt)
188 if (dev1->tt != dev2->tt)
191 return dev1->ttport == dev2->ttport;
196 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
198 /* Which uframe does the low/fullspeed transfer start in?
200 * The parameter is the mask of ssplits in "H-frame" terms
201 * and this returns the transfer start uframe in "B-frame" terms,
202 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
203 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
204 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
206 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
208 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
210 ehci_err(ehci, "invalid empty smask!\n");
211 /* uframe 7 can't have bw so this will indicate failure */
214 return ffs(smask) - 1;
217 static const unsigned char
218 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
220 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
221 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
224 for (i=0; i<7; i++) {
225 if (max_tt_usecs[i] < tt_usecs[i]) {
226 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
227 tt_usecs[i] = max_tt_usecs[i];
232 /* How many of the tt's periodic downstream 1000 usecs are allocated?
234 * While this measures the bandwidth in terms of usecs/uframe,
235 * the low/fullspeed bus has no notion of uframes, so any particular
236 * low/fullspeed transfer can "carry over" from one uframe to the next,
237 * since the TT just performs downstream transfers in sequence.
239 * For example two separate 100 usec transfers can start in the same uframe,
240 * and the second one would "carry over" 75 usecs into the next uframe.
244 struct ehci_hcd *ehci,
245 struct usb_device *dev,
247 unsigned short tt_usecs[8]
250 __hc32 *hw_p = &ehci->periodic [frame];
251 union ehci_shadow *q = &ehci->pshadow [frame];
254 memset(tt_usecs, 0, 16);
257 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
259 hw_p = &q->itd->hw_next;
260 q = &q->itd->itd_next;
263 if (same_tt(dev, q->qh->dev)) {
264 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
265 tt_usecs[uf] += q->qh->tt_usecs;
267 hw_p = &q->qh->hw->hw_next;
271 if (same_tt(dev, q->sitd->urb->dev)) {
272 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
273 tt_usecs[uf] += q->sitd->stream->tt_usecs;
275 hw_p = &q->sitd->hw_next;
276 q = &q->sitd->sitd_next;
280 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
282 hw_p = &q->fstn->hw_next;
283 q = &q->fstn->fstn_next;
287 carryover_tt_bandwidth(tt_usecs);
289 if (max_tt_usecs[7] < tt_usecs[7])
290 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
291 frame, tt_usecs[7] - max_tt_usecs[7]);
295 * Return true if the device's tt's downstream bus is available for a
296 * periodic transfer of the specified length (usecs), starting at the
297 * specified frame/uframe. Note that (as summarized in section 11.19
298 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
301 * The uframe parameter is when the fullspeed/lowspeed transfer
302 * should be executed in "B-frame" terms, which is the same as the
303 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
304 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
305 * See the EHCI spec sec 4.5 and fig 4.7.
307 * This checks if the full/lowspeed bus, at the specified starting uframe,
308 * has the specified bandwidth available, according to rules listed
309 * in USB 2.0 spec section 11.18.1 fig 11-60.
311 * This does not check if the transfer would exceed the max ssplit
312 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
313 * since proper scheduling limits ssplits to less than 16 per uframe.
315 static int tt_available (
316 struct ehci_hcd *ehci,
318 struct usb_device *dev,
324 if ((period == 0) || (uframe >= 7)) /* error */
327 for (; frame < ehci->periodic_size; frame += period) {
328 unsigned short tt_usecs[8];
330 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
332 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
333 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
334 frame, usecs, uframe,
335 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
336 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
338 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
339 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
344 /* special case for isoc transfers larger than 125us:
345 * the first and each subsequent fully used uframe
346 * must be empty, so as to not illegally delay
347 * already scheduled transactions
350 int ufs = (usecs / 125);
352 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
353 if (0 < tt_usecs[i]) {
355 "multi-uframe xfer can't fit "
356 "in frame %d uframe %d\n",
362 tt_usecs[uframe] += usecs;
364 carryover_tt_bandwidth(tt_usecs);
366 /* fail if the carryover pushed bw past the last uframe's limit */
367 if (max_tt_usecs[7] < tt_usecs[7]) {
369 "tt unavailable usecs %d frame %d uframe %d\n",
370 usecs, frame, uframe);
380 /* return true iff the device's transaction translator is available
381 * for a periodic transfer starting at the specified frame, using
382 * all the uframes in the mask.
384 static int tt_no_collision (
385 struct ehci_hcd *ehci,
387 struct usb_device *dev,
392 if (period == 0) /* error */
395 /* note bandwidth wastage: split never follows csplit
396 * (different dev or endpoint) until the next uframe.
397 * calling convention doesn't make that distinction.
399 for (; frame < ehci->periodic_size; frame += period) {
400 union ehci_shadow here;
402 struct ehci_qh_hw *hw;
404 here = ehci->pshadow [frame];
405 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
407 switch (hc32_to_cpu(ehci, type)) {
409 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
410 here = here.itd->itd_next;
414 if (same_tt (dev, here.qh->dev)) {
417 mask = hc32_to_cpu(ehci,
419 /* "knows" no gap is needed */
424 type = Q_NEXT_TYPE(ehci, hw->hw_next);
425 here = here.qh->qh_next;
428 if (same_tt (dev, here.sitd->urb->dev)) {
431 mask = hc32_to_cpu(ehci, here.sitd
433 /* FIXME assumes no gap for IN! */
438 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
439 here = here.sitd->sitd_next;
444 "periodic frame %d bogus type %d\n",
448 /* collision or error */
457 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
459 /*-------------------------------------------------------------------------*/
461 static int enable_periodic (struct ehci_hcd *ehci)
466 if (ehci->periodic_sched++)
469 /* did clearing PSE did take effect yet?
470 * takes effect only at frame boundaries...
472 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
473 STS_PSS, 0, 9 * 125);
477 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
478 ehci_writel(ehci, cmd, &ehci->regs->command);
479 /* posted write ... PSS happens later */
480 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
482 /* make sure ehci_work scans these */
483 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
484 % (ehci->periodic_size << 3);
485 if (unlikely(ehci->broken_periodic))
486 ehci->last_periodic_enable = ktime_get_real();
490 static int disable_periodic (struct ehci_hcd *ehci)
495 if (--ehci->periodic_sched)
498 if (unlikely(ehci->broken_periodic)) {
499 /* delay experimentally determined */
500 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
501 ktime_t now = ktime_get_real();
502 s64 delay = ktime_us_delta(safe, now);
504 if (unlikely(delay > 0))
508 /* did setting PSE not take effect yet?
509 * takes effect only at frame boundaries...
511 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
512 STS_PSS, STS_PSS, 9 * 125);
516 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
517 ehci_writel(ehci, cmd, &ehci->regs->command);
518 /* posted write ... */
520 free_cached_lists(ehci);
522 ehci->next_uframe = -1;
526 /*-------------------------------------------------------------------------*/
528 /* periodic schedule slots have iso tds (normal or split) first, then a
529 * sparse tree for active interrupt transfers.
531 * this just links in a qh; caller guarantees uframe masks are set right.
532 * no FSTN support (yet; ehci 0.96+)
534 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
537 unsigned period = qh->period;
539 dev_dbg (&qh->dev->dev,
540 "link qh%d-%04x/%p start %d [%d/%d us]\n",
541 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
542 & (QH_CMASK | QH_SMASK),
543 qh, qh->start, qh->usecs, qh->c_usecs);
545 /* high bandwidth, or otherwise every microframe */
549 for (i = qh->start; i < ehci->periodic_size; i += period) {
550 union ehci_shadow *prev = &ehci->pshadow[i];
551 __hc32 *hw_p = &ehci->periodic[i];
552 union ehci_shadow here = *prev;
555 /* skip the iso nodes at list head */
557 type = Q_NEXT_TYPE(ehci, *hw_p);
558 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
560 prev = periodic_next_shadow(ehci, prev, type);
561 hw_p = shadow_next_periodic(ehci, &here, type);
565 /* sorting each branch by period (slow-->fast)
566 * enables sharing interior tree nodes
568 while (here.ptr && qh != here.qh) {
569 if (qh->period > here.qh->period)
571 prev = &here.qh->qh_next;
572 hw_p = &here.qh->hw->hw_next;
575 /* link in this qh, unless some earlier pass did that */
579 qh->hw->hw_next = *hw_p;
582 *hw_p = QH_NEXT (ehci, qh->qh_dma);
585 qh->qh_state = QH_STATE_LINKED;
589 /* update per-qh bandwidth for usbfs */
590 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
591 ? ((qh->usecs + qh->c_usecs) / qh->period)
594 /* maybe enable periodic schedule processing */
595 return enable_periodic(ehci);
598 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
604 // IF this isn't high speed
605 // and this qh is active in the current uframe
606 // (and overlay token SplitXstate is false?)
608 // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
610 /* high bandwidth, or otherwise part of every microframe */
611 if ((period = qh->period) == 0)
614 for (i = qh->start; i < ehci->periodic_size; i += period)
615 periodic_unlink (ehci, i, qh);
617 /* update per-qh bandwidth for usbfs */
618 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
619 ? ((qh->usecs + qh->c_usecs) / qh->period)
622 dev_dbg (&qh->dev->dev,
623 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
625 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
626 qh, qh->start, qh->usecs, qh->c_usecs);
628 /* qh->qh_next still "live" to HC */
629 qh->qh_state = QH_STATE_UNLINK;
630 qh->qh_next.ptr = NULL;
633 /* maybe turn off periodic schedule */
634 return disable_periodic(ehci);
637 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
640 struct ehci_qh_hw *hw = qh->hw;
643 /* If the QH isn't linked then there's nothing we can do
644 * unless we were called during a giveback, in which case
645 * qh_completions() has to deal with it.
647 if (qh->qh_state != QH_STATE_LINKED) {
648 if (qh->qh_state == QH_STATE_COMPLETING)
649 qh->needs_rescan = 1;
653 qh_unlink_periodic (ehci, qh);
655 /* simple/paranoid: always delay, expecting the HC needs to read
656 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
657 * expect khubd to clean up after any CSPLITs we won't issue.
658 * active high speed queues may need bigger delays...
660 if (list_empty (&qh->qtd_list)
661 || (cpu_to_hc32(ehci, QH_CMASK)
662 & hw->hw_info2) != 0)
665 wait = 55; /* worst case: 3 * 1024 */
668 qh->qh_state = QH_STATE_IDLE;
669 hw->hw_next = EHCI_LIST_END(ehci);
672 qh_completions(ehci, qh);
674 /* reschedule QH iff another request is queued */
675 if (!list_empty(&qh->qtd_list) &&
676 HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
677 rc = qh_schedule(ehci, qh);
679 /* An error here likely indicates handshake failure
680 * or no space left in the schedule. Neither fault
681 * should happen often ...
683 * FIXME kill the now-dysfunctional queued urbs
686 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
691 /*-------------------------------------------------------------------------*/
693 static int check_period (
694 struct ehci_hcd *ehci,
702 /* complete split running into next frame?
703 * given FSTN support, we could sometimes check...
709 * 80% periodic == 100 usec/uframe available
710 * convert "usecs we need" to "max already claimed"
714 /* we "know" 2 and 4 uframe intervals were rejected; so
715 * for period 0, check _every_ microframe in the schedule.
717 if (unlikely (period == 0)) {
719 for (uframe = 0; uframe < 7; uframe++) {
720 claimed = periodic_usecs (ehci, frame, uframe);
724 } while ((frame += 1) < ehci->periodic_size);
726 /* just check the specified uframe, at that period */
729 claimed = periodic_usecs (ehci, frame, uframe);
732 } while ((frame += period) < ehci->periodic_size);
739 static int check_intr_schedule (
740 struct ehci_hcd *ehci,
743 const struct ehci_qh *qh,
747 int retval = -ENOSPC;
750 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
753 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
761 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
762 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
766 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
767 for (i=uframe+1; i<8 && i<uframe+4; i++)
768 if (!check_period (ehci, frame, i,
769 qh->period, qh->c_usecs))
776 *c_maskp = cpu_to_hc32(ehci, mask << 8);
779 /* Make sure this tt's buffer is also available for CSPLITs.
780 * We pessimize a bit; probably the typical full speed case
781 * doesn't need the second CSPLIT.
783 * NOTE: both SPLIT and CSPLIT could be checked in just
786 mask = 0x03 << (uframe + qh->gap_uf);
787 *c_maskp = cpu_to_hc32(ehci, mask << 8);
790 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
791 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
792 qh->period, qh->c_usecs))
794 if (!check_period (ehci, frame, uframe + qh->gap_uf,
795 qh->period, qh->c_usecs))
804 /* "first fit" scheduling policy used the first time through,
805 * or when the previous schedule slot can't be re-used.
807 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
812 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
813 struct ehci_qh_hw *hw = qh->hw;
815 qh_refresh(ehci, qh);
816 hw->hw_next = EHCI_LIST_END(ehci);
819 /* reuse the previous schedule slots, if we can */
820 if (frame < qh->period) {
821 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
822 status = check_intr_schedule (ehci, frame, --uframe,
830 /* else scan the schedule to find a group of slots such that all
831 * uframes have enough periodic bandwidth available.
834 /* "normal" case, uframing flexible except with splits */
838 for (i = qh->period; status && i > 0; --i) {
839 frame = ++ehci->random_frame % qh->period;
840 for (uframe = 0; uframe < 8; uframe++) {
841 status = check_intr_schedule (ehci,
849 /* qh->period == 0 means every uframe */
852 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
858 /* reset S-frame and (maybe) C-frame masks */
859 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
860 hw->hw_info2 |= qh->period
861 ? cpu_to_hc32(ehci, 1 << uframe)
862 : cpu_to_hc32(ehci, QH_SMASK);
863 hw->hw_info2 |= c_mask;
865 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
867 /* stuff into the periodic schedule */
868 status = qh_link_periodic (ehci, qh);
873 static int intr_submit (
874 struct ehci_hcd *ehci,
876 struct list_head *qtd_list,
883 struct list_head empty;
885 /* get endpoint and transfer/schedule data */
886 epnum = urb->ep->desc.bEndpointAddress;
888 spin_lock_irqsave (&ehci->lock, flags);
890 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
892 goto done_not_linked;
894 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
895 if (unlikely(status))
896 goto done_not_linked;
898 /* get qh and force any scheduling errors */
899 INIT_LIST_HEAD (&empty);
900 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
905 if (qh->qh_state == QH_STATE_IDLE) {
906 if ((status = qh_schedule (ehci, qh)) != 0)
910 /* then queue the urb's tds to the qh */
911 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
914 /* ... update usbfs periodic stats */
915 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
918 if (unlikely(status))
919 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
921 spin_unlock_irqrestore (&ehci->lock, flags);
923 qtd_list_free (ehci, urb, qtd_list);
928 /*-------------------------------------------------------------------------*/
930 /* ehci_iso_stream ops work with both ITD and SITD */
932 static struct ehci_iso_stream *
933 iso_stream_alloc (gfp_t mem_flags)
935 struct ehci_iso_stream *stream;
937 stream = kzalloc(sizeof *stream, mem_flags);
938 if (likely (stream != NULL)) {
939 INIT_LIST_HEAD(&stream->td_list);
940 INIT_LIST_HEAD(&stream->free_list);
941 stream->next_uframe = -1;
942 stream->refcount = 1;
949 struct ehci_hcd *ehci,
950 struct ehci_iso_stream *stream,
951 struct usb_device *dev,
956 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
959 unsigned epnum, maxp;
964 * this might be a "high bandwidth" highspeed endpoint,
965 * as encoded in the ep descriptor's wMaxPacket field
967 epnum = usb_pipeendpoint (pipe);
968 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
969 maxp = usb_maxpacket(dev, pipe, !is_input);
976 /* knows about ITD vs SITD */
977 if (dev->speed == USB_SPEED_HIGH) {
978 unsigned multi = hb_mult(maxp);
980 stream->highspeed = 1;
982 maxp = max_packet(maxp);
986 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
987 stream->buf1 = cpu_to_hc32(ehci, buf1);
988 stream->buf2 = cpu_to_hc32(ehci, multi);
990 /* usbfs wants to report the average usecs per frame tied up
991 * when transfers on this endpoint are scheduled ...
993 stream->usecs = HS_USECS_ISO (maxp);
994 bandwidth = stream->usecs * 8;
995 bandwidth /= interval;
1002 addr = dev->ttport << 24;
1003 if (!ehci_is_TDI(ehci)
1005 ehci_to_hcd(ehci)->self.root_hub))
1006 addr |= dev->tt->hub->devnum << 16;
1008 addr |= dev->devnum;
1009 stream->usecs = HS_USECS_ISO (maxp);
1010 think_time = dev->tt ? dev->tt->think_time : 0;
1011 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1012 dev->speed, is_input, 1, maxp));
1013 hs_transfers = max (1u, (maxp + 187) / 188);
1018 stream->c_usecs = stream->usecs;
1019 stream->usecs = HS_USECS_ISO (1);
1020 stream->raw_mask = 1;
1022 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1023 tmp = (1 << (hs_transfers + 2)) - 1;
1024 stream->raw_mask |= tmp << (8 + 2);
1026 stream->raw_mask = smask_out [hs_transfers - 1];
1027 bandwidth = stream->usecs + stream->c_usecs;
1028 bandwidth /= interval << 3;
1030 /* stream->splits gets created from raw_mask later */
1031 stream->address = cpu_to_hc32(ehci, addr);
1033 stream->bandwidth = bandwidth;
1037 stream->bEndpointAddress = is_input | epnum;
1038 stream->interval = interval;
1039 stream->maxp = maxp;
1043 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1047 /* free whenever just a dev->ep reference remains.
1048 * not like a QH -- no persistent state (toggle, halt)
1050 if (stream->refcount == 1) {
1053 // BUG_ON (!list_empty(&stream->td_list));
1055 while (!list_empty (&stream->free_list)) {
1056 struct list_head *entry;
1058 entry = stream->free_list.next;
1061 /* knows about ITD vs SITD */
1062 if (stream->highspeed) {
1063 struct ehci_itd *itd;
1065 itd = list_entry (entry, struct ehci_itd,
1067 dma_pool_free (ehci->itd_pool, itd,
1070 struct ehci_sitd *sitd;
1072 sitd = list_entry (entry, struct ehci_sitd,
1074 dma_pool_free (ehci->sitd_pool, sitd,
1079 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1080 stream->bEndpointAddress &= 0x0f;
1082 stream->ep->hcpriv = NULL;
1088 static inline struct ehci_iso_stream *
1089 iso_stream_get (struct ehci_iso_stream *stream)
1091 if (likely (stream != NULL))
1096 static struct ehci_iso_stream *
1097 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1100 struct ehci_iso_stream *stream;
1101 struct usb_host_endpoint *ep;
1102 unsigned long flags;
1104 epnum = usb_pipeendpoint (urb->pipe);
1105 if (usb_pipein(urb->pipe))
1106 ep = urb->dev->ep_in[epnum];
1108 ep = urb->dev->ep_out[epnum];
1110 spin_lock_irqsave (&ehci->lock, flags);
1111 stream = ep->hcpriv;
1113 if (unlikely (stream == NULL)) {
1114 stream = iso_stream_alloc(GFP_ATOMIC);
1115 if (likely (stream != NULL)) {
1116 /* dev->ep owns the initial refcount */
1117 ep->hcpriv = stream;
1119 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1123 /* if dev->ep [epnum] is a QH, hw is set */
1124 } else if (unlikely (stream->hw != NULL)) {
1125 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1126 urb->dev->devpath, epnum,
1127 usb_pipein(urb->pipe) ? "in" : "out");
1131 /* caller guarantees an eventual matching iso_stream_put */
1132 stream = iso_stream_get (stream);
1134 spin_unlock_irqrestore (&ehci->lock, flags);
1138 /*-------------------------------------------------------------------------*/
1140 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1142 static struct ehci_iso_sched *
1143 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1145 struct ehci_iso_sched *iso_sched;
1146 int size = sizeof *iso_sched;
1148 size += packets * sizeof (struct ehci_iso_packet);
1149 iso_sched = kzalloc(size, mem_flags);
1150 if (likely (iso_sched != NULL)) {
1151 INIT_LIST_HEAD (&iso_sched->td_list);
1158 struct ehci_hcd *ehci,
1159 struct ehci_iso_sched *iso_sched,
1160 struct ehci_iso_stream *stream,
1165 dma_addr_t dma = urb->transfer_dma;
1167 /* how many uframes are needed for these transfers */
1168 iso_sched->span = urb->number_of_packets * stream->interval;
1170 /* figure out per-uframe itd fields that we'll need later
1171 * when we fit new itds into the schedule.
1173 for (i = 0; i < urb->number_of_packets; i++) {
1174 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1179 length = urb->iso_frame_desc [i].length;
1180 buf = dma + urb->iso_frame_desc [i].offset;
1182 trans = EHCI_ISOC_ACTIVE;
1183 trans |= buf & 0x0fff;
1184 if (unlikely (((i + 1) == urb->number_of_packets))
1185 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1186 trans |= EHCI_ITD_IOC;
1187 trans |= length << 16;
1188 uframe->transaction = cpu_to_hc32(ehci, trans);
1190 /* might need to cross a buffer page within a uframe */
1191 uframe->bufp = (buf & ~(u64)0x0fff);
1193 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1200 struct ehci_iso_stream *stream,
1201 struct ehci_iso_sched *iso_sched
1206 // caller must hold ehci->lock!
1207 list_splice (&iso_sched->td_list, &stream->free_list);
1212 itd_urb_transaction (
1213 struct ehci_iso_stream *stream,
1214 struct ehci_hcd *ehci,
1219 struct ehci_itd *itd;
1223 struct ehci_iso_sched *sched;
1224 unsigned long flags;
1226 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1227 if (unlikely (sched == NULL))
1230 itd_sched_init(ehci, sched, stream, urb);
1232 if (urb->interval < 8)
1233 num_itds = 1 + (sched->span + 7) / 8;
1235 num_itds = urb->number_of_packets;
1237 /* allocate/init ITDs */
1238 spin_lock_irqsave (&ehci->lock, flags);
1239 for (i = 0; i < num_itds; i++) {
1241 /* free_list.next might be cache-hot ... but maybe
1242 * the HC caches it too. avoid that issue for now.
1245 /* prefer previously-allocated itds */
1246 if (likely (!list_empty(&stream->free_list))) {
1247 itd = list_entry (stream->free_list.prev,
1248 struct ehci_itd, itd_list);
1249 list_del (&itd->itd_list);
1250 itd_dma = itd->itd_dma;
1252 spin_unlock_irqrestore (&ehci->lock, flags);
1253 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1255 spin_lock_irqsave (&ehci->lock, flags);
1257 iso_sched_free(stream, sched);
1258 spin_unlock_irqrestore(&ehci->lock, flags);
1263 memset (itd, 0, sizeof *itd);
1264 itd->itd_dma = itd_dma;
1265 list_add (&itd->itd_list, &sched->td_list);
1267 spin_unlock_irqrestore (&ehci->lock, flags);
1269 /* temporarily store schedule info in hcpriv */
1270 urb->hcpriv = sched;
1271 urb->error_count = 0;
1275 /*-------------------------------------------------------------------------*/
1279 struct ehci_hcd *ehci,
1288 /* can't commit more than 80% periodic == 100 usec */
1289 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1293 /* we know urb->interval is 2^N uframes */
1295 } while (uframe < mod);
1301 struct ehci_hcd *ehci,
1303 struct ehci_iso_stream *stream,
1305 struct ehci_iso_sched *sched,
1312 mask = stream->raw_mask << (uframe & 7);
1314 /* for IN, don't wrap CSPLIT into the next frame */
1318 /* this multi-pass logic is simple, but performance may
1319 * suffer when the schedule data isn't cached.
1322 /* check bandwidth */
1323 uframe %= period_uframes;
1327 frame = uframe >> 3;
1330 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1331 /* The tt's fullspeed bus bandwidth must be available.
1332 * tt_available scheduling guarantees 10+% for control/bulk.
1334 if (!tt_available (ehci, period_uframes << 3,
1335 stream->udev, frame, uf, stream->tt_usecs))
1338 /* tt must be idle for start(s), any gap, and csplit.
1339 * assume scheduling slop leaves 10+% for control/bulk.
1341 if (!tt_no_collision (ehci, period_uframes << 3,
1342 stream->udev, frame, mask))
1346 /* check starts (OUT uses more than one) */
1347 max_used = 100 - stream->usecs;
1348 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1349 if (periodic_usecs (ehci, frame, uf) > max_used)
1353 /* for IN, check CSPLIT */
1354 if (stream->c_usecs) {
1356 max_used = 100 - stream->c_usecs;
1360 if ((stream->raw_mask & tmp) == 0)
1362 if (periodic_usecs (ehci, frame, uf)
1368 /* we know urb->interval is 2^N uframes */
1369 uframe += period_uframes;
1370 } while (uframe < mod);
1372 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1377 * This scheduler plans almost as far into the future as it has actual
1378 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1379 * "as small as possible" to be cache-friendlier.) That limits the size
1380 * transfers you can stream reliably; avoid more than 64 msec per urb.
1381 * Also avoid queue depths of less than ehci's worst irq latency (affected
1382 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1383 * and other factors); or more than about 230 msec total (for portability,
1384 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1387 #define SCHEDULE_SLOP 80 /* microframes */
1390 iso_stream_schedule (
1391 struct ehci_hcd *ehci,
1393 struct ehci_iso_stream *stream
1396 u32 now, next, start, period, span;
1398 unsigned mod = ehci->periodic_size << 3;
1399 struct ehci_iso_sched *sched = urb->hcpriv;
1401 period = urb->interval;
1403 if (!stream->highspeed) {
1408 if (span > mod - SCHEDULE_SLOP) {
1409 ehci_dbg (ehci, "iso request %p too long\n", urb);
1414 now = ehci_readl(ehci, &ehci->regs->frame_index) & (mod - 1);
1416 /* Typical case: reuse current schedule, stream is still active.
1417 * Hopefully there are no gaps from the host falling behind
1418 * (irq delays etc), but if there are we'll take the next
1419 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1421 if (likely (!list_empty (&stream->td_list))) {
1424 /* For high speed devices, allow scheduling within the
1425 * isochronous scheduling threshold. For full speed devices
1426 * and Intel PCI-based controllers, don't (work around for
1429 if (!stream->highspeed && ehci->fs_i_thresh)
1430 next = now + ehci->i_thresh;
1434 /* Fell behind (by up to twice the slop amount)?
1435 * We decide based on the time of the last currently-scheduled
1436 * slot, not the time of the next available slot.
1438 excess = (stream->next_uframe - period - next) & (mod - 1);
1439 if (excess >= mod - 2 * SCHEDULE_SLOP)
1440 start = next + excess - mod + period *
1441 DIV_ROUND_UP(mod - excess, period);
1443 start = next + excess + period;
1444 if (start - now >= mod) {
1445 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1446 urb, start - now - period, period,
1453 /* need to schedule; when's the next (u)frame we could start?
1454 * this is bigger than ehci->i_thresh allows; scheduling itself
1455 * isn't free, the slop should handle reasonably slow cpus. it
1456 * can also help high bandwidth if the dma and irq loads don't
1457 * jump until after the queue is primed.
1460 start = SCHEDULE_SLOP + (now & ~0x07);
1462 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1464 /* find a uframe slot with enough bandwidth */
1465 next = start + period;
1466 for (; start < next; start++) {
1468 /* check schedule: enough space? */
1469 if (stream->highspeed) {
1470 if (itd_slot_ok(ehci, mod, start,
1471 stream->usecs, period))
1474 if ((start % 8) >= 6)
1476 if (sitd_slot_ok(ehci, mod, stream,
1477 start, sched, period))
1482 /* no room in the schedule */
1483 if (start == next) {
1484 ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n",
1485 urb, now, now + mod);
1491 /* Tried to schedule too far into the future? */
1492 if (unlikely(start - now + span - period
1493 >= mod - 2 * SCHEDULE_SLOP)) {
1494 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1495 urb, start - now, span - period,
1496 mod - 2 * SCHEDULE_SLOP);
1501 stream->next_uframe = start & (mod - 1);
1503 /* report high speed start in uframes; full speed, in frames */
1504 urb->start_frame = stream->next_uframe;
1505 if (!stream->highspeed)
1506 urb->start_frame >>= 3;
1510 iso_sched_free(stream, sched);
1515 /*-------------------------------------------------------------------------*/
1518 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1519 struct ehci_itd *itd)
1523 /* it's been recently zeroed */
1524 itd->hw_next = EHCI_LIST_END(ehci);
1525 itd->hw_bufp [0] = stream->buf0;
1526 itd->hw_bufp [1] = stream->buf1;
1527 itd->hw_bufp [2] = stream->buf2;
1529 for (i = 0; i < 8; i++)
1532 /* All other fields are filled when scheduling */
1537 struct ehci_hcd *ehci,
1538 struct ehci_itd *itd,
1539 struct ehci_iso_sched *iso_sched,
1544 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1545 unsigned pg = itd->pg;
1547 // BUG_ON (pg == 6 && uf->cross);
1550 itd->index [uframe] = index;
1552 itd->hw_transaction[uframe] = uf->transaction;
1553 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1554 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1555 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1557 /* iso_frame_desc[].offset must be strictly increasing */
1558 if (unlikely (uf->cross)) {
1559 u64 bufp = uf->bufp + 4096;
1562 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1563 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1568 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1570 union ehci_shadow *prev = &ehci->pshadow[frame];
1571 __hc32 *hw_p = &ehci->periodic[frame];
1572 union ehci_shadow here = *prev;
1575 /* skip any iso nodes which might belong to previous microframes */
1577 type = Q_NEXT_TYPE(ehci, *hw_p);
1578 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1580 prev = periodic_next_shadow(ehci, prev, type);
1581 hw_p = shadow_next_periodic(ehci, &here, type);
1585 itd->itd_next = here;
1586 itd->hw_next = *hw_p;
1590 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1593 /* fit urb's itds into the selected schedule slot; activate as needed */
1596 struct ehci_hcd *ehci,
1599 struct ehci_iso_stream *stream
1603 unsigned next_uframe, uframe, frame;
1604 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1605 struct ehci_itd *itd;
1607 next_uframe = stream->next_uframe & (mod - 1);
1609 if (unlikely (list_empty(&stream->td_list))) {
1610 ehci_to_hcd(ehci)->self.bandwidth_allocated
1611 += stream->bandwidth;
1613 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1614 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1615 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1617 next_uframe >> 3, next_uframe & 0x7);
1619 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1621 /* fill iTDs uframe by uframe */
1622 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1624 /* ASSERT: we have all necessary itds */
1625 // BUG_ON (list_empty (&iso_sched->td_list));
1627 /* ASSERT: no itds for this endpoint in this uframe */
1629 itd = list_entry (iso_sched->td_list.next,
1630 struct ehci_itd, itd_list);
1631 list_move_tail (&itd->itd_list, &stream->td_list);
1632 itd->stream = iso_stream_get (stream);
1634 itd_init (ehci, stream, itd);
1637 uframe = next_uframe & 0x07;
1638 frame = next_uframe >> 3;
1640 itd_patch(ehci, itd, iso_sched, packet, uframe);
1642 next_uframe += stream->interval;
1643 next_uframe &= mod - 1;
1646 /* link completed itds into the schedule */
1647 if (((next_uframe >> 3) != frame)
1648 || packet == urb->number_of_packets) {
1649 itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1653 stream->next_uframe = next_uframe;
1655 /* don't need that schedule data any more */
1656 iso_sched_free (stream, iso_sched);
1659 timer_action (ehci, TIMER_IO_WATCHDOG);
1660 return enable_periodic(ehci);
1663 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1665 /* Process and recycle a completed ITD. Return true iff its urb completed,
1666 * and hence its completion callback probably added things to the hardware
1669 * Note that we carefully avoid recycling this descriptor until after any
1670 * completion callback runs, so that it won't be reused quickly. That is,
1671 * assuming (a) no more than two urbs per frame on this endpoint, and also
1672 * (b) only this endpoint's completions submit URBs. It seems some silicon
1673 * corrupts things if you reuse completed descriptors very quickly...
1677 struct ehci_hcd *ehci,
1678 struct ehci_itd *itd
1680 struct urb *urb = itd->urb;
1681 struct usb_iso_packet_descriptor *desc;
1685 struct ehci_iso_stream *stream = itd->stream;
1686 struct usb_device *dev;
1687 unsigned retval = false;
1689 /* for each uframe with a packet */
1690 for (uframe = 0; uframe < 8; uframe++) {
1691 if (likely (itd->index[uframe] == -1))
1693 urb_index = itd->index[uframe];
1694 desc = &urb->iso_frame_desc [urb_index];
1696 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1697 itd->hw_transaction [uframe] = 0;
1699 /* report transfer status */
1700 if (unlikely (t & ISO_ERRS)) {
1702 if (t & EHCI_ISOC_BUF_ERR)
1703 desc->status = usb_pipein (urb->pipe)
1704 ? -ENOSR /* hc couldn't read */
1705 : -ECOMM; /* hc couldn't write */
1706 else if (t & EHCI_ISOC_BABBLE)
1707 desc->status = -EOVERFLOW;
1708 else /* (t & EHCI_ISOC_XACTERR) */
1709 desc->status = -EPROTO;
1711 /* HC need not update length with this error */
1712 if (!(t & EHCI_ISOC_BABBLE)) {
1713 desc->actual_length = EHCI_ITD_LENGTH(t);
1714 urb->actual_length += desc->actual_length;
1716 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1718 desc->actual_length = EHCI_ITD_LENGTH(t);
1719 urb->actual_length += desc->actual_length;
1721 /* URB was too late */
1722 desc->status = -EXDEV;
1726 /* handle completion now? */
1727 if (likely ((urb_index + 1) != urb->number_of_packets))
1730 /* ASSERT: it's really the last itd for this urb
1731 list_for_each_entry (itd, &stream->td_list, itd_list)
1732 BUG_ON (itd->urb == urb);
1735 /* give urb back to the driver; completion often (re)submits */
1737 ehci_urb_done(ehci, urb, 0);
1740 (void) disable_periodic(ehci);
1741 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1743 if (unlikely(list_is_singular(&stream->td_list))) {
1744 ehci_to_hcd(ehci)->self.bandwidth_allocated
1745 -= stream->bandwidth;
1747 "deschedule devp %s ep%d%s-iso\n",
1748 dev->devpath, stream->bEndpointAddress & 0x0f,
1749 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1751 iso_stream_put (ehci, stream);
1755 if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1756 /* OK to recycle this ITD now. */
1758 list_move(&itd->itd_list, &stream->free_list);
1759 iso_stream_put(ehci, stream);
1761 /* HW might remember this ITD, so we can't recycle it yet.
1762 * Move it to a safe place until a new frame starts.
1764 list_move(&itd->itd_list, &ehci->cached_itd_list);
1765 if (stream->refcount == 2) {
1766 /* If iso_stream_put() were called here, stream
1767 * would be freed. Instead, just prevent reuse.
1769 stream->ep->hcpriv = NULL;
1776 /*-------------------------------------------------------------------------*/
1778 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1781 int status = -EINVAL;
1782 unsigned long flags;
1783 struct ehci_iso_stream *stream;
1785 /* Get iso_stream head */
1786 stream = iso_stream_find (ehci, urb);
1787 if (unlikely (stream == NULL)) {
1788 ehci_dbg (ehci, "can't get iso stream\n");
1791 if (unlikely (urb->interval != stream->interval)) {
1792 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1793 stream->interval, urb->interval);
1797 #ifdef EHCI_URB_TRACE
1799 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1800 __func__, urb->dev->devpath, urb,
1801 usb_pipeendpoint (urb->pipe),
1802 usb_pipein (urb->pipe) ? "in" : "out",
1803 urb->transfer_buffer_length,
1804 urb->number_of_packets, urb->interval,
1808 /* allocate ITDs w/o locking anything */
1809 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1810 if (unlikely (status < 0)) {
1811 ehci_dbg (ehci, "can't init itds\n");
1815 /* schedule ... need to lock */
1816 spin_lock_irqsave (&ehci->lock, flags);
1817 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
1818 status = -ESHUTDOWN;
1819 goto done_not_linked;
1821 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1822 if (unlikely(status))
1823 goto done_not_linked;
1824 status = iso_stream_schedule(ehci, urb, stream);
1825 if (likely (status == 0))
1826 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1828 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1830 spin_unlock_irqrestore (&ehci->lock, flags);
1833 if (unlikely (status < 0))
1834 iso_stream_put (ehci, stream);
1838 /*-------------------------------------------------------------------------*/
1841 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1842 * TTs in USB 2.0 hubs. These need microframe scheduling.
1847 struct ehci_hcd *ehci,
1848 struct ehci_iso_sched *iso_sched,
1849 struct ehci_iso_stream *stream,
1854 dma_addr_t dma = urb->transfer_dma;
1856 /* how many frames are needed for these transfers */
1857 iso_sched->span = urb->number_of_packets * stream->interval;
1859 /* figure out per-frame sitd fields that we'll need later
1860 * when we fit new sitds into the schedule.
1862 for (i = 0; i < urb->number_of_packets; i++) {
1863 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1868 length = urb->iso_frame_desc [i].length & 0x03ff;
1869 buf = dma + urb->iso_frame_desc [i].offset;
1871 trans = SITD_STS_ACTIVE;
1872 if (((i + 1) == urb->number_of_packets)
1873 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1875 trans |= length << 16;
1876 packet->transaction = cpu_to_hc32(ehci, trans);
1878 /* might need to cross a buffer page within a td */
1880 packet->buf1 = (buf + length) & ~0x0fff;
1881 if (packet->buf1 != (buf & ~(u64)0x0fff))
1884 /* OUT uses multiple start-splits */
1885 if (stream->bEndpointAddress & USB_DIR_IN)
1887 length = (length + 187) / 188;
1888 if (length > 1) /* BEGIN vs ALL */
1890 packet->buf1 |= length;
1895 sitd_urb_transaction (
1896 struct ehci_iso_stream *stream,
1897 struct ehci_hcd *ehci,
1902 struct ehci_sitd *sitd;
1903 dma_addr_t sitd_dma;
1905 struct ehci_iso_sched *iso_sched;
1906 unsigned long flags;
1908 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1909 if (iso_sched == NULL)
1912 sitd_sched_init(ehci, iso_sched, stream, urb);
1914 /* allocate/init sITDs */
1915 spin_lock_irqsave (&ehci->lock, flags);
1916 for (i = 0; i < urb->number_of_packets; i++) {
1918 /* NOTE: for now, we don't try to handle wraparound cases
1919 * for IN (using sitd->hw_backpointer, like a FSTN), which
1920 * means we never need two sitds for full speed packets.
1923 /* free_list.next might be cache-hot ... but maybe
1924 * the HC caches it too. avoid that issue for now.
1927 /* prefer previously-allocated sitds */
1928 if (!list_empty(&stream->free_list)) {
1929 sitd = list_entry (stream->free_list.prev,
1930 struct ehci_sitd, sitd_list);
1931 list_del (&sitd->sitd_list);
1932 sitd_dma = sitd->sitd_dma;
1934 spin_unlock_irqrestore (&ehci->lock, flags);
1935 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1937 spin_lock_irqsave (&ehci->lock, flags);
1939 iso_sched_free(stream, iso_sched);
1940 spin_unlock_irqrestore(&ehci->lock, flags);
1945 memset (sitd, 0, sizeof *sitd);
1946 sitd->sitd_dma = sitd_dma;
1947 list_add (&sitd->sitd_list, &iso_sched->td_list);
1950 /* temporarily store schedule info in hcpriv */
1951 urb->hcpriv = iso_sched;
1952 urb->error_count = 0;
1954 spin_unlock_irqrestore (&ehci->lock, flags);
1958 /*-------------------------------------------------------------------------*/
1962 struct ehci_hcd *ehci,
1963 struct ehci_iso_stream *stream,
1964 struct ehci_sitd *sitd,
1965 struct ehci_iso_sched *iso_sched,
1969 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1970 u64 bufp = uf->bufp;
1972 sitd->hw_next = EHCI_LIST_END(ehci);
1973 sitd->hw_fullspeed_ep = stream->address;
1974 sitd->hw_uframe = stream->splits;
1975 sitd->hw_results = uf->transaction;
1976 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1979 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1980 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1982 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1985 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1986 sitd->index = index;
1990 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1992 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1993 sitd->sitd_next = ehci->pshadow [frame];
1994 sitd->hw_next = ehci->periodic [frame];
1995 ehci->pshadow [frame].sitd = sitd;
1996 sitd->frame = frame;
1998 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
2001 /* fit urb's sitds into the selected schedule slot; activate as needed */
2004 struct ehci_hcd *ehci,
2007 struct ehci_iso_stream *stream
2011 unsigned next_uframe;
2012 struct ehci_iso_sched *sched = urb->hcpriv;
2013 struct ehci_sitd *sitd;
2015 next_uframe = stream->next_uframe;
2017 if (list_empty(&stream->td_list)) {
2018 /* usbfs ignores TT bandwidth */
2019 ehci_to_hcd(ehci)->self.bandwidth_allocated
2020 += stream->bandwidth;
2022 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2023 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2024 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2025 (next_uframe >> 3) & (ehci->periodic_size - 1),
2026 stream->interval, hc32_to_cpu(ehci, stream->splits));
2028 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2030 /* fill sITDs frame by frame */
2031 for (packet = 0, sitd = NULL;
2032 packet < urb->number_of_packets;
2035 /* ASSERT: we have all necessary sitds */
2036 BUG_ON (list_empty (&sched->td_list));
2038 /* ASSERT: no itds for this endpoint in this frame */
2040 sitd = list_entry (sched->td_list.next,
2041 struct ehci_sitd, sitd_list);
2042 list_move_tail (&sitd->sitd_list, &stream->td_list);
2043 sitd->stream = iso_stream_get (stream);
2046 sitd_patch(ehci, stream, sitd, sched, packet);
2047 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
2050 next_uframe += stream->interval << 3;
2052 stream->next_uframe = next_uframe & (mod - 1);
2054 /* don't need that schedule data any more */
2055 iso_sched_free (stream, sched);
2058 timer_action (ehci, TIMER_IO_WATCHDOG);
2059 return enable_periodic(ehci);
2062 /*-------------------------------------------------------------------------*/
2064 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2065 | SITD_STS_XACT | SITD_STS_MMF)
2067 /* Process and recycle a completed SITD. Return true iff its urb completed,
2068 * and hence its completion callback probably added things to the hardware
2071 * Note that we carefully avoid recycling this descriptor until after any
2072 * completion callback runs, so that it won't be reused quickly. That is,
2073 * assuming (a) no more than two urbs per frame on this endpoint, and also
2074 * (b) only this endpoint's completions submit URBs. It seems some silicon
2075 * corrupts things if you reuse completed descriptors very quickly...
2079 struct ehci_hcd *ehci,
2080 struct ehci_sitd *sitd
2082 struct urb *urb = sitd->urb;
2083 struct usb_iso_packet_descriptor *desc;
2086 struct ehci_iso_stream *stream = sitd->stream;
2087 struct usb_device *dev;
2088 unsigned retval = false;
2090 urb_index = sitd->index;
2091 desc = &urb->iso_frame_desc [urb_index];
2092 t = hc32_to_cpup(ehci, &sitd->hw_results);
2094 /* report transfer status */
2095 if (t & SITD_ERRS) {
2097 if (t & SITD_STS_DBE)
2098 desc->status = usb_pipein (urb->pipe)
2099 ? -ENOSR /* hc couldn't read */
2100 : -ECOMM; /* hc couldn't write */
2101 else if (t & SITD_STS_BABBLE)
2102 desc->status = -EOVERFLOW;
2103 else /* XACT, MMF, etc */
2104 desc->status = -EPROTO;
2107 desc->actual_length = desc->length - SITD_LENGTH(t);
2108 urb->actual_length += desc->actual_length;
2111 /* handle completion now? */
2112 if ((urb_index + 1) != urb->number_of_packets)
2115 /* ASSERT: it's really the last sitd for this urb
2116 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2117 BUG_ON (sitd->urb == urb);
2120 /* give urb back to the driver; completion often (re)submits */
2122 ehci_urb_done(ehci, urb, 0);
2125 (void) disable_periodic(ehci);
2126 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2128 if (list_is_singular(&stream->td_list)) {
2129 ehci_to_hcd(ehci)->self.bandwidth_allocated
2130 -= stream->bandwidth;
2132 "deschedule devp %s ep%d%s-iso\n",
2133 dev->devpath, stream->bEndpointAddress & 0x0f,
2134 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2136 iso_stream_put (ehci, stream);
2140 if (ehci->clock_frame != sitd->frame) {
2141 /* OK to recycle this SITD now. */
2142 sitd->stream = NULL;
2143 list_move(&sitd->sitd_list, &stream->free_list);
2144 iso_stream_put(ehci, stream);
2146 /* HW might remember this SITD, so we can't recycle it yet.
2147 * Move it to a safe place until a new frame starts.
2149 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2150 if (stream->refcount == 2) {
2151 /* If iso_stream_put() were called here, stream
2152 * would be freed. Instead, just prevent reuse.
2154 stream->ep->hcpriv = NULL;
2162 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2165 int status = -EINVAL;
2166 unsigned long flags;
2167 struct ehci_iso_stream *stream;
2169 /* Get iso_stream head */
2170 stream = iso_stream_find (ehci, urb);
2171 if (stream == NULL) {
2172 ehci_dbg (ehci, "can't get iso stream\n");
2175 if (urb->interval != stream->interval) {
2176 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2177 stream->interval, urb->interval);
2181 #ifdef EHCI_URB_TRACE
2183 "submit %p dev%s ep%d%s-iso len %d\n",
2184 urb, urb->dev->devpath,
2185 usb_pipeendpoint (urb->pipe),
2186 usb_pipein (urb->pipe) ? "in" : "out",
2187 urb->transfer_buffer_length);
2190 /* allocate SITDs */
2191 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2193 ehci_dbg (ehci, "can't init sitds\n");
2197 /* schedule ... need to lock */
2198 spin_lock_irqsave (&ehci->lock, flags);
2199 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
2200 status = -ESHUTDOWN;
2201 goto done_not_linked;
2203 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2204 if (unlikely(status))
2205 goto done_not_linked;
2206 status = iso_stream_schedule(ehci, urb, stream);
2208 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2210 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2212 spin_unlock_irqrestore (&ehci->lock, flags);
2216 iso_stream_put (ehci, stream);
2220 /*-------------------------------------------------------------------------*/
2222 static void free_cached_lists(struct ehci_hcd *ehci)
2224 struct ehci_itd *itd, *n;
2225 struct ehci_sitd *sitd, *sn;
2227 list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2228 struct ehci_iso_stream *stream = itd->stream;
2230 list_move(&itd->itd_list, &stream->free_list);
2231 iso_stream_put(ehci, stream);
2234 list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2235 struct ehci_iso_stream *stream = sitd->stream;
2236 sitd->stream = NULL;
2237 list_move(&sitd->sitd_list, &stream->free_list);
2238 iso_stream_put(ehci, stream);
2242 /*-------------------------------------------------------------------------*/
2245 scan_periodic (struct ehci_hcd *ehci)
2247 unsigned now_uframe, frame, clock, clock_frame, mod;
2250 mod = ehci->periodic_size << 3;
2253 * When running, scan from last scan point up to "now"
2254 * else clean up by scanning everything that's left.
2255 * Touches as few pages as possible: cache-friendly.
2257 now_uframe = ehci->next_uframe;
2258 if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2259 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2260 clock_frame = (clock >> 3) & (ehci->periodic_size - 1);
2262 clock = now_uframe + mod - 1;
2265 if (ehci->clock_frame != clock_frame) {
2266 free_cached_lists(ehci);
2267 ehci->clock_frame = clock_frame;
2270 clock_frame = clock >> 3;
2273 union ehci_shadow q, *q_p;
2275 unsigned incomplete = false;
2277 frame = now_uframe >> 3;
2280 /* scan each element in frame's queue for completions */
2281 q_p = &ehci->pshadow [frame];
2282 hw_p = &ehci->periodic [frame];
2284 type = Q_NEXT_TYPE(ehci, *hw_p);
2287 while (q.ptr != NULL) {
2289 union ehci_shadow temp;
2292 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2293 switch (hc32_to_cpu(ehci, type)) {
2295 /* handle any completions */
2296 temp.qh = qh_get (q.qh);
2297 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
2299 modified = qh_completions (ehci, temp.qh);
2300 if (unlikely(list_empty(&temp.qh->qtd_list) ||
2301 temp.qh->needs_rescan))
2302 intr_deschedule (ehci, temp.qh);
2306 /* for "save place" FSTNs, look at QH entries
2307 * in the previous frame for completions.
2309 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2310 dbg ("ignoring completions from FSTNs");
2312 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2313 q = q.fstn->fstn_next;
2316 /* If this ITD is still active, leave it for
2317 * later processing ... check the next entry.
2318 * No need to check for activity unless the
2321 if (frame == clock_frame && live) {
2323 for (uf = 0; uf < 8; uf++) {
2324 if (q.itd->hw_transaction[uf] &
2330 q_p = &q.itd->itd_next;
2331 hw_p = &q.itd->hw_next;
2332 type = Q_NEXT_TYPE(ehci,
2339 /* Take finished ITDs out of the schedule
2340 * and process them: recycle, maybe report
2341 * URB completion. HC won't cache the
2342 * pointer for much longer, if at all.
2344 *q_p = q.itd->itd_next;
2345 if (!ehci->use_dummy_qh ||
2346 q.itd->hw_next != EHCI_LIST_END(ehci))
2347 *hw_p = q.itd->hw_next;
2349 *hw_p = ehci->dummy->qh_dma;
2350 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2352 modified = itd_complete (ehci, q.itd);
2356 /* If this SITD is still active, leave it for
2357 * later processing ... check the next entry.
2358 * No need to check for activity unless the
2361 if (((frame == clock_frame) ||
2362 (((frame + 1) & (ehci->periodic_size - 1))
2365 && (q.sitd->hw_results &
2366 SITD_ACTIVE(ehci))) {
2369 q_p = &q.sitd->sitd_next;
2370 hw_p = &q.sitd->hw_next;
2371 type = Q_NEXT_TYPE(ehci,
2377 /* Take finished SITDs out of the schedule
2378 * and process them: recycle, maybe report
2381 *q_p = q.sitd->sitd_next;
2382 if (!ehci->use_dummy_qh ||
2383 q.sitd->hw_next != EHCI_LIST_END(ehci))
2384 *hw_p = q.sitd->hw_next;
2386 *hw_p = ehci->dummy->qh_dma;
2387 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2389 modified = sitd_complete (ehci, q.sitd);
2393 dbg ("corrupt type %d frame %d shadow %p",
2394 type, frame, q.ptr);
2399 /* assume completion callbacks modify the queue */
2400 if (unlikely (modified)) {
2401 if (likely(ehci->periodic_sched > 0))
2403 /* short-circuit this scan */
2409 /* If we can tell we caught up to the hardware, stop now.
2410 * We can't advance our scan without collecting the ISO
2411 * transfers that are still pending in this frame.
2413 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2414 ehci->next_uframe = now_uframe;
2418 // FIXME: this assumes we won't get lapped when
2419 // latencies climb; that should be rare, but...
2420 // detect it, and just go all the way around.
2421 // FLR might help detect this case, so long as latencies
2422 // don't exceed periodic_size msec (default 1.024 sec).
2424 // FIXME: likewise assumes HC doesn't halt mid-scan
2426 if (now_uframe == clock) {
2429 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2430 || ehci->periodic_sched == 0)
2432 ehci->next_uframe = now_uframe;
2433 now = ehci_readl(ehci, &ehci->regs->frame_index) &
2435 if (now_uframe == now)
2438 /* rescan the rest of this frame, then ... */
2440 clock_frame = clock >> 3;
2441 if (ehci->clock_frame != clock_frame) {
2442 free_cached_lists(ehci);
2443 ehci->clock_frame = clock_frame;
2447 now_uframe &= mod - 1;