drivers/usb/host/ehci-omap.c

   1 /*
   2  * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
   3  *
   4  * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
   5  * Tested on OMAP3430 ES2.0 SDP
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  *      Author: Vikram Pandita <vikram.pandita@ti.com>
   9  *
  10  * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  *
  26  */
  27
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <mach/gpio.h>
  31
  32 #include "ehci-omap.h"
  33
  34
  35 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
  36 /* EHCI connected to External PHY */
  37
  38 /* External USB connectivity board: 750-2083-001
  39  * Connected to OMAP3430 SDP
  40  * The board has Port1 and Port2 connected to ISP1504 in 12-pin ULPI mode
  41  */
  42
  43 /* ISSUE1:
  44  *      ISP1504 for input clocking mode needs special reset handling
  45  *      Hold the PHY in reset by asserting RESET_N signal
  46  *      Then start the 60Mhz clock input to PHY
  47  *      Release the reset after a delay -
  48  *              to get the PHY state machine in working state
  49  */
  50 #define EXTERNAL_PHY_RESET
  51 #define EXT_PHY_RESET_GPIO_PORT1        (57)
  52 #define EXT_PHY_RESET_GPIO_PORT2        (61)
  53 #define EXT_PHY_RESET_DELAY             (10)
  54
  55 /* ISSUE2:
  56  * USBHOST supports External charge pump PHYs only
  57  * Use the VBUS from Port1 to power VBUS of Port2 externally
  58  * So use Port2 as the working ULPI port
  59  */
  60 #define VBUS_INTERNAL_CHARGEPUMP_HACK
  61
  62 #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
  63
  64 /*-------------------------------------------------------------------------*/
  65
  66 /* Define USBHOST clocks for clock management */
  67 struct ehci_omap_clock_defs {
  68         struct clk      *usbhost_ick_clk;
  69         struct clk      *usbhost2_120m_fck_clk;
  70         struct clk      *usbhost1_48m_fck_clk;
  71         struct clk      *usbtll_fck_clk;
  72         struct clk      *usbtll_ick_clk;
  73 };
  74
  75 /* Clock names as per clock framework: May change so keep as #defs */
  76 #define USBHOST_ICKL            "usbhost_ick"
  77 #define USBHOST_120M_FCLK       "usbhost_120m_fck"
  78 #define USBHOST_48M_FCLK        "usbhost_48m_fck"
  79 #define USBHOST_TLL_ICKL        "usbtll_ick"
  80 #define USBHOST_TLL_FCLK        "usbtll_fck"
  81 /*-------------------------------------------------------------------------*/
  82
  83
  84 #ifndef CONFIG_OMAP_EHCI_PHY_MODE
  85
  86 static void omap_usb_utmi_init(struct usb_hcd *hcd, u8 tll_channel_mask)
  87 {
  88         int i;
  89
  90         /* Use UTMI Ports of TLL */
  91         omap_writel((1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)|
  92                         (1<<OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN_SHIFT)|
  93                         (1<<OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN_SHIFT)|
  94                         (1<<OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN_SHIFT)|
  95                         (0<<OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN_SHIFT),
  96                                                 OMAP_UHH_HOSTCONFIG);
  97         /* Enusre bit is set */
  98         while (!(omap_readl(OMAP_UHH_HOSTCONFIG) &
  99                 (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)));
 100
 101         dev_dbg(hcd->self.controller, "\nEntered UTMI MODE: success\n");
 102
 103         /* Program the 3 TLL channels upfront */
 104
 105         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 106
 107                 /* Disable AutoIdle */
 108                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 109                             ~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
 110                             OMAP_TLL_CHANNEL_CONF(i));
 111                 /* Disable BitStuffing */
 112                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 113                             ~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
 114                             OMAP_TLL_CHANNEL_CONF(i));
 115                 /* SDR Mode */
 116                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 117                             ~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
 118                             OMAP_TLL_CHANNEL_CONF(i));
 119
 120         }
 121
 122         /* Program Common TLL register */
 123         omap_writel((1 << OMAP_TLL_SHARED_CONF_FCLK_IS_ON_SHIFT) |
 124                         (1 << OMAP_TLL_SHARED_CONF_USB_DIVRATION_SHIFT) |
 125                         (0 << OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN_SHIFT) |
 126                         (0 << OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN_SHFT),
 127                                 OMAP_TLL_SHARED_CONF);
 128
 129         /* Enable channels now */
 130         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 131
 132                 /* Enable only the channel that is needed */
 133                 if (!(tll_channel_mask & 1<<i))
 134                         continue;
 135
 136                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) |
 137                             (1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
 138                             OMAP_TLL_CHANNEL_CONF(i));
 139
 140                 omap_writeb(0xBE, OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
 141                 dev_dbg(hcd->self.controller, "\nULPI_SCRATCH_REG[ch=%d]"
 142                         "= 0x%02x\n",
 143                         i+1, omap_readb(OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
 144         }
 145 }
 146
 147 #else
 148 # define omap_usb_utmi_init(x, y)       0
 149 #endif
 150
 151
 152 /* omap_start_ehc
 153  *      - Start the TI USBHOST controller
 154  */
 155 static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 156 {
 157         struct ehci_omap_clock_defs *ehci_clocks;
 158
 159         dev_dbg(hcd->self.controller, ": starting TI EHCI USB Controller\n");
 160
 161         ehci_clocks = (struct ehci_omap_clock_defs *)(
 162                                 ((char *)hcd_to_ehci(hcd)) +
 163                                         sizeof(struct ehci_hcd));
 164
 165         /* Start DPLL5 Programming:
 166          * Clock Framework is not doing this now:
 167          * This will be done in clock framework later
 168          */
 169         /* Enable DPLL 5 : Based on Input of 13Mhz*/
 170         cm_write_mod_reg((12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT)|
 171                         (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT),
 172                         PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 173
 174         cm_write_mod_reg(1 << OMAP3430ES2_DIV_120M_SHIFT,
 175                         PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 176
 177         cm_write_mod_reg((7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT) |
 178                         (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT),
 179                         PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 180
 181         while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST2) &
 182                                 OMAP3430ES2_ST_PERIPH2_CLK_MASK))
 183                 dev_dbg(hcd->self.controller,
 184                         "idlest2 = 0x%x\n",
 185                         cm_read_mod_reg(PLL_MOD, CM_IDLEST2));
 186         /* End DPLL5 programming */
 187
 188
 189         /* PRCM settings for USBHOST:
 190          * Interface clk un-related to domain transition
 191          */
 192         cm_write_mod_reg(0 << OMAP3430ES2_AUTO_USBHOST_SHIFT,
 193                                 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 194
 195         /* Disable sleep dependency with MPU and IVA */
 196         cm_write_mod_reg((0 << OMAP3430ES2_EN_MPU_SHIFT) |
 197                                 (0 << OMAP3430ES2_EN_IVA2_SHIFT),
 198                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 199
 200         /* Disable Automatic transition of clock */
 201         cm_write_mod_reg(0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT,
 202                                 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
 203
 204         /* Enable Clocks for USBHOST */
 205         ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev,
 206                                                 USBHOST_ICKL);
 207         if (IS_ERR(ehci_clocks->usbhost_ick_clk))
 208                 return PTR_ERR(ehci_clocks->usbhost_ick_clk);
 209         clk_enable(ehci_clocks->usbhost_ick_clk);
 210
 211
 212         ehci_clocks->usbhost2_120m_fck_clk = clk_get(&dev->dev,
 213                                                         USBHOST_120M_FCLK);
 214         if (IS_ERR(ehci_clocks->usbhost2_120m_fck_clk))
 215                 return PTR_ERR(ehci_clocks->usbhost2_120m_fck_clk);
 216         clk_enable(ehci_clocks->usbhost2_120m_fck_clk);
 217
 218         ehci_clocks->usbhost1_48m_fck_clk = clk_get(&dev->dev,
 219                                                 USBHOST_48M_FCLK);
 220         if (IS_ERR(ehci_clocks->usbhost1_48m_fck_clk))
 221                 return PTR_ERR(ehci_clocks->usbhost1_48m_fck_clk);
 222         clk_enable(ehci_clocks->usbhost1_48m_fck_clk);
 223
 224
 225 #ifdef EXTERNAL_PHY_RESET
 226         /* Refer: ISSUE1 */
 227         omap_request_gpio(EXT_PHY_RESET_GPIO_PORT1);
 228         omap_set_gpio_direction(EXT_PHY_RESET_GPIO_PORT1, 0);
 229         omap_request_gpio(EXT_PHY_RESET_GPIO_PORT2);
 230         omap_set_gpio_direction(EXT_PHY_RESET_GPIO_PORT2, 0);
 231         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT1, 0);
 232         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT2, 0);
 233         /* Hold the PHY in RESET for enough time till DIR is high */
 234         udelay(EXT_PHY_RESET_DELAY);
 235 #endif
 236
 237         /* Configure TLL for 60Mhz clk for ULPI */
 238         ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
 239         if (IS_ERR(ehci_clocks->usbtll_fck_clk))
 240                 return PTR_ERR(ehci_clocks->usbtll_fck_clk);
 241         clk_enable(ehci_clocks->usbtll_fck_clk);
 242
 243         ehci_clocks->usbtll_ick_clk = clk_get(&dev->dev, USBHOST_TLL_ICKL);
 244         if (IS_ERR(ehci_clocks->usbtll_ick_clk))
 245                 return PTR_ERR(ehci_clocks->usbtll_ick_clk);
 246         clk_enable(ehci_clocks->usbtll_ick_clk);
 247
 248         /* Disable Auto Idle of USBTLL */
 249         cm_write_mod_reg((0 << OMAP3430ES2_AUTO_USBTLL_SHIFT),
 250                                 CORE_MOD, CM_AUTOIDLE3);
 251
 252         /* Wait for TLL to be Active */
 253         while ((cm_read_mod_reg(CORE_MOD, OMAP2430_CM_IDLEST3) &
 254                 (1 << OMAP3430ES2_ST_USBTLL_SHIFT)));
 255
 256         /* perform TLL soft reset, and wait until reset is complete */
 257         omap_writel(1 << OMAP_USBTLL_SYSCONFIG_SOFTRESET_SHIFT,
 258                         OMAP_USBTLL_SYSCONFIG);
 259         /* Wait for TLL reset to complete */
 260         while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) &
 261                 (1 << OMAP_USBTLL_SYSSTATUS_RESETDONE_SHIFT)));
 262
 263         dev_dbg(hcd->self.controller, "\n TLL RESET DONE\n");
 264
 265         /* (1<<3) = no idle mode only for initial debugging */
 266         omap_writel((1 << OMAP_USBTLL_SYSCONFIG_ENAWAKEUP_SHIFT) |
 267                         (1 << OMAP_USBTLL_SYSCONFIG_SIDLEMODE_SHIFT) |
 268                         (1 << OMAP_USBTLL_SYSCONFIG_CACTIVITY_SHIFT),
 269                         OMAP_USBTLL_SYSCONFIG);
 270
 271
 272         /* Put UHH in NoIdle/NoStandby mode */
 273         omap_writel((0 << OMAP_UHH_SYSCONFIG_AUTOIDLE_SHIFT) |
 274                         (1 << OMAP_UHH_SYSCONFIG_ENAWAKEUP_SHIFT) |
 275                         (1 << OMAP_UHH_SYSCONFIG_SIDLEMODE_SHIFT) |
 276                         (1 << OMAP_UHH_SYSCONFIG_CACTIVITY_SHIFT) |
 277                         (1 << OMAP_UHH_SYSCONFIG_MIDLEMODE_SHIFT),
 278                         OMAP_UHH_SYSCONFIG);
 279
 280 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
 281         /* Bypass the TLL module for PHY mode operation */
 282         omap_writel((0 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)|
 283                         (1<<OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN_SHIFT)|
 284                         (1<<OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN_SHIFT)|
 285                         (1<<OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN_SHIFT)|
 286                         (0<<OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN_SHIFT),
 287                                                 OMAP_UHH_HOSTCONFIG);
 288         /* Ensure that BYPASS is set */
 289         while (omap_readl(OMAP_UHH_HOSTCONFIG) &
 290                 (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT));
 291
 292         dev_dbg(hcd->self.controller, "Entered ULPI PHY MODE: success");
 293
 294 #else
 295         /* Enable UTMI mode for all 3 TLL channels */
 296         omap_usb_utmi_init(hcd,
 297                 OMAP_TLL_CHANNEL_1_EN_MASK |
 298                 OMAP_TLL_CHANNEL_2_EN_MASK |
 299                 OMAP_TLL_CHANNEL_3_EN_MASK
 300                 );
 301 #endif
 302
 303 #ifdef EXTERNAL_PHY_RESET
 304         /* Refer ISSUE1:
 305          * Hold the PHY in RESET for enough time till PHY is settled and ready
 306          */
 307         udelay(EXT_PHY_RESET_DELAY);
 308         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT1, 1);
 309         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT2, 1);
 310 #endif
 311
 312 #ifdef VBUS_INTERNAL_CHARGEPUMP_HACK
 313         /* Refer ISSUE2: LINK assumes external charge pump */
 314
 315         /* use Port1 VBUS to charge externally Port2:
 316          *      So for PHY mode operation use Port2 only
 317          */
 318         omap_writel((0xA << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* OTG ctrl reg*/
 319                         (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
 320                         (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
 321                         (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
 322                         (0x26),
 323                         EHCI_INSNREG05_ULPI);
 324
 325         while (!(omap_readl(EHCI_INSNREG05_ULPI) &
 326                 (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
 327
 328 #endif
 329
 330         return 0;
 331 }
 332
 333 /*-------------------------------------------------------------------------*/
 334
 335 static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 336 {
 337         struct ehci_omap_clock_defs *ehci_clocks;
 338
 339         ehci_clocks = (struct ehci_omap_clock_defs *)
 340                         (((char *)hcd_to_ehci(hcd)) + sizeof(struct ehci_hcd));
 341
 342         dev_dbg(hcd->self.controller, ": stopping TI EHCI USB Controller\n");
 343
 344         /* Reset OMAP modules for insmod/rmmod to work */
 345         omap_writel((1<<1), OMAP_UHH_SYSCONFIG);
 346         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<0)));
 347         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<1)));
 348         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<2)));
 349         dev_dbg(hcd->self.controller,
 350                 "UHH RESET DONE OMAP_UHH_SYSSTATUS %x !!\n",
 351                         omap_readl(OMAP_UHH_SYSSTATUS));
 352
 353         omap_writel((1<<1), OMAP_USBTLL_SYSCONFIG);
 354         while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) & (1<<0)));
 355         dev_dbg(hcd->self.controller, ":TLL RESEET DONE");
 356
 357         if (ehci_clocks->usbtll_fck_clk != NULL) {
 358                 clk_disable(ehci_clocks->usbtll_fck_clk);
 359                 clk_put(ehci_clocks->usbtll_fck_clk);
 360                 ehci_clocks->usbtll_fck_clk = NULL;
 361         }
 362
 363         if (ehci_clocks->usbhost_ick_clk != NULL) {
 364                 clk_disable(ehci_clocks->usbhost_ick_clk);
 365                 clk_put(ehci_clocks->usbhost_ick_clk);
 366                 ehci_clocks->usbhost_ick_clk = NULL;
 367         }
 368
 369         if (ehci_clocks->usbhost1_48m_fck_clk != NULL) {
 370                 clk_disable(ehci_clocks->usbhost1_48m_fck_clk);
 371                 clk_put(ehci_clocks->usbhost1_48m_fck_clk);
 372                 ehci_clocks->usbhost1_48m_fck_clk = NULL;
 373         }
 374
 375         if (ehci_clocks->usbhost2_120m_fck_clk != NULL) {
 376                 clk_disable(ehci_clocks->usbhost2_120m_fck_clk);
 377                 clk_put(ehci_clocks->usbhost2_120m_fck_clk);
 378                 ehci_clocks->usbhost2_120m_fck_clk = NULL;
 379         }
 380
 381         if (ehci_clocks->usbtll_ick_clk != NULL) {
 382                 clk_disable(ehci_clocks->usbtll_ick_clk);
 383                 clk_put(ehci_clocks->usbtll_ick_clk);
 384                 ehci_clocks->usbtll_ick_clk = NULL;
 385         }
 386
 387
 388 #ifdef EXTERNAL_PHY_RESET
 389         omap_free_gpio(EXT_PHY_RESET_GPIO_PORT1);
 390         omap_free_gpio(EXT_PHY_RESET_GPIO_PORT2);
 391 #endif
 392
 393         dev_dbg(hcd->self.controller,
 394                 ": Clock to USB host has been disabled\n");
 395 }
 396
 397 static const struct hc_driver ehci_omap_hc_driver;
 398
 399 /*-------------------------------------------------------------------------*/
 400 /* configure so an HC device and id are always provided */
 401 /* always called with process context; sleeping is OK */
 402
 403 /**
 404  * ehci_hcd_omap_drv_probe - initialize TI-based HCDs
 405  * Context: !in_interrupt()
 406  *
 407  * Allocates basic resources for this USB host controller, and
 408  * then invokes the start() method for the HCD associated with it
 409  * through the hotplug entry's driver_data.
 410  *
 411  */
 412 static int ehci_hcd_omap_drv_probe(struct platform_device *dev)
 413 {
 414         int retval = 0;
 415         struct usb_hcd *hcd;
 416         struct ehci_hcd *ehci;
 417
 418         dev_dbg(&dev->dev, "ehci_hcd_omap_drv_probe()");
 419
 420         if (usb_disabled())
 421                 return -ENODEV;
 422
 423         if (dev->resource[1].flags != IORESOURCE_IRQ) {
 424                 dev_dbg(&dev->dev, "resource[1] is not IORESOURCE_IRQ");
 425                 retval = -ENOMEM;
 426         }
 427
 428         hcd = usb_create_hcd(&ehci_omap_hc_driver, &dev->dev, dev->dev.bus_id);
 429         if (!hcd)
 430                 return -ENOMEM;
 431
 432         retval = omap_start_ehc(dev, hcd);
 433         if (retval)
 434                 return retval;
 435
 436         hcd->rsrc_start = 0;
 437         hcd->rsrc_len = 0;
 438         hcd->rsrc_start = dev->resource[0].start;
 439         hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
 440
 441         hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
 442         if (!hcd->regs) {
 443                 dev_err(&dev->dev, "ioremap failed\n");
 444                 return -ENOMEM;
 445         }
 446
 447         ehci = hcd_to_ehci(hcd);
 448         ehci->caps = hcd->regs;
 449
 450         ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
 451         /* cache this readonly data; minimize chip reads */
 452         ehci->hcs_params = readl(&ehci->caps->hcs_params);
 453
 454         /* SET 1 micro-frame Interrupt interval */
 455         writel(readl(&ehci->regs->command) | (1<<16), &ehci->regs->command);
 456
 457         retval = usb_add_hcd(hcd, dev->resource[1].start,
 458                                 IRQF_DISABLED | IRQF_SHARED);
 459         if (retval == 0)
 460                 return retval;
 461
 462         dev_dbg(hcd->self.controller, "ERR: add_hcd");
 463         omap_stop_ehc(dev, hcd);
 464         iounmap(hcd->regs);
 465         usb_put_hcd(hcd);
 466
 467         return retval;
 468 }
 469
 470 /*-------------------------------------------------------------------------*/
 471
 472 /* may be called without controller electrically present */
 473 /* may be called with controller, bus, and devices active */
 474
 475 /**
 476  * ehci_hcd_omap_drv_remove - shutdown processing for EHCI HCDs
 477  * @dev: USB Host Controller being removed
 478  * Context: !in_interrupt()
 479  *
 480  * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
 481  * the HCD's stop() method.  It is always called from a thread
 482  * context, normally "rmmod", "apmd", or something similar.
 483  *
 484  */
 485 static int ehci_hcd_omap_drv_remove(struct platform_device *dev)
 486 {
 487         struct usb_hcd *hcd = platform_get_drvdata(dev);
 488
 489         dev_dbg(&dev->dev, "ehci_hcd_omap_drv_remove()");
 490
 491         iounmap(hcd->regs);
 492         usb_remove_hcd(hcd);
 493         usb_put_hcd(hcd);
 494         omap_stop_ehc(dev, hcd);
 495
 496         return 0;
 497 }
 498
 499 /*-------------------------------------------------------------------------*/
 500 #ifdef CONFIG_PM
 501 static int omap_ehci_bus_suspend(struct usb_hcd *hcd)
 502 {
 503         return ehci_bus_suspend(hcd);
 504 }
 505
 506 static int omap_ehci_bus_resume(struct usb_hcd *hcd)
 507 {
 508         return ehci_bus_resume(hcd);
 509 }
 510 #endif
 511 /*-------------------------------------------------------------------------*/
 512
 513 static const struct hc_driver ehci_omap_hc_driver = {
 514         .description = hcd_name,
 515         .product_desc = "OMAP-EHCI Host Controller",
 516         .hcd_priv_size = sizeof(struct ehci_hcd)
 517                                 + sizeof(struct ehci_omap_clock_defs),
 518
 519         /*
 520          * generic hardware linkage
 521          */
 522         .irq = ehci_irq,
 523         .flags = HCD_MEMORY | HCD_USB2,
 524
 525         /*
 526          * basic lifecycle operations
 527          */
 528         .reset = ehci_init,
 529         .start = ehci_run,
 530         .stop = ehci_stop,
 531         .shutdown = ehci_shutdown,
 532
 533         /*
 534          * managing i/o requests and associated device resources
 535          */
 536         .urb_enqueue = ehci_urb_enqueue,
 537         .urb_dequeue = ehci_urb_dequeue,
 538         .endpoint_disable = ehci_endpoint_disable,
 539
 540         /*
 541          * scheduling support
 542          */
 543         .get_frame_number = ehci_get_frame,
 544
 545         /*
 546          * root hub support
 547          */
 548         .hub_status_data = ehci_hub_status_data,
 549         .hub_control = ehci_hub_control,
 550 #ifdef  CONFIG_PM
 551         .bus_suspend = omap_ehci_bus_suspend,
 552         .bus_resume = omap_ehci_bus_resume,
 553 #endif
 554 };
 555
 556 /*-------------------------------------------------------------------------*/
 557 MODULE_ALIAS("omap-ehci");
 558 static struct platform_driver ehci_hcd_omap_driver = {
 559         .probe = ehci_hcd_omap_drv_probe,
 560         .remove = ehci_hcd_omap_drv_remove,
 561         .shutdown = usb_hcd_platform_shutdown,
 562         /*.suspend      = ehci_hcd_omap_drv_suspend, */
 563         /*.resume       = ehci_hcd_omap_drv_resume, */
 564         .driver = {
 565                 .name = "ehci-omap",
 566                 .bus = &platform_bus_type
 567         }
 568 };