2 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * Copyright (c) 2000-2004 by David Brownell
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/ktime.h>
35 #include <linux/list.h>
36 #include <linux/interrupt.h>
37 #include <linux/usb.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/moduleparam.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/slab.h>
43 #include <linux/uaccess.h>
45 #include <asm/byteorder.h>
48 #include <asm/system.h>
49 #include <asm/unaligned.h>
51 /*-------------------------------------------------------------------------*/
54 * EHCI hc_driver implementation ... experimental, incomplete.
55 * Based on the final 1.0 register interface specification.
57 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
58 * First was PCMCIA, like ISA; then CardBus, which is PCI.
59 * Next comes "CardBay", using USB 2.0 signals.
61 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
62 * Special thanks to Intel and VIA for providing host controllers to
63 * test this driver on, and Cypress (including In-System Design) for
64 * providing early devices for those host controllers to talk to!
67 #define DRIVER_AUTHOR "David Brownell"
68 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
70 static const char hcd_name [] = "ehci_hcd";
80 /* magic numbers that can affect system performance */
81 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
82 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
83 #define EHCI_TUNE_RL_TT 0
84 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
85 #define EHCI_TUNE_MULT_TT 1
87 * Some drivers think it's safe to schedule isochronous transfers more than
88 * 256 ms into the future (partly as a result of an old bug in the scheduling
89 * code). In an attempt to avoid trouble, we will use a minimum scheduling
90 * length of 512 frames instead of 256.
92 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
94 #define EHCI_IAA_MSECS 10 /* arbitrary */
95 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
96 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
97 #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1)
98 /* 5-ms async qh unlink delay */
100 /* Initial IRQ latency: faster than hw default */
101 static int log2_irq_thresh = 0; // 0 to 6
102 module_param (log2_irq_thresh, int, S_IRUGO);
103 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
105 /* initial park setting: slower than hw default */
106 static unsigned park = 0;
107 module_param (park, uint, S_IRUGO);
108 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
110 /* for flakey hardware, ignore overcurrent indicators */
111 static int ignore_oc = 0;
112 module_param (ignore_oc, bool, S_IRUGO);
113 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
115 /* for link power management(LPM) feature */
116 static unsigned int hird;
117 module_param(hird, int, S_IRUGO);
118 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
120 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
122 /*-------------------------------------------------------------------------*/
125 #include "ehci-dbg.c"
126 #include "pci-quirks.h"
128 /*-------------------------------------------------------------------------*/
131 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
133 /* Don't override timeouts which shrink or (later) disable
134 * the async ring; just the I/O watchdog. Note that if a
135 * SHRINK were pending, OFF would never be requested.
137 if (timer_pending(&ehci->watchdog)
138 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
142 if (!test_and_set_bit(action, &ehci->actions)) {
146 case TIMER_IO_WATCHDOG:
147 if (!ehci->need_io_watchdog)
151 case TIMER_ASYNC_OFF:
152 t = EHCI_ASYNC_JIFFIES;
154 /* case TIMER_ASYNC_SHRINK: */
156 t = EHCI_SHRINK_JIFFIES;
159 mod_timer(&ehci->watchdog, t + jiffies);
163 /*-------------------------------------------------------------------------*/
166 * handshake - spin reading hc until handshake completes or fails
167 * @ptr: address of hc register to be read
168 * @mask: bits to look at in result of read
169 * @done: value of those bits when handshake succeeds
170 * @usec: timeout in microseconds
172 * Returns negative errno, or zero on success
174 * Success happens when the "mask" bits have the specified value (hardware
175 * handshake done). There are two failure modes: "usec" have passed (major
176 * hardware flakeout), or the register reads as all-ones (hardware removed).
178 * That last failure should_only happen in cases like physical cardbus eject
179 * before driver shutdown. But it also seems to be caused by bugs in cardbus
180 * bridge shutdown: shutting down the bridge before the devices using it.
182 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
183 u32 mask, u32 done, int usec)
188 result = ehci_readl(ehci, ptr);
189 if (result == ~(u32)0) /* card removed */
200 /* check TDI/ARC silicon is in host mode */
201 static int tdi_in_host_mode (struct ehci_hcd *ehci)
203 u32 __iomem *reg_ptr;
206 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
207 tmp = ehci_readl(ehci, reg_ptr);
208 return (tmp & 3) == USBMODE_CM_HC;
211 /* force HC to halt state from unknown (EHCI spec section 2.3) */
212 static int ehci_halt (struct ehci_hcd *ehci)
214 u32 temp = ehci_readl(ehci, &ehci->regs->status);
216 /* disable any irqs left enabled by previous code */
217 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
219 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
223 if ((temp & STS_HALT) != 0)
226 temp = ehci_readl(ehci, &ehci->regs->command);
228 ehci_writel(ehci, temp, &ehci->regs->command);
229 return handshake (ehci, &ehci->regs->status,
230 STS_HALT, STS_HALT, 16 * 125);
233 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
234 u32 mask, u32 done, int usec)
238 error = handshake(ehci, ptr, mask, done, usec);
241 ehci->rh_state = EHCI_RH_HALTED;
242 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
243 ptr, mask, done, error);
249 /* put TDI/ARC silicon into EHCI mode */
250 static void tdi_reset (struct ehci_hcd *ehci)
252 u32 __iomem *reg_ptr;
255 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
256 tmp = ehci_readl(ehci, reg_ptr);
257 tmp |= USBMODE_CM_HC;
258 /* The default byte access to MMR space is LE after
259 * controller reset. Set the required endian mode
260 * for transfer buffers to match the host microprocessor
262 if (ehci_big_endian_mmio(ehci))
264 ehci_writel(ehci, tmp, reg_ptr);
267 /* reset a non-running (STS_HALT == 1) controller */
268 static int ehci_reset (struct ehci_hcd *ehci)
271 u32 command = ehci_readl(ehci, &ehci->regs->command);
273 /* If the EHCI debug controller is active, special care must be
274 * taken before and after a host controller reset */
275 if (ehci->debug && !dbgp_reset_prep())
278 command |= CMD_RESET;
279 dbg_cmd (ehci, "reset", command);
280 ehci_writel(ehci, command, &ehci->regs->command);
281 ehci->rh_state = EHCI_RH_HALTED;
282 ehci->next_statechange = jiffies;
283 retval = handshake (ehci, &ehci->regs->command,
284 CMD_RESET, 0, 250 * 1000);
286 if (ehci->has_hostpc) {
287 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
288 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
289 ehci_writel(ehci, TXFIFO_DEFAULT,
290 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
295 if (ehci_is_TDI(ehci))
299 dbgp_external_startup();
304 /* idle the controller (from running) */
305 static void ehci_quiesce (struct ehci_hcd *ehci)
310 if (ehci->rh_state != EHCI_RH_RUNNING)
314 /* wait for any schedule enables/disables to take effect */
315 temp = ehci_readl(ehci, &ehci->regs->command) << 10;
316 temp &= STS_ASS | STS_PSS;
317 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
318 STS_ASS | STS_PSS, temp, 16 * 125))
321 /* then disable anything that's still active */
322 temp = ehci_readl(ehci, &ehci->regs->command);
323 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
324 ehci_writel(ehci, temp, &ehci->regs->command);
326 /* hardware can take 16 microframes to turn off ... */
327 handshake_on_error_set_halt(ehci, &ehci->regs->status,
328 STS_ASS | STS_PSS, 0, 16 * 125);
331 /*-------------------------------------------------------------------------*/
333 static void end_unlink_async(struct ehci_hcd *ehci);
334 static void ehci_work(struct ehci_hcd *ehci);
336 #include "ehci-hub.c"
337 #include "ehci-lpm.c"
338 #include "ehci-mem.c"
340 #include "ehci-sched.c"
341 #include "ehci-sysfs.c"
343 /*-------------------------------------------------------------------------*/
345 static void ehci_iaa_watchdog(unsigned long param)
347 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
350 spin_lock_irqsave (&ehci->lock, flags);
352 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
353 * So we need this watchdog, but must protect it against both
354 * (a) SMP races against real IAA firing and retriggering, and
355 * (b) clean HC shutdown, when IAA watchdog was pending.
358 && !timer_pending(&ehci->iaa_watchdog)
359 && ehci->rh_state == EHCI_RH_RUNNING) {
362 /* If we get here, IAA is *REALLY* late. It's barely
363 * conceivable that the system is so busy that CMD_IAAD
364 * is still legitimately set, so let's be sure it's
365 * clear before we read STS_IAA. (The HC should clear
366 * CMD_IAAD when it sets STS_IAA.)
368 cmd = ehci_readl(ehci, &ehci->regs->command);
370 ehci_writel(ehci, cmd & ~CMD_IAAD,
371 &ehci->regs->command);
373 /* If IAA is set here it either legitimately triggered
374 * before we cleared IAAD above (but _way_ late, so we'll
375 * still count it as lost) ... or a silicon erratum:
376 * - VIA seems to set IAA without triggering the IRQ;
377 * - IAAD potentially cleared without setting IAA.
379 status = ehci_readl(ehci, &ehci->regs->status);
380 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
381 COUNT (ehci->stats.lost_iaa);
382 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
385 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
387 end_unlink_async(ehci);
390 spin_unlock_irqrestore(&ehci->lock, flags);
393 static void ehci_watchdog(unsigned long param)
395 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
398 spin_lock_irqsave(&ehci->lock, flags);
400 /* stop async processing after it's idled a bit */
401 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
402 start_unlink_async (ehci, ehci->async);
404 /* ehci could run by timer, without IRQs ... */
407 spin_unlock_irqrestore (&ehci->lock, flags);
410 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
411 * The firmware seems to think that powering off is a wakeup event!
412 * This routine turns off remote wakeup and everything else, on all ports.
414 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
416 int port = HCS_N_PORTS(ehci->hcs_params);
419 ehci_writel(ehci, PORT_RWC_BITS,
420 &ehci->regs->port_status[port]);
424 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
425 * Should be called with ehci->lock held.
427 static void ehci_silence_controller(struct ehci_hcd *ehci)
430 ehci_turn_off_all_ports(ehci);
432 /* make BIOS/etc use companion controller during reboot */
433 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
435 /* unblock posted writes */
436 ehci_readl(ehci, &ehci->regs->configured_flag);
439 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
440 * This forcibly disables dma and IRQs, helping kexec and other cases
441 * where the next system software may expect clean state.
443 static void ehci_shutdown(struct usb_hcd *hcd)
445 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
447 del_timer_sync(&ehci->watchdog);
448 del_timer_sync(&ehci->iaa_watchdog);
450 spin_lock_irq(&ehci->lock);
451 ehci_silence_controller(ehci);
452 spin_unlock_irq(&ehci->lock);
455 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
459 if (!HCS_PPC (ehci->hcs_params))
462 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
463 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
464 (void) ehci_hub_control(ehci_to_hcd(ehci),
465 is_on ? SetPortFeature : ClearPortFeature,
468 /* Flush those writes */
469 ehci_readl(ehci, &ehci->regs->command);
473 /*-------------------------------------------------------------------------*/
476 * ehci_work is called from some interrupts, timers, and so on.
477 * it calls driver completion functions, after dropping ehci->lock.
479 static void ehci_work (struct ehci_hcd *ehci)
481 timer_action_done (ehci, TIMER_IO_WATCHDOG);
483 /* another CPU may drop ehci->lock during a schedule scan while
484 * it reports urb completions. this flag guards against bogus
485 * attempts at re-entrant schedule scanning.
491 if (ehci->next_uframe != -1)
492 scan_periodic (ehci);
495 /* the IO watchdog guards against hardware or driver bugs that
496 * misplace IRQs, and should let us run completely without IRQs.
497 * such lossage has been observed on both VT6202 and VT8235.
499 if (ehci->rh_state == EHCI_RH_RUNNING &&
500 (ehci->async->qh_next.ptr != NULL ||
501 ehci->periodic_sched != 0))
502 timer_action (ehci, TIMER_IO_WATCHDOG);
506 * Called when the ehci_hcd module is removed.
508 static void ehci_stop (struct usb_hcd *hcd)
510 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
512 ehci_dbg (ehci, "stop\n");
514 /* no more interrupts ... */
515 del_timer_sync (&ehci->watchdog);
516 del_timer_sync(&ehci->iaa_watchdog);
518 spin_lock_irq(&ehci->lock);
519 if (ehci->rh_state == EHCI_RH_RUNNING)
522 ehci_silence_controller(ehci);
524 spin_unlock_irq(&ehci->lock);
526 remove_sysfs_files(ehci);
527 remove_debug_files (ehci);
529 /* root hub is shut down separately (first, when possible) */
530 spin_lock_irq (&ehci->lock);
533 spin_unlock_irq (&ehci->lock);
534 ehci_mem_cleanup (ehci);
536 if (ehci->amd_pll_fix == 1)
540 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
541 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
542 ehci->stats.lost_iaa);
543 ehci_dbg (ehci, "complete %ld unlink %ld\n",
544 ehci->stats.complete, ehci->stats.unlink);
547 dbg_status (ehci, "ehci_stop completed",
548 ehci_readl(ehci, &ehci->regs->status));
551 /* one-time init, only for memory state */
552 static int ehci_init(struct usb_hcd *hcd)
554 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
558 struct ehci_qh_hw *hw;
560 spin_lock_init(&ehci->lock);
563 * keep io watchdog by default, those good HCDs could turn off it later
565 ehci->need_io_watchdog = 1;
566 init_timer(&ehci->watchdog);
567 ehci->watchdog.function = ehci_watchdog;
568 ehci->watchdog.data = (unsigned long) ehci;
570 init_timer(&ehci->iaa_watchdog);
571 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
572 ehci->iaa_watchdog.data = (unsigned long) ehci;
574 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
577 * by default set standard 80% (== 100 usec/uframe) max periodic
578 * bandwidth as required by USB 2.0
580 ehci->uframe_periodic_max = 100;
583 * hw default: 1K periodic list heads, one per frame.
584 * periodic_size can shrink by USBCMD update if hcc_params allows.
586 ehci->periodic_size = DEFAULT_I_TDPS;
587 INIT_LIST_HEAD(&ehci->cached_itd_list);
588 INIT_LIST_HEAD(&ehci->cached_sitd_list);
590 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
591 /* periodic schedule size can be smaller than default */
592 switch (EHCI_TUNE_FLS) {
593 case 0: ehci->periodic_size = 1024; break;
594 case 1: ehci->periodic_size = 512; break;
595 case 2: ehci->periodic_size = 256; break;
599 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
602 /* controllers may cache some of the periodic schedule ... */
603 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
604 ehci->i_thresh = 2 + 8;
605 else // N microframes cached
606 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
608 ehci->reclaim = NULL;
609 ehci->next_uframe = -1;
610 ehci->clock_frame = -1;
613 * dedicate a qh for the async ring head, since we couldn't unlink
614 * a 'real' qh without stopping the async schedule [4.8]. use it
615 * as the 'reclamation list head' too.
616 * its dummy is used in hw_alt_next of many tds, to prevent the qh
617 * from automatically advancing to the next td after short reads.
619 ehci->async->qh_next.qh = NULL;
620 hw = ehci->async->hw;
621 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
622 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
623 #if defined(CONFIG_PPC_PS3)
624 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */
626 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
627 hw->hw_qtd_next = EHCI_LIST_END(ehci);
628 ehci->async->qh_state = QH_STATE_LINKED;
629 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
631 /* clear interrupt enables, set irq latency */
632 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
634 temp = 1 << (16 + log2_irq_thresh);
635 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
637 ehci_dbg(ehci, "enable per-port change event\n");
640 if (HCC_CANPARK(hcc_params)) {
641 /* HW default park == 3, on hardware that supports it (like
642 * NVidia and ALI silicon), maximizes throughput on the async
643 * schedule by avoiding QH fetches between transfers.
645 * With fast usb storage devices and NForce2, "park" seems to
646 * make problems: throughput reduction (!), data errors...
649 park = min(park, (unsigned) 3);
653 ehci_dbg(ehci, "park %d\n", park);
655 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
656 /* periodic schedule size can be smaller than default */
658 temp |= (EHCI_TUNE_FLS << 2);
660 if (HCC_LPM(hcc_params)) {
661 /* support link power management EHCI 1.1 addendum */
662 ehci_dbg(ehci, "support lpm\n");
665 ehci_dbg(ehci, "hird %d invalid, use default 0",
671 ehci->command = temp;
673 /* Accept arbitrarily long scatter-gather lists */
674 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
675 hcd->self.sg_tablesize = ~0;
679 /* start HC running; it's halted, ehci_init() has been run (once) */
680 static int ehci_run (struct usb_hcd *hcd)
682 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
687 hcd->uses_new_polling = 1;
689 /* EHCI spec section 4.1 */
691 * TDI driver does the ehci_reset in their reset callback.
692 * Don't reset here, because configuration settings will
695 if (!ehci_is_TDI(ehci) && (retval = ehci_reset(ehci)) != 0) {
696 ehci_mem_cleanup(ehci);
699 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
700 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
703 * hcc_params controls whether ehci->regs->segment must (!!!)
704 * be used; it constrains QH/ITD/SITD and QTD locations.
705 * pci_pool consistent memory always uses segment zero.
706 * streaming mappings for I/O buffers, like pci_map_single(),
707 * can return segments above 4GB, if the device allows.
709 * NOTE: the dma mask is visible through dma_supported(), so
710 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
711 * Scsi_Host.highmem_io, and so forth. It's readonly to all
712 * host side drivers though.
714 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
715 if (HCC_64BIT_ADDR(hcc_params)) {
716 ehci_writel(ehci, 0, &ehci->regs->segment);
718 // this is deeply broken on almost all architectures
719 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
720 ehci_info(ehci, "enabled 64bit DMA\n");
725 // Philips, Intel, and maybe others need CMD_RUN before the
726 // root hub will detect new devices (why?); NEC doesn't
727 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
728 ehci->command |= CMD_RUN;
729 ehci_writel(ehci, ehci->command, &ehci->regs->command);
730 dbg_cmd (ehci, "init", ehci->command);
733 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
734 * are explicitly handed to companion controller(s), so no TT is
735 * involved with the root hub. (Except where one is integrated,
736 * and there's no companion controller unless maybe for USB OTG.)
738 * Turning on the CF flag will transfer ownership of all ports
739 * from the companions to the EHCI controller. If any of the
740 * companions are in the middle of a port reset at the time, it
741 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
742 * guarantees that no resets are in progress. After we set CF,
743 * a short delay lets the hardware catch up; new resets shouldn't
744 * be started before the port switching actions could complete.
746 down_write(&ehci_cf_port_reset_rwsem);
747 ehci->rh_state = EHCI_RH_RUNNING;
748 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
749 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
751 up_write(&ehci_cf_port_reset_rwsem);
752 ehci->last_periodic_enable = ktime_get_real();
754 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
756 "USB %x.%x started, EHCI %x.%02x%s\n",
757 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
758 temp >> 8, temp & 0xff,
759 ignore_oc ? ", overcurrent ignored" : "");
761 ehci_writel(ehci, INTR_MASK,
762 &ehci->regs->intr_enable); /* Turn On Interrupts */
764 /* GRR this is run-once init(), being done every time the HC starts.
765 * So long as they're part of class devices, we can't do it init()
766 * since the class device isn't created that early.
768 create_debug_files(ehci);
769 create_sysfs_files(ehci);
774 static int __maybe_unused ehci_setup (struct usb_hcd *hcd)
776 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
779 ehci->regs = (void __iomem *)ehci->caps +
780 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
781 dbg_hcs_params(ehci, "reset");
782 dbg_hcc_params(ehci, "reset");
784 /* cache this readonly data; minimize chip reads */
785 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
787 ehci->sbrn = HCD_USB2;
789 retval = ehci_halt(ehci);
793 /* data structure init */
794 retval = ehci_init(hcd);
803 /*-------------------------------------------------------------------------*/
805 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
807 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
808 u32 status, masked_status, pcd_status = 0, cmd;
813 * For threadirqs option we use spin_lock_irqsave() variant to prevent
814 * deadlock with ehci hrtimer callback, because hrtimer callbacks run
815 * in interrupt context even when threadirqs is specified. We can go
816 * back to spin_lock() variant when hrtimer callbacks become threaded.
818 spin_lock_irqsave(&ehci->lock, flags);
820 status = ehci_readl(ehci, &ehci->regs->status);
822 /* e.g. cardbus physical eject */
823 if (status == ~(u32) 0) {
824 ehci_dbg (ehci, "device removed\n");
829 * We don't use STS_FLR, but some controllers don't like it to
830 * remain on, so mask it out along with the other status bits.
832 masked_status = status & (INTR_MASK | STS_FLR);
835 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
836 spin_unlock_irqrestore(&ehci->lock, flags);
840 /* clear (just) interrupts */
841 ehci_writel(ehci, masked_status, &ehci->regs->status);
842 cmd = ehci_readl(ehci, &ehci->regs->command);
846 /* unrequested/ignored: Frame List Rollover */
847 dbg_status (ehci, "irq", status);
850 /* INT, ERR, and IAA interrupt rates can be throttled */
852 /* normal [4.15.1.2] or error [4.15.1.1] completion */
853 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
854 if (likely ((status & STS_ERR) == 0))
855 COUNT (ehci->stats.normal);
857 COUNT (ehci->stats.error);
861 /* complete the unlinking of some qh [4.15.2.3] */
862 if (status & STS_IAA) {
863 /* guard against (alleged) silicon errata */
864 if (cmd & CMD_IAAD) {
865 ehci_writel(ehci, cmd & ~CMD_IAAD,
866 &ehci->regs->command);
867 ehci_dbg(ehci, "IAA with IAAD still set?\n");
870 COUNT(ehci->stats.reclaim);
871 end_unlink_async(ehci);
873 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
876 /* remote wakeup [4.3.1] */
877 if (status & STS_PCD) {
878 unsigned i = HCS_N_PORTS (ehci->hcs_params);
881 /* kick root hub later */
884 /* resume root hub? */
885 if (ehci->rh_state == EHCI_RH_SUSPENDED)
886 usb_hcd_resume_root_hub(hcd);
888 /* get per-port change detect bits */
895 /* leverage per-port change bits feature */
896 if (ehci->has_ppcd && !(ppcd & (1 << i)))
898 pstatus = ehci_readl(ehci,
899 &ehci->regs->port_status[i]);
901 if (pstatus & PORT_OWNER)
903 if (!(test_bit(i, &ehci->suspended_ports) &&
904 ((pstatus & PORT_RESUME) ||
905 !(pstatus & PORT_SUSPEND)) &&
906 (pstatus & PORT_PE) &&
907 ehci->reset_done[i] == 0))
910 /* start 20 msec resume signaling from this port,
911 * and make khubd collect PORT_STAT_C_SUSPEND to
912 * stop that signaling. Use 5 ms extra for safety,
913 * like usb_port_resume() does.
915 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
916 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
917 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
921 /* PCI errors [4.15.2.4] */
922 if (unlikely ((status & STS_FATAL) != 0)) {
923 ehci_err(ehci, "fatal error\n");
924 dbg_cmd(ehci, "fatal", cmd);
925 dbg_status(ehci, "fatal", status);
929 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
931 /* generic layer kills/unlinks all urbs, then
932 * uses ehci_stop to clean up the rest
939 spin_unlock_irqrestore(&ehci->lock, flags);
941 usb_hcd_poll_rh_status(hcd);
945 /*-------------------------------------------------------------------------*/
948 * non-error returns are a promise to giveback() the urb later
949 * we drop ownership so next owner (or urb unlink) can get it
951 * urb + dev is in hcd.self.controller.urb_list
952 * we're queueing TDs onto software and hardware lists
954 * hcd-specific init for hcpriv hasn't been done yet
956 * NOTE: control, bulk, and interrupt share the same code to append TDs
957 * to a (possibly active) QH, and the same QH scanning code.
959 static int ehci_urb_enqueue (
964 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
965 struct list_head qtd_list;
967 INIT_LIST_HEAD (&qtd_list);
969 switch (usb_pipetype (urb->pipe)) {
971 /* qh_completions() code doesn't handle all the fault cases
972 * in multi-TD control transfers. Even 1KB is rare anyway.
974 if (urb->transfer_buffer_length > (16 * 1024))
977 /* case PIPE_BULK: */
979 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
981 return submit_async(ehci, urb, &qtd_list, mem_flags);
984 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
986 return intr_submit(ehci, urb, &qtd_list, mem_flags);
988 case PIPE_ISOCHRONOUS:
989 if (urb->dev->speed == USB_SPEED_HIGH)
990 return itd_submit (ehci, urb, mem_flags);
992 return sitd_submit (ehci, urb, mem_flags);
996 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
999 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim)
1000 end_unlink_async(ehci);
1002 /* If the QH isn't linked then there's nothing we can do
1003 * unless we were called during a giveback, in which case
1004 * qh_completions() has to deal with it.
1006 if (qh->qh_state != QH_STATE_LINKED) {
1007 if (qh->qh_state == QH_STATE_COMPLETING)
1008 qh->needs_rescan = 1;
1012 /* defer till later if busy */
1013 if (ehci->reclaim) {
1014 struct ehci_qh *last;
1016 for (last = ehci->reclaim;
1018 last = last->reclaim)
1020 qh->qh_state = QH_STATE_UNLINK_WAIT;
1023 /* start IAA cycle */
1025 start_unlink_async (ehci, qh);
1028 /* remove from hardware lists
1029 * completions normally happen asynchronously
1032 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1034 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1036 unsigned long flags;
1039 spin_lock_irqsave (&ehci->lock, flags);
1040 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
1044 switch (usb_pipetype (urb->pipe)) {
1045 // case PIPE_CONTROL:
1048 qh = (struct ehci_qh *) urb->hcpriv;
1051 switch (qh->qh_state) {
1052 case QH_STATE_LINKED:
1053 case QH_STATE_COMPLETING:
1054 unlink_async(ehci, qh);
1056 case QH_STATE_UNLINK:
1057 case QH_STATE_UNLINK_WAIT:
1058 /* already started */
1061 /* QH might be waiting for a Clear-TT-Buffer */
1062 qh_completions(ehci, qh);
1067 case PIPE_INTERRUPT:
1068 qh = (struct ehci_qh *) urb->hcpriv;
1071 switch (qh->qh_state) {
1072 case QH_STATE_LINKED:
1073 case QH_STATE_COMPLETING:
1074 intr_deschedule (ehci, qh);
1077 qh_completions (ehci, qh);
1080 ehci_dbg (ehci, "bogus qh %p state %d\n",
1086 case PIPE_ISOCHRONOUS:
1089 // wait till next completion, do it then.
1090 // completion irqs can wait up to 1024 msec,
1094 spin_unlock_irqrestore (&ehci->lock, flags);
1098 /*-------------------------------------------------------------------------*/
1100 // bulk qh holds the data toggle
1103 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1105 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1106 unsigned long flags;
1107 struct ehci_qh *qh, *tmp;
1109 /* ASSERT: any requests/urbs are being unlinked */
1110 /* ASSERT: nobody can be submitting urbs for this any more */
1113 spin_lock_irqsave (&ehci->lock, flags);
1118 /* endpoints can be iso streams. for now, we don't
1119 * accelerate iso completions ... so spin a while.
1121 if (qh->hw == NULL) {
1122 ehci_vdbg (ehci, "iso delay\n");
1126 if (ehci->rh_state != EHCI_RH_RUNNING)
1127 qh->qh_state = QH_STATE_IDLE;
1128 switch (qh->qh_state) {
1129 case QH_STATE_LINKED:
1130 case QH_STATE_COMPLETING:
1131 for (tmp = ehci->async->qh_next.qh;
1133 tmp = tmp->qh_next.qh)
1135 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1136 * may already be unlinked.
1139 unlink_async(ehci, qh);
1141 case QH_STATE_UNLINK: /* wait for hw to finish? */
1142 case QH_STATE_UNLINK_WAIT:
1144 spin_unlock_irqrestore (&ehci->lock, flags);
1145 schedule_timeout_uninterruptible(1);
1147 case QH_STATE_IDLE: /* fully unlinked */
1148 if (qh->clearing_tt)
1150 if (list_empty (&qh->qtd_list)) {
1154 /* else FALL THROUGH */
1156 /* caller was supposed to have unlinked any requests;
1157 * that's not our job. just leak this memory.
1159 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1160 qh, ep->desc.bEndpointAddress, qh->qh_state,
1161 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1166 spin_unlock_irqrestore (&ehci->lock, flags);
1170 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1172 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1174 int eptype = usb_endpoint_type(&ep->desc);
1175 int epnum = usb_endpoint_num(&ep->desc);
1176 int is_out = usb_endpoint_dir_out(&ep->desc);
1177 unsigned long flags;
1179 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1182 spin_lock_irqsave(&ehci->lock, flags);
1185 /* For Bulk and Interrupt endpoints we maintain the toggle state
1186 * in the hardware; the toggle bits in udev aren't used at all.
1187 * When an endpoint is reset by usb_clear_halt() we must reset
1188 * the toggle bit in the QH.
1191 usb_settoggle(qh->dev, epnum, is_out, 0);
1192 if (!list_empty(&qh->qtd_list)) {
1193 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1194 } else if (qh->qh_state == QH_STATE_LINKED ||
1195 qh->qh_state == QH_STATE_COMPLETING) {
1197 /* The toggle value in the QH can't be updated
1198 * while the QH is active. Unlink it now;
1199 * re-linking will call qh_refresh().
1201 if (eptype == USB_ENDPOINT_XFER_BULK)
1202 unlink_async(ehci, qh);
1204 intr_deschedule(ehci, qh);
1207 spin_unlock_irqrestore(&ehci->lock, flags);
1210 static int ehci_get_frame (struct usb_hcd *hcd)
1212 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1213 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1216 /*-------------------------------------------------------------------------*/
1218 MODULE_DESCRIPTION(DRIVER_DESC);
1219 MODULE_AUTHOR (DRIVER_AUTHOR);
1220 MODULE_LICENSE ("GPL");
1223 #include "ehci-pci.c"
1224 #define PCI_DRIVER ehci_pci_driver
1227 #ifdef CONFIG_USB_EHCI_FSL
1228 #include "ehci-fsl.c"
1229 #define PLATFORM_DRIVER ehci_fsl_driver
1232 #ifdef CONFIG_USB_EHCI_MXC
1233 #include "ehci-mxc.c"
1234 #define PLATFORM_DRIVER ehci_mxc_driver
1237 #ifdef CONFIG_USB_EHCI_SH
1238 #include "ehci-sh.c"
1239 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1242 #ifdef CONFIG_MIPS_ALCHEMY
1243 #include "ehci-au1xxx.c"
1244 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1247 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1248 #include "ehci-omap.c"
1249 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1252 #ifdef CONFIG_PPC_PS3
1253 #include "ehci-ps3.c"
1254 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1257 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1258 #include "ehci-ppc-of.c"
1259 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1262 #ifdef CONFIG_XPS_USB_HCD_XILINX
1263 #include "ehci-xilinx-of.c"
1264 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1267 #ifdef CONFIG_PLAT_ORION
1268 #include "ehci-orion.c"
1269 #define PLATFORM_DRIVER ehci_orion_driver
1272 #ifdef CONFIG_ARCH_IXP4XX
1273 #include "ehci-ixp4xx.c"
1274 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1277 #ifdef CONFIG_USB_W90X900_EHCI
1278 #include "ehci-w90x900.c"
1279 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1282 #ifdef CONFIG_ARCH_AT91
1283 #include "ehci-atmel.c"
1284 #define PLATFORM_DRIVER ehci_atmel_driver
1287 #ifdef CONFIG_USB_OCTEON_EHCI
1288 #include "ehci-octeon.c"
1289 #define PLATFORM_DRIVER ehci_octeon_driver
1292 #ifdef CONFIG_USB_CNS3XXX_EHCI
1293 #include "ehci-cns3xxx.c"
1294 #define PLATFORM_DRIVER cns3xxx_ehci_driver
1297 #ifdef CONFIG_ARCH_VT8500
1298 #include "ehci-vt8500.c"
1299 #define PLATFORM_DRIVER vt8500_ehci_driver
1302 #ifdef CONFIG_PLAT_SPEAR
1303 #include "ehci-spear.c"
1304 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1307 #ifdef CONFIG_USB_EHCI_MSM
1308 #include "ehci-msm.c"
1309 #define PLATFORM_DRIVER ehci_msm_driver
1312 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1313 #include "ehci-pmcmsp.c"
1314 #define PLATFORM_DRIVER ehci_hcd_msp_driver
1317 #ifdef CONFIG_USB_EHCI_TEGRA
1318 #include "ehci-tegra.c"
1319 #define PLATFORM_DRIVER tegra_ehci_driver
1322 #ifdef CONFIG_USB_EHCI_S5P
1323 #include "ehci-s5p.c"
1324 #define PLATFORM_DRIVER s5p_ehci_driver
1327 #ifdef CONFIG_USB_EHCI_ATH79
1328 #include "ehci-ath79.c"
1329 #define PLATFORM_DRIVER ehci_ath79_driver
1332 #ifdef CONFIG_SPARC_LEON
1333 #include "ehci-grlib.c"
1334 #define PLATFORM_DRIVER ehci_grlib_driver
1337 #ifdef CONFIG_USB_PXA168_EHCI
1338 #include "ehci-pxa168.c"
1339 #define PLATFORM_DRIVER ehci_pxa168_driver
1342 #ifdef CONFIG_NLM_XLR
1343 #include "ehci-xls.c"
1344 #define PLATFORM_DRIVER ehci_xls_driver
1347 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1348 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1349 !defined(XILINX_OF_PLATFORM_DRIVER)
1350 #error "missing bus glue for ehci-hcd"
1353 static int __init ehci_hcd_init(void)
1360 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1361 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1362 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1363 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1364 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1365 " before uhci_hcd and ohci_hcd, not after\n");
1367 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1369 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1370 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1373 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1374 if (!ehci_debug_root) {
1380 #ifdef PLATFORM_DRIVER
1381 retval = platform_driver_register(&PLATFORM_DRIVER);
1387 retval = pci_register_driver(&PCI_DRIVER);
1392 #ifdef PS3_SYSTEM_BUS_DRIVER
1393 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1398 #ifdef OF_PLATFORM_DRIVER
1399 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1404 #ifdef XILINX_OF_PLATFORM_DRIVER
1405 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1411 #ifdef XILINX_OF_PLATFORM_DRIVER
1412 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1415 #ifdef OF_PLATFORM_DRIVER
1416 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1419 #ifdef PS3_SYSTEM_BUS_DRIVER
1420 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1424 pci_unregister_driver(&PCI_DRIVER);
1427 #ifdef PLATFORM_DRIVER
1428 platform_driver_unregister(&PLATFORM_DRIVER);
1432 debugfs_remove(ehci_debug_root);
1433 ehci_debug_root = NULL;
1436 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1439 module_init(ehci_hcd_init);
1441 static void __exit ehci_hcd_cleanup(void)
1443 #ifdef XILINX_OF_PLATFORM_DRIVER
1444 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1446 #ifdef OF_PLATFORM_DRIVER
1447 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1449 #ifdef PLATFORM_DRIVER
1450 platform_driver_unregister(&PLATFORM_DRIVER);
1453 pci_unregister_driver(&PCI_DRIVER);
1455 #ifdef PS3_SYSTEM_BUS_DRIVER
1456 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1459 debugfs_remove(ehci_debug_root);
1461 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1463 module_exit(ehci_hcd_cleanup);