drivers/usb/gadget/pxa2xx_udc.c

   1 /*
   2  * linux/drivers/usb/gadget/pxa2xx_udc.c
   3  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
   4  *
   5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   8  * Copyright (C) 2003 David Brownell
   9  * Copyright (C) 2003 Joshua Wise
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  *
  25  */
  26
  27 #undef  DEBUG
  28 // #define      VERBOSE DBG_VERBOSE
  29
  30 #include <linux/module.h>
  31 #include <linux/kernel.h>
  32 #include <linux/ioport.h>
  33 #include <linux/types.h>
  34 #include <linux/errno.h>
  35 #include <linux/delay.h>
  36 #include <linux/slab.h>
  37 #include <linux/init.h>
  38 #include <linux/timer.h>
  39 #include <linux/list.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/proc_fs.h>
  42 #include <linux/mm.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/irq.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/dma.h>
  49 #include <asm/io.h>
  50 #include <asm/system.h>
  51 #include <asm/mach-types.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/hardware.h>
  54 #ifdef CONFIG_ARCH_PXA
  55 #include <asm/arch/pxa-regs.h>
  56 #endif
  57
  58 #include <linux/usb/ch9.h>
  59 #include <linux/usb_gadget.h>
  60
  61 #include <asm/arch/udc.h>
  62
  63
  64 /*
  65  * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
  66  * series processors.  The UDC for the IXP 4xx series is very similar.
  67  * There are fifteen endpoints, in addition to ep0.
  68  *
  69  * Such controller drivers work with a gadget driver.  The gadget driver
  70  * returns descriptors, implements configuration and data protocols used
  71  * by the host to interact with this device, and allocates endpoints to
  72  * the different protocol interfaces.  The controller driver virtualizes
  73  * usb hardware so that the gadget drivers will be more portable.
  74  *
  75  * This UDC hardware wants to implement a bit too much USB protocol, so
  76  * it constrains the sorts of USB configuration change events that work.
  77  * The errata for these chips are misleading; some "fixed" bugs from
  78  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  79  */
  80
  81 #define DRIVER_VERSION  "4-May-2005"
  82 #define DRIVER_DESC     "PXA 25x USB Device Controller driver"
  83
  84
  85 static const char driver_name [] = "pxa2xx_udc";
  86
  87 static const char ep0name [] = "ep0";
  88
  89
  90 // #define      USE_DMA
  91 // #define      USE_OUT_DMA
  92 // #define      DISABLE_TEST_MODE
  93
  94 #ifdef CONFIG_ARCH_IXP4XX
  95 #undef USE_DMA
  96
  97 /* cpu-specific register addresses are compiled in to this code */
  98 #ifdef CONFIG_ARCH_PXA
  99 #error "Can't configure both IXP and PXA"
 100 #endif
 101
 102 #endif
 103
 104 #include "pxa2xx_udc.h"
 105
 106
 107 #ifdef  USE_DMA
 108 static int use_dma = 1;
 109 module_param(use_dma, bool, 0);
 110 MODULE_PARM_DESC (use_dma, "true to use dma");
 111
 112 static void dma_nodesc_handler (int dmach, void *_ep);
 113 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req);
 114
 115 #ifdef USE_OUT_DMA
 116 #define DMASTR " (dma support)"
 117 #else
 118 #define DMASTR " (dma in)"
 119 #endif
 120
 121 #else   /* !USE_DMA */
 122 #define DMASTR " (pio only)"
 123 #undef  USE_OUT_DMA
 124 #endif
 125
 126 #ifdef  CONFIG_USB_PXA2XX_SMALL
 127 #define SIZE_STR        " (small)"
 128 #else
 129 #define SIZE_STR        ""
 130 #endif
 131
 132 #ifdef DISABLE_TEST_MODE
 133 /* (mode == 0) == no undocumented chip tweaks
 134  * (mode & 1)  == double buffer bulk IN
 135  * (mode & 2)  == double buffer bulk OUT
 136  * ... so mode = 3 (or 7, 15, etc) does it for both
 137  */
 138 static ushort fifo_mode = 0;
 139 module_param(fifo_mode, ushort, 0);
 140 MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
 141 #endif
 142
 143 /* ---------------------------------------------------------------------------
 144  *      endpoint related parts of the api to the usb controller hardware,
 145  *      used by gadget driver; and the inner talker-to-hardware core.
 146  * ---------------------------------------------------------------------------
 147  */
 148
 149 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
 150 static void nuke (struct pxa2xx_ep *, int status);
 151
 152 /* one GPIO should be used to detect VBUS from the host */
 153 static int is_vbus_present(void)
 154 {
 155         struct pxa2xx_udc_mach_info             *mach = the_controller->mach;
 156
 157         if (mach->gpio_vbus)
 158                 return udc_gpio_get(mach->gpio_vbus);
 159         if (mach->udc_is_connected)
 160                 return mach->udc_is_connected();
 161         return 1;
 162 }
 163
 164 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
 165 static void pullup_off(void)
 166 {
 167         struct pxa2xx_udc_mach_info             *mach = the_controller->mach;
 168
 169         if (mach->gpio_pullup)
 170                 udc_gpio_set(mach->gpio_pullup, 0);
 171         else if (mach->udc_command)
 172                 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
 173 }
 174
 175 static void pullup_on(void)
 176 {
 177         struct pxa2xx_udc_mach_info             *mach = the_controller->mach;
 178
 179         if (mach->gpio_pullup)
 180                 udc_gpio_set(mach->gpio_pullup, 1);
 181         else if (mach->udc_command)
 182                 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
 183 }
 184
 185 static void pio_irq_enable(int bEndpointAddress)
 186 {
 187         bEndpointAddress &= 0xf;
 188         if (bEndpointAddress < 8)
 189                 UICR0 &= ~(1 << bEndpointAddress);
 190         else {
 191                 bEndpointAddress -= 8;
 192                 UICR1 &= ~(1 << bEndpointAddress);
 193         }
 194 }
 195
 196 static void pio_irq_disable(int bEndpointAddress)
 197 {
 198         bEndpointAddress &= 0xf;
 199         if (bEndpointAddress < 8)
 200                 UICR0 |= 1 << bEndpointAddress;
 201         else {
 202                 bEndpointAddress -= 8;
 203                 UICR1 |= 1 << bEndpointAddress;
 204         }
 205 }
 206
 207 /* The UDCCR reg contains mask and interrupt status bits,
 208  * so using '|=' isn't safe as it may ack an interrupt.
 209  */
 210 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
 211
 212 static inline void udc_set_mask_UDCCR(int mask)
 213 {
 214         UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
 215 }
 216
 217 static inline void udc_clear_mask_UDCCR(int mask)
 218 {
 219         UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
 220 }
 221
 222 static inline void udc_ack_int_UDCCR(int mask)
 223 {
 224         /* udccr contains the bits we dont want to change */
 225         __u32 udccr = UDCCR & UDCCR_MASK_BITS;
 226
 227         UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
 228 }
 229
 230 /*
 231  * endpoint enable/disable
 232  *
 233  * we need to verify the descriptors used to enable endpoints.  since pxa2xx
 234  * endpoint configurations are fixed, and are pretty much always enabled,
 235  * there's not a lot to manage here.
 236  *
 237  * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
 238  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 239  * for a single interface (with only the default altsetting) and for gadget
 240  * drivers that don't halt endpoints (not reset by set_interface).  that also
 241  * means that if you use ISO, you must violate the USB spec rule that all
 242  * iso endpoints must be in non-default altsettings.
 243  */
 244 static int pxa2xx_ep_enable (struct usb_ep *_ep,
 245                 const struct usb_endpoint_descriptor *desc)
 246 {
 247         struct pxa2xx_ep        *ep;
 248         struct pxa2xx_udc       *dev;
 249
 250         ep = container_of (_ep, struct pxa2xx_ep, ep);
 251         if (!_ep || !desc || ep->desc || _ep->name == ep0name
 252                         || desc->bDescriptorType != USB_DT_ENDPOINT
 253                         || ep->bEndpointAddress != desc->bEndpointAddress
 254                         || ep->fifo_size < le16_to_cpu
 255                                                 (desc->wMaxPacketSize)) {
 256                 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
 257                 return -EINVAL;
 258         }
 259
 260         /* xfer types must match, except that interrupt ~= bulk */
 261         if (ep->bmAttributes != desc->bmAttributes
 262                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 263                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 264                 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 265                 return -EINVAL;
 266         }
 267
 268         /* hardware _could_ do smaller, but driver doesn't */
 269         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 270                                 && le16_to_cpu (desc->wMaxPacketSize)
 271                                                 != BULK_FIFO_SIZE)
 272                         || !desc->wMaxPacketSize) {
 273                 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 274                 return -ERANGE;
 275         }
 276
 277         dev = ep->dev;
 278         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 279                 DMSG("%s, bogus device state\n", __FUNCTION__);
 280                 return -ESHUTDOWN;
 281         }
 282
 283         ep->desc = desc;
 284         ep->dma = -1;
 285         ep->stopped = 0;
 286         ep->pio_irqs = ep->dma_irqs = 0;
 287         ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 288
 289         /* flush fifo (mostly for OUT buffers) */
 290         pxa2xx_ep_fifo_flush (_ep);
 291
 292         /* ... reset halt state too, if we could ... */
 293
 294 #ifdef  USE_DMA
 295         /* for (some) bulk and ISO endpoints, try to get a DMA channel and
 296          * bind it to the endpoint.  otherwise use PIO.
 297          */
 298         switch (ep->bmAttributes) {
 299         case USB_ENDPOINT_XFER_ISOC:
 300                 if (le16_to_cpu(desc->wMaxPacketSize) % 32)
 301                         break;
 302                 // fall through
 303         case USB_ENDPOINT_XFER_BULK:
 304                 if (!use_dma || !ep->reg_drcmr)
 305                         break;
 306                 ep->dma = pxa_request_dma ((char *)_ep->name,
 307                                 (le16_to_cpu (desc->wMaxPacketSize) > 64)
 308                                         ? DMA_PRIO_MEDIUM /* some iso */
 309                                         : DMA_PRIO_LOW,
 310                                 dma_nodesc_handler, ep);
 311                 if (ep->dma >= 0) {
 312                         *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
 313                         DMSG("%s using dma%d\n", _ep->name, ep->dma);
 314                 }
 315         }
 316 #endif
 317
 318         DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 319         return 0;
 320 }
 321
 322 static int pxa2xx_ep_disable (struct usb_ep *_ep)
 323 {
 324         struct pxa2xx_ep        *ep;
 325         unsigned long           flags;
 326
 327         ep = container_of (_ep, struct pxa2xx_ep, ep);
 328         if (!_ep || !ep->desc) {
 329                 DMSG("%s, %s not enabled\n", __FUNCTION__,
 330                         _ep ? ep->ep.name : NULL);
 331                 return -EINVAL;
 332         }
 333         local_irq_save(flags);
 334
 335         nuke (ep, -ESHUTDOWN);
 336
 337 #ifdef  USE_DMA
 338         if (ep->dma >= 0) {
 339                 *ep->reg_drcmr = 0;
 340                 pxa_free_dma (ep->dma);
 341                 ep->dma = -1;
 342         }
 343 #endif
 344
 345         /* flush fifo (mostly for IN buffers) */
 346         pxa2xx_ep_fifo_flush (_ep);
 347
 348         ep->desc = NULL;
 349         ep->stopped = 1;
 350
 351         local_irq_restore(flags);
 352         DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 353         return 0;
 354 }
 355
 356 /*-------------------------------------------------------------------------*/
 357
 358 /* for the pxa2xx, these can just wrap kmalloc/kfree.  gadget drivers
 359  * must still pass correctly initialized endpoints, since other controller
 360  * drivers may care about how it's currently set up (dma issues etc).
 361  */
 362
 363 /*
 364  *      pxa2xx_ep_alloc_request - allocate a request data structure
 365  */
 366 static struct usb_request *
 367 pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
 368 {
 369         struct pxa2xx_request *req;
 370
 371         req = kzalloc(sizeof(*req), gfp_flags);
 372         if (!req)
 373                 return NULL;
 374
 375         INIT_LIST_HEAD (&req->queue);
 376         return &req->req;
 377 }
 378
 379
 380 /*
 381  *      pxa2xx_ep_free_request - deallocate a request data structure
 382  */
 383 static void
 384 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 385 {
 386         struct pxa2xx_request   *req;
 387
 388         req = container_of (_req, struct pxa2xx_request, req);
 389         WARN_ON (!list_empty (&req->queue));
 390         kfree(req);
 391 }
 392
 393
 394 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
 395  * no device-affinity and the heap works perfectly well for i/o buffers.
 396  * It wastes much less memory than dma_alloc_coherent() would, and even
 397  * prevents cacheline (32 bytes wide) sharing problems.
 398  */
 399 static void *
 400 pxa2xx_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
 401         dma_addr_t *dma, gfp_t gfp_flags)
 402 {
 403         char                    *retval;
 404
 405         retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
 406         if (retval)
 407 #ifdef  USE_DMA
 408                 *dma = virt_to_bus (retval);
 409 #else
 410                 *dma = (dma_addr_t)~0;
 411 #endif
 412         return retval;
 413 }
 414
 415 static void
 416 pxa2xx_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
 417                 unsigned bytes)
 418 {
 419         kfree (buf);
 420 }
 421
 422 /*-------------------------------------------------------------------------*/
 423
 424 /*
 425  *      done - retire a request; caller blocked irqs
 426  */
 427 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
 428 {
 429         unsigned                stopped = ep->stopped;
 430
 431         list_del_init(&req->queue);
 432
 433         if (likely (req->req.status == -EINPROGRESS))
 434                 req->req.status = status;
 435         else
 436                 status = req->req.status;
 437
 438         if (status && status != -ESHUTDOWN)
 439                 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 440                         ep->ep.name, &req->req, status,
 441                         req->req.actual, req->req.length);
 442
 443         /* don't modify queue heads during completion callback */
 444         ep->stopped = 1;
 445         req->req.complete(&ep->ep, &req->req);
 446         ep->stopped = stopped;
 447 }
 448
 449
 450 static inline void ep0_idle (struct pxa2xx_udc *dev)
 451 {
 452         dev->ep0state = EP0_IDLE;
 453 }
 454
 455 static int
 456 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
 457 {
 458         u8              *buf;
 459         unsigned        length, count;
 460
 461         buf = req->req.buf + req->req.actual;
 462         prefetch(buf);
 463
 464         /* how big will this packet be? */
 465         length = min(req->req.length - req->req.actual, max);
 466         req->req.actual += length;
 467
 468         count = length;
 469         while (likely(count--))
 470                 *uddr = *buf++;
 471
 472         return length;
 473 }
 474
 475 /*
 476  * write to an IN endpoint fifo, as many packets as possible.
 477  * irqs will use this to write the rest later.
 478  * caller guarantees at least one packet buffer is ready (or a zlp).
 479  */
 480 static int
 481 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 482 {
 483         unsigned                max;
 484
 485         max = le16_to_cpu(ep->desc->wMaxPacketSize);
 486         do {
 487                 unsigned        count;
 488                 int             is_last, is_short;
 489
 490                 count = write_packet(ep->reg_uddr, req, max);
 491
 492                 /* last packet is usually short (or a zlp) */
 493                 if (unlikely (count != max))
 494                         is_last = is_short = 1;
 495                 else {
 496                         if (likely(req->req.length != req->req.actual)
 497                                         || req->req.zero)
 498                                 is_last = 0;
 499                         else
 500                                 is_last = 1;
 501                         /* interrupt/iso maxpacket may not fill the fifo */
 502                         is_short = unlikely (max < ep->fifo_size);
 503                 }
 504
 505                 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 506                         ep->ep.name, count,
 507                         is_last ? "/L" : "", is_short ? "/S" : "",
 508                         req->req.length - req->req.actual, req);
 509
 510                 /* let loose that packet. maybe try writing another one,
 511                  * double buffering might work.  TSP, TPC, and TFS
 512                  * bit values are the same for all normal IN endpoints.
 513                  */
 514                 *ep->reg_udccs = UDCCS_BI_TPC;
 515                 if (is_short)
 516                         *ep->reg_udccs = UDCCS_BI_TSP;
 517
 518                 /* requests complete when all IN data is in the FIFO */
 519                 if (is_last) {
 520                         done (ep, req, 0);
 521                         if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
 522                                 pio_irq_disable (ep->bEndpointAddress);
 523 #ifdef USE_DMA
 524                                 /* unaligned data and zlps couldn't use dma */
 525                                 if (unlikely(!list_empty(&ep->queue))) {
 526                                         req = list_entry(ep->queue.next,
 527                                                 struct pxa2xx_request, queue);
 528                                         kick_dma(ep,req);
 529                                         return 0;
 530                                 }
 531 #endif
 532                         }
 533                         return 1;
 534                 }
 535
 536                 // TODO experiment: how robust can fifo mode tweaking be?
 537                 // double buffering is off in the default fifo mode, which
 538                 // prevents TFS from being set here.
 539
 540         } while (*ep->reg_udccs & UDCCS_BI_TFS);
 541         return 0;
 542 }
 543
 544 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
 545  * ep0 data stage.  these chips want very simple state transitions.
 546  */
 547 static inline
 548 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
 549 {
 550         UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
 551         USIR0 = USIR0_IR0;
 552         dev->req_pending = 0;
 553         DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 554                 __FUNCTION__, tag, UDCCS0, flags);
 555 }
 556
 557 static int
 558 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 559 {
 560         unsigned        count;
 561         int             is_short;
 562
 563         count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
 564         ep->dev->stats.write.bytes += count;
 565
 566         /* last packet "must be" short (or a zlp) */
 567         is_short = (count != EP0_FIFO_SIZE);
 568
 569         DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 570                 req->req.length - req->req.actual, req);
 571
 572         if (unlikely (is_short)) {
 573                 if (ep->dev->req_pending)
 574                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 575                 else
 576                         UDCCS0 = UDCCS0_IPR;
 577
 578                 count = req->req.length;
 579                 done (ep, req, 0);
 580                 ep0_idle(ep->dev);
 581 #ifndef CONFIG_ARCH_IXP4XX
 582 #if 1
 583                 /* This seems to get rid of lost status irqs in some cases:
 584                  * host responds quickly, or next request involves config
 585                  * change automagic, or should have been hidden, or ...
 586                  *
 587                  * FIXME get rid of all udelays possible...
 588                  */
 589                 if (count >= EP0_FIFO_SIZE) {
 590                         count = 100;
 591                         do {
 592                                 if ((UDCCS0 & UDCCS0_OPR) != 0) {
 593                                         /* clear OPR, generate ack */
 594                                         UDCCS0 = UDCCS0_OPR;
 595                                         break;
 596                                 }
 597                                 count--;
 598                                 udelay(1);
 599                         } while (count);
 600                 }
 601 #endif
 602 #endif
 603         } else if (ep->dev->req_pending)
 604                 ep0start(ep->dev, 0, "IN");
 605         return is_short;
 606 }
 607
 608
 609 /*
 610  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 611  * transfers and put them into the request.  caller should have made
 612  * sure there's at least one packet ready.
 613  *
 614  * returns true if the request completed because of short packet or the
 615  * request buffer having filled (and maybe overran till end-of-packet).
 616  */
 617 static int
 618 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 619 {
 620         for (;;) {
 621                 u32             udccs;
 622                 u8              *buf;
 623                 unsigned        bufferspace, count, is_short;
 624
 625                 /* make sure there's a packet in the FIFO.
 626                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 627                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 628                  */
 629                 udccs = *ep->reg_udccs;
 630                 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
 631                         break;
 632                 buf = req->req.buf + req->req.actual;
 633                 prefetchw(buf);
 634                 bufferspace = req->req.length - req->req.actual;
 635
 636                 /* read all bytes from this packet */
 637                 if (likely (udccs & UDCCS_BO_RNE)) {
 638                         count = 1 + (0x0ff & *ep->reg_ubcr);
 639                         req->req.actual += min (count, bufferspace);
 640                 } else /* zlp */
 641                         count = 0;
 642                 is_short = (count < ep->ep.maxpacket);
 643                 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 644                         ep->ep.name, udccs, count,
 645                         is_short ? "/S" : "",
 646                         req, req->req.actual, req->req.length);
 647                 while (likely (count-- != 0)) {
 648                         u8      byte = (u8) *ep->reg_uddr;
 649
 650                         if (unlikely (bufferspace == 0)) {
 651                                 /* this happens when the driver's buffer
 652                                  * is smaller than what the host sent.
 653                                  * discard the extra data.
 654                                  */
 655                                 if (req->req.status != -EOVERFLOW)
 656                                         DMSG("%s overflow %d\n",
 657                                                 ep->ep.name, count);
 658                                 req->req.status = -EOVERFLOW;
 659                         } else {
 660                                 *buf++ = byte;
 661                                 bufferspace--;
 662                         }
 663                 }
 664                 *ep->reg_udccs =  UDCCS_BO_RPC;
 665                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 666
 667                 /* iso is one request per packet */
 668                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 669                         if (udccs & UDCCS_IO_ROF)
 670                                 req->req.status = -EHOSTUNREACH;
 671                         /* more like "is_done" */
 672                         is_short = 1;
 673                 }
 674
 675                 /* completion */
 676                 if (is_short || req->req.actual == req->req.length) {
 677                         done (ep, req, 0);
 678                         if (list_empty(&ep->queue))
 679                                 pio_irq_disable (ep->bEndpointAddress);
 680                         return 1;
 681                 }
 682
 683                 /* finished that packet.  the next one may be waiting... */
 684         }
 685         return 0;
 686 }
 687
 688 /*
 689  * special ep0 version of the above.  no UBCR0 or double buffering; status
 690  * handshaking is magic.  most device protocols don't need control-OUT.
 691  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 692  * protocols do use them.
 693  */
 694 static int
 695 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 696 {
 697         u8              *buf, byte;
 698         unsigned        bufferspace;
 699
 700         buf = req->req.buf + req->req.actual;
 701         bufferspace = req->req.length - req->req.actual;
 702
 703         while (UDCCS0 & UDCCS0_RNE) {
 704                 byte = (u8) UDDR0;
 705
 706                 if (unlikely (bufferspace == 0)) {
 707                         /* this happens when the driver's buffer
 708                          * is smaller than what the host sent.
 709                          * discard the extra data.
 710                          */
 711                         if (req->req.status != -EOVERFLOW)
 712                                 DMSG("%s overflow\n", ep->ep.name);
 713                         req->req.status = -EOVERFLOW;
 714                 } else {
 715                         *buf++ = byte;
 716                         req->req.actual++;
 717                         bufferspace--;
 718                 }
 719         }
 720
 721         UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
 722
 723         /* completion */
 724         if (req->req.actual >= req->req.length)
 725                 return 1;
 726
 727         /* finished that packet.  the next one may be waiting... */
 728         return 0;
 729 }
 730
 731 #ifdef  USE_DMA
 732
 733 #define MAX_IN_DMA      ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
 734
 735 static void
 736 start_dma_nodesc(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int is_in)
 737 {
 738         u32     dcmd = req->req.length;
 739         u32     buf = req->req.dma;
 740         u32     fifo = io_v2p ((u32)ep->reg_uddr);
 741
 742         /* caller guarantees there's a packet or more remaining
 743          *  - IN may end with a short packet (TSP set separately),
 744          *  - OUT is always full length
 745          */
 746         buf += req->req.actual;
 747         dcmd -= req->req.actual;
 748         ep->dma_fixup = 0;
 749
 750         /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
 751         DCSR(ep->dma) = DCSR_NODESC;
 752         if (is_in) {
 753                 DSADR(ep->dma) = buf;
 754                 DTADR(ep->dma) = fifo;
 755                 if (dcmd > MAX_IN_DMA)
 756                         dcmd = MAX_IN_DMA;
 757                 else
 758                         ep->dma_fixup = (dcmd % ep->ep.maxpacket) != 0;
 759                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 760                         | DCMD_FLOWTRG | DCMD_INCSRCADDR;
 761         } else {
 762 #ifdef USE_OUT_DMA
 763                 DSADR(ep->dma) = fifo;
 764                 DTADR(ep->dma) = buf;
 765                 if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
 766                         dcmd = ep->ep.maxpacket;
 767                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 768                         | DCMD_FLOWSRC | DCMD_INCTRGADDR;
 769 #endif
 770         }
 771         DCMD(ep->dma) = dcmd;
 772         DCSR(ep->dma) = DCSR_RUN | DCSR_NODESC
 773                 | (unlikely(is_in)
 774                         ? DCSR_STOPIRQEN        /* use dma_nodesc_handler() */
 775                         : 0);                   /* use handle_ep() */
 776 }
 777
 778 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 779 {
 780         int     is_in = ep->bEndpointAddress & USB_DIR_IN;
 781
 782         if (is_in) {
 783                 /* unaligned tx buffers and zlps only work with PIO */
 784                 if ((req->req.dma & 0x0f) != 0
 785                                 || unlikely((req->req.length - req->req.actual)
 786                                                 == 0)) {
 787                         pio_irq_enable(ep->bEndpointAddress);
 788                         if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0)
 789                                 (void) write_fifo(ep, req);
 790                 } else {
 791                         start_dma_nodesc(ep, req, USB_DIR_IN);
 792                 }
 793         } else {
 794                 if ((req->req.length - req->req.actual) < ep->ep.maxpacket) {
 795                         DMSG("%s short dma read...\n", ep->ep.name);
 796                         /* we're always set up for pio out */
 797                         read_fifo (ep, req);
 798                 } else {
 799                         *ep->reg_udccs = UDCCS_BO_DME
 800                                 | (*ep->reg_udccs & UDCCS_BO_FST);
 801                         start_dma_nodesc(ep, req, USB_DIR_OUT);
 802                 }
 803         }
 804 }
 805
 806 static void cancel_dma(struct pxa2xx_ep *ep)
 807 {
 808         struct pxa2xx_request   *req;
 809         u32                     tmp;
 810
 811         if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
 812                 return;
 813
 814         DCSR(ep->dma) = 0;
 815         while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
 816                 cpu_relax();
 817
 818         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 819         tmp = DCMD(ep->dma) & DCMD_LENGTH;
 820         req->req.actual = req->req.length - (tmp & DCMD_LENGTH);
 821
 822         /* the last tx packet may be incomplete, so flush the fifo.
 823          * FIXME correct req.actual if we can
 824          */
 825         if (ep->bEndpointAddress & USB_DIR_IN)
 826                 *ep->reg_udccs = UDCCS_BI_FTF;
 827 }
 828
 829 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
 830 static void dma_nodesc_handler(int dmach, void *_ep)
 831 {
 832         struct pxa2xx_ep        *ep = _ep;
 833         struct pxa2xx_request   *req;
 834         u32                     tmp, completed;
 835
 836         local_irq_disable();
 837
 838         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 839
 840         ep->dma_irqs++;
 841         ep->dev->stats.irqs++;
 842         HEX_DISPLAY(ep->dev->stats.irqs);
 843
 844         /* ack/clear */
 845         tmp = DCSR(ep->dma);
 846         DCSR(ep->dma) = tmp;
 847         if ((tmp & DCSR_STOPSTATE) == 0
 848                         || (DDADR(ep->dma) & DDADR_STOP) != 0) {
 849                 DBG(DBG_VERBOSE, "%s, dcsr %08x ddadr %08x\n",
 850                         ep->ep.name, DCSR(ep->dma), DDADR(ep->dma));
 851                 goto done;
 852         }
 853         DCSR(ep->dma) = 0;      /* clear DCSR_STOPSTATE */
 854
 855         /* update transfer status */
 856         completed = tmp & DCSR_BUSERR;
 857         if (ep->bEndpointAddress & USB_DIR_IN)
 858                 tmp = DSADR(ep->dma);
 859         else
 860                 tmp = DTADR(ep->dma);
 861         req->req.actual = tmp - req->req.dma;
 862
 863         /* FIXME seems we sometimes see partial transfers... */
 864
 865         if (unlikely(completed != 0))
 866                 req->req.status = -EIO;
 867         else if (req->req.actual) {
 868                 /* these registers have zeroes in low bits; they miscount
 869                  * some (end-of-transfer) short packets:  tx 14 as tx 12
 870                  */
 871                 if (ep->dma_fixup)
 872                         req->req.actual = min(req->req.actual + 3,
 873                                                 req->req.length);
 874
 875                 tmp = (req->req.length - req->req.actual);
 876                 completed = (tmp == 0);
 877                 if (completed && (ep->bEndpointAddress & USB_DIR_IN)) {
 878
 879                         /* maybe validate final short packet ... */
 880                         if ((req->req.actual % ep->ep.maxpacket) != 0)
 881                                 *ep->reg_udccs = UDCCS_BI_TSP/*|UDCCS_BI_TPC*/;
 882
 883                         /* ... or zlp, using pio fallback */
 884                         else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK
 885                                         && req->req.zero) {
 886                                 DMSG("%s zlp terminate ...\n", ep->ep.name);
 887                                 completed = 0;
 888                         }
 889                 }
 890         }
 891
 892         if (likely(completed)) {
 893                 done(ep, req, 0);
 894
 895                 /* maybe re-activate after completion */
 896                 if (ep->stopped || list_empty(&ep->queue))
 897                         goto done;
 898                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 899         }
 900         kick_dma(ep, req);
 901 done:
 902         local_irq_enable();
 903 }
 904
 905 #endif
 906
 907 /*-------------------------------------------------------------------------*/
 908
 909 static int
 910 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 911 {
 912         struct pxa2xx_request   *req;
 913         struct pxa2xx_ep        *ep;
 914         struct pxa2xx_udc       *dev;
 915         unsigned long           flags;
 916
 917         req = container_of(_req, struct pxa2xx_request, req);
 918         if (unlikely (!_req || !_req->complete || !_req->buf
 919                         || !list_empty(&req->queue))) {
 920                 DMSG("%s, bad params\n", __FUNCTION__);
 921                 return -EINVAL;
 922         }
 923
 924         ep = container_of(_ep, struct pxa2xx_ep, ep);
 925         if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 926                 DMSG("%s, bad ep\n", __FUNCTION__);
 927                 return -EINVAL;
 928         }
 929
 930         dev = ep->dev;
 931         if (unlikely (!dev->driver
 932                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 933                 DMSG("%s, bogus device state\n", __FUNCTION__);
 934                 return -ESHUTDOWN;
 935         }
 936
 937         /* iso is always one packet per request, that's the only way
 938          * we can report per-packet status.  that also helps with dma.
 939          */
 940         if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 941                         && req->req.length > le16_to_cpu
 942                                                 (ep->desc->wMaxPacketSize)))
 943                 return -EMSGSIZE;
 944
 945 #ifdef  USE_DMA
 946         // FIXME caller may already have done the dma mapping
 947         if (ep->dma >= 0) {
 948                 _req->dma = dma_map_single(dev->dev,
 949                         _req->buf, _req->length,
 950                         ((ep->bEndpointAddress & USB_DIR_IN) != 0)
 951                                 ? DMA_TO_DEVICE
 952                                 : DMA_FROM_DEVICE);
 953         }
 954 #endif
 955
 956         DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
 957              _ep->name, _req, _req->length, _req->buf);
 958
 959         local_irq_save(flags);
 960
 961         _req->status = -EINPROGRESS;
 962         _req->actual = 0;
 963
 964         /* kickstart this i/o queue? */
 965         if (list_empty(&ep->queue) && !ep->stopped) {
 966                 if (ep->desc == 0 /* ep0 */) {
 967                         unsigned        length = _req->length;
 968
 969                         switch (dev->ep0state) {
 970                         case EP0_IN_DATA_PHASE:
 971                                 dev->stats.write.ops++;
 972                                 if (write_ep0_fifo(ep, req))
 973                                         req = NULL;
 974                                 break;
 975
 976                         case EP0_OUT_DATA_PHASE:
 977                                 dev->stats.read.ops++;
 978                                 /* messy ... */
 979                                 if (dev->req_config) {
 980                                         DBG(DBG_VERBOSE, "ep0 config ack%s\n",
 981                                                 dev->has_cfr ?  "" : " raced");
 982                                         if (dev->has_cfr)
 983                                                 UDCCFR = UDCCFR_AREN|UDCCFR_ACM
 984                                                         |UDCCFR_MB1;
 985                                         done(ep, req, 0);
 986                                         dev->ep0state = EP0_END_XFER;
 987                                         local_irq_restore (flags);
 988                                         return 0;
 989                                 }
 990                                 if (dev->req_pending)
 991                                         ep0start(dev, UDCCS0_IPR, "OUT");
 992                                 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
 993                                                 && read_ep0_fifo(ep, req))) {
 994                                         ep0_idle(dev);
 995                                         done(ep, req, 0);
 996                                         req = NULL;
 997                                 }
 998                                 break;
 999
1000                         default:
1001                                 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
1002                                 local_irq_restore (flags);
1003                                 return -EL2HLT;
1004                         }
1005 #ifdef  USE_DMA
1006                 /* either start dma or prime pio pump */
1007                 } else if (ep->dma >= 0) {
1008                         kick_dma(ep, req);
1009 #endif
1010                 /* can the FIFO can satisfy the request immediately? */
1011                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
1012                         if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0
1013                                         && write_fifo(ep, req))
1014                                 req = NULL;
1015                 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
1016                                 && read_fifo(ep, req)) {
1017                         req = NULL;
1018                 }
1019
1020                 if (likely (req && ep->desc) && ep->dma < 0)
1021                         pio_irq_enable(ep->bEndpointAddress);
1022         }
1023
1024         /* pio or dma irq handler advances the queue. */
1025         if (likely (req != 0))
1026                 list_add_tail(&req->queue, &ep->queue);
1027         local_irq_restore(flags);
1028
1029         return 0;
1030 }
1031
1032
1033 /*
1034  *      nuke - dequeue ALL requests
1035  */
1036 static void nuke(struct pxa2xx_ep *ep, int status)
1037 {
1038         struct pxa2xx_request *req;
1039
1040         /* called with irqs blocked */
1041 #ifdef  USE_DMA
1042         if (ep->dma >= 0 && !ep->stopped)
1043                 cancel_dma(ep);
1044 #endif
1045         while (!list_empty(&ep->queue)) {
1046                 req = list_entry(ep->queue.next,
1047                                 struct pxa2xx_request,
1048                                 queue);
1049                 done(ep, req, status);
1050         }
1051         if (ep->desc)
1052                 pio_irq_disable (ep->bEndpointAddress);
1053 }
1054
1055
1056 /* dequeue JUST ONE request */
1057 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1058 {
1059         struct pxa2xx_ep        *ep;
1060         struct pxa2xx_request   *req;
1061         unsigned long           flags;
1062
1063         ep = container_of(_ep, struct pxa2xx_ep, ep);
1064         if (!_ep || ep->ep.name == ep0name)
1065                 return -EINVAL;
1066
1067         local_irq_save(flags);
1068
1069         /* make sure it's actually queued on this endpoint */
1070         list_for_each_entry (req, &ep->queue, queue) {
1071                 if (&req->req == _req)
1072                         break;
1073         }
1074         if (&req->req != _req) {
1075                 local_irq_restore(flags);
1076                 return -EINVAL;
1077         }
1078
1079 #ifdef  USE_DMA
1080         if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1081                 cancel_dma(ep);
1082                 done(ep, req, -ECONNRESET);
1083                 /* restart i/o */
1084                 if (!list_empty(&ep->queue)) {
1085                         req = list_entry(ep->queue.next,
1086                                         struct pxa2xx_request, queue);
1087                         kick_dma(ep, req);
1088                 }
1089         } else
1090 #endif
1091                 done(ep, req, -ECONNRESET);
1092
1093         local_irq_restore(flags);
1094         return 0;
1095 }
1096
1097 /*-------------------------------------------------------------------------*/
1098
1099 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
1100 {
1101         struct pxa2xx_ep        *ep;
1102         unsigned long           flags;
1103
1104         ep = container_of(_ep, struct pxa2xx_ep, ep);
1105         if (unlikely (!_ep
1106                         || (!ep->desc && ep->ep.name != ep0name))
1107                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1108                 DMSG("%s, bad ep\n", __FUNCTION__);
1109                 return -EINVAL;
1110         }
1111         if (value == 0) {
1112                 /* this path (reset toggle+halt) is needed to implement
1113                  * SET_INTERFACE on normal hardware.  but it can't be
1114                  * done from software on the PXA UDC, and the hardware
1115                  * forgets to do it as part of SET_INTERFACE automagic.
1116                  */
1117                 DMSG("only host can clear %s halt\n", _ep->name);
1118                 return -EROFS;
1119         }
1120
1121         local_irq_save(flags);
1122
1123         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1124                         && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
1125                            || !list_empty(&ep->queue))) {
1126                 local_irq_restore(flags);
1127                 return -EAGAIN;
1128         }
1129
1130         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1131         *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
1132
1133         /* ep0 needs special care */
1134         if (!ep->desc) {
1135                 start_watchdog(ep->dev);
1136                 ep->dev->req_pending = 0;
1137                 ep->dev->ep0state = EP0_STALL;
1138
1139         /* and bulk/intr endpoints like dropping stalls too */
1140         } else {
1141                 unsigned i;
1142                 for (i = 0; i < 1000; i += 20) {
1143                         if (*ep->reg_udccs & UDCCS_BI_SST)
1144                                 break;
1145                         udelay(20);
1146                 }
1147         }
1148         local_irq_restore(flags);
1149
1150         DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1151         return 0;
1152 }
1153
1154 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
1155 {
1156         struct pxa2xx_ep        *ep;
1157
1158         ep = container_of(_ep, struct pxa2xx_ep, ep);
1159         if (!_ep) {
1160                 DMSG("%s, bad ep\n", __FUNCTION__);
1161                 return -ENODEV;
1162         }
1163         /* pxa can't report unclaimed bytes from IN fifos */
1164         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1165                 return -EOPNOTSUPP;
1166         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1167                         || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
1168                 return 0;
1169         else
1170                 return (*ep->reg_ubcr & 0xfff) + 1;
1171 }
1172
1173 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
1174 {
1175         struct pxa2xx_ep        *ep;
1176
1177         ep = container_of(_ep, struct pxa2xx_ep, ep);
1178         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1179                 DMSG("%s, bad ep\n", __FUNCTION__);
1180                 return;
1181         }
1182
1183         /* toggle and halt bits stay unchanged */
1184
1185         /* for OUT, just read and discard the FIFO contents. */
1186         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1187                 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
1188                         (void) *ep->reg_uddr;
1189                 return;
1190         }
1191
1192         /* most IN status is the same, but ISO can't stall */
1193         *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1194                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1195                         ? 0 : UDCCS_BI_SST;
1196 }
1197
1198
1199 static struct usb_ep_ops pxa2xx_ep_ops = {
1200         .enable         = pxa2xx_ep_enable,
1201         .disable        = pxa2xx_ep_disable,
1202
1203         .alloc_request  = pxa2xx_ep_alloc_request,
1204         .free_request   = pxa2xx_ep_free_request,
1205
1206         .alloc_buffer   = pxa2xx_ep_alloc_buffer,
1207         .free_buffer    = pxa2xx_ep_free_buffer,
1208
1209         .queue          = pxa2xx_ep_queue,
1210         .dequeue        = pxa2xx_ep_dequeue,
1211
1212         .set_halt       = pxa2xx_ep_set_halt,
1213         .fifo_status    = pxa2xx_ep_fifo_status,
1214         .fifo_flush     = pxa2xx_ep_fifo_flush,
1215 };
1216
1217
1218 /* ---------------------------------------------------------------------------
1219  *      device-scoped parts of the api to the usb controller hardware
1220  * ---------------------------------------------------------------------------
1221  */
1222
1223 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
1224 {
1225         return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
1226 }
1227
1228 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
1229 {
1230         /* host may not have enabled remote wakeup */
1231         if ((UDCCS0 & UDCCS0_DRWF) == 0)
1232                 return -EHOSTUNREACH;
1233         udc_set_mask_UDCCR(UDCCR_RSM);
1234         return 0;
1235 }
1236
1237 static void stop_activity(struct pxa2xx_udc *, struct usb_gadget_driver *);
1238 static void udc_enable (struct pxa2xx_udc *);
1239 static void udc_disable(struct pxa2xx_udc *);
1240
1241 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1242  * in active use.
1243  */
1244 static int pullup(struct pxa2xx_udc *udc, int is_active)
1245 {
1246         is_active = is_active && udc->vbus && udc->pullup;
1247         DMSG("%s\n", is_active ? "active" : "inactive");
1248         if (is_active)
1249                 udc_enable(udc);
1250         else {
1251                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1252                         DMSG("disconnect %s\n", udc->driver
1253                                 ? udc->driver->driver.name
1254                                 : "(no driver)");
1255                         stop_activity(udc, udc->driver);
1256                 }
1257                 udc_disable(udc);
1258         }
1259         return 0;
1260 }
1261
1262 /* VBUS reporting logically comes from a transceiver */
1263 static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1264 {
1265         struct pxa2xx_udc       *udc;
1266
1267         udc = container_of(_gadget, struct pxa2xx_udc, gadget);
1268         udc->vbus = is_active = (is_active != 0);
1269         DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
1270         pullup(udc, is_active);
1271         return 0;
1272 }
1273
1274 /* drivers may have software control over D+ pullup */
1275 static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active)
1276 {
1277         struct pxa2xx_udc       *udc;
1278
1279         udc = container_of(_gadget, struct pxa2xx_udc, gadget);
1280
1281         /* not all boards support pullup control */
1282         if (!udc->mach->udc_command)
1283                 return -EOPNOTSUPP;
1284
1285         is_active = (is_active != 0);
1286         udc->pullup = is_active;
1287         pullup(udc, is_active);
1288         return 0;
1289 }
1290
1291 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1292         .get_frame      = pxa2xx_udc_get_frame,
1293         .wakeup         = pxa2xx_udc_wakeup,
1294         .vbus_session   = pxa2xx_udc_vbus_session,
1295         .pullup         = pxa2xx_udc_pullup,
1296
1297         // .vbus_draw ... boards may consume current from VBUS, up to
1298         // 100-500mA based on config.  the 500uA suspend ceiling means
1299         // that exclusively vbus-powered PXA designs violate USB specs.
1300 };
1301
1302 /*-------------------------------------------------------------------------*/
1303
1304 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1305
1306 static const char proc_node_name [] = "driver/udc";
1307
1308 static int
1309 udc_proc_read(char *page, char **start, off_t off, int count,
1310                 int *eof, void *_dev)
1311 {
1312         char                    *buf = page;
1313         struct pxa2xx_udc       *dev = _dev;
1314         char                    *next = buf;
1315         unsigned                size = count;
1316         unsigned long           flags;
1317         int                     i, t;
1318         u32                     tmp;
1319
1320         if (off != 0)
1321                 return 0;
1322
1323         local_irq_save(flags);
1324
1325         /* basic device status */
1326         t = scnprintf(next, size, DRIVER_DESC "\n"
1327                 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1328                 driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1329                 dev->driver ? dev->driver->driver.name : "(none)",
1330                 is_vbus_present() ? "full speed" : "disconnected");
1331         size -= t;
1332         next += t;
1333
1334         /* registers for device and ep0 */
1335         t = scnprintf(next, size,
1336                 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1337                 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1338         size -= t;
1339         next += t;
1340
1341         tmp = UDCCR;
1342         t = scnprintf(next, size,
1343                 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1344                 (tmp & UDCCR_REM) ? " rem" : "",
1345                 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1346                 (tmp & UDCCR_SRM) ? " srm" : "",
1347                 (tmp & UDCCR_SUSIR) ? " susir" : "",
1348                 (tmp & UDCCR_RESIR) ? " resir" : "",
1349                 (tmp & UDCCR_RSM) ? " rsm" : "",
1350                 (tmp & UDCCR_UDA) ? " uda" : "",
1351                 (tmp & UDCCR_UDE) ? " ude" : "");
1352         size -= t;
1353         next += t;
1354
1355         tmp = UDCCS0;
1356         t = scnprintf(next, size,
1357                 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1358                 (tmp & UDCCS0_SA) ? " sa" : "",
1359                 (tmp & UDCCS0_RNE) ? " rne" : "",
1360                 (tmp & UDCCS0_FST) ? " fst" : "",
1361                 (tmp & UDCCS0_SST) ? " sst" : "",
1362                 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1363                 (tmp & UDCCS0_FTF) ? " ftf" : "",
1364                 (tmp & UDCCS0_IPR) ? " ipr" : "",
1365                 (tmp & UDCCS0_OPR) ? " opr" : "");
1366         size -= t;
1367         next += t;
1368
1369         if (dev->has_cfr) {
1370                 tmp = UDCCFR;
1371                 t = scnprintf(next, size,
1372                         "udccfr %02X =%s%s\n", tmp,
1373                         (tmp & UDCCFR_AREN) ? " aren" : "",
1374                         (tmp & UDCCFR_ACM) ? " acm" : "");
1375                 size -= t;
1376                 next += t;
1377         }
1378
1379         if (!is_vbus_present() || !dev->driver)
1380                 goto done;
1381
1382         t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1383                 dev->stats.write.bytes, dev->stats.write.ops,
1384                 dev->stats.read.bytes, dev->stats.read.ops,
1385                 dev->stats.irqs);
1386         size -= t;
1387         next += t;
1388
1389         /* dump endpoint queues */
1390         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1391                 struct pxa2xx_ep        *ep = &dev->ep [i];
1392                 struct pxa2xx_request   *req;
1393                 int                     t;
1394
1395                 if (i != 0) {
1396                         const struct usb_endpoint_descriptor    *d;
1397
1398                         d = ep->desc;
1399                         if (!d)
1400                                 continue;
1401                         tmp = *dev->ep [i].reg_udccs;
1402                         t = scnprintf(next, size,
1403                                 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1404                                 ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1405                                 (ep->dma >= 0) ? "dma" : "pio", tmp,
1406                                 ep->pio_irqs, ep->dma_irqs);
1407                         /* TODO translate all five groups of udccs bits! */
1408
1409                 } else /* ep0 should only have one transfer queued */
1410                         t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1411                                 ep->pio_irqs);
1412                 if (t <= 0 || t > size)
1413                         goto done;
1414                 size -= t;
1415                 next += t;
1416
1417                 if (list_empty(&ep->queue)) {
1418                         t = scnprintf(next, size, "\t(nothing queued)\n");
1419                         if (t <= 0 || t > size)
1420                                 goto done;
1421                         size -= t;
1422                         next += t;
1423                         continue;
1424                 }
1425                 list_for_each_entry(req, &ep->queue, queue) {
1426 #ifdef  USE_DMA
1427                         if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1428                                 t = scnprintf(next, size,
1429                                         "\treq %p len %d/%d "
1430                                         "buf %p (dma%d dcmd %08x)\n",
1431                                         &req->req, req->req.actual,
1432                                         req->req.length, req->req.buf,
1433                                         ep->dma, DCMD(ep->dma)
1434                                         // low 13 bits == bytes-to-go
1435                                         );
1436                         else
1437 #endif
1438                                 t = scnprintf(next, size,
1439                                         "\treq %p len %d/%d buf %p\n",
1440                                         &req->req, req->req.actual,
1441                                         req->req.length, req->req.buf);
1442                         if (t <= 0 || t > size)
1443                                 goto done;
1444                         size -= t;
1445                         next += t;
1446                 }
1447         }
1448
1449 done:
1450         local_irq_restore(flags);
1451         *eof = 1;
1452         return count - size;
1453 }
1454
1455 #define create_proc_files() \
1456         create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1457 #define remove_proc_files() \
1458         remove_proc_entry(proc_node_name, NULL)
1459
1460 #else   /* !CONFIG_USB_GADGET_DEBUG_FILES */
1461
1462 #define create_proc_files() do {} while (0)
1463 #define remove_proc_files() do {} while (0)
1464
1465 #endif  /* CONFIG_USB_GADGET_DEBUG_FILES */
1466
1467 /* "function" sysfs attribute */
1468 static ssize_t
1469 show_function (struct device *_dev, struct device_attribute *attr, char *buf)
1470 {
1471         struct pxa2xx_udc       *dev = dev_get_drvdata (_dev);
1472
1473         if (!dev->driver
1474                         || !dev->driver->function
1475                         || strlen (dev->driver->function) > PAGE_SIZE)
1476                 return 0;
1477         return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1478 }
1479 static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1480
1481 /*-------------------------------------------------------------------------*/
1482
1483 /*
1484  *      udc_disable - disable USB device controller
1485  */
1486 static void udc_disable(struct pxa2xx_udc *dev)
1487 {
1488         /* block all irqs */
1489         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1490         UICR0 = UICR1 = 0xff;
1491         UFNRH = UFNRH_SIM;
1492
1493         /* if hardware supports it, disconnect from usb */
1494         pullup_off();
1495
1496         udc_clear_mask_UDCCR(UDCCR_UDE);
1497
1498 #ifdef  CONFIG_ARCH_PXA
1499         /* Disable clock for USB device */
1500         pxa_set_cken(CKEN11_USB, 0);
1501 #endif
1502
1503         ep0_idle (dev);
1504         dev->gadget.speed = USB_SPEED_UNKNOWN;
1505         LED_CONNECTED_OFF;
1506 }
1507
1508
1509 /*
1510  *      udc_reinit - initialize software state
1511  */
1512 static void udc_reinit(struct pxa2xx_udc *dev)
1513 {
1514         u32     i;
1515
1516         /* device/ep0 records init */
1517         INIT_LIST_HEAD (&dev->gadget.ep_list);
1518         INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1519         dev->ep0state = EP0_IDLE;
1520
1521         /* basic endpoint records init */
1522         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1523                 struct pxa2xx_ep *ep = &dev->ep[i];
1524
1525                 if (i != 0)
1526                         list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1527
1528                 ep->desc = NULL;
1529                 ep->stopped = 0;
1530                 INIT_LIST_HEAD (&ep->queue);
1531                 ep->pio_irqs = ep->dma_irqs = 0;
1532         }
1533
1534         /* the rest was statically initialized, and is read-only */
1535 }
1536
1537 /* until it's enabled, this UDC should be completely invisible
1538  * to any USB host.
1539  */
1540 static void udc_enable (struct pxa2xx_udc *dev)
1541 {
1542         udc_clear_mask_UDCCR(UDCCR_UDE);
1543
1544 #ifdef  CONFIG_ARCH_PXA
1545         /* Enable clock for USB device */
1546         pxa_set_cken(CKEN11_USB, 1);
1547         udelay(5);
1548 #endif
1549
1550         /* try to clear these bits before we enable the udc */
1551         udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1552
1553         ep0_idle(dev);
1554         dev->gadget.speed = USB_SPEED_UNKNOWN;
1555         dev->stats.irqs = 0;
1556
1557         /*
1558          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1559          * - enable UDC
1560          * - if RESET is already in progress, ack interrupt
1561          * - unmask reset interrupt
1562          */
1563         udc_set_mask_UDCCR(UDCCR_UDE);
1564         if (!(UDCCR & UDCCR_UDA))
1565                 udc_ack_int_UDCCR(UDCCR_RSTIR);
1566
1567         if (dev->has_cfr /* UDC_RES2 is defined */) {
1568                 /* pxa255 (a0+) can avoid a set_config race that could
1569                  * prevent gadget drivers from configuring correctly
1570                  */
1571                 UDCCFR = UDCCFR_ACM | UDCCFR_MB1;
1572         } else {
1573                 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1574                  * which could result in missing packets and interrupts.
1575                  * supposedly one bit per endpoint, controlling whether it
1576                  * double buffers or not; ACM/AREN bits fit into the holes.
1577                  * zero bits (like USIR0_IRx) disable double buffering.
1578                  */
1579                 UDC_RES1 = 0x00;
1580                 UDC_RES2 = 0x00;
1581         }
1582
1583 #ifdef  DISABLE_TEST_MODE
1584         /* "test mode" seems to have become the default in later chip
1585          * revs, preventing double buffering (and invalidating docs).
1586          * this EXPERIMENT enables it for bulk endpoints by tweaking
1587          * undefined/reserved register bits (that other drivers clear).
1588          * Belcarra code comments noted this usage.
1589          */
1590         if (fifo_mode & 1) {    /* IN endpoints */
1591                 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1592                 UDC_RES2 |= USIR1_IR11;
1593         }
1594         if (fifo_mode & 2) {    /* OUT endpoints */
1595                 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1596                 UDC_RES2 |= USIR1_IR12;
1597         }
1598 #endif
1599
1600         /* enable suspend/resume and reset irqs */
1601         udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1602
1603         /* enable ep0 irqs */
1604         UICR0 &= ~UICR0_IM0;
1605
1606         /* if hardware supports it, pullup D+ and wait for reset */
1607         pullup_on();
1608 }
1609
1610
1611 /* when a driver is successfully registered, it will receive
1612  * control requests including set_configuration(), which enables
1613  * non-control requests.  then usb traffic follows until a
1614  * disconnect is reported.  then a host may connect again, or
1615  * the driver might get unbound.
1616  */
1617 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1618 {
1619         struct pxa2xx_udc       *dev = the_controller;
1620         int                     retval;
1621
1622         if (!driver
1623                         || driver->speed < USB_SPEED_FULL
1624                         || !driver->bind
1625                         || !driver->disconnect
1626                         || !driver->setup)
1627                 return -EINVAL;
1628         if (!dev)
1629                 return -ENODEV;
1630         if (dev->driver)
1631                 return -EBUSY;
1632
1633         /* first hook up the driver ... */
1634         dev->driver = driver;
1635         dev->gadget.dev.driver = &driver->driver;
1636         dev->pullup = 1;
1637
1638         device_add (&dev->gadget.dev);
1639         retval = driver->bind(&dev->gadget);
1640         if (retval) {
1641                 DMSG("bind to driver %s --> error %d\n",
1642                                 driver->driver.name, retval);
1643                 device_del (&dev->gadget.dev);
1644
1645                 dev->driver = NULL;
1646                 dev->gadget.dev.driver = NULL;
1647                 return retval;
1648         }
1649         device_create_file(dev->dev, &dev_attr_function);
1650
1651         /* ... then enable host detection and ep0; and we're ready
1652          * for set_configuration as well as eventual disconnect.
1653          */
1654         DMSG("registered gadget driver '%s'\n", driver->driver.name);
1655         pullup(dev, 1);
1656         dump_state(dev);
1657         return 0;
1658 }
1659 EXPORT_SYMBOL(usb_gadget_register_driver);
1660
1661 static void
1662 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1663 {
1664         int i;
1665
1666         /* don't disconnect drivers more than once */
1667         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1668                 driver = NULL;
1669         dev->gadget.speed = USB_SPEED_UNKNOWN;
1670
1671         /* prevent new request submissions, kill any outstanding requests  */
1672         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1673                 struct pxa2xx_ep *ep = &dev->ep[i];
1674
1675                 ep->stopped = 1;
1676                 nuke(ep, -ESHUTDOWN);
1677         }
1678         del_timer_sync(&dev->timer);
1679
1680         /* report disconnect; the driver is already quiesced */
1681         LED_CONNECTED_OFF;
1682         if (driver)
1683                 driver->disconnect(&dev->gadget);
1684
1685         /* re-init driver-visible data structures */
1686         udc_reinit(dev);
1687 }
1688
1689 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1690 {
1691         struct pxa2xx_udc       *dev = the_controller;
1692
1693         if (!dev)
1694                 return -ENODEV;
1695         if (!driver || driver != dev->driver || !driver->unbind)
1696                 return -EINVAL;
1697
1698         local_irq_disable();
1699         pullup(dev, 0);
1700         stop_activity(dev, driver);
1701         local_irq_enable();
1702
1703         driver->unbind(&dev->gadget);
1704         dev->driver = NULL;
1705
1706         device_del (&dev->gadget.dev);
1707         device_remove_file(dev->dev, &dev_attr_function);
1708
1709         DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1710         dump_state(dev);
1711         return 0;
1712 }
1713 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1714
1715
1716 /*-------------------------------------------------------------------------*/
1717
1718 #ifdef CONFIG_ARCH_LUBBOCK
1719
1720 /* Lubbock has separate connect and disconnect irqs.  More typical designs
1721  * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1722  */
1723
1724 static irqreturn_t
1725 lubbock_vbus_irq(int irq, void *_dev)
1726 {
1727         struct pxa2xx_udc       *dev = _dev;
1728         int                     vbus;
1729
1730         dev->stats.irqs++;
1731         HEX_DISPLAY(dev->stats.irqs);
1732         switch (irq) {
1733         case LUBBOCK_USB_IRQ:
1734                 LED_CONNECTED_ON;
1735                 vbus = 1;
1736                 disable_irq(LUBBOCK_USB_IRQ);
1737                 enable_irq(LUBBOCK_USB_DISC_IRQ);
1738                 break;
1739         case LUBBOCK_USB_DISC_IRQ:
1740                 LED_CONNECTED_OFF;
1741                 vbus = 0;
1742                 disable_irq(LUBBOCK_USB_DISC_IRQ);
1743                 enable_irq(LUBBOCK_USB_IRQ);
1744                 break;
1745         default:
1746                 return IRQ_NONE;
1747         }
1748
1749         pxa2xx_udc_vbus_session(&dev->gadget, vbus);
1750         return IRQ_HANDLED;
1751 }
1752
1753 #endif
1754
1755 static irqreturn_t udc_vbus_irq(int irq, void *_dev)
1756 {
1757         struct pxa2xx_udc       *dev = _dev;
1758         int                     vbus = udc_gpio_get(dev->mach->gpio_vbus);
1759
1760         pxa2xx_udc_vbus_session(&dev->gadget, vbus);
1761         return IRQ_HANDLED;
1762 }
1763
1764
1765 /*-------------------------------------------------------------------------*/
1766
1767 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1768 {
1769         unsigned i;
1770
1771         /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1772          * fifos, and pending transactions mustn't be continued in any case.
1773          */
1774         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1775                 nuke(&dev->ep[i], -ECONNABORTED);
1776 }
1777
1778 static void udc_watchdog(unsigned long _dev)
1779 {
1780         struct pxa2xx_udc       *dev = (void *)_dev;
1781
1782         local_irq_disable();
1783         if (dev->ep0state == EP0_STALL
1784                         && (UDCCS0 & UDCCS0_FST) == 0
1785                         && (UDCCS0 & UDCCS0_SST) == 0) {
1786                 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1787                 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1788                 start_watchdog(dev);
1789         }
1790         local_irq_enable();
1791 }
1792
1793 static void handle_ep0 (struct pxa2xx_udc *dev)
1794 {
1795         u32                     udccs0 = UDCCS0;
1796         struct pxa2xx_ep        *ep = &dev->ep [0];
1797         struct pxa2xx_request   *req;
1798         union {
1799                 struct usb_ctrlrequest  r;
1800                 u8                      raw [8];
1801                 u32                     word [2];
1802         } u;
1803
1804         if (list_empty(&ep->queue))
1805                 req = NULL;
1806         else
1807                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1808
1809         /* clear stall status */
1810         if (udccs0 & UDCCS0_SST) {
1811                 nuke(ep, -EPIPE);
1812                 UDCCS0 = UDCCS0_SST;
1813                 del_timer(&dev->timer);
1814                 ep0_idle(dev);
1815         }
1816
1817         /* previous request unfinished?  non-error iff back-to-back ... */
1818         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1819                 nuke(ep, 0);
1820                 del_timer(&dev->timer);
1821                 ep0_idle(dev);
1822         }
1823
1824         switch (dev->ep0state) {
1825         case EP0_IDLE:
1826                 /* late-breaking status? */
1827                 udccs0 = UDCCS0;
1828
1829                 /* start control request? */
1830                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1831                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1832                         int i;
1833
1834                         nuke (ep, -EPROTO);
1835
1836                         /* read SETUP packet */
1837                         for (i = 0; i < 8; i++) {
1838                                 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1839 bad_setup:
1840                                         DMSG("SETUP %d!\n", i);
1841                                         goto stall;
1842                                 }
1843                                 u.raw [i] = (u8) UDDR0;
1844                         }
1845                         if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1846                                 goto bad_setup;
1847
1848 got_setup:
1849                         DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1850                                 u.r.bRequestType, u.r.bRequest,
1851                                 le16_to_cpu(u.r.wValue),
1852                                 le16_to_cpu(u.r.wIndex),
1853                                 le16_to_cpu(u.r.wLength));
1854
1855                         /* cope with automagic for some standard requests. */
1856                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1857                                                 == USB_TYPE_STANDARD;
1858                         dev->req_config = 0;
1859                         dev->req_pending = 1;
1860                         switch (u.r.bRequest) {
1861                         /* hardware restricts gadget drivers here! */
1862                         case USB_REQ_SET_CONFIGURATION:
1863                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1864                                         /* reflect hardware's automagic
1865                                          * up to the gadget driver.
1866                                          */
1867 config_change:
1868                                         dev->req_config = 1;
1869                                         clear_ep_state(dev);
1870                                         /* if !has_cfr, there's no synch
1871                                          * else use AREN (later) not SA|OPR
1872                                          * USIR0_IR0 acts edge sensitive
1873                                          */
1874                                 }
1875                                 break;
1876                         /* ... and here, even more ... */
1877                         case USB_REQ_SET_INTERFACE:
1878                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1879                                         /* udc hardware is broken by design:
1880                                          *  - altsetting may only be zero;
1881                                          *  - hw resets all interfaces' eps;
1882                                          *  - ep reset doesn't include halt(?).
1883                                          */
1884                                         DMSG("broken set_interface (%d/%d)\n",
1885                                                 le16_to_cpu(u.r.wIndex),
1886                                                 le16_to_cpu(u.r.wValue));
1887                                         goto config_change;
1888                                 }
1889                                 break;
1890                         /* hardware was supposed to hide this */
1891                         case USB_REQ_SET_ADDRESS:
1892                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1893                                         ep0start(dev, 0, "address");
1894                                         return;
1895                                 }
1896                                 break;
1897                         }
1898
1899                         if (u.r.bRequestType & USB_DIR_IN)
1900                                 dev->ep0state = EP0_IN_DATA_PHASE;
1901                         else
1902                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1903
1904                         i = dev->driver->setup(&dev->gadget, &u.r);
1905                         if (i < 0) {
1906                                 /* hardware automagic preventing STALL... */
1907                                 if (dev->req_config) {
1908                                         /* hardware sometimes neglects to tell
1909                                          * tell us about config change events,
1910                                          * so later ones may fail...
1911                                          */
1912                                         WARN("config change %02x fail %d?\n",
1913                                                 u.r.bRequest, i);
1914                                         return;
1915                                         /* TODO experiment:  if has_cfr,
1916                                          * hardware didn't ACK; maybe we
1917                                          * could actually STALL!
1918                                          */
1919                                 }
1920                                 DBG(DBG_VERBOSE, "protocol STALL, "
1921                                         "%02x err %d\n", UDCCS0, i);
1922 stall:
1923                                 /* the watchdog timer helps deal with cases
1924                                  * where udc seems to clear FST wrongly, and
1925                                  * then NAKs instead of STALLing.
1926                                  */
1927                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1928                                 start_watchdog(dev);
1929                                 dev->ep0state = EP0_STALL;
1930
1931                         /* deferred i/o == no response yet */
1932                         } else if (dev->req_pending) {
1933                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1934                                                 || dev->req_std || u.r.wLength))
1935                                         ep0start(dev, 0, "defer");
1936                                 else
1937                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1938                         }
1939
1940                         /* expect at least one data or status stage irq */
1941                         return;
1942
1943                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1944                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1945                         unsigned i;
1946
1947                         /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1948                          * still observed on a pxa255 a0.
1949                          */
1950                         DBG(DBG_VERBOSE, "e131\n");
1951                         nuke(ep, -EPROTO);
1952
1953                         /* read SETUP data, but don't trust it too much */
1954                         for (i = 0; i < 8; i++)
1955                                 u.raw [i] = (u8) UDDR0;
1956                         if ((u.r.bRequestType & USB_RECIP_MASK)
1957                                         > USB_RECIP_OTHER)
1958                                 goto stall;
1959                         if (u.word [0] == 0 && u.word [1] == 0)
1960                                 goto stall;
1961                         goto got_setup;
1962                 } else {
1963                         /* some random early IRQ:
1964                          * - we acked FST
1965                          * - IPR cleared
1966                          * - OPR got set, without SA (likely status stage)
1967                          */
1968                         UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1969                 }
1970                 break;
1971         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1972                 if (udccs0 & UDCCS0_OPR) {
1973                         UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1974                         DBG(DBG_VERBOSE, "ep0in premature status\n");
1975                         if (req)
1976                                 done(ep, req, 0);
1977                         ep0_idle(dev);
1978                 } else /* irq was IPR clearing */ {
1979                         if (req) {
1980                                 /* this IN packet might finish the request */
1981                                 (void) write_ep0_fifo(ep, req);
1982                         } /* else IN token before response was written */
1983                 }
1984                 break;
1985         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1986                 if (udccs0 & UDCCS0_OPR) {
1987                         if (req) {
1988                                 /* this OUT packet might finish the request */
1989                                 if (read_ep0_fifo(ep, req))
1990                                         done(ep, req, 0);
1991                                 /* else more OUT packets expected */
1992                         } /* else OUT token before read was issued */
1993                 } else /* irq was IPR clearing */ {
1994                         DBG(DBG_VERBOSE, "ep0out premature status\n");
1995                         if (req)
1996                                 done(ep, req, 0);
1997                         ep0_idle(dev);
1998                 }
1999                 break;
2000         case EP0_END_XFER:
2001                 if (req)
2002                         done(ep, req, 0);
2003                 /* ack control-IN status (maybe in-zlp was skipped)
2004                  * also appears after some config change events.
2005                  */
2006                 if (udccs0 & UDCCS0_OPR)
2007                         UDCCS0 = UDCCS0_OPR;
2008                 ep0_idle(dev);
2009                 break;
2010         case EP0_STALL:
2011                 UDCCS0 = UDCCS0_FST;
2012                 break;
2013         }
2014         USIR0 = USIR0_IR0;
2015 }
2016
2017 static void handle_ep(struct pxa2xx_ep *ep)
2018 {
2019         struct pxa2xx_request   *req;
2020         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
2021         int                     completed;
2022         u32                     udccs, tmp;
2023
2024         do {
2025                 completed = 0;
2026                 if (likely (!list_empty(&ep->queue)))
2027                         req = list_entry(ep->queue.next,
2028                                         struct pxa2xx_request, queue);
2029                 else
2030                         req = NULL;
2031
2032                 // TODO check FST handling
2033
2034                 udccs = *ep->reg_udccs;
2035                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
2036                         tmp = UDCCS_BI_TUR;
2037                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
2038                                 tmp |= UDCCS_BI_SST;
2039                         tmp &= udccs;
2040                         if (likely (tmp))
2041                                 *ep->reg_udccs = tmp;
2042                         if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
2043                                 completed = write_fifo(ep, req);
2044
2045                 } else {        /* irq from RPC (or for ISO, ROF) */
2046                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
2047                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
2048                         else
2049                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
2050                         tmp &= udccs;
2051                         if (likely(tmp))
2052                                 *ep->reg_udccs = tmp;
2053
2054                         /* fifos can hold packets, ready for reading... */
2055                         if (likely(req)) {
2056 #ifdef USE_OUT_DMA
2057 // TODO didn't yet debug out-dma.  this approach assumes
2058 // the worst about short packets and RPC; it might be better.
2059
2060                                 if (likely(ep->dma >= 0)) {
2061                                         if (!(udccs & UDCCS_BO_RSP)) {
2062                                                 *ep->reg_udccs = UDCCS_BO_RPC;
2063                                                 ep->dma_irqs++;
2064                                                 return;
2065                                         }
2066                                 }
2067 #endif
2068                                 completed = read_fifo(ep, req);
2069                         } else
2070                                 pio_irq_disable (ep->bEndpointAddress);
2071                 }
2072                 ep->pio_irqs++;
2073         } while (completed);
2074 }
2075
2076 /*
2077  *      pxa2xx_udc_irq - interrupt handler
2078  *
2079  * avoid delays in ep0 processing. the control handshaking isn't always
2080  * under software control (pxa250c0 and the pxa255 are better), and delays
2081  * could cause usb protocol errors.
2082  */
2083 static irqreturn_t
2084 pxa2xx_udc_irq(int irq, void *_dev)
2085 {
2086         struct pxa2xx_udc       *dev = _dev;
2087         int                     handled;
2088
2089         dev->stats.irqs++;
2090         HEX_DISPLAY(dev->stats.irqs);
2091         do {
2092                 u32             udccr = UDCCR;
2093
2094                 handled = 0;
2095
2096                 /* SUSpend Interrupt Request */
2097                 if (unlikely(udccr & UDCCR_SUSIR)) {
2098                         udc_ack_int_UDCCR(UDCCR_SUSIR);
2099                         handled = 1;
2100                         DBG(DBG_VERBOSE, "USB suspend%s\n", is_vbus_present()
2101                                 ? "" : "+disconnect");
2102
2103                         if (!is_vbus_present())
2104                                 stop_activity(dev, dev->driver);
2105                         else if (dev->gadget.speed != USB_SPEED_UNKNOWN
2106                                         && dev->driver
2107                                         && dev->driver->suspend)
2108                                 dev->driver->suspend(&dev->gadget);
2109                         ep0_idle (dev);
2110                 }
2111
2112                 /* RESume Interrupt Request */
2113                 if (unlikely(udccr & UDCCR_RESIR)) {
2114                         udc_ack_int_UDCCR(UDCCR_RESIR);
2115                         handled = 1;
2116                         DBG(DBG_VERBOSE, "USB resume\n");
2117
2118                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
2119                                         && dev->driver
2120                                         && dev->driver->resume
2121                                         && is_vbus_present())
2122                                 dev->driver->resume(&dev->gadget);
2123                 }
2124
2125                 /* ReSeT Interrupt Request - USB reset */
2126                 if (unlikely(udccr & UDCCR_RSTIR)) {
2127                         udc_ack_int_UDCCR(UDCCR_RSTIR);
2128                         handled = 1;
2129
2130                         if ((UDCCR & UDCCR_UDA) == 0) {
2131                                 DBG(DBG_VERBOSE, "USB reset start\n");
2132
2133                                 /* reset driver and endpoints,
2134                                  * in case that's not yet done
2135                                  */
2136                                 stop_activity (dev, dev->driver);
2137
2138                         } else {
2139                                 DBG(DBG_VERBOSE, "USB reset end\n");
2140                                 dev->gadget.speed = USB_SPEED_FULL;
2141                                 LED_CONNECTED_ON;
2142                                 memset(&dev->stats, 0, sizeof dev->stats);
2143                                 /* driver and endpoints are still reset */
2144                         }
2145
2146                 } else {
2147                         u32     usir0 = USIR0 & ~UICR0;
2148                         u32     usir1 = USIR1 & ~UICR1;
2149                         int     i;
2150
2151                         if (unlikely (!usir0 && !usir1))
2152                                 continue;
2153
2154                         DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
2155
2156                         /* control traffic */
2157                         if (usir0 & USIR0_IR0) {
2158                                 dev->ep[0].pio_irqs++;
2159                                 handle_ep0(dev);
2160                                 handled = 1;
2161                         }
2162
2163                         /* endpoint data transfers */
2164                         for (i = 0; i < 8; i++) {
2165                                 u32     tmp = 1 << i;
2166
2167                                 if (i && (usir0 & tmp)) {
2168                                         handle_ep(&dev->ep[i]);
2169                                         USIR0 |= tmp;
2170                                         handled = 1;
2171                                 }
2172                                 if (usir1 & tmp) {
2173                                         handle_ep(&dev->ep[i+8]);
2174                                         USIR1 |= tmp;
2175                                         handled = 1;
2176                                 }
2177                         }
2178                 }
2179
2180                 /* we could also ask for 1 msec SOF (SIR) interrupts */
2181
2182         } while (handled);
2183         return IRQ_HANDLED;
2184 }
2185
2186 /*-------------------------------------------------------------------------*/
2187
2188 static void nop_release (struct device *dev)
2189 {
2190         DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2191 }
2192
2193 /* this uses load-time allocation and initialization (instead of
2194  * doing it at run-time) to save code, eliminate fault paths, and
2195  * be more obviously correct.
2196  */
2197 static struct pxa2xx_udc memory = {
2198         .gadget = {
2199                 .ops            = &pxa2xx_udc_ops,
2200                 .ep0            = &memory.ep[0].ep,
2201                 .name           = driver_name,
2202                 .dev = {
2203                         .bus_id         = "gadget",
2204                         .release        = nop_release,
2205                 },
2206         },
2207
2208         /* control endpoint */
2209         .ep[0] = {
2210                 .ep = {
2211                         .name           = ep0name,
2212                         .ops            = &pxa2xx_ep_ops,
2213                         .maxpacket      = EP0_FIFO_SIZE,
2214                 },
2215                 .dev            = &memory,
2216                 .reg_udccs      = &UDCCS0,
2217                 .reg_uddr       = &UDDR0,
2218         },
2219
2220         /* first group of endpoints */
2221         .ep[1] = {
2222                 .ep = {
2223                         .name           = "ep1in-bulk",
2224                         .ops            = &pxa2xx_ep_ops,
2225                         .maxpacket      = BULK_FIFO_SIZE,
2226                 },
2227                 .dev            = &memory,
2228                 .fifo_size      = BULK_FIFO_SIZE,
2229                 .bEndpointAddress = USB_DIR_IN | 1,
2230                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2231                 .reg_udccs      = &UDCCS1,
2232                 .reg_uddr       = &UDDR1,
2233                 drcmr (25)
2234         },
2235         .ep[2] = {
2236                 .ep = {
2237                         .name           = "ep2out-bulk",
2238                         .ops            = &pxa2xx_ep_ops,
2239                         .maxpacket      = BULK_FIFO_SIZE,
2240                 },
2241                 .dev            = &memory,
2242                 .fifo_size      = BULK_FIFO_SIZE,
2243                 .bEndpointAddress = 2,
2244                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2245                 .reg_udccs      = &UDCCS2,
2246                 .reg_ubcr       = &UBCR2,
2247                 .reg_uddr       = &UDDR2,
2248                 drcmr (26)
2249         },
2250 #ifndef CONFIG_USB_PXA2XX_SMALL
2251         .ep[3] = {
2252                 .ep = {
2253                         .name           = "ep3in-iso",
2254                         .ops            = &pxa2xx_ep_ops,
2255                         .maxpacket      = ISO_FIFO_SIZE,
2256                 },
2257                 .dev            = &memory,
2258                 .fifo_size      = ISO_FIFO_SIZE,
2259                 .bEndpointAddress = USB_DIR_IN | 3,
2260                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2261                 .reg_udccs      = &UDCCS3,
2262                 .reg_uddr       = &UDDR3,
2263                 drcmr (27)
2264         },
2265         .ep[4] = {
2266                 .ep = {
2267                         .name           = "ep4out-iso",
2268                         .ops            = &pxa2xx_ep_ops,
2269                         .maxpacket      = ISO_FIFO_SIZE,
2270                 },
2271                 .dev            = &memory,
2272                 .fifo_size      = ISO_FIFO_SIZE,
2273                 .bEndpointAddress = 4,
2274                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2275                 .reg_udccs      = &UDCCS4,
2276                 .reg_ubcr       = &UBCR4,
2277                 .reg_uddr       = &UDDR4,
2278                 drcmr (28)
2279         },
2280         .ep[5] = {
2281                 .ep = {
2282                         .name           = "ep5in-int",
2283                         .ops            = &pxa2xx_ep_ops,
2284                         .maxpacket      = INT_FIFO_SIZE,
2285                 },
2286                 .dev            = &memory,
2287                 .fifo_size      = INT_FIFO_SIZE,
2288                 .bEndpointAddress = USB_DIR_IN | 5,
2289                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2290                 .reg_udccs      = &UDCCS5,
2291                 .reg_uddr       = &UDDR5,
2292         },
2293
2294         /* second group of endpoints */
2295         .ep[6] = {
2296                 .ep = {
2297                         .name           = "ep6in-bulk",
2298                         .ops            = &pxa2xx_ep_ops,
2299                         .maxpacket      = BULK_FIFO_SIZE,
2300                 },
2301                 .dev            = &memory,
2302                 .fifo_size      = BULK_FIFO_SIZE,
2303                 .bEndpointAddress = USB_DIR_IN | 6,
2304                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2305                 .reg_udccs      = &UDCCS6,
2306                 .reg_uddr       = &UDDR6,
2307                 drcmr (30)
2308         },
2309         .ep[7] = {
2310                 .ep = {
2311                         .name           = "ep7out-bulk",
2312                         .ops            = &pxa2xx_ep_ops,
2313                         .maxpacket      = BULK_FIFO_SIZE,
2314                 },
2315                 .dev            = &memory,
2316                 .fifo_size      = BULK_FIFO_SIZE,
2317                 .bEndpointAddress = 7,
2318                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2319                 .reg_udccs      = &UDCCS7,
2320                 .reg_ubcr       = &UBCR7,
2321                 .reg_uddr       = &UDDR7,
2322                 drcmr (31)
2323         },
2324         .ep[8] = {
2325                 .ep = {
2326                         .name           = "ep8in-iso",
2327                         .ops            = &pxa2xx_ep_ops,
2328                         .maxpacket      = ISO_FIFO_SIZE,
2329                 },
2330                 .dev            = &memory,
2331                 .fifo_size      = ISO_FIFO_SIZE,
2332                 .bEndpointAddress = USB_DIR_IN | 8,
2333                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2334                 .reg_udccs      = &UDCCS8,
2335                 .reg_uddr       = &UDDR8,
2336                 drcmr (32)
2337         },
2338         .ep[9] = {
2339                 .ep = {
2340                         .name           = "ep9out-iso",
2341                         .ops            = &pxa2xx_ep_ops,
2342                         .maxpacket      = ISO_FIFO_SIZE,
2343                 },
2344                 .dev            = &memory,
2345                 .fifo_size      = ISO_FIFO_SIZE,
2346                 .bEndpointAddress = 9,
2347                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2348                 .reg_udccs      = &UDCCS9,
2349                 .reg_ubcr       = &UBCR9,
2350                 .reg_uddr       = &UDDR9,
2351                 drcmr (33)
2352         },
2353         .ep[10] = {
2354                 .ep = {
2355                         .name           = "ep10in-int",
2356                         .ops            = &pxa2xx_ep_ops,
2357                         .maxpacket      = INT_FIFO_SIZE,
2358                 },
2359                 .dev            = &memory,
2360                 .fifo_size      = INT_FIFO_SIZE,
2361                 .bEndpointAddress = USB_DIR_IN | 10,
2362                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2363                 .reg_udccs      = &UDCCS10,
2364                 .reg_uddr       = &UDDR10,
2365         },
2366
2367         /* third group of endpoints */
2368         .ep[11] = {
2369                 .ep = {
2370                         .name           = "ep11in-bulk",
2371                         .ops            = &pxa2xx_ep_ops,
2372                         .maxpacket      = BULK_FIFO_SIZE,
2373                 },
2374                 .dev            = &memory,
2375                 .fifo_size      = BULK_FIFO_SIZE,
2376                 .bEndpointAddress = USB_DIR_IN | 11,
2377                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2378                 .reg_udccs      = &UDCCS11,
2379                 .reg_uddr       = &UDDR11,
2380                 drcmr (35)
2381         },
2382         .ep[12] = {
2383                 .ep = {
2384                         .name           = "ep12out-bulk",
2385                         .ops            = &pxa2xx_ep_ops,
2386                         .maxpacket      = BULK_FIFO_SIZE,
2387                 },
2388                 .dev            = &memory,
2389                 .fifo_size      = BULK_FIFO_SIZE,
2390                 .bEndpointAddress = 12,
2391                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2392                 .reg_udccs      = &UDCCS12,
2393                 .reg_ubcr       = &UBCR12,
2394                 .reg_uddr       = &UDDR12,
2395                 drcmr (36)
2396         },
2397         .ep[13] = {
2398                 .ep = {
2399                         .name           = "ep13in-iso",
2400                         .ops            = &pxa2xx_ep_ops,
2401                         .maxpacket      = ISO_FIFO_SIZE,
2402                 },
2403                 .dev            = &memory,
2404                 .fifo_size      = ISO_FIFO_SIZE,
2405                 .bEndpointAddress = USB_DIR_IN | 13,
2406                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2407                 .reg_udccs      = &UDCCS13,
2408                 .reg_uddr       = &UDDR13,
2409                 drcmr (37)
2410         },
2411         .ep[14] = {
2412                 .ep = {
2413                         .name           = "ep14out-iso",
2414                         .ops            = &pxa2xx_ep_ops,
2415                         .maxpacket      = ISO_FIFO_SIZE,
2416                 },
2417                 .dev            = &memory,
2418                 .fifo_size      = ISO_FIFO_SIZE,
2419                 .bEndpointAddress = 14,
2420                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2421                 .reg_udccs      = &UDCCS14,
2422                 .reg_ubcr       = &UBCR14,
2423                 .reg_uddr       = &UDDR14,
2424                 drcmr (38)
2425         },
2426         .ep[15] = {
2427                 .ep = {
2428                         .name           = "ep15in-int",
2429                         .ops            = &pxa2xx_ep_ops,
2430                         .maxpacket      = INT_FIFO_SIZE,
2431                 },
2432                 .dev            = &memory,
2433                 .fifo_size      = INT_FIFO_SIZE,
2434                 .bEndpointAddress = USB_DIR_IN | 15,
2435                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2436                 .reg_udccs      = &UDCCS15,
2437                 .reg_uddr       = &UDDR15,
2438         },
2439 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2440 };
2441
2442 #define CP15R0_VENDOR_MASK      0xffffe000
2443
2444 #if     defined(CONFIG_ARCH_PXA)
2445 #define CP15R0_XSCALE_VALUE     0x69052000      /* intel/arm/xscale */
2446
2447 #elif   defined(CONFIG_ARCH_IXP4XX)
2448 #define CP15R0_XSCALE_VALUE     0x69054000      /* intel/arm/ixp4xx */
2449
2450 #endif
2451
2452 #define CP15R0_PROD_MASK        0x000003f0
2453 #define PXA25x                  0x00000100      /* and PXA26x */
2454 #define PXA210                  0x00000120
2455
2456 #define CP15R0_REV_MASK         0x0000000f
2457
2458 #define CP15R0_PRODREV_MASK     (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2459
2460 #define PXA255_A0               0x00000106      /* or PXA260_B1 */
2461 #define PXA250_C0               0x00000105      /* or PXA26x_B0 */
2462 #define PXA250_B2               0x00000104
2463 #define PXA250_B1               0x00000103      /* or PXA260_A0 */
2464 #define PXA250_B0               0x00000102
2465 #define PXA250_A1               0x00000101
2466 #define PXA250_A0               0x00000100
2467
2468 #define PXA210_C0               0x00000125
2469 #define PXA210_B2               0x00000124
2470 #define PXA210_B1               0x00000123
2471 #define PXA210_B0               0x00000122
2472 #define IXP425_A0               0x000001c1
2473 #define IXP425_B0               0x000001f1
2474 #define IXP465_AD               0x00000200
2475
2476 /*
2477  *      probe - binds to the platform device
2478  */
2479 static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2480 {
2481         struct pxa2xx_udc *dev = &memory;
2482         int retval, out_dma = 1, vbus_irq;
2483         u32 chiprev;
2484
2485         /* insist on Intel/ARM/XScale */
2486         asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2487         if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2488                 printk(KERN_ERR "%s: not XScale!\n", driver_name);
2489                 return -ENODEV;
2490         }
2491
2492         /* trigger chiprev-specific logic */
2493         switch (chiprev & CP15R0_PRODREV_MASK) {
2494 #if     defined(CONFIG_ARCH_PXA)
2495         case PXA255_A0:
2496                 dev->has_cfr = 1;
2497                 break;
2498         case PXA250_A0:
2499         case PXA250_A1:
2500                 /* A0/A1 "not released"; ep 13, 15 unusable */
2501                 /* fall through */
2502         case PXA250_B2: case PXA210_B2:
2503         case PXA250_B1: case PXA210_B1:
2504         case PXA250_B0: case PXA210_B0:
2505                 out_dma = 0;
2506                 /* fall through */
2507         case PXA250_C0: case PXA210_C0:
2508                 break;
2509 #elif   defined(CONFIG_ARCH_IXP4XX)
2510         case IXP425_A0:
2511         case IXP425_B0:
2512         case IXP465_AD:
2513                 dev->has_cfr = 1;
2514                 out_dma = 0;
2515                 break;
2516 #endif
2517         default:
2518                 out_dma = 0;
2519                 printk(KERN_ERR "%s: unrecognized processor: %08x\n",
2520                         driver_name, chiprev);
2521                 /* iop3xx, ixp4xx, ... */
2522                 return -ENODEV;
2523         }
2524
2525         pr_debug("%s: IRQ %d%s%s%s\n", driver_name, IRQ_USB,
2526                 dev->has_cfr ? "" : " (!cfr)",
2527                 out_dma ? "" : " (broken dma-out)",
2528                 SIZE_STR DMASTR
2529                 );
2530
2531 #ifdef  USE_DMA
2532 #ifndef USE_OUT_DMA
2533         out_dma = 0;
2534 #endif
2535         /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2536         if (!out_dma) {
2537                 DMSG("disabled OUT dma\n");
2538                 dev->ep[ 2].reg_drcmr = dev->ep[ 4].reg_drcmr = 0;
2539                 dev->ep[ 7].reg_drcmr = dev->ep[ 9].reg_drcmr = 0;
2540                 dev->ep[12].reg_drcmr = dev->ep[14].reg_drcmr = 0;
2541         }
2542 #endif
2543
2544         /* other non-static parts of init */
2545         dev->dev = &pdev->dev;
2546         dev->mach = pdev->dev.platform_data;
2547         if (dev->mach->gpio_vbus) {
2548                 udc_gpio_init_vbus(dev->mach->gpio_vbus);
2549                 vbus_irq = udc_gpio_to_irq(dev->mach->gpio_vbus);
2550                 set_irq_type(vbus_irq, IRQT_BOTHEDGE);
2551         } else
2552                 vbus_irq = 0;
2553         if (dev->mach->gpio_pullup)
2554                 udc_gpio_init_pullup(dev->mach->gpio_pullup);
2555
2556         init_timer(&dev->timer);
2557         dev->timer.function = udc_watchdog;
2558         dev->timer.data = (unsigned long) dev;
2559
2560         device_initialize(&dev->gadget.dev);
2561         dev->gadget.dev.parent = &pdev->dev;
2562         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2563
2564         the_controller = dev;
2565         platform_set_drvdata(pdev, dev);
2566
2567         udc_disable(dev);
2568         udc_reinit(dev);
2569
2570         dev->vbus = is_vbus_present();
2571
2572         /* irq setup after old hardware state is cleaned up */
2573         retval = request_irq(IRQ_USB, pxa2xx_udc_irq,
2574                         IRQF_DISABLED, driver_name, dev);
2575         if (retval != 0) {
2576                 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2577                         driver_name, IRQ_USB, retval);
2578                 return -EBUSY;
2579         }
2580         dev->got_irq = 1;
2581
2582 #ifdef CONFIG_ARCH_LUBBOCK
2583         if (machine_is_lubbock()) {
2584                 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2585                                 lubbock_vbus_irq,
2586                                 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2587                                 driver_name, dev);
2588                 if (retval != 0) {
2589                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2590                                 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2591 lubbock_fail0:
2592                         free_irq(IRQ_USB, dev);
2593                         return -EBUSY;
2594                 }
2595                 retval = request_irq(LUBBOCK_USB_IRQ,
2596                                 lubbock_vbus_irq,
2597                                 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2598                                 driver_name, dev);
2599                 if (retval != 0) {
2600                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2601                                 driver_name, LUBBOCK_USB_IRQ, retval);
2602                         free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2603                         goto lubbock_fail0;
2604                 }
2605 #ifdef DEBUG
2606                 /* with U-Boot (but not BLOB), hex is off by default */
2607                 HEX_DISPLAY(dev->stats.irqs);
2608                 LUB_DISC_BLNK_LED &= 0xff;
2609 #endif
2610         } else
2611 #endif
2612         if (vbus_irq) {
2613                 retval = request_irq(vbus_irq, udc_vbus_irq,
2614                                 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2615                                 driver_name, dev);
2616                 if (retval != 0) {
2617                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2618                                 driver_name, vbus_irq, retval);
2619                         free_irq(IRQ_USB, dev);
2620                         return -EBUSY;
2621                 }
2622         }
2623         create_proc_files();
2624
2625         return 0;
2626 }
2627
2628 static void pxa2xx_udc_shutdown(struct platform_device *_dev)
2629 {
2630         pullup_off();
2631 }
2632
2633 static int __exit pxa2xx_udc_remove(struct platform_device *pdev)
2634 {
2635         struct pxa2xx_udc *dev = platform_get_drvdata(pdev);
2636
2637         if (dev->driver)
2638                 return -EBUSY;
2639
2640         udc_disable(dev);
2641         remove_proc_files();
2642
2643         if (dev->got_irq) {
2644                 free_irq(IRQ_USB, dev);
2645                 dev->got_irq = 0;
2646         }
2647 #ifdef CONFIG_ARCH_LUBBOCK
2648         if (machine_is_lubbock()) {
2649                 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2650                 free_irq(LUBBOCK_USB_IRQ, dev);
2651         }
2652 #endif
2653         if (dev->mach->gpio_vbus)
2654                 free_irq(IRQ_GPIO(dev->mach->gpio_vbus), dev);
2655         platform_set_drvdata(pdev, NULL);
2656         the_controller = NULL;
2657         return 0;
2658 }
2659
2660 /*-------------------------------------------------------------------------*/
2661
2662 #ifdef  CONFIG_PM
2663
2664 /* USB suspend (controlled by the host) and system suspend (controlled
2665  * by the PXA) don't necessarily work well together.  If USB is active,
2666  * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2667  * mode, or any deeper PM saving state.
2668  *
2669  * For now, we punt and forcibly disconnect from the USB host when PXA
2670  * enters any suspend state.  While we're disconnected, we always disable
2671  * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2672  * Boards without software pullup control shouldn't use those states.
2673  * VBUS IRQs should probably be ignored so that the PXA device just acts
2674  * "dead" to USB hosts until system resume.
2675  */
2676 static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state)
2677 {
2678         struct pxa2xx_udc       *udc = platform_get_drvdata(dev);
2679
2680         if (!udc->mach->udc_command)
2681                 WARN("USB host won't detect disconnect!\n");
2682         pullup(udc, 0);
2683
2684         return 0;
2685 }
2686
2687 static int pxa2xx_udc_resume(struct platform_device *dev)
2688 {
2689         struct pxa2xx_udc       *udc = platform_get_drvdata(dev);
2690
2691         pullup(udc, 1);
2692
2693         return 0;
2694 }
2695
2696 #else
2697 #define pxa2xx_udc_suspend      NULL
2698 #define pxa2xx_udc_resume       NULL
2699 #endif
2700
2701 /*-------------------------------------------------------------------------*/
2702
2703 static struct platform_driver udc_driver = {
2704         .probe          = pxa2xx_udc_probe,
2705         .shutdown       = pxa2xx_udc_shutdown,
2706         .remove         = __exit_p(pxa2xx_udc_remove),
2707         .suspend        = pxa2xx_udc_suspend,
2708         .resume         = pxa2xx_udc_resume,
2709         .driver         = {
2710                 .owner  = THIS_MODULE,
2711                 .name   = "pxa2xx-udc",
2712         },
2713 };
2714
2715 static int __init udc_init(void)
2716 {
2717         printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2718         return platform_driver_register(&udc_driver);
2719 }
2720 module_init(udc_init);
2721
2722 static void __exit udc_exit(void)
2723 {
2724         platform_driver_unregister(&udc_driver);
2725 }
2726 module_exit(udc_exit);
2727
2728 MODULE_DESCRIPTION(DRIVER_DESC);
2729 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2730 MODULE_LICENSE("GPL");
2731