drivers/usb/gadget/pch_udc.c

   1 /*
   2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  */
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/errno.h>
  14 #include <linux/list.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/usb/ch9.h>
  17 #include <linux/usb/gadget.h>
  18
  19 /* Address offset of Registers */
  20 #define UDC_EP_REG_SHIFT        0x20    /* Offset to next EP */
  21
  22 #define UDC_EPCTL_ADDR          0x00    /* Endpoint control */
  23 #define UDC_EPSTS_ADDR          0x04    /* Endpoint status */
  24 #define UDC_BUFIN_FRAMENUM_ADDR 0x08    /* buffer size in / frame number out */
  25 #define UDC_BUFOUT_MAXPKT_ADDR  0x0C    /* buffer size out / maxpkt in */
  26 #define UDC_SUBPTR_ADDR         0x10    /* setup buffer pointer */
  27 #define UDC_DESPTR_ADDR         0x14    /* Data descriptor pointer */
  28 #define UDC_CONFIRM_ADDR        0x18    /* Write/Read confirmation */
  29
  30 #define UDC_DEVCFG_ADDR         0x400   /* Device configuration */
  31 #define UDC_DEVCTL_ADDR         0x404   /* Device control */
  32 #define UDC_DEVSTS_ADDR         0x408   /* Device status */
  33 #define UDC_DEVIRQSTS_ADDR      0x40C   /* Device irq status */
  34 #define UDC_DEVIRQMSK_ADDR      0x410   /* Device irq mask */
  35 #define UDC_EPIRQSTS_ADDR       0x414   /* Endpoint irq status */
  36 #define UDC_EPIRQMSK_ADDR       0x418   /* Endpoint irq mask */
  37 #define UDC_DEVLPM_ADDR         0x41C   /* LPM control / status */
  38 #define UDC_CSR_BUSY_ADDR       0x4f0   /* UDC_CSR_BUSY Status register */
  39 #define UDC_SRST_ADDR           0x4fc   /* SOFT RESET register */
  40 #define UDC_CSR_ADDR            0x500   /* USB_DEVICE endpoint register */
  41
  42 /* Endpoint control register */
  43 /* Bit position */
  44 #define UDC_EPCTL_MRXFLUSH              (1 << 12)
  45 #define UDC_EPCTL_RRDY                  (1 << 9)
  46 #define UDC_EPCTL_CNAK                  (1 << 8)
  47 #define UDC_EPCTL_SNAK                  (1 << 7)
  48 #define UDC_EPCTL_NAK                   (1 << 6)
  49 #define UDC_EPCTL_P                     (1 << 3)
  50 #define UDC_EPCTL_F                     (1 << 1)
  51 #define UDC_EPCTL_S                     (1 << 0)
  52 #define UDC_EPCTL_ET_SHIFT              4
  53 /* Mask patern */
  54 #define UDC_EPCTL_ET_MASK               0x00000030
  55 /* Value for ET field */
  56 #define UDC_EPCTL_ET_CONTROL            0
  57 #define UDC_EPCTL_ET_ISO                1
  58 #define UDC_EPCTL_ET_BULK               2
  59 #define UDC_EPCTL_ET_INTERRUPT          3
  60
  61 /* Endpoint status register */
  62 /* Bit position */
  63 #define UDC_EPSTS_XFERDONE              (1 << 27)
  64 #define UDC_EPSTS_RSS                   (1 << 26)
  65 #define UDC_EPSTS_RCS                   (1 << 25)
  66 #define UDC_EPSTS_TXEMPTY               (1 << 24)
  67 #define UDC_EPSTS_TDC                   (1 << 10)
  68 #define UDC_EPSTS_HE                    (1 << 9)
  69 #define UDC_EPSTS_MRXFIFO_EMP           (1 << 8)
  70 #define UDC_EPSTS_BNA                   (1 << 7)
  71 #define UDC_EPSTS_IN                    (1 << 6)
  72 #define UDC_EPSTS_OUT_SHIFT             4
  73 /* Mask patern */
  74 #define UDC_EPSTS_OUT_MASK              0x00000030
  75 #define UDC_EPSTS_ALL_CLR_MASK          0x1F0006F0
  76 /* Value for OUT field */
  77 #define UDC_EPSTS_OUT_SETUP             2
  78 #define UDC_EPSTS_OUT_DATA              1
  79
  80 /* Device configuration register */
  81 /* Bit position */
  82 #define UDC_DEVCFG_CSR_PRG              (1 << 17)
  83 #define UDC_DEVCFG_SP                   (1 << 3)
  84 /* SPD Valee */
  85 #define UDC_DEVCFG_SPD_HS               0x0
  86 #define UDC_DEVCFG_SPD_FS               0x1
  87 #define UDC_DEVCFG_SPD_LS               0x2
  88
  89 /* Device control register */
  90 /* Bit position */
  91 #define UDC_DEVCTL_THLEN_SHIFT          24
  92 #define UDC_DEVCTL_BRLEN_SHIFT          16
  93 #define UDC_DEVCTL_CSR_DONE             (1 << 13)
  94 #define UDC_DEVCTL_SD                   (1 << 10)
  95 #define UDC_DEVCTL_MODE                 (1 << 9)
  96 #define UDC_DEVCTL_BREN                 (1 << 8)
  97 #define UDC_DEVCTL_THE                  (1 << 7)
  98 #define UDC_DEVCTL_DU                   (1 << 4)
  99 #define UDC_DEVCTL_TDE                  (1 << 3)
 100 #define UDC_DEVCTL_RDE                  (1 << 2)
 101 #define UDC_DEVCTL_RES                  (1 << 0)
 102
 103 /* Device status register */
 104 /* Bit position */
 105 #define UDC_DEVSTS_TS_SHIFT             18
 106 #define UDC_DEVSTS_ENUM_SPEED_SHIFT     13
 107 #define UDC_DEVSTS_ALT_SHIFT            8
 108 #define UDC_DEVSTS_INTF_SHIFT           4
 109 #define UDC_DEVSTS_CFG_SHIFT            0
 110 /* Mask patern */
 111 #define UDC_DEVSTS_TS_MASK              0xfffc0000
 112 #define UDC_DEVSTS_ENUM_SPEED_MASK      0x00006000
 113 #define UDC_DEVSTS_ALT_MASK             0x00000f00
 114 #define UDC_DEVSTS_INTF_MASK            0x000000f0
 115 #define UDC_DEVSTS_CFG_MASK             0x0000000f
 116 /* value for maximum speed for SPEED field */
 117 #define UDC_DEVSTS_ENUM_SPEED_FULL      1
 118 #define UDC_DEVSTS_ENUM_SPEED_HIGH      0
 119 #define UDC_DEVSTS_ENUM_SPEED_LOW       2
 120 #define UDC_DEVSTS_ENUM_SPEED_FULLX     3
 121
 122 /* Device irq register */
 123 /* Bit position */
 124 #define UDC_DEVINT_RWKP                 (1 << 7)
 125 #define UDC_DEVINT_ENUM                 (1 << 6)
 126 #define UDC_DEVINT_SOF                  (1 << 5)
 127 #define UDC_DEVINT_US                   (1 << 4)
 128 #define UDC_DEVINT_UR                   (1 << 3)
 129 #define UDC_DEVINT_ES                   (1 << 2)
 130 #define UDC_DEVINT_SI                   (1 << 1)
 131 #define UDC_DEVINT_SC                   (1 << 0)
 132 /* Mask patern */
 133 #define UDC_DEVINT_MSK                  0x7f
 134
 135 /* Endpoint irq register */
 136 /* Bit position */
 137 #define UDC_EPINT_IN_SHIFT              0
 138 #define UDC_EPINT_OUT_SHIFT             16
 139 #define UDC_EPINT_IN_EP0                (1 << 0)
 140 #define UDC_EPINT_OUT_EP0               (1 << 16)
 141 /* Mask patern */
 142 #define UDC_EPINT_MSK_DISABLE_ALL       0xffffffff
 143
 144 /* UDC_CSR_BUSY Status register */
 145 /* Bit position */
 146 #define UDC_CSR_BUSY                    (1 << 0)
 147
 148 /* SOFT RESET register */
 149 /* Bit position */
 150 #define UDC_PSRST                       (1 << 1)
 151 #define UDC_SRST                        (1 << 0)
 152
 153 /* USB_DEVICE endpoint register */
 154 /* Bit position */
 155 #define UDC_CSR_NE_NUM_SHIFT            0
 156 #define UDC_CSR_NE_DIR_SHIFT            4
 157 #define UDC_CSR_NE_TYPE_SHIFT           5
 158 #define UDC_CSR_NE_CFG_SHIFT            7
 159 #define UDC_CSR_NE_INTF_SHIFT           11
 160 #define UDC_CSR_NE_ALT_SHIFT            15
 161 #define UDC_CSR_NE_MAX_PKT_SHIFT        19
 162 /* Mask patern */
 163 #define UDC_CSR_NE_NUM_MASK             0x0000000f
 164 #define UDC_CSR_NE_DIR_MASK             0x00000010
 165 #define UDC_CSR_NE_TYPE_MASK            0x00000060
 166 #define UDC_CSR_NE_CFG_MASK             0x00000780
 167 #define UDC_CSR_NE_INTF_MASK            0x00007800
 168 #define UDC_CSR_NE_ALT_MASK             0x00078000
 169 #define UDC_CSR_NE_MAX_PKT_MASK         0x3ff80000
 170
 171 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
 172 #define PCH_UDC_EPINT(in, num)\
 173                 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
 174
 175 /* Index of endpoint */
 176 #define UDC_EP0IN_IDX           0
 177 #define UDC_EP0OUT_IDX          1
 178 #define UDC_EPIN_IDX(ep)        (ep * 2)
 179 #define UDC_EPOUT_IDX(ep)       (ep * 2 + 1)
 180 #define PCH_UDC_EP0             0
 181 #define PCH_UDC_EP1             1
 182 #define PCH_UDC_EP2             2
 183 #define PCH_UDC_EP3             3
 184
 185 /* Number of endpoint */
 186 #define PCH_UDC_EP_NUM          32      /* Total number of EPs (16 IN,16 OUT) */
 187 #define PCH_UDC_USED_EP_NUM     4       /* EP number of EP's really used */
 188 /* Length Value */
 189 #define PCH_UDC_BRLEN           0x0F    /* Burst length */
 190 #define PCH_UDC_THLEN           0x1F    /* Threshold length */
 191 /* Value of EP Buffer Size */
 192 #define UDC_EP0IN_BUFF_SIZE     16
 193 #define UDC_EPIN_BUFF_SIZE      256
 194 #define UDC_EP0OUT_BUFF_SIZE    16
 195 #define UDC_EPOUT_BUFF_SIZE     256
 196 /* Value of EP maximum packet size */
 197 #define UDC_EP0IN_MAX_PKT_SIZE  64
 198 #define UDC_EP0OUT_MAX_PKT_SIZE 64
 199 #define UDC_BULK_MAX_PKT_SIZE   512
 200
 201 /* DMA */
 202 #define DMA_DIR_RX              1       /* DMA for data receive */
 203 #define DMA_DIR_TX              2       /* DMA for data transmit */
 204 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
 205 #define UDC_DMA_MAXPACKET       65536   /* maximum packet size for DMA */
 206
 207 /**
 208  * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
 209  *                                for data
 210  * @status:             Status quadlet
 211  * @reserved:           Reserved
 212  * @dataptr:            Buffer descriptor
 213  * @next:               Next descriptor
 214  */
 215 struct pch_udc_data_dma_desc {
 216         u32 status;
 217         u32 reserved;
 218         u32 dataptr;
 219         u32 next;
 220 };
 221
 222 /**
 223  * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
 224  *                               for control data
 225  * @status:     Status
 226  * @reserved:   Reserved
 227  * @data12:     First setup word
 228  * @data34:     Second setup word
 229  */
 230 struct pch_udc_stp_dma_desc {
 231         u32 status;
 232         u32 reserved;
 233         struct usb_ctrlrequest request;
 234 } __attribute((packed));
 235
 236 /* DMA status definitions */
 237 /* Buffer status */
 238 #define PCH_UDC_BUFF_STS        0xC0000000
 239 #define PCH_UDC_BS_HST_RDY      0x00000000
 240 #define PCH_UDC_BS_DMA_BSY      0x40000000
 241 #define PCH_UDC_BS_DMA_DONE     0x80000000
 242 #define PCH_UDC_BS_HST_BSY      0xC0000000
 243 /*  Rx/Tx Status */
 244 #define PCH_UDC_RXTX_STS        0x30000000
 245 #define PCH_UDC_RTS_SUCC        0x00000000
 246 #define PCH_UDC_RTS_DESERR      0x10000000
 247 #define PCH_UDC_RTS_BUFERR      0x30000000
 248 /* Last Descriptor Indication */
 249 #define PCH_UDC_DMA_LAST        0x08000000
 250 /* Number of Rx/Tx Bytes Mask */
 251 #define PCH_UDC_RXTX_BYTES      0x0000ffff
 252
 253 /**
 254  * struct pch_udc_cfg_data - Structure to hold current configuration
 255  *                           and interface information
 256  * @cur_cfg:    current configuration in use
 257  * @cur_intf:   current interface in use
 258  * @cur_alt:    current alt interface in use
 259  */
 260 struct pch_udc_cfg_data {
 261         u16 cur_cfg;
 262         u16 cur_intf;
 263         u16 cur_alt;
 264 };
 265
 266 /**
 267  * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
 268  * @ep:                 embedded ep request
 269  * @td_stp_phys:        for setup request
 270  * @td_data_phys:       for data request
 271  * @td_stp:             for setup request
 272  * @td_data:            for data request
 273  * @dev:                reference to device struct
 274  * @offset_addr:        offset address of ep register
 275  * @desc:               for this ep
 276  * @queue:              queue for requests
 277  * @num:                endpoint number
 278  * @in:                 endpoint is IN
 279  * @halted:             endpoint halted?
 280  * @epsts:              Endpoint status
 281  */
 282 struct pch_udc_ep {
 283         struct usb_ep                   ep;
 284         dma_addr_t                      td_stp_phys;
 285         dma_addr_t                      td_data_phys;
 286         struct pch_udc_stp_dma_desc     *td_stp;
 287         struct pch_udc_data_dma_desc    *td_data;
 288         struct pch_udc_dev              *dev;
 289         unsigned long                   offset_addr;
 290         const struct usb_endpoint_descriptor    *desc;
 291         struct list_head                queue;
 292         unsigned                        num:5,
 293                                         in:1,
 294                                         halted:1;
 295         unsigned long                   epsts;
 296 };
 297
 298 /**
 299  * struct pch_udc_dev - Structure holding complete information
 300  *                      of the PCH USB device
 301  * @gadget:             gadget driver data
 302  * @driver:             reference to gadget driver bound
 303  * @pdev:               reference to the PCI device
 304  * @ep:                 array of endpoints
 305  * @lock:               protects all state
 306  * @active:             enabled the PCI device
 307  * @stall:              stall requested
 308  * @prot_stall:         protcol stall requested
 309  * @irq_registered:     irq registered with system
 310  * @mem_region:         device memory mapped
 311  * @registered:         driver regsitered with system
 312  * @suspended:          driver in suspended state
 313  * @connected:          gadget driver associated
 314  * @vbus_session:       required vbus_session state
 315  * @set_cfg_not_acked:  pending acknowledgement 4 setup
 316  * @waiting_zlp_ack:    pending acknowledgement 4 ZLP
 317  * @data_requests:      DMA pool for data requests
 318  * @stp_requests:       DMA pool for setup requests
 319  * @dma_addr:           DMA pool for received
 320  * @ep0out_buf:         Buffer for DMA
 321  * @setup_data:         Received setup data
 322  * @phys_addr:          of device memory
 323  * @base_addr:          for mapped device memory
 324  * @irq:                IRQ line for the device
 325  * @cfg_data:           current cfg, intf, and alt in use
 326  */
 327 struct pch_udc_dev {
 328         struct usb_gadget               gadget;
 329         struct usb_gadget_driver        *driver;
 330         struct pci_dev                  *pdev;
 331         struct pch_udc_ep               ep[PCH_UDC_EP_NUM];
 332         spinlock_t                      lock; /* protects all state */
 333         unsigned        active:1,
 334                         stall:1,
 335                         prot_stall:1,
 336                         irq_registered:1,
 337                         mem_region:1,
 338                         registered:1,
 339                         suspended:1,
 340                         connected:1,
 341                         vbus_session:1,
 342                         set_cfg_not_acked:1,
 343                         waiting_zlp_ack:1;
 344         struct pci_pool         *data_requests;
 345         struct pci_pool         *stp_requests;
 346         dma_addr_t                      dma_addr;
 347         void                            *ep0out_buf;
 348         struct usb_ctrlrequest          setup_data;
 349         unsigned long                   phys_addr;
 350         void __iomem                    *base_addr;
 351         unsigned                        irq;
 352         struct pch_udc_cfg_data cfg_data;
 353 };
 354
 355 #define PCH_UDC_PCI_BAR                 1
 356 #define PCI_DEVICE_ID_INTEL_EG20T_UDC   0x8808
 357 #define PCI_VENDOR_ID_ROHM              0x10DB
 358 #define PCI_DEVICE_ID_ML7213_IOH_UDC    0x801D
 359 #define PCI_DEVICE_ID_ML7831_IOH_UDC    0x8808
 360
 361 static const char       ep0_string[] = "ep0in";
 362 static DEFINE_SPINLOCK(udc_stall_spinlock);     /* stall spin lock */
 363 struct pch_udc_dev *pch_udc;            /* pointer to device object */
 364 static int speed_fs;
 365 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
 366 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
 367
 368 /**
 369  * struct pch_udc_request - Structure holding a PCH USB device request packet
 370  * @req:                embedded ep request
 371  * @td_data_phys:       phys. address
 372  * @td_data:            first dma desc. of chain
 373  * @td_data_last:       last dma desc. of chain
 374  * @queue:              associated queue
 375  * @dma_going:          DMA in progress for request
 376  * @dma_mapped:         DMA memory mapped for request
 377  * @dma_done:           DMA completed for request
 378  * @chain_len:          chain length
 379  * @buf:                Buffer memory for align adjustment
 380  * @dma:                DMA memory for align adjustment
 381  */
 382 struct pch_udc_request {
 383         struct usb_request              req;
 384         dma_addr_t                      td_data_phys;
 385         struct pch_udc_data_dma_desc    *td_data;
 386         struct pch_udc_data_dma_desc    *td_data_last;
 387         struct list_head                queue;
 388         unsigned                        dma_going:1,
 389                                         dma_mapped:1,
 390                                         dma_done:1;
 391         unsigned                        chain_len;
 392         void                            *buf;
 393         dma_addr_t                      dma;
 394 };
 395
 396 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
 397 {
 398         return ioread32(dev->base_addr + reg);
 399 }
 400
 401 static inline void pch_udc_writel(struct pch_udc_dev *dev,
 402                                     unsigned long val, unsigned long reg)
 403 {
 404         iowrite32(val, dev->base_addr + reg);
 405 }
 406
 407 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
 408                                      unsigned long reg,
 409                                      unsigned long bitmask)
 410 {
 411         pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
 412 }
 413
 414 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
 415                                      unsigned long reg,
 416                                      unsigned long bitmask)
 417 {
 418         pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
 419 }
 420
 421 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
 422 {
 423         return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
 424 }
 425
 426 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
 427                                     unsigned long val, unsigned long reg)
 428 {
 429         iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
 430 }
 431
 432 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
 433                                      unsigned long reg,
 434                                      unsigned long bitmask)
 435 {
 436         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
 437 }
 438
 439 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
 440                                      unsigned long reg,
 441                                      unsigned long bitmask)
 442 {
 443         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
 444 }
 445
 446 /**
 447  * pch_udc_csr_busy() - Wait till idle.
 448  * @dev:        Reference to pch_udc_dev structure
 449  */
 450 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
 451 {
 452         unsigned int count = 200;
 453
 454         /* Wait till idle */
 455         while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
 456                 && --count)
 457                 cpu_relax();
 458         if (!count)
 459                 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
 460 }
 461
 462 /**
 463  * pch_udc_write_csr() - Write the command and status registers.
 464  * @dev:        Reference to pch_udc_dev structure
 465  * @val:        value to be written to CSR register
 466  * @addr:       address of CSR register
 467  */
 468 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
 469                                unsigned int ep)
 470 {
 471         unsigned long reg = PCH_UDC_CSR(ep);
 472
 473         pch_udc_csr_busy(dev);          /* Wait till idle */
 474         pch_udc_writel(dev, val, reg);
 475         pch_udc_csr_busy(dev);          /* Wait till idle */
 476 }
 477
 478 /**
 479  * pch_udc_read_csr() - Read the command and status registers.
 480  * @dev:        Reference to pch_udc_dev structure
 481  * @addr:       address of CSR register
 482  *
 483  * Return codes:        content of CSR register
 484  */
 485 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
 486 {
 487         unsigned long reg = PCH_UDC_CSR(ep);
 488
 489         pch_udc_csr_busy(dev);          /* Wait till idle */
 490         pch_udc_readl(dev, reg);        /* Dummy read */
 491         pch_udc_csr_busy(dev);          /* Wait till idle */
 492         return pch_udc_readl(dev, reg);
 493 }
 494
 495 /**
 496  * pch_udc_rmt_wakeup() - Initiate for remote wakeup
 497  * @dev:        Reference to pch_udc_dev structure
 498  */
 499 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
 500 {
 501         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 502         mdelay(1);
 503         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 504 }
 505
 506 /**
 507  * pch_udc_get_frame() - Get the current frame from device status register
 508  * @dev:        Reference to pch_udc_dev structure
 509  * Retern       current frame
 510  */
 511 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
 512 {
 513         u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 514         return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
 515 }
 516
 517 /**
 518  * pch_udc_clear_selfpowered() - Clear the self power control
 519  * @dev:        Reference to pch_udc_regs structure
 520  */
 521 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
 522 {
 523         pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 524 }
 525
 526 /**
 527  * pch_udc_set_selfpowered() - Set the self power control
 528  * @dev:        Reference to pch_udc_regs structure
 529  */
 530 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
 531 {
 532         pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 533 }
 534
 535 /**
 536  * pch_udc_set_disconnect() - Set the disconnect status.
 537  * @dev:        Reference to pch_udc_regs structure
 538  */
 539 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
 540 {
 541         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 542 }
 543
 544 /**
 545  * pch_udc_clear_disconnect() - Clear the disconnect status.
 546  * @dev:        Reference to pch_udc_regs structure
 547  */
 548 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
 549 {
 550         /* Clear the disconnect */
 551         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 552         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 553         mdelay(1);
 554         /* Resume USB signalling */
 555         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 556 }
 557
 558 /**
 559  * pch_udc_reconnect() - This API initializes usb device controller,
 560  *                                              and clear the disconnect status.
 561  * @dev:                Reference to pch_udc_regs structure
 562  */
 563 static void pch_udc_init(struct pch_udc_dev *dev);
 564 static void pch_udc_reconnect(struct pch_udc_dev *dev)
 565 {
 566         pch_udc_init(dev);
 567
 568         /* enable device interrupts */
 569         /* pch_udc_enable_interrupts() */
 570         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
 571                         UDC_DEVINT_UR | UDC_DEVINT_ENUM);
 572
 573         /* Clear the disconnect */
 574         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 575         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 576         mdelay(1);
 577         /* Resume USB signalling */
 578         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 579 }
 580
 581 /**
 582  * pch_udc_vbus_session() - set or clearr the disconnect status.
 583  * @dev:        Reference to pch_udc_regs structure
 584  * @is_active:  Parameter specifying the action
 585  *                0:   indicating VBUS power is ending
 586  *                !0:  indicating VBUS power is starting
 587  */
 588 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
 589                                           int is_active)
 590 {
 591         if (is_active) {
 592                 pch_udc_reconnect(dev);
 593                 dev->vbus_session = 1;
 594         } else {
 595                 if (dev->driver && dev->driver->disconnect) {
 596                         spin_unlock(&dev->lock);
 597                         dev->driver->disconnect(&dev->gadget);
 598                         spin_lock(&dev->lock);
 599                 }
 600                 pch_udc_set_disconnect(dev);
 601                 dev->vbus_session = 0;
 602         }
 603 }
 604
 605 /**
 606  * pch_udc_ep_set_stall() - Set the stall of endpoint
 607  * @ep:         Reference to structure of type pch_udc_ep_regs
 608  */
 609 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
 610 {
 611         if (ep->in) {
 612                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 613                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 614         } else {
 615                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 616         }
 617 }
 618
 619 /**
 620  * pch_udc_ep_clear_stall() - Clear the stall of endpoint
 621  * @ep:         Reference to structure of type pch_udc_ep_regs
 622  */
 623 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
 624 {
 625         /* Clear the stall */
 626         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 627         /* Clear NAK by writing CNAK */
 628         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 629 }
 630
 631 /**
 632  * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
 633  * @ep:         Reference to structure of type pch_udc_ep_regs
 634  * @type:       Type of endpoint
 635  */
 636 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
 637                                         u8 type)
 638 {
 639         pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
 640                                 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
 641 }
 642
 643 /**
 644  * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
 645  * @ep:         Reference to structure of type pch_udc_ep_regs
 646  * @buf_size:   The buffer word size
 647  */
 648 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
 649                                                  u32 buf_size, u32 ep_in)
 650 {
 651         u32 data;
 652         if (ep_in) {
 653                 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
 654                 data = (data & 0xffff0000) | (buf_size & 0xffff);
 655                 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
 656         } else {
 657                 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 658                 data = (buf_size << 16) | (data & 0xffff);
 659                 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 660         }
 661 }
 662
 663 /**
 664  * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
 665  * @ep:         Reference to structure of type pch_udc_ep_regs
 666  * @pkt_size:   The packet byte size
 667  */
 668 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
 669 {
 670         u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 671         data = (data & 0xffff0000) | (pkt_size & 0xffff);
 672         pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 673 }
 674
 675 /**
 676  * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
 677  * @ep:         Reference to structure of type pch_udc_ep_regs
 678  * @addr:       Address of the register
 679  */
 680 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
 681 {
 682         pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
 683 }
 684
 685 /**
 686  * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
 687  * @ep:         Reference to structure of type pch_udc_ep_regs
 688  * @addr:       Address of the register
 689  */
 690 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
 691 {
 692         pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
 693 }
 694
 695 /**
 696  * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
 697  * @ep:         Reference to structure of type pch_udc_ep_regs
 698  */
 699 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
 700 {
 701         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
 702 }
 703
 704 /**
 705  * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
 706  * @ep:         Reference to structure of type pch_udc_ep_regs
 707  */
 708 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
 709 {
 710         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 711 }
 712
 713 /**
 714  * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
 715  * @ep:         Reference to structure of type pch_udc_ep_regs
 716  */
 717 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
 718 {
 719         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 720 }
 721
 722 /**
 723  * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
 724  *                      register depending on the direction specified
 725  * @dev:        Reference to structure of type pch_udc_regs
 726  * @dir:        whether Tx or Rx
 727  *                DMA_DIR_RX: Receive
 728  *                DMA_DIR_TX: Transmit
 729  */
 730 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
 731 {
 732         if (dir == DMA_DIR_RX)
 733                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 734         else if (dir == DMA_DIR_TX)
 735                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 736 }
 737
 738 /**
 739  * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
 740  *                               register depending on the direction specified
 741  * @dev:        Reference to structure of type pch_udc_regs
 742  * @dir:        Whether Tx or Rx
 743  *                DMA_DIR_RX: Receive
 744  *                DMA_DIR_TX: Transmit
 745  */
 746 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
 747 {
 748         if (dir == DMA_DIR_RX)
 749                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 750         else if (dir == DMA_DIR_TX)
 751                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 752 }
 753
 754 /**
 755  * pch_udc_set_csr_done() - Set the device control register
 756  *                              CSR done field (bit 13)
 757  * @dev:        reference to structure of type pch_udc_regs
 758  */
 759 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
 760 {
 761         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
 762 }
 763
 764 /**
 765  * pch_udc_disable_interrupts() - Disables the specified interrupts
 766  * @dev:        Reference to structure of type pch_udc_regs
 767  * @mask:       Mask to disable interrupts
 768  */
 769 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
 770                                             u32 mask)
 771 {
 772         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
 773 }
 774
 775 /**
 776  * pch_udc_enable_interrupts() - Enable the specified interrupts
 777  * @dev:        Reference to structure of type pch_udc_regs
 778  * @mask:       Mask to enable interrupts
 779  */
 780 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
 781                                            u32 mask)
 782 {
 783         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
 784 }
 785
 786 /**
 787  * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
 788  * @dev:        Reference to structure of type pch_udc_regs
 789  * @mask:       Mask to disable interrupts
 790  */
 791 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
 792                                                 u32 mask)
 793 {
 794         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
 795 }
 796
 797 /**
 798  * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
 799  * @dev:        Reference to structure of type pch_udc_regs
 800  * @mask:       Mask to enable interrupts
 801  */
 802 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
 803                                               u32 mask)
 804 {
 805         pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
 806 }
 807
 808 /**
 809  * pch_udc_read_device_interrupts() - Read the device interrupts
 810  * @dev:        Reference to structure of type pch_udc_regs
 811  * Retern       The device interrupts
 812  */
 813 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
 814 {
 815         return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
 816 }
 817
 818 /**
 819  * pch_udc_write_device_interrupts() - Write device interrupts
 820  * @dev:        Reference to structure of type pch_udc_regs
 821  * @val:        The value to be written to interrupt register
 822  */
 823 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
 824                                                      u32 val)
 825 {
 826         pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
 827 }
 828
 829 /**
 830  * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
 831  * @dev:        Reference to structure of type pch_udc_regs
 832  * Retern       The endpoint interrupt
 833  */
 834 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
 835 {
 836         return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
 837 }
 838
 839 /**
 840  * pch_udc_write_ep_interrupts() - Clear endpoint interupts
 841  * @dev:        Reference to structure of type pch_udc_regs
 842  * @val:        The value to be written to interrupt register
 843  */
 844 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
 845                                              u32 val)
 846 {
 847         pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
 848 }
 849
 850 /**
 851  * pch_udc_read_device_status() - Read the device status
 852  * @dev:        Reference to structure of type pch_udc_regs
 853  * Retern       The device status
 854  */
 855 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
 856 {
 857         return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 858 }
 859
 860 /**
 861  * pch_udc_read_ep_control() - Read the endpoint control
 862  * @ep:         Reference to structure of type pch_udc_ep_regs
 863  * Retern       The endpoint control register value
 864  */
 865 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
 866 {
 867         return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
 868 }
 869
 870 /**
 871  * pch_udc_clear_ep_control() - Clear the endpoint control register
 872  * @ep:         Reference to structure of type pch_udc_ep_regs
 873  * Retern       The endpoint control register value
 874  */
 875 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
 876 {
 877         return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
 878 }
 879
 880 /**
 881  * pch_udc_read_ep_status() - Read the endpoint status
 882  * @ep:         Reference to structure of type pch_udc_ep_regs
 883  * Retern       The endpoint status
 884  */
 885 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
 886 {
 887         return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
 888 }
 889
 890 /**
 891  * pch_udc_clear_ep_status() - Clear the endpoint status
 892  * @ep:         Reference to structure of type pch_udc_ep_regs
 893  * @stat:       Endpoint status
 894  */
 895 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
 896                                          u32 stat)
 897 {
 898         return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
 899 }
 900
 901 /**
 902  * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
 903  *                              of the endpoint control register
 904  * @ep:         Reference to structure of type pch_udc_ep_regs
 905  */
 906 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
 907 {
 908         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
 909 }
 910
 911 /**
 912  * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
 913  *                              of the endpoint control register
 914  * @ep:         reference to structure of type pch_udc_ep_regs
 915  */
 916 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
 917 {
 918         unsigned int loopcnt = 0;
 919         struct pch_udc_dev *dev = ep->dev;
 920
 921         if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
 922                 return;
 923         if (!ep->in) {
 924                 loopcnt = 10000;
 925                 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
 926                         --loopcnt)
 927                         udelay(5);
 928                 if (!loopcnt)
 929                         dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
 930                                 __func__);
 931         }
 932         loopcnt = 10000;
 933         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
 934                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 935                 udelay(5);
 936         }
 937         if (!loopcnt)
 938                 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
 939                         __func__, ep->num, (ep->in ? "in" : "out"));
 940 }
 941
 942 /**
 943  * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
 944  * @ep: reference to structure of type pch_udc_ep_regs
 945  * @dir:        direction of endpoint
 946  *                0:  endpoint is OUT
 947  *                !0: endpoint is IN
 948  */
 949 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
 950 {
 951         if (dir) {      /* IN ep */
 952                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 953                 return;
 954         }
 955 }
 956
 957 /**
 958  * pch_udc_ep_enable() - This api enables endpoint
 959  * @regs:       Reference to structure pch_udc_ep_regs
 960  * @desc:       endpoint descriptor
 961  */
 962 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
 963                                struct pch_udc_cfg_data *cfg,
 964                                const struct usb_endpoint_descriptor *desc)
 965 {
 966         u32 val = 0;
 967         u32 buff_size = 0;
 968
 969         pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
 970         if (ep->in)
 971                 buff_size = UDC_EPIN_BUFF_SIZE;
 972         else
 973                 buff_size = UDC_EPOUT_BUFF_SIZE;
 974         pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
 975         pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
 976         pch_udc_ep_set_nak(ep);
 977         pch_udc_ep_fifo_flush(ep, ep->in);
 978         /* Configure the endpoint */
 979         val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
 980               ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
 981                 UDC_CSR_NE_TYPE_SHIFT) |
 982               (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
 983               (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
 984               (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
 985               usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
 986
 987         if (ep->in)
 988                 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
 989         else
 990                 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
 991 }
 992
 993 /**
 994  * pch_udc_ep_disable() - This api disables endpoint
 995  * @regs:       Reference to structure pch_udc_ep_regs
 996  */
 997 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
 998 {
 999         if (ep->in) {
1000                 /* flush the fifo */
1001                 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1002                 /* set NAK */
1003                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1004                 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1005         } else {
1006                 /* set NAK */
1007                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1008         }
1009         /* reset desc pointer */
1010         pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1011 }
1012
1013 /**
1014  * pch_udc_wait_ep_stall() - Wait EP stall.
1015  * @dev:        Reference to pch_udc_dev structure
1016  */
1017 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1018 {
1019         unsigned int count = 10000;
1020
1021         /* Wait till idle */
1022         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1023                 udelay(5);
1024         if (!count)
1025                 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1026 }
1027
1028 /**
1029  * pch_udc_init() - This API initializes usb device controller
1030  * @dev:        Rreference to pch_udc_regs structure
1031  */
1032 static void pch_udc_init(struct pch_udc_dev *dev)
1033 {
1034         if (NULL == dev) {
1035                 pr_err("%s: Invalid address\n", __func__);
1036                 return;
1037         }
1038         /* Soft Reset and Reset PHY */
1039         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1040         pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1041         mdelay(1);
1042         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1043         pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1044         mdelay(1);
1045         /* mask and clear all device interrupts */
1046         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1047         pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1048
1049         /* mask and clear all ep interrupts */
1050         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1051         pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1052
1053         /* enable dynamic CSR programmingi, self powered and device speed */
1054         if (speed_fs)
1055                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1056                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1057         else /* defaul high speed */
1058                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1059                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1060         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1061                         (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1062                         (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1063                         UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1064                         UDC_DEVCTL_THE);
1065 }
1066
1067 /**
1068  * pch_udc_exit() - This API exit usb device controller
1069  * @dev:        Reference to pch_udc_regs structure
1070  */
1071 static void pch_udc_exit(struct pch_udc_dev *dev)
1072 {
1073         /* mask all device interrupts */
1074         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1075         /* mask all ep interrupts */
1076         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1077         /* put device in disconnected state */
1078         pch_udc_set_disconnect(dev);
1079 }
1080
1081 /**
1082  * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1083  * @gadget:     Reference to the gadget driver
1084  *
1085  * Return codes:
1086  *      0:              Success
1087  *      -EINVAL:        If the gadget passed is NULL
1088  */
1089 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1090 {
1091         struct pch_udc_dev      *dev;
1092
1093         if (!gadget)
1094                 return -EINVAL;
1095         dev = container_of(gadget, struct pch_udc_dev, gadget);
1096         return pch_udc_get_frame(dev);
1097 }
1098
1099 /**
1100  * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1101  * @gadget:     Reference to the gadget driver
1102  *
1103  * Return codes:
1104  *      0:              Success
1105  *      -EINVAL:        If the gadget passed is NULL
1106  */
1107 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1108 {
1109         struct pch_udc_dev      *dev;
1110         unsigned long           flags;
1111
1112         if (!gadget)
1113                 return -EINVAL;
1114         dev = container_of(gadget, struct pch_udc_dev, gadget);
1115         spin_lock_irqsave(&dev->lock, flags);
1116         pch_udc_rmt_wakeup(dev);
1117         spin_unlock_irqrestore(&dev->lock, flags);
1118         return 0;
1119 }
1120
1121 /**
1122  * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1123  *                              is self powered or not
1124  * @gadget:     Reference to the gadget driver
1125  * @value:      Specifies self powered or not
1126  *
1127  * Return codes:
1128  *      0:              Success
1129  *      -EINVAL:        If the gadget passed is NULL
1130  */
1131 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1132 {
1133         struct pch_udc_dev      *dev;
1134
1135         if (!gadget)
1136                 return -EINVAL;
1137         dev = container_of(gadget, struct pch_udc_dev, gadget);
1138         if (value)
1139                 pch_udc_set_selfpowered(dev);
1140         else
1141                 pch_udc_clear_selfpowered(dev);
1142         return 0;
1143 }
1144
1145 /**
1146  * pch_udc_pcd_pullup() - This API is invoked to make the device
1147  *                              visible/invisible to the host
1148  * @gadget:     Reference to the gadget driver
1149  * @is_on:      Specifies whether the pull up is made active or inactive
1150  *
1151  * Return codes:
1152  *      0:              Success
1153  *      -EINVAL:        If the gadget passed is NULL
1154  */
1155 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1156 {
1157         struct pch_udc_dev      *dev;
1158
1159         if (!gadget)
1160                 return -EINVAL;
1161         dev = container_of(gadget, struct pch_udc_dev, gadget);
1162         if (is_on) {
1163                 pch_udc_reconnect(dev);
1164         } else {
1165                 if (dev->driver && dev->driver->disconnect) {
1166                         spin_unlock(&dev->lock);
1167                         dev->driver->disconnect(&dev->gadget);
1168                         spin_lock(&dev->lock);
1169                 }
1170                 pch_udc_set_disconnect(dev);
1171         }
1172
1173         return 0;
1174 }
1175
1176 /**
1177  * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1178  *                              transceiver (or GPIO) that
1179  *                              detects a VBUS power session starting/ending
1180  * @gadget:     Reference to the gadget driver
1181  * @is_active:  specifies whether the session is starting or ending
1182  *
1183  * Return codes:
1184  *      0:              Success
1185  *      -EINVAL:        If the gadget passed is NULL
1186  */
1187 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1188 {
1189         struct pch_udc_dev      *dev;
1190
1191         if (!gadget)
1192                 return -EINVAL;
1193         dev = container_of(gadget, struct pch_udc_dev, gadget);
1194         pch_udc_vbus_session(dev, is_active);
1195         return 0;
1196 }
1197
1198 /**
1199  * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1200  *                              SET_CONFIGURATION calls to
1201  *                              specify how much power the device can consume
1202  * @gadget:     Reference to the gadget driver
1203  * @mA:         specifies the current limit in 2mA unit
1204  *
1205  * Return codes:
1206  *      -EINVAL:        If the gadget passed is NULL
1207  *      -EOPNOTSUPP:
1208  */
1209 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1210 {
1211         return -EOPNOTSUPP;
1212 }
1213
1214 static int pch_udc_start(struct usb_gadget_driver *driver,
1215         int (*bind)(struct usb_gadget *));
1216 static int pch_udc_stop(struct usb_gadget_driver *driver);
1217 static const struct usb_gadget_ops pch_udc_ops = {
1218         .get_frame = pch_udc_pcd_get_frame,
1219         .wakeup = pch_udc_pcd_wakeup,
1220         .set_selfpowered = pch_udc_pcd_selfpowered,
1221         .pullup = pch_udc_pcd_pullup,
1222         .vbus_session = pch_udc_pcd_vbus_session,
1223         .vbus_draw = pch_udc_pcd_vbus_draw,
1224         .start  = pch_udc_start,
1225         .stop   = pch_udc_stop,
1226 };
1227
1228 /**
1229  * complete_req() - This API is invoked from the driver when processing
1230  *                      of a request is complete
1231  * @ep:         Reference to the endpoint structure
1232  * @req:        Reference to the request structure
1233  * @status:     Indicates the success/failure of completion
1234  */
1235 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1236                                                                  int status)
1237 {
1238         struct pch_udc_dev      *dev;
1239         unsigned halted = ep->halted;
1240
1241         list_del_init(&req->queue);
1242
1243         /* set new status if pending */
1244         if (req->req.status == -EINPROGRESS)
1245                 req->req.status = status;
1246         else
1247                 status = req->req.status;
1248
1249         dev = ep->dev;
1250         if (req->dma_mapped) {
1251                 if (req->dma == DMA_ADDR_INVALID) {
1252                         if (ep->in)
1253                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1254                                                  req->req.length,
1255                                                  DMA_TO_DEVICE);
1256                         else
1257                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1258                                                  req->req.length,
1259                                                  DMA_FROM_DEVICE);
1260                         req->req.dma = DMA_ADDR_INVALID;
1261                 } else {
1262                         if (ep->in)
1263                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1264                                                  req->req.length,
1265                                                  DMA_TO_DEVICE);
1266                         else {
1267                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1268                                                  req->req.length,
1269                                                  DMA_FROM_DEVICE);
1270                                 memcpy(req->req.buf, req->buf, req->req.length);
1271                         }
1272                         kfree(req->buf);
1273                         req->dma = DMA_ADDR_INVALID;
1274                 }
1275                 req->dma_mapped = 0;
1276         }
1277         ep->halted = 1;
1278         spin_unlock(&dev->lock);
1279         if (!ep->in)
1280                 pch_udc_ep_clear_rrdy(ep);
1281         req->req.complete(&ep->ep, &req->req);
1282         spin_lock(&dev->lock);
1283         ep->halted = halted;
1284 }
1285
1286 /**
1287  * empty_req_queue() - This API empties the request queue of an endpoint
1288  * @ep:         Reference to the endpoint structure
1289  */
1290 static void empty_req_queue(struct pch_udc_ep *ep)
1291 {
1292         struct pch_udc_request  *req;
1293
1294         ep->halted = 1;
1295         while (!list_empty(&ep->queue)) {
1296                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1297                 complete_req(ep, req, -ESHUTDOWN);      /* Remove from list */
1298         }
1299 }
1300
1301 /**
1302  * pch_udc_free_dma_chain() - This function frees the DMA chain created
1303  *                              for the request
1304  * @dev         Reference to the driver structure
1305  * @req         Reference to the request to be freed
1306  *
1307  * Return codes:
1308  *      0: Success
1309  */
1310 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1311                                    struct pch_udc_request *req)
1312 {
1313         struct pch_udc_data_dma_desc *td = req->td_data;
1314         unsigned i = req->chain_len;
1315
1316         dma_addr_t addr2;
1317         dma_addr_t addr = (dma_addr_t)td->next;
1318         td->next = 0x00;
1319         for (; i > 1; --i) {
1320                 /* do not free first desc., will be done by free for request */
1321                 td = phys_to_virt(addr);
1322                 addr2 = (dma_addr_t)td->next;
1323                 pci_pool_free(dev->data_requests, td, addr);
1324                 td->next = 0x00;
1325                 addr = addr2;
1326         }
1327         req->chain_len = 1;
1328 }
1329
1330 /**
1331  * pch_udc_create_dma_chain() - This function creates or reinitializes
1332  *                              a DMA chain
1333  * @ep:         Reference to the endpoint structure
1334  * @req:        Reference to the request
1335  * @buf_len:    The buffer length
1336  * @gfp_flags:  Flags to be used while mapping the data buffer
1337  *
1338  * Return codes:
1339  *      0:              success,
1340  *      -ENOMEM:        pci_pool_alloc invocation fails
1341  */
1342 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1343                                     struct pch_udc_request *req,
1344                                     unsigned long buf_len,
1345                                     gfp_t gfp_flags)
1346 {
1347         struct pch_udc_data_dma_desc *td = req->td_data, *last;
1348         unsigned long bytes = req->req.length, i = 0;
1349         dma_addr_t dma_addr;
1350         unsigned len = 1;
1351
1352         if (req->chain_len > 1)
1353                 pch_udc_free_dma_chain(ep->dev, req);
1354
1355         if (req->dma == DMA_ADDR_INVALID)
1356                 td->dataptr = req->req.dma;
1357         else
1358                 td->dataptr = req->dma;
1359
1360         td->status = PCH_UDC_BS_HST_BSY;
1361         for (; ; bytes -= buf_len, ++len) {
1362                 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1363                 if (bytes <= buf_len)
1364                         break;
1365                 last = td;
1366                 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1367                                     &dma_addr);
1368                 if (!td)
1369                         goto nomem;
1370                 i += buf_len;
1371                 td->dataptr = req->td_data->dataptr + i;
1372                 last->next = dma_addr;
1373         }
1374
1375         req->td_data_last = td;
1376         td->status |= PCH_UDC_DMA_LAST;
1377         td->next = req->td_data_phys;
1378         req->chain_len = len;
1379         return 0;
1380
1381 nomem:
1382         if (len > 1) {
1383                 req->chain_len = len;
1384                 pch_udc_free_dma_chain(ep->dev, req);
1385         }
1386         req->chain_len = 1;
1387         return -ENOMEM;
1388 }
1389
1390 /**
1391  * prepare_dma() - This function creates and initializes the DMA chain
1392  *                      for the request
1393  * @ep:         Reference to the endpoint structure
1394  * @req:        Reference to the request
1395  * @gfp:        Flag to be used while mapping the data buffer
1396  *
1397  * Return codes:
1398  *      0:              Success
1399  *      Other 0:        linux error number on failure
1400  */
1401 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1402                           gfp_t gfp)
1403 {
1404         int     retval;
1405
1406         /* Allocate and create a DMA chain */
1407         retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1408         if (retval) {
1409                 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1410                 return retval;
1411         }
1412         if (ep->in)
1413                 req->td_data->status = (req->td_data->status &
1414                                 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1415         return 0;
1416 }
1417
1418 /**
1419  * process_zlp() - This function process zero length packets
1420  *                      from the gadget driver
1421  * @ep:         Reference to the endpoint structure
1422  * @req:        Reference to the request
1423  */
1424 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1425 {
1426         struct pch_udc_dev      *dev = ep->dev;
1427
1428         /* IN zlp's are handled by hardware */
1429         complete_req(ep, req, 0);
1430
1431         /* if set_config or set_intf is waiting for ack by zlp
1432          * then set CSR_DONE
1433          */
1434         if (dev->set_cfg_not_acked) {
1435                 pch_udc_set_csr_done(dev);
1436                 dev->set_cfg_not_acked = 0;
1437         }
1438         /* setup command is ACK'ed now by zlp */
1439         if (!dev->stall && dev->waiting_zlp_ack) {
1440                 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1441                 dev->waiting_zlp_ack = 0;
1442         }
1443 }
1444
1445 /**
1446  * pch_udc_start_rxrequest() - This function starts the receive requirement.
1447  * @ep:         Reference to the endpoint structure
1448  * @req:        Reference to the request structure
1449  */
1450 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1451                                          struct pch_udc_request *req)
1452 {
1453         struct pch_udc_data_dma_desc *td_data;
1454
1455         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1456         td_data = req->td_data;
1457         /* Set the status bits for all descriptors */
1458         while (1) {
1459                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1460                                     PCH_UDC_BS_HST_RDY;
1461                 if ((td_data->status & PCH_UDC_DMA_LAST) ==  PCH_UDC_DMA_LAST)
1462                         break;
1463                 td_data = phys_to_virt(td_data->next);
1464         }
1465         /* Write the descriptor pointer */
1466         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1467         req->dma_going = 1;
1468         pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1469         pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1470         pch_udc_ep_clear_nak(ep);
1471         pch_udc_ep_set_rrdy(ep);
1472 }
1473
1474 /**
1475  * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1476  *                              from gadget driver
1477  * @usbep:      Reference to the USB endpoint structure
1478  * @desc:       Reference to the USB endpoint descriptor structure
1479  *
1480  * Return codes:
1481  *      0:              Success
1482  *      -EINVAL:
1483  *      -ESHUTDOWN:
1484  */
1485 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1486                                     const struct usb_endpoint_descriptor *desc)
1487 {
1488         struct pch_udc_ep       *ep;
1489         struct pch_udc_dev      *dev;
1490         unsigned long           iflags;
1491
1492         if (!usbep || (usbep->name == ep0_string) || !desc ||
1493             (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1494                 return -EINVAL;
1495
1496         ep = container_of(usbep, struct pch_udc_ep, ep);
1497         dev = ep->dev;
1498         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1499                 return -ESHUTDOWN;
1500         spin_lock_irqsave(&dev->lock, iflags);
1501         ep->desc = desc;
1502         ep->halted = 0;
1503         pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1504         ep->ep.maxpacket = usb_endpoint_maxp(desc);
1505         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1506         spin_unlock_irqrestore(&dev->lock, iflags);
1507         return 0;
1508 }
1509
1510 /**
1511  * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1512  *                              from gadget driver
1513  * @usbep       Reference to the USB endpoint structure
1514  *
1515  * Return codes:
1516  *      0:              Success
1517  *      -EINVAL:
1518  */
1519 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1520 {
1521         struct pch_udc_ep       *ep;
1522         struct pch_udc_dev      *dev;
1523         unsigned long   iflags;
1524
1525         if (!usbep)
1526                 return -EINVAL;
1527
1528         ep = container_of(usbep, struct pch_udc_ep, ep);
1529         dev = ep->dev;
1530         if ((usbep->name == ep0_string) || !ep->desc)
1531                 return -EINVAL;
1532
1533         spin_lock_irqsave(&ep->dev->lock, iflags);
1534         empty_req_queue(ep);
1535         ep->halted = 1;
1536         pch_udc_ep_disable(ep);
1537         pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1538         ep->desc = NULL;
1539         INIT_LIST_HEAD(&ep->queue);
1540         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1541         return 0;
1542 }
1543
1544 /**
1545  * pch_udc_alloc_request() - This function allocates request structure.
1546  *                              It is called by gadget driver
1547  * @usbep:      Reference to the USB endpoint structure
1548  * @gfp:        Flag to be used while allocating memory
1549  *
1550  * Return codes:
1551  *      NULL:                   Failure
1552  *      Allocated address:      Success
1553  */
1554 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1555                                                   gfp_t gfp)
1556 {
1557         struct pch_udc_request          *req;
1558         struct pch_udc_ep               *ep;
1559         struct pch_udc_data_dma_desc    *dma_desc;
1560         struct pch_udc_dev              *dev;
1561
1562         if (!usbep)
1563                 return NULL;
1564         ep = container_of(usbep, struct pch_udc_ep, ep);
1565         dev = ep->dev;
1566         req = kzalloc(sizeof *req, gfp);
1567         if (!req)
1568                 return NULL;
1569         req->req.dma = DMA_ADDR_INVALID;
1570         req->dma = DMA_ADDR_INVALID;
1571         INIT_LIST_HEAD(&req->queue);
1572         if (!ep->dev->dma_addr)
1573                 return &req->req;
1574         /* ep0 in requests are allocated from data pool here */
1575         dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1576                                   &req->td_data_phys);
1577         if (NULL == dma_desc) {
1578                 kfree(req);
1579                 return NULL;
1580         }
1581         /* prevent from using desc. - set HOST BUSY */
1582         dma_desc->status |= PCH_UDC_BS_HST_BSY;
1583         dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1584         req->td_data = dma_desc;
1585         req->td_data_last = dma_desc;
1586         req->chain_len = 1;
1587         return &req->req;
1588 }
1589
1590 /**
1591  * pch_udc_free_request() - This function frees request structure.
1592  *                              It is called by gadget driver
1593  * @usbep:      Reference to the USB endpoint structure
1594  * @usbreq:     Reference to the USB request
1595  */
1596 static void pch_udc_free_request(struct usb_ep *usbep,
1597                                   struct usb_request *usbreq)
1598 {
1599         struct pch_udc_ep       *ep;
1600         struct pch_udc_request  *req;
1601         struct pch_udc_dev      *dev;
1602
1603         if (!usbep || !usbreq)
1604                 return;
1605         ep = container_of(usbep, struct pch_udc_ep, ep);
1606         req = container_of(usbreq, struct pch_udc_request, req);
1607         dev = ep->dev;
1608         if (!list_empty(&req->queue))
1609                 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1610                         __func__, usbep->name, req);
1611         if (req->td_data != NULL) {
1612                 if (req->chain_len > 1)
1613                         pch_udc_free_dma_chain(ep->dev, req);
1614                 pci_pool_free(ep->dev->data_requests, req->td_data,
1615                               req->td_data_phys);
1616         }
1617         kfree(req);
1618 }
1619
1620 /**
1621  * pch_udc_pcd_queue() - This function queues a request packet. It is called
1622  *                      by gadget driver
1623  * @usbep:      Reference to the USB endpoint structure
1624  * @usbreq:     Reference to the USB request
1625  * @gfp:        Flag to be used while mapping the data buffer
1626  *
1627  * Return codes:
1628  *      0:                      Success
1629  *      linux error number:     Failure
1630  */
1631 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1632                                                                  gfp_t gfp)
1633 {
1634         int retval = 0;
1635         struct pch_udc_ep       *ep;
1636         struct pch_udc_dev      *dev;
1637         struct pch_udc_request  *req;
1638         unsigned long   iflags;
1639
1640         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1641                 return -EINVAL;
1642         ep = container_of(usbep, struct pch_udc_ep, ep);
1643         dev = ep->dev;
1644         if (!ep->desc && ep->num)
1645                 return -EINVAL;
1646         req = container_of(usbreq, struct pch_udc_request, req);
1647         if (!list_empty(&req->queue))
1648                 return -EINVAL;
1649         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1650                 return -ESHUTDOWN;
1651         spin_lock_irqsave(&dev->lock, iflags);
1652         /* map the buffer for dma */
1653         if (usbreq->length &&
1654             ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1655                 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1656                         if (ep->in)
1657                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1658                                                              usbreq->buf,
1659                                                              usbreq->length,
1660                                                              DMA_TO_DEVICE);
1661                         else
1662                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1663                                                              usbreq->buf,
1664                                                              usbreq->length,
1665                                                              DMA_FROM_DEVICE);
1666                 } else {
1667                         req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1668                         if (!req->buf) {
1669                                 retval = -ENOMEM;
1670                                 goto probe_end;
1671                         }
1672                         if (ep->in) {
1673                                 memcpy(req->buf, usbreq->buf, usbreq->length);
1674                                 req->dma = dma_map_single(&dev->pdev->dev,
1675                                                           req->buf,
1676                                                           usbreq->length,
1677                                                           DMA_TO_DEVICE);
1678                         } else
1679                                 req->dma = dma_map_single(&dev->pdev->dev,
1680                                                           req->buf,
1681                                                           usbreq->length,
1682                                                           DMA_FROM_DEVICE);
1683                 }
1684                 req->dma_mapped = 1;
1685         }
1686         if (usbreq->length > 0) {
1687                 retval = prepare_dma(ep, req, GFP_ATOMIC);
1688                 if (retval)
1689                         goto probe_end;
1690         }
1691         usbreq->actual = 0;
1692         usbreq->status = -EINPROGRESS;
1693         req->dma_done = 0;
1694         if (list_empty(&ep->queue) && !ep->halted) {
1695                 /* no pending transfer, so start this req */
1696                 if (!usbreq->length) {
1697                         process_zlp(ep, req);
1698                         retval = 0;
1699                         goto probe_end;
1700                 }
1701                 if (!ep->in) {
1702                         pch_udc_start_rxrequest(ep, req);
1703                 } else {
1704                         /*
1705                         * For IN trfr the descriptors will be programmed and
1706                         * P bit will be set when
1707                         * we get an IN token
1708                         */
1709                         pch_udc_wait_ep_stall(ep);
1710                         pch_udc_ep_clear_nak(ep);
1711                         pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1712                 }
1713         }
1714         /* Now add this request to the ep's pending requests */
1715         if (req != NULL)
1716                 list_add_tail(&req->queue, &ep->queue);
1717
1718 probe_end:
1719         spin_unlock_irqrestore(&dev->lock, iflags);
1720         return retval;
1721 }
1722
1723 /**
1724  * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1725  *                              It is called by gadget driver
1726  * @usbep:      Reference to the USB endpoint structure
1727  * @usbreq:     Reference to the USB request
1728  *
1729  * Return codes:
1730  *      0:                      Success
1731  *      linux error number:     Failure
1732  */
1733 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1734                                 struct usb_request *usbreq)
1735 {
1736         struct pch_udc_ep       *ep;
1737         struct pch_udc_request  *req;
1738         struct pch_udc_dev      *dev;
1739         unsigned long           flags;
1740         int ret = -EINVAL;
1741
1742         ep = container_of(usbep, struct pch_udc_ep, ep);
1743         dev = ep->dev;
1744         if (!usbep || !usbreq || (!ep->desc && ep->num))
1745                 return ret;
1746         req = container_of(usbreq, struct pch_udc_request, req);
1747         spin_lock_irqsave(&ep->dev->lock, flags);
1748         /* make sure it's still queued on this endpoint */
1749         list_for_each_entry(req, &ep->queue, queue) {
1750                 if (&req->req == usbreq) {
1751                         pch_udc_ep_set_nak(ep);
1752                         if (!list_empty(&req->queue))
1753                                 complete_req(ep, req, -ECONNRESET);
1754                         ret = 0;
1755                         break;
1756                 }
1757         }
1758         spin_unlock_irqrestore(&ep->dev->lock, flags);
1759         return ret;
1760 }
1761
1762 /**
1763  * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1764  *                          feature
1765  * @usbep:      Reference to the USB endpoint structure
1766  * @halt:       Specifies whether to set or clear the feature
1767  *
1768  * Return codes:
1769  *      0:                      Success
1770  *      linux error number:     Failure
1771  */
1772 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1773 {
1774         struct pch_udc_ep       *ep;
1775         struct pch_udc_dev      *dev;
1776         unsigned long iflags;
1777         int ret;
1778
1779         if (!usbep)
1780                 return -EINVAL;
1781         ep = container_of(usbep, struct pch_udc_ep, ep);
1782         dev = ep->dev;
1783         if (!ep->desc && !ep->num)
1784                 return -EINVAL;
1785         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1786                 return -ESHUTDOWN;
1787         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1788         if (list_empty(&ep->queue)) {
1789                 if (halt) {
1790                         if (ep->num == PCH_UDC_EP0)
1791                                 ep->dev->stall = 1;
1792                         pch_udc_ep_set_stall(ep);
1793                         pch_udc_enable_ep_interrupts(ep->dev,
1794                                                      PCH_UDC_EPINT(ep->in,
1795                                                                    ep->num));
1796                 } else {
1797                         pch_udc_ep_clear_stall(ep);
1798                 }
1799                 ret = 0;
1800         } else {
1801                 ret = -EAGAIN;
1802         }
1803         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1804         return ret;
1805 }
1806
1807 /**
1808  * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1809  *                              halt feature
1810  * @usbep:      Reference to the USB endpoint structure
1811  * @halt:       Specifies whether to set or clear the feature
1812  *
1813  * Return codes:
1814  *      0:                      Success
1815  *      linux error number:     Failure
1816  */
1817 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1818 {
1819         struct pch_udc_ep       *ep;
1820         struct pch_udc_dev      *dev;
1821         unsigned long iflags;
1822         int ret;
1823
1824         if (!usbep)
1825                 return -EINVAL;
1826         ep = container_of(usbep, struct pch_udc_ep, ep);
1827         dev = ep->dev;
1828         if (!ep->desc && !ep->num)
1829                 return -EINVAL;
1830         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1831                 return -ESHUTDOWN;
1832         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1833         if (!list_empty(&ep->queue)) {
1834                 ret = -EAGAIN;
1835         } else {
1836                 if (ep->num == PCH_UDC_EP0)
1837                         ep->dev->stall = 1;
1838                 pch_udc_ep_set_stall(ep);
1839                 pch_udc_enable_ep_interrupts(ep->dev,
1840                                              PCH_UDC_EPINT(ep->in, ep->num));
1841                 ep->dev->prot_stall = 1;
1842                 ret = 0;
1843         }
1844         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1845         return ret;
1846 }
1847
1848 /**
1849  * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1850  * @usbep:      Reference to the USB endpoint structure
1851  */
1852 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1853 {
1854         struct pch_udc_ep  *ep;
1855
1856         if (!usbep)
1857                 return;
1858
1859         ep = container_of(usbep, struct pch_udc_ep, ep);
1860         if (ep->desc || !ep->num)
1861                 pch_udc_ep_fifo_flush(ep, ep->in);
1862 }
1863
1864 static const struct usb_ep_ops pch_udc_ep_ops = {
1865         .enable         = pch_udc_pcd_ep_enable,
1866         .disable        = pch_udc_pcd_ep_disable,
1867         .alloc_request  = pch_udc_alloc_request,
1868         .free_request   = pch_udc_free_request,
1869         .queue          = pch_udc_pcd_queue,
1870         .dequeue        = pch_udc_pcd_dequeue,
1871         .set_halt       = pch_udc_pcd_set_halt,
1872         .set_wedge      = pch_udc_pcd_set_wedge,
1873         .fifo_status    = NULL,
1874         .fifo_flush     = pch_udc_pcd_fifo_flush,
1875 };
1876
1877 /**
1878  * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1879  * @td_stp:     Reference to the SETP buffer structure
1880  */
1881 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
1882 {
1883         static u32      pky_marker;
1884
1885         if (!td_stp)
1886                 return;
1887         td_stp->reserved = ++pky_marker;
1888         memset(&td_stp->request, 0xFF, sizeof td_stp->request);
1889         td_stp->status = PCH_UDC_BS_HST_RDY;
1890 }
1891
1892 /**
1893  * pch_udc_start_next_txrequest() - This function starts
1894  *                                      the next transmission requirement
1895  * @ep: Reference to the endpoint structure
1896  */
1897 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
1898 {
1899         struct pch_udc_request *req;
1900         struct pch_udc_data_dma_desc *td_data;
1901
1902         if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
1903                 return;
1904
1905         if (list_empty(&ep->queue))
1906                 return;
1907
1908         /* next request */
1909         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1910         if (req->dma_going)
1911                 return;
1912         if (!req->td_data)
1913                 return;
1914         pch_udc_wait_ep_stall(ep);
1915         req->dma_going = 1;
1916         pch_udc_ep_set_ddptr(ep, 0);
1917         td_data = req->td_data;
1918         while (1) {
1919                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1920                                    PCH_UDC_BS_HST_RDY;
1921                 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1922                         break;
1923                 td_data = phys_to_virt(td_data->next);
1924         }
1925         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1926         pch_udc_set_dma(ep->dev, DMA_DIR_TX);
1927         pch_udc_ep_set_pd(ep);
1928         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1929         pch_udc_ep_clear_nak(ep);
1930 }
1931
1932 /**
1933  * pch_udc_complete_transfer() - This function completes a transfer
1934  * @ep:         Reference to the endpoint structure
1935  */
1936 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
1937 {
1938         struct pch_udc_request *req;
1939         struct pch_udc_dev *dev = ep->dev;
1940
1941         if (list_empty(&ep->queue))
1942                 return;
1943         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1944         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1945             PCH_UDC_BS_DMA_DONE)
1946                 return;
1947         if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1948              PCH_UDC_RTS_SUCC) {
1949                 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1950                         "epstatus=0x%08x\n",
1951                        (req->td_data_last->status & PCH_UDC_RXTX_STS),
1952                        (int)(ep->epsts));
1953                 return;
1954         }
1955
1956         req->req.actual = req->req.length;
1957         req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1958         req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1959         complete_req(ep, req, 0);
1960         req->dma_going = 0;
1961         if (!list_empty(&ep->queue)) {
1962                 pch_udc_wait_ep_stall(ep);
1963                 pch_udc_ep_clear_nak(ep);
1964                 pch_udc_enable_ep_interrupts(ep->dev,
1965                                              PCH_UDC_EPINT(ep->in, ep->num));
1966         } else {
1967                 pch_udc_disable_ep_interrupts(ep->dev,
1968                                               PCH_UDC_EPINT(ep->in, ep->num));
1969         }
1970 }
1971
1972 /**
1973  * pch_udc_complete_receiver() - This function completes a receiver
1974  * @ep:         Reference to the endpoint structure
1975  */
1976 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1977 {
1978         struct pch_udc_request *req;
1979         struct pch_udc_dev *dev = ep->dev;
1980         unsigned int count;
1981         struct pch_udc_data_dma_desc *td;
1982         dma_addr_t addr;
1983
1984         if (list_empty(&ep->queue))
1985                 return;
1986         /* next request */
1987         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1988         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1989         pch_udc_ep_set_ddptr(ep, 0);
1990         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
1991             PCH_UDC_BS_DMA_DONE)
1992                 td = req->td_data_last;
1993         else
1994                 td = req->td_data;
1995
1996         while (1) {
1997                 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
1998                         dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
1999                                 "epstatus=0x%08x\n",
2000                                 (req->td_data->status & PCH_UDC_RXTX_STS),
2001                                 (int)(ep->epsts));
2002                         return;
2003                 }
2004                 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2005                         if (td->status | PCH_UDC_DMA_LAST) {
2006                                 count = td->status & PCH_UDC_RXTX_BYTES;
2007                                 break;
2008                         }
2009                 if (td == req->td_data_last) {
2010                         dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2011                         return;
2012                 }
2013                 addr = (dma_addr_t)td->next;
2014                 td = phys_to_virt(addr);
2015         }
2016         /* on 64k packets the RXBYTES field is zero */
2017         if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2018                 count = UDC_DMA_MAXPACKET;
2019         req->td_data->status |= PCH_UDC_DMA_LAST;
2020         td->status |= PCH_UDC_BS_HST_BSY;
2021
2022         req->dma_going = 0;
2023         req->req.actual = count;
2024         complete_req(ep, req, 0);
2025         /* If there is a new/failed requests try that now */
2026         if (!list_empty(&ep->queue)) {
2027                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2028                 pch_udc_start_rxrequest(ep, req);
2029         }
2030 }
2031
2032 /**
2033  * pch_udc_svc_data_in() - This function process endpoint interrupts
2034  *                              for IN endpoints
2035  * @dev:        Reference to the device structure
2036  * @ep_num:     Endpoint that generated the interrupt
2037  */
2038 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2039 {
2040         u32     epsts;
2041         struct pch_udc_ep       *ep;
2042
2043         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2044         epsts = ep->epsts;
2045         ep->epsts = 0;
2046
2047         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA  | UDC_EPSTS_HE |
2048                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2049                        UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2050                 return;
2051         if ((epsts & UDC_EPSTS_BNA))
2052                 return;
2053         if (epsts & UDC_EPSTS_HE)
2054                 return;
2055         if (epsts & UDC_EPSTS_RSS) {
2056                 pch_udc_ep_set_stall(ep);
2057                 pch_udc_enable_ep_interrupts(ep->dev,
2058                                              PCH_UDC_EPINT(ep->in, ep->num));
2059         }
2060         if (epsts & UDC_EPSTS_RCS) {
2061                 if (!dev->prot_stall) {
2062                         pch_udc_ep_clear_stall(ep);
2063                 } else {
2064                         pch_udc_ep_set_stall(ep);
2065                         pch_udc_enable_ep_interrupts(ep->dev,
2066                                                 PCH_UDC_EPINT(ep->in, ep->num));
2067                 }
2068         }
2069         if (epsts & UDC_EPSTS_TDC)
2070                 pch_udc_complete_transfer(ep);
2071         /* On IN interrupt, provide data if we have any */
2072         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2073             !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2074                 pch_udc_start_next_txrequest(ep);
2075 }
2076
2077 /**
2078  * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2079  * @dev:        Reference to the device structure
2080  * @ep_num:     Endpoint that generated the interrupt
2081  */
2082 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2083 {
2084         u32                     epsts;
2085         struct pch_udc_ep               *ep;
2086         struct pch_udc_request          *req = NULL;
2087
2088         ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2089         epsts = ep->epsts;
2090         ep->epsts = 0;
2091
2092         if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2093                 /* next request */
2094                 req = list_entry(ep->queue.next, struct pch_udc_request,
2095                                  queue);
2096                 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2097                      PCH_UDC_BS_DMA_DONE) {
2098                         if (!req->dma_going)
2099                                 pch_udc_start_rxrequest(ep, req);
2100                         return;
2101                 }
2102         }
2103         if (epsts & UDC_EPSTS_HE)
2104                 return;
2105         if (epsts & UDC_EPSTS_RSS) {
2106                 pch_udc_ep_set_stall(ep);
2107                 pch_udc_enable_ep_interrupts(ep->dev,
2108                                              PCH_UDC_EPINT(ep->in, ep->num));
2109         }
2110         if (epsts & UDC_EPSTS_RCS) {
2111                 if (!dev->prot_stall) {
2112                         pch_udc_ep_clear_stall(ep);
2113                 } else {
2114                         pch_udc_ep_set_stall(ep);
2115                         pch_udc_enable_ep_interrupts(ep->dev,
2116                                                 PCH_UDC_EPINT(ep->in, ep->num));
2117                 }
2118         }
2119         if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2120             UDC_EPSTS_OUT_DATA) {
2121                 if (ep->dev->prot_stall == 1) {
2122                         pch_udc_ep_set_stall(ep);
2123                         pch_udc_enable_ep_interrupts(ep->dev,
2124                                                 PCH_UDC_EPINT(ep->in, ep->num));
2125                 } else {
2126                         pch_udc_complete_receiver(ep);
2127                 }
2128         }
2129         if (list_empty(&ep->queue))
2130                 pch_udc_set_dma(dev, DMA_DIR_RX);
2131 }
2132
2133 /**
2134  * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2135  * @dev:        Reference to the device structure
2136  */
2137 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2138 {
2139         u32     epsts;
2140         struct pch_udc_ep       *ep;
2141         struct pch_udc_ep       *ep_out;
2142
2143         ep = &dev->ep[UDC_EP0IN_IDX];
2144         ep_out = &dev->ep[UDC_EP0OUT_IDX];
2145         epsts = ep->epsts;
2146         ep->epsts = 0;
2147
2148         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2149                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2150                        UDC_EPSTS_XFERDONE)))
2151                 return;
2152         if ((epsts & UDC_EPSTS_BNA))
2153                 return;
2154         if (epsts & UDC_EPSTS_HE)
2155                 return;
2156         if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2157                 pch_udc_complete_transfer(ep);
2158                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2159                 ep_out->td_data->status = (ep_out->td_data->status &
2160                                         ~PCH_UDC_BUFF_STS) |
2161                                         PCH_UDC_BS_HST_RDY;
2162                 pch_udc_ep_clear_nak(ep_out);
2163                 pch_udc_set_dma(dev, DMA_DIR_RX);
2164                 pch_udc_ep_set_rrdy(ep_out);
2165         }
2166         /* On IN interrupt, provide data if we have any */
2167         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2168              !(epsts & UDC_EPSTS_TXEMPTY))
2169                 pch_udc_start_next_txrequest(ep);
2170 }
2171
2172 /**
2173  * pch_udc_svc_control_out() - Routine that handle Control
2174  *                                      OUT endpoint interrupts
2175  * @dev:        Reference to the device structure
2176  */
2177 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2178 {
2179         u32     stat;
2180         int setup_supported;
2181         struct pch_udc_ep       *ep;
2182
2183         ep = &dev->ep[UDC_EP0OUT_IDX];
2184         stat = ep->epsts;
2185         ep->epsts = 0;
2186
2187         /* If setup data */
2188         if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2189             UDC_EPSTS_OUT_SETUP) {
2190                 dev->stall = 0;
2191                 dev->ep[UDC_EP0IN_IDX].halted = 0;
2192                 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2193                 dev->setup_data = ep->td_stp->request;
2194                 pch_udc_init_setup_buff(ep->td_stp);
2195                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2196                 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2197                                       dev->ep[UDC_EP0IN_IDX].in);
2198                 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2199                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2200                 else /* OUT */
2201                         dev->gadget.ep0 = &ep->ep;
2202                 spin_unlock(&dev->lock);
2203                 /* If Mass storage Reset */
2204                 if ((dev->setup_data.bRequestType == 0x21) &&
2205                     (dev->setup_data.bRequest == 0xFF))
2206                         dev->prot_stall = 0;
2207                 /* call gadget with setup data received */
2208                 setup_supported = dev->driver->setup(&dev->gadget,
2209                                                      &dev->setup_data);
2210                 spin_lock(&dev->lock);
2211
2212                 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2213                         ep->td_data->status = (ep->td_data->status &
2214                                                 ~PCH_UDC_BUFF_STS) |
2215                                                 PCH_UDC_BS_HST_RDY;
2216                         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2217                 }
2218                 /* ep0 in returns data on IN phase */
2219                 if (setup_supported >= 0 && setup_supported <
2220                                             UDC_EP0IN_MAX_PKT_SIZE) {
2221                         pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2222                         /* Gadget would have queued a request when
2223                          * we called the setup */
2224                         if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2225                                 pch_udc_set_dma(dev, DMA_DIR_RX);
2226                                 pch_udc_ep_clear_nak(ep);
2227                         }
2228                 } else if (setup_supported < 0) {
2229                         /* if unsupported request, then stall */
2230                         pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2231                         pch_udc_enable_ep_interrupts(ep->dev,
2232                                                 PCH_UDC_EPINT(ep->in, ep->num));
2233                         dev->stall = 0;
2234                         pch_udc_set_dma(dev, DMA_DIR_RX);
2235                 } else {
2236                         dev->waiting_zlp_ack = 1;
2237                 }
2238         } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2239                      UDC_EPSTS_OUT_DATA) && !dev->stall) {
2240                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2241                 pch_udc_ep_set_ddptr(ep, 0);
2242                 if (!list_empty(&ep->queue)) {
2243                         ep->epsts = stat;
2244                         pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2245                 }
2246                 pch_udc_set_dma(dev, DMA_DIR_RX);
2247         }
2248         pch_udc_ep_set_rrdy(ep);
2249 }
2250
2251
2252 /**
2253  * pch_udc_postsvc_epinters() - This function enables end point interrupts
2254  *                              and clears NAK status
2255  * @dev:        Reference to the device structure
2256  * @ep_num:     End point number
2257  */
2258 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2259 {
2260         struct pch_udc_ep       *ep;
2261         struct pch_udc_request *req;
2262
2263         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2264         if (!list_empty(&ep->queue)) {
2265                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2266                 pch_udc_enable_ep_interrupts(ep->dev,
2267                                              PCH_UDC_EPINT(ep->in, ep->num));
2268                 pch_udc_ep_clear_nak(ep);
2269         }
2270 }
2271
2272 /**
2273  * pch_udc_read_all_epstatus() - This function read all endpoint status
2274  * @dev:        Reference to the device structure
2275  * @ep_intr:    Status of endpoint interrupt
2276  */
2277 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2278 {
2279         int i;
2280         struct pch_udc_ep       *ep;
2281
2282         for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2283                 /* IN */
2284                 if (ep_intr & (0x1 << i)) {
2285                         ep = &dev->ep[UDC_EPIN_IDX(i)];
2286                         ep->epsts = pch_udc_read_ep_status(ep);
2287                         pch_udc_clear_ep_status(ep, ep->epsts);
2288                 }
2289                 /* OUT */
2290                 if (ep_intr & (0x10000 << i)) {
2291                         ep = &dev->ep[UDC_EPOUT_IDX(i)];
2292                         ep->epsts = pch_udc_read_ep_status(ep);
2293                         pch_udc_clear_ep_status(ep, ep->epsts);
2294                 }
2295         }
2296 }
2297
2298 /**
2299  * pch_udc_activate_control_ep() - This function enables the control endpoints
2300  *                                      for traffic after a reset
2301  * @dev:        Reference to the device structure
2302  */
2303 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2304 {
2305         struct pch_udc_ep       *ep;
2306         u32 val;
2307
2308         /* Setup the IN endpoint */
2309         ep = &dev->ep[UDC_EP0IN_IDX];
2310         pch_udc_clear_ep_control(ep);
2311         pch_udc_ep_fifo_flush(ep, ep->in);
2312         pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2313         pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2314         /* Initialize the IN EP Descriptor */
2315         ep->td_data      = NULL;
2316         ep->td_stp       = NULL;
2317         ep->td_data_phys = 0;
2318         ep->td_stp_phys  = 0;
2319
2320         /* Setup the OUT endpoint */
2321         ep = &dev->ep[UDC_EP0OUT_IDX];
2322         pch_udc_clear_ep_control(ep);
2323         pch_udc_ep_fifo_flush(ep, ep->in);
2324         pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2325         pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2326         val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2327         pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2328
2329         /* Initialize the SETUP buffer */
2330         pch_udc_init_setup_buff(ep->td_stp);
2331         /* Write the pointer address of dma descriptor */
2332         pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2333         /* Write the pointer address of Setup descriptor */
2334         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2335
2336         /* Initialize the dma descriptor */
2337         ep->td_data->status  = PCH_UDC_DMA_LAST;
2338         ep->td_data->dataptr = dev->dma_addr;
2339         ep->td_data->next    = ep->td_data_phys;
2340
2341         pch_udc_ep_clear_nak(ep);
2342 }
2343
2344
2345 /**
2346  * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2347  * @dev:        Reference to driver structure
2348  */
2349 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2350 {
2351         struct pch_udc_ep       *ep;
2352         int i;
2353
2354         pch_udc_clear_dma(dev, DMA_DIR_TX);
2355         pch_udc_clear_dma(dev, DMA_DIR_RX);
2356         /* Mask all endpoint interrupts */
2357         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2358         /* clear all endpoint interrupts */
2359         pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2360
2361         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2362                 ep = &dev->ep[i];
2363                 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2364                 pch_udc_clear_ep_control(ep);
2365                 pch_udc_ep_set_ddptr(ep, 0);
2366                 pch_udc_write_csr(ep->dev, 0x00, i);
2367         }
2368         dev->stall = 0;
2369         dev->prot_stall = 0;
2370         dev->waiting_zlp_ack = 0;
2371         dev->set_cfg_not_acked = 0;
2372
2373         /* disable ep to empty req queue. Skip the control EP's */
2374         for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2375                 ep = &dev->ep[i];
2376                 pch_udc_ep_set_nak(ep);
2377                 pch_udc_ep_fifo_flush(ep, ep->in);
2378                 /* Complete request queue */
2379                 empty_req_queue(ep);
2380         }
2381         if (dev->driver && dev->driver->disconnect) {
2382                 spin_unlock(&dev->lock);
2383                 dev->driver->disconnect(&dev->gadget);
2384                 spin_lock(&dev->lock);
2385         }
2386 }
2387
2388 /**
2389  * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2390  *                              done interrupt
2391  * @dev:        Reference to driver structure
2392  */
2393 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2394 {
2395         u32 dev_stat, dev_speed;
2396         u32 speed = USB_SPEED_FULL;
2397
2398         dev_stat = pch_udc_read_device_status(dev);
2399         dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2400                                                  UDC_DEVSTS_ENUM_SPEED_SHIFT;
2401         switch (dev_speed) {
2402         case UDC_DEVSTS_ENUM_SPEED_HIGH:
2403                 speed = USB_SPEED_HIGH;
2404                 break;
2405         case  UDC_DEVSTS_ENUM_SPEED_FULL:
2406                 speed = USB_SPEED_FULL;
2407                 break;
2408         case  UDC_DEVSTS_ENUM_SPEED_LOW:
2409                 speed = USB_SPEED_LOW;
2410                 break;
2411         default:
2412                 BUG();
2413         }
2414         dev->gadget.speed = speed;
2415         pch_udc_activate_control_ep(dev);
2416         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2417         pch_udc_set_dma(dev, DMA_DIR_TX);
2418         pch_udc_set_dma(dev, DMA_DIR_RX);
2419         pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2420
2421         /* enable device interrupts */
2422         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2423                                         UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2424                                         UDC_DEVINT_SI | UDC_DEVINT_SC);
2425 }
2426
2427 /**
2428  * pch_udc_svc_intf_interrupt() - This function handles a set interface
2429  *                                interrupt
2430  * @dev:        Reference to driver structure
2431  */
2432 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2433 {
2434         u32 reg, dev_stat = 0;
2435         int i, ret;
2436
2437         dev_stat = pch_udc_read_device_status(dev);
2438         dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2439                                                          UDC_DEVSTS_INTF_SHIFT;
2440         dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2441                                                          UDC_DEVSTS_ALT_SHIFT;
2442         dev->set_cfg_not_acked = 1;
2443         /* Construct the usb request for gadget driver and inform it */
2444         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2445         dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2446         dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2447         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2448         dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2449         /* programm the Endpoint Cfg registers */
2450         /* Only one end point cfg register */
2451         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2452         reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2453               (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2454         reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2455               (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2456         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2457         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2458                 /* clear stall bits */
2459                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2460                 dev->ep[i].halted = 0;
2461         }
2462         dev->stall = 0;
2463         spin_unlock(&dev->lock);
2464         ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2465         spin_lock(&dev->lock);
2466 }
2467
2468 /**
2469  * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2470  *                              interrupt
2471  * @dev:        Reference to driver structure
2472  */
2473 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2474 {
2475         int i, ret;
2476         u32 reg, dev_stat = 0;
2477
2478         dev_stat = pch_udc_read_device_status(dev);
2479         dev->set_cfg_not_acked = 1;
2480         dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2481                                 UDC_DEVSTS_CFG_SHIFT;
2482         /* make usb request for gadget driver */
2483         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2484         dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2485         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2486         /* program the NE registers */
2487         /* Only one end point cfg register */
2488         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2489         reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2490               (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2491         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2492         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2493                 /* clear stall bits */
2494                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2495                 dev->ep[i].halted = 0;
2496         }
2497         dev->stall = 0;
2498
2499         /* call gadget zero with setup data received */
2500         spin_unlock(&dev->lock);
2501         ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2502         spin_lock(&dev->lock);
2503 }
2504
2505 /**
2506  * pch_udc_dev_isr() - This function services device interrupts
2507  *                      by invoking appropriate routines.
2508  * @dev:        Reference to the device structure
2509  * @dev_intr:   The Device interrupt status.
2510  */
2511 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2512 {
2513         /* USB Reset Interrupt */
2514         if (dev_intr & UDC_DEVINT_UR)
2515                 pch_udc_svc_ur_interrupt(dev);
2516         /* Enumeration Done Interrupt */
2517         if (dev_intr & UDC_DEVINT_ENUM)
2518                 pch_udc_svc_enum_interrupt(dev);
2519         /* Set Interface Interrupt */
2520         if (dev_intr & UDC_DEVINT_SI)
2521                 pch_udc_svc_intf_interrupt(dev);
2522         /* Set Config Interrupt */
2523         if (dev_intr & UDC_DEVINT_SC)
2524                 pch_udc_svc_cfg_interrupt(dev);
2525         /* USB Suspend interrupt */
2526         if (dev_intr & UDC_DEVINT_US) {
2527                 if (dev->driver
2528                         && dev->driver->suspend) {
2529                         spin_unlock(&dev->lock);
2530                         dev->driver->suspend(&dev->gadget);
2531                         spin_lock(&dev->lock);
2532                 }
2533
2534                 if (dev->vbus_session == 0) {
2535                         if (dev->driver && dev->driver->disconnect) {
2536                                 spin_unlock(&dev->lock);
2537                                 dev->driver->disconnect(&dev->gadget);
2538                                 spin_lock(&dev->lock);
2539                         }
2540                         pch_udc_reconnect(dev);
2541                 }
2542                 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2543         }
2544         /* Clear the SOF interrupt, if enabled */
2545         if (dev_intr & UDC_DEVINT_SOF)
2546                 dev_dbg(&dev->pdev->dev, "SOF\n");
2547         /* ES interrupt, IDLE > 3ms on the USB */
2548         if (dev_intr & UDC_DEVINT_ES)
2549                 dev_dbg(&dev->pdev->dev, "ES\n");
2550         /* RWKP interrupt */
2551         if (dev_intr & UDC_DEVINT_RWKP)
2552                 dev_dbg(&dev->pdev->dev, "RWKP\n");
2553 }
2554
2555 /**
2556  * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2557  * @irq:        Interrupt request number
2558  * @dev:        Reference to the device structure
2559  */
2560 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2561 {
2562         struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2563         u32 dev_intr, ep_intr;
2564         int i;
2565
2566         dev_intr = pch_udc_read_device_interrupts(dev);
2567         ep_intr = pch_udc_read_ep_interrupts(dev);
2568
2569         /* For a hot plug, this find that the controller is hung up. */
2570         if (dev_intr == ep_intr)
2571                 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2572                         dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2573                         /* The controller is reset */
2574                         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2575                         return IRQ_HANDLED;
2576                 }
2577         if (dev_intr)
2578                 /* Clear device interrupts */
2579                 pch_udc_write_device_interrupts(dev, dev_intr);
2580         if (ep_intr)
2581                 /* Clear ep interrupts */
2582                 pch_udc_write_ep_interrupts(dev, ep_intr);
2583         if (!dev_intr && !ep_intr)
2584                 return IRQ_NONE;
2585         spin_lock(&dev->lock);
2586         if (dev_intr)
2587                 pch_udc_dev_isr(dev, dev_intr);
2588         if (ep_intr) {
2589                 pch_udc_read_all_epstatus(dev, ep_intr);
2590                 /* Process Control In interrupts, if present */
2591                 if (ep_intr & UDC_EPINT_IN_EP0) {
2592                         pch_udc_svc_control_in(dev);
2593                         pch_udc_postsvc_epinters(dev, 0);
2594                 }
2595                 /* Process Control Out interrupts, if present */
2596                 if (ep_intr & UDC_EPINT_OUT_EP0)
2597                         pch_udc_svc_control_out(dev);
2598                 /* Process data in end point interrupts */
2599                 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2600                         if (ep_intr & (1 <<  i)) {
2601                                 pch_udc_svc_data_in(dev, i);
2602                                 pch_udc_postsvc_epinters(dev, i);
2603                         }
2604                 }
2605                 /* Process data out end point interrupts */
2606                 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2607                                                  PCH_UDC_USED_EP_NUM); i++)
2608                         if (ep_intr & (1 <<  i))
2609                                 pch_udc_svc_data_out(dev, i -
2610                                                          UDC_EPINT_OUT_SHIFT);
2611         }
2612         spin_unlock(&dev->lock);
2613         return IRQ_HANDLED;
2614 }
2615
2616 /**
2617  * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2618  * @dev:        Reference to the device structure
2619  */
2620 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2621 {
2622         /* enable ep0 interrupts */
2623         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2624                                                 UDC_EPINT_OUT_EP0);
2625         /* enable device interrupts */
2626         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2627                                        UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2628                                        UDC_DEVINT_SI | UDC_DEVINT_SC);
2629 }
2630
2631 /**
2632  * gadget_release() - Free the gadget driver private data
2633  * @pdev        reference to struct pci_dev
2634  */
2635 static void gadget_release(struct device *pdev)
2636 {
2637         struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2638
2639         kfree(dev);
2640 }
2641
2642 /**
2643  * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2644  * @dev:        Reference to the driver structure
2645  */
2646 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2647 {
2648         const char *const ep_string[] = {
2649                 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2650                 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2651                 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2652                 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2653                 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2654                 "ep15in", "ep15out",
2655         };
2656         int i;
2657
2658         dev->gadget.speed = USB_SPEED_UNKNOWN;
2659         INIT_LIST_HEAD(&dev->gadget.ep_list);
2660
2661         /* Initialize the endpoints structures */
2662         memset(dev->ep, 0, sizeof dev->ep);
2663         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2664                 struct pch_udc_ep *ep = &dev->ep[i];
2665                 ep->dev = dev;
2666                 ep->halted = 1;
2667                 ep->num = i / 2;
2668                 ep->in = ~i & 1;
2669                 ep->ep.name = ep_string[i];
2670                 ep->ep.ops = &pch_udc_ep_ops;
2671                 if (ep->in)
2672                         ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2673                 else
2674                         ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2675                                           UDC_EP_REG_SHIFT;
2676                 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2677                 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2678                 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2679                 INIT_LIST_HEAD(&ep->queue);
2680         }
2681         dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2682         dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2683
2684         /* remove ep0 in and out from the list.  They have own pointer */
2685         list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2686         list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2687
2688         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2689         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2690 }
2691
2692 /**
2693  * pch_udc_pcd_init() - This API initializes the driver structure
2694  * @dev:        Reference to the driver structure
2695  *
2696  * Return codes:
2697  *      0: Success
2698  */
2699 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2700 {
2701         pch_udc_init(dev);
2702         pch_udc_pcd_reinit(dev);
2703         return 0;
2704 }
2705
2706 /**
2707  * init_dma_pools() - create dma pools during initialization
2708  * @pdev:       reference to struct pci_dev
2709  */
2710 static int init_dma_pools(struct pch_udc_dev *dev)
2711 {
2712         struct pch_udc_stp_dma_desc     *td_stp;
2713         struct pch_udc_data_dma_desc    *td_data;
2714
2715         /* DMA setup */
2716         dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2717                 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2718         if (!dev->data_requests) {
2719                 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2720                         __func__);
2721                 return -ENOMEM;
2722         }
2723
2724         /* dma desc for setup data */
2725         dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2726                 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2727         if (!dev->stp_requests) {
2728                 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2729                         __func__);
2730                 return -ENOMEM;
2731         }
2732         /* setup */
2733         td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2734                                 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2735         if (!td_stp) {
2736                 dev_err(&dev->pdev->dev,
2737                         "%s: can't allocate setup dma descriptor\n", __func__);
2738                 return -ENOMEM;
2739         }
2740         dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2741
2742         /* data: 0 packets !? */
2743         td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2744                                 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2745         if (!td_data) {
2746                 dev_err(&dev->pdev->dev,
2747                         "%s: can't allocate data dma descriptor\n", __func__);
2748                 return -ENOMEM;
2749         }
2750         dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2751         dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2752         dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2753         dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2754         dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2755
2756         dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2757         if (!dev->ep0out_buf)
2758                 return -ENOMEM;
2759         dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2760                                        UDC_EP0OUT_BUFF_SIZE * 4,
2761                                        DMA_FROM_DEVICE);
2762         return 0;
2763 }
2764
2765 static int pch_udc_start(struct usb_gadget_driver *driver,
2766         int (*bind)(struct usb_gadget *))
2767 {
2768         struct pch_udc_dev      *dev = pch_udc;
2769         int                     retval;
2770
2771         if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
2772             !driver->setup || !driver->unbind || !driver->disconnect) {
2773                 dev_err(&dev->pdev->dev,
2774                         "%s: invalid driver parameter\n", __func__);
2775                 return -EINVAL;
2776         }
2777
2778         if (!dev)
2779                 return -ENODEV;
2780
2781         if (dev->driver) {
2782                 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2783                 return -EBUSY;
2784         }
2785         driver->driver.bus = NULL;
2786         dev->driver = driver;
2787         dev->gadget.dev.driver = &driver->driver;
2788
2789         /* Invoke the bind routine of the gadget driver */
2790         retval = bind(&dev->gadget);
2791
2792         if (retval) {
2793                 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2794                        __func__, driver->driver.name, retval);
2795                 dev->driver = NULL;
2796                 dev->gadget.dev.driver = NULL;
2797                 return retval;
2798         }
2799         /* get ready for ep0 traffic */
2800         pch_udc_setup_ep0(dev);
2801
2802         /* clear SD */
2803         pch_udc_clear_disconnect(dev);
2804
2805         dev->connected = 1;
2806         return 0;
2807 }
2808
2809 static int pch_udc_stop(struct usb_gadget_driver *driver)
2810 {
2811         struct pch_udc_dev      *dev = pch_udc;
2812
2813         if (!dev)
2814                 return -ENODEV;
2815
2816         if (!driver || (driver != dev->driver)) {
2817                 dev_err(&dev->pdev->dev,
2818                         "%s: invalid driver parameter\n", __func__);
2819                 return -EINVAL;
2820         }
2821
2822         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2823
2824         /* Assures that there are no pending requests with this driver */
2825         driver->disconnect(&dev->gadget);
2826         driver->unbind(&dev->gadget);
2827         dev->gadget.dev.driver = NULL;
2828         dev->driver = NULL;
2829         dev->connected = 0;
2830
2831         /* set SD */
2832         pch_udc_set_disconnect(dev);
2833         return 0;
2834 }
2835
2836 static void pch_udc_shutdown(struct pci_dev *pdev)
2837 {
2838         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2839
2840         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2841         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2842
2843         /* disable the pullup so the host will think we're gone */
2844         pch_udc_set_disconnect(dev);
2845 }
2846
2847 static void pch_udc_remove(struct pci_dev *pdev)
2848 {
2849         struct pch_udc_dev      *dev = pci_get_drvdata(pdev);
2850
2851         usb_del_gadget_udc(&dev->gadget);
2852
2853         /* gadget driver must not be registered */
2854         if (dev->driver)
2855                 dev_err(&pdev->dev,
2856                         "%s: gadget driver still bound!!!\n", __func__);
2857         /* dma pool cleanup */
2858         if (dev->data_requests)
2859                 pci_pool_destroy(dev->data_requests);
2860
2861         if (dev->stp_requests) {
2862                 /* cleanup DMA desc's for ep0in */
2863                 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2864                         pci_pool_free(dev->stp_requests,
2865                                 dev->ep[UDC_EP0OUT_IDX].td_stp,
2866                                 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2867                 }
2868                 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
2869                         pci_pool_free(dev->stp_requests,
2870                                 dev->ep[UDC_EP0OUT_IDX].td_data,
2871                                 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2872                 }
2873                 pci_pool_destroy(dev->stp_requests);
2874         }
2875
2876         if (dev->dma_addr)
2877                 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
2878                                  UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
2879         kfree(dev->ep0out_buf);
2880
2881         pch_udc_exit(dev);
2882
2883         if (dev->irq_registered)
2884                 free_irq(pdev->irq, dev);
2885         if (dev->base_addr)
2886                 iounmap(dev->base_addr);
2887         if (dev->mem_region)
2888                 release_mem_region(dev->phys_addr,
2889                                    pci_resource_len(pdev, PCH_UDC_PCI_BAR));
2890         if (dev->active)
2891                 pci_disable_device(pdev);
2892         if (dev->registered)
2893                 device_unregister(&dev->gadget.dev);
2894         kfree(dev);
2895         pci_set_drvdata(pdev, NULL);
2896 }
2897
2898 #ifdef CONFIG_PM
2899 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
2900 {
2901         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2902
2903         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2904         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2905
2906         pci_disable_device(pdev);
2907         pci_enable_wake(pdev, PCI_D3hot, 0);
2908
2909         if (pci_save_state(pdev)) {
2910                 dev_err(&pdev->dev,
2911                         "%s: could not save PCI config state\n", __func__);
2912                 return -ENOMEM;
2913         }
2914         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2915         return 0;
2916 }
2917
2918 static int pch_udc_resume(struct pci_dev *pdev)
2919 {
2920         int ret;
2921
2922         pci_set_power_state(pdev, PCI_D0);
2923         pci_restore_state(pdev);
2924         ret = pci_enable_device(pdev);
2925         if (ret) {
2926                 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
2927                 return ret;
2928         }
2929         pci_enable_wake(pdev, PCI_D3hot, 0);
2930         return 0;
2931 }
2932 #else
2933 #define pch_udc_suspend NULL
2934 #define pch_udc_resume  NULL
2935 #endif /* CONFIG_PM */
2936
2937 static int pch_udc_probe(struct pci_dev *pdev,
2938                           const struct pci_device_id *id)
2939 {
2940         unsigned long           resource;
2941         unsigned long           len;
2942         int                     retval;
2943         struct pch_udc_dev      *dev;
2944
2945         /* one udc only */
2946         if (pch_udc) {
2947                 pr_err("%s: already probed\n", __func__);
2948                 return -EBUSY;
2949         }
2950         /* init */
2951         dev = kzalloc(sizeof *dev, GFP_KERNEL);
2952         if (!dev) {
2953                 pr_err("%s: no memory for device structure\n", __func__);
2954                 return -ENOMEM;
2955         }
2956         /* pci setup */
2957         if (pci_enable_device(pdev) < 0) {
2958                 kfree(dev);
2959                 pr_err("%s: pci_enable_device failed\n", __func__);
2960                 return -ENODEV;
2961         }
2962         dev->active = 1;
2963         pci_set_drvdata(pdev, dev);
2964
2965         /* PCI resource allocation */
2966         resource = pci_resource_start(pdev, 1);
2967         len = pci_resource_len(pdev, 1);
2968
2969         if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
2970                 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
2971                 retval = -EBUSY;
2972                 goto finished;
2973         }
2974         dev->phys_addr = resource;
2975         dev->mem_region = 1;
2976
2977         dev->base_addr = ioremap_nocache(resource, len);
2978         if (!dev->base_addr) {
2979                 pr_err("%s: device memory cannot be mapped\n", __func__);
2980                 retval = -ENOMEM;
2981                 goto finished;
2982         }
2983         if (!pdev->irq) {
2984                 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
2985                 retval = -ENODEV;
2986                 goto finished;
2987         }
2988         pch_udc = dev;
2989         /* initialize the hardware */
2990         if (pch_udc_pcd_init(dev)) {
2991                 retval = -ENODEV;
2992                 goto finished;
2993         }
2994         if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
2995                         dev)) {
2996                 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
2997                         pdev->irq);
2998                 retval = -ENODEV;
2999                 goto finished;
3000         }
3001         dev->irq = pdev->irq;
3002         dev->irq_registered = 1;
3003
3004         pci_set_master(pdev);
3005         pci_try_set_mwi(pdev);
3006
3007         /* device struct setup */
3008         spin_lock_init(&dev->lock);
3009         dev->pdev = pdev;
3010         dev->gadget.ops = &pch_udc_ops;
3011
3012         retval = init_dma_pools(dev);
3013         if (retval)
3014                 goto finished;
3015
3016         dev_set_name(&dev->gadget.dev, "gadget");
3017         dev->gadget.dev.parent = &pdev->dev;
3018         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3019         dev->gadget.dev.release = gadget_release;
3020         dev->gadget.name = KBUILD_MODNAME;
3021         dev->gadget.is_dualspeed = 1;
3022
3023         retval = device_register(&dev->gadget.dev);
3024         if (retval)
3025                 goto finished;
3026         dev->registered = 1;
3027
3028         /* Put the device in disconnected state till a driver is bound */
3029         pch_udc_set_disconnect(dev);
3030         retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3031         if (retval)
3032                 goto finished;
3033         return 0;
3034
3035 finished:
3036         pch_udc_remove(pdev);
3037         return retval;
3038 }
3039
3040 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
3041         {
3042                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3043                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3044                 .class_mask = 0xffffffff,
3045         },
3046         {
3047                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3048                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3049                 .class_mask = 0xffffffff,
3050         },
3051         {
3052                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3053                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3054                 .class_mask = 0xffffffff,
3055         },
3056         { 0 },
3057 };
3058
3059 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3060
3061
3062 static struct pci_driver pch_udc_driver = {
3063         .name = KBUILD_MODNAME,
3064         .id_table =     pch_udc_pcidev_id,
3065         .probe =        pch_udc_probe,
3066         .remove =       pch_udc_remove,
3067         .suspend =      pch_udc_suspend,
3068         .resume =       pch_udc_resume,
3069         .shutdown =     pch_udc_shutdown,
3070 };
3071
3072 static int __init pch_udc_pci_init(void)
3073 {
3074         return pci_register_driver(&pch_udc_driver);
3075 }
3076 module_init(pch_udc_pci_init);
3077
3078 static void __exit pch_udc_pci_exit(void)
3079 {
3080         pci_unregister_driver(&pch_udc_driver);
3081 }
3082 module_exit(pch_udc_pci_exit);
3083
3084 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3085 MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
3086 MODULE_LICENSE("GPL");