drivers/usb/gadget/pch_udc.c

   1 /*
   2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <linux/list.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/usb/ch9.h>
  26 #include <linux/usb/gadget.h>
  27
  28 /* Address offset of Registers */
  29 #define UDC_EP_REG_SHIFT        0x20    /* Offset to next EP */
  30
  31 #define UDC_EPCTL_ADDR          0x00    /* Endpoint control */
  32 #define UDC_EPSTS_ADDR          0x04    /* Endpoint status */
  33 #define UDC_BUFIN_FRAMENUM_ADDR 0x08    /* buffer size in / frame number out */
  34 #define UDC_BUFOUT_MAXPKT_ADDR  0x0C    /* buffer size out / maxpkt in */
  35 #define UDC_SUBPTR_ADDR         0x10    /* setup buffer pointer */
  36 #define UDC_DESPTR_ADDR         0x14    /* Data descriptor pointer */
  37 #define UDC_CONFIRM_ADDR        0x18    /* Write/Read confirmation */
  38
  39 #define UDC_DEVCFG_ADDR         0x400   /* Device configuration */
  40 #define UDC_DEVCTL_ADDR         0x404   /* Device control */
  41 #define UDC_DEVSTS_ADDR         0x408   /* Device status */
  42 #define UDC_DEVIRQSTS_ADDR      0x40C   /* Device irq status */
  43 #define UDC_DEVIRQMSK_ADDR      0x410   /* Device irq mask */
  44 #define UDC_EPIRQSTS_ADDR       0x414   /* Endpoint irq status */
  45 #define UDC_EPIRQMSK_ADDR       0x418   /* Endpoint irq mask */
  46 #define UDC_DEVLPM_ADDR         0x41C   /* LPM control / status */
  47 #define UDC_CSR_BUSY_ADDR       0x4f0   /* UDC_CSR_BUSY Status register */
  48 #define UDC_SRST_ADDR           0x4fc   /* SOFT RESET register */
  49 #define UDC_CSR_ADDR            0x500   /* USB_DEVICE endpoint register */
  50
  51 /* Endpoint control register */
  52 /* Bit position */
  53 #define UDC_EPCTL_MRXFLUSH              (1 << 12)
  54 #define UDC_EPCTL_RRDY                  (1 << 9)
  55 #define UDC_EPCTL_CNAK                  (1 << 8)
  56 #define UDC_EPCTL_SNAK                  (1 << 7)
  57 #define UDC_EPCTL_NAK                   (1 << 6)
  58 #define UDC_EPCTL_P                     (1 << 3)
  59 #define UDC_EPCTL_F                     (1 << 1)
  60 #define UDC_EPCTL_S                     (1 << 0)
  61 #define UDC_EPCTL_ET_SHIFT              4
  62 /* Mask patern */
  63 #define UDC_EPCTL_ET_MASK               0x00000030
  64 /* Value for ET field */
  65 #define UDC_EPCTL_ET_CONTROL            0
  66 #define UDC_EPCTL_ET_ISO                1
  67 #define UDC_EPCTL_ET_BULK               2
  68 #define UDC_EPCTL_ET_INTERRUPT          3
  69
  70 /* Endpoint status register */
  71 /* Bit position */
  72 #define UDC_EPSTS_XFERDONE              (1 << 27)
  73 #define UDC_EPSTS_RSS                   (1 << 26)
  74 #define UDC_EPSTS_RCS                   (1 << 25)
  75 #define UDC_EPSTS_TXEMPTY               (1 << 24)
  76 #define UDC_EPSTS_TDC                   (1 << 10)
  77 #define UDC_EPSTS_HE                    (1 << 9)
  78 #define UDC_EPSTS_MRXFIFO_EMP           (1 << 8)
  79 #define UDC_EPSTS_BNA                   (1 << 7)
  80 #define UDC_EPSTS_IN                    (1 << 6)
  81 #define UDC_EPSTS_OUT_SHIFT             4
  82 /* Mask patern */
  83 #define UDC_EPSTS_OUT_MASK              0x00000030
  84 #define UDC_EPSTS_ALL_CLR_MASK          0x1F0006F0
  85 /* Value for OUT field */
  86 #define UDC_EPSTS_OUT_SETUP             2
  87 #define UDC_EPSTS_OUT_DATA              1
  88
  89 /* Device configuration register */
  90 /* Bit position */
  91 #define UDC_DEVCFG_CSR_PRG              (1 << 17)
  92 #define UDC_DEVCFG_SP                   (1 << 3)
  93 /* SPD Valee */
  94 #define UDC_DEVCFG_SPD_HS               0x0
  95 #define UDC_DEVCFG_SPD_FS               0x1
  96 #define UDC_DEVCFG_SPD_LS               0x2
  97
  98 /* Device control register */
  99 /* Bit position */
 100 #define UDC_DEVCTL_THLEN_SHIFT          24
 101 #define UDC_DEVCTL_BRLEN_SHIFT          16
 102 #define UDC_DEVCTL_CSR_DONE             (1 << 13)
 103 #define UDC_DEVCTL_SD                   (1 << 10)
 104 #define UDC_DEVCTL_MODE                 (1 << 9)
 105 #define UDC_DEVCTL_BREN                 (1 << 8)
 106 #define UDC_DEVCTL_THE                  (1 << 7)
 107 #define UDC_DEVCTL_DU                   (1 << 4)
 108 #define UDC_DEVCTL_TDE                  (1 << 3)
 109 #define UDC_DEVCTL_RDE                  (1 << 2)
 110 #define UDC_DEVCTL_RES                  (1 << 0)
 111
 112 /* Device status register */
 113 /* Bit position */
 114 #define UDC_DEVSTS_TS_SHIFT             18
 115 #define UDC_DEVSTS_ENUM_SPEED_SHIFT     13
 116 #define UDC_DEVSTS_ALT_SHIFT            8
 117 #define UDC_DEVSTS_INTF_SHIFT           4
 118 #define UDC_DEVSTS_CFG_SHIFT            0
 119 /* Mask patern */
 120 #define UDC_DEVSTS_TS_MASK              0xfffc0000
 121 #define UDC_DEVSTS_ENUM_SPEED_MASK      0x00006000
 122 #define UDC_DEVSTS_ALT_MASK             0x00000f00
 123 #define UDC_DEVSTS_INTF_MASK            0x000000f0
 124 #define UDC_DEVSTS_CFG_MASK             0x0000000f
 125 /* value for maximum speed for SPEED field */
 126 #define UDC_DEVSTS_ENUM_SPEED_FULL      1
 127 #define UDC_DEVSTS_ENUM_SPEED_HIGH      0
 128 #define UDC_DEVSTS_ENUM_SPEED_LOW       2
 129 #define UDC_DEVSTS_ENUM_SPEED_FULLX     3
 130
 131 /* Device irq register */
 132 /* Bit position */
 133 #define UDC_DEVINT_RWKP                 (1 << 7)
 134 #define UDC_DEVINT_ENUM                 (1 << 6)
 135 #define UDC_DEVINT_SOF                  (1 << 5)
 136 #define UDC_DEVINT_US                   (1 << 4)
 137 #define UDC_DEVINT_UR                   (1 << 3)
 138 #define UDC_DEVINT_ES                   (1 << 2)
 139 #define UDC_DEVINT_SI                   (1 << 1)
 140 #define UDC_DEVINT_SC                   (1 << 0)
 141 /* Mask patern */
 142 #define UDC_DEVINT_MSK                  0x7f
 143
 144 /* Endpoint irq register */
 145 /* Bit position */
 146 #define UDC_EPINT_IN_SHIFT              0
 147 #define UDC_EPINT_OUT_SHIFT             16
 148 #define UDC_EPINT_IN_EP0                (1 << 0)
 149 #define UDC_EPINT_OUT_EP0               (1 << 16)
 150 /* Mask patern */
 151 #define UDC_EPINT_MSK_DISABLE_ALL       0xffffffff
 152
 153 /* UDC_CSR_BUSY Status register */
 154 /* Bit position */
 155 #define UDC_CSR_BUSY                    (1 << 0)
 156
 157 /* SOFT RESET register */
 158 /* Bit position */
 159 #define UDC_PSRST                       (1 << 1)
 160 #define UDC_SRST                        (1 << 0)
 161
 162 /* USB_DEVICE endpoint register */
 163 /* Bit position */
 164 #define UDC_CSR_NE_NUM_SHIFT            0
 165 #define UDC_CSR_NE_DIR_SHIFT            4
 166 #define UDC_CSR_NE_TYPE_SHIFT           5
 167 #define UDC_CSR_NE_CFG_SHIFT            7
 168 #define UDC_CSR_NE_INTF_SHIFT           11
 169 #define UDC_CSR_NE_ALT_SHIFT            15
 170 #define UDC_CSR_NE_MAX_PKT_SHIFT        19
 171 /* Mask patern */
 172 #define UDC_CSR_NE_NUM_MASK             0x0000000f
 173 #define UDC_CSR_NE_DIR_MASK             0x00000010
 174 #define UDC_CSR_NE_TYPE_MASK            0x00000060
 175 #define UDC_CSR_NE_CFG_MASK             0x00000780
 176 #define UDC_CSR_NE_INTF_MASK            0x00007800
 177 #define UDC_CSR_NE_ALT_MASK             0x00078000
 178 #define UDC_CSR_NE_MAX_PKT_MASK         0x3ff80000
 179
 180 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
 181 #define PCH_UDC_EPINT(in, num)\
 182                 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
 183
 184 /* Index of endpoint */
 185 #define UDC_EP0IN_IDX           0
 186 #define UDC_EP0OUT_IDX          1
 187 #define UDC_EPIN_IDX(ep)        (ep * 2)
 188 #define UDC_EPOUT_IDX(ep)       (ep * 2 + 1)
 189 #define PCH_UDC_EP0             0
 190 #define PCH_UDC_EP1             1
 191 #define PCH_UDC_EP2             2
 192 #define PCH_UDC_EP3             3
 193
 194 /* Number of endpoint */
 195 #define PCH_UDC_EP_NUM          32      /* Total number of EPs (16 IN,16 OUT) */
 196 #define PCH_UDC_USED_EP_NUM     4       /* EP number of EP's really used */
 197 /* Length Value */
 198 #define PCH_UDC_BRLEN           0x0F    /* Burst length */
 199 #define PCH_UDC_THLEN           0x1F    /* Threshold length */
 200 /* Value of EP Buffer Size */
 201 #define UDC_EP0IN_BUFF_SIZE     16
 202 #define UDC_EPIN_BUFF_SIZE      256
 203 #define UDC_EP0OUT_BUFF_SIZE    16
 204 #define UDC_EPOUT_BUFF_SIZE     256
 205 /* Value of EP maximum packet size */
 206 #define UDC_EP0IN_MAX_PKT_SIZE  64
 207 #define UDC_EP0OUT_MAX_PKT_SIZE 64
 208 #define UDC_BULK_MAX_PKT_SIZE   512
 209
 210 /* DMA */
 211 #define DMA_DIR_RX              1       /* DMA for data receive */
 212 #define DMA_DIR_TX              2       /* DMA for data transmit */
 213 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
 214 #define UDC_DMA_MAXPACKET       65536   /* maximum packet size for DMA */
 215
 216 /**
 217  * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
 218  *                                for data
 219  * @status:             Status quadlet
 220  * @reserved:           Reserved
 221  * @dataptr:            Buffer descriptor
 222  * @next:               Next descriptor
 223  */
 224 struct pch_udc_data_dma_desc {
 225         u32 status;
 226         u32 reserved;
 227         u32 dataptr;
 228         u32 next;
 229 };
 230
 231 /**
 232  * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
 233  *                               for control data
 234  * @status:     Status
 235  * @reserved:   Reserved
 236  * @data12:     First setup word
 237  * @data34:     Second setup word
 238  */
 239 struct pch_udc_stp_dma_desc {
 240         u32 status;
 241         u32 reserved;
 242         struct usb_ctrlrequest request;
 243 } __attribute((packed));
 244
 245 /* DMA status definitions */
 246 /* Buffer status */
 247 #define PCH_UDC_BUFF_STS        0xC0000000
 248 #define PCH_UDC_BS_HST_RDY      0x00000000
 249 #define PCH_UDC_BS_DMA_BSY      0x40000000
 250 #define PCH_UDC_BS_DMA_DONE     0x80000000
 251 #define PCH_UDC_BS_HST_BSY      0xC0000000
 252 /*  Rx/Tx Status */
 253 #define PCH_UDC_RXTX_STS        0x30000000
 254 #define PCH_UDC_RTS_SUCC        0x00000000
 255 #define PCH_UDC_RTS_DESERR      0x10000000
 256 #define PCH_UDC_RTS_BUFERR      0x30000000
 257 /* Last Descriptor Indication */
 258 #define PCH_UDC_DMA_LAST        0x08000000
 259 /* Number of Rx/Tx Bytes Mask */
 260 #define PCH_UDC_RXTX_BYTES      0x0000ffff
 261
 262 /**
 263  * struct pch_udc_cfg_data - Structure to hold current configuration
 264  *                           and interface information
 265  * @cur_cfg:    current configuration in use
 266  * @cur_intf:   current interface in use
 267  * @cur_alt:    current alt interface in use
 268  */
 269 struct pch_udc_cfg_data {
 270         u16 cur_cfg;
 271         u16 cur_intf;
 272         u16 cur_alt;
 273 };
 274
 275 /**
 276  * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
 277  * @ep:                 embedded ep request
 278  * @td_stp_phys:        for setup request
 279  * @td_data_phys:       for data request
 280  * @td_stp:             for setup request
 281  * @td_data:            for data request
 282  * @dev:                reference to device struct
 283  * @offset_addr:        offset address of ep register
 284  * @desc:               for this ep
 285  * @queue:              queue for requests
 286  * @num:                endpoint number
 287  * @in:                 endpoint is IN
 288  * @halted:             endpoint halted?
 289  * @epsts:              Endpoint status
 290  */
 291 struct pch_udc_ep {
 292         struct usb_ep                   ep;
 293         dma_addr_t                      td_stp_phys;
 294         dma_addr_t                      td_data_phys;
 295         struct pch_udc_stp_dma_desc     *td_stp;
 296         struct pch_udc_data_dma_desc    *td_data;
 297         struct pch_udc_dev              *dev;
 298         unsigned long                   offset_addr;
 299         const struct usb_endpoint_descriptor    *desc;
 300         struct list_head                queue;
 301         unsigned                        num:5,
 302                                         in:1,
 303                                         halted:1;
 304         unsigned long                   epsts;
 305 };
 306
 307 /**
 308  * struct pch_udc_dev - Structure holding complete information
 309  *                      of the PCH USB device
 310  * @gadget:             gadget driver data
 311  * @driver:             reference to gadget driver bound
 312  * @pdev:               reference to the PCI device
 313  * @ep:                 array of endpoints
 314  * @lock:               protects all state
 315  * @active:             enabled the PCI device
 316  * @stall:              stall requested
 317  * @prot_stall:         protcol stall requested
 318  * @irq_registered:     irq registered with system
 319  * @mem_region:         device memory mapped
 320  * @registered:         driver regsitered with system
 321  * @suspended:          driver in suspended state
 322  * @connected:          gadget driver associated
 323  * @set_cfg_not_acked:  pending acknowledgement 4 setup
 324  * @waiting_zlp_ack:    pending acknowledgement 4 ZLP
 325  * @data_requests:      DMA pool for data requests
 326  * @stp_requests:       DMA pool for setup requests
 327  * @dma_addr:           DMA pool for received
 328  * @ep0out_buf:         Buffer for DMA
 329  * @setup_data:         Received setup data
 330  * @phys_addr:          of device memory
 331  * @base_addr:          for mapped device memory
 332  * @irq:                IRQ line for the device
 333  * @cfg_data:           current cfg, intf, and alt in use
 334  */
 335 struct pch_udc_dev {
 336         struct usb_gadget               gadget;
 337         struct usb_gadget_driver        *driver;
 338         struct pci_dev                  *pdev;
 339         struct pch_udc_ep               ep[PCH_UDC_EP_NUM];
 340         spinlock_t                      lock; /* protects all state */
 341         unsigned        active:1,
 342                         stall:1,
 343                         prot_stall:1,
 344                         irq_registered:1,
 345                         mem_region:1,
 346                         registered:1,
 347                         suspended:1,
 348                         connected:1,
 349                         set_cfg_not_acked:1,
 350                         waiting_zlp_ack:1;
 351         struct pci_pool         *data_requests;
 352         struct pci_pool         *stp_requests;
 353         dma_addr_t                      dma_addr;
 354         void                            *ep0out_buf;
 355         struct usb_ctrlrequest          setup_data;
 356         unsigned long                   phys_addr;
 357         void __iomem                    *base_addr;
 358         unsigned                        irq;
 359         struct pch_udc_cfg_data cfg_data;
 360 };
 361
 362 #define PCH_UDC_PCI_BAR                 1
 363 #define PCI_DEVICE_ID_INTEL_EG20T_UDC   0x8808
 364 #define PCI_VENDOR_ID_ROHM              0x10DB
 365 #define PCI_DEVICE_ID_ML7213_IOH_UDC    0x801D
 366
 367 static const char       ep0_string[] = "ep0in";
 368 static DEFINE_SPINLOCK(udc_stall_spinlock);     /* stall spin lock */
 369 struct pch_udc_dev *pch_udc;            /* pointer to device object */
 370
 371 static int speed_fs;
 372 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
 373 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
 374
 375 /**
 376  * struct pch_udc_request - Structure holding a PCH USB device request packet
 377  * @req:                embedded ep request
 378  * @td_data_phys:       phys. address
 379  * @td_data:            first dma desc. of chain
 380  * @td_data_last:       last dma desc. of chain
 381  * @queue:              associated queue
 382  * @dma_going:          DMA in progress for request
 383  * @dma_mapped:         DMA memory mapped for request
 384  * @dma_done:           DMA completed for request
 385  * @chain_len:          chain length
 386  */
 387 struct pch_udc_request {
 388         struct usb_request              req;
 389         dma_addr_t                      td_data_phys;
 390         struct pch_udc_data_dma_desc    *td_data;
 391         struct pch_udc_data_dma_desc    *td_data_last;
 392         struct list_head                queue;
 393         unsigned                        dma_going:1,
 394                                         dma_mapped:1,
 395                                         dma_done:1;
 396         unsigned                        chain_len;
 397 };
 398
 399 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
 400 {
 401         return ioread32(dev->base_addr + reg);
 402 }
 403
 404 static inline void pch_udc_writel(struct pch_udc_dev *dev,
 405                                     unsigned long val, unsigned long reg)
 406 {
 407         iowrite32(val, dev->base_addr + reg);
 408 }
 409
 410 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
 411                                      unsigned long reg,
 412                                      unsigned long bitmask)
 413 {
 414         pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
 415 }
 416
 417 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
 418                                      unsigned long reg,
 419                                      unsigned long bitmask)
 420 {
 421         pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
 422 }
 423
 424 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
 425 {
 426         return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
 427 }
 428
 429 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
 430                                     unsigned long val, unsigned long reg)
 431 {
 432         iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
 433 }
 434
 435 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
 436                                      unsigned long reg,
 437                                      unsigned long bitmask)
 438 {
 439         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
 440 }
 441
 442 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
 443                                      unsigned long reg,
 444                                      unsigned long bitmask)
 445 {
 446         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
 447 }
 448
 449 /**
 450  * pch_udc_csr_busy() - Wait till idle.
 451  * @dev:        Reference to pch_udc_dev structure
 452  */
 453 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
 454 {
 455         unsigned int count = 200;
 456
 457         /* Wait till idle */
 458         while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
 459                 && --count)
 460                 cpu_relax();
 461         if (!count)
 462                 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
 463 }
 464
 465 /**
 466  * pch_udc_write_csr() - Write the command and status registers.
 467  * @dev:        Reference to pch_udc_dev structure
 468  * @val:        value to be written to CSR register
 469  * @addr:       address of CSR register
 470  */
 471 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
 472                                unsigned int ep)
 473 {
 474         unsigned long reg = PCH_UDC_CSR(ep);
 475
 476         pch_udc_csr_busy(dev);          /* Wait till idle */
 477         pch_udc_writel(dev, val, reg);
 478         pch_udc_csr_busy(dev);          /* Wait till idle */
 479 }
 480
 481 /**
 482  * pch_udc_read_csr() - Read the command and status registers.
 483  * @dev:        Reference to pch_udc_dev structure
 484  * @addr:       address of CSR register
 485  *
 486  * Return codes:        content of CSR register
 487  */
 488 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
 489 {
 490         unsigned long reg = PCH_UDC_CSR(ep);
 491
 492         pch_udc_csr_busy(dev);          /* Wait till idle */
 493         pch_udc_readl(dev, reg);        /* Dummy read */
 494         pch_udc_csr_busy(dev);          /* Wait till idle */
 495         return pch_udc_readl(dev, reg);
 496 }
 497
 498 /**
 499  * pch_udc_rmt_wakeup() - Initiate for remote wakeup
 500  * @dev:        Reference to pch_udc_dev structure
 501  */
 502 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
 503 {
 504         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 505         mdelay(1);
 506         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 507 }
 508
 509 /**
 510  * pch_udc_get_frame() - Get the current frame from device status register
 511  * @dev:        Reference to pch_udc_dev structure
 512  * Retern       current frame
 513  */
 514 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
 515 {
 516         u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 517         return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
 518 }
 519
 520 /**
 521  * pch_udc_clear_selfpowered() - Clear the self power control
 522  * @dev:        Reference to pch_udc_regs structure
 523  */
 524 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
 525 {
 526         pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 527 }
 528
 529 /**
 530  * pch_udc_set_selfpowered() - Set the self power control
 531  * @dev:        Reference to pch_udc_regs structure
 532  */
 533 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
 534 {
 535         pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 536 }
 537
 538 /**
 539  * pch_udc_set_disconnect() - Set the disconnect status.
 540  * @dev:        Reference to pch_udc_regs structure
 541  */
 542 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
 543 {
 544         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 545 }
 546
 547 /**
 548  * pch_udc_clear_disconnect() - Clear the disconnect status.
 549  * @dev:        Reference to pch_udc_regs structure
 550  */
 551 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
 552 {
 553         /* Clear the disconnect */
 554         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 555         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 556         mdelay(1);
 557         /* Resume USB signalling */
 558         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 559 }
 560
 561 /**
 562  * pch_udc_vbus_session() - set or clearr the disconnect status.
 563  * @dev:        Reference to pch_udc_regs structure
 564  * @is_active:  Parameter specifying the action
 565  *                0:   indicating VBUS power is ending
 566  *                !0:  indicating VBUS power is starting
 567  */
 568 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
 569                                           int is_active)
 570 {
 571         if (is_active)
 572                 pch_udc_clear_disconnect(dev);
 573         else
 574                 pch_udc_set_disconnect(dev);
 575 }
 576
 577 /**
 578  * pch_udc_ep_set_stall() - Set the stall of endpoint
 579  * @ep:         Reference to structure of type pch_udc_ep_regs
 580  */
 581 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
 582 {
 583         if (ep->in) {
 584                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 585                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 586         } else {
 587                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 588         }
 589 }
 590
 591 /**
 592  * pch_udc_ep_clear_stall() - Clear the stall of endpoint
 593  * @ep:         Reference to structure of type pch_udc_ep_regs
 594  */
 595 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
 596 {
 597         /* Clear the stall */
 598         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 599         /* Clear NAK by writing CNAK */
 600         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 601 }
 602
 603 /**
 604  * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
 605  * @ep:         Reference to structure of type pch_udc_ep_regs
 606  * @type:       Type of endpoint
 607  */
 608 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
 609                                         u8 type)
 610 {
 611         pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
 612                                 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
 613 }
 614
 615 /**
 616  * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
 617  * @ep:         Reference to structure of type pch_udc_ep_regs
 618  * @buf_size:   The buffer size
 619  */
 620 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
 621                                                  u32 buf_size, u32 ep_in)
 622 {
 623         u32 data;
 624         if (ep_in) {
 625                 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
 626                 data = (data & 0xffff0000) | (buf_size & 0xffff);
 627                 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
 628         } else {
 629                 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 630                 data = (buf_size << 16) | (data & 0xffff);
 631                 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 632         }
 633 }
 634
 635 /**
 636  * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
 637  * @ep:         Reference to structure of type pch_udc_ep_regs
 638  * @pkt_size:   The packet size
 639  */
 640 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
 641 {
 642         u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 643         data = (data & 0xffff0000) | (pkt_size & 0xffff);
 644         pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 645 }
 646
 647 /**
 648  * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
 649  * @ep:         Reference to structure of type pch_udc_ep_regs
 650  * @addr:       Address of the register
 651  */
 652 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
 653 {
 654         pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
 655 }
 656
 657 /**
 658  * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
 659  * @ep:         Reference to structure of type pch_udc_ep_regs
 660  * @addr:       Address of the register
 661  */
 662 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
 663 {
 664         pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
 665 }
 666
 667 /**
 668  * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
 669  * @ep:         Reference to structure of type pch_udc_ep_regs
 670  */
 671 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
 672 {
 673         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
 674 }
 675
 676 /**
 677  * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
 678  * @ep:         Reference to structure of type pch_udc_ep_regs
 679  */
 680 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
 681 {
 682         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 683 }
 684
 685 /**
 686  * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
 687  * @ep:         Reference to structure of type pch_udc_ep_regs
 688  */
 689 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
 690 {
 691         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 692 }
 693
 694 /**
 695  * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
 696  *                      register depending on the direction specified
 697  * @dev:        Reference to structure of type pch_udc_regs
 698  * @dir:        whether Tx or Rx
 699  *                DMA_DIR_RX: Receive
 700  *                DMA_DIR_TX: Transmit
 701  */
 702 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
 703 {
 704         if (dir == DMA_DIR_RX)
 705                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 706         else if (dir == DMA_DIR_TX)
 707                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 708 }
 709
 710 /**
 711  * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
 712  *                               register depending on the direction specified
 713  * @dev:        Reference to structure of type pch_udc_regs
 714  * @dir:        Whether Tx or Rx
 715  *                DMA_DIR_RX: Receive
 716  *                DMA_DIR_TX: Transmit
 717  */
 718 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
 719 {
 720         if (dir == DMA_DIR_RX)
 721                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 722         else if (dir == DMA_DIR_TX)
 723                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 724 }
 725
 726 /**
 727  * pch_udc_set_csr_done() - Set the device control register
 728  *                              CSR done field (bit 13)
 729  * @dev:        reference to structure of type pch_udc_regs
 730  */
 731 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
 732 {
 733         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
 734 }
 735
 736 /**
 737  * pch_udc_disable_interrupts() - Disables the specified interrupts
 738  * @dev:        Reference to structure of type pch_udc_regs
 739  * @mask:       Mask to disable interrupts
 740  */
 741 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
 742                                             u32 mask)
 743 {
 744         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
 745 }
 746
 747 /**
 748  * pch_udc_enable_interrupts() - Enable the specified interrupts
 749  * @dev:        Reference to structure of type pch_udc_regs
 750  * @mask:       Mask to enable interrupts
 751  */
 752 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
 753                                            u32 mask)
 754 {
 755         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
 756 }
 757
 758 /**
 759  * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
 760  * @dev:        Reference to structure of type pch_udc_regs
 761  * @mask:       Mask to disable interrupts
 762  */
 763 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
 764                                                 u32 mask)
 765 {
 766         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
 767 }
 768
 769 /**
 770  * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
 771  * @dev:        Reference to structure of type pch_udc_regs
 772  * @mask:       Mask to enable interrupts
 773  */
 774 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
 775                                               u32 mask)
 776 {
 777         pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
 778 }
 779
 780 /**
 781  * pch_udc_read_device_interrupts() - Read the device interrupts
 782  * @dev:        Reference to structure of type pch_udc_regs
 783  * Retern       The device interrupts
 784  */
 785 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
 786 {
 787         return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
 788 }
 789
 790 /**
 791  * pch_udc_write_device_interrupts() - Write device interrupts
 792  * @dev:        Reference to structure of type pch_udc_regs
 793  * @val:        The value to be written to interrupt register
 794  */
 795 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
 796                                                      u32 val)
 797 {
 798         pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
 799 }
 800
 801 /**
 802  * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
 803  * @dev:        Reference to structure of type pch_udc_regs
 804  * Retern       The endpoint interrupt
 805  */
 806 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
 807 {
 808         return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
 809 }
 810
 811 /**
 812  * pch_udc_write_ep_interrupts() - Clear endpoint interupts
 813  * @dev:        Reference to structure of type pch_udc_regs
 814  * @val:        The value to be written to interrupt register
 815  */
 816 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
 817                                              u32 val)
 818 {
 819         pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
 820 }
 821
 822 /**
 823  * pch_udc_read_device_status() - Read the device status
 824  * @dev:        Reference to structure of type pch_udc_regs
 825  * Retern       The device status
 826  */
 827 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
 828 {
 829         return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 830 }
 831
 832 /**
 833  * pch_udc_read_ep_control() - Read the endpoint control
 834  * @ep:         Reference to structure of type pch_udc_ep_regs
 835  * Retern       The endpoint control register value
 836  */
 837 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
 838 {
 839         return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
 840 }
 841
 842 /**
 843  * pch_udc_clear_ep_control() - Clear the endpoint control register
 844  * @ep:         Reference to structure of type pch_udc_ep_regs
 845  * Retern       The endpoint control register value
 846  */
 847 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
 848 {
 849         return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
 850 }
 851
 852 /**
 853  * pch_udc_read_ep_status() - Read the endpoint status
 854  * @ep:         Reference to structure of type pch_udc_ep_regs
 855  * Retern       The endpoint status
 856  */
 857 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
 858 {
 859         return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
 860 }
 861
 862 /**
 863  * pch_udc_clear_ep_status() - Clear the endpoint status
 864  * @ep:         Reference to structure of type pch_udc_ep_regs
 865  * @stat:       Endpoint status
 866  */
 867 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
 868                                          u32 stat)
 869 {
 870         return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
 871 }
 872
 873 /**
 874  * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
 875  *                              of the endpoint control register
 876  * @ep:         Reference to structure of type pch_udc_ep_regs
 877  */
 878 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
 879 {
 880         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
 881 }
 882
 883 /**
 884  * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
 885  *                              of the endpoint control register
 886  * @ep:         reference to structure of type pch_udc_ep_regs
 887  */
 888 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
 889 {
 890         unsigned int loopcnt = 0;
 891         struct pch_udc_dev *dev = ep->dev;
 892
 893         if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
 894                 return;
 895         if (!ep->in) {
 896                 loopcnt = 10000;
 897                 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
 898                         --loopcnt)
 899                         udelay(5);
 900                 if (!loopcnt)
 901                         dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
 902                                 __func__);
 903         }
 904         loopcnt = 10000;
 905         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
 906                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 907                 udelay(5);
 908         }
 909         if (!loopcnt)
 910                 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
 911                         __func__, ep->num, (ep->in ? "in" : "out"));
 912 }
 913
 914 /**
 915  * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
 916  * @ep: reference to structure of type pch_udc_ep_regs
 917  * @dir:        direction of endpoint
 918  *                0:  endpoint is OUT
 919  *                !0: endpoint is IN
 920  */
 921 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
 922 {
 923         unsigned int loopcnt = 0;
 924         struct pch_udc_dev *dev = ep->dev;
 925
 926         if (dir) {      /* IN ep */
 927                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 928                 return;
 929         }
 930
 931         if (pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP)
 932                 return;
 933         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_MRXFLUSH);
 934         /* Wait for RxFIFO Empty */
 935         loopcnt = 10000;
 936         while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
 937                 --loopcnt)
 938                 udelay(5);
 939         if (!loopcnt)
 940                 dev_err(&dev->pdev->dev, "RxFIFO not Empty\n");
 941         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_MRXFLUSH);
 942 }
 943
 944 /**
 945  * pch_udc_ep_enable() - This api enables endpoint
 946  * @regs:       Reference to structure pch_udc_ep_regs
 947  * @desc:       endpoint descriptor
 948  */
 949 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
 950                                struct pch_udc_cfg_data *cfg,
 951                                const struct usb_endpoint_descriptor *desc)
 952 {
 953         u32 val = 0;
 954         u32 buff_size = 0;
 955
 956         pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
 957         if (ep->in)
 958                 buff_size = UDC_EPIN_BUFF_SIZE;
 959         else
 960                 buff_size = UDC_EPOUT_BUFF_SIZE;
 961         pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
 962         pch_udc_ep_set_maxpkt(ep, le16_to_cpu(desc->wMaxPacketSize));
 963         pch_udc_ep_set_nak(ep);
 964         pch_udc_ep_fifo_flush(ep, ep->in);
 965         /* Configure the endpoint */
 966         val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
 967               ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
 968                 UDC_CSR_NE_TYPE_SHIFT) |
 969               (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
 970               (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
 971               (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
 972               le16_to_cpu(desc->wMaxPacketSize) << UDC_CSR_NE_MAX_PKT_SHIFT;
 973
 974         if (ep->in)
 975                 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
 976         else
 977                 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
 978 }
 979
 980 /**
 981  * pch_udc_ep_disable() - This api disables endpoint
 982  * @regs:       Reference to structure pch_udc_ep_regs
 983  */
 984 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
 985 {
 986         if (ep->in) {
 987                 /* flush the fifo */
 988                 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
 989                 /* set NAK */
 990                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
 991                 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
 992         } else {
 993                 /* set NAK */
 994                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
 995         }
 996         /* reset desc pointer */
 997         pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
 998 }
 999
1000 /**
1001  * pch_udc_wait_ep_stall() - Wait EP stall.
1002  * @dev:        Reference to pch_udc_dev structure
1003  */
1004 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1005 {
1006         unsigned int count = 10000;
1007
1008         /* Wait till idle */
1009         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1010                 udelay(5);
1011         if (!count)
1012                 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1013 }
1014
1015 /**
1016  * pch_udc_init() - This API initializes usb device controller
1017  * @dev:        Rreference to pch_udc_regs structure
1018  */
1019 static void pch_udc_init(struct pch_udc_dev *dev)
1020 {
1021         if (NULL == dev) {
1022                 pr_err("%s: Invalid address\n", __func__);
1023                 return;
1024         }
1025         /* Soft Reset and Reset PHY */
1026         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1027         pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1028         mdelay(1);
1029         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1030         pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1031         mdelay(1);
1032         /* mask and clear all device interrupts */
1033         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1034         pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1035
1036         /* mask and clear all ep interrupts */
1037         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1038         pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1039
1040         /* enable dynamic CSR programmingi, self powered and device speed */
1041         if (speed_fs)
1042                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1043                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1044         else /* defaul high speed */
1045                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1046                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1047         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1048                         (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1049                         (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1050                         UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1051                         UDC_DEVCTL_THE);
1052 }
1053
1054 /**
1055  * pch_udc_exit() - This API exit usb device controller
1056  * @dev:        Reference to pch_udc_regs structure
1057  */
1058 static void pch_udc_exit(struct pch_udc_dev *dev)
1059 {
1060         /* mask all device interrupts */
1061         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1062         /* mask all ep interrupts */
1063         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1064         /* put device in disconnected state */
1065         pch_udc_set_disconnect(dev);
1066 }
1067
1068 /**
1069  * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1070  * @gadget:     Reference to the gadget driver
1071  *
1072  * Return codes:
1073  *      0:              Success
1074  *      -EINVAL:        If the gadget passed is NULL
1075  */
1076 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1077 {
1078         struct pch_udc_dev      *dev;
1079
1080         if (!gadget)
1081                 return -EINVAL;
1082         dev = container_of(gadget, struct pch_udc_dev, gadget);
1083         return pch_udc_get_frame(dev);
1084 }
1085
1086 /**
1087  * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1088  * @gadget:     Reference to the gadget driver
1089  *
1090  * Return codes:
1091  *      0:              Success
1092  *      -EINVAL:        If the gadget passed is NULL
1093  */
1094 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1095 {
1096         struct pch_udc_dev      *dev;
1097         unsigned long           flags;
1098
1099         if (!gadget)
1100                 return -EINVAL;
1101         dev = container_of(gadget, struct pch_udc_dev, gadget);
1102         spin_lock_irqsave(&dev->lock, flags);
1103         pch_udc_rmt_wakeup(dev);
1104         spin_unlock_irqrestore(&dev->lock, flags);
1105         return 0;
1106 }
1107
1108 /**
1109  * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1110  *                              is self powered or not
1111  * @gadget:     Reference to the gadget driver
1112  * @value:      Specifies self powered or not
1113  *
1114  * Return codes:
1115  *      0:              Success
1116  *      -EINVAL:        If the gadget passed is NULL
1117  */
1118 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1119 {
1120         struct pch_udc_dev      *dev;
1121
1122         if (!gadget)
1123                 return -EINVAL;
1124         dev = container_of(gadget, struct pch_udc_dev, gadget);
1125         if (value)
1126                 pch_udc_set_selfpowered(dev);
1127         else
1128                 pch_udc_clear_selfpowered(dev);
1129         return 0;
1130 }
1131
1132 /**
1133  * pch_udc_pcd_pullup() - This API is invoked to make the device
1134  *                              visible/invisible to the host
1135  * @gadget:     Reference to the gadget driver
1136  * @is_on:      Specifies whether the pull up is made active or inactive
1137  *
1138  * Return codes:
1139  *      0:              Success
1140  *      -EINVAL:        If the gadget passed is NULL
1141  */
1142 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1143 {
1144         struct pch_udc_dev      *dev;
1145
1146         if (!gadget)
1147                 return -EINVAL;
1148         dev = container_of(gadget, struct pch_udc_dev, gadget);
1149         pch_udc_vbus_session(dev, is_on);
1150         return 0;
1151 }
1152
1153 /**
1154  * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1155  *                              transceiver (or GPIO) that
1156  *                              detects a VBUS power session starting/ending
1157  * @gadget:     Reference to the gadget driver
1158  * @is_active:  specifies whether the session is starting or ending
1159  *
1160  * Return codes:
1161  *      0:              Success
1162  *      -EINVAL:        If the gadget passed is NULL
1163  */
1164 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1165 {
1166         struct pch_udc_dev      *dev;
1167
1168         if (!gadget)
1169                 return -EINVAL;
1170         dev = container_of(gadget, struct pch_udc_dev, gadget);
1171         pch_udc_vbus_session(dev, is_active);
1172         return 0;
1173 }
1174
1175 /**
1176  * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1177  *                              SET_CONFIGURATION calls to
1178  *                              specify how much power the device can consume
1179  * @gadget:     Reference to the gadget driver
1180  * @mA:         specifies the current limit in 2mA unit
1181  *
1182  * Return codes:
1183  *      -EINVAL:        If the gadget passed is NULL
1184  *      -EOPNOTSUPP:
1185  */
1186 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1187 {
1188         return -EOPNOTSUPP;
1189 }
1190
1191 static const struct usb_gadget_ops pch_udc_ops = {
1192         .get_frame = pch_udc_pcd_get_frame,
1193         .wakeup = pch_udc_pcd_wakeup,
1194         .set_selfpowered = pch_udc_pcd_selfpowered,
1195         .pullup = pch_udc_pcd_pullup,
1196         .vbus_session = pch_udc_pcd_vbus_session,
1197         .vbus_draw = pch_udc_pcd_vbus_draw,
1198 };
1199
1200 /**
1201  * complete_req() - This API is invoked from the driver when processing
1202  *                      of a request is complete
1203  * @ep:         Reference to the endpoint structure
1204  * @req:        Reference to the request structure
1205  * @status:     Indicates the success/failure of completion
1206  */
1207 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1208                                                                  int status)
1209 {
1210         struct pch_udc_dev      *dev;
1211         unsigned halted = ep->halted;
1212
1213         list_del_init(&req->queue);
1214
1215         /* set new status if pending */
1216         if (req->req.status == -EINPROGRESS)
1217                 req->req.status = status;
1218         else
1219                 status = req->req.status;
1220
1221         dev = ep->dev;
1222         if (req->dma_mapped) {
1223                 if (ep->in)
1224                         dma_unmap_single(&dev->pdev->dev, req->req.dma,
1225                                          req->req.length, DMA_TO_DEVICE);
1226                 else
1227                         dma_unmap_single(&dev->pdev->dev, req->req.dma,
1228                                          req->req.length, DMA_FROM_DEVICE);
1229                 req->dma_mapped = 0;
1230                 req->req.dma = DMA_ADDR_INVALID;
1231         }
1232         ep->halted = 1;
1233         spin_unlock(&dev->lock);
1234         if (!ep->in)
1235                 pch_udc_ep_clear_rrdy(ep);
1236         req->req.complete(&ep->ep, &req->req);
1237         spin_lock(&dev->lock);
1238         ep->halted = halted;
1239 }
1240
1241 /**
1242  * empty_req_queue() - This API empties the request queue of an endpoint
1243  * @ep:         Reference to the endpoint structure
1244  */
1245 static void empty_req_queue(struct pch_udc_ep *ep)
1246 {
1247         struct pch_udc_request  *req;
1248
1249         ep->halted = 1;
1250         while (!list_empty(&ep->queue)) {
1251                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1252                 complete_req(ep, req, -ESHUTDOWN);      /* Remove from list */
1253         }
1254 }
1255
1256 /**
1257  * pch_udc_free_dma_chain() - This function frees the DMA chain created
1258  *                              for the request
1259  * @dev         Reference to the driver structure
1260  * @req         Reference to the request to be freed
1261  *
1262  * Return codes:
1263  *      0: Success
1264  */
1265 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1266                                    struct pch_udc_request *req)
1267 {
1268         struct pch_udc_data_dma_desc *td = req->td_data;
1269         unsigned i = req->chain_len;
1270
1271         for (; i > 1; --i) {
1272                 dma_addr_t addr = (dma_addr_t)td->next;
1273                 /* do not free first desc., will be done by free for request */
1274                 td = phys_to_virt(addr);
1275                 pci_pool_free(dev->data_requests, td, addr);
1276         }
1277 }
1278
1279 /**
1280  * pch_udc_create_dma_chain() - This function creates or reinitializes
1281  *                              a DMA chain
1282  * @ep:         Reference to the endpoint structure
1283  * @req:        Reference to the request
1284  * @buf_len:    The buffer length
1285  * @gfp_flags:  Flags to be used while mapping the data buffer
1286  *
1287  * Return codes:
1288  *      0:              success,
1289  *      -ENOMEM:        pci_pool_alloc invocation fails
1290  */
1291 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1292                                     struct pch_udc_request *req,
1293                                     unsigned long buf_len,
1294                                     gfp_t gfp_flags)
1295 {
1296         struct pch_udc_data_dma_desc *td = req->td_data, *last;
1297         unsigned long bytes = req->req.length, i = 0;
1298         dma_addr_t dma_addr;
1299         unsigned len = 1;
1300
1301         if (req->chain_len > 1)
1302                 pch_udc_free_dma_chain(ep->dev, req);
1303
1304         for (; ; bytes -= buf_len, ++len) {
1305                 if (ep->in)
1306                         td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1307                 else
1308                         td->status = PCH_UDC_BS_HST_BSY;
1309
1310                 if (bytes <= buf_len)
1311                         break;
1312
1313                 last = td;
1314                 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1315                                     &dma_addr);
1316                 if (!td)
1317                         goto nomem;
1318
1319                 i += buf_len;
1320                 td->dataptr = req->req.dma + i;
1321                 last->next = dma_addr;
1322         }
1323
1324         req->td_data_last = td;
1325         td->status |= PCH_UDC_DMA_LAST;
1326         td->next = req->td_data_phys;
1327         req->chain_len = len;
1328         return 0;
1329
1330 nomem:
1331         if (len > 1) {
1332                 req->chain_len = len;
1333                 pch_udc_free_dma_chain(ep->dev, req);
1334         }
1335         req->chain_len = 1;
1336         return -ENOMEM;
1337 }
1338
1339 /**
1340  * prepare_dma() - This function creates and initializes the DMA chain
1341  *                      for the request
1342  * @ep:         Reference to the endpoint structure
1343  * @req:        Reference to the request
1344  * @gfp:        Flag to be used while mapping the data buffer
1345  *
1346  * Return codes:
1347  *      0:              Success
1348  *      Other 0:        linux error number on failure
1349  */
1350 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1351                           gfp_t gfp)
1352 {
1353         int     retval;
1354
1355         req->td_data->dataptr = req->req.dma;
1356         req->td_data->status |= PCH_UDC_DMA_LAST;
1357         /* Allocate and create a DMA chain */
1358         retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1359         if (retval) {
1360                 pr_err("%s: could not create DMA chain: %d\n",
1361                        __func__, retval);
1362                 return retval;
1363         }
1364         if (!ep->in)
1365                 return 0;
1366         if (req->req.length <= ep->ep.maxpacket)
1367                 req->td_data->status = PCH_UDC_DMA_LAST | PCH_UDC_BS_HST_BSY |
1368                                        req->req.length;
1369         /* if bytes < max packet then tx bytes must
1370          * be written in packet per buffer mode
1371          */
1372         if ((req->req.length < ep->ep.maxpacket) || !ep->num)
1373                 req->td_data->status = (req->td_data->status &
1374                                         ~PCH_UDC_RXTX_BYTES) | req->req.length;
1375         req->td_data->status = (req->td_data->status &
1376                                 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_BSY;
1377         return 0;
1378 }
1379
1380 /**
1381  * process_zlp() - This function process zero length packets
1382  *                      from the gadget driver
1383  * @ep:         Reference to the endpoint structure
1384  * @req:        Reference to the request
1385  */
1386 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1387 {
1388         struct pch_udc_dev      *dev = ep->dev;
1389
1390         /* IN zlp's are handled by hardware */
1391         complete_req(ep, req, 0);
1392
1393         /* if set_config or set_intf is waiting for ack by zlp
1394          * then set CSR_DONE
1395          */
1396         if (dev->set_cfg_not_acked) {
1397                 pch_udc_set_csr_done(dev);
1398                 dev->set_cfg_not_acked = 0;
1399         }
1400         /* setup command is ACK'ed now by zlp */
1401         if (!dev->stall && dev->waiting_zlp_ack) {
1402                 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1403                 dev->waiting_zlp_ack = 0;
1404         }
1405 }
1406
1407 /**
1408  * pch_udc_start_rxrequest() - This function starts the receive requirement.
1409  * @ep:         Reference to the endpoint structure
1410  * @req:        Reference to the request structure
1411  */
1412 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1413                                          struct pch_udc_request *req)
1414 {
1415         struct pch_udc_data_dma_desc *td_data;
1416
1417         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1418         td_data = req->td_data;
1419         /* Set the status bits for all descriptors */
1420         while (1) {
1421                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1422                                     PCH_UDC_BS_HST_RDY;
1423                 if ((td_data->status & PCH_UDC_DMA_LAST) ==  PCH_UDC_DMA_LAST)
1424                         break;
1425                 td_data = phys_to_virt(td_data->next);
1426         }
1427         /* Write the descriptor pointer */
1428         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1429         req->dma_going = 1;
1430         pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1431         pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1432         pch_udc_ep_clear_nak(ep);
1433         pch_udc_ep_set_rrdy(ep);
1434 }
1435
1436 /**
1437  * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1438  *                              from gadget driver
1439  * @usbep:      Reference to the USB endpoint structure
1440  * @desc:       Reference to the USB endpoint descriptor structure
1441  *
1442  * Return codes:
1443  *      0:              Success
1444  *      -EINVAL:
1445  *      -ESHUTDOWN:
1446  */
1447 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1448                                     const struct usb_endpoint_descriptor *desc)
1449 {
1450         struct pch_udc_ep       *ep;
1451         struct pch_udc_dev      *dev;
1452         unsigned long           iflags;
1453
1454         if (!usbep || (usbep->name == ep0_string) || !desc ||
1455             (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1456                 return -EINVAL;
1457
1458         ep = container_of(usbep, struct pch_udc_ep, ep);
1459         dev = ep->dev;
1460         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1461                 return -ESHUTDOWN;
1462         spin_lock_irqsave(&dev->lock, iflags);
1463         ep->desc = desc;
1464         ep->halted = 0;
1465         pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1466         ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
1467         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1468         spin_unlock_irqrestore(&dev->lock, iflags);
1469         return 0;
1470 }
1471
1472 /**
1473  * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1474  *                              from gadget driver
1475  * @usbep       Reference to the USB endpoint structure
1476  *
1477  * Return codes:
1478  *      0:              Success
1479  *      -EINVAL:
1480  */
1481 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1482 {
1483         struct pch_udc_ep       *ep;
1484         struct pch_udc_dev      *dev;
1485         unsigned long   iflags;
1486
1487         if (!usbep)
1488                 return -EINVAL;
1489
1490         ep = container_of(usbep, struct pch_udc_ep, ep);
1491         dev = ep->dev;
1492         if ((usbep->name == ep0_string) || !ep->desc)
1493                 return -EINVAL;
1494
1495         spin_lock_irqsave(&ep->dev->lock, iflags);
1496         empty_req_queue(ep);
1497         ep->halted = 1;
1498         pch_udc_ep_disable(ep);
1499         pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1500         ep->desc = NULL;
1501         INIT_LIST_HEAD(&ep->queue);
1502         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1503         return 0;
1504 }
1505
1506 /**
1507  * pch_udc_alloc_request() - This function allocates request structure.
1508  *                              It is called by gadget driver
1509  * @usbep:      Reference to the USB endpoint structure
1510  * @gfp:        Flag to be used while allocating memory
1511  *
1512  * Return codes:
1513  *      NULL:                   Failure
1514  *      Allocated address:      Success
1515  */
1516 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1517                                                   gfp_t gfp)
1518 {
1519         struct pch_udc_request          *req;
1520         struct pch_udc_ep               *ep;
1521         struct pch_udc_data_dma_desc    *dma_desc;
1522         struct pch_udc_dev              *dev;
1523
1524         if (!usbep)
1525                 return NULL;
1526         ep = container_of(usbep, struct pch_udc_ep, ep);
1527         dev = ep->dev;
1528         req = kzalloc(sizeof *req, gfp);
1529         if (!req)
1530                 return NULL;
1531         req->req.dma = DMA_ADDR_INVALID;
1532         INIT_LIST_HEAD(&req->queue);
1533         if (!ep->dev->dma_addr)
1534                 return &req->req;
1535         /* ep0 in requests are allocated from data pool here */
1536         dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1537                                   &req->td_data_phys);
1538         if (NULL == dma_desc) {
1539                 kfree(req);
1540                 return NULL;
1541         }
1542         /* prevent from using desc. - set HOST BUSY */
1543         dma_desc->status |= PCH_UDC_BS_HST_BSY;
1544         dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1545         req->td_data = dma_desc;
1546         req->td_data_last = dma_desc;
1547         req->chain_len = 1;
1548         return &req->req;
1549 }
1550
1551 /**
1552  * pch_udc_free_request() - This function frees request structure.
1553  *                              It is called by gadget driver
1554  * @usbep:      Reference to the USB endpoint structure
1555  * @usbreq:     Reference to the USB request
1556  */
1557 static void pch_udc_free_request(struct usb_ep *usbep,
1558                                   struct usb_request *usbreq)
1559 {
1560         struct pch_udc_ep       *ep;
1561         struct pch_udc_request  *req;
1562         struct pch_udc_dev      *dev;
1563
1564         if (!usbep || !usbreq)
1565                 return;
1566         ep = container_of(usbep, struct pch_udc_ep, ep);
1567         req = container_of(usbreq, struct pch_udc_request, req);
1568         dev = ep->dev;
1569         if (!list_empty(&req->queue))
1570                 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1571                         __func__, usbep->name, req);
1572         if (req->td_data != NULL) {
1573                 if (req->chain_len > 1)
1574                         pch_udc_free_dma_chain(ep->dev, req);
1575                 pci_pool_free(ep->dev->data_requests, req->td_data,
1576                               req->td_data_phys);
1577         }
1578         kfree(req);
1579 }
1580
1581 /**
1582  * pch_udc_pcd_queue() - This function queues a request packet. It is called
1583  *                      by gadget driver
1584  * @usbep:      Reference to the USB endpoint structure
1585  * @usbreq:     Reference to the USB request
1586  * @gfp:        Flag to be used while mapping the data buffer
1587  *
1588  * Return codes:
1589  *      0:                      Success
1590  *      linux error number:     Failure
1591  */
1592 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1593                                                                  gfp_t gfp)
1594 {
1595         int retval = 0;
1596         struct pch_udc_ep       *ep;
1597         struct pch_udc_dev      *dev;
1598         struct pch_udc_request  *req;
1599         unsigned long   iflags;
1600
1601         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1602                 return -EINVAL;
1603         ep = container_of(usbep, struct pch_udc_ep, ep);
1604         dev = ep->dev;
1605         if (!ep->desc && ep->num)
1606                 return -EINVAL;
1607         req = container_of(usbreq, struct pch_udc_request, req);
1608         if (!list_empty(&req->queue))
1609                 return -EINVAL;
1610         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1611                 return -ESHUTDOWN;
1612         spin_lock_irqsave(&ep->dev->lock, iflags);
1613         /* map the buffer for dma */
1614         if (usbreq->length &&
1615             ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1616                 if (ep->in)
1617                         usbreq->dma = dma_map_single(&dev->pdev->dev,
1618                                                      usbreq->buf,
1619                                                      usbreq->length,
1620                                                      DMA_TO_DEVICE);
1621                 else
1622                         usbreq->dma = dma_map_single(&dev->pdev->dev,
1623                                                      usbreq->buf,
1624                                                      usbreq->length,
1625                                                      DMA_FROM_DEVICE);
1626                 req->dma_mapped = 1;
1627         }
1628         if (usbreq->length > 0) {
1629                 retval = prepare_dma(ep, req, GFP_ATOMIC);
1630                 if (retval)
1631                         goto probe_end;
1632         }
1633         usbreq->actual = 0;
1634         usbreq->status = -EINPROGRESS;
1635         req->dma_done = 0;
1636         if (list_empty(&ep->queue) && !ep->halted) {
1637                 /* no pending transfer, so start this req */
1638                 if (!usbreq->length) {
1639                         process_zlp(ep, req);
1640                         retval = 0;
1641                         goto probe_end;
1642                 }
1643                 if (!ep->in) {
1644                         pch_udc_start_rxrequest(ep, req);
1645                 } else {
1646                         /*
1647                         * For IN trfr the descriptors will be programmed and
1648                         * P bit will be set when
1649                         * we get an IN token
1650                         */
1651                         pch_udc_wait_ep_stall(ep);
1652                         pch_udc_ep_clear_nak(ep);
1653                         pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1654                 }
1655         }
1656         /* Now add this request to the ep's pending requests */
1657         if (req != NULL)
1658                 list_add_tail(&req->queue, &ep->queue);
1659
1660 probe_end:
1661         spin_unlock_irqrestore(&dev->lock, iflags);
1662         return retval;
1663 }
1664
1665 /**
1666  * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1667  *                              It is called by gadget driver
1668  * @usbep:      Reference to the USB endpoint structure
1669  * @usbreq:     Reference to the USB request
1670  *
1671  * Return codes:
1672  *      0:                      Success
1673  *      linux error number:     Failure
1674  */
1675 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1676                                 struct usb_request *usbreq)
1677 {
1678         struct pch_udc_ep       *ep;
1679         struct pch_udc_request  *req;
1680         struct pch_udc_dev      *dev;
1681         unsigned long           flags;
1682         int ret = -EINVAL;
1683
1684         ep = container_of(usbep, struct pch_udc_ep, ep);
1685         dev = ep->dev;
1686         if (!usbep || !usbreq || (!ep->desc && ep->num))
1687                 return ret;
1688         req = container_of(usbreq, struct pch_udc_request, req);
1689         spin_lock_irqsave(&ep->dev->lock, flags);
1690         /* make sure it's still queued on this endpoint */
1691         list_for_each_entry(req, &ep->queue, queue) {
1692                 if (&req->req == usbreq) {
1693                         pch_udc_ep_set_nak(ep);
1694                         if (!list_empty(&req->queue))
1695                                 complete_req(ep, req, -ECONNRESET);
1696                         ret = 0;
1697                         break;
1698                 }
1699         }
1700         spin_unlock_irqrestore(&ep->dev->lock, flags);
1701         return ret;
1702 }
1703
1704 /**
1705  * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1706  *                          feature
1707  * @usbep:      Reference to the USB endpoint structure
1708  * @halt:       Specifies whether to set or clear the feature
1709  *
1710  * Return codes:
1711  *      0:                      Success
1712  *      linux error number:     Failure
1713  */
1714 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1715 {
1716         struct pch_udc_ep       *ep;
1717         struct pch_udc_dev      *dev;
1718         unsigned long iflags;
1719         int ret;
1720
1721         if (!usbep)
1722                 return -EINVAL;
1723         ep = container_of(usbep, struct pch_udc_ep, ep);
1724         dev = ep->dev;
1725         if (!ep->desc && !ep->num)
1726                 return -EINVAL;
1727         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1728                 return -ESHUTDOWN;
1729         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1730         if (list_empty(&ep->queue)) {
1731                 if (halt) {
1732                         if (ep->num == PCH_UDC_EP0)
1733                                 ep->dev->stall = 1;
1734                         pch_udc_ep_set_stall(ep);
1735                         pch_udc_enable_ep_interrupts(ep->dev,
1736                                                      PCH_UDC_EPINT(ep->in,
1737                                                                    ep->num));
1738                 } else {
1739                         pch_udc_ep_clear_stall(ep);
1740                 }
1741                 ret = 0;
1742         } else {
1743                 ret = -EAGAIN;
1744         }
1745         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1746         return ret;
1747 }
1748
1749 /**
1750  * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1751  *                              halt feature
1752  * @usbep:      Reference to the USB endpoint structure
1753  * @halt:       Specifies whether to set or clear the feature
1754  *
1755  * Return codes:
1756  *      0:                      Success
1757  *      linux error number:     Failure
1758  */
1759 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1760 {
1761         struct pch_udc_ep       *ep;
1762         struct pch_udc_dev      *dev;
1763         unsigned long iflags;
1764         int ret;
1765
1766         if (!usbep)
1767                 return -EINVAL;
1768         ep = container_of(usbep, struct pch_udc_ep, ep);
1769         dev = ep->dev;
1770         if (!ep->desc && !ep->num)
1771                 return -EINVAL;
1772         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1773                 return -ESHUTDOWN;
1774         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1775         if (!list_empty(&ep->queue)) {
1776                 ret = -EAGAIN;
1777         } else {
1778                 if (ep->num == PCH_UDC_EP0)
1779                         ep->dev->stall = 1;
1780                 pch_udc_ep_set_stall(ep);
1781                 pch_udc_enable_ep_interrupts(ep->dev,
1782                                              PCH_UDC_EPINT(ep->in, ep->num));
1783                 ep->dev->prot_stall = 1;
1784                 ret = 0;
1785         }
1786         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1787         return ret;
1788 }
1789
1790 /**
1791  * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1792  * @usbep:      Reference to the USB endpoint structure
1793  */
1794 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1795 {
1796         struct pch_udc_ep  *ep;
1797
1798         if (!usbep)
1799                 return;
1800
1801         ep = container_of(usbep, struct pch_udc_ep, ep);
1802         if (ep->desc || !ep->num)
1803                 pch_udc_ep_fifo_flush(ep, ep->in);
1804 }
1805
1806 static const struct usb_ep_ops pch_udc_ep_ops = {
1807         .enable         = pch_udc_pcd_ep_enable,
1808         .disable        = pch_udc_pcd_ep_disable,
1809         .alloc_request  = pch_udc_alloc_request,
1810         .free_request   = pch_udc_free_request,
1811         .queue          = pch_udc_pcd_queue,
1812         .dequeue        = pch_udc_pcd_dequeue,
1813         .set_halt       = pch_udc_pcd_set_halt,
1814         .set_wedge      = pch_udc_pcd_set_wedge,
1815         .fifo_status    = NULL,
1816         .fifo_flush     = pch_udc_pcd_fifo_flush,
1817 };
1818
1819 /**
1820  * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1821  * @td_stp:     Reference to the SETP buffer structure
1822  */
1823 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
1824 {
1825         static u32      pky_marker;
1826
1827         if (!td_stp)
1828                 return;
1829         td_stp->reserved = ++pky_marker;
1830         memset(&td_stp->request, 0xFF, sizeof td_stp->request);
1831         td_stp->status = PCH_UDC_BS_HST_RDY;
1832 }
1833
1834 /**
1835  * pch_udc_start_next_txrequest() - This function starts
1836  *                                      the next transmission requirement
1837  * @ep: Reference to the endpoint structure
1838  */
1839 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
1840 {
1841         struct pch_udc_request *req;
1842         struct pch_udc_data_dma_desc *td_data;
1843
1844         if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
1845                 return;
1846
1847         if (list_empty(&ep->queue))
1848                 return;
1849
1850         /* next request */
1851         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1852         if (req->dma_going)
1853                 return;
1854         if (!req->td_data)
1855                 return;
1856         pch_udc_wait_ep_stall(ep);
1857         req->dma_going = 1;
1858         pch_udc_ep_set_ddptr(ep, 0);
1859         td_data = req->td_data;
1860         while (1) {
1861                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1862                                    PCH_UDC_BS_HST_RDY;
1863                 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1864                         break;
1865                 td_data = phys_to_virt(td_data->next);
1866         }
1867         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1868         pch_udc_set_dma(ep->dev, DMA_DIR_TX);
1869         pch_udc_ep_set_pd(ep);
1870         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1871         pch_udc_ep_clear_nak(ep);
1872 }
1873
1874 /**
1875  * pch_udc_complete_transfer() - This function completes a transfer
1876  * @ep:         Reference to the endpoint structure
1877  */
1878 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
1879 {
1880         struct pch_udc_request *req;
1881         struct pch_udc_dev *dev = ep->dev;
1882
1883         if (list_empty(&ep->queue))
1884                 return;
1885         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1886         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1887             PCH_UDC_BS_DMA_DONE)
1888                 return;
1889         if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1890              PCH_UDC_RTS_SUCC) {
1891                 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1892                         "epstatus=0x%08x\n",
1893                        (req->td_data_last->status & PCH_UDC_RXTX_STS),
1894                        (int)(ep->epsts));
1895                 return;
1896         }
1897
1898         req->req.actual = req->req.length;
1899         req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1900         req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1901         complete_req(ep, req, 0);
1902         req->dma_going = 0;
1903         if (!list_empty(&ep->queue)) {
1904                 pch_udc_wait_ep_stall(ep);
1905                 pch_udc_ep_clear_nak(ep);
1906                 pch_udc_enable_ep_interrupts(ep->dev,
1907                                              PCH_UDC_EPINT(ep->in, ep->num));
1908         } else {
1909                 pch_udc_disable_ep_interrupts(ep->dev,
1910                                               PCH_UDC_EPINT(ep->in, ep->num));
1911         }
1912 }
1913
1914 /**
1915  * pch_udc_complete_receiver() - This function completes a receiver
1916  * @ep:         Reference to the endpoint structure
1917  */
1918 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1919 {
1920         struct pch_udc_request *req;
1921         struct pch_udc_dev *dev = ep->dev;
1922         unsigned int count;
1923
1924         if (list_empty(&ep->queue))
1925                 return;
1926
1927         /* next request */
1928         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1929         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1930             PCH_UDC_BS_DMA_DONE)
1931                 return;
1932         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1933         pch_udc_ep_set_ddptr(ep, 0);
1934         if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1935             PCH_UDC_RTS_SUCC) {
1936                 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1937                         "epstatus=0x%08x\n",
1938                         (req->td_data_last->status & PCH_UDC_RXTX_STS),
1939                         (int)(ep->epsts));
1940                 return;
1941         }
1942         count = req->td_data_last->status & PCH_UDC_RXTX_BYTES;
1943
1944         /* on 64k packets the RXBYTES field is zero */
1945         if (!count && (req->req.length == UDC_DMA_MAXPACKET))
1946                 count = UDC_DMA_MAXPACKET;
1947         req->td_data->status |= PCH_UDC_DMA_LAST;
1948         req->td_data_last->status |= PCH_UDC_BS_HST_BSY;
1949
1950         req->dma_going = 0;
1951         req->req.actual = count;
1952         complete_req(ep, req, 0);
1953         /* If there is a new/failed requests try that now */
1954         if (!list_empty(&ep->queue)) {
1955                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1956                 pch_udc_start_rxrequest(ep, req);
1957         }
1958 }
1959
1960 /**
1961  * pch_udc_svc_data_in() - This function process endpoint interrupts
1962  *                              for IN endpoints
1963  * @dev:        Reference to the device structure
1964  * @ep_num:     Endpoint that generated the interrupt
1965  */
1966 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
1967 {
1968         u32     epsts;
1969         struct pch_udc_ep       *ep;
1970
1971         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
1972         epsts = ep->epsts;
1973         ep->epsts = 0;
1974
1975         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA  | UDC_EPSTS_HE |
1976                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
1977                        UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
1978                 return;
1979         if ((epsts & UDC_EPSTS_BNA))
1980                 return;
1981         if (epsts & UDC_EPSTS_HE)
1982                 return;
1983         if (epsts & UDC_EPSTS_RSS) {
1984                 pch_udc_ep_set_stall(ep);
1985                 pch_udc_enable_ep_interrupts(ep->dev,
1986                                              PCH_UDC_EPINT(ep->in, ep->num));
1987         }
1988         if (epsts & UDC_EPSTS_RCS) {
1989                 if (!dev->prot_stall) {
1990                         pch_udc_ep_clear_stall(ep);
1991                 } else {
1992                         pch_udc_ep_set_stall(ep);
1993                         pch_udc_enable_ep_interrupts(ep->dev,
1994                                                 PCH_UDC_EPINT(ep->in, ep->num));
1995                 }
1996         }
1997         if (epsts & UDC_EPSTS_TDC)
1998                 pch_udc_complete_transfer(ep);
1999         /* On IN interrupt, provide data if we have any */
2000         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2001             !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2002                 pch_udc_start_next_txrequest(ep);
2003 }
2004
2005 /**
2006  * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2007  * @dev:        Reference to the device structure
2008  * @ep_num:     Endpoint that generated the interrupt
2009  */
2010 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2011 {
2012         u32                     epsts;
2013         struct pch_udc_ep               *ep;
2014         struct pch_udc_request          *req = NULL;
2015
2016         ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2017         epsts = ep->epsts;
2018         ep->epsts = 0;
2019
2020         if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2021                 /* next request */
2022                 req = list_entry(ep->queue.next, struct pch_udc_request,
2023                                  queue);
2024                 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2025                      PCH_UDC_BS_DMA_DONE) {
2026                         if (!req->dma_going)
2027                                 pch_udc_start_rxrequest(ep, req);
2028                         return;
2029                 }
2030         }
2031         if (epsts & UDC_EPSTS_HE)
2032                 return;
2033         if (epsts & UDC_EPSTS_RSS) {
2034                 pch_udc_ep_set_stall(ep);
2035                 pch_udc_enable_ep_interrupts(ep->dev,
2036                                              PCH_UDC_EPINT(ep->in, ep->num));
2037         }
2038         if (epsts & UDC_EPSTS_RCS) {
2039                 if (!dev->prot_stall) {
2040                         pch_udc_ep_clear_stall(ep);
2041                 } else {
2042                         pch_udc_ep_set_stall(ep);
2043                         pch_udc_enable_ep_interrupts(ep->dev,
2044                                                 PCH_UDC_EPINT(ep->in, ep->num));
2045                 }
2046         }
2047         if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2048             UDC_EPSTS_OUT_DATA) {
2049                 if (ep->dev->prot_stall == 1) {
2050                         pch_udc_ep_set_stall(ep);
2051                         pch_udc_enable_ep_interrupts(ep->dev,
2052                                                 PCH_UDC_EPINT(ep->in, ep->num));
2053                 } else {
2054                         pch_udc_complete_receiver(ep);
2055                 }
2056         }
2057         if (list_empty(&ep->queue))
2058                 pch_udc_set_dma(dev, DMA_DIR_RX);
2059 }
2060
2061 /**
2062  * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2063  * @dev:        Reference to the device structure
2064  */
2065 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2066 {
2067         u32     epsts;
2068         struct pch_udc_ep       *ep;
2069         struct pch_udc_ep       *ep_out;
2070
2071         ep = &dev->ep[UDC_EP0IN_IDX];
2072         ep_out = &dev->ep[UDC_EP0OUT_IDX];
2073         epsts = ep->epsts;
2074         ep->epsts = 0;
2075
2076         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2077                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2078                        UDC_EPSTS_XFERDONE)))
2079                 return;
2080         if ((epsts & UDC_EPSTS_BNA))
2081                 return;
2082         if (epsts & UDC_EPSTS_HE)
2083                 return;
2084         if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2085                 pch_udc_complete_transfer(ep);
2086                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2087                 ep_out->td_data->status = (ep_out->td_data->status &
2088                                         ~PCH_UDC_BUFF_STS) |
2089                                         PCH_UDC_BS_HST_RDY;
2090                 pch_udc_ep_clear_nak(ep_out);
2091                 pch_udc_set_dma(dev, DMA_DIR_RX);
2092                 pch_udc_ep_set_rrdy(ep_out);
2093         }
2094         /* On IN interrupt, provide data if we have any */
2095         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2096              !(epsts & UDC_EPSTS_TXEMPTY))
2097                 pch_udc_start_next_txrequest(ep);
2098 }
2099
2100 /**
2101  * pch_udc_svc_control_out() - Routine that handle Control
2102  *                                      OUT endpoint interrupts
2103  * @dev:        Reference to the device structure
2104  */
2105 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2106 {
2107         u32     stat;
2108         int setup_supported;
2109         struct pch_udc_ep       *ep;
2110
2111         ep = &dev->ep[UDC_EP0OUT_IDX];
2112         stat = ep->epsts;
2113         ep->epsts = 0;
2114
2115         /* If setup data */
2116         if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2117             UDC_EPSTS_OUT_SETUP) {
2118                 dev->stall = 0;
2119                 dev->ep[UDC_EP0IN_IDX].halted = 0;
2120                 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2121                 dev->setup_data = ep->td_stp->request;
2122                 pch_udc_init_setup_buff(ep->td_stp);
2123                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2124                 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2125                                       dev->ep[UDC_EP0IN_IDX].in);
2126                 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2127                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2128                 else /* OUT */
2129                         dev->gadget.ep0 = &ep->ep;
2130                 spin_unlock(&dev->lock);
2131                 /* If Mass storage Reset */
2132                 if ((dev->setup_data.bRequestType == 0x21) &&
2133                     (dev->setup_data.bRequest == 0xFF))
2134                         dev->prot_stall = 0;
2135                 /* call gadget with setup data received */
2136                 setup_supported = dev->driver->setup(&dev->gadget,
2137                                                      &dev->setup_data);
2138                 spin_lock(&dev->lock);
2139
2140                 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2141                         ep->td_data->status = (ep->td_data->status &
2142                                                 ~PCH_UDC_BUFF_STS) |
2143                                                 PCH_UDC_BS_HST_RDY;
2144                         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2145                 }
2146                 /* ep0 in returns data on IN phase */
2147                 if (setup_supported >= 0 && setup_supported <
2148                                             UDC_EP0IN_MAX_PKT_SIZE) {
2149                         pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2150                         /* Gadget would have queued a request when
2151                          * we called the setup */
2152                         if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2153                                 pch_udc_set_dma(dev, DMA_DIR_RX);
2154                                 pch_udc_ep_clear_nak(ep);
2155                         }
2156                 } else if (setup_supported < 0) {
2157                         /* if unsupported request, then stall */
2158                         pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2159                         pch_udc_enable_ep_interrupts(ep->dev,
2160                                                 PCH_UDC_EPINT(ep->in, ep->num));
2161                         dev->stall = 0;
2162                         pch_udc_set_dma(dev, DMA_DIR_RX);
2163                 } else {
2164                         dev->waiting_zlp_ack = 1;
2165                 }
2166         } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2167                      UDC_EPSTS_OUT_DATA) && !dev->stall) {
2168                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2169                 pch_udc_ep_set_ddptr(ep, 0);
2170                 if (!list_empty(&ep->queue)) {
2171                         ep->epsts = stat;
2172                         pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2173                 }
2174                 pch_udc_set_dma(dev, DMA_DIR_RX);
2175         }
2176         pch_udc_ep_set_rrdy(ep);
2177 }
2178
2179
2180 /**
2181  * pch_udc_postsvc_epinters() - This function enables end point interrupts
2182  *                              and clears NAK status
2183  * @dev:        Reference to the device structure
2184  * @ep_num:     End point number
2185  */
2186 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2187 {
2188         struct pch_udc_ep       *ep;
2189         struct pch_udc_request *req;
2190
2191         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2192         if (!list_empty(&ep->queue)) {
2193                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2194                 pch_udc_enable_ep_interrupts(ep->dev,
2195                                              PCH_UDC_EPINT(ep->in, ep->num));
2196                 pch_udc_ep_clear_nak(ep);
2197         }
2198 }
2199
2200 /**
2201  * pch_udc_read_all_epstatus() - This function read all endpoint status
2202  * @dev:        Reference to the device structure
2203  * @ep_intr:    Status of endpoint interrupt
2204  */
2205 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2206 {
2207         int i;
2208         struct pch_udc_ep       *ep;
2209
2210         for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2211                 /* IN */
2212                 if (ep_intr & (0x1 << i)) {
2213                         ep = &dev->ep[UDC_EPIN_IDX(i)];
2214                         ep->epsts = pch_udc_read_ep_status(ep);
2215                         pch_udc_clear_ep_status(ep, ep->epsts);
2216                 }
2217                 /* OUT */
2218                 if (ep_intr & (0x10000 << i)) {
2219                         ep = &dev->ep[UDC_EPOUT_IDX(i)];
2220                         ep->epsts = pch_udc_read_ep_status(ep);
2221                         pch_udc_clear_ep_status(ep, ep->epsts);
2222                 }
2223         }
2224 }
2225
2226 /**
2227  * pch_udc_activate_control_ep() - This function enables the control endpoints
2228  *                                      for traffic after a reset
2229  * @dev:        Reference to the device structure
2230  */
2231 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2232 {
2233         struct pch_udc_ep       *ep;
2234         u32 val;
2235
2236         /* Setup the IN endpoint */
2237         ep = &dev->ep[UDC_EP0IN_IDX];
2238         pch_udc_clear_ep_control(ep);
2239         pch_udc_ep_fifo_flush(ep, ep->in);
2240         pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2241         pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2242         /* Initialize the IN EP Descriptor */
2243         ep->td_data      = NULL;
2244         ep->td_stp       = NULL;
2245         ep->td_data_phys = 0;
2246         ep->td_stp_phys  = 0;
2247
2248         /* Setup the OUT endpoint */
2249         ep = &dev->ep[UDC_EP0OUT_IDX];
2250         pch_udc_clear_ep_control(ep);
2251         pch_udc_ep_fifo_flush(ep, ep->in);
2252         pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2253         pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2254         val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2255         pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2256
2257         /* Initialize the SETUP buffer */
2258         pch_udc_init_setup_buff(ep->td_stp);
2259         /* Write the pointer address of dma descriptor */
2260         pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2261         /* Write the pointer address of Setup descriptor */
2262         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2263
2264         /* Initialize the dma descriptor */
2265         ep->td_data->status  = PCH_UDC_DMA_LAST;
2266         ep->td_data->dataptr = dev->dma_addr;
2267         ep->td_data->next    = ep->td_data_phys;
2268
2269         pch_udc_ep_clear_nak(ep);
2270 }
2271
2272
2273 /**
2274  * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2275  * @dev:        Reference to driver structure
2276  */
2277 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2278 {
2279         struct pch_udc_ep       *ep;
2280         int i;
2281
2282         pch_udc_clear_dma(dev, DMA_DIR_TX);
2283         pch_udc_clear_dma(dev, DMA_DIR_RX);
2284         /* Mask all endpoint interrupts */
2285         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2286         /* clear all endpoint interrupts */
2287         pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2288
2289         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2290                 ep = &dev->ep[i];
2291                 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2292                 pch_udc_clear_ep_control(ep);
2293                 pch_udc_ep_set_ddptr(ep, 0);
2294                 pch_udc_write_csr(ep->dev, 0x00, i);
2295         }
2296         dev->stall = 0;
2297         dev->prot_stall = 0;
2298         dev->waiting_zlp_ack = 0;
2299         dev->set_cfg_not_acked = 0;
2300
2301         /* disable ep to empty req queue. Skip the control EP's */
2302         for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2303                 ep = &dev->ep[i];
2304                 pch_udc_ep_set_nak(ep);
2305                 pch_udc_ep_fifo_flush(ep, ep->in);
2306                 /* Complete request queue */
2307                 empty_req_queue(ep);
2308         }
2309         if (dev->driver && dev->driver->disconnect)
2310                 dev->driver->disconnect(&dev->gadget);
2311 }
2312
2313 /**
2314  * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2315  *                              done interrupt
2316  * @dev:        Reference to driver structure
2317  */
2318 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2319 {
2320         u32 dev_stat, dev_speed;
2321         u32 speed = USB_SPEED_FULL;
2322
2323         dev_stat = pch_udc_read_device_status(dev);
2324         dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2325                                                  UDC_DEVSTS_ENUM_SPEED_SHIFT;
2326         switch (dev_speed) {
2327         case UDC_DEVSTS_ENUM_SPEED_HIGH:
2328                 speed = USB_SPEED_HIGH;
2329                 break;
2330         case  UDC_DEVSTS_ENUM_SPEED_FULL:
2331                 speed = USB_SPEED_FULL;
2332                 break;
2333         case  UDC_DEVSTS_ENUM_SPEED_LOW:
2334                 speed = USB_SPEED_LOW;
2335                 break;
2336         default:
2337                 BUG();
2338         }
2339         dev->gadget.speed = speed;
2340         pch_udc_activate_control_ep(dev);
2341         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2342         pch_udc_set_dma(dev, DMA_DIR_TX);
2343         pch_udc_set_dma(dev, DMA_DIR_RX);
2344         pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2345 }
2346
2347 /**
2348  * pch_udc_svc_intf_interrupt() - This function handles a set interface
2349  *                                interrupt
2350  * @dev:        Reference to driver structure
2351  */
2352 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2353 {
2354         u32 reg, dev_stat = 0;
2355         int i, ret;
2356
2357         dev_stat = pch_udc_read_device_status(dev);
2358         dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2359                                                          UDC_DEVSTS_INTF_SHIFT;
2360         dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2361                                                          UDC_DEVSTS_ALT_SHIFT;
2362         dev->set_cfg_not_acked = 1;
2363         /* Construct the usb request for gadget driver and inform it */
2364         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2365         dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2366         dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2367         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2368         dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2369         /* programm the Endpoint Cfg registers */
2370         /* Only one end point cfg register */
2371         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2372         reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2373               (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2374         reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2375               (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2376         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2377         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2378                 /* clear stall bits */
2379                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2380                 dev->ep[i].halted = 0;
2381         }
2382         dev->stall = 0;
2383         spin_unlock(&dev->lock);
2384         ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2385         spin_lock(&dev->lock);
2386 }
2387
2388 /**
2389  * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2390  *                              interrupt
2391  * @dev:        Reference to driver structure
2392  */
2393 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2394 {
2395         int i, ret;
2396         u32 reg, dev_stat = 0;
2397
2398         dev_stat = pch_udc_read_device_status(dev);
2399         dev->set_cfg_not_acked = 1;
2400         dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2401                                 UDC_DEVSTS_CFG_SHIFT;
2402         /* make usb request for gadget driver */
2403         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2404         dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2405         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2406         /* program the NE registers */
2407         /* Only one end point cfg register */
2408         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2409         reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2410               (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2411         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2412         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2413                 /* clear stall bits */
2414                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2415                 dev->ep[i].halted = 0;
2416         }
2417         dev->stall = 0;
2418
2419         /* call gadget zero with setup data received */
2420         spin_unlock(&dev->lock);
2421         ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2422         spin_lock(&dev->lock);
2423 }
2424
2425 /**
2426  * pch_udc_dev_isr() - This function services device interrupts
2427  *                      by invoking appropriate routines.
2428  * @dev:        Reference to the device structure
2429  * @dev_intr:   The Device interrupt status.
2430  */
2431 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2432 {
2433         /* USB Reset Interrupt */
2434         if (dev_intr & UDC_DEVINT_UR)
2435                 pch_udc_svc_ur_interrupt(dev);
2436         /* Enumeration Done Interrupt */
2437         if (dev_intr & UDC_DEVINT_ENUM)
2438                 pch_udc_svc_enum_interrupt(dev);
2439         /* Set Interface Interrupt */
2440         if (dev_intr & UDC_DEVINT_SI)
2441                 pch_udc_svc_intf_interrupt(dev);
2442         /* Set Config Interrupt */
2443         if (dev_intr & UDC_DEVINT_SC)
2444                 pch_udc_svc_cfg_interrupt(dev);
2445         /* USB Suspend interrupt */
2446         if (dev_intr & UDC_DEVINT_US)
2447                 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2448         /* Clear the SOF interrupt, if enabled */
2449         if (dev_intr & UDC_DEVINT_SOF)
2450                 dev_dbg(&dev->pdev->dev, "SOF\n");
2451         /* ES interrupt, IDLE > 3ms on the USB */
2452         if (dev_intr & UDC_DEVINT_ES)
2453                 dev_dbg(&dev->pdev->dev, "ES\n");
2454         /* RWKP interrupt */
2455         if (dev_intr & UDC_DEVINT_RWKP)
2456                 dev_dbg(&dev->pdev->dev, "RWKP\n");
2457 }
2458
2459 /**
2460  * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2461  * @irq:        Interrupt request number
2462  * @dev:        Reference to the device structure
2463  */
2464 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2465 {
2466         struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2467         u32 dev_intr, ep_intr;
2468         int i;
2469
2470         dev_intr = pch_udc_read_device_interrupts(dev);
2471         ep_intr = pch_udc_read_ep_interrupts(dev);
2472
2473         if (dev_intr)
2474                 /* Clear device interrupts */
2475                 pch_udc_write_device_interrupts(dev, dev_intr);
2476         if (ep_intr)
2477                 /* Clear ep interrupts */
2478                 pch_udc_write_ep_interrupts(dev, ep_intr);
2479         if (!dev_intr && !ep_intr)
2480                 return IRQ_NONE;
2481         spin_lock(&dev->lock);
2482         if (dev_intr)
2483                 pch_udc_dev_isr(dev, dev_intr);
2484         if (ep_intr) {
2485                 pch_udc_read_all_epstatus(dev, ep_intr);
2486                 /* Process Control In interrupts, if present */
2487                 if (ep_intr & UDC_EPINT_IN_EP0) {
2488                         pch_udc_svc_control_in(dev);
2489                         pch_udc_postsvc_epinters(dev, 0);
2490                 }
2491                 /* Process Control Out interrupts, if present */
2492                 if (ep_intr & UDC_EPINT_OUT_EP0)
2493                         pch_udc_svc_control_out(dev);
2494                 /* Process data in end point interrupts */
2495                 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2496                         if (ep_intr & (1 <<  i)) {
2497                                 pch_udc_svc_data_in(dev, i);
2498                                 pch_udc_postsvc_epinters(dev, i);
2499                         }
2500                 }
2501                 /* Process data out end point interrupts */
2502                 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2503                                                  PCH_UDC_USED_EP_NUM); i++)
2504                         if (ep_intr & (1 <<  i))
2505                                 pch_udc_svc_data_out(dev, i -
2506                                                          UDC_EPINT_OUT_SHIFT);
2507         }
2508         spin_unlock(&dev->lock);
2509         return IRQ_HANDLED;
2510 }
2511
2512 /**
2513  * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2514  * @dev:        Reference to the device structure
2515  */
2516 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2517 {
2518         /* enable ep0 interrupts */
2519         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2520                                                 UDC_EPINT_OUT_EP0);
2521         /* enable device interrupts */
2522         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2523                                        UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2524                                        UDC_DEVINT_SI | UDC_DEVINT_SC);
2525 }
2526
2527 /**
2528  * gadget_release() - Free the gadget driver private data
2529  * @pdev        reference to struct pci_dev
2530  */
2531 static void gadget_release(struct device *pdev)
2532 {
2533         struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2534
2535         kfree(dev);
2536 }
2537
2538 /**
2539  * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2540  * @dev:        Reference to the driver structure
2541  */
2542 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2543 {
2544         const char *const ep_string[] = {
2545                 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2546                 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2547                 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2548                 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2549                 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2550                 "ep15in", "ep15out",
2551         };
2552         int i;
2553
2554         dev->gadget.speed = USB_SPEED_UNKNOWN;
2555         INIT_LIST_HEAD(&dev->gadget.ep_list);
2556
2557         /* Initialize the endpoints structures */
2558         memset(dev->ep, 0, sizeof dev->ep);
2559         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2560                 struct pch_udc_ep *ep = &dev->ep[i];
2561                 ep->dev = dev;
2562                 ep->halted = 1;
2563                 ep->num = i / 2;
2564                 ep->in = ~i & 1;
2565                 ep->ep.name = ep_string[i];
2566                 ep->ep.ops = &pch_udc_ep_ops;
2567                 if (ep->in)
2568                         ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2569                 else
2570                         ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2571                                           UDC_EP_REG_SHIFT;
2572                 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2573                 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2574                 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2575                 INIT_LIST_HEAD(&ep->queue);
2576         }
2577         dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2578         dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2579
2580         /* remove ep0 in and out from the list.  They have own pointer */
2581         list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2582         list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2583
2584         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2585         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2586 }
2587
2588 /**
2589  * pch_udc_pcd_init() - This API initializes the driver structure
2590  * @dev:        Reference to the driver structure
2591  *
2592  * Return codes:
2593  *      0: Success
2594  */
2595 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2596 {
2597         pch_udc_init(dev);
2598         pch_udc_pcd_reinit(dev);
2599         return 0;
2600 }
2601
2602 /**
2603  * init_dma_pools() - create dma pools during initialization
2604  * @pdev:       reference to struct pci_dev
2605  */
2606 static int init_dma_pools(struct pch_udc_dev *dev)
2607 {
2608         struct pch_udc_stp_dma_desc     *td_stp;
2609         struct pch_udc_data_dma_desc    *td_data;
2610
2611         /* DMA setup */
2612         dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2613                 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2614         if (!dev->data_requests) {
2615                 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2616                         __func__);
2617                 return -ENOMEM;
2618         }
2619
2620         /* dma desc for setup data */
2621         dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2622                 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2623         if (!dev->stp_requests) {
2624                 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2625                         __func__);
2626                 return -ENOMEM;
2627         }
2628         /* setup */
2629         td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2630                                 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2631         if (!td_stp) {
2632                 dev_err(&dev->pdev->dev,
2633                         "%s: can't allocate setup dma descriptor\n", __func__);
2634                 return -ENOMEM;
2635         }
2636         dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2637
2638         /* data: 0 packets !? */
2639         td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2640                                 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2641         if (!td_data) {
2642                 dev_err(&dev->pdev->dev,
2643                         "%s: can't allocate data dma descriptor\n", __func__);
2644                 return -ENOMEM;
2645         }
2646         dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2647         dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2648         dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2649         dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2650         dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2651
2652         dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2653         if (!dev->ep0out_buf)
2654                 return -ENOMEM;
2655         dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2656                                        UDC_EP0OUT_BUFF_SIZE * 4,
2657                                        DMA_FROM_DEVICE);
2658         return 0;
2659 }
2660
2661 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
2662         int (*bind)(struct usb_gadget *))
2663 {
2664         struct pch_udc_dev      *dev = pch_udc;
2665         int                     retval;
2666
2667         if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
2668             !driver->setup || !driver->unbind || !driver->disconnect) {
2669                 dev_err(&dev->pdev->dev,
2670                         "%s: invalid driver parameter\n", __func__);
2671                 return -EINVAL;
2672         }
2673
2674         if (!dev)
2675                 return -ENODEV;
2676
2677         if (dev->driver) {
2678                 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2679                 return -EBUSY;
2680         }
2681         driver->driver.bus = NULL;
2682         dev->driver = driver;
2683         dev->gadget.dev.driver = &driver->driver;
2684
2685         /* Invoke the bind routine of the gadget driver */
2686         retval = bind(&dev->gadget);
2687
2688         if (retval) {
2689                 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2690                        __func__, driver->driver.name, retval);
2691                 dev->driver = NULL;
2692                 dev->gadget.dev.driver = NULL;
2693                 return retval;
2694         }
2695         /* get ready for ep0 traffic */
2696         pch_udc_setup_ep0(dev);
2697
2698         /* clear SD */
2699         pch_udc_clear_disconnect(dev);
2700
2701         dev->connected = 1;
2702         return 0;
2703 }
2704 EXPORT_SYMBOL(usb_gadget_probe_driver);
2705
2706 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2707 {
2708         struct pch_udc_dev      *dev = pch_udc;
2709
2710         if (!dev)
2711                 return -ENODEV;
2712
2713         if (!driver || (driver != dev->driver)) {
2714                 dev_err(&dev->pdev->dev,
2715                         "%s: invalid driver parameter\n", __func__);
2716                 return -EINVAL;
2717         }
2718
2719         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2720
2721         /* Assures that there are no pending requests with this driver */
2722         driver->disconnect(&dev->gadget);
2723         driver->unbind(&dev->gadget);
2724         dev->gadget.dev.driver = NULL;
2725         dev->driver = NULL;
2726         dev->connected = 0;
2727
2728         /* set SD */
2729         pch_udc_set_disconnect(dev);
2730         return 0;
2731 }
2732 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2733
2734 static void pch_udc_shutdown(struct pci_dev *pdev)
2735 {
2736         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2737
2738         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2739         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2740
2741         /* disable the pullup so the host will think we're gone */
2742         pch_udc_set_disconnect(dev);
2743 }
2744
2745 static void pch_udc_remove(struct pci_dev *pdev)
2746 {
2747         struct pch_udc_dev      *dev = pci_get_drvdata(pdev);
2748
2749         /* gadget driver must not be registered */
2750         if (dev->driver)
2751                 dev_err(&pdev->dev,
2752                         "%s: gadget driver still bound!!!\n", __func__);
2753         /* dma pool cleanup */
2754         if (dev->data_requests)
2755                 pci_pool_destroy(dev->data_requests);
2756
2757         if (dev->stp_requests) {
2758                 /* cleanup DMA desc's for ep0in */
2759                 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2760                         pci_pool_free(dev->stp_requests,
2761                                 dev->ep[UDC_EP0OUT_IDX].td_stp,
2762                                 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2763                 }
2764                 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
2765                         pci_pool_free(dev->stp_requests,
2766                                 dev->ep[UDC_EP0OUT_IDX].td_data,
2767                                 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2768                 }
2769                 pci_pool_destroy(dev->stp_requests);
2770         }
2771
2772         if (dev->dma_addr)
2773                 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
2774                                  UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
2775         kfree(dev->ep0out_buf);
2776
2777         pch_udc_exit(dev);
2778
2779         if (dev->irq_registered)
2780                 free_irq(pdev->irq, dev);
2781         if (dev->base_addr)
2782                 iounmap(dev->base_addr);
2783         if (dev->mem_region)
2784                 release_mem_region(dev->phys_addr,
2785                                    pci_resource_len(pdev, PCH_UDC_PCI_BAR));
2786         if (dev->active)
2787                 pci_disable_device(pdev);
2788         if (dev->registered)
2789                 device_unregister(&dev->gadget.dev);
2790         kfree(dev);
2791         pci_set_drvdata(pdev, NULL);
2792 }
2793
2794 #ifdef CONFIG_PM
2795 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
2796 {
2797         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2798
2799         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2800         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2801
2802         pci_disable_device(pdev);
2803         pci_enable_wake(pdev, PCI_D3hot, 0);
2804
2805         if (pci_save_state(pdev)) {
2806                 dev_err(&pdev->dev,
2807                         "%s: could not save PCI config state\n", __func__);
2808                 return -ENOMEM;
2809         }
2810         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2811         return 0;
2812 }
2813
2814 static int pch_udc_resume(struct pci_dev *pdev)
2815 {
2816         int ret;
2817
2818         pci_set_power_state(pdev, PCI_D0);
2819         pci_restore_state(pdev);
2820         ret = pci_enable_device(pdev);
2821         if (ret) {
2822                 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
2823                 return ret;
2824         }
2825         pci_enable_wake(pdev, PCI_D3hot, 0);
2826         return 0;
2827 }
2828 #else
2829 #define pch_udc_suspend NULL
2830 #define pch_udc_resume  NULL
2831 #endif /* CONFIG_PM */
2832
2833 static int pch_udc_probe(struct pci_dev *pdev,
2834                           const struct pci_device_id *id)
2835 {
2836         unsigned long           resource;
2837         unsigned long           len;
2838         int                     retval;
2839         struct pch_udc_dev      *dev;
2840
2841         /* one udc only */
2842         if (pch_udc) {
2843                 pr_err("%s: already probed\n", __func__);
2844                 return -EBUSY;
2845         }
2846         /* init */
2847         dev = kzalloc(sizeof *dev, GFP_KERNEL);
2848         if (!dev) {
2849                 pr_err("%s: no memory for device structure\n", __func__);
2850                 return -ENOMEM;
2851         }
2852         /* pci setup */
2853         if (pci_enable_device(pdev) < 0) {
2854                 kfree(dev);
2855                 pr_err("%s: pci_enable_device failed\n", __func__);
2856                 return -ENODEV;
2857         }
2858         dev->active = 1;
2859         pci_set_drvdata(pdev, dev);
2860
2861         /* PCI resource allocation */
2862         resource = pci_resource_start(pdev, 1);
2863         len = pci_resource_len(pdev, 1);
2864
2865         if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
2866                 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
2867                 retval = -EBUSY;
2868                 goto finished;
2869         }
2870         dev->phys_addr = resource;
2871         dev->mem_region = 1;
2872
2873         dev->base_addr = ioremap_nocache(resource, len);
2874         if (!dev->base_addr) {
2875                 pr_err("%s: device memory cannot be mapped\n", __func__);
2876                 retval = -ENOMEM;
2877                 goto finished;
2878         }
2879         if (!pdev->irq) {
2880                 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
2881                 retval = -ENODEV;
2882                 goto finished;
2883         }
2884         pch_udc = dev;
2885         /* initialize the hardware */
2886         if (pch_udc_pcd_init(dev))
2887                 goto finished;
2888         if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
2889                         dev)) {
2890                 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
2891                         pdev->irq);
2892                 retval = -ENODEV;
2893                 goto finished;
2894         }
2895         dev->irq = pdev->irq;
2896         dev->irq_registered = 1;
2897
2898         pci_set_master(pdev);
2899         pci_try_set_mwi(pdev);
2900
2901         /* device struct setup */
2902         spin_lock_init(&dev->lock);
2903         dev->pdev = pdev;
2904         dev->gadget.ops = &pch_udc_ops;
2905
2906         retval = init_dma_pools(dev);
2907         if (retval)
2908                 goto finished;
2909
2910         dev_set_name(&dev->gadget.dev, "gadget");
2911         dev->gadget.dev.parent = &pdev->dev;
2912         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2913         dev->gadget.dev.release = gadget_release;
2914         dev->gadget.name = KBUILD_MODNAME;
2915         dev->gadget.is_dualspeed = 1;
2916
2917         retval = device_register(&dev->gadget.dev);
2918         if (retval)
2919                 goto finished;
2920         dev->registered = 1;
2921
2922         /* Put the device in disconnected state till a driver is bound */
2923         pch_udc_set_disconnect(dev);
2924         return 0;
2925
2926 finished:
2927         pch_udc_remove(pdev);
2928         return retval;
2929 }
2930
2931 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
2932         {
2933                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
2934                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2935                 .class_mask = 0xffffffff,
2936         },
2937         {
2938                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
2939                 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2940                 .class_mask = 0xffffffff,
2941         },
2942         { 0 },
2943 };
2944
2945 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
2946
2947
2948 static struct pci_driver pch_udc_driver = {
2949         .name = KBUILD_MODNAME,
2950         .id_table =     pch_udc_pcidev_id,
2951         .probe =        pch_udc_probe,
2952         .remove =       pch_udc_remove,
2953         .suspend =      pch_udc_suspend,
2954         .resume =       pch_udc_resume,
2955         .shutdown =     pch_udc_shutdown,
2956 };
2957
2958 static int __init pch_udc_pci_init(void)
2959 {
2960         return pci_register_driver(&pch_udc_driver);
2961 }
2962 module_init(pch_udc_pci_init);
2963
2964 static void __exit pch_udc_pci_exit(void)
2965 {
2966         pci_unregister_driver(&pch_udc_driver);
2967 }
2968 module_exit(pch_udc_pci_exit);
2969
2970 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
2971 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2972 MODULE_LICENSE("GPL");