drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #undef  DEBUG
  25 #undef  VERBOSE
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/types.h>
  31 #include <linux/errno.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb/ch9.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <mach/dma.h>
  56 #include <mach/usb.h>
  57
  58 #include "omap_udc.h"
  59
  60 #undef  USB_TRACE
  61
  62 /* bulk DMA seems to be behaving for both IN and OUT */
  63 #define USE_DMA
  64
  65 /* ISO too */
  66 #define USE_ISO
  67
  68 #define DRIVER_DESC     "OMAP UDC driver"
  69 #define DRIVER_VERSION  "4 October 2004"
  70
  71 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  72
  73 #define OMAP2_DMA_CH(ch)        (((ch) - 1) << 1)
  74 #define OMAP24XX_DMA(name, ch)  (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
  75
  76 /*
  77  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  78  * D+ pullup to allow enumeration.  That's too early for the gadget
  79  * framework to use from usb_endpoint_enable(), which happens after
  80  * enumeration as part of activating an interface.  (But if we add an
  81  * optional new "UDC not yet running" state to the gadget driver model,
  82  * even just during driver binding, the endpoint autoconfig logic is the
  83  * natural spot to manufacture new endpoints.)
  84  *
  85  * So instead of using endpoint enable calls to control the hardware setup,
  86  * this driver defines a "fifo mode" parameter.  It's used during driver
  87  * initialization to choose among a set of pre-defined endpoint configs.
  88  * See omap_udc_setup() for available modes, or to add others.  That code
  89  * lives in an init section, so use this driver as a module if you need
  90  * to change the fifo mode after the kernel boots.
  91  *
  92  * Gadget drivers normally ignore endpoints they don't care about, and
  93  * won't include them in configuration descriptors.  That means only
  94  * misbehaving hosts would even notice they exist.
  95  */
  96 #ifdef  USE_ISO
  97 static unsigned fifo_mode = 3;
  98 #else
  99 static unsigned fifo_mode = 0;
 100 #endif
 101
 102 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 103  * boot parameter "omap_udc:fifo_mode=42"
 104  */
 105 module_param (fifo_mode, uint, 0);
 106 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 107
 108 #ifdef  USE_DMA
 109 static unsigned use_dma = 1;
 110
 111 /* "modprobe omap_udc use_dma=y", or else as a kernel
 112  * boot parameter "omap_udc:use_dma=y"
 113  */
 114 module_param (use_dma, bool, 0);
 115 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 116 #else   /* !USE_DMA */
 117
 118 /* save a bit of code */
 119 #define use_dma         0
 120 #endif  /* !USE_DMA */
 121
 122
 123 static const char driver_name [] = "omap_udc";
 124 static const char driver_desc [] = DRIVER_DESC;
 125
 126 /*-------------------------------------------------------------------------*/
 127
 128 /* there's a notion of "current endpoint" for modifying endpoint
 129  * state, and PIO access to its FIFO.
 130  */
 131
 132 static void use_ep(struct omap_ep *ep, u16 select)
 133 {
 134         u16     num = ep->bEndpointAddress & 0x0f;
 135
 136         if (ep->bEndpointAddress & USB_DIR_IN)
 137                 num |= UDC_EP_DIR;
 138         omap_writew(num | select, UDC_EP_NUM);
 139         /* when select, MUST deselect later !! */
 140 }
 141
 142 static inline void deselect_ep(void)
 143 {
 144         u16 w;
 145
 146         w = omap_readw(UDC_EP_NUM);
 147         w &= ~UDC_EP_SEL;
 148         omap_writew(w, UDC_EP_NUM);
 149         /* 6 wait states before TX will happen */
 150 }
 151
 152 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 153
 154 /*-------------------------------------------------------------------------*/
 155
 156 static int omap_ep_enable(struct usb_ep *_ep,
 157                 const struct usb_endpoint_descriptor *desc)
 158 {
 159         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 160         struct omap_udc *udc;
 161         unsigned long   flags;
 162         u16             maxp;
 163
 164         /* catch various bogus parameters */
 165         if (!_ep || !desc || ep->desc
 166                         || desc->bDescriptorType != USB_DT_ENDPOINT
 167                         || ep->bEndpointAddress != desc->bEndpointAddress
 168                         || ep->maxpacket < le16_to_cpu
 169                                                 (desc->wMaxPacketSize)) {
 170                 DBG("%s, bad ep or descriptor\n", __func__);
 171                 return -EINVAL;
 172         }
 173         maxp = le16_to_cpu (desc->wMaxPacketSize);
 174         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 175                                 && maxp != ep->maxpacket)
 176                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 177                         || !desc->wMaxPacketSize) {
 178                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 179                 return -ERANGE;
 180         }
 181
 182 #ifdef  USE_ISO
 183         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 184                                 && desc->bInterval != 1)) {
 185                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 186                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 187                                 1 << (desc->bInterval - 1));
 188                 return -EDOM;
 189         }
 190 #else
 191         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 192                 DBG("%s, ISO nyet\n", _ep->name);
 193                 return -EDOM;
 194         }
 195 #endif
 196
 197         /* xfer types must match, except that interrupt ~= bulk */
 198         if (ep->bmAttributes != desc->bmAttributes
 199                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 200                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 201                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
 202                 return -EINVAL;
 203         }
 204
 205         udc = ep->udc;
 206         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 207                 DBG("%s, bogus device state\n", __func__);
 208                 return -ESHUTDOWN;
 209         }
 210
 211         spin_lock_irqsave(&udc->lock, flags);
 212
 213         ep->desc = desc;
 214         ep->irqs = 0;
 215         ep->stopped = 0;
 216         ep->ep.maxpacket = maxp;
 217
 218         /* set endpoint to initial state */
 219         ep->dma_channel = 0;
 220         ep->has_dma = 0;
 221         ep->lch = -1;
 222         use_ep(ep, UDC_EP_SEL);
 223         omap_writew(udc->clr_halt, UDC_CTRL);
 224         ep->ackwait = 0;
 225         deselect_ep();
 226
 227         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 228                 list_add(&ep->iso, &udc->iso);
 229
 230         /* maybe assign a DMA channel to this endpoint */
 231         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 232                 /* FIXME ISO can dma, but prefers first channel */
 233                 dma_channel_claim(ep, 0);
 234
 235         /* PIO OUT may RX packets */
 236         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 237                         && !ep->has_dma
 238                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 239                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 240                 ep->ackwait = 1 + ep->double_buf;
 241         }
 242
 243         spin_unlock_irqrestore(&udc->lock, flags);
 244         VDBG("%s enabled\n", _ep->name);
 245         return 0;
 246 }
 247
 248 static void nuke(struct omap_ep *, int status);
 249
 250 static int omap_ep_disable(struct usb_ep *_ep)
 251 {
 252         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 253         unsigned long   flags;
 254
 255         if (!_ep || !ep->desc) {
 256                 DBG("%s, %s not enabled\n", __func__,
 257                         _ep ? ep->ep.name : NULL);
 258                 return -EINVAL;
 259         }
 260
 261         spin_lock_irqsave(&ep->udc->lock, flags);
 262         ep->desc = NULL;
 263         nuke (ep, -ESHUTDOWN);
 264         ep->ep.maxpacket = ep->maxpacket;
 265         ep->has_dma = 0;
 266         omap_writew(UDC_SET_HALT, UDC_CTRL);
 267         list_del_init(&ep->iso);
 268         del_timer(&ep->timer);
 269
 270         spin_unlock_irqrestore(&ep->udc->lock, flags);
 271
 272         VDBG("%s disabled\n", _ep->name);
 273         return 0;
 274 }
 275
 276 /*-------------------------------------------------------------------------*/
 277
 278 static struct usb_request *
 279 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 280 {
 281         struct omap_req *req;
 282
 283         req = kzalloc(sizeof(*req), gfp_flags);
 284         if (req) {
 285                 req->req.dma = DMA_ADDR_INVALID;
 286                 INIT_LIST_HEAD (&req->queue);
 287         }
 288         return &req->req;
 289 }
 290
 291 static void
 292 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 293 {
 294         struct omap_req *req = container_of(_req, struct omap_req, req);
 295
 296         if (_req)
 297                 kfree (req);
 298 }
 299
 300 /*-------------------------------------------------------------------------*/
 301
 302 static void
 303 done(struct omap_ep *ep, struct omap_req *req, int status)
 304 {
 305         unsigned                stopped = ep->stopped;
 306
 307         list_del_init(&req->queue);
 308
 309         if (req->req.status == -EINPROGRESS)
 310                 req->req.status = status;
 311         else
 312                 status = req->req.status;
 313
 314         if (use_dma && ep->has_dma) {
 315                 if (req->mapped) {
 316                         dma_unmap_single(ep->udc->gadget.dev.parent,
 317                                 req->req.dma, req->req.length,
 318                                 (ep->bEndpointAddress & USB_DIR_IN)
 319                                         ? DMA_TO_DEVICE
 320                                         : DMA_FROM_DEVICE);
 321                         req->req.dma = DMA_ADDR_INVALID;
 322                         req->mapped = 0;
 323                 } else
 324                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 325                                 req->req.dma, req->req.length,
 326                                 (ep->bEndpointAddress & USB_DIR_IN)
 327                                         ? DMA_TO_DEVICE
 328                                         : DMA_FROM_DEVICE);
 329         }
 330
 331 #ifndef USB_TRACE
 332         if (status && status != -ESHUTDOWN)
 333 #endif
 334                 VDBG("complete %s req %p stat %d len %u/%u\n",
 335                         ep->ep.name, &req->req, status,
 336                         req->req.actual, req->req.length);
 337
 338         /* don't modify queue heads during completion callback */
 339         ep->stopped = 1;
 340         spin_unlock(&ep->udc->lock);
 341         req->req.complete(&ep->ep, &req->req);
 342         spin_lock(&ep->udc->lock);
 343         ep->stopped = stopped;
 344 }
 345
 346 /*-------------------------------------------------------------------------*/
 347
 348 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 349 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 350
 351 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 352 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 353
 354 static inline int
 355 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 356 {
 357         unsigned        len;
 358         u16             *wp;
 359
 360         len = min(req->req.length - req->req.actual, max);
 361         req->req.actual += len;
 362
 363         max = len;
 364         if (likely((((int)buf) & 1) == 0)) {
 365                 wp = (u16 *)buf;
 366                 while (max >= 2) {
 367                         omap_writew(*wp++, UDC_DATA);
 368                         max -= 2;
 369                 }
 370                 buf = (u8 *)wp;
 371         }
 372         while (max--)
 373                 omap_writeb(*buf++, UDC_DATA);
 374         return len;
 375 }
 376
 377 // FIXME change r/w fifo calling convention
 378
 379
 380 // return:  0 = still running, 1 = completed, negative = errno
 381 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 382 {
 383         u8              *buf;
 384         unsigned        count;
 385         int             is_last;
 386         u16             ep_stat;
 387
 388         buf = req->req.buf + req->req.actual;
 389         prefetch(buf);
 390
 391         /* PIO-IN isn't double buffered except for iso */
 392         ep_stat = omap_readw(UDC_STAT_FLG);
 393         if (ep_stat & UDC_FIFO_UNWRITABLE)
 394                 return 0;
 395
 396         count = ep->ep.maxpacket;
 397         count = write_packet(buf, req, count);
 398         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 399         ep->ackwait = 1;
 400
 401         /* last packet is often short (sometimes a zlp) */
 402         if (count != ep->ep.maxpacket)
 403                 is_last = 1;
 404         else if (req->req.length == req->req.actual
 405                         && !req->req.zero)
 406                 is_last = 1;
 407         else
 408                 is_last = 0;
 409
 410         /* NOTE:  requests complete when all IN data is in a
 411          * FIFO (or sometimes later, if a zlp was needed).
 412          * Use usb_ep_fifo_status() where needed.
 413          */
 414         if (is_last)
 415                 done(ep, req, 0);
 416         return is_last;
 417 }
 418
 419 static inline int
 420 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 421 {
 422         unsigned        len;
 423         u16             *wp;
 424
 425         len = min(req->req.length - req->req.actual, avail);
 426         req->req.actual += len;
 427         avail = len;
 428
 429         if (likely((((int)buf) & 1) == 0)) {
 430                 wp = (u16 *)buf;
 431                 while (avail >= 2) {
 432                         *wp++ = omap_readw(UDC_DATA);
 433                         avail -= 2;
 434                 }
 435                 buf = (u8 *)wp;
 436         }
 437         while (avail--)
 438                 *buf++ = omap_readb(UDC_DATA);
 439         return len;
 440 }
 441
 442 // return:  0 = still running, 1 = queue empty, negative = errno
 443 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 444 {
 445         u8              *buf;
 446         unsigned        count, avail;
 447         int             is_last;
 448
 449         buf = req->req.buf + req->req.actual;
 450         prefetchw(buf);
 451
 452         for (;;) {
 453                 u16     ep_stat = omap_readw(UDC_STAT_FLG);
 454
 455                 is_last = 0;
 456                 if (ep_stat & FIFO_EMPTY) {
 457                         if (!ep->double_buf)
 458                                 break;
 459                         ep->fnf = 1;
 460                 }
 461                 if (ep_stat & UDC_EP_HALTED)
 462                         break;
 463
 464                 if (ep_stat & UDC_FIFO_FULL)
 465                         avail = ep->ep.maxpacket;
 466                 else  {
 467                         avail = omap_readw(UDC_RXFSTAT);
 468                         ep->fnf = ep->double_buf;
 469                 }
 470                 count = read_packet(buf, req, avail);
 471
 472                 /* partial packet reads may not be errors */
 473                 if (count < ep->ep.maxpacket) {
 474                         is_last = 1;
 475                         /* overflowed this request?  flush extra data */
 476                         if (count != avail) {
 477                                 req->req.status = -EOVERFLOW;
 478                                 avail -= count;
 479                                 while (avail--)
 480                                         omap_readw(UDC_DATA);
 481                         }
 482                 } else if (req->req.length == req->req.actual)
 483                         is_last = 1;
 484                 else
 485                         is_last = 0;
 486
 487                 if (!ep->bEndpointAddress)
 488                         break;
 489                 if (is_last)
 490                         done(ep, req, 0);
 491                 break;
 492         }
 493         return is_last;
 494 }
 495
 496 /*-------------------------------------------------------------------------*/
 497
 498 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 499 {
 500         dma_addr_t      end;
 501
 502         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 503          * the last transfer's bytecount by more than a FIFO's worth.
 504          */
 505         if (cpu_is_omap15xx())
 506                 return 0;
 507
 508         end = omap_get_dma_src_pos(ep->lch);
 509         if (end == ep->dma_counter)
 510                 return 0;
 511
 512         end |= start & (0xffff << 16);
 513         if (end < start)
 514                 end += 0x10000;
 515         return end - start;
 516 }
 517
 518 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 519 {
 520         dma_addr_t      end;
 521
 522         end = omap_get_dma_dst_pos(ep->lch);
 523         if (end == ep->dma_counter)
 524                 return 0;
 525
 526         end |= start & (0xffff << 16);
 527         if (cpu_is_omap15xx())
 528                 end++;
 529         if (end < start)
 530                 end += 0x10000;
 531         return end - start;
 532 }
 533
 534
 535 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 536  * When DMA completion isn't request completion, the UDC continues with
 537  * the next DMA transfer for that USB transfer.
 538  */
 539
 540 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 541 {
 542         u16             txdma_ctrl, w;
 543         unsigned        length = req->req.length - req->req.actual;
 544         const int       sync_mode = cpu_is_omap15xx()
 545                                 ? OMAP_DMA_SYNC_FRAME
 546                                 : OMAP_DMA_SYNC_ELEMENT;
 547         int             dma_trigger = 0;
 548
 549         if (cpu_is_omap24xx())
 550                 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
 551
 552         /* measure length in either bytes or packets */
 553         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 554                         || (cpu_is_omap24xx() && length < ep->maxpacket)
 555                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 556                 txdma_ctrl = UDC_TXN_EOT | length;
 557                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 558                                 length, 1, sync_mode, dma_trigger, 0);
 559         } else {
 560                 length = min(length / ep->maxpacket,
 561                                 (unsigned) UDC_TXN_TSC + 1);
 562                 txdma_ctrl = length;
 563                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 564                                 ep->ep.maxpacket >> 1, length, sync_mode,
 565                                 dma_trigger, 0);
 566                 length *= ep->maxpacket;
 567         }
 568         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 569                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 570                 0, 0);
 571
 572         omap_start_dma(ep->lch);
 573         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 574         w = omap_readw(UDC_DMA_IRQ_EN);
 575         w |= UDC_TX_DONE_IE(ep->dma_channel);
 576         omap_writew(w, UDC_DMA_IRQ_EN);
 577         omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
 578         req->dma_bytes = length;
 579 }
 580
 581 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 582 {
 583         u16 w;
 584
 585         if (status == 0) {
 586                 req->req.actual += req->dma_bytes;
 587
 588                 /* return if this request needs to send data or zlp */
 589                 if (req->req.actual < req->req.length)
 590                         return;
 591                 if (req->req.zero
 592                                 && req->dma_bytes != 0
 593                                 && (req->req.actual % ep->maxpacket) == 0)
 594                         return;
 595         } else
 596                 req->req.actual += dma_src_len(ep, req->req.dma
 597                                                         + req->req.actual);
 598
 599         /* tx completion */
 600         omap_stop_dma(ep->lch);
 601         w = omap_readw(UDC_DMA_IRQ_EN);
 602         w &= ~UDC_TX_DONE_IE(ep->dma_channel);
 603         omap_writew(w, UDC_DMA_IRQ_EN);
 604         done(ep, req, status);
 605 }
 606
 607 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 608 {
 609         unsigned packets = req->req.length - req->req.actual;
 610         int dma_trigger = 0;
 611         u16 w;
 612
 613         if (cpu_is_omap24xx())
 614                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
 615
 616         /* NOTE:  we filtered out "short reads" before, so we know
 617          * the buffer has only whole numbers of packets.
 618          * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
 619          */
 620         if (cpu_is_omap24xx() && packets < ep->maxpacket) {
 621                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 622                                 packets, 1, OMAP_DMA_SYNC_ELEMENT,
 623                                 dma_trigger, 0);
 624                 req->dma_bytes = packets;
 625         } else {
 626                 /* set up this DMA transfer, enable the fifo, start */
 627                 packets /= ep->ep.maxpacket;
 628                 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 629                 req->dma_bytes = packets * ep->ep.maxpacket;
 630                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 631                                 ep->ep.maxpacket >> 1, packets,
 632                                 OMAP_DMA_SYNC_ELEMENT,
 633                                 dma_trigger, 0);
 634         }
 635         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 636                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 637                 0, 0);
 638         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 639
 640         omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
 641         w = omap_readw(UDC_DMA_IRQ_EN);
 642         w |= UDC_RX_EOT_IE(ep->dma_channel);
 643         omap_writew(w, UDC_DMA_IRQ_EN);
 644         omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
 645         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 646
 647         omap_start_dma(ep->lch);
 648 }
 649
 650 static void
 651 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 652 {
 653         u16     count, w;
 654
 655         if (status == 0)
 656                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 657         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 658         count += req->req.actual;
 659         if (one)
 660                 count--;
 661         if (count <= req->req.length)
 662                 req->req.actual = count;
 663
 664         if (count != req->dma_bytes || status)
 665                 omap_stop_dma(ep->lch);
 666
 667         /* if this wasn't short, request may need another transfer */
 668         else if (req->req.actual < req->req.length)
 669                 return;
 670
 671         /* rx completion */
 672         w = omap_readw(UDC_DMA_IRQ_EN);
 673         w &= ~UDC_RX_EOT_IE(ep->dma_channel);
 674         omap_writew(w, UDC_DMA_IRQ_EN);
 675         done(ep, req, status);
 676 }
 677
 678 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 679 {
 680         u16             dman_stat = omap_readw(UDC_DMAN_STAT);
 681         struct omap_ep  *ep;
 682         struct omap_req *req;
 683
 684         /* IN dma: tx to host */
 685         if (irq_src & UDC_TXN_DONE) {
 686                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 687                 ep->irqs++;
 688                 /* can see TXN_DONE after dma abort */
 689                 if (!list_empty(&ep->queue)) {
 690                         req = container_of(ep->queue.next,
 691                                                 struct omap_req, queue);
 692                         finish_in_dma(ep, req, 0);
 693                 }
 694                 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
 695
 696                 if (!list_empty (&ep->queue)) {
 697                         req = container_of(ep->queue.next,
 698                                         struct omap_req, queue);
 699                         next_in_dma(ep, req);
 700                 }
 701         }
 702
 703         /* OUT dma: rx from host */
 704         if (irq_src & UDC_RXN_EOT) {
 705                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 706                 ep->irqs++;
 707                 /* can see RXN_EOT after dma abort */
 708                 if (!list_empty(&ep->queue)) {
 709                         req = container_of(ep->queue.next,
 710                                         struct omap_req, queue);
 711                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 712                 }
 713                 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
 714
 715                 if (!list_empty (&ep->queue)) {
 716                         req = container_of(ep->queue.next,
 717                                         struct omap_req, queue);
 718                         next_out_dma(ep, req);
 719                 }
 720         }
 721
 722         if (irq_src & UDC_RXN_CNT) {
 723                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 724                 ep->irqs++;
 725                 /* omap15xx does this unasked... */
 726                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 727                 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
 728         }
 729 }
 730
 731 static void dma_error(int lch, u16 ch_status, void *data)
 732 {
 733         struct omap_ep  *ep = data;
 734
 735         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 736         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 737         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 738
 739         /* complete current transfer ... */
 740 }
 741
 742 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 743 {
 744         u16     reg;
 745         int     status, restart, is_in;
 746         int     dma_channel;
 747
 748         is_in = ep->bEndpointAddress & USB_DIR_IN;
 749         if (is_in)
 750                 reg = omap_readw(UDC_TXDMA_CFG);
 751         else
 752                 reg = omap_readw(UDC_RXDMA_CFG);
 753         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 754
 755         ep->dma_channel = 0;
 756         ep->lch = -1;
 757         if (channel == 0 || channel > 3) {
 758                 if ((reg & 0x0f00) == 0)
 759                         channel = 3;
 760                 else if ((reg & 0x00f0) == 0)
 761                         channel = 2;
 762                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 763                         channel = 1;
 764                 else {
 765                         status = -EMLINK;
 766                         goto just_restart;
 767                 }
 768         }
 769         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 770         ep->dma_channel = channel;
 771
 772         if (is_in) {
 773                 if (cpu_is_omap24xx())
 774                         dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
 775                 else
 776                         dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 777                 status = omap_request_dma(dma_channel,
 778                         ep->ep.name, dma_error, ep, &ep->lch);
 779                 if (status == 0) {
 780                         omap_writew(reg, UDC_TXDMA_CFG);
 781                         /* EMIFF or SDRC */
 782                         omap_set_dma_src_burst_mode(ep->lch,
 783                                                 OMAP_DMA_DATA_BURST_4);
 784                         omap_set_dma_src_data_pack(ep->lch, 1);
 785                         /* TIPB */
 786                         omap_set_dma_dest_params(ep->lch,
 787                                 OMAP_DMA_PORT_TIPB,
 788                                 OMAP_DMA_AMODE_CONSTANT,
 789                                 (unsigned long) io_v2p(UDC_DATA_DMA),
 790                                 0, 0);
 791                 }
 792         } else {
 793                 if (cpu_is_omap24xx())
 794                         dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
 795                 else
 796                         dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 797
 798                 status = omap_request_dma(dma_channel,
 799                         ep->ep.name, dma_error, ep, &ep->lch);
 800                 if (status == 0) {
 801                         omap_writew(reg, UDC_RXDMA_CFG);
 802                         /* TIPB */
 803                         omap_set_dma_src_params(ep->lch,
 804                                 OMAP_DMA_PORT_TIPB,
 805                                 OMAP_DMA_AMODE_CONSTANT,
 806                                 (unsigned long) io_v2p(UDC_DATA_DMA),
 807                                 0, 0);
 808                         /* EMIFF or SDRC */
 809                         omap_set_dma_dest_burst_mode(ep->lch,
 810                                                 OMAP_DMA_DATA_BURST_4);
 811                         omap_set_dma_dest_data_pack(ep->lch, 1);
 812                 }
 813         }
 814         if (status)
 815                 ep->dma_channel = 0;
 816         else {
 817                 ep->has_dma = 1;
 818                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 819
 820                 /* channel type P: hw synch (fifo) */
 821                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
 822                         omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
 823         }
 824
 825 just_restart:
 826         /* restart any queue, even if the claim failed  */
 827         restart = !ep->stopped && !list_empty(&ep->queue);
 828
 829         if (status)
 830                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 831                         restart ? " (restart)" : "");
 832         else
 833                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 834                         is_in ? 't' : 'r',
 835                         ep->dma_channel - 1, ep->lch,
 836                         restart ? " (restart)" : "");
 837
 838         if (restart) {
 839                 struct omap_req *req;
 840                 req = container_of(ep->queue.next, struct omap_req, queue);
 841                 if (ep->has_dma)
 842                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 843                 else {
 844                         use_ep(ep, UDC_EP_SEL);
 845                         (is_in ? write_fifo : read_fifo)(ep, req);
 846                         deselect_ep();
 847                         if (!is_in) {
 848                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 849                                 ep->ackwait = 1 + ep->double_buf;
 850                         }
 851                         /* IN: 6 wait states before it'll tx */
 852                 }
 853         }
 854 }
 855
 856 static void dma_channel_release(struct omap_ep *ep)
 857 {
 858         int             shift = 4 * (ep->dma_channel - 1);
 859         u16             mask = 0x0f << shift;
 860         struct omap_req *req;
 861         int             active;
 862
 863         /* abort any active usb transfer request */
 864         if (!list_empty(&ep->queue))
 865                 req = container_of(ep->queue.next, struct omap_req, queue);
 866         else
 867                 req = NULL;
 868
 869         active = omap_get_dma_active_status(ep->lch);
 870
 871         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 872                         active ? "active" : "idle",
 873                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 874                         ep->dma_channel - 1, req);
 875
 876         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 877          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 878          */
 879
 880         /* wait till current packet DMA finishes, and fifo empties */
 881         if (ep->bEndpointAddress & USB_DIR_IN) {
 882                 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 883                                         UDC_TXDMA_CFG);
 884
 885                 if (req) {
 886                         finish_in_dma(ep, req, -ECONNRESET);
 887
 888                         /* clear FIFO; hosts probably won't empty it */
 889                         use_ep(ep, UDC_EP_SEL);
 890                         omap_writew(UDC_CLR_EP, UDC_CTRL);
 891                         deselect_ep();
 892                 }
 893                 while (omap_readw(UDC_TXDMA_CFG) & mask)
 894                         udelay(10);
 895         } else {
 896                 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 897                                         UDC_RXDMA_CFG);
 898
 899                 /* dma empties the fifo */
 900                 while (omap_readw(UDC_RXDMA_CFG) & mask)
 901                         udelay(10);
 902                 if (req)
 903                         finish_out_dma(ep, req, -ECONNRESET, 0);
 904         }
 905         omap_free_dma(ep->lch);
 906         ep->dma_channel = 0;
 907         ep->lch = -1;
 908         /* has_dma still set, till endpoint is fully quiesced */
 909 }
 910
 911
 912 /*-------------------------------------------------------------------------*/
 913
 914 static int
 915 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 916 {
 917         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 918         struct omap_req *req = container_of(_req, struct omap_req, req);
 919         struct omap_udc *udc;
 920         unsigned long   flags;
 921         int             is_iso = 0;
 922
 923         /* catch various bogus parameters */
 924         if (!_req || !req->req.complete || !req->req.buf
 925                         || !list_empty(&req->queue)) {
 926                 DBG("%s, bad params\n", __func__);
 927                 return -EINVAL;
 928         }
 929         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 930                 DBG("%s, bad ep\n", __func__);
 931                 return -EINVAL;
 932         }
 933         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 934                 if (req->req.length > ep->ep.maxpacket)
 935                         return -EMSGSIZE;
 936                 is_iso = 1;
 937         }
 938
 939         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 940          * have a hard time with partial packet reads...  reject it.
 941          * Except OMAP2 can handle the small packets.
 942          */
 943         if (use_dma
 944                         && ep->has_dma
 945                         && ep->bEndpointAddress != 0
 946                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 947                         && !cpu_class_is_omap2()
 948                         && (req->req.length % ep->ep.maxpacket) != 0) {
 949                 DBG("%s, no partial packet OUT reads\n", __func__);
 950                 return -EMSGSIZE;
 951         }
 952
 953         udc = ep->udc;
 954         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 955                 return -ESHUTDOWN;
 956
 957         if (use_dma && ep->has_dma) {
 958                 if (req->req.dma == DMA_ADDR_INVALID) {
 959                         req->req.dma = dma_map_single(
 960                                 ep->udc->gadget.dev.parent,
 961                                 req->req.buf,
 962                                 req->req.length,
 963                                 (ep->bEndpointAddress & USB_DIR_IN)
 964                                         ? DMA_TO_DEVICE
 965                                         : DMA_FROM_DEVICE);
 966                         req->mapped = 1;
 967                 } else {
 968                         dma_sync_single_for_device(
 969                                 ep->udc->gadget.dev.parent,
 970                                 req->req.dma, req->req.length,
 971                                 (ep->bEndpointAddress & USB_DIR_IN)
 972                                         ? DMA_TO_DEVICE
 973                                         : DMA_FROM_DEVICE);
 974                         req->mapped = 0;
 975                 }
 976         }
 977
 978         VDBG("%s queue req %p, len %d buf %p\n",
 979                 ep->ep.name, _req, _req->length, _req->buf);
 980
 981         spin_lock_irqsave(&udc->lock, flags);
 982
 983         req->req.status = -EINPROGRESS;
 984         req->req.actual = 0;
 985
 986         /* maybe kickstart non-iso i/o queues */
 987         if (is_iso) {
 988                 u16 w;
 989
 990                 w = omap_readw(UDC_IRQ_EN);
 991                 w |= UDC_SOF_IE;
 992                 omap_writew(w, UDC_IRQ_EN);
 993         } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 994                 int     is_in;
 995
 996                 if (ep->bEndpointAddress == 0) {
 997                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
 998                                 spin_unlock_irqrestore(&udc->lock, flags);
 999                                 return -EL2HLT;
1000                         }
1001
1002                         /* empty DATA stage? */
1003                         is_in = udc->ep0_in;
1004                         if (!req->req.length) {
1005
1006                                 /* chip became CONFIGURED or ADDRESSED
1007                                  * earlier; drivers may already have queued
1008                                  * requests to non-control endpoints
1009                                  */
1010                                 if (udc->ep0_set_config) {
1011                                         u16     irq_en = omap_readw(UDC_IRQ_EN);
1012
1013                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1014                                         if (!udc->ep0_reset_config)
1015                                                 irq_en |= UDC_EPN_RX_IE
1016                                                         | UDC_EPN_TX_IE;
1017                                         omap_writew(irq_en, UDC_IRQ_EN);
1018                                 }
1019
1020                                 /* STATUS for zero length DATA stages is
1021                                  * always an IN ... even for IN transfers,
1022                                  * a weird case which seem to stall OMAP.
1023                                  */
1024                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1025                                 omap_writew(UDC_CLR_EP, UDC_CTRL);
1026                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1027                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1028
1029                                 /* cleanup */
1030                                 udc->ep0_pending = 0;
1031                                 done(ep, req, 0);
1032                                 req = NULL;
1033
1034                         /* non-empty DATA stage */
1035                         } else if (is_in) {
1036                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1037                         } else {
1038                                 if (udc->ep0_setup)
1039                                         goto irq_wait;
1040                                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1041                         }
1042                 } else {
1043                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1044                         if (!ep->has_dma)
1045                                 use_ep(ep, UDC_EP_SEL);
1046                         /* if ISO: SOF IRQs must be enabled/disabled! */
1047                 }
1048
1049                 if (ep->has_dma)
1050                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1051                 else if (req) {
1052                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1053                                 req = NULL;
1054                         deselect_ep();
1055                         if (!is_in) {
1056                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1057                                 ep->ackwait = 1 + ep->double_buf;
1058                         }
1059                         /* IN: 6 wait states before it'll tx */
1060                 }
1061         }
1062
1063 irq_wait:
1064         /* irq handler advances the queue */
1065         if (req != NULL)
1066                 list_add_tail(&req->queue, &ep->queue);
1067         spin_unlock_irqrestore(&udc->lock, flags);
1068
1069         return 0;
1070 }
1071
1072 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1073 {
1074         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1075         struct omap_req *req;
1076         unsigned long   flags;
1077
1078         if (!_ep || !_req)
1079                 return -EINVAL;
1080
1081         spin_lock_irqsave(&ep->udc->lock, flags);
1082
1083         /* make sure it's actually queued on this endpoint */
1084         list_for_each_entry (req, &ep->queue, queue) {
1085                 if (&req->req == _req)
1086                         break;
1087         }
1088         if (&req->req != _req) {
1089                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1090                 return -EINVAL;
1091         }
1092
1093         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1094                 int channel = ep->dma_channel;
1095
1096                 /* releasing the channel cancels the request,
1097                  * reclaiming the channel restarts the queue
1098                  */
1099                 dma_channel_release(ep);
1100                 dma_channel_claim(ep, channel);
1101         } else
1102                 done(ep, req, -ECONNRESET);
1103         spin_unlock_irqrestore(&ep->udc->lock, flags);
1104         return 0;
1105 }
1106
1107 /*-------------------------------------------------------------------------*/
1108
1109 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1110 {
1111         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1112         unsigned long   flags;
1113         int             status = -EOPNOTSUPP;
1114
1115         spin_lock_irqsave(&ep->udc->lock, flags);
1116
1117         /* just use protocol stalls for ep0; real halts are annoying */
1118         if (ep->bEndpointAddress == 0) {
1119                 if (!ep->udc->ep0_pending)
1120                         status = -EINVAL;
1121                 else if (value) {
1122                         if (ep->udc->ep0_set_config) {
1123                                 WARNING("error changing config?\n");
1124                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1125                         }
1126                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1127                         ep->udc->ep0_pending = 0;
1128                         status = 0;
1129                 } else /* NOP */
1130                         status = 0;
1131
1132         /* otherwise, all active non-ISO endpoints can halt */
1133         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1134
1135                 /* IN endpoints must already be idle */
1136                 if ((ep->bEndpointAddress & USB_DIR_IN)
1137                                 && !list_empty(&ep->queue)) {
1138                         status = -EAGAIN;
1139                         goto done;
1140                 }
1141
1142                 if (value) {
1143                         int     channel;
1144
1145                         if (use_dma && ep->dma_channel
1146                                         && !list_empty(&ep->queue)) {
1147                                 channel = ep->dma_channel;
1148                                 dma_channel_release(ep);
1149                         } else
1150                                 channel = 0;
1151
1152                         use_ep(ep, UDC_EP_SEL);
1153                         if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1154                                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1155                                 status = 0;
1156                         } else
1157                                 status = -EAGAIN;
1158                         deselect_ep();
1159
1160                         if (channel)
1161                                 dma_channel_claim(ep, channel);
1162                 } else {
1163                         use_ep(ep, 0);
1164                         omap_writew(ep->udc->clr_halt, UDC_CTRL);
1165                         ep->ackwait = 0;
1166                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1167                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1168                                 ep->ackwait = 1 + ep->double_buf;
1169                         }
1170                 }
1171         }
1172 done:
1173         VDBG("%s %s halt stat %d\n", ep->ep.name,
1174                 value ? "set" : "clear", status);
1175
1176         spin_unlock_irqrestore(&ep->udc->lock, flags);
1177         return status;
1178 }
1179
1180 static struct usb_ep_ops omap_ep_ops = {
1181         .enable         = omap_ep_enable,
1182         .disable        = omap_ep_disable,
1183
1184         .alloc_request  = omap_alloc_request,
1185         .free_request   = omap_free_request,
1186
1187         .queue          = omap_ep_queue,
1188         .dequeue        = omap_ep_dequeue,
1189
1190         .set_halt       = omap_ep_set_halt,
1191         // fifo_status ... report bytes in fifo
1192         // fifo_flush ... flush fifo
1193 };
1194
1195 /*-------------------------------------------------------------------------*/
1196
1197 static int omap_get_frame(struct usb_gadget *gadget)
1198 {
1199         u16     sof = omap_readw(UDC_SOF);
1200         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1201 }
1202
1203 static int omap_wakeup(struct usb_gadget *gadget)
1204 {
1205         struct omap_udc *udc;
1206         unsigned long   flags;
1207         int             retval = -EHOSTUNREACH;
1208
1209         udc = container_of(gadget, struct omap_udc, gadget);
1210
1211         spin_lock_irqsave(&udc->lock, flags);
1212         if (udc->devstat & UDC_SUS) {
1213                 /* NOTE:  OTG spec erratum says that OTG devices may
1214                  * issue wakeups without host enable.
1215                  */
1216                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1217                         DBG("remote wakeup...\n");
1218                         omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1219                         retval = 0;
1220                 }
1221
1222         /* NOTE:  non-OTG systems may use SRP TOO... */
1223         } else if (!(udc->devstat & UDC_ATT)) {
1224                 if (udc->transceiver)
1225                         retval = otg_start_srp(udc->transceiver);
1226         }
1227         spin_unlock_irqrestore(&udc->lock, flags);
1228
1229         return retval;
1230 }
1231
1232 static int
1233 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1234 {
1235         struct omap_udc *udc;
1236         unsigned long   flags;
1237         u16             syscon1;
1238
1239         udc = container_of(gadget, struct omap_udc, gadget);
1240         spin_lock_irqsave(&udc->lock, flags);
1241         syscon1 = omap_readw(UDC_SYSCON1);
1242         if (is_selfpowered)
1243                 syscon1 |= UDC_SELF_PWR;
1244         else
1245                 syscon1 &= ~UDC_SELF_PWR;
1246         omap_writew(syscon1, UDC_SYSCON1);
1247         spin_unlock_irqrestore(&udc->lock, flags);
1248
1249         return 0;
1250 }
1251
1252 static int can_pullup(struct omap_udc *udc)
1253 {
1254         return udc->driver && udc->softconnect && udc->vbus_active;
1255 }
1256
1257 static void pullup_enable(struct omap_udc *udc)
1258 {
1259         u16 w;
1260
1261         w = omap_readw(UDC_SYSCON1);
1262         w |= UDC_PULLUP_EN;
1263         omap_writew(w, UDC_SYSCON1);
1264         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1265                 u32 l;
1266
1267                 l = omap_readl(OTG_CTRL);
1268                 l |= OTG_BSESSVLD;
1269                 omap_writel(l, OTG_CTRL);
1270         }
1271         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1272 }
1273
1274 static void pullup_disable(struct omap_udc *udc)
1275 {
1276         u16 w;
1277
1278         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1279                 u32 l;
1280
1281                 l = omap_readl(OTG_CTRL);
1282                 l &= ~OTG_BSESSVLD;
1283                 omap_writel(l, OTG_CTRL);
1284         }
1285         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1286         w = omap_readw(UDC_SYSCON1);
1287         w &= ~UDC_PULLUP_EN;
1288         omap_writew(w, UDC_SYSCON1);
1289 }
1290
1291 static struct omap_udc *udc;
1292
1293 static void omap_udc_enable_clock(int enable)
1294 {
1295         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1296                 return;
1297
1298         if (enable) {
1299                 clk_enable(udc->dc_clk);
1300                 clk_enable(udc->hhc_clk);
1301                 udelay(100);
1302         } else {
1303                 clk_disable(udc->hhc_clk);
1304                 clk_disable(udc->dc_clk);
1305         }
1306 }
1307
1308 /*
1309  * Called by whatever detects VBUS sessions:  external transceiver
1310  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1311  */
1312 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1313 {
1314         struct omap_udc *udc;
1315         unsigned long   flags;
1316         u32 l;
1317
1318         udc = container_of(gadget, struct omap_udc, gadget);
1319         spin_lock_irqsave(&udc->lock, flags);
1320         VDBG("VBUS %s\n", is_active ? "on" : "off");
1321         udc->vbus_active = (is_active != 0);
1322         if (cpu_is_omap15xx()) {
1323                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1324                 l = omap_readl(FUNC_MUX_CTRL_0);
1325                 if (is_active)
1326                         l |= VBUS_CTRL_1510;
1327                 else
1328                         l &= ~VBUS_CTRL_1510;
1329                 omap_writel(l, FUNC_MUX_CTRL_0);
1330         }
1331         if (udc->dc_clk != NULL && is_active) {
1332                 if (!udc->clk_requested) {
1333                         omap_udc_enable_clock(1);
1334                         udc->clk_requested = 1;
1335                 }
1336         }
1337         if (can_pullup(udc))
1338                 pullup_enable(udc);
1339         else
1340                 pullup_disable(udc);
1341         if (udc->dc_clk != NULL && !is_active) {
1342                 if (udc->clk_requested) {
1343                         omap_udc_enable_clock(0);
1344                         udc->clk_requested = 0;
1345                 }
1346         }
1347         spin_unlock_irqrestore(&udc->lock, flags);
1348         return 0;
1349 }
1350
1351 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1352 {
1353         struct omap_udc *udc;
1354
1355         udc = container_of(gadget, struct omap_udc, gadget);
1356         if (udc->transceiver)
1357                 return otg_set_power(udc->transceiver, mA);
1358         return -EOPNOTSUPP;
1359 }
1360
1361 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1362 {
1363         struct omap_udc *udc;
1364         unsigned long   flags;
1365
1366         udc = container_of(gadget, struct omap_udc, gadget);
1367         spin_lock_irqsave(&udc->lock, flags);
1368         udc->softconnect = (is_on != 0);
1369         if (can_pullup(udc))
1370                 pullup_enable(udc);
1371         else
1372                 pullup_disable(udc);
1373         spin_unlock_irqrestore(&udc->lock, flags);
1374         return 0;
1375 }
1376
1377 static struct usb_gadget_ops omap_gadget_ops = {
1378         .get_frame              = omap_get_frame,
1379         .wakeup                 = omap_wakeup,
1380         .set_selfpowered        = omap_set_selfpowered,
1381         .vbus_session           = omap_vbus_session,
1382         .vbus_draw              = omap_vbus_draw,
1383         .pullup                 = omap_pullup,
1384 };
1385
1386 /*-------------------------------------------------------------------------*/
1387
1388 /* dequeue ALL requests; caller holds udc->lock */
1389 static void nuke(struct omap_ep *ep, int status)
1390 {
1391         struct omap_req *req;
1392
1393         ep->stopped = 1;
1394
1395         if (use_dma && ep->dma_channel)
1396                 dma_channel_release(ep);
1397
1398         use_ep(ep, 0);
1399         omap_writew(UDC_CLR_EP, UDC_CTRL);
1400         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1401                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1402
1403         while (!list_empty(&ep->queue)) {
1404                 req = list_entry(ep->queue.next, struct omap_req, queue);
1405                 done(ep, req, status);
1406         }
1407 }
1408
1409 /* caller holds udc->lock */
1410 static void udc_quiesce(struct omap_udc *udc)
1411 {
1412         struct omap_ep  *ep;
1413
1414         udc->gadget.speed = USB_SPEED_UNKNOWN;
1415         nuke(&udc->ep[0], -ESHUTDOWN);
1416         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1417                 nuke(ep, -ESHUTDOWN);
1418 }
1419
1420 /*-------------------------------------------------------------------------*/
1421
1422 static void update_otg(struct omap_udc *udc)
1423 {
1424         u16     devstat;
1425
1426         if (!gadget_is_otg(&udc->gadget))
1427                 return;
1428
1429         if (omap_readl(OTG_CTRL) & OTG_ID)
1430                 devstat = omap_readw(UDC_DEVSTAT);
1431         else
1432                 devstat = 0;
1433
1434         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1435         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1436         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1437
1438         /* Enable HNP early, avoiding races on suspend irq path.
1439          * ASSUMES OTG state machine B_BUS_REQ input is true.
1440          */
1441         if (udc->gadget.b_hnp_enable) {
1442                 u32 l;
1443
1444                 l = omap_readl(OTG_CTRL);
1445                 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1446                 l &= ~OTG_PULLUP;
1447                 omap_writel(l, OTG_CTRL);
1448         }
1449 }
1450
1451 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1452 {
1453         struct omap_ep  *ep0 = &udc->ep[0];
1454         struct omap_req *req = NULL;
1455
1456         ep0->irqs++;
1457
1458         /* Clear any pending requests and then scrub any rx/tx state
1459          * before starting to handle the SETUP request.
1460          */
1461         if (irq_src & UDC_SETUP) {
1462                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1463
1464                 nuke(ep0, 0);
1465                 if (ack) {
1466                         omap_writew(ack, UDC_IRQ_SRC);
1467                         irq_src = UDC_SETUP;
1468                 }
1469         }
1470
1471         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1472          * This driver uses only uses protocol stalls (ep0 never halts),
1473          * and if we got this far the gadget driver already had a
1474          * chance to stall.  Tries to be forgiving of host oddities.
1475          *
1476          * NOTE:  the last chance gadget drivers have to stall control
1477          * requests is during their request completion callback.
1478          */
1479         if (!list_empty(&ep0->queue))
1480                 req = container_of(ep0->queue.next, struct omap_req, queue);
1481
1482         /* IN == TX to host */
1483         if (irq_src & UDC_EP0_TX) {
1484                 int     stat;
1485
1486                 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1487                 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1488                 stat = omap_readw(UDC_STAT_FLG);
1489                 if (stat & UDC_ACK) {
1490                         if (udc->ep0_in) {
1491                                 /* write next IN packet from response,
1492                                  * or set up the status stage.
1493                                  */
1494                                 if (req)
1495                                         stat = write_fifo(ep0, req);
1496                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1497                                 if (!req && udc->ep0_pending) {
1498                                         omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1499                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1500                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1501                                         omap_writew(0, UDC_EP_NUM);
1502                                         udc->ep0_pending = 0;
1503                                 } /* else:  6 wait states before it'll tx */
1504                         } else {
1505                                 /* ack status stage of OUT transfer */
1506                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1507                                 if (req)
1508                                         done(ep0, req, 0);
1509                         }
1510                         req = NULL;
1511                 } else if (stat & UDC_STALL) {
1512                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1513                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1514                 } else {
1515                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1516                 }
1517         }
1518
1519         /* OUT == RX from host */
1520         if (irq_src & UDC_EP0_RX) {
1521                 int     stat;
1522
1523                 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1524                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1525                 stat = omap_readw(UDC_STAT_FLG);
1526                 if (stat & UDC_ACK) {
1527                         if (!udc->ep0_in) {
1528                                 stat = 0;
1529                                 /* read next OUT packet of request, maybe
1530                                  * reactiviting the fifo; stall on errors.
1531                                  */
1532                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1533                                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1534                                         udc->ep0_pending = 0;
1535                                         stat = 0;
1536                                 } else if (stat == 0)
1537                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1538                                 omap_writew(0, UDC_EP_NUM);
1539
1540                                 /* activate status stage */
1541                                 if (stat == 1) {
1542                                         done(ep0, req, 0);
1543                                         /* that may have STALLed ep0... */
1544                                         omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1545                                                         UDC_EP_NUM);
1546                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1547                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1548                                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1549                                         udc->ep0_pending = 0;
1550                                 }
1551                         } else {
1552                                 /* ack status stage of IN transfer */
1553                                 omap_writew(0, UDC_EP_NUM);
1554                                 if (req)
1555                                         done(ep0, req, 0);
1556                         }
1557                 } else if (stat & UDC_STALL) {
1558                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1559                         omap_writew(0, UDC_EP_NUM);
1560                 } else {
1561                         omap_writew(0, UDC_EP_NUM);
1562                 }
1563         }
1564
1565         /* SETUP starts all control transfers */
1566         if (irq_src & UDC_SETUP) {
1567                 union u {
1568                         u16                     word[4];
1569                         struct usb_ctrlrequest  r;
1570                 } u;
1571                 int                     status = -EINVAL;
1572                 struct omap_ep          *ep;
1573
1574                 /* read the (latest) SETUP message */
1575                 do {
1576                         omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1577                         /* two bytes at a time */
1578                         u.word[0] = omap_readw(UDC_DATA);
1579                         u.word[1] = omap_readw(UDC_DATA);
1580                         u.word[2] = omap_readw(UDC_DATA);
1581                         u.word[3] = omap_readw(UDC_DATA);
1582                         omap_writew(0, UDC_EP_NUM);
1583                 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1584
1585 #define w_value         le16_to_cpu(u.r.wValue)
1586 #define w_index         le16_to_cpu(u.r.wIndex)
1587 #define w_length        le16_to_cpu(u.r.wLength)
1588
1589                 /* Delegate almost all control requests to the gadget driver,
1590                  * except for a handful of ch9 status/feature requests that
1591                  * hardware doesn't autodecode _and_ the gadget API hides.
1592                  */
1593                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1594                 udc->ep0_set_config = 0;
1595                 udc->ep0_pending = 1;
1596                 ep0->stopped = 0;
1597                 ep0->ackwait = 0;
1598                 switch (u.r.bRequest) {
1599                 case USB_REQ_SET_CONFIGURATION:
1600                         /* udc needs to know when ep != 0 is valid */
1601                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1602                                 goto delegate;
1603                         if (w_length != 0)
1604                                 goto do_stall;
1605                         udc->ep0_set_config = 1;
1606                         udc->ep0_reset_config = (w_value == 0);
1607                         VDBG("set config %d\n", w_value);
1608
1609                         /* update udc NOW since gadget driver may start
1610                          * queueing requests immediately; clear config
1611                          * later if it fails the request.
1612                          */
1613                         if (udc->ep0_reset_config)
1614                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1615                         else
1616                                 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1617                         update_otg(udc);
1618                         goto delegate;
1619                 case USB_REQ_CLEAR_FEATURE:
1620                         /* clear endpoint halt */
1621                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1622                                 goto delegate;
1623                         if (w_value != USB_ENDPOINT_HALT
1624                                         || w_length != 0)
1625                                 goto do_stall;
1626                         ep = &udc->ep[w_index & 0xf];
1627                         if (ep != ep0) {
1628                                 if (w_index & USB_DIR_IN)
1629                                         ep += 16;
1630                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1631                                                 || !ep->desc)
1632                                         goto do_stall;
1633                                 use_ep(ep, 0);
1634                                 omap_writew(udc->clr_halt, UDC_CTRL);
1635                                 ep->ackwait = 0;
1636                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1637                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1638                                         ep->ackwait = 1 + ep->double_buf;
1639                                 }
1640                                 /* NOTE:  assumes the host behaves sanely,
1641                                  * only clearing real halts.  Else we may
1642                                  * need to kill pending transfers and then
1643                                  * restart the queue... very messy for DMA!
1644                                  */
1645                         }
1646                         VDBG("%s halt cleared by host\n", ep->name);
1647                         goto ep0out_status_stage;
1648                 case USB_REQ_SET_FEATURE:
1649                         /* set endpoint halt */
1650                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1651                                 goto delegate;
1652                         if (w_value != USB_ENDPOINT_HALT
1653                                         || w_length != 0)
1654                                 goto do_stall;
1655                         ep = &udc->ep[w_index & 0xf];
1656                         if (w_index & USB_DIR_IN)
1657                                 ep += 16;
1658                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1659                                         || ep == ep0 || !ep->desc)
1660                                 goto do_stall;
1661                         if (use_dma && ep->has_dma) {
1662                                 /* this has rude side-effects (aborts) and
1663                                  * can't really work if DMA-IN is active
1664                                  */
1665                                 DBG("%s host set_halt, NYET \n", ep->name);
1666                                 goto do_stall;
1667                         }
1668                         use_ep(ep, 0);
1669                         /* can't halt if fifo isn't empty... */
1670                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1671                         omap_writew(UDC_SET_HALT, UDC_CTRL);
1672                         VDBG("%s halted by host\n", ep->name);
1673 ep0out_status_stage:
1674                         status = 0;
1675                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1676                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1677                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1678                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1679                         udc->ep0_pending = 0;
1680                         break;
1681                 case USB_REQ_GET_STATUS:
1682                         /* USB_ENDPOINT_HALT status? */
1683                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1684                                 goto intf_status;
1685
1686                         /* ep0 never stalls */
1687                         if (!(w_index & 0xf))
1688                                 goto zero_status;
1689
1690                         /* only active endpoints count */
1691                         ep = &udc->ep[w_index & 0xf];
1692                         if (w_index & USB_DIR_IN)
1693                                 ep += 16;
1694                         if (!ep->desc)
1695                                 goto do_stall;
1696
1697                         /* iso never stalls */
1698                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1699                                 goto zero_status;
1700
1701                         /* FIXME don't assume non-halted endpoints!! */
1702                         ERR("%s status, can't report\n", ep->ep.name);
1703                         goto do_stall;
1704
1705 intf_status:
1706                         /* return interface status.  if we were pedantic,
1707                          * we'd detect non-existent interfaces, and stall.
1708                          */
1709                         if (u.r.bRequestType
1710                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1711                                 goto delegate;
1712
1713 zero_status:
1714                         /* return two zero bytes */
1715                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1716                         omap_writew(0, UDC_DATA);
1717                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1718                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1719                         status = 0;
1720                         VDBG("GET_STATUS, interface %d\n", w_index);
1721                         /* next, status stage */
1722                         break;
1723                 default:
1724 delegate:
1725                         /* activate the ep0out fifo right away */
1726                         if (!udc->ep0_in && w_length) {
1727                                 omap_writew(0, UDC_EP_NUM);
1728                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1729                         }
1730
1731                         /* gadget drivers see class/vendor specific requests,
1732                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1733                          * and more
1734                          */
1735                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1736                                 u.r.bRequestType, u.r.bRequest,
1737                                 w_value, w_index, w_length);
1738
1739 #undef  w_value
1740 #undef  w_index
1741 #undef  w_length
1742
1743                         /* The gadget driver may return an error here,
1744                          * causing an immediate protocol stall.
1745                          *
1746                          * Else it must issue a response, either queueing a
1747                          * response buffer for the DATA stage, or halting ep0
1748                          * (causing a protocol stall, not a real halt).  A
1749                          * zero length buffer means no DATA stage.
1750                          *
1751                          * It's fine to issue that response after the setup()
1752                          * call returns, and this IRQ was handled.
1753                          */
1754                         udc->ep0_setup = 1;
1755                         spin_unlock(&udc->lock);
1756                         status = udc->driver->setup (&udc->gadget, &u.r);
1757                         spin_lock(&udc->lock);
1758                         udc->ep0_setup = 0;
1759                 }
1760
1761                 if (status < 0) {
1762 do_stall:
1763                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1764                                         u.r.bRequestType, u.r.bRequest, status);
1765                         if (udc->ep0_set_config) {
1766                                 if (udc->ep0_reset_config)
1767                                         WARNING("error resetting config?\n");
1768                                 else
1769                                         omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1770                         }
1771                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1772                         udc->ep0_pending = 0;
1773                 }
1774         }
1775 }
1776
1777 /*-------------------------------------------------------------------------*/
1778
1779 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1780
1781 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1782 {
1783         u16     devstat, change;
1784
1785         devstat = omap_readw(UDC_DEVSTAT);
1786         change = devstat ^ udc->devstat;
1787         udc->devstat = devstat;
1788
1789         if (change & (UDC_USB_RESET|UDC_ATT)) {
1790                 udc_quiesce(udc);
1791
1792                 if (change & UDC_ATT) {
1793                         /* driver for any external transceiver will
1794                          * have called omap_vbus_session() already
1795                          */
1796                         if (devstat & UDC_ATT) {
1797                                 udc->gadget.speed = USB_SPEED_FULL;
1798                                 VDBG("connect\n");
1799                                 if (!udc->transceiver)
1800                                         pullup_enable(udc);
1801                                 // if (driver->connect) call it
1802                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1803                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1804                                 if (!udc->transceiver)
1805                                         pullup_disable(udc);
1806                                 DBG("disconnect, gadget %s\n",
1807                                         udc->driver->driver.name);
1808                                 if (udc->driver->disconnect) {
1809                                         spin_unlock(&udc->lock);
1810                                         udc->driver->disconnect(&udc->gadget);
1811                                         spin_lock(&udc->lock);
1812                                 }
1813                         }
1814                         change &= ~UDC_ATT;
1815                 }
1816
1817                 if (change & UDC_USB_RESET) {
1818                         if (devstat & UDC_USB_RESET) {
1819                                 VDBG("RESET=1\n");
1820                         } else {
1821                                 udc->gadget.speed = USB_SPEED_FULL;
1822                                 INFO("USB reset done, gadget %s\n",
1823                                         udc->driver->driver.name);
1824                                 /* ep0 traffic is legal from now on */
1825                                 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1826                                                 UDC_IRQ_EN);
1827                         }
1828                         change &= ~UDC_USB_RESET;
1829                 }
1830         }
1831         if (change & UDC_SUS) {
1832                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1833                         // FIXME tell isp1301 to suspend/resume (?)
1834                         if (devstat & UDC_SUS) {
1835                                 VDBG("suspend\n");
1836                                 update_otg(udc);
1837                                 /* HNP could be under way already */
1838                                 if (udc->gadget.speed == USB_SPEED_FULL
1839                                                 && udc->driver->suspend) {
1840                                         spin_unlock(&udc->lock);
1841                                         udc->driver->suspend(&udc->gadget);
1842                                         spin_lock(&udc->lock);
1843                                 }
1844                                 if (udc->transceiver)
1845                                         otg_set_suspend(udc->transceiver, 1);
1846                         } else {
1847                                 VDBG("resume\n");
1848                                 if (udc->transceiver)
1849                                         otg_set_suspend(udc->transceiver, 0);
1850                                 if (udc->gadget.speed == USB_SPEED_FULL
1851                                                 && udc->driver->resume) {
1852                                         spin_unlock(&udc->lock);
1853                                         udc->driver->resume(&udc->gadget);
1854                                         spin_lock(&udc->lock);
1855                                 }
1856                         }
1857                 }
1858                 change &= ~UDC_SUS;
1859         }
1860         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1861                 update_otg(udc);
1862                 change &= ~OTG_FLAGS;
1863         }
1864
1865         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1866         if (change)
1867                 VDBG("devstat %03x, ignore change %03x\n",
1868                         devstat,  change);
1869
1870         omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1871 }
1872
1873 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1874 {
1875         struct omap_udc *udc = _udc;
1876         u16             irq_src;
1877         irqreturn_t     status = IRQ_NONE;
1878         unsigned long   flags;
1879
1880         spin_lock_irqsave(&udc->lock, flags);
1881         irq_src = omap_readw(UDC_IRQ_SRC);
1882
1883         /* Device state change (usb ch9 stuff) */
1884         if (irq_src & UDC_DS_CHG) {
1885                 devstate_irq(_udc, irq_src);
1886                 status = IRQ_HANDLED;
1887                 irq_src &= ~UDC_DS_CHG;
1888         }
1889
1890         /* EP0 control transfers */
1891         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1892                 ep0_irq(_udc, irq_src);
1893                 status = IRQ_HANDLED;
1894                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1895         }
1896
1897         /* DMA transfer completion */
1898         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1899                 dma_irq(_udc, irq_src);
1900                 status = IRQ_HANDLED;
1901                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1902         }
1903
1904         irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1905         if (irq_src)
1906                 DBG("udc_irq, unhandled %03x\n", irq_src);
1907         spin_unlock_irqrestore(&udc->lock, flags);
1908
1909         return status;
1910 }
1911
1912 /* workaround for seemingly-lost IRQs for RX ACKs... */
1913 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1914 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1915
1916 static void pio_out_timer(unsigned long _ep)
1917 {
1918         struct omap_ep  *ep = (void *) _ep;
1919         unsigned long   flags;
1920         u16             stat_flg;
1921
1922         spin_lock_irqsave(&ep->udc->lock, flags);
1923         if (!list_empty(&ep->queue) && ep->ackwait) {
1924                 use_ep(ep, UDC_EP_SEL);
1925                 stat_flg = omap_readw(UDC_STAT_FLG);
1926
1927                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1928                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1929                         struct omap_req *req;
1930
1931                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1932                         req = container_of(ep->queue.next,
1933                                         struct omap_req, queue);
1934                         (void) read_fifo(ep, req);
1935                         omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1936                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1937                         ep->ackwait = 1 + ep->double_buf;
1938                 } else
1939                         deselect_ep();
1940         }
1941         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1942         spin_unlock_irqrestore(&ep->udc->lock, flags);
1943 }
1944
1945 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1946 {
1947         u16             epn_stat, irq_src;
1948         irqreturn_t     status = IRQ_NONE;
1949         struct omap_ep  *ep;
1950         int             epnum;
1951         struct omap_udc *udc = _dev;
1952         struct omap_req *req;
1953         unsigned long   flags;
1954
1955         spin_lock_irqsave(&udc->lock, flags);
1956         epn_stat = omap_readw(UDC_EPN_STAT);
1957         irq_src = omap_readw(UDC_IRQ_SRC);
1958
1959         /* handle OUT first, to avoid some wasteful NAKs */
1960         if (irq_src & UDC_EPN_RX) {
1961                 epnum = (epn_stat >> 8) & 0x0f;
1962                 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1963                 status = IRQ_HANDLED;
1964                 ep = &udc->ep[epnum];
1965                 ep->irqs++;
1966
1967                 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1968                 ep->fnf = 0;
1969                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1970                         ep->ackwait--;
1971                         if (!list_empty(&ep->queue)) {
1972                                 int stat;
1973                                 req = container_of(ep->queue.next,
1974                                                 struct omap_req, queue);
1975                                 stat = read_fifo(ep, req);
1976                                 if (!ep->double_buf)
1977                                         ep->fnf = 1;
1978                         }
1979                 }
1980                 /* min 6 clock delay before clearing EP_SEL ... */
1981                 epn_stat = omap_readw(UDC_EPN_STAT);
1982                 epn_stat = omap_readw(UDC_EPN_STAT);
1983                 omap_writew(epnum, UDC_EP_NUM);
1984
1985                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1986                  * reduces lossage; timer still needed though (sigh).
1987                  */
1988                 if (ep->fnf) {
1989                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1990                         ep->ackwait = 1 + ep->double_buf;
1991                 }
1992                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1993         }
1994
1995         /* then IN transfers */
1996         else if (irq_src & UDC_EPN_TX) {
1997                 epnum = epn_stat & 0x0f;
1998                 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1999                 status = IRQ_HANDLED;
2000                 ep = &udc->ep[16 + epnum];
2001                 ep->irqs++;
2002
2003                 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2004                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2005                         ep->ackwait = 0;
2006                         if (!list_empty(&ep->queue)) {
2007                                 req = container_of(ep->queue.next,
2008                                                 struct omap_req, queue);
2009                                 (void) write_fifo(ep, req);
2010                         }
2011                 }
2012                 /* min 6 clock delay before clearing EP_SEL ... */
2013                 epn_stat = omap_readw(UDC_EPN_STAT);
2014                 epn_stat = omap_readw(UDC_EPN_STAT);
2015                 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2016                 /* then 6 clocks before it'd tx */
2017         }
2018
2019         spin_unlock_irqrestore(&udc->lock, flags);
2020         return status;
2021 }
2022
2023 #ifdef  USE_ISO
2024 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2025 {
2026         struct omap_udc *udc = _dev;
2027         struct omap_ep  *ep;
2028         int             pending = 0;
2029         unsigned long   flags;
2030
2031         spin_lock_irqsave(&udc->lock, flags);
2032
2033         /* handle all non-DMA ISO transfers */
2034         list_for_each_entry (ep, &udc->iso, iso) {
2035                 u16             stat;
2036                 struct omap_req *req;
2037
2038                 if (ep->has_dma || list_empty(&ep->queue))
2039                         continue;
2040                 req = list_entry(ep->queue.next, struct omap_req, queue);
2041
2042                 use_ep(ep, UDC_EP_SEL);
2043                 stat = omap_readw(UDC_STAT_FLG);
2044
2045                 /* NOTE: like the other controller drivers, this isn't
2046                  * currently reporting lost or damaged frames.
2047                  */
2048                 if (ep->bEndpointAddress & USB_DIR_IN) {
2049                         if (stat & UDC_MISS_IN)
2050                                 /* done(ep, req, -EPROTO) */;
2051                         else
2052                                 write_fifo(ep, req);
2053                 } else {
2054                         int     status = 0;
2055
2056                         if (stat & UDC_NO_RXPACKET)
2057                                 status = -EREMOTEIO;
2058                         else if (stat & UDC_ISO_ERR)
2059                                 status = -EILSEQ;
2060                         else if (stat & UDC_DATA_FLUSH)
2061                                 status = -ENOSR;
2062
2063                         if (status)
2064                                 /* done(ep, req, status) */;
2065                         else
2066                                 read_fifo(ep, req);
2067                 }
2068                 deselect_ep();
2069                 /* 6 wait states before next EP */
2070
2071                 ep->irqs++;
2072                 if (!list_empty(&ep->queue))
2073                         pending = 1;
2074         }
2075         if (!pending) {
2076                 u16 w;
2077
2078                 w = omap_readw(UDC_IRQ_EN);
2079                 w &= ~UDC_SOF_IE;
2080                 omap_writew(w, UDC_IRQ_EN);
2081         }
2082         omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2083
2084         spin_unlock_irqrestore(&udc->lock, flags);
2085         return IRQ_HANDLED;
2086 }
2087 #endif
2088
2089 /*-------------------------------------------------------------------------*/
2090
2091 static inline int machine_without_vbus_sense(void)
2092 {
2093         return (machine_is_omap_innovator()
2094                 || machine_is_omap_osk()
2095                 || machine_is_omap_apollon()
2096 #ifndef CONFIG_MACH_OMAP_H4_OTG
2097                 || machine_is_omap_h4()
2098 #endif
2099                 || machine_is_sx1()
2100                 );
2101 }
2102
2103 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2104 {
2105         int             status = -ENODEV;
2106         struct omap_ep  *ep;
2107         unsigned long   flags;
2108
2109         /* basic sanity tests */
2110         if (!udc)
2111                 return -ENODEV;
2112         if (!driver
2113                         // FIXME if otg, check:  driver->is_otg
2114                         || driver->speed < USB_SPEED_FULL
2115                         || !driver->bind
2116                         || !driver->setup)
2117                 return -EINVAL;
2118
2119         spin_lock_irqsave(&udc->lock, flags);
2120         if (udc->driver) {
2121                 spin_unlock_irqrestore(&udc->lock, flags);
2122                 return -EBUSY;
2123         }
2124
2125         /* reset state */
2126         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2127                 ep->irqs = 0;
2128                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2129                         continue;
2130                 use_ep(ep, 0);
2131                 omap_writew(UDC_SET_HALT, UDC_CTRL);
2132         }
2133         udc->ep0_pending = 0;
2134         udc->ep[0].irqs = 0;
2135         udc->softconnect = 1;
2136
2137         /* hook up the driver */
2138         driver->driver.bus = NULL;
2139         udc->driver = driver;
2140         udc->gadget.dev.driver = &driver->driver;
2141         spin_unlock_irqrestore(&udc->lock, flags);
2142
2143         if (udc->dc_clk != NULL)
2144                 omap_udc_enable_clock(1);
2145
2146         status = driver->bind (&udc->gadget);
2147         if (status) {
2148                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2149                 udc->gadget.dev.driver = NULL;
2150                 udc->driver = NULL;
2151                 goto done;
2152         }
2153         DBG("bound to driver %s\n", driver->driver.name);
2154
2155         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2156
2157         /* connect to bus through transceiver */
2158         if (udc->transceiver) {
2159                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2160                 if (status < 0) {
2161                         ERR("can't bind to transceiver\n");
2162                         if (driver->unbind) {
2163                                 driver->unbind (&udc->gadget);
2164                                 udc->gadget.dev.driver = NULL;
2165                                 udc->driver = NULL;
2166                         }
2167                         goto done;
2168                 }
2169         } else {
2170                 if (can_pullup(udc))
2171                         pullup_enable (udc);
2172                 else
2173                         pullup_disable (udc);
2174         }
2175
2176         /* boards that don't have VBUS sensing can't autogate 48MHz;
2177          * can't enter deep sleep while a gadget driver is active.
2178          */
2179         if (machine_without_vbus_sense())
2180                 omap_vbus_session(&udc->gadget, 1);
2181
2182 done:
2183         if (udc->dc_clk != NULL)
2184                 omap_udc_enable_clock(0);
2185         return status;
2186 }
2187 EXPORT_SYMBOL(usb_gadget_register_driver);
2188
2189 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2190 {
2191         unsigned long   flags;
2192         int             status = -ENODEV;
2193
2194         if (!udc)
2195                 return -ENODEV;
2196         if (!driver || driver != udc->driver || !driver->unbind)
2197                 return -EINVAL;
2198
2199         if (udc->dc_clk != NULL)
2200                 omap_udc_enable_clock(1);
2201
2202         if (machine_without_vbus_sense())
2203                 omap_vbus_session(&udc->gadget, 0);
2204
2205         if (udc->transceiver)
2206                 (void) otg_set_peripheral(udc->transceiver, NULL);
2207         else
2208                 pullup_disable(udc);
2209
2210         spin_lock_irqsave(&udc->lock, flags);
2211         udc_quiesce(udc);
2212         spin_unlock_irqrestore(&udc->lock, flags);
2213
2214         driver->unbind(&udc->gadget);
2215         udc->gadget.dev.driver = NULL;
2216         udc->driver = NULL;
2217
2218         if (udc->dc_clk != NULL)
2219                 omap_udc_enable_clock(0);
2220         DBG("unregistered driver '%s'\n", driver->driver.name);
2221         return status;
2222 }
2223 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2224
2225
2226 /*-------------------------------------------------------------------------*/
2227
2228 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2229
2230 #include <linux/seq_file.h>
2231
2232 static const char proc_filename[] = "driver/udc";
2233
2234 #define FOURBITS "%s%s%s%s"
2235 #define EIGHTBITS FOURBITS FOURBITS
2236
2237 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2238 {
2239         u16             stat_flg;
2240         struct omap_req *req;
2241         char            buf[20];
2242
2243         use_ep(ep, 0);
2244
2245         if (use_dma && ep->has_dma)
2246                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2247                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2248                         ep->dma_channel - 1, ep->lch);
2249         else
2250                 buf[0] = 0;
2251
2252         stat_flg = omap_readw(UDC_STAT_FLG);
2253         seq_printf(s,
2254                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2255                 ep->name, buf,
2256                 ep->double_buf ? "dbuf " : "",
2257                 ({char *s; switch(ep->ackwait){
2258                 case 0: s = ""; break;
2259                 case 1: s = "(ackw) "; break;
2260                 case 2: s = "(ackw2) "; break;
2261                 default: s = "(?) "; break;
2262                 } s;}),
2263                 ep->irqs, stat_flg,
2264                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2265                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2266                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2267                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2268                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2269                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2270                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2271                 (stat_flg & UDC_STALL) ? "STALL " : "",
2272                 (stat_flg & UDC_NAK) ? "NAK " : "",
2273                 (stat_flg & UDC_ACK) ? "ACK " : "",
2274                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2275                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2276                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2277
2278         if (list_empty (&ep->queue))
2279                 seq_printf(s, "\t(queue empty)\n");
2280         else
2281                 list_for_each_entry (req, &ep->queue, queue) {
2282                         unsigned        length = req->req.actual;
2283
2284                         if (use_dma && buf[0]) {
2285                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2286                                                 ? dma_src_len : dma_dest_len)
2287                                         (ep, req->req.dma + length);
2288                                 buf[0] = 0;
2289                         }
2290                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2291                                         &req->req, length,
2292                                         req->req.length, req->req.buf);
2293                 }
2294 }
2295
2296 static char *trx_mode(unsigned m, int enabled)
2297 {
2298         switch (m) {
2299         case 0:         return enabled ? "*6wire" : "unused";
2300         case 1:         return "4wire";
2301         case 2:         return "3wire";
2302         case 3:         return "6wire";
2303         default:        return "unknown";
2304         }
2305 }
2306
2307 static int proc_otg_show(struct seq_file *s)
2308 {
2309         u32             tmp;
2310         u32             trans;
2311         char            *ctrl_name;
2312
2313         tmp = OTG_REV_REG;
2314         if (cpu_is_omap24xx()) {
2315                 ctrl_name = "control_devconf";
2316                 trans = CONTROL_DEVCONF_REG;
2317         } else {
2318                 ctrl_name = "tranceiver_ctrl";
2319                 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2320         }
2321         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2322                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2323         tmp = omap_readw(OTG_SYSCON_1);
2324         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2325                         FOURBITS "\n", tmp,
2326                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2327                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2328                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2329                         ? "internal"
2330                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2331                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2332                 (tmp & HST_IDLE_EN) ? " !host" : "",
2333                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2334                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2335         tmp = omap_readl(OTG_SYSCON_2);
2336         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2337                         " b_ase_brst=%d hmc=%d\n", tmp,
2338                 (tmp & OTG_EN) ? " otg_en" : "",
2339                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2340                 // much more SRP stuff
2341                 (tmp & SRP_DATA) ? " srp_data" : "",
2342                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2343                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2344                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2345                 (tmp & UHOST_EN) ? " uhost_en" : "",
2346                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2347                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2348                 B_ASE_BRST(tmp),
2349                 OTG_HMC(tmp));
2350         tmp = omap_readl(OTG_CTRL);
2351         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2352                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2353                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2354                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2355                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2356                 (tmp & OTG_ID) ? " id" : "",
2357                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2358                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2359                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2360                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2361                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2362                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2363                 (tmp & OTG_PULLDOWN) ? " down" : "",
2364                 (tmp & OTG_PULLUP) ? " up" : "",
2365                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2366                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2367                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2368                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2369                 );
2370         tmp = omap_readw(OTG_IRQ_EN);
2371         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2372         tmp = omap_readw(OTG_IRQ_SRC);
2373         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2374         tmp = omap_readw(OTG_OUTCTRL);
2375         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2376         tmp = omap_readw(OTG_TEST);
2377         seq_printf(s, "otg_test    %04x" "\n", tmp);
2378         return 0;
2379 }
2380
2381 static int proc_udc_show(struct seq_file *s, void *_)
2382 {
2383         u32             tmp;
2384         struct omap_ep  *ep;
2385         unsigned long   flags;
2386
2387         spin_lock_irqsave(&udc->lock, flags);
2388
2389         seq_printf(s, "%s, version: " DRIVER_VERSION
2390 #ifdef  USE_ISO
2391                 " (iso)"
2392 #endif
2393                 "%s\n",
2394                 driver_desc,
2395                 use_dma ?  " (dma)" : "");
2396
2397         tmp = omap_readw(UDC_REV) & 0xff;
2398         seq_printf(s,
2399                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2400                 "hmc %d, transceiver %s\n",
2401                 tmp >> 4, tmp & 0xf,
2402                 fifo_mode,
2403                 udc->driver ? udc->driver->driver.name : "(none)",
2404                 HMC,
2405                 udc->transceiver
2406                         ? udc->transceiver->label
2407                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2408                                 ? "external" : "(none)"));
2409         if (cpu_class_is_omap1()) {
2410                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2411                         omap_readw(ULPD_CLOCK_CTRL),
2412                         omap_readw(ULPD_SOFT_REQ),
2413                         omap_readw(ULPD_STATUS_REQ));
2414         }
2415
2416         /* OTG controller registers */
2417         if (!cpu_is_omap15xx())
2418                 proc_otg_show(s);
2419
2420         tmp = omap_readw(UDC_SYSCON1);
2421         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2422                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2423                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2424                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2425                 (tmp & UDC_NAK_EN) ? " nak" : "",
2426                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2427                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2428                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2429                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2430         // syscon2 is write-only
2431
2432         /* UDC controller registers */
2433         if (!(tmp & UDC_PULLUP_EN)) {
2434                 seq_printf(s, "(suspended)\n");
2435                 spin_unlock_irqrestore(&udc->lock, flags);
2436                 return 0;
2437         }
2438
2439         tmp = omap_readw(UDC_DEVSTAT);
2440         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2441                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2442                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2443                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2444                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2445                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2446                 (tmp & UDC_SUS) ? " SUS" : "",
2447                 (tmp & UDC_CFG) ? " CFG" : "",
2448                 (tmp & UDC_ADD) ? " ADD" : "",
2449                 (tmp & UDC_DEF) ? " DEF" : "",
2450                 (tmp & UDC_ATT) ? " ATT" : "");
2451         seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2452         tmp = omap_readw(UDC_IRQ_EN);
2453         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2454                 (tmp & UDC_SOF_IE) ? " sof" : "",
2455                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2456                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2457                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2458                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2459         tmp = omap_readw(UDC_IRQ_SRC);
2460         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2461                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2462                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2463                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2464                 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2465                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2466                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2467                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2468                 (tmp & UDC_SETUP) ? " setup" : "",
2469                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2470                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2471         if (use_dma) {
2472                 unsigned i;
2473
2474                 tmp = omap_readw(UDC_DMA_IRQ_EN);
2475                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2476                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2477                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2478                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2479
2480                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2481                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2482                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2483
2484                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2485                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2486                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2487
2488                 tmp = omap_readw(UDC_RXDMA_CFG);
2489                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2490                 if (tmp) {
2491                         for (i = 0; i < 3; i++) {
2492                                 if ((tmp & (0x0f << (i * 4))) == 0)
2493                                         continue;
2494                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2495                                                 omap_readw(UDC_RXDMA(i + 1)));
2496                         }
2497                 }
2498                 tmp = omap_readw(UDC_TXDMA_CFG);
2499                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2500                 if (tmp) {
2501                         for (i = 0; i < 3; i++) {
2502                                 if (!(tmp & (0x0f << (i * 4))))
2503                                         continue;
2504                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2505                                                 omap_readw(UDC_TXDMA(i + 1)));
2506                         }
2507                 }
2508         }
2509
2510         tmp = omap_readw(UDC_DEVSTAT);
2511         if (tmp & UDC_ATT) {
2512                 proc_ep_show(s, &udc->ep[0]);
2513                 if (tmp & UDC_ADD) {
2514                         list_for_each_entry (ep, &udc->gadget.ep_list,
2515                                         ep.ep_list) {
2516                                 if (ep->desc)
2517                                         proc_ep_show(s, ep);
2518                         }
2519                 }
2520         }
2521         spin_unlock_irqrestore(&udc->lock, flags);
2522         return 0;
2523 }
2524
2525 static int proc_udc_open(struct inode *inode, struct file *file)
2526 {
2527         return single_open(file, proc_udc_show, NULL);
2528 }
2529
2530 static const struct file_operations proc_ops = {
2531         .owner          = THIS_MODULE,
2532         .open           = proc_udc_open,
2533         .read           = seq_read,
2534         .llseek         = seq_lseek,
2535         .release        = single_release,
2536 };
2537
2538 static void create_proc_file(void)
2539 {
2540         proc_create(proc_filename, 0, NULL, &proc_ops);
2541 }
2542
2543 static void remove_proc_file(void)
2544 {
2545         remove_proc_entry(proc_filename, NULL);
2546 }
2547
2548 #else
2549
2550 static inline void create_proc_file(void) {}
2551 static inline void remove_proc_file(void) {}
2552
2553 #endif
2554
2555 /*-------------------------------------------------------------------------*/
2556
2557 /* Before this controller can enumerate, we need to pick an endpoint
2558  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2559  * buffer space among the endpoints we'll be operating.
2560  *
2561  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2562  * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2563  * capability yet though.
2564  */
2565 static unsigned __init
2566 omap_ep_setup(char *name, u8 addr, u8 type,
2567                 unsigned buf, unsigned maxp, int dbuf)
2568 {
2569         struct omap_ep  *ep;
2570         u16             epn_rxtx = 0;
2571
2572         /* OUT endpoints first, then IN */
2573         ep = &udc->ep[addr & 0xf];
2574         if (addr & USB_DIR_IN)
2575                 ep += 16;
2576
2577         /* in case of ep init table bugs */
2578         BUG_ON(ep->name[0]);
2579
2580         /* chip setup ... bit values are same for IN, OUT */
2581         if (type == USB_ENDPOINT_XFER_ISOC) {
2582                 switch (maxp) {
2583                 case 8:         epn_rxtx = 0 << 12; break;
2584                 case 16:        epn_rxtx = 1 << 12; break;
2585                 case 32:        epn_rxtx = 2 << 12; break;
2586                 case 64:        epn_rxtx = 3 << 12; break;
2587                 case 128:       epn_rxtx = 4 << 12; break;
2588                 case 256:       epn_rxtx = 5 << 12; break;
2589                 case 512:       epn_rxtx = 6 << 12; break;
2590                 default:        BUG();
2591                 }
2592                 epn_rxtx |= UDC_EPN_RX_ISO;
2593                 dbuf = 1;
2594         } else {
2595                 /* double-buffering "not supported" on 15xx,
2596                  * and ignored for PIO-IN on newer chips
2597                  * (for more reliable behavior)
2598                  */
2599                 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2600                         dbuf = 0;
2601
2602                 switch (maxp) {
2603                 case 8:         epn_rxtx = 0 << 12; break;
2604                 case 16:        epn_rxtx = 1 << 12; break;
2605                 case 32:        epn_rxtx = 2 << 12; break;
2606                 case 64:        epn_rxtx = 3 << 12; break;
2607                 default:        BUG();
2608                 }
2609                 if (dbuf && addr)
2610                         epn_rxtx |= UDC_EPN_RX_DB;
2611                 init_timer(&ep->timer);
2612                 ep->timer.function = pio_out_timer;
2613                 ep->timer.data = (unsigned long) ep;
2614         }
2615         if (addr)
2616                 epn_rxtx |= UDC_EPN_RX_VALID;
2617         BUG_ON(buf & 0x07);
2618         epn_rxtx |= buf >> 3;
2619
2620         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2621                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2622
2623         if (addr & USB_DIR_IN)
2624                 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2625         else
2626                 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2627
2628         /* next endpoint's buffer starts after this one's */
2629         buf += maxp;
2630         if (dbuf)
2631                 buf += maxp;
2632         BUG_ON(buf > 2048);
2633
2634         /* set up driver data structures */
2635         BUG_ON(strlen(name) >= sizeof ep->name);
2636         strlcpy(ep->name, name, sizeof ep->name);
2637         INIT_LIST_HEAD(&ep->queue);
2638         INIT_LIST_HEAD(&ep->iso);
2639         ep->bEndpointAddress = addr;
2640         ep->bmAttributes = type;
2641         ep->double_buf = dbuf;
2642         ep->udc = udc;
2643
2644         ep->ep.name = ep->name;
2645         ep->ep.ops = &omap_ep_ops;
2646         ep->ep.maxpacket = ep->maxpacket = maxp;
2647         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2648
2649         return buf;
2650 }
2651
2652 static void omap_udc_release(struct device *dev)
2653 {
2654         complete(udc->done);
2655         kfree (udc);
2656         udc = NULL;
2657 }
2658
2659 static int __init
2660 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2661 {
2662         unsigned        tmp, buf;
2663
2664         /* abolish any previous hardware state */
2665         omap_writew(0, UDC_SYSCON1);
2666         omap_writew(0, UDC_IRQ_EN);
2667         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2668         omap_writew(0, UDC_DMA_IRQ_EN);
2669         omap_writew(0, UDC_RXDMA_CFG);
2670         omap_writew(0, UDC_TXDMA_CFG);
2671
2672         /* UDC_PULLUP_EN gates the chip clock */
2673         // OTG_SYSCON_1 |= DEV_IDLE_EN;
2674
2675         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2676         if (!udc)
2677                 return -ENOMEM;
2678
2679         spin_lock_init (&udc->lock);
2680
2681         udc->gadget.ops = &omap_gadget_ops;
2682         udc->gadget.ep0 = &udc->ep[0].ep;
2683         INIT_LIST_HEAD(&udc->gadget.ep_list);
2684         INIT_LIST_HEAD(&udc->iso);
2685         udc->gadget.speed = USB_SPEED_UNKNOWN;
2686         udc->gadget.name = driver_name;
2687
2688         device_initialize(&udc->gadget.dev);
2689         dev_set_name(&udc->gadget.dev, "gadget");
2690         udc->gadget.dev.release = omap_udc_release;
2691         udc->gadget.dev.parent = &odev->dev;
2692         if (use_dma)
2693                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2694
2695         udc->transceiver = xceiv;
2696
2697         /* ep0 is special; put it right after the SETUP buffer */
2698         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2699                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2700         list_del_init(&udc->ep[0].ep.ep_list);
2701
2702         /* initially disable all non-ep0 endpoints */
2703         for (tmp = 1; tmp < 15; tmp++) {
2704                 omap_writew(0, UDC_EP_RX(tmp));
2705                 omap_writew(0, UDC_EP_TX(tmp));
2706         }
2707
2708 #define OMAP_BULK_EP(name,addr) \
2709         buf = omap_ep_setup(name "-bulk", addr, \
2710                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2711 #define OMAP_INT_EP(name,addr, maxp) \
2712         buf = omap_ep_setup(name "-int", addr, \
2713                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2714 #define OMAP_ISO_EP(name,addr, maxp) \
2715         buf = omap_ep_setup(name "-iso", addr, \
2716                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2717
2718         switch (fifo_mode) {
2719         case 0:
2720                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2721                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2722                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2723                 break;
2724         case 1:
2725                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2726                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2727                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2728
2729                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2730                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2731                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2732
2733                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2734                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2735                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2736
2737                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2738                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2739                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2740
2741                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2742                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2743                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2744                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2745
2746                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2747                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2748                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2749                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2750
2751                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2752                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2753
2754                 break;
2755
2756 #ifdef  USE_ISO
2757         case 2:                 /* mixed iso/bulk */
2758                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2759                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2760                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2761                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2762
2763                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2764
2765                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2766                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2767                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2768                 break;
2769         case 3:                 /* mixed bulk/iso */
2770                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2771                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2772                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2773
2774                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2775                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2776                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2777
2778                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2779                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2780                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2781                 break;
2782 #endif
2783
2784         /* add more modes as needed */
2785
2786         default:
2787                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2788                 return -ENODEV;
2789         }
2790         omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2791         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2792         return 0;
2793 }
2794
2795 static int __init omap_udc_probe(struct platform_device *pdev)
2796 {
2797         int                     status = -ENODEV;
2798         int                     hmc;
2799         struct otg_transceiver  *xceiv = NULL;
2800         const char              *type = NULL;
2801         struct omap_usb_config  *config = pdev->dev.platform_data;
2802         struct clk              *dc_clk;
2803         struct clk              *hhc_clk;
2804
2805         /* NOTE:  "knows" the order of the resources! */
2806         if (!request_mem_region(pdev->resource[0].start,
2807                         pdev->resource[0].end - pdev->resource[0].start + 1,
2808                         driver_name)) {
2809                 DBG("request_mem_region failed\n");
2810                 return -EBUSY;
2811         }
2812
2813         if (cpu_is_omap16xx()) {
2814                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2815                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2816                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2817                 /* can't use omap_udc_enable_clock yet */
2818                 clk_enable(dc_clk);
2819                 clk_enable(hhc_clk);
2820                 udelay(100);
2821         }
2822
2823         if (cpu_is_omap24xx()) {
2824                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2825                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2826                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2827                 /* can't use omap_udc_enable_clock yet */
2828                 clk_enable(dc_clk);
2829                 clk_enable(hhc_clk);
2830                 udelay(100);
2831         }
2832
2833         INFO("OMAP UDC rev %d.%d%s\n",
2834                 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2835                 config->otg ? ", Mini-AB" : "");
2836
2837         /* use the mode given to us by board init code */
2838         if (cpu_is_omap15xx()) {
2839                 hmc = HMC_1510;
2840                 type = "(unknown)";
2841
2842                 if (machine_without_vbus_sense()) {
2843                         /* just set up software VBUS detect, and then
2844                          * later rig it so we always report VBUS.
2845                          * FIXME without really sensing VBUS, we can't
2846                          * know when to turn PULLUP_EN on/off; and that
2847                          * means we always "need" the 48MHz clock.
2848                          */
2849                         u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2850                         tmp &= ~VBUS_CTRL_1510;
2851                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2852                         tmp |= VBUS_MODE_1510;
2853                         tmp &= ~VBUS_CTRL_1510;
2854                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2855                 }
2856         } else {
2857                 /* The transceiver may package some GPIO logic or handle
2858                  * loopback and/or transceiverless setup; if we find one,
2859                  * use it.  Except for OTG, we don't _need_ to talk to one;
2860                  * but not having one probably means no VBUS detection.
2861                  */
2862                 xceiv = otg_get_transceiver();
2863                 if (xceiv)
2864                         type = xceiv->label;
2865                 else if (config->otg) {
2866                         DBG("OTG requires external transceiver!\n");
2867                         goto cleanup0;
2868                 }
2869
2870                 hmc = HMC_1610;
2871
2872                 if (cpu_is_omap24xx()) {
2873                         /* this could be transceiverless in one of the
2874                          * "we don't need to know" modes.
2875                          */
2876                         type = "external";
2877                         goto known;
2878                 }
2879
2880                 switch (hmc) {
2881                 case 0:                 /* POWERUP DEFAULT == 0 */
2882                 case 4:
2883                 case 12:
2884                 case 20:
2885                         if (!cpu_is_omap1710()) {
2886                                 type = "integrated";
2887                                 break;
2888                         }
2889                         /* FALL THROUGH */
2890                 case 3:
2891                 case 11:
2892                 case 16:
2893                 case 19:
2894                 case 25:
2895                         if (!xceiv) {
2896                                 DBG("external transceiver not registered!\n");
2897                                 type = "unknown";
2898                         }
2899                         break;
2900                 case 21:                        /* internal loopback */
2901                         type = "loopback";
2902                         break;
2903                 case 14:                        /* transceiverless */
2904                         if (cpu_is_omap1710())
2905                                 goto bad_on_1710;
2906                         /* FALL THROUGH */
2907                 case 13:
2908                 case 15:
2909                         type = "no";
2910                         break;
2911
2912                 default:
2913 bad_on_1710:
2914                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2915                         goto cleanup0;
2916                 }
2917         }
2918 known:
2919         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2920
2921         /* a "gadget" abstracts/virtualizes the controller */
2922         status = omap_udc_setup(pdev, xceiv);
2923         if (status) {
2924                 goto cleanup0;
2925         }
2926         xceiv = NULL;
2927         // "udc" is now valid
2928         pullup_disable(udc);
2929 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2930         udc->gadget.is_otg = (config->otg != 0);
2931 #endif
2932
2933         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2934         if (omap_readw(UDC_REV) >= 0x61)
2935                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2936         else
2937                 udc->clr_halt = UDC_RESET_EP;
2938
2939         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2940         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2941                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2942         if (status != 0) {
2943                 ERR("can't get irq %d, err %d\n",
2944                         (int) pdev->resource[1].start, status);
2945                 goto cleanup1;
2946         }
2947
2948         /* USB "non-iso" IRQ (PIO for all but ep0) */
2949         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2950                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2951         if (status != 0) {
2952                 ERR("can't get irq %d, err %d\n",
2953                         (int) pdev->resource[2].start, status);
2954                 goto cleanup2;
2955         }
2956 #ifdef  USE_ISO
2957         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2958                         IRQF_DISABLED, "omap_udc iso", udc);
2959         if (status != 0) {
2960                 ERR("can't get irq %d, err %d\n",
2961                         (int) pdev->resource[3].start, status);
2962                 goto cleanup3;
2963         }
2964 #endif
2965         if (cpu_is_omap16xx()) {
2966                 udc->dc_clk = dc_clk;
2967                 udc->hhc_clk = hhc_clk;
2968                 clk_disable(hhc_clk);
2969                 clk_disable(dc_clk);
2970         }
2971
2972         if (cpu_is_omap24xx()) {
2973                 udc->dc_clk = dc_clk;
2974                 udc->hhc_clk = hhc_clk;
2975                 /* FIXME OMAP2 don't release hhc & dc clock */
2976 #if 0
2977                 clk_disable(hhc_clk);
2978                 clk_disable(dc_clk);
2979 #endif
2980         }
2981
2982         create_proc_file();
2983         status = device_add(&udc->gadget.dev);
2984         if (!status)
2985                 return status;
2986         /* If fail, fall through */
2987 #ifdef  USE_ISO
2988 cleanup3:
2989         free_irq(pdev->resource[2].start, udc);
2990 #endif
2991
2992 cleanup2:
2993         free_irq(pdev->resource[1].start, udc);
2994
2995 cleanup1:
2996         kfree (udc);
2997         udc = NULL;
2998
2999 cleanup0:
3000         if (xceiv)
3001                 put_device(xceiv->dev);
3002
3003         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
3004                 clk_disable(hhc_clk);
3005                 clk_disable(dc_clk);
3006                 clk_put(hhc_clk);
3007                 clk_put(dc_clk);
3008         }
3009
3010         release_mem_region(pdev->resource[0].start,
3011                         pdev->resource[0].end - pdev->resource[0].start + 1);
3012
3013         return status;
3014 }
3015
3016 static int __exit omap_udc_remove(struct platform_device *pdev)
3017 {
3018         DECLARE_COMPLETION_ONSTACK(done);
3019
3020         if (!udc)
3021                 return -ENODEV;
3022         if (udc->driver)
3023                 return -EBUSY;
3024
3025         udc->done = &done;
3026
3027         pullup_disable(udc);
3028         if (udc->transceiver) {
3029                 put_device(udc->transceiver->dev);
3030                 udc->transceiver = NULL;
3031         }
3032         omap_writew(0, UDC_SYSCON1);
3033
3034         remove_proc_file();
3035
3036 #ifdef  USE_ISO
3037         free_irq(pdev->resource[3].start, udc);
3038 #endif
3039         free_irq(pdev->resource[2].start, udc);
3040         free_irq(pdev->resource[1].start, udc);
3041
3042         if (udc->dc_clk) {
3043                 if (udc->clk_requested)
3044                         omap_udc_enable_clock(0);
3045                 clk_put(udc->hhc_clk);
3046                 clk_put(udc->dc_clk);
3047         }
3048
3049         release_mem_region(pdev->resource[0].start,
3050                         pdev->resource[0].end - pdev->resource[0].start + 1);
3051
3052         device_unregister(&udc->gadget.dev);
3053         wait_for_completion(&done);
3054
3055         return 0;
3056 }
3057
3058 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3059  * system is forced into deep sleep
3060  *
3061  * REVISIT we should probably reject suspend requests when there's a host
3062  * session active, rather than disconnecting, at least on boards that can
3063  * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
3064  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3065  * may involve talking to an external transceiver (e.g. isp1301).
3066  */
3067
3068 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3069 {
3070         u32     devstat;
3071
3072         devstat = omap_readw(UDC_DEVSTAT);
3073
3074         /* we're requesting 48 MHz clock if the pullup is enabled
3075          * (== we're attached to the host) and we're not suspended,
3076          * which would prevent entry to deep sleep...
3077          */
3078         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3079                 WARNING("session active; suspend requires disconnect\n");
3080                 omap_pullup(&udc->gadget, 0);
3081         }
3082
3083         return 0;
3084 }
3085
3086 static int omap_udc_resume(struct platform_device *dev)
3087 {
3088         DBG("resume + wakeup/SRP\n");
3089         omap_pullup(&udc->gadget, 1);
3090
3091         /* maybe the host would enumerate us if we nudged it */
3092         msleep(100);
3093         return omap_wakeup(&udc->gadget);
3094 }
3095
3096 /*-------------------------------------------------------------------------*/
3097
3098 static struct platform_driver udc_driver = {
3099         .probe          = omap_udc_probe,
3100         .remove         = __exit_p(omap_udc_remove),
3101         .suspend        = omap_udc_suspend,
3102         .resume         = omap_udc_resume,
3103         .driver         = {
3104                 .owner  = THIS_MODULE,
3105                 .name   = (char *) driver_name,
3106         },
3107 };
3108
3109 static int __init udc_init(void)
3110 {
3111         INFO("%s, version: " DRIVER_VERSION
3112 #ifdef  USE_ISO
3113                 " (iso)"
3114 #endif
3115                 "%s\n", driver_desc,
3116                 use_dma ?  " (dma)" : "");
3117         return platform_driver_register(&udc_driver);
3118 }
3119 module_init(udc_init);
3120
3121 static void __exit udc_exit(void)
3122 {
3123         platform_driver_unregister(&udc_driver);
3124 }
3125 module_exit(udc_exit);
3126
3127 MODULE_DESCRIPTION(DRIVER_DESC);
3128 MODULE_LICENSE("GPL");
3129 MODULE_ALIAS("platform:omap_udc");