drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #undef  DEBUG
  23 #undef  VERBOSE
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/ioport.h>
  28 #include <linux/types.h>
  29 #include <linux/errno.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32 #include <linux/slab.h>
  33 #include <linux/init.h>
  34 #include <linux/timer.h>
  35 #include <linux/list.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/proc_fs.h>
  38 #include <linux/mm.h>
  39 #include <linux/moduleparam.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/usb_ch9.h>
  42 #include <linux/usb_gadget.h>
  43 #include <linux/usb/otg.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/clk.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/io.h>
  49 #include <asm/irq.h>
  50 #include <asm/system.h>
  51 #include <asm/unaligned.h>
  52 #include <asm/mach-types.h>
  53
  54 #include <asm/arch/dma.h>
  55 #include <asm/arch/usb.h>
  56
  57 #include "omap_udc.h"
  58
  59 #undef  USB_TRACE
  60
  61 /* bulk DMA seems to be behaving for both IN and OUT */
  62 #define USE_DMA
  63
  64 /* FIXME: OMAP2 currently has some problem in DMA mode */
  65 #ifdef CONFIG_ARCH_OMAP2
  66 #undef USE_DMA
  67 #endif
  68
  69 /* ISO too */
  70 #define USE_ISO
  71
  72 #define DRIVER_DESC     "OMAP UDC driver"
  73 #define DRIVER_VERSION  "4 October 2004"
  74
  75 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  76
  77
  78 /*
  79  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  80  * D+ pullup to allow enumeration.  That's too early for the gadget
  81  * framework to use from usb_endpoint_enable(), which happens after
  82  * enumeration as part of activating an interface.  (But if we add an
  83  * optional new "UDC not yet running" state to the gadget driver model,
  84  * even just during driver binding, the endpoint autoconfig logic is the
  85  * natural spot to manufacture new endpoints.)
  86  *
  87  * So instead of using endpoint enable calls to control the hardware setup,
  88  * this driver defines a "fifo mode" parameter.  It's used during driver
  89  * initialization to choose among a set of pre-defined endpoint configs.
  90  * See omap_udc_setup() for available modes, or to add others.  That code
  91  * lives in an init section, so use this driver as a module if you need
  92  * to change the fifo mode after the kernel boots.
  93  *
  94  * Gadget drivers normally ignore endpoints they don't care about, and
  95  * won't include them in configuration descriptors.  That means only
  96  * misbehaving hosts would even notice they exist.
  97  */
  98 #ifdef  USE_ISO
  99 static unsigned fifo_mode = 3;
 100 #else
 101 static unsigned fifo_mode = 0;
 102 #endif
 103
 104 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 105  * boot parameter "omap_udc:fifo_mode=42"
 106  */
 107 module_param (fifo_mode, uint, 0);
 108 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 109
 110 #ifdef  USE_DMA
 111 static unsigned use_dma = 1;
 112
 113 /* "modprobe omap_udc use_dma=y", or else as a kernel
 114  * boot parameter "omap_udc:use_dma=y"
 115  */
 116 module_param (use_dma, bool, 0);
 117 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 118 #else   /* !USE_DMA */
 119
 120 /* save a bit of code */
 121 #define use_dma         0
 122 #endif  /* !USE_DMA */
 123
 124
 125 static const char driver_name [] = "omap_udc";
 126 static const char driver_desc [] = DRIVER_DESC;
 127
 128 /*-------------------------------------------------------------------------*/
 129
 130 /* there's a notion of "current endpoint" for modifying endpoint
 131  * state, and PIO access to its FIFO.
 132  */
 133
 134 static void use_ep(struct omap_ep *ep, u16 select)
 135 {
 136         u16     num = ep->bEndpointAddress & 0x0f;
 137
 138         if (ep->bEndpointAddress & USB_DIR_IN)
 139                 num |= UDC_EP_DIR;
 140         UDC_EP_NUM_REG = num | select;
 141         /* when select, MUST deselect later !! */
 142 }
 143
 144 static inline void deselect_ep(void)
 145 {
 146         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 147         /* 6 wait states before TX will happen */
 148 }
 149
 150 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 151
 152 /*-------------------------------------------------------------------------*/
 153
 154 static int omap_ep_enable(struct usb_ep *_ep,
 155                 const struct usb_endpoint_descriptor *desc)
 156 {
 157         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 158         struct omap_udc *udc;
 159         unsigned long   flags;
 160         u16             maxp;
 161
 162         /* catch various bogus parameters */
 163         if (!_ep || !desc || ep->desc
 164                         || desc->bDescriptorType != USB_DT_ENDPOINT
 165                         || ep->bEndpointAddress != desc->bEndpointAddress
 166                         || ep->maxpacket < le16_to_cpu
 167                                                 (desc->wMaxPacketSize)) {
 168                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 169                 return -EINVAL;
 170         }
 171         maxp = le16_to_cpu (desc->wMaxPacketSize);
 172         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 173                                 && maxp != ep->maxpacket)
 174                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 175                         || !desc->wMaxPacketSize) {
 176                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 177                 return -ERANGE;
 178         }
 179
 180 #ifdef  USE_ISO
 181         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 182                                 && desc->bInterval != 1)) {
 183                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 184                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 185                                 1 << (desc->bInterval - 1));
 186                 return -EDOM;
 187         }
 188 #else
 189         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 190                 DBG("%s, ISO nyet\n", _ep->name);
 191                 return -EDOM;
 192         }
 193 #endif
 194
 195         /* xfer types must match, except that interrupt ~= bulk */
 196         if (ep->bmAttributes != desc->bmAttributes
 197                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 198                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 199                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 200                 return -EINVAL;
 201         }
 202
 203         udc = ep->udc;
 204         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 205                 DBG("%s, bogus device state\n", __FUNCTION__);
 206                 return -ESHUTDOWN;
 207         }
 208
 209         spin_lock_irqsave(&udc->lock, flags);
 210
 211         ep->desc = desc;
 212         ep->irqs = 0;
 213         ep->stopped = 0;
 214         ep->ep.maxpacket = maxp;
 215
 216         /* set endpoint to initial state */
 217         ep->dma_channel = 0;
 218         ep->has_dma = 0;
 219         ep->lch = -1;
 220         use_ep(ep, UDC_EP_SEL);
 221         UDC_CTRL_REG = udc->clr_halt;
 222         ep->ackwait = 0;
 223         deselect_ep();
 224
 225         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 226                 list_add(&ep->iso, &udc->iso);
 227
 228         /* maybe assign a DMA channel to this endpoint */
 229         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 230                 /* FIXME ISO can dma, but prefers first channel */
 231                 dma_channel_claim(ep, 0);
 232
 233         /* PIO OUT may RX packets */
 234         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 235                         && !ep->has_dma
 236                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 237                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 238                 ep->ackwait = 1 + ep->double_buf;
 239         }
 240
 241         spin_unlock_irqrestore(&udc->lock, flags);
 242         VDBG("%s enabled\n", _ep->name);
 243         return 0;
 244 }
 245
 246 static void nuke(struct omap_ep *, int status);
 247
 248 static int omap_ep_disable(struct usb_ep *_ep)
 249 {
 250         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 251         unsigned long   flags;
 252
 253         if (!_ep || !ep->desc) {
 254                 DBG("%s, %s not enabled\n", __FUNCTION__,
 255                         _ep ? ep->ep.name : NULL);
 256                 return -EINVAL;
 257         }
 258
 259         spin_lock_irqsave(&ep->udc->lock, flags);
 260         ep->desc = NULL;
 261         nuke (ep, -ESHUTDOWN);
 262         ep->ep.maxpacket = ep->maxpacket;
 263         ep->has_dma = 0;
 264         UDC_CTRL_REG = UDC_SET_HALT;
 265         list_del_init(&ep->iso);
 266         del_timer(&ep->timer);
 267
 268         spin_unlock_irqrestore(&ep->udc->lock, flags);
 269
 270         VDBG("%s disabled\n", _ep->name);
 271         return 0;
 272 }
 273
 274 /*-------------------------------------------------------------------------*/
 275
 276 static struct usb_request *
 277 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 278 {
 279         struct omap_req *req;
 280
 281         req = kzalloc(sizeof(*req), gfp_flags);
 282         if (req) {
 283                 req->req.dma = DMA_ADDR_INVALID;
 284                 INIT_LIST_HEAD (&req->queue);
 285         }
 286         return &req->req;
 287 }
 288
 289 static void
 290 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 291 {
 292         struct omap_req *req = container_of(_req, struct omap_req, req);
 293
 294         if (_req)
 295                 kfree (req);
 296 }
 297
 298 /*-------------------------------------------------------------------------*/
 299
 300 static void *
 301 omap_alloc_buffer(
 302         struct usb_ep   *_ep,
 303         unsigned        bytes,
 304         dma_addr_t      *dma,
 305         gfp_t           gfp_flags
 306 )
 307 {
 308         void            *retval;
 309         struct omap_ep  *ep;
 310
 311         ep = container_of(_ep, struct omap_ep, ep);
 312         if (use_dma && ep->has_dma) {
 313                 static int      warned;
 314                 if (!warned && bytes < PAGE_SIZE) {
 315                         dev_warn(ep->udc->gadget.dev.parent,
 316                                 "using dma_alloc_coherent for "
 317                                 "small allocations wastes memory\n");
 318                         warned++;
 319                 }
 320                 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
 321                                 bytes, dma, gfp_flags);
 322         }
 323
 324         retval = kmalloc(bytes, gfp_flags);
 325         if (retval)
 326                 *dma = virt_to_phys(retval);
 327         return retval;
 328 }
 329
 330 static void omap_free_buffer(
 331         struct usb_ep   *_ep,
 332         void            *buf,
 333         dma_addr_t      dma,
 334         unsigned        bytes
 335 )
 336 {
 337         struct omap_ep  *ep;
 338
 339         ep = container_of(_ep, struct omap_ep, ep);
 340         if (use_dma && _ep && ep->has_dma)
 341                 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
 342         else
 343                 kfree (buf);
 344 }
 345
 346 /*-------------------------------------------------------------------------*/
 347
 348 static void
 349 done(struct omap_ep *ep, struct omap_req *req, int status)
 350 {
 351         unsigned                stopped = ep->stopped;
 352
 353         list_del_init(&req->queue);
 354
 355         if (req->req.status == -EINPROGRESS)
 356                 req->req.status = status;
 357         else
 358                 status = req->req.status;
 359
 360         if (use_dma && ep->has_dma) {
 361                 if (req->mapped) {
 362                         dma_unmap_single(ep->udc->gadget.dev.parent,
 363                                 req->req.dma, req->req.length,
 364                                 (ep->bEndpointAddress & USB_DIR_IN)
 365                                         ? DMA_TO_DEVICE
 366                                         : DMA_FROM_DEVICE);
 367                         req->req.dma = DMA_ADDR_INVALID;
 368                         req->mapped = 0;
 369                 } else
 370                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 371                                 req->req.dma, req->req.length,
 372                                 (ep->bEndpointAddress & USB_DIR_IN)
 373                                         ? DMA_TO_DEVICE
 374                                         : DMA_FROM_DEVICE);
 375         }
 376
 377 #ifndef USB_TRACE
 378         if (status && status != -ESHUTDOWN)
 379 #endif
 380                 VDBG("complete %s req %p stat %d len %u/%u\n",
 381                         ep->ep.name, &req->req, status,
 382                         req->req.actual, req->req.length);
 383
 384         /* don't modify queue heads during completion callback */
 385         ep->stopped = 1;
 386         spin_unlock(&ep->udc->lock);
 387         req->req.complete(&ep->ep, &req->req);
 388         spin_lock(&ep->udc->lock);
 389         ep->stopped = stopped;
 390 }
 391
 392 /*-------------------------------------------------------------------------*/
 393
 394 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 395 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 396
 397 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 398 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 399
 400 static inline int
 401 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 402 {
 403         unsigned        len;
 404         u16             *wp;
 405
 406         len = min(req->req.length - req->req.actual, max);
 407         req->req.actual += len;
 408
 409         max = len;
 410         if (likely((((int)buf) & 1) == 0)) {
 411                 wp = (u16 *)buf;
 412                 while (max >= 2) {
 413                         UDC_DATA_REG = *wp++;
 414                         max -= 2;
 415                 }
 416                 buf = (u8 *)wp;
 417         }
 418         while (max--)
 419                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 420         return len;
 421 }
 422
 423 // FIXME change r/w fifo calling convention
 424
 425
 426 // return:  0 = still running, 1 = completed, negative = errno
 427 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 428 {
 429         u8              *buf;
 430         unsigned        count;
 431         int             is_last;
 432         u16             ep_stat;
 433
 434         buf = req->req.buf + req->req.actual;
 435         prefetch(buf);
 436
 437         /* PIO-IN isn't double buffered except for iso */
 438         ep_stat = UDC_STAT_FLG_REG;
 439         if (ep_stat & UDC_FIFO_UNWRITABLE)
 440                 return 0;
 441
 442         count = ep->ep.maxpacket;
 443         count = write_packet(buf, req, count);
 444         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 445         ep->ackwait = 1;
 446
 447         /* last packet is often short (sometimes a zlp) */
 448         if (count != ep->ep.maxpacket)
 449                 is_last = 1;
 450         else if (req->req.length == req->req.actual
 451                         && !req->req.zero)
 452                 is_last = 1;
 453         else
 454                 is_last = 0;
 455
 456         /* NOTE:  requests complete when all IN data is in a
 457          * FIFO (or sometimes later, if a zlp was needed).
 458          * Use usb_ep_fifo_status() where needed.
 459          */
 460         if (is_last)
 461                 done(ep, req, 0);
 462         return is_last;
 463 }
 464
 465 static inline int
 466 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 467 {
 468         unsigned        len;
 469         u16             *wp;
 470
 471         len = min(req->req.length - req->req.actual, avail);
 472         req->req.actual += len;
 473         avail = len;
 474
 475         if (likely((((int)buf) & 1) == 0)) {
 476                 wp = (u16 *)buf;
 477                 while (avail >= 2) {
 478                         *wp++ = UDC_DATA_REG;
 479                         avail -= 2;
 480                 }
 481                 buf = (u8 *)wp;
 482         }
 483         while (avail--)
 484                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 485         return len;
 486 }
 487
 488 // return:  0 = still running, 1 = queue empty, negative = errno
 489 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 490 {
 491         u8              *buf;
 492         unsigned        count, avail;
 493         int             is_last;
 494
 495         buf = req->req.buf + req->req.actual;
 496         prefetchw(buf);
 497
 498         for (;;) {
 499                 u16     ep_stat = UDC_STAT_FLG_REG;
 500
 501                 is_last = 0;
 502                 if (ep_stat & FIFO_EMPTY) {
 503                         if (!ep->double_buf)
 504                                 break;
 505                         ep->fnf = 1;
 506                 }
 507                 if (ep_stat & UDC_EP_HALTED)
 508                         break;
 509
 510                 if (ep_stat & UDC_FIFO_FULL)
 511                         avail = ep->ep.maxpacket;
 512                 else  {
 513                         avail = UDC_RXFSTAT_REG;
 514                         ep->fnf = ep->double_buf;
 515                 }
 516                 count = read_packet(buf, req, avail);
 517
 518                 /* partial packet reads may not be errors */
 519                 if (count < ep->ep.maxpacket) {
 520                         is_last = 1;
 521                         /* overflowed this request?  flush extra data */
 522                         if (count != avail) {
 523                                 req->req.status = -EOVERFLOW;
 524                                 avail -= count;
 525                                 while (avail--)
 526                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 527                         }
 528                 } else if (req->req.length == req->req.actual)
 529                         is_last = 1;
 530                 else
 531                         is_last = 0;
 532
 533                 if (!ep->bEndpointAddress)
 534                         break;
 535                 if (is_last)
 536                         done(ep, req, 0);
 537                 break;
 538         }
 539         return is_last;
 540 }
 541
 542 /*-------------------------------------------------------------------------*/
 543
 544 static inline dma_addr_t dma_csac(unsigned lch)
 545 {
 546         dma_addr_t      csac;
 547
 548         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 549          * read before the DMA controller finished disabling the channel.
 550          */
 551         csac = OMAP_DMA_CSAC_REG(lch);
 552         if (csac == 0)
 553                 csac = OMAP_DMA_CSAC_REG(lch);
 554         return csac;
 555 }
 556
 557 static inline dma_addr_t dma_cdac(unsigned lch)
 558 {
 559         dma_addr_t      cdac;
 560
 561         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 562          * read before the DMA controller finished disabling the channel.
 563          */
 564         cdac = OMAP_DMA_CDAC_REG(lch);
 565         if (cdac == 0)
 566                 cdac = OMAP_DMA_CDAC_REG(lch);
 567         return cdac;
 568 }
 569
 570 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 571 {
 572         dma_addr_t      end;
 573
 574         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 575          * the last transfer's bytecount by more than a FIFO's worth.
 576          */
 577         if (cpu_is_omap15xx())
 578                 return 0;
 579
 580         end = dma_csac(ep->lch);
 581         if (end == ep->dma_counter)
 582                 return 0;
 583
 584         end |= start & (0xffff << 16);
 585         if (end < start)
 586                 end += 0x10000;
 587         return end - start;
 588 }
 589
 590 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 591                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 592                 : dma_cdac(x))
 593
 594 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 595 {
 596         dma_addr_t      end;
 597
 598         end = DMA_DEST_LAST(ep->lch);
 599         if (end == ep->dma_counter)
 600                 return 0;
 601
 602         end |= start & (0xffff << 16);
 603         if (cpu_is_omap15xx())
 604                 end++;
 605         if (end < start)
 606                 end += 0x10000;
 607         return end - start;
 608 }
 609
 610
 611 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 612  * When DMA completion isn't request completion, the UDC continues with
 613  * the next DMA transfer for that USB transfer.
 614  */
 615
 616 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 617 {
 618         u16             txdma_ctrl;
 619         unsigned        length = req->req.length - req->req.actual;
 620         const int       sync_mode = cpu_is_omap15xx()
 621                                 ? OMAP_DMA_SYNC_FRAME
 622                                 : OMAP_DMA_SYNC_ELEMENT;
 623
 624         /* measure length in either bytes or packets */
 625         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 626                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 627                 txdma_ctrl = UDC_TXN_EOT | length;
 628                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 629                                 length, 1, sync_mode, 0, 0);
 630         } else {
 631                 length = min(length / ep->maxpacket,
 632                                 (unsigned) UDC_TXN_TSC + 1);
 633                 txdma_ctrl = length;
 634                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 635                                 ep->ep.maxpacket >> 1, length, sync_mode,
 636                                 0, 0);
 637                 length *= ep->maxpacket;
 638         }
 639         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 640                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 641                 0, 0);
 642
 643         omap_start_dma(ep->lch);
 644         ep->dma_counter = dma_csac(ep->lch);
 645         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 646         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 647         req->dma_bytes = length;
 648 }
 649
 650 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 651 {
 652         if (status == 0) {
 653                 req->req.actual += req->dma_bytes;
 654
 655                 /* return if this request needs to send data or zlp */
 656                 if (req->req.actual < req->req.length)
 657                         return;
 658                 if (req->req.zero
 659                                 && req->dma_bytes != 0
 660                                 && (req->req.actual % ep->maxpacket) == 0)
 661                         return;
 662         } else
 663                 req->req.actual += dma_src_len(ep, req->req.dma
 664                                                         + req->req.actual);
 665
 666         /* tx completion */
 667         omap_stop_dma(ep->lch);
 668         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 669         done(ep, req, status);
 670 }
 671
 672 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 673 {
 674         unsigned packets;
 675
 676         /* NOTE:  we filtered out "short reads" before, so we know
 677          * the buffer has only whole numbers of packets.
 678          */
 679
 680         /* set up this DMA transfer, enable the fifo, start */
 681         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
 682         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 683         req->dma_bytes = packets * ep->ep.maxpacket;
 684         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 685                         ep->ep.maxpacket >> 1, packets,
 686                         OMAP_DMA_SYNC_ELEMENT,
 687                         0, 0);
 688         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 689                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 690                 0, 0);
 691         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 692
 693         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 694         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 695         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 696         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 697
 698         omap_start_dma(ep->lch);
 699 }
 700
 701 static void
 702 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 703 {
 704         u16     count;
 705
 706         if (status == 0)
 707                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 708         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 709         count += req->req.actual;
 710         if (one)
 711                 count--;
 712         if (count <= req->req.length)
 713                 req->req.actual = count;
 714
 715         if (count != req->dma_bytes || status)
 716                 omap_stop_dma(ep->lch);
 717
 718         /* if this wasn't short, request may need another transfer */
 719         else if (req->req.actual < req->req.length)
 720                 return;
 721
 722         /* rx completion */
 723         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 724         done(ep, req, status);
 725 }
 726
 727 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 728 {
 729         u16             dman_stat = UDC_DMAN_STAT_REG;
 730         struct omap_ep  *ep;
 731         struct omap_req *req;
 732
 733         /* IN dma: tx to host */
 734         if (irq_src & UDC_TXN_DONE) {
 735                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 736                 ep->irqs++;
 737                 /* can see TXN_DONE after dma abort */
 738                 if (!list_empty(&ep->queue)) {
 739                         req = container_of(ep->queue.next,
 740                                                 struct omap_req, queue);
 741                         finish_in_dma(ep, req, 0);
 742                 }
 743                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 744
 745                 if (!list_empty (&ep->queue)) {
 746                         req = container_of(ep->queue.next,
 747                                         struct omap_req, queue);
 748                         next_in_dma(ep, req);
 749                 }
 750         }
 751
 752         /* OUT dma: rx from host */
 753         if (irq_src & UDC_RXN_EOT) {
 754                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 755                 ep->irqs++;
 756                 /* can see RXN_EOT after dma abort */
 757                 if (!list_empty(&ep->queue)) {
 758                         req = container_of(ep->queue.next,
 759                                         struct omap_req, queue);
 760                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 761                 }
 762                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 763
 764                 if (!list_empty (&ep->queue)) {
 765                         req = container_of(ep->queue.next,
 766                                         struct omap_req, queue);
 767                         next_out_dma(ep, req);
 768                 }
 769         }
 770
 771         if (irq_src & UDC_RXN_CNT) {
 772                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 773                 ep->irqs++;
 774                 /* omap15xx does this unasked... */
 775                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 776                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 777         }
 778 }
 779
 780 static void dma_error(int lch, u16 ch_status, void *data)
 781 {
 782         struct omap_ep  *ep = data;
 783
 784         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 785         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 786         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 787
 788         /* complete current transfer ... */
 789 }
 790
 791 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 792 {
 793         u16     reg;
 794         int     status, restart, is_in;
 795
 796         is_in = ep->bEndpointAddress & USB_DIR_IN;
 797         if (is_in)
 798                 reg = UDC_TXDMA_CFG_REG;
 799         else
 800                 reg = UDC_RXDMA_CFG_REG;
 801         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 802
 803         ep->dma_channel = 0;
 804         ep->lch = -1;
 805         if (channel == 0 || channel > 3) {
 806                 if ((reg & 0x0f00) == 0)
 807                         channel = 3;
 808                 else if ((reg & 0x00f0) == 0)
 809                         channel = 2;
 810                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 811                         channel = 1;
 812                 else {
 813                         status = -EMLINK;
 814                         goto just_restart;
 815                 }
 816         }
 817         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 818         ep->dma_channel = channel;
 819
 820         if (is_in) {
 821                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
 822                         ep->ep.name, dma_error, ep, &ep->lch);
 823                 if (status == 0) {
 824                         UDC_TXDMA_CFG_REG = reg;
 825                         /* EMIFF */
 826                         omap_set_dma_src_burst_mode(ep->lch,
 827                                                 OMAP_DMA_DATA_BURST_4);
 828                         omap_set_dma_src_data_pack(ep->lch, 1);
 829                         /* TIPB */
 830                         omap_set_dma_dest_params(ep->lch,
 831                                 OMAP_DMA_PORT_TIPB,
 832                                 OMAP_DMA_AMODE_CONSTANT,
 833                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 834                                 0, 0);
 835                 }
 836         } else {
 837                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
 838                         ep->ep.name, dma_error, ep, &ep->lch);
 839                 if (status == 0) {
 840                         UDC_RXDMA_CFG_REG = reg;
 841                         /* TIPB */
 842                         omap_set_dma_src_params(ep->lch,
 843                                 OMAP_DMA_PORT_TIPB,
 844                                 OMAP_DMA_AMODE_CONSTANT,
 845                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 846                                 0, 0);
 847                         /* EMIFF */
 848                         omap_set_dma_dest_burst_mode(ep->lch,
 849                                                 OMAP_DMA_DATA_BURST_4);
 850                         omap_set_dma_dest_data_pack(ep->lch, 1);
 851                 }
 852         }
 853         if (status)
 854                 ep->dma_channel = 0;
 855         else {
 856                 ep->has_dma = 1;
 857                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 858
 859                 /* channel type P: hw synch (fifo) */
 860                 if (!cpu_is_omap15xx())
 861                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 862         }
 863
 864 just_restart:
 865         /* restart any queue, even if the claim failed  */
 866         restart = !ep->stopped && !list_empty(&ep->queue);
 867
 868         if (status)
 869                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 870                         restart ? " (restart)" : "");
 871         else
 872                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 873                         is_in ? 't' : 'r',
 874                         ep->dma_channel - 1, ep->lch,
 875                         restart ? " (restart)" : "");
 876
 877         if (restart) {
 878                 struct omap_req *req;
 879                 req = container_of(ep->queue.next, struct omap_req, queue);
 880                 if (ep->has_dma)
 881                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 882                 else {
 883                         use_ep(ep, UDC_EP_SEL);
 884                         (is_in ? write_fifo : read_fifo)(ep, req);
 885                         deselect_ep();
 886                         if (!is_in) {
 887                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 888                                 ep->ackwait = 1 + ep->double_buf;
 889                         }
 890                         /* IN: 6 wait states before it'll tx */
 891                 }
 892         }
 893 }
 894
 895 static void dma_channel_release(struct omap_ep *ep)
 896 {
 897         int             shift = 4 * (ep->dma_channel - 1);
 898         u16             mask = 0x0f << shift;
 899         struct omap_req *req;
 900         int             active;
 901
 902         /* abort any active usb transfer request */
 903         if (!list_empty(&ep->queue))
 904                 req = container_of(ep->queue.next, struct omap_req, queue);
 905         else
 906                 req = NULL;
 907
 908         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 909
 910         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 911                         active ? "active" : "idle",
 912                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 913                         ep->dma_channel - 1, req);
 914
 915         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 916          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 917          */
 918
 919         /* wait till current packet DMA finishes, and fifo empties */
 920         if (ep->bEndpointAddress & USB_DIR_IN) {
 921                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 922
 923                 if (req) {
 924                         finish_in_dma(ep, req, -ECONNRESET);
 925
 926                         /* clear FIFO; hosts probably won't empty it */
 927                         use_ep(ep, UDC_EP_SEL);
 928                         UDC_CTRL_REG = UDC_CLR_EP;
 929                         deselect_ep();
 930                 }
 931                 while (UDC_TXDMA_CFG_REG & mask)
 932                         udelay(10);
 933         } else {
 934                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 935
 936                 /* dma empties the fifo */
 937                 while (UDC_RXDMA_CFG_REG & mask)
 938                         udelay(10);
 939                 if (req)
 940                         finish_out_dma(ep, req, -ECONNRESET, 0);
 941         }
 942         omap_free_dma(ep->lch);
 943         ep->dma_channel = 0;
 944         ep->lch = -1;
 945         /* has_dma still set, till endpoint is fully quiesced */
 946 }
 947
 948
 949 /*-------------------------------------------------------------------------*/
 950
 951 static int
 952 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 953 {
 954         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 955         struct omap_req *req = container_of(_req, struct omap_req, req);
 956         struct omap_udc *udc;
 957         unsigned long   flags;
 958         int             is_iso = 0;
 959
 960         /* catch various bogus parameters */
 961         if (!_req || !req->req.complete || !req->req.buf
 962                         || !list_empty(&req->queue)) {
 963                 DBG("%s, bad params\n", __FUNCTION__);
 964                 return -EINVAL;
 965         }
 966         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 967                 DBG("%s, bad ep\n", __FUNCTION__);
 968                 return -EINVAL;
 969         }
 970         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 971                 if (req->req.length > ep->ep.maxpacket)
 972                         return -EMSGSIZE;
 973                 is_iso = 1;
 974         }
 975
 976         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 977          * have a hard time with partial packet reads...  reject it.
 978          */
 979         if (use_dma
 980                         && ep->has_dma
 981                         && ep->bEndpointAddress != 0
 982                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 983                         && (req->req.length % ep->ep.maxpacket) != 0) {
 984                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
 985                 return -EMSGSIZE;
 986         }
 987
 988         udc = ep->udc;
 989         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 990                 return -ESHUTDOWN;
 991
 992         if (use_dma && ep->has_dma) {
 993                 if (req->req.dma == DMA_ADDR_INVALID) {
 994                         req->req.dma = dma_map_single(
 995                                 ep->udc->gadget.dev.parent,
 996                                 req->req.buf,
 997                                 req->req.length,
 998                                 (ep->bEndpointAddress & USB_DIR_IN)
 999                                         ? DMA_TO_DEVICE
1000                                         : DMA_FROM_DEVICE);
1001                         req->mapped = 1;
1002                 } else {
1003                         dma_sync_single_for_device(
1004                                 ep->udc->gadget.dev.parent,
1005                                 req->req.dma, req->req.length,
1006                                 (ep->bEndpointAddress & USB_DIR_IN)
1007                                         ? DMA_TO_DEVICE
1008                                         : DMA_FROM_DEVICE);
1009                         req->mapped = 0;
1010                 }
1011         }
1012
1013         VDBG("%s queue req %p, len %d buf %p\n",
1014                 ep->ep.name, _req, _req->length, _req->buf);
1015
1016         spin_lock_irqsave(&udc->lock, flags);
1017
1018         req->req.status = -EINPROGRESS;
1019         req->req.actual = 0;
1020
1021         /* maybe kickstart non-iso i/o queues */
1022         if (is_iso)
1023                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1024         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1025                 int     is_in;
1026
1027                 if (ep->bEndpointAddress == 0) {
1028                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1029                                 spin_unlock_irqrestore(&udc->lock, flags);
1030                                 return -EL2HLT;
1031                         }
1032
1033                         /* empty DATA stage? */
1034                         is_in = udc->ep0_in;
1035                         if (!req->req.length) {
1036
1037                                 /* chip became CONFIGURED or ADDRESSED
1038                                  * earlier; drivers may already have queued
1039                                  * requests to non-control endpoints
1040                                  */
1041                                 if (udc->ep0_set_config) {
1042                                         u16     irq_en = UDC_IRQ_EN_REG;
1043
1044                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1045                                         if (!udc->ep0_reset_config)
1046                                                 irq_en |= UDC_EPN_RX_IE
1047                                                         | UDC_EPN_TX_IE;
1048                                         UDC_IRQ_EN_REG = irq_en;
1049                                 }
1050
1051                                 /* STATUS for zero length DATA stages is
1052                                  * always an IN ... even for IN transfers,
1053                                  * a wierd case which seem to stall OMAP.
1054                                  */
1055                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1056                                 UDC_CTRL_REG = UDC_CLR_EP;
1057                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1058                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1059
1060                                 /* cleanup */
1061                                 udc->ep0_pending = 0;
1062                                 done(ep, req, 0);
1063                                 req = NULL;
1064
1065                         /* non-empty DATA stage */
1066                         } else if (is_in) {
1067                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1068                         } else {
1069                                 if (udc->ep0_setup)
1070                                         goto irq_wait;
1071                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1072                         }
1073                 } else {
1074                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1075                         if (!ep->has_dma)
1076                                 use_ep(ep, UDC_EP_SEL);
1077                         /* if ISO: SOF IRQs must be enabled/disabled! */
1078                 }
1079
1080                 if (ep->has_dma)
1081                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1082                 else if (req) {
1083                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1084                                 req = NULL;
1085                         deselect_ep();
1086                         if (!is_in) {
1087                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1088                                 ep->ackwait = 1 + ep->double_buf;
1089                         }
1090                         /* IN: 6 wait states before it'll tx */
1091                 }
1092         }
1093
1094 irq_wait:
1095         /* irq handler advances the queue */
1096         if (req != NULL)
1097                 list_add_tail(&req->queue, &ep->queue);
1098         spin_unlock_irqrestore(&udc->lock, flags);
1099
1100         return 0;
1101 }
1102
1103 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1104 {
1105         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1106         struct omap_req *req;
1107         unsigned long   flags;
1108
1109         if (!_ep || !_req)
1110                 return -EINVAL;
1111
1112         spin_lock_irqsave(&ep->udc->lock, flags);
1113
1114         /* make sure it's actually queued on this endpoint */
1115         list_for_each_entry (req, &ep->queue, queue) {
1116                 if (&req->req == _req)
1117                         break;
1118         }
1119         if (&req->req != _req) {
1120                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1121                 return -EINVAL;
1122         }
1123
1124         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1125                 int channel = ep->dma_channel;
1126
1127                 /* releasing the channel cancels the request,
1128                  * reclaiming the channel restarts the queue
1129                  */
1130                 dma_channel_release(ep);
1131                 dma_channel_claim(ep, channel);
1132         } else
1133                 done(ep, req, -ECONNRESET);
1134         spin_unlock_irqrestore(&ep->udc->lock, flags);
1135         return 0;
1136 }
1137
1138 /*-------------------------------------------------------------------------*/
1139
1140 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1141 {
1142         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1143         unsigned long   flags;
1144         int             status = -EOPNOTSUPP;
1145
1146         spin_lock_irqsave(&ep->udc->lock, flags);
1147
1148         /* just use protocol stalls for ep0; real halts are annoying */
1149         if (ep->bEndpointAddress == 0) {
1150                 if (!ep->udc->ep0_pending)
1151                         status = -EINVAL;
1152                 else if (value) {
1153                         if (ep->udc->ep0_set_config) {
1154                                 WARN("error changing config?\n");
1155                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1156                         }
1157                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1158                         ep->udc->ep0_pending = 0;
1159                         status = 0;
1160                 } else /* NOP */
1161                         status = 0;
1162
1163         /* otherwise, all active non-ISO endpoints can halt */
1164         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1165
1166                 /* IN endpoints must already be idle */
1167                 if ((ep->bEndpointAddress & USB_DIR_IN)
1168                                 && !list_empty(&ep->queue)) {
1169                         status = -EAGAIN;
1170                         goto done;
1171                 }
1172
1173                 if (value) {
1174                         int     channel;
1175
1176                         if (use_dma && ep->dma_channel
1177                                         && !list_empty(&ep->queue)) {
1178                                 channel = ep->dma_channel;
1179                                 dma_channel_release(ep);
1180                         } else
1181                                 channel = 0;
1182
1183                         use_ep(ep, UDC_EP_SEL);
1184                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1185                                 UDC_CTRL_REG = UDC_SET_HALT;
1186                                 status = 0;
1187                         } else
1188                                 status = -EAGAIN;
1189                         deselect_ep();
1190
1191                         if (channel)
1192                                 dma_channel_claim(ep, channel);
1193                 } else {
1194                         use_ep(ep, 0);
1195                         UDC_CTRL_REG = ep->udc->clr_halt;
1196                         ep->ackwait = 0;
1197                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1198                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1199                                 ep->ackwait = 1 + ep->double_buf;
1200                         }
1201                 }
1202         }
1203 done:
1204         VDBG("%s %s halt stat %d\n", ep->ep.name,
1205                 value ? "set" : "clear", status);
1206
1207         spin_unlock_irqrestore(&ep->udc->lock, flags);
1208         return status;
1209 }
1210
1211 static struct usb_ep_ops omap_ep_ops = {
1212         .enable         = omap_ep_enable,
1213         .disable        = omap_ep_disable,
1214
1215         .alloc_request  = omap_alloc_request,
1216         .free_request   = omap_free_request,
1217
1218         .alloc_buffer   = omap_alloc_buffer,
1219         .free_buffer    = omap_free_buffer,
1220
1221         .queue          = omap_ep_queue,
1222         .dequeue        = omap_ep_dequeue,
1223
1224         .set_halt       = omap_ep_set_halt,
1225         // fifo_status ... report bytes in fifo
1226         // fifo_flush ... flush fifo
1227 };
1228
1229 /*-------------------------------------------------------------------------*/
1230
1231 static int omap_get_frame(struct usb_gadget *gadget)
1232 {
1233         u16     sof = UDC_SOF_REG;
1234         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1235 }
1236
1237 static int omap_wakeup(struct usb_gadget *gadget)
1238 {
1239         struct omap_udc *udc;
1240         unsigned long   flags;
1241         int             retval = -EHOSTUNREACH;
1242
1243         udc = container_of(gadget, struct omap_udc, gadget);
1244
1245         spin_lock_irqsave(&udc->lock, flags);
1246         if (udc->devstat & UDC_SUS) {
1247                 /* NOTE:  OTG spec erratum says that OTG devices may
1248                  * issue wakeups without host enable.
1249                  */
1250                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1251                         DBG("remote wakeup...\n");
1252                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1253                         retval = 0;
1254                 }
1255
1256         /* NOTE:  non-OTG systems may use SRP TOO... */
1257         } else if (!(udc->devstat & UDC_ATT)) {
1258                 if (udc->transceiver)
1259                         retval = otg_start_srp(udc->transceiver);
1260         }
1261         spin_unlock_irqrestore(&udc->lock, flags);
1262
1263         return retval;
1264 }
1265
1266 static int
1267 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1268 {
1269         struct omap_udc *udc;
1270         unsigned long   flags;
1271         u16             syscon1;
1272
1273         udc = container_of(gadget, struct omap_udc, gadget);
1274         spin_lock_irqsave(&udc->lock, flags);
1275         syscon1 = UDC_SYSCON1_REG;
1276         if (is_selfpowered)
1277                 syscon1 |= UDC_SELF_PWR;
1278         else
1279                 syscon1 &= ~UDC_SELF_PWR;
1280         UDC_SYSCON1_REG = syscon1;
1281         spin_unlock_irqrestore(&udc->lock, flags);
1282
1283         return 0;
1284 }
1285
1286 static int can_pullup(struct omap_udc *udc)
1287 {
1288         return udc->driver && udc->softconnect && udc->vbus_active;
1289 }
1290
1291 static void pullup_enable(struct omap_udc *udc)
1292 {
1293         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1294         udc->gadget.dev.power.power_state = PMSG_ON;
1295         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1296 #ifndef CONFIG_USB_OTG
1297         if (!cpu_is_omap15xx())
1298                 OTG_CTRL_REG |= OTG_BSESSVLD;
1299 #endif
1300         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1301 }
1302
1303 static void pullup_disable(struct omap_udc *udc)
1304 {
1305 #ifndef CONFIG_USB_OTG
1306         if (!cpu_is_omap15xx())
1307                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1308 #endif
1309         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1310         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1311 }
1312
1313 static struct omap_udc *udc;
1314
1315 static void omap_udc_enable_clock(int enable)
1316 {
1317         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1318                 return;
1319
1320         if (enable) {
1321                 clk_enable(udc->dc_clk);
1322                 clk_enable(udc->hhc_clk);
1323                 udelay(100);
1324         } else {
1325                 clk_disable(udc->hhc_clk);
1326                 clk_disable(udc->dc_clk);
1327         }
1328 }
1329
1330 /*
1331  * Called by whatever detects VBUS sessions:  external transceiver
1332  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1333  */
1334 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1335 {
1336         struct omap_udc *udc;
1337         unsigned long   flags;
1338
1339         udc = container_of(gadget, struct omap_udc, gadget);
1340         spin_lock_irqsave(&udc->lock, flags);
1341         VDBG("VBUS %s\n", is_active ? "on" : "off");
1342         udc->vbus_active = (is_active != 0);
1343         if (cpu_is_omap15xx()) {
1344                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1345                 if (is_active)
1346                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1347                 else
1348                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1349         }
1350         if (udc->dc_clk != NULL && is_active) {
1351                 if (!udc->clk_requested) {
1352                         omap_udc_enable_clock(1);
1353                         udc->clk_requested = 1;
1354                 }
1355         }
1356         if (can_pullup(udc))
1357                 pullup_enable(udc);
1358         else
1359                 pullup_disable(udc);
1360         if (udc->dc_clk != NULL && !is_active) {
1361                 if (udc->clk_requested) {
1362                         omap_udc_enable_clock(0);
1363                         udc->clk_requested = 0;
1364                 }
1365         }
1366         spin_unlock_irqrestore(&udc->lock, flags);
1367         return 0;
1368 }
1369
1370 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1371 {
1372         struct omap_udc *udc;
1373
1374         udc = container_of(gadget, struct omap_udc, gadget);
1375         if (udc->transceiver)
1376                 return otg_set_power(udc->transceiver, mA);
1377         return -EOPNOTSUPP;
1378 }
1379
1380 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1381 {
1382         struct omap_udc *udc;
1383         unsigned long   flags;
1384
1385         udc = container_of(gadget, struct omap_udc, gadget);
1386         spin_lock_irqsave(&udc->lock, flags);
1387         udc->softconnect = (is_on != 0);
1388         if (can_pullup(udc))
1389                 pullup_enable(udc);
1390         else
1391                 pullup_disable(udc);
1392         spin_unlock_irqrestore(&udc->lock, flags);
1393         return 0;
1394 }
1395
1396 static struct usb_gadget_ops omap_gadget_ops = {
1397         .get_frame              = omap_get_frame,
1398         .wakeup                 = omap_wakeup,
1399         .set_selfpowered        = omap_set_selfpowered,
1400         .vbus_session           = omap_vbus_session,
1401         .vbus_draw              = omap_vbus_draw,
1402         .pullup                 = omap_pullup,
1403 };
1404
1405 /*-------------------------------------------------------------------------*/
1406
1407 /* dequeue ALL requests; caller holds udc->lock */
1408 static void nuke(struct omap_ep *ep, int status)
1409 {
1410         struct omap_req *req;
1411
1412         ep->stopped = 1;
1413
1414         if (use_dma && ep->dma_channel)
1415                 dma_channel_release(ep);
1416
1417         use_ep(ep, 0);
1418         UDC_CTRL_REG = UDC_CLR_EP;
1419         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1420                 UDC_CTRL_REG = UDC_SET_HALT;
1421
1422         while (!list_empty(&ep->queue)) {
1423                 req = list_entry(ep->queue.next, struct omap_req, queue);
1424                 done(ep, req, status);
1425         }
1426 }
1427
1428 /* caller holds udc->lock */
1429 static void udc_quiesce(struct omap_udc *udc)
1430 {
1431         struct omap_ep  *ep;
1432
1433         udc->gadget.speed = USB_SPEED_UNKNOWN;
1434         nuke(&udc->ep[0], -ESHUTDOWN);
1435         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1436                 nuke(ep, -ESHUTDOWN);
1437 }
1438
1439 /*-------------------------------------------------------------------------*/
1440
1441 static void update_otg(struct omap_udc *udc)
1442 {
1443         u16     devstat;
1444
1445         if (!udc->gadget.is_otg)
1446                 return;
1447
1448         if (OTG_CTRL_REG & OTG_ID)
1449                 devstat = UDC_DEVSTAT_REG;
1450         else
1451                 devstat = 0;
1452
1453         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1454         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1455         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1456
1457         /* Enable HNP early, avoiding races on suspend irq path.
1458          * ASSUMES OTG state machine B_BUS_REQ input is true.
1459          */
1460         if (udc->gadget.b_hnp_enable)
1461                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1462                                 & ~OTG_PULLUP;
1463 }
1464
1465 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1466 {
1467         struct omap_ep  *ep0 = &udc->ep[0];
1468         struct omap_req *req = NULL;
1469
1470         ep0->irqs++;
1471
1472         /* Clear any pending requests and then scrub any rx/tx state
1473          * before starting to handle the SETUP request.
1474          */
1475         if (irq_src & UDC_SETUP) {
1476                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1477
1478                 nuke(ep0, 0);
1479                 if (ack) {
1480                         UDC_IRQ_SRC_REG = ack;
1481                         irq_src = UDC_SETUP;
1482                 }
1483         }
1484
1485         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1486          * This driver uses only uses protocol stalls (ep0 never halts),
1487          * and if we got this far the gadget driver already had a
1488          * chance to stall.  Tries to be forgiving of host oddities.
1489          *
1490          * NOTE:  the last chance gadget drivers have to stall control
1491          * requests is during their request completion callback.
1492          */
1493         if (!list_empty(&ep0->queue))
1494                 req = container_of(ep0->queue.next, struct omap_req, queue);
1495
1496         /* IN == TX to host */
1497         if (irq_src & UDC_EP0_TX) {
1498                 int     stat;
1499
1500                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1501                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1502                 stat = UDC_STAT_FLG_REG;
1503                 if (stat & UDC_ACK) {
1504                         if (udc->ep0_in) {
1505                                 /* write next IN packet from response,
1506                                  * or set up the status stage.
1507                                  */
1508                                 if (req)
1509                                         stat = write_fifo(ep0, req);
1510                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1511                                 if (!req && udc->ep0_pending) {
1512                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1513                                         UDC_CTRL_REG = UDC_CLR_EP;
1514                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1515                                         UDC_EP_NUM_REG = 0;
1516                                         udc->ep0_pending = 0;
1517                                 } /* else:  6 wait states before it'll tx */
1518                         } else {
1519                                 /* ack status stage of OUT transfer */
1520                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1521                                 if (req)
1522                                         done(ep0, req, 0);
1523                         }
1524                         req = NULL;
1525                 } else if (stat & UDC_STALL) {
1526                         UDC_CTRL_REG = UDC_CLR_HALT;
1527                         UDC_EP_NUM_REG = UDC_EP_DIR;
1528                 } else {
1529                         UDC_EP_NUM_REG = UDC_EP_DIR;
1530                 }
1531         }
1532
1533         /* OUT == RX from host */
1534         if (irq_src & UDC_EP0_RX) {
1535                 int     stat;
1536
1537                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1538                 UDC_EP_NUM_REG = UDC_EP_SEL;
1539                 stat = UDC_STAT_FLG_REG;
1540                 if (stat & UDC_ACK) {
1541                         if (!udc->ep0_in) {
1542                                 stat = 0;
1543                                 /* read next OUT packet of request, maybe
1544                                  * reactiviting the fifo; stall on errors.
1545                                  */
1546                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1547                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1548                                         udc->ep0_pending = 0;
1549                                         stat = 0;
1550                                 } else if (stat == 0)
1551                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1552                                 UDC_EP_NUM_REG = 0;
1553
1554                                 /* activate status stage */
1555                                 if (stat == 1) {
1556                                         done(ep0, req, 0);
1557                                         /* that may have STALLed ep0... */
1558                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1559                                         UDC_CTRL_REG = UDC_CLR_EP;
1560                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1561                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1562                                         udc->ep0_pending = 0;
1563                                 }
1564                         } else {
1565                                 /* ack status stage of IN transfer */
1566                                 UDC_EP_NUM_REG = 0;
1567                                 if (req)
1568                                         done(ep0, req, 0);
1569                         }
1570                 } else if (stat & UDC_STALL) {
1571                         UDC_CTRL_REG = UDC_CLR_HALT;
1572                         UDC_EP_NUM_REG = 0;
1573                 } else {
1574                         UDC_EP_NUM_REG = 0;
1575                 }
1576         }
1577
1578         /* SETUP starts all control transfers */
1579         if (irq_src & UDC_SETUP) {
1580                 union u {
1581                         u16                     word[4];
1582                         struct usb_ctrlrequest  r;
1583                 } u;
1584                 int                     status = -EINVAL;
1585                 struct omap_ep          *ep;
1586
1587                 /* read the (latest) SETUP message */
1588                 do {
1589                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1590                         /* two bytes at a time */
1591                         u.word[0] = UDC_DATA_REG;
1592                         u.word[1] = UDC_DATA_REG;
1593                         u.word[2] = UDC_DATA_REG;
1594                         u.word[3] = UDC_DATA_REG;
1595                         UDC_EP_NUM_REG = 0;
1596                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1597
1598 #define w_value         le16_to_cpup (&u.r.wValue)
1599 #define w_index         le16_to_cpup (&u.r.wIndex)
1600 #define w_length        le16_to_cpup (&u.r.wLength)
1601
1602                 /* Delegate almost all control requests to the gadget driver,
1603                  * except for a handful of ch9 status/feature requests that
1604                  * hardware doesn't autodecode _and_ the gadget API hides.
1605                  */
1606                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1607                 udc->ep0_set_config = 0;
1608                 udc->ep0_pending = 1;
1609                 ep0->stopped = 0;
1610                 ep0->ackwait = 0;
1611                 switch (u.r.bRequest) {
1612                 case USB_REQ_SET_CONFIGURATION:
1613                         /* udc needs to know when ep != 0 is valid */
1614                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1615                                 goto delegate;
1616                         if (w_length != 0)
1617                                 goto do_stall;
1618                         udc->ep0_set_config = 1;
1619                         udc->ep0_reset_config = (w_value == 0);
1620                         VDBG("set config %d\n", w_value);
1621
1622                         /* update udc NOW since gadget driver may start
1623                          * queueing requests immediately; clear config
1624                          * later if it fails the request.
1625                          */
1626                         if (udc->ep0_reset_config)
1627                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1628                         else
1629                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1630                         update_otg(udc);
1631                         goto delegate;
1632                 case USB_REQ_CLEAR_FEATURE:
1633                         /* clear endpoint halt */
1634                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1635                                 goto delegate;
1636                         if (w_value != USB_ENDPOINT_HALT
1637                                         || w_length != 0)
1638                                 goto do_stall;
1639                         ep = &udc->ep[w_index & 0xf];
1640                         if (ep != ep0) {
1641                                 if (w_index & USB_DIR_IN)
1642                                         ep += 16;
1643                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1644                                                 || !ep->desc)
1645                                         goto do_stall;
1646                                 use_ep(ep, 0);
1647                                 UDC_CTRL_REG = udc->clr_halt;
1648                                 ep->ackwait = 0;
1649                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1650                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1651                                         ep->ackwait = 1 + ep->double_buf;
1652                                 }
1653                                 /* NOTE:  assumes the host behaves sanely,
1654                                  * only clearing real halts.  Else we may
1655                                  * need to kill pending transfers and then
1656                                  * restart the queue... very messy for DMA!
1657                                  */
1658                         }
1659                         VDBG("%s halt cleared by host\n", ep->name);
1660                         goto ep0out_status_stage;
1661                 case USB_REQ_SET_FEATURE:
1662                         /* set endpoint halt */
1663                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1664                                 goto delegate;
1665                         if (w_value != USB_ENDPOINT_HALT
1666                                         || w_length != 0)
1667                                 goto do_stall;
1668                         ep = &udc->ep[w_index & 0xf];
1669                         if (w_index & USB_DIR_IN)
1670                                 ep += 16;
1671                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1672                                         || ep == ep0 || !ep->desc)
1673                                 goto do_stall;
1674                         if (use_dma && ep->has_dma) {
1675                                 /* this has rude side-effects (aborts) and
1676                                  * can't really work if DMA-IN is active
1677                                  */
1678                                 DBG("%s host set_halt, NYET \n", ep->name);
1679                                 goto do_stall;
1680                         }
1681                         use_ep(ep, 0);
1682                         /* can't halt if fifo isn't empty... */
1683                         UDC_CTRL_REG = UDC_CLR_EP;
1684                         UDC_CTRL_REG = UDC_SET_HALT;
1685                         VDBG("%s halted by host\n", ep->name);
1686 ep0out_status_stage:
1687                         status = 0;
1688                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1689                         UDC_CTRL_REG = UDC_CLR_EP;
1690                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1691                         UDC_EP_NUM_REG = UDC_EP_DIR;
1692                         udc->ep0_pending = 0;
1693                         break;
1694                 case USB_REQ_GET_STATUS:
1695                         /* return interface status.  if we were pedantic,
1696                          * we'd detect non-existent interfaces, and stall.
1697                          */
1698                         if (u.r.bRequestType
1699                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1700                                 goto delegate;
1701                         /* return two zero bytes */
1702                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1703                         UDC_DATA_REG = 0;
1704                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1705                         UDC_EP_NUM_REG = UDC_EP_DIR;
1706                         status = 0;
1707                         VDBG("GET_STATUS, interface %d\n", w_index);
1708                         /* next, status stage */
1709                         break;
1710                 default:
1711 delegate:
1712                         /* activate the ep0out fifo right away */
1713                         if (!udc->ep0_in && w_length) {
1714                                 UDC_EP_NUM_REG = 0;
1715                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1716                         }
1717
1718                         /* gadget drivers see class/vendor specific requests,
1719                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1720                          * and more
1721                          */
1722                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1723                                 u.r.bRequestType, u.r.bRequest,
1724                                 w_value, w_index, w_length);
1725
1726 #undef  w_value
1727 #undef  w_index
1728 #undef  w_length
1729
1730                         /* The gadget driver may return an error here,
1731                          * causing an immediate protocol stall.
1732                          *
1733                          * Else it must issue a response, either queueing a
1734                          * response buffer for the DATA stage, or halting ep0
1735                          * (causing a protocol stall, not a real halt).  A
1736                          * zero length buffer means no DATA stage.
1737                          *
1738                          * It's fine to issue that response after the setup()
1739                          * call returns, and this IRQ was handled.
1740                          */
1741                         udc->ep0_setup = 1;
1742                         spin_unlock(&udc->lock);
1743                         status = udc->driver->setup (&udc->gadget, &u.r);
1744                         spin_lock(&udc->lock);
1745                         udc->ep0_setup = 0;
1746                 }
1747
1748                 if (status < 0) {
1749 do_stall:
1750                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1751                                         u.r.bRequestType, u.r.bRequest, status);
1752                         if (udc->ep0_set_config) {
1753                                 if (udc->ep0_reset_config)
1754                                         WARN("error resetting config?\n");
1755                                 else
1756                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1757                         }
1758                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1759                         udc->ep0_pending = 0;
1760                 }
1761         }
1762 }
1763
1764 /*-------------------------------------------------------------------------*/
1765
1766 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1767
1768 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1769 {
1770         u16     devstat, change;
1771
1772         devstat = UDC_DEVSTAT_REG;
1773         change = devstat ^ udc->devstat;
1774         udc->devstat = devstat;
1775
1776         if (change & (UDC_USB_RESET|UDC_ATT)) {
1777                 udc_quiesce(udc);
1778
1779                 if (change & UDC_ATT) {
1780                         /* driver for any external transceiver will
1781                          * have called omap_vbus_session() already
1782                          */
1783                         if (devstat & UDC_ATT) {
1784                                 udc->gadget.speed = USB_SPEED_FULL;
1785                                 VDBG("connect\n");
1786                                 if (!udc->transceiver)
1787                                         pullup_enable(udc);
1788                                 // if (driver->connect) call it
1789                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1790                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1791                                 if (!udc->transceiver)
1792                                         pullup_disable(udc);
1793                                 DBG("disconnect, gadget %s\n",
1794                                         udc->driver->driver.name);
1795                                 if (udc->driver->disconnect) {
1796                                         spin_unlock(&udc->lock);
1797                                         udc->driver->disconnect(&udc->gadget);
1798                                         spin_lock(&udc->lock);
1799                                 }
1800                         }
1801                         change &= ~UDC_ATT;
1802                 }
1803
1804                 if (change & UDC_USB_RESET) {
1805                         if (devstat & UDC_USB_RESET) {
1806                                 VDBG("RESET=1\n");
1807                         } else {
1808                                 udc->gadget.speed = USB_SPEED_FULL;
1809                                 INFO("USB reset done, gadget %s\n",
1810                                         udc->driver->driver.name);
1811                                 /* ep0 traffic is legal from now on */
1812                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1813                         }
1814                         change &= ~UDC_USB_RESET;
1815                 }
1816         }
1817         if (change & UDC_SUS) {
1818                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1819                         // FIXME tell isp1301 to suspend/resume (?)
1820                         if (devstat & UDC_SUS) {
1821                                 VDBG("suspend\n");
1822                                 update_otg(udc);
1823                                 /* HNP could be under way already */
1824                                 if (udc->gadget.speed == USB_SPEED_FULL
1825                                                 && udc->driver->suspend) {
1826                                         spin_unlock(&udc->lock);
1827                                         udc->driver->suspend(&udc->gadget);
1828                                         spin_lock(&udc->lock);
1829                                 }
1830                                 if (udc->transceiver)
1831                                         otg_set_suspend(udc->transceiver, 1);
1832                         } else {
1833                                 VDBG("resume\n");
1834                                 if (udc->transceiver)
1835                                         otg_set_suspend(udc->transceiver, 0);
1836                                 if (udc->gadget.speed == USB_SPEED_FULL
1837                                                 && udc->driver->resume) {
1838                                         spin_unlock(&udc->lock);
1839                                         udc->driver->resume(&udc->gadget);
1840                                         spin_lock(&udc->lock);
1841                                 }
1842                         }
1843                 }
1844                 change &= ~UDC_SUS;
1845         }
1846         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1847                 update_otg(udc);
1848                 change &= ~OTG_FLAGS;
1849         }
1850
1851         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1852         if (change)
1853                 VDBG("devstat %03x, ignore change %03x\n",
1854                         devstat,  change);
1855
1856         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1857 }
1858
1859 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1860 {
1861         struct omap_udc *udc = _udc;
1862         u16             irq_src;
1863         irqreturn_t     status = IRQ_NONE;
1864         unsigned long   flags;
1865
1866         spin_lock_irqsave(&udc->lock, flags);
1867         irq_src = UDC_IRQ_SRC_REG;
1868
1869         /* Device state change (usb ch9 stuff) */
1870         if (irq_src & UDC_DS_CHG) {
1871                 devstate_irq(_udc, irq_src);
1872                 status = IRQ_HANDLED;
1873                 irq_src &= ~UDC_DS_CHG;
1874         }
1875
1876         /* EP0 control transfers */
1877         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1878                 ep0_irq(_udc, irq_src);
1879                 status = IRQ_HANDLED;
1880                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1881         }
1882
1883         /* DMA transfer completion */
1884         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1885                 dma_irq(_udc, irq_src);
1886                 status = IRQ_HANDLED;
1887                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1888         }
1889
1890         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1891         if (irq_src)
1892                 DBG("udc_irq, unhandled %03x\n", irq_src);
1893         spin_unlock_irqrestore(&udc->lock, flags);
1894
1895         return status;
1896 }
1897
1898 /* workaround for seemingly-lost IRQs for RX ACKs... */
1899 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1900 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1901
1902 static void pio_out_timer(unsigned long _ep)
1903 {
1904         struct omap_ep  *ep = (void *) _ep;
1905         unsigned long   flags;
1906         u16             stat_flg;
1907
1908         spin_lock_irqsave(&ep->udc->lock, flags);
1909         if (!list_empty(&ep->queue) && ep->ackwait) {
1910                 use_ep(ep, UDC_EP_SEL);
1911                 stat_flg = UDC_STAT_FLG_REG;
1912
1913                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1914                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1915                         struct omap_req *req;
1916
1917                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1918                         req = container_of(ep->queue.next,
1919                                         struct omap_req, queue);
1920                         (void) read_fifo(ep, req);
1921                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1922                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1923                         ep->ackwait = 1 + ep->double_buf;
1924                 } else
1925                         deselect_ep();
1926         }
1927         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1928         spin_unlock_irqrestore(&ep->udc->lock, flags);
1929 }
1930
1931 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1932 {
1933         u16             epn_stat, irq_src;
1934         irqreturn_t     status = IRQ_NONE;
1935         struct omap_ep  *ep;
1936         int             epnum;
1937         struct omap_udc *udc = _dev;
1938         struct omap_req *req;
1939         unsigned long   flags;
1940
1941         spin_lock_irqsave(&udc->lock, flags);
1942         epn_stat = UDC_EPN_STAT_REG;
1943         irq_src = UDC_IRQ_SRC_REG;
1944
1945         /* handle OUT first, to avoid some wasteful NAKs */
1946         if (irq_src & UDC_EPN_RX) {
1947                 epnum = (epn_stat >> 8) & 0x0f;
1948                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1949                 status = IRQ_HANDLED;
1950                 ep = &udc->ep[epnum];
1951                 ep->irqs++;
1952
1953                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1954                 ep->fnf = 0;
1955                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1956                         ep->ackwait--;
1957                         if (!list_empty(&ep->queue)) {
1958                                 int stat;
1959                                 req = container_of(ep->queue.next,
1960                                                 struct omap_req, queue);
1961                                 stat = read_fifo(ep, req);
1962                                 if (!ep->double_buf)
1963                                         ep->fnf = 1;
1964                         }
1965                 }
1966                 /* min 6 clock delay before clearing EP_SEL ... */
1967                 epn_stat = UDC_EPN_STAT_REG;
1968                 epn_stat = UDC_EPN_STAT_REG;
1969                 UDC_EP_NUM_REG = epnum;
1970
1971                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1972                  * reduces lossage; timer still needed though (sigh).
1973                  */
1974                 if (ep->fnf) {
1975                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1976                         ep->ackwait = 1 + ep->double_buf;
1977                 }
1978                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1979         }
1980
1981         /* then IN transfers */
1982         else if (irq_src & UDC_EPN_TX) {
1983                 epnum = epn_stat & 0x0f;
1984                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1985                 status = IRQ_HANDLED;
1986                 ep = &udc->ep[16 + epnum];
1987                 ep->irqs++;
1988
1989                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1990                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1991                         ep->ackwait = 0;
1992                         if (!list_empty(&ep->queue)) {
1993                                 req = container_of(ep->queue.next,
1994                                                 struct omap_req, queue);
1995                                 (void) write_fifo(ep, req);
1996                         }
1997                 }
1998                 /* min 6 clock delay before clearing EP_SEL ... */
1999                 epn_stat = UDC_EPN_STAT_REG;
2000                 epn_stat = UDC_EPN_STAT_REG;
2001                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
2002                 /* then 6 clocks before it'd tx */
2003         }
2004
2005         spin_unlock_irqrestore(&udc->lock, flags);
2006         return status;
2007 }
2008
2009 #ifdef  USE_ISO
2010 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2011 {
2012         struct omap_udc *udc = _dev;
2013         struct omap_ep  *ep;
2014         int             pending = 0;
2015         unsigned long   flags;
2016
2017         spin_lock_irqsave(&udc->lock, flags);
2018
2019         /* handle all non-DMA ISO transfers */
2020         list_for_each_entry (ep, &udc->iso, iso) {
2021                 u16             stat;
2022                 struct omap_req *req;
2023
2024                 if (ep->has_dma || list_empty(&ep->queue))
2025                         continue;
2026                 req = list_entry(ep->queue.next, struct omap_req, queue);
2027
2028                 use_ep(ep, UDC_EP_SEL);
2029                 stat = UDC_STAT_FLG_REG;
2030
2031                 /* NOTE: like the other controller drivers, this isn't
2032                  * currently reporting lost or damaged frames.
2033                  */
2034                 if (ep->bEndpointAddress & USB_DIR_IN) {
2035                         if (stat & UDC_MISS_IN)
2036                                 /* done(ep, req, -EPROTO) */;
2037                         else
2038                                 write_fifo(ep, req);
2039                 } else {
2040                         int     status = 0;
2041
2042                         if (stat & UDC_NO_RXPACKET)
2043                                 status = -EREMOTEIO;
2044                         else if (stat & UDC_ISO_ERR)
2045                                 status = -EILSEQ;
2046                         else if (stat & UDC_DATA_FLUSH)
2047                                 status = -ENOSR;
2048
2049                         if (status)
2050                                 /* done(ep, req, status) */;
2051                         else
2052                                 read_fifo(ep, req);
2053                 }
2054                 deselect_ep();
2055                 /* 6 wait states before next EP */
2056
2057                 ep->irqs++;
2058                 if (!list_empty(&ep->queue))
2059                         pending = 1;
2060         }
2061         if (!pending)
2062                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2063         UDC_IRQ_SRC_REG = UDC_SOF;
2064
2065         spin_unlock_irqrestore(&udc->lock, flags);
2066         return IRQ_HANDLED;
2067 }
2068 #endif
2069
2070 /*-------------------------------------------------------------------------*/
2071
2072 static inline int machine_needs_vbus_session(void)
2073 {
2074         return (machine_is_omap_innovator()
2075                 || machine_is_omap_osk()
2076                 || machine_is_omap_apollon()
2077 #ifndef CONFIG_MACH_OMAP_H4_OTG
2078                 || machine_is_omap_h4()
2079 #endif
2080                 || machine_is_sx1()
2081                 );
2082 }
2083
2084 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2085 {
2086         int             status = -ENODEV;
2087         struct omap_ep  *ep;
2088         unsigned long   flags;
2089
2090         /* basic sanity tests */
2091         if (!udc)
2092                 return -ENODEV;
2093         if (!driver
2094                         // FIXME if otg, check:  driver->is_otg
2095                         || driver->speed < USB_SPEED_FULL
2096                         || !driver->bind
2097                         || !driver->setup)
2098                 return -EINVAL;
2099
2100         spin_lock_irqsave(&udc->lock, flags);
2101         if (udc->driver) {
2102                 spin_unlock_irqrestore(&udc->lock, flags);
2103                 return -EBUSY;
2104         }
2105
2106         /* reset state */
2107         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2108                 ep->irqs = 0;
2109                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2110                         continue;
2111                 use_ep(ep, 0);
2112                 UDC_CTRL_REG = UDC_SET_HALT;
2113         }
2114         udc->ep0_pending = 0;
2115         udc->ep[0].irqs = 0;
2116         udc->softconnect = 1;
2117
2118         /* hook up the driver */
2119         driver->driver.bus = NULL;
2120         udc->driver = driver;
2121         udc->gadget.dev.driver = &driver->driver;
2122         spin_unlock_irqrestore(&udc->lock, flags);
2123
2124         if (udc->dc_clk != NULL)
2125                 omap_udc_enable_clock(1);
2126
2127         status = driver->bind (&udc->gadget);
2128         if (status) {
2129                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2130                 udc->gadget.dev.driver = NULL;
2131                 udc->driver = NULL;
2132                 goto done;
2133         }
2134         DBG("bound to driver %s\n", driver->driver.name);
2135
2136         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2137
2138         /* connect to bus through transceiver */
2139         if (udc->transceiver) {
2140                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2141                 if (status < 0) {
2142                         ERR("can't bind to transceiver\n");
2143                         if (driver->unbind) {
2144                                 driver->unbind (&udc->gadget);
2145                                 udc->gadget.dev.driver = NULL;
2146                                 udc->driver = NULL;
2147                         }
2148                         goto done;
2149                 }
2150         } else {
2151                 if (can_pullup(udc))
2152                         pullup_enable (udc);
2153                 else
2154                         pullup_disable (udc);
2155         }
2156
2157         /* boards that don't have VBUS sensing can't autogate 48MHz;
2158          * can't enter deep sleep while a gadget driver is active.
2159          */
2160         if (machine_needs_vbus_session())
2161                 omap_vbus_session(&udc->gadget, 1);
2162
2163 done:
2164         if (udc->dc_clk != NULL)
2165                 omap_udc_enable_clock(0);
2166         return status;
2167 }
2168 EXPORT_SYMBOL(usb_gadget_register_driver);
2169
2170 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2171 {
2172         unsigned long   flags;
2173         int             status = -ENODEV;
2174
2175         if (!udc)
2176                 return -ENODEV;
2177         if (!driver || driver != udc->driver || !driver->unbind)
2178                 return -EINVAL;
2179
2180         if (udc->dc_clk != NULL)
2181                 omap_udc_enable_clock(1);
2182
2183         if (machine_needs_vbus_session())
2184                 omap_vbus_session(&udc->gadget, 0);
2185
2186         if (udc->transceiver)
2187                 (void) otg_set_peripheral(udc->transceiver, NULL);
2188         else
2189                 pullup_disable(udc);
2190
2191         spin_lock_irqsave(&udc->lock, flags);
2192         udc_quiesce(udc);
2193         spin_unlock_irqrestore(&udc->lock, flags);
2194
2195         driver->unbind(&udc->gadget);
2196         udc->gadget.dev.driver = NULL;
2197         udc->driver = NULL;
2198
2199         if (udc->dc_clk != NULL)
2200                 omap_udc_enable_clock(0);
2201         DBG("unregistered driver '%s'\n", driver->driver.name);
2202         return status;
2203 }
2204 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2205
2206
2207 /*-------------------------------------------------------------------------*/
2208
2209 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2210
2211 #include <linux/seq_file.h>
2212
2213 static const char proc_filename[] = "driver/udc";
2214
2215 #define FOURBITS "%s%s%s%s"
2216 #define EIGHTBITS FOURBITS FOURBITS
2217
2218 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2219 {
2220         u16             stat_flg;
2221         struct omap_req *req;
2222         char            buf[20];
2223
2224         use_ep(ep, 0);
2225
2226         if (use_dma && ep->has_dma)
2227                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2228                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2229                         ep->dma_channel - 1, ep->lch);
2230         else
2231                 buf[0] = 0;
2232
2233         stat_flg = UDC_STAT_FLG_REG;
2234         seq_printf(s,
2235                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2236                 ep->name, buf,
2237                 ep->double_buf ? "dbuf " : "",
2238                 ({char *s; switch(ep->ackwait){
2239                 case 0: s = ""; break;
2240                 case 1: s = "(ackw) "; break;
2241                 case 2: s = "(ackw2) "; break;
2242                 default: s = "(?) "; break;
2243                 } s;}),
2244                 ep->irqs, stat_flg,
2245                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2246                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2247                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2248                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2249                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2250                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2251                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2252                 (stat_flg & UDC_STALL) ? "STALL " : "",
2253                 (stat_flg & UDC_NAK) ? "NAK " : "",
2254                 (stat_flg & UDC_ACK) ? "ACK " : "",
2255                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2256                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2257                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2258
2259         if (list_empty (&ep->queue))
2260                 seq_printf(s, "\t(queue empty)\n");
2261         else
2262                 list_for_each_entry (req, &ep->queue, queue) {
2263                         unsigned        length = req->req.actual;
2264
2265                         if (use_dma && buf[0]) {
2266                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2267                                                 ? dma_src_len : dma_dest_len)
2268                                         (ep, req->req.dma + length);
2269                                 buf[0] = 0;
2270                         }
2271                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2272                                         &req->req, length,
2273                                         req->req.length, req->req.buf);
2274                 }
2275 }
2276
2277 static char *trx_mode(unsigned m, int enabled)
2278 {
2279         switch (m) {
2280         case 0:         return enabled ? "*6wire" : "unused";
2281         case 1:         return "4wire";
2282         case 2:         return "3wire";
2283         case 3:         return "6wire";
2284         default:        return "unknown";
2285         }
2286 }
2287
2288 static int proc_otg_show(struct seq_file *s)
2289 {
2290         u32             tmp;
2291         u32             trans;
2292         char            *ctrl_name;
2293
2294         tmp = OTG_REV_REG;
2295         if (cpu_is_omap24xx()) {
2296                 ctrl_name = "control_devconf";
2297                 trans = CONTROL_DEVCONF_REG;
2298         } else {
2299                 ctrl_name = "tranceiver_ctrl";
2300                 trans = USB_TRANSCEIVER_CTRL_REG;
2301         }
2302         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2303                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2304         tmp = OTG_SYSCON_1_REG;
2305         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2306                         FOURBITS "\n", tmp,
2307                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2308                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2309                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2310                         ? "internal"
2311                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2312                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2313                 (tmp & HST_IDLE_EN) ? " !host" : "",
2314                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2315                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2316         tmp = OTG_SYSCON_2_REG;
2317         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2318                         " b_ase_brst=%d hmc=%d\n", tmp,
2319                 (tmp & OTG_EN) ? " otg_en" : "",
2320                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2321                 // much more SRP stuff
2322                 (tmp & SRP_DATA) ? " srp_data" : "",
2323                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2324                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2325                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2326                 (tmp & UHOST_EN) ? " uhost_en" : "",
2327                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2328                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2329                 B_ASE_BRST(tmp),
2330                 OTG_HMC(tmp));
2331         tmp = OTG_CTRL_REG;
2332         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2333                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2334                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2335                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2336                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2337                 (tmp & OTG_ID) ? " id" : "",
2338                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2339                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2340                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2341                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2342                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2343                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2344                 (tmp & OTG_PULLDOWN) ? " down" : "",
2345                 (tmp & OTG_PULLUP) ? " up" : "",
2346                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2347                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2348                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2349                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2350                 );
2351         tmp = OTG_IRQ_EN_REG;
2352         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2353         tmp = OTG_IRQ_SRC_REG;
2354         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2355         tmp = OTG_OUTCTRL_REG;
2356         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2357         tmp = OTG_TEST_REG;
2358         seq_printf(s, "otg_test    %04x" "\n", tmp);
2359         return 0;
2360 }
2361
2362 static int proc_udc_show(struct seq_file *s, void *_)
2363 {
2364         u32             tmp;
2365         struct omap_ep  *ep;
2366         unsigned long   flags;
2367
2368         spin_lock_irqsave(&udc->lock, flags);
2369
2370         seq_printf(s, "%s, version: " DRIVER_VERSION
2371 #ifdef  USE_ISO
2372                 " (iso)"
2373 #endif
2374                 "%s\n",
2375                 driver_desc,
2376                 use_dma ?  " (dma)" : "");
2377
2378         tmp = UDC_REV_REG & 0xff;
2379         seq_printf(s,
2380                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2381                 "hmc %d, transceiver %s\n",
2382                 tmp >> 4, tmp & 0xf,
2383                 fifo_mode,
2384                 udc->driver ? udc->driver->driver.name : "(none)",
2385                 HMC,
2386                 udc->transceiver
2387                         ? udc->transceiver->label
2388                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2389                                 ? "external" : "(none)"));
2390         if (cpu_class_is_omap1()) {
2391                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2392                         __REG16(ULPD_CLOCK_CTRL),
2393                         __REG16(ULPD_SOFT_REQ),
2394                         __REG16(ULPD_STATUS_REQ));
2395         }
2396
2397         /* OTG controller registers */
2398         if (!cpu_is_omap15xx())
2399                 proc_otg_show(s);
2400
2401         tmp = UDC_SYSCON1_REG;
2402         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2403                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2404                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2405                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2406                 (tmp & UDC_NAK_EN) ? " nak" : "",
2407                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2408                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2409                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2410                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2411         // syscon2 is write-only
2412
2413         /* UDC controller registers */
2414         if (!(tmp & UDC_PULLUP_EN)) {
2415                 seq_printf(s, "(suspended)\n");
2416                 spin_unlock_irqrestore(&udc->lock, flags);
2417                 return 0;
2418         }
2419
2420         tmp = UDC_DEVSTAT_REG;
2421         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2422                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2423                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2424                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2425                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2426                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2427                 (tmp & UDC_SUS) ? " SUS" : "",
2428                 (tmp & UDC_CFG) ? " CFG" : "",
2429                 (tmp & UDC_ADD) ? " ADD" : "",
2430                 (tmp & UDC_DEF) ? " DEF" : "",
2431                 (tmp & UDC_ATT) ? " ATT" : "");
2432         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2433         tmp = UDC_IRQ_EN_REG;
2434         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2435                 (tmp & UDC_SOF_IE) ? " sof" : "",
2436                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2437                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2438                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2439                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2440         tmp = UDC_IRQ_SRC_REG;
2441         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2442                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2443                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2444                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2445                 (tmp & UDC_SOF) ? " sof" : "",
2446                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2447                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2448                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2449                 (tmp & UDC_SETUP) ? " setup" : "",
2450                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2451                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2452         if (use_dma) {
2453                 unsigned i;
2454
2455                 tmp = UDC_DMA_IRQ_EN_REG;
2456                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2457                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2458                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2459                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2460
2461                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2462                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2463                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2464
2465                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2466                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2467                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2468
2469                 tmp = UDC_RXDMA_CFG_REG;
2470                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2471                 if (tmp) {
2472                         for (i = 0; i < 3; i++) {
2473                                 if ((tmp & (0x0f << (i * 4))) == 0)
2474                                         continue;
2475                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2476                                                 UDC_RXDMA_REG(i + 1));
2477                         }
2478                 }
2479                 tmp = UDC_TXDMA_CFG_REG;
2480                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2481                 if (tmp) {
2482                         for (i = 0; i < 3; i++) {
2483                                 if (!(tmp & (0x0f << (i * 4))))
2484                                         continue;
2485                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2486                                                 UDC_TXDMA_REG(i + 1));
2487                         }
2488                 }
2489         }
2490
2491         tmp = UDC_DEVSTAT_REG;
2492         if (tmp & UDC_ATT) {
2493                 proc_ep_show(s, &udc->ep[0]);
2494                 if (tmp & UDC_ADD) {
2495                         list_for_each_entry (ep, &udc->gadget.ep_list,
2496                                         ep.ep_list) {
2497                                 if (ep->desc)
2498                                         proc_ep_show(s, ep);
2499                         }
2500                 }
2501         }
2502         spin_unlock_irqrestore(&udc->lock, flags);
2503         return 0;
2504 }
2505
2506 static int proc_udc_open(struct inode *inode, struct file *file)
2507 {
2508         return single_open(file, proc_udc_show, NULL);
2509 }
2510
2511 static const struct file_operations proc_ops = {
2512         .open           = proc_udc_open,
2513         .read           = seq_read,
2514         .llseek         = seq_lseek,
2515         .release        = single_release,
2516 };
2517
2518 static void create_proc_file(void)
2519 {
2520         struct proc_dir_entry *pde;
2521
2522         pde = create_proc_entry (proc_filename, 0, NULL);
2523         if (pde)
2524                 pde->proc_fops = &proc_ops;
2525 }
2526
2527 static void remove_proc_file(void)
2528 {
2529         remove_proc_entry(proc_filename, NULL);
2530 }
2531
2532 #else
2533
2534 static inline void create_proc_file(void) {}
2535 static inline void remove_proc_file(void) {}
2536
2537 #endif
2538
2539 /*-------------------------------------------------------------------------*/
2540
2541 /* Before this controller can enumerate, we need to pick an endpoint
2542  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2543  * buffer space among the endpoints we'll be operating.
2544  *
2545  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2546  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2547  * capability yet though.
2548  */
2549 static unsigned __init
2550 omap_ep_setup(char *name, u8 addr, u8 type,
2551                 unsigned buf, unsigned maxp, int dbuf)
2552 {
2553         struct omap_ep  *ep;
2554         u16             epn_rxtx = 0;
2555
2556         /* OUT endpoints first, then IN */
2557         ep = &udc->ep[addr & 0xf];
2558         if (addr & USB_DIR_IN)
2559                 ep += 16;
2560
2561         /* in case of ep init table bugs */
2562         BUG_ON(ep->name[0]);
2563
2564         /* chip setup ... bit values are same for IN, OUT */
2565         if (type == USB_ENDPOINT_XFER_ISOC) {
2566                 switch (maxp) {
2567                 case 8:         epn_rxtx = 0 << 12; break;
2568                 case 16:        epn_rxtx = 1 << 12; break;
2569                 case 32:        epn_rxtx = 2 << 12; break;
2570                 case 64:        epn_rxtx = 3 << 12; break;
2571                 case 128:       epn_rxtx = 4 << 12; break;
2572                 case 256:       epn_rxtx = 5 << 12; break;
2573                 case 512:       epn_rxtx = 6 << 12; break;
2574                 default:        BUG();
2575                 }
2576                 epn_rxtx |= UDC_EPN_RX_ISO;
2577                 dbuf = 1;
2578         } else {
2579                 /* double-buffering "not supported" on 15xx,
2580                  * and ignored for PIO-IN on newer chips
2581                  * (for more reliable behavior)
2582                  */
2583                 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2584                         dbuf = 0;
2585
2586                 switch (maxp) {
2587                 case 8:         epn_rxtx = 0 << 12; break;
2588                 case 16:        epn_rxtx = 1 << 12; break;
2589                 case 32:        epn_rxtx = 2 << 12; break;
2590                 case 64:        epn_rxtx = 3 << 12; break;
2591                 default:        BUG();
2592                 }
2593                 if (dbuf && addr)
2594                         epn_rxtx |= UDC_EPN_RX_DB;
2595                 init_timer(&ep->timer);
2596                 ep->timer.function = pio_out_timer;
2597                 ep->timer.data = (unsigned long) ep;
2598         }
2599         if (addr)
2600                 epn_rxtx |= UDC_EPN_RX_VALID;
2601         BUG_ON(buf & 0x07);
2602         epn_rxtx |= buf >> 3;
2603
2604         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2605                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2606
2607         if (addr & USB_DIR_IN)
2608                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2609         else
2610                 UDC_EP_RX_REG(addr) = epn_rxtx;
2611
2612         /* next endpoint's buffer starts after this one's */
2613         buf += maxp;
2614         if (dbuf)
2615                 buf += maxp;
2616         BUG_ON(buf > 2048);
2617
2618         /* set up driver data structures */
2619         BUG_ON(strlen(name) >= sizeof ep->name);
2620         strlcpy(ep->name, name, sizeof ep->name);
2621         INIT_LIST_HEAD(&ep->queue);
2622         INIT_LIST_HEAD(&ep->iso);
2623         ep->bEndpointAddress = addr;
2624         ep->bmAttributes = type;
2625         ep->double_buf = dbuf;
2626         ep->udc = udc;
2627
2628         ep->ep.name = ep->name;
2629         ep->ep.ops = &omap_ep_ops;
2630         ep->ep.maxpacket = ep->maxpacket = maxp;
2631         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2632
2633         return buf;
2634 }
2635
2636 static void omap_udc_release(struct device *dev)
2637 {
2638         complete(udc->done);
2639         kfree (udc);
2640         udc = NULL;
2641 }
2642
2643 static int __init
2644 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2645 {
2646         unsigned        tmp, buf;
2647
2648         /* abolish any previous hardware state */
2649         UDC_SYSCON1_REG = 0;
2650         UDC_IRQ_EN_REG = 0;
2651         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2652         UDC_DMA_IRQ_EN_REG = 0;
2653         UDC_RXDMA_CFG_REG = 0;
2654         UDC_TXDMA_CFG_REG = 0;
2655
2656         /* UDC_PULLUP_EN gates the chip clock */
2657         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2658
2659         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2660         if (!udc)
2661                 return -ENOMEM;
2662
2663         spin_lock_init (&udc->lock);
2664
2665         udc->gadget.ops = &omap_gadget_ops;
2666         udc->gadget.ep0 = &udc->ep[0].ep;
2667         INIT_LIST_HEAD(&udc->gadget.ep_list);
2668         INIT_LIST_HEAD(&udc->iso);
2669         udc->gadget.speed = USB_SPEED_UNKNOWN;
2670         udc->gadget.name = driver_name;
2671
2672         device_initialize(&udc->gadget.dev);
2673         strcpy (udc->gadget.dev.bus_id, "gadget");
2674         udc->gadget.dev.release = omap_udc_release;
2675         udc->gadget.dev.parent = &odev->dev;
2676         if (use_dma)
2677                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2678
2679         udc->transceiver = xceiv;
2680
2681         /* ep0 is special; put it right after the SETUP buffer */
2682         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2683                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2684         list_del_init(&udc->ep[0].ep.ep_list);
2685
2686         /* initially disable all non-ep0 endpoints */
2687         for (tmp = 1; tmp < 15; tmp++) {
2688                 UDC_EP_RX_REG(tmp) = 0;
2689                 UDC_EP_TX_REG(tmp) = 0;
2690         }
2691
2692 #define OMAP_BULK_EP(name,addr) \
2693         buf = omap_ep_setup(name "-bulk", addr, \
2694                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2695 #define OMAP_INT_EP(name,addr, maxp) \
2696         buf = omap_ep_setup(name "-int", addr, \
2697                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2698 #define OMAP_ISO_EP(name,addr, maxp) \
2699         buf = omap_ep_setup(name "-iso", addr, \
2700                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2701
2702         switch (fifo_mode) {
2703         case 0:
2704                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2705                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2706                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2707                 break;
2708         case 1:
2709                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2710                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2711                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2712
2713                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2714                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2715                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2716
2717                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2718                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2719                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2720
2721                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2722                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2723                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2724
2725                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2726                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2727                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2728                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2729
2730                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2731                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2732                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2733                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2734
2735                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2736                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2737
2738                 break;
2739
2740 #ifdef  USE_ISO
2741         case 2:                 /* mixed iso/bulk */
2742                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2743                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2744                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2745                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2746
2747                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2748
2749                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2750                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2751                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2752                 break;
2753         case 3:                 /* mixed bulk/iso */
2754                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2755                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2756                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2757
2758                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2759                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2760                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2761
2762                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2763                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2764                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2765                 break;
2766 #endif
2767
2768         /* add more modes as needed */
2769
2770         default:
2771                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2772                 return -ENODEV;
2773         }
2774         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2775         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2776         return 0;
2777 }
2778
2779 static int __init omap_udc_probe(struct platform_device *pdev)
2780 {
2781         int                     status = -ENODEV;
2782         int                     hmc;
2783         struct otg_transceiver  *xceiv = NULL;
2784         const char              *type = NULL;
2785         struct omap_usb_config  *config = pdev->dev.platform_data;
2786         struct clk              *dc_clk;
2787         struct clk              *hhc_clk;
2788
2789         /* NOTE:  "knows" the order of the resources! */
2790         if (!request_mem_region(pdev->resource[0].start,
2791                         pdev->resource[0].end - pdev->resource[0].start + 1,
2792                         driver_name)) {
2793                 DBG("request_mem_region failed\n");
2794                 return -EBUSY;
2795         }
2796
2797         if (cpu_is_omap16xx()) {
2798                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2799                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2800                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2801                 /* can't use omap_udc_enable_clock yet */
2802                 clk_enable(dc_clk);
2803                 clk_enable(hhc_clk);
2804                 udelay(100);
2805         }
2806
2807         if (cpu_is_omap24xx()) {
2808                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2809                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2810                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2811                 /* can't use omap_udc_enable_clock yet */
2812                 clk_enable(dc_clk);
2813                 clk_enable(hhc_clk);
2814                 udelay(100);
2815         }
2816
2817         INFO("OMAP UDC rev %d.%d%s\n",
2818                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2819                 config->otg ? ", Mini-AB" : "");
2820
2821         /* use the mode given to us by board init code */
2822         if (cpu_is_omap15xx()) {
2823                 hmc = HMC_1510;
2824                 type = "(unknown)";
2825
2826                 if (machine_is_omap_innovator() || machine_is_sx1()) {
2827                         /* just set up software VBUS detect, and then
2828                          * later rig it so we always report VBUS.
2829                          * FIXME without really sensing VBUS, we can't
2830                          * know when to turn PULLUP_EN on/off; and that
2831                          * means we always "need" the 48MHz clock.
2832                          */
2833                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2834
2835                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2836                         tmp |= VBUS_MODE_1510;
2837                         tmp &= ~VBUS_CTRL_1510;
2838                         FUNC_MUX_CTRL_0_REG = tmp;
2839                 }
2840         } else {
2841                 /* The transceiver may package some GPIO logic or handle
2842                  * loopback and/or transceiverless setup; if we find one,
2843                  * use it.  Except for OTG, we don't _need_ to talk to one;
2844                  * but not having one probably means no VBUS detection.
2845                  */
2846                 xceiv = otg_get_transceiver();
2847                 if (xceiv)
2848                         type = xceiv->label;
2849                 else if (config->otg) {
2850                         DBG("OTG requires external transceiver!\n");
2851                         goto cleanup0;
2852                 }
2853
2854                 hmc = HMC_1610;
2855
2856                 if (cpu_is_omap24xx()) {
2857                         /* this could be transceiverless in one of the
2858                          * "we don't need to know" modes.
2859                          */
2860                         type = "external";
2861                         goto known;
2862                 }
2863
2864                 switch (hmc) {
2865                 case 0:                 /* POWERUP DEFAULT == 0 */
2866                 case 4:
2867                 case 12:
2868                 case 20:
2869                         if (!cpu_is_omap1710()) {
2870                                 type = "integrated";
2871                                 break;
2872                         }
2873                         /* FALL THROUGH */
2874                 case 3:
2875                 case 11:
2876                 case 16:
2877                 case 19:
2878                 case 25:
2879                         if (!xceiv) {
2880                                 DBG("external transceiver not registered!\n");
2881                                 type = "unknown";
2882                         }
2883                         break;
2884                 case 21:                        /* internal loopback */
2885                         type = "loopback";
2886                         break;
2887                 case 14:                        /* transceiverless */
2888                         if (cpu_is_omap1710())
2889                                 goto bad_on_1710;
2890                         /* FALL THROUGH */
2891                 case 13:
2892                 case 15:
2893                         type = "no";
2894                         break;
2895
2896                 default:
2897 bad_on_1710:
2898                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2899                         goto cleanup0;
2900                 }
2901         }
2902 known:
2903         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2904
2905         /* a "gadget" abstracts/virtualizes the controller */
2906         status = omap_udc_setup(pdev, xceiv);
2907         if (status) {
2908                 goto cleanup0;
2909         }
2910         xceiv = NULL;
2911         // "udc" is now valid
2912         pullup_disable(udc);
2913 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2914         udc->gadget.is_otg = (config->otg != 0);
2915 #endif
2916
2917         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2918         if (UDC_REV_REG >= 0x61)
2919                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2920         else
2921                 udc->clr_halt = UDC_RESET_EP;
2922
2923         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2924         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2925                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2926         if (status != 0) {
2927                 ERR("can't get irq %d, err %d\n",
2928                         (int) pdev->resource[1].start, status);
2929                 goto cleanup1;
2930         }
2931
2932         /* USB "non-iso" IRQ (PIO for all but ep0) */
2933         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2934                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2935         if (status != 0) {
2936                 ERR("can't get irq %d, err %d\n",
2937                         (int) pdev->resource[2].start, status);
2938                 goto cleanup2;
2939         }
2940 #ifdef  USE_ISO
2941         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2942                         IRQF_DISABLED, "omap_udc iso", udc);
2943         if (status != 0) {
2944                 ERR("can't get irq %d, err %d\n",
2945                         (int) pdev->resource[3].start, status);
2946                 goto cleanup3;
2947         }
2948 #endif
2949         if (cpu_is_omap16xx()) {
2950                 udc->dc_clk = dc_clk;
2951                 udc->hhc_clk = hhc_clk;
2952                 clk_disable(hhc_clk);
2953                 clk_disable(dc_clk);
2954         }
2955
2956         if (cpu_is_omap24xx()) {
2957                 udc->dc_clk = dc_clk;
2958                 udc->hhc_clk = hhc_clk;
2959                 /* FIXME OMAP2 don't release hhc & dc clock */
2960 #if 0
2961                 clk_disable(hhc_clk);
2962                 clk_disable(dc_clk);
2963 #endif
2964         }
2965
2966         create_proc_file();
2967         status = device_add(&udc->gadget.dev);
2968         if (!status)
2969                 return status;
2970         /* If fail, fall through */
2971 #ifdef  USE_ISO
2972 cleanup3:
2973         free_irq(pdev->resource[2].start, udc);
2974 #endif
2975
2976 cleanup2:
2977         free_irq(pdev->resource[1].start, udc);
2978
2979 cleanup1:
2980         kfree (udc);
2981         udc = NULL;
2982
2983 cleanup0:
2984         if (xceiv)
2985                 put_device(xceiv->dev);
2986
2987         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2988                 clk_disable(hhc_clk);
2989                 clk_disable(dc_clk);
2990                 clk_put(hhc_clk);
2991                 clk_put(dc_clk);
2992         }
2993
2994         release_mem_region(pdev->resource[0].start,
2995                         pdev->resource[0].end - pdev->resource[0].start + 1);
2996
2997         return status;
2998 }
2999
3000 static int __exit omap_udc_remove(struct platform_device *pdev)
3001 {
3002         DECLARE_COMPLETION_ONSTACK(done);
3003
3004         if (!udc)
3005                 return -ENODEV;
3006         if (udc->driver)
3007                 return -EBUSY;
3008
3009         udc->done = &done;
3010
3011         pullup_disable(udc);
3012         if (udc->transceiver) {
3013                 put_device(udc->transceiver->dev);
3014                 udc->transceiver = NULL;
3015         }
3016         UDC_SYSCON1_REG = 0;
3017
3018         remove_proc_file();
3019
3020 #ifdef  USE_ISO
3021         free_irq(pdev->resource[3].start, udc);
3022 #endif
3023         free_irq(pdev->resource[2].start, udc);
3024         free_irq(pdev->resource[1].start, udc);
3025
3026         if (udc->dc_clk) {
3027                 if (udc->clk_requested)
3028                         omap_udc_enable_clock(0);
3029                 clk_put(udc->hhc_clk);
3030                 clk_put(udc->dc_clk);
3031         }
3032
3033         release_mem_region(pdev->resource[0].start,
3034                         pdev->resource[0].end - pdev->resource[0].start + 1);
3035
3036         device_unregister(&udc->gadget.dev);
3037         wait_for_completion(&done);
3038
3039         return 0;
3040 }
3041
3042 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3043  * system is forced into deep sleep
3044  *
3045  * REVISIT we should probably reject suspend requests when there's a host
3046  * session active, rather than disconnecting, at least on boards that can
3047  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3048  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3049  * may involve talking to an external transceiver (e.g. isp1301).
3050  */
3051
3052 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3053 {
3054         u32     devstat;
3055
3056         devstat = UDC_DEVSTAT_REG;
3057
3058         /* we're requesting 48 MHz clock if the pullup is enabled
3059          * (== we're attached to the host) and we're not suspended,
3060          * which would prevent entry to deep sleep...
3061          */
3062         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3063                 WARN("session active; suspend requires disconnect\n");
3064                 omap_pullup(&udc->gadget, 0);
3065         }
3066
3067         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3068         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3069         return 0;
3070 }
3071
3072 static int omap_udc_resume(struct platform_device *dev)
3073 {
3074         DBG("resume + wakeup/SRP\n");
3075         omap_pullup(&udc->gadget, 1);
3076
3077         /* maybe the host would enumerate us if we nudged it */
3078         msleep(100);
3079         return omap_wakeup(&udc->gadget);
3080 }
3081
3082 /*-------------------------------------------------------------------------*/
3083
3084 static struct platform_driver udc_driver = {
3085         .probe          = omap_udc_probe,
3086         .remove         = __exit_p(omap_udc_remove),
3087         .suspend        = omap_udc_suspend,
3088         .resume         = omap_udc_resume,
3089         .driver         = {
3090                 .owner  = THIS_MODULE,
3091                 .name   = (char *) driver_name,
3092         },
3093 };
3094
3095 static int __init udc_init(void)
3096 {
3097         INFO("%s, version: " DRIVER_VERSION
3098 #ifdef  USE_ISO
3099                 " (iso)"
3100 #endif
3101                 "%s\n", driver_desc,
3102                 use_dma ?  " (dma)" : "");
3103         return platform_driver_register(&udc_driver);
3104 }
3105 module_init(udc_init);
3106
3107 static void __exit udc_exit(void)
3108 {
3109         platform_driver_unregister(&udc_driver);
3110 }
3111 module_exit(udc_exit);
3112
3113 MODULE_DESCRIPTION(DRIVER_DESC);
3114 MODULE_LICENSE("GPL");
3115