drivers/usb/gadget/mv_udc_core.c

   1 #include <linux/module.h>
   2 #include <linux/pci.h>
   3 #include <linux/dma-mapping.h>
   4 #include <linux/dmapool.h>
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/ioport.h>
   8 #include <linux/sched.h>
   9 #include <linux/slab.h>
  10 #include <linux/errno.h>
  11 #include <linux/init.h>
  12 #include <linux/timer.h>
  13 #include <linux/list.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/device.h>
  17 #include <linux/usb/ch9.h>
  18 #include <linux/usb/gadget.h>
  19 #include <linux/usb/otg.h>
  20 #include <linux/pm.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/clk.h>
  25 #include <asm/system.h>
  26 #include <asm/unaligned.h>
  27
  28 #include "mv_udc.h"
  29
  30 #define DRIVER_DESC             "Marvell PXA USB Device Controller driver"
  31 #define DRIVER_VERSION          "8 Nov 2010"
  32
  33 #define ep_dir(ep)      (((ep)->ep_num == 0) ? \
  34                                 ((ep)->udc->ep0_dir) : ((ep)->direction))
  35
  36 /* timeout value -- usec */
  37 #define RESET_TIMEOUT           10000
  38 #define FLUSH_TIMEOUT           10000
  39 #define EPSTATUS_TIMEOUT        10000
  40 #define PRIME_TIMEOUT           10000
  41 #define READSAFE_TIMEOUT        1000
  42 #define DTD_TIMEOUT             1000
  43
  44 #define LOOPS_USEC_SHIFT        4
  45 #define LOOPS_USEC              (1 << LOOPS_USEC_SHIFT)
  46 #define LOOPS(timeout)          ((timeout) >> LOOPS_USEC_SHIFT)
  47
  48 static const char driver_name[] = "mv_udc";
  49 static const char driver_desc[] = DRIVER_DESC;
  50
  51 /* controller device global variable */
  52 static struct mv_udc    *the_controller;
  53 int mv_usb_otgsc;
  54
  55 static void nuke(struct mv_ep *ep, int status);
  56
  57 /* for endpoint 0 operations */
  58 static const struct usb_endpoint_descriptor mv_ep0_desc = {
  59         .bLength =              USB_DT_ENDPOINT_SIZE,
  60         .bDescriptorType =      USB_DT_ENDPOINT,
  61         .bEndpointAddress =     0,
  62         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  63         .wMaxPacketSize =       EP0_MAX_PKT_SIZE,
  64 };
  65
  66 static void ep0_reset(struct mv_udc *udc)
  67 {
  68         struct mv_ep *ep;
  69         u32 epctrlx;
  70         int i = 0;
  71
  72         /* ep0 in and out */
  73         for (i = 0; i < 2; i++) {
  74                 ep = &udc->eps[i];
  75                 ep->udc = udc;
  76
  77                 /* ep0 dQH */
  78                 ep->dqh = &udc->ep_dqh[i];
  79
  80                 /* configure ep0 endpoint capabilities in dQH */
  81                 ep->dqh->max_packet_length =
  82                         (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
  83                         | EP_QUEUE_HEAD_IOS;
  84
  85                 epctrlx = readl(&udc->op_regs->epctrlx[0]);
  86                 if (i) {        /* TX */
  87                         epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
  88                                 | (USB_ENDPOINT_XFER_CONTROL
  89                                         << EPCTRL_TX_EP_TYPE_SHIFT);
  90
  91                 } else {        /* RX */
  92                         epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
  93                                 | (USB_ENDPOINT_XFER_CONTROL
  94                                         << EPCTRL_RX_EP_TYPE_SHIFT);
  95                 }
  96
  97                 writel(epctrlx, &udc->op_regs->epctrlx[0]);
  98         }
  99 }
 100
 101 /* protocol ep0 stall, will automatically be cleared on new transaction */
 102 static void ep0_stall(struct mv_udc *udc)
 103 {
 104         u32     epctrlx;
 105
 106         /* set TX and RX to stall */
 107         epctrlx = readl(&udc->op_regs->epctrlx[0]);
 108         epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
 109         writel(epctrlx, &udc->op_regs->epctrlx[0]);
 110
 111         /* update ep0 state */
 112         udc->ep0_state = WAIT_FOR_SETUP;
 113         udc->ep0_dir = EP_DIR_OUT;
 114 }
 115
 116 static int process_ep_req(struct mv_udc *udc, int index,
 117         struct mv_req *curr_req)
 118 {
 119         struct mv_dtd   *curr_dtd;
 120         struct mv_dqh   *curr_dqh;
 121         int td_complete, actual, remaining_length;
 122         int i, direction;
 123         int retval = 0;
 124         u32 errors;
 125
 126         curr_dqh = &udc->ep_dqh[index];
 127         direction = index % 2;
 128
 129         curr_dtd = curr_req->head;
 130         td_complete = 0;
 131         actual = curr_req->req.length;
 132
 133         for (i = 0; i < curr_req->dtd_count; i++) {
 134                 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
 135                         dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
 136                                 udc->eps[index].name);
 137                         return 1;
 138                 }
 139
 140                 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
 141                 if (!errors) {
 142                         remaining_length +=
 143                                 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
 144                                         >> DTD_LENGTH_BIT_POS;
 145                         actual -= remaining_length;
 146                 } else {
 147                         dev_info(&udc->dev->dev,
 148                                 "complete_tr error: ep=%d %s: error = 0x%x\n",
 149                                 index >> 1, direction ? "SEND" : "RECV",
 150                                 errors);
 151                         if (errors & DTD_STATUS_HALTED) {
 152                                 /* Clear the errors and Halt condition */
 153                                 curr_dqh->size_ioc_int_sts &= ~errors;
 154                                 retval = -EPIPE;
 155                         } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
 156                                 retval = -EPROTO;
 157                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
 158                                 retval = -EILSEQ;
 159                         }
 160                 }
 161                 if (i != curr_req->dtd_count - 1)
 162                         curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
 163         }
 164         if (retval)
 165                 return retval;
 166
 167         curr_req->req.actual = actual;
 168
 169         return 0;
 170 }
 171
 172 /*
 173  * done() - retire a request; caller blocked irqs
 174  * @status : request status to be set, only works when
 175  * request is still in progress.
 176  */
 177 static void done(struct mv_ep *ep, struct mv_req *req, int status)
 178 {
 179         struct mv_udc *udc = NULL;
 180         unsigned char stopped = ep->stopped;
 181         struct mv_dtd *curr_td, *next_td;
 182         int j;
 183
 184         udc = (struct mv_udc *)ep->udc;
 185         /* Removed the req from fsl_ep->queue */
 186         list_del_init(&req->queue);
 187
 188         /* req.status should be set as -EINPROGRESS in ep_queue() */
 189         if (req->req.status == -EINPROGRESS)
 190                 req->req.status = status;
 191         else
 192                 status = req->req.status;
 193
 194         /* Free dtd for the request */
 195         next_td = req->head;
 196         for (j = 0; j < req->dtd_count; j++) {
 197                 curr_td = next_td;
 198                 if (j != req->dtd_count - 1)
 199                         next_td = curr_td->next_dtd_virt;
 200                 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
 201         }
 202
 203         if (req->mapped) {
 204                 dma_unmap_single(ep->udc->gadget.dev.parent,
 205                         req->req.dma, req->req.length,
 206                         ((ep_dir(ep) == EP_DIR_IN) ?
 207                                 DMA_TO_DEVICE : DMA_FROM_DEVICE));
 208                 req->req.dma = DMA_ADDR_INVALID;
 209                 req->mapped = 0;
 210         } else
 211                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 212                         req->req.dma, req->req.length,
 213                         ((ep_dir(ep) == EP_DIR_IN) ?
 214                                 DMA_TO_DEVICE : DMA_FROM_DEVICE));
 215
 216         if (status && (status != -ESHUTDOWN))
 217                 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
 218                         ep->ep.name, &req->req, status,
 219                         req->req.actual, req->req.length);
 220
 221         ep->stopped = 1;
 222
 223         spin_unlock(&ep->udc->lock);
 224         /*
 225          * complete() is from gadget layer,
 226          * eg fsg->bulk_in_complete()
 227          */
 228         if (req->req.complete)
 229                 req->req.complete(&ep->ep, &req->req);
 230
 231         spin_lock(&ep->udc->lock);
 232         ep->stopped = stopped;
 233 }
 234
 235 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
 236 {
 237         u32 tmp, epstatus, bit_pos, direction;
 238         struct mv_udc *udc;
 239         struct mv_dqh *dqh;
 240         unsigned int loops;
 241         int readsafe, retval = 0;
 242
 243         udc = ep->udc;
 244         direction = ep_dir(ep);
 245         dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
 246         bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
 247
 248         /* check if the pipe is empty */
 249         if (!(list_empty(&ep->queue))) {
 250                 struct mv_req *lastreq;
 251                 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
 252                 lastreq->tail->dtd_next =
 253                         req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 254                 if (readl(&udc->op_regs->epprime) & bit_pos) {
 255                         loops = LOOPS(PRIME_TIMEOUT);
 256                         while (readl(&udc->op_regs->epprime) & bit_pos) {
 257                                 if (loops == 0) {
 258                                         retval = -ETIME;
 259                                         goto done;
 260                                 }
 261                                 udelay(LOOPS_USEC);
 262                                 loops--;
 263                         }
 264                         if (readl(&udc->op_regs->epstatus) & bit_pos)
 265                                 goto done;
 266                 }
 267                 readsafe = 0;
 268                 loops = LOOPS(READSAFE_TIMEOUT);
 269                 while (readsafe == 0) {
 270                         if (loops == 0) {
 271                                 retval = -ETIME;
 272                                 goto done;
 273                         }
 274                         /* start with setting the semaphores */
 275                         tmp = readl(&udc->op_regs->usbcmd);
 276                         tmp |= USBCMD_ATDTW_TRIPWIRE_SET;
 277                         writel(tmp, &udc->op_regs->usbcmd);
 278
 279                         /* read the endpoint status */
 280                         epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
 281
 282                         /*
 283                          * Reread the ATDTW semaphore bit to check if it is
 284                          * cleared. When hardware see a hazard, it will clear
 285                          * the bit or else we remain set to 1 and we can
 286                          * proceed with priming of endpoint if not already
 287                          * primed.
 288                          */
 289                         if (readl(&udc->op_regs->usbcmd)
 290                                 & USBCMD_ATDTW_TRIPWIRE_SET) {
 291                                 readsafe = 1;
 292                         }
 293                         loops--;
 294                         udelay(LOOPS_USEC);
 295                 }
 296
 297                 /* Clear the semaphore */
 298                 tmp = readl(&udc->op_regs->usbcmd);
 299                 tmp &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
 300                 writel(tmp, &udc->op_regs->usbcmd);
 301
 302                 /* If endpoint is not active, we activate it now. */
 303                 if (!epstatus) {
 304                         if (direction == EP_DIR_IN) {
 305                                 struct mv_dtd *curr_dtd = dma_to_virt(
 306                                         &udc->dev->dev, dqh->curr_dtd_ptr);
 307
 308                                 loops = LOOPS(DTD_TIMEOUT);
 309                                 while (curr_dtd->size_ioc_sts
 310                                         & DTD_STATUS_ACTIVE) {
 311                                         if (loops == 0) {
 312                                                 retval = -ETIME;
 313                                                 goto done;
 314                                         }
 315                                         loops--;
 316                                         udelay(LOOPS_USEC);
 317                                 }
 318                         }
 319                         /* No other transfers on the queue */
 320
 321                         /* Write dQH next pointer and terminate bit to 0 */
 322                         dqh->next_dtd_ptr = req->head->td_dma
 323                                 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 324                         dqh->size_ioc_int_sts = 0;
 325
 326                         /*
 327                          * Ensure that updates to the QH will
 328                          * occur before priming.
 329                          */
 330                         wmb();
 331
 332                         /* Prime the Endpoint */
 333                         writel(bit_pos, &udc->op_regs->epprime);
 334                 }
 335         } else {
 336                 /* Write dQH next pointer and terminate bit to 0 */
 337                 dqh->next_dtd_ptr = req->head->td_dma
 338                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK;;
 339                 dqh->size_ioc_int_sts = 0;
 340
 341                 /* Ensure that updates to the QH will occur before priming. */
 342                 wmb();
 343
 344                 /* Prime the Endpoint */
 345                 writel(bit_pos, &udc->op_regs->epprime);
 346
 347                 if (direction == EP_DIR_IN) {
 348                         /* FIXME add status check after prime the IN ep */
 349                         int prime_again;
 350                         u32 curr_dtd_ptr = dqh->curr_dtd_ptr;
 351
 352                         loops = LOOPS(DTD_TIMEOUT);
 353                         prime_again = 0;
 354                         while ((curr_dtd_ptr != req->head->td_dma)) {
 355                                 curr_dtd_ptr = dqh->curr_dtd_ptr;
 356                                 if (loops == 0) {
 357                                         dev_err(&udc->dev->dev,
 358                                                 "failed to prime %s\n",
 359                                                 ep->name);
 360                                         retval = -ETIME;
 361                                         goto done;
 362                                 }
 363                                 loops--;
 364                                 udelay(LOOPS_USEC);
 365
 366                                 if (loops == (LOOPS(DTD_TIMEOUT) >> 2)) {
 367                                         if (prime_again)
 368                                                 goto done;
 369                                         dev_info(&udc->dev->dev,
 370                                                 "prime again\n");
 371                                         writel(bit_pos,
 372                                                 &udc->op_regs->epprime);
 373                                         prime_again = 1;
 374                                 }
 375                         }
 376                 }
 377         }
 378 done:
 379         return retval;;
 380 }
 381
 382 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
 383                 dma_addr_t *dma, int *is_last)
 384 {
 385         u32 temp;
 386         struct mv_dtd *dtd;
 387         struct mv_udc *udc;
 388
 389         /* how big will this transfer be? */
 390         *length = min(req->req.length - req->req.actual,
 391                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 392
 393         udc = req->ep->udc;
 394
 395         /*
 396          * Be careful that no _GFP_HIGHMEM is set,
 397          * or we can not use dma_to_virt
 398          */
 399         dtd = dma_pool_alloc(udc->dtd_pool, GFP_KERNEL, dma);
 400         if (dtd == NULL)
 401                 return dtd;
 402
 403         dtd->td_dma = *dma;
 404         /* initialize buffer page pointers */
 405         temp = (u32)(req->req.dma + req->req.actual);
 406         dtd->buff_ptr0 = cpu_to_le32(temp);
 407         temp &= ~0xFFF;
 408         dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
 409         dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
 410         dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
 411         dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
 412
 413         req->req.actual += *length;
 414
 415         /* zlp is needed if req->req.zero is set */
 416         if (req->req.zero) {
 417                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 418                         *is_last = 1;
 419                 else
 420                         *is_last = 0;
 421         } else if (req->req.length == req->req.actual)
 422                 *is_last = 1;
 423         else
 424                 *is_last = 0;
 425
 426         /* Fill in the transfer size; set active bit */
 427         temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 428
 429         /* Enable interrupt for the last dtd of a request */
 430         if (*is_last && !req->req.no_interrupt)
 431                 temp |= DTD_IOC;
 432
 433         dtd->size_ioc_sts = temp;
 434
 435         mb();
 436
 437         return dtd;
 438 }
 439
 440 /* generate dTD linked list for a request */
 441 static int req_to_dtd(struct mv_req *req)
 442 {
 443         unsigned count;
 444         int is_last, is_first = 1;
 445         struct mv_dtd *dtd, *last_dtd = NULL;
 446         struct mv_udc *udc;
 447         dma_addr_t dma;
 448
 449         udc = req->ep->udc;
 450
 451         do {
 452                 dtd = build_dtd(req, &count, &dma, &is_last);
 453                 if (dtd == NULL)
 454                         return -ENOMEM;
 455
 456                 if (is_first) {
 457                         is_first = 0;
 458                         req->head = dtd;
 459                 } else {
 460                         last_dtd->dtd_next = dma;
 461                         last_dtd->next_dtd_virt = dtd;
 462                 }
 463                 last_dtd = dtd;
 464                 req->dtd_count++;
 465         } while (!is_last);
 466
 467         /* set terminate bit to 1 for the last dTD */
 468         dtd->dtd_next = DTD_NEXT_TERMINATE;
 469
 470         req->tail = dtd;
 471
 472         return 0;
 473 }
 474
 475 static int mv_ep_enable(struct usb_ep *_ep,
 476                 const struct usb_endpoint_descriptor *desc)
 477 {
 478         struct mv_udc *udc;
 479         struct mv_ep *ep;
 480         struct mv_dqh *dqh;
 481         u16 max = 0;
 482         u32 bit_pos, epctrlx, direction;
 483         unsigned char zlt = 0, ios = 0, mult = 0;
 484
 485         ep = container_of(_ep, struct mv_ep, ep);
 486         udc = ep->udc;
 487
 488         if (!_ep || !desc || ep->desc
 489                         || desc->bDescriptorType != USB_DT_ENDPOINT)
 490                 return -EINVAL;
 491
 492         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 493                 return -ESHUTDOWN;
 494
 495         direction = ep_dir(ep);
 496         max = le16_to_cpu(desc->wMaxPacketSize);
 497
 498         /*
 499          * disable HW zero length termination select
 500          * driver handles zero length packet through req->req.zero
 501          */
 502         zlt = 1;
 503
 504         /* Get the endpoint queue head address */
 505         dqh = (struct mv_dqh *)ep->dqh;
 506
 507         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 508
 509         /* Check if the Endpoint is Primed */
 510         if ((readl(&udc->op_regs->epprime) & bit_pos)
 511                 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
 512                 dev_info(&udc->dev->dev,
 513                         "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
 514                         " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
 515                         (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
 516                         (unsigned)readl(&udc->op_regs->epprime),
 517                         (unsigned)readl(&udc->op_regs->epstatus),
 518                         (unsigned)bit_pos);
 519                 goto en_done;
 520         }
 521         /* Set the max packet length, interrupt on Setup and Mult fields */
 522         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 523         case USB_ENDPOINT_XFER_BULK:
 524                 zlt = 1;
 525                 mult = 0;
 526                 break;
 527         case USB_ENDPOINT_XFER_CONTROL:
 528                 ios = 1;
 529         case USB_ENDPOINT_XFER_INT:
 530                 mult = 0;
 531                 break;
 532         case USB_ENDPOINT_XFER_ISOC:
 533                 /* Calculate transactions needed for high bandwidth iso */
 534                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 535                 max = max & 0x8ff;      /* bit 0~10 */
 536                 /* 3 transactions at most */
 537                 if (mult > 3)
 538                         goto en_done;
 539                 break;
 540         default:
 541                 goto en_done;
 542         }
 543         dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 544                 | (mult << EP_QUEUE_HEAD_MULT_POS)
 545                 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
 546                 | (ios ? EP_QUEUE_HEAD_IOS : 0);
 547         dqh->next_dtd_ptr = 1;
 548         dqh->size_ioc_int_sts = 0;
 549
 550         ep->ep.maxpacket = max;
 551         ep->desc = desc;
 552         ep->stopped = 0;
 553
 554         /* Enable the endpoint for Rx or Tx and set the endpoint type */
 555         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 556         if (direction == EP_DIR_IN) {
 557                 epctrlx &= ~EPCTRL_TX_ALL_MASK;
 558                 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
 559                         | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 560                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 561         } else {
 562                 epctrlx &= ~EPCTRL_RX_ALL_MASK;
 563                 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
 564                         | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 565                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 566         }
 567         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 568
 569         /*
 570          * Implement Guideline (GL# USB-7) The unused endpoint type must
 571          * be programmed to bulk.
 572          */
 573         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 574         if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
 575                 epctrlx |= ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 576                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 577                 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 578         }
 579
 580         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 581         if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
 582                 epctrlx |= ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 583                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 584                 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 585         }
 586
 587         return 0;
 588 en_done:
 589         return -EINVAL;
 590 }
 591
 592 static int  mv_ep_disable(struct usb_ep *_ep)
 593 {
 594         struct mv_udc *udc;
 595         struct mv_ep *ep;
 596         struct mv_dqh *dqh;
 597         u32 bit_pos, epctrlx, direction;
 598
 599         ep = container_of(_ep, struct mv_ep, ep);
 600         if ((_ep == NULL) || !ep->desc)
 601                 return -EINVAL;
 602
 603         udc = ep->udc;
 604
 605         /* Get the endpoint queue head address */
 606         dqh = ep->dqh;
 607
 608         direction = ep_dir(ep);
 609         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 610
 611         /* Reset the max packet length and the interrupt on Setup */
 612         dqh->max_packet_length = 0;
 613
 614         /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 615         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 616         epctrlx &= ~((direction == EP_DIR_IN)
 617                         ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
 618                         : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
 619         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 620
 621         /* nuke all pending requests (does flush) */
 622         nuke(ep, -ESHUTDOWN);
 623
 624         ep->desc = NULL;
 625         ep->stopped = 1;
 626         return 0;
 627 }
 628
 629 static struct usb_request *
 630 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 631 {
 632         struct mv_req *req = NULL;
 633
 634         req = kzalloc(sizeof *req, gfp_flags);
 635         if (!req)
 636                 return NULL;
 637
 638         req->req.dma = DMA_ADDR_INVALID;
 639         INIT_LIST_HEAD(&req->queue);
 640
 641         return &req->req;
 642 }
 643
 644 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
 645 {
 646         struct mv_req *req = NULL;
 647
 648         req = container_of(_req, struct mv_req, req);
 649
 650         if (_req)
 651                 kfree(req);
 652 }
 653
 654 static void mv_ep_fifo_flush(struct usb_ep *_ep)
 655 {
 656         struct mv_udc *udc;
 657         u32 bit_pos, direction;
 658         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 659         unsigned int loops;
 660
 661         udc = ep->udc;
 662         direction = ep_dir(ep);
 663         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 664         /*
 665          * Flushing will halt the pipe
 666          * Write 1 to the Flush register
 667          */
 668         writel(bit_pos, &udc->op_regs->epflush);
 669
 670         /* Wait until flushing completed */
 671         loops = LOOPS(FLUSH_TIMEOUT);
 672         while (readl(&udc->op_regs->epflush) & bit_pos) {
 673                 /*
 674                  * ENDPTFLUSH bit should be cleared to indicate this
 675                  * operation is complete
 676                  */
 677                 if (loops == 0) {
 678                         dev_err(&udc->dev->dev,
 679                                 "TIMEOUT for ENDPTFLUSH=0x%x, bit_pos=0x%x\n",
 680                                 (unsigned)readl(&udc->op_regs->epflush),
 681                                 (unsigned)bit_pos);
 682                         return;
 683                 }
 684                 loops--;
 685                 udelay(LOOPS_USEC);
 686         }
 687         loops = LOOPS(EPSTATUS_TIMEOUT);
 688         while (readl(&udc->op_regs->epstatus) & bit_pos) {
 689                 unsigned int inter_loops;
 690
 691                 if (loops == 0) {
 692                         dev_err(&udc->dev->dev,
 693                                 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
 694                                 (unsigned)readl(&udc->op_regs->epstatus),
 695                                 (unsigned)bit_pos);
 696                         return;
 697                 }
 698                 /* Write 1 to the Flush register */
 699                 writel(bit_pos, &udc->op_regs->epflush);
 700
 701                 /* Wait until flushing completed */
 702                 inter_loops = LOOPS(FLUSH_TIMEOUT);
 703                 while (readl(&udc->op_regs->epflush) & bit_pos) {
 704                         /*
 705                          * ENDPTFLUSH bit should be cleared to indicate this
 706                          * operation is complete
 707                          */
 708                         if (inter_loops == 0) {
 709                                 dev_err(&udc->dev->dev,
 710                                         "TIMEOUT for ENDPTFLUSH=0x%x,"
 711                                         "bit_pos=0x%x\n",
 712                                         (unsigned)readl(&udc->op_regs->epflush),
 713                                         (unsigned)bit_pos);
 714                                 return;
 715                         }
 716                         inter_loops--;
 717                         udelay(LOOPS_USEC);
 718                 }
 719                 loops--;
 720         }
 721 }
 722
 723 /* queues (submits) an I/O request to an endpoint */
 724 static int
 725 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 726 {
 727         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 728         struct mv_req *req = container_of(_req, struct mv_req, req);
 729         struct mv_udc *udc = ep->udc;
 730         unsigned long flags;
 731
 732         /* catch various bogus parameters */
 733         if (!_req || !req->req.complete || !req->req.buf
 734                         || !list_empty(&req->queue)) {
 735                 dev_err(&udc->dev->dev, "%s, bad params", __func__);
 736                 return -EINVAL;
 737         }
 738         if (unlikely(!_ep || !ep->desc)) {
 739                 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
 740                 return -EINVAL;
 741         }
 742         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 743                 if (req->req.length > ep->ep.maxpacket)
 744                         return -EMSGSIZE;
 745         }
 746
 747         udc = ep->udc;
 748         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 749                 return -ESHUTDOWN;
 750
 751         req->ep = ep;
 752
 753         /* map virtual address to hardware */
 754         if (req->req.dma == DMA_ADDR_INVALID) {
 755                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 756                                         req->req.buf,
 757                                         req->req.length, ep_dir(ep)
 758                                                 ? DMA_TO_DEVICE
 759                                                 : DMA_FROM_DEVICE);
 760                 req->mapped = 1;
 761         } else {
 762                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 763                                         req->req.dma, req->req.length,
 764                                         ep_dir(ep)
 765                                                 ? DMA_TO_DEVICE
 766                                                 : DMA_FROM_DEVICE);
 767                 req->mapped = 0;
 768         }
 769
 770         req->req.status = -EINPROGRESS;
 771         req->req.actual = 0;
 772         req->dtd_count = 0;
 773
 774         spin_lock_irqsave(&udc->lock, flags);
 775
 776         /* build dtds and push them to device queue */
 777         if (!req_to_dtd(req)) {
 778                 int retval;
 779                 retval = queue_dtd(ep, req);
 780                 if (retval) {
 781                         spin_unlock_irqrestore(&udc->lock, flags);
 782                         return retval;
 783                 }
 784         } else {
 785                 spin_unlock_irqrestore(&udc->lock, flags);
 786                 return -ENOMEM;
 787         }
 788
 789         /* Update ep0 state */
 790         if (ep->ep_num == 0)
 791                 udc->ep0_state = DATA_STATE_XMIT;
 792
 793         /* irq handler advances the queue */
 794         if (req != NULL)
 795                 list_add_tail(&req->queue, &ep->queue);
 796         spin_unlock_irqrestore(&udc->lock, flags);
 797
 798         return 0;
 799 }
 800
 801 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 802 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 803 {
 804         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 805         struct mv_req *req;
 806         struct mv_udc *udc = ep->udc;
 807         unsigned long flags;
 808         int stopped, ret = 0;
 809         u32 epctrlx;
 810
 811         if (!_ep || !_req)
 812                 return -EINVAL;
 813
 814         spin_lock_irqsave(&ep->udc->lock, flags);
 815         stopped = ep->stopped;
 816
 817         /* Stop the ep before we deal with the queue */
 818         ep->stopped = 1;
 819         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 820         if (ep_dir(ep) == EP_DIR_IN)
 821                 epctrlx &= ~EPCTRL_TX_ENABLE;
 822         else
 823                 epctrlx &= ~EPCTRL_RX_ENABLE;
 824         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 825
 826         /* make sure it's actually queued on this endpoint */
 827         list_for_each_entry(req, &ep->queue, queue) {
 828                 if (&req->req == _req)
 829                         break;
 830         }
 831         if (&req->req != _req) {
 832                 ret = -EINVAL;
 833                 goto out;
 834         }
 835
 836         /* The request is in progress, or completed but not dequeued */
 837         if (ep->queue.next == &req->queue) {
 838                 _req->status = -ECONNRESET;
 839                 mv_ep_fifo_flush(_ep);  /* flush current transfer */
 840
 841                 /* The request isn't the last request in this ep queue */
 842                 if (req->queue.next != &ep->queue) {
 843                         struct mv_dqh *qh;
 844                         struct mv_req *next_req;
 845
 846                         qh = ep->dqh;
 847                         next_req = list_entry(req->queue.next, struct mv_req,
 848                                         queue);
 849
 850                         /* Point the QH to the first TD of next request */
 851                         writel((u32) next_req->head, &qh->curr_dtd_ptr);
 852                 } else {
 853                         struct mv_dqh *qh;
 854
 855                         qh = ep->dqh;
 856                         qh->next_dtd_ptr = 1;
 857                         qh->size_ioc_int_sts = 0;
 858                 }
 859
 860                 /* The request hasn't been processed, patch up the TD chain */
 861         } else {
 862                 struct mv_req *prev_req;
 863
 864                 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
 865                 writel(readl(&req->tail->dtd_next),
 866                                 &prev_req->tail->dtd_next);
 867
 868         }
 869
 870         done(ep, req, -ECONNRESET);
 871
 872         /* Enable EP */
 873 out:
 874         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 875         if (ep_dir(ep) == EP_DIR_IN)
 876                 epctrlx |= EPCTRL_TX_ENABLE;
 877         else
 878                 epctrlx |= EPCTRL_RX_ENABLE;
 879         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 880         ep->stopped = stopped;
 881
 882         spin_unlock_irqrestore(&ep->udc->lock, flags);
 883         return ret;
 884 }
 885
 886 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
 887 {
 888         u32 epctrlx;
 889
 890         epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
 891
 892         if (stall) {
 893                 if (direction == EP_DIR_IN)
 894                         epctrlx |= EPCTRL_TX_EP_STALL;
 895                 else
 896                         epctrlx |= EPCTRL_RX_EP_STALL;
 897         } else {
 898                 if (direction == EP_DIR_IN) {
 899                         epctrlx &= ~EPCTRL_TX_EP_STALL;
 900                         epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
 901                 } else {
 902                         epctrlx &= ~EPCTRL_RX_EP_STALL;
 903                         epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
 904                 }
 905         }
 906         writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
 907 }
 908
 909 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
 910 {
 911         u32 epctrlx;
 912
 913         epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
 914
 915         if (direction == EP_DIR_OUT)
 916                 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
 917         else
 918                 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
 919 }
 920
 921 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 922 {
 923         struct mv_ep *ep;
 924         unsigned long flags = 0;
 925         int status = 0;
 926         struct mv_udc *udc;
 927
 928         ep = container_of(_ep, struct mv_ep, ep);
 929         udc = ep->udc;
 930         if (!_ep || !ep->desc) {
 931                 status = -EINVAL;
 932                 goto out;
 933         }
 934
 935         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 936                 status = -EOPNOTSUPP;
 937                 goto out;
 938         }
 939
 940         /*
 941          * Attempt to halt IN ep will fail if any transfer requests
 942          * are still queue
 943          */
 944         if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
 945                 status = -EAGAIN;
 946                 goto out;
 947         }
 948
 949         spin_lock_irqsave(&ep->udc->lock, flags);
 950         ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
 951         if (halt && wedge)
 952                 ep->wedge = 1;
 953         else if (!halt)
 954                 ep->wedge = 0;
 955         spin_unlock_irqrestore(&ep->udc->lock, flags);
 956
 957         if (ep->ep_num == 0) {
 958                 udc->ep0_state = WAIT_FOR_SETUP;
 959                 udc->ep0_dir = EP_DIR_OUT;
 960         }
 961 out:
 962         return status;
 963 }
 964
 965 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
 966 {
 967         return mv_ep_set_halt_wedge(_ep, halt, 0);
 968 }
 969
 970 static int mv_ep_set_wedge(struct usb_ep *_ep)
 971 {
 972         return mv_ep_set_halt_wedge(_ep, 1, 1);
 973 }
 974
 975 static struct usb_ep_ops mv_ep_ops = {
 976         .enable         = mv_ep_enable,
 977         .disable        = mv_ep_disable,
 978
 979         .alloc_request  = mv_alloc_request,
 980         .free_request   = mv_free_request,
 981
 982         .queue          = mv_ep_queue,
 983         .dequeue        = mv_ep_dequeue,
 984
 985         .set_wedge      = mv_ep_set_wedge,
 986         .set_halt       = mv_ep_set_halt,
 987         .fifo_flush     = mv_ep_fifo_flush,     /* flush fifo */
 988 };
 989
 990 static void udc_stop(struct mv_udc *udc)
 991 {
 992         u32 tmp;
 993
 994         /* Disable interrupts */
 995         tmp = readl(&udc->op_regs->usbintr);
 996         tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
 997                 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
 998         writel(tmp, &udc->op_regs->usbintr);
 999
1000         /* Reset the Run the bit in the command register to stop VUSB */
1001         tmp = readl(&udc->op_regs->usbcmd);
1002         tmp &= ~USBCMD_RUN_STOP;
1003         writel(tmp, &udc->op_regs->usbcmd);
1004 }
1005
1006 static void udc_start(struct mv_udc *udc)
1007 {
1008         u32 usbintr;
1009
1010         usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1011                 | USBINTR_PORT_CHANGE_DETECT_EN
1012                 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1013         /* Enable interrupts */
1014         writel(usbintr, &udc->op_regs->usbintr);
1015
1016         /* Set the Run bit in the command register */
1017         writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1018 }
1019
1020 static int udc_reset(struct mv_udc *udc)
1021 {
1022         unsigned int loops;
1023         u32 tmp, portsc;
1024
1025         /* Stop the controller */
1026         tmp = readl(&udc->op_regs->usbcmd);
1027         tmp &= ~USBCMD_RUN_STOP;
1028         writel(tmp, &udc->op_regs->usbcmd);
1029
1030         /* Reset the controller to get default values */
1031         writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1032
1033         /* wait for reset to complete */
1034         loops = LOOPS(RESET_TIMEOUT);
1035         while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1036                 if (loops == 0) {
1037                         dev_err(&udc->dev->dev,
1038                                 "Wait for RESET completed TIMEOUT\n");
1039                         return -ETIMEDOUT;
1040                 }
1041                 loops--;
1042                 udelay(LOOPS_USEC);
1043         }
1044
1045         /* set controller to device mode */
1046         tmp = readl(&udc->op_regs->usbmode);
1047         tmp |= USBMODE_CTRL_MODE_DEVICE;
1048
1049         /* turn setup lockout off, require setup tripwire in usbcmd */
1050         tmp |= USBMODE_SETUP_LOCK_OFF | USBMODE_STREAM_DISABLE;
1051
1052         writel(tmp, &udc->op_regs->usbmode);
1053
1054         writel(0x0, &udc->op_regs->epsetupstat);
1055
1056         /* Configure the Endpoint List Address */
1057         writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1058                 &udc->op_regs->eplistaddr);
1059
1060         portsc = readl(&udc->op_regs->portsc[0]);
1061         if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1062                 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1063
1064         if (udc->force_fs)
1065                 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1066         else
1067                 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1068
1069         writel(portsc, &udc->op_regs->portsc[0]);
1070
1071         tmp = readl(&udc->op_regs->epctrlx[0]);
1072         tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1073         writel(tmp, &udc->op_regs->epctrlx[0]);
1074
1075         return 0;
1076 }
1077
1078 static int mv_udc_get_frame(struct usb_gadget *gadget)
1079 {
1080         struct mv_udc *udc;
1081         u16     retval;
1082
1083         if (!gadget)
1084                 return -ENODEV;
1085
1086         udc = container_of(gadget, struct mv_udc, gadget);
1087
1088         retval = readl(udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1089
1090         return retval;
1091 }
1092
1093 /* Tries to wake up the host connected to this gadget */
1094 static int mv_udc_wakeup(struct usb_gadget *gadget)
1095 {
1096         struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1097         u32 portsc;
1098
1099         /* Remote wakeup feature not enabled by host */
1100         if (!udc->remote_wakeup)
1101                 return -ENOTSUPP;
1102
1103         portsc = readl(&udc->op_regs->portsc);
1104         /* not suspended? */
1105         if (!(portsc & PORTSCX_PORT_SUSPEND))
1106                 return 0;
1107         /* trigger force resume */
1108         portsc |= PORTSCX_PORT_FORCE_RESUME;
1109         writel(portsc, &udc->op_regs->portsc[0]);
1110         return 0;
1111 }
1112
1113 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1114 {
1115         struct mv_udc *udc;
1116         unsigned long flags;
1117
1118         udc = container_of(gadget, struct mv_udc, gadget);
1119         spin_lock_irqsave(&udc->lock, flags);
1120
1121         udc->softconnect = (is_on != 0);
1122         if (udc->driver && udc->softconnect)
1123                 udc_start(udc);
1124         else
1125                 udc_stop(udc);
1126
1127         spin_unlock_irqrestore(&udc->lock, flags);
1128         return 0;
1129 }
1130
1131 /* device controller usb_gadget_ops structure */
1132 static const struct usb_gadget_ops mv_ops = {
1133
1134         /* returns the current frame number */
1135         .get_frame      = mv_udc_get_frame,
1136
1137         /* tries to wake up the host connected to this gadget */
1138         .wakeup         = mv_udc_wakeup,
1139
1140         /* D+ pullup, software-controlled connect/disconnect to USB host */
1141         .pullup         = mv_udc_pullup,
1142 };
1143
1144 static void mv_udc_testmode(struct mv_udc *udc, u16 index, bool enter)
1145 {
1146         dev_info(&udc->dev->dev, "Test Mode is not support yet\n");
1147 }
1148
1149 static int eps_init(struct mv_udc *udc)
1150 {
1151         struct mv_ep    *ep;
1152         char name[14];
1153         int i;
1154
1155         /* initialize ep0 */
1156         ep = &udc->eps[0];
1157         ep->udc = udc;
1158         strncpy(ep->name, "ep0", sizeof(ep->name));
1159         ep->ep.name = ep->name;
1160         ep->ep.ops = &mv_ep_ops;
1161         ep->wedge = 0;
1162         ep->stopped = 0;
1163         ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1164         ep->ep_num = 0;
1165         ep->desc = &mv_ep0_desc;
1166         INIT_LIST_HEAD(&ep->queue);
1167
1168         ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1169
1170         /* initialize other endpoints */
1171         for (i = 2; i < udc->max_eps * 2; i++) {
1172                 ep = &udc->eps[i];
1173                 if (i % 2) {
1174                         snprintf(name, sizeof(name), "ep%din", i / 2);
1175                         ep->direction = EP_DIR_IN;
1176                 } else {
1177                         snprintf(name, sizeof(name), "ep%dout", i / 2);
1178                         ep->direction = EP_DIR_OUT;
1179                 }
1180                 ep->udc = udc;
1181                 strncpy(ep->name, name, sizeof(ep->name));
1182                 ep->ep.name = ep->name;
1183
1184                 ep->ep.ops = &mv_ep_ops;
1185                 ep->stopped = 0;
1186                 ep->ep.maxpacket = (unsigned short) ~0;
1187                 ep->ep_num = i / 2;
1188
1189                 INIT_LIST_HEAD(&ep->queue);
1190                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1191
1192                 ep->dqh = &udc->ep_dqh[i];
1193         }
1194
1195         return 0;
1196 }
1197
1198 /* delete all endpoint requests, called with spinlock held */
1199 static void nuke(struct mv_ep *ep, int status)
1200 {
1201         /* called with spinlock held */
1202         ep->stopped = 1;
1203
1204         /* endpoint fifo flush */
1205         mv_ep_fifo_flush(&ep->ep);
1206
1207         while (!list_empty(&ep->queue)) {
1208                 struct mv_req *req = NULL;
1209                 req = list_entry(ep->queue.next, struct mv_req, queue);
1210                 done(ep, req, status);
1211         }
1212 }
1213
1214 /* stop all USB activities */
1215 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1216 {
1217         struct mv_ep    *ep;
1218
1219         nuke(&udc->eps[0], -ESHUTDOWN);
1220
1221         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1222                 nuke(ep, -ESHUTDOWN);
1223         }
1224
1225         /* report disconnect; the driver is already quiesced */
1226         if (driver) {
1227                 spin_unlock(&udc->lock);
1228                 driver->disconnect(&udc->gadget);
1229                 spin_lock(&udc->lock);
1230         }
1231 }
1232
1233 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1234                 int (*bind)(struct usb_gadget *))
1235 {
1236         struct mv_udc *udc = the_controller;
1237         int retval = 0;
1238         unsigned long flags;
1239
1240         if (!udc)
1241                 return -ENODEV;
1242
1243         if (udc->driver)
1244                 return -EBUSY;
1245
1246         spin_lock_irqsave(&udc->lock, flags);
1247
1248         /* hook up the driver ... */
1249         driver->driver.bus = NULL;
1250         udc->driver = driver;
1251         udc->gadget.dev.driver = &driver->driver;
1252
1253         udc->usb_state = USB_STATE_ATTACHED;
1254         udc->ep0_state = WAIT_FOR_SETUP;
1255         udc->ep0_dir = USB_DIR_OUT;
1256
1257         spin_unlock_irqrestore(&udc->lock, flags);
1258
1259         retval = bind(&udc->gadget);
1260         if (retval) {
1261                 dev_err(&udc->dev->dev, "bind to driver %s --> %d\n",
1262                                 driver->driver.name, retval);
1263                 udc->driver = NULL;
1264                 udc->gadget.dev.driver = NULL;
1265                 return retval;
1266         }
1267         udc_reset(udc);
1268         ep0_reset(udc);
1269         udc_start(udc);
1270
1271         return 0;
1272 }
1273 EXPORT_SYMBOL(usb_gadget_probe_driver);
1274
1275 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1276 {
1277         struct mv_udc *udc = the_controller;
1278         unsigned long flags;
1279
1280         if (!udc)
1281                 return -ENODEV;
1282
1283         udc_stop(udc);
1284
1285         spin_lock_irqsave(&udc->lock, flags);
1286
1287         /* stop all usb activities */
1288         udc->gadget.speed = USB_SPEED_UNKNOWN;
1289         stop_activity(udc, driver);
1290         spin_unlock_irqrestore(&udc->lock, flags);
1291
1292         /* unbind gadget driver */
1293         driver->unbind(&udc->gadget);
1294         udc->gadget.dev.driver = NULL;
1295         udc->driver = NULL;
1296
1297         return 0;
1298 }
1299 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1300
1301 static int
1302 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1303 {
1304         int retval = 0;
1305         struct mv_req *req;
1306         struct mv_ep *ep;
1307
1308         ep = &udc->eps[0];
1309         udc->ep0_dir = direction;
1310
1311         req = udc->status_req;
1312
1313         /* fill in the reqest structure */
1314         if (empty == false) {
1315                 *((u16 *) req->req.buf) = cpu_to_le16(status);
1316                 req->req.length = 2;
1317         } else
1318                 req->req.length = 0;
1319
1320         req->ep = ep;
1321         req->req.status = -EINPROGRESS;
1322         req->req.actual = 0;
1323         req->req.complete = NULL;
1324         req->dtd_count = 0;
1325
1326         /* prime the data phase */
1327         if (!req_to_dtd(req))
1328                 retval = queue_dtd(ep, req);
1329         else{   /* no mem */
1330                 retval = -ENOMEM;
1331                 goto out;
1332         }
1333
1334         if (retval) {
1335                 dev_err(&udc->dev->dev, "response error on GET_STATUS request\n");
1336                 goto out;
1337         }
1338
1339         list_add_tail(&req->queue, &ep->queue);
1340
1341         return 0;
1342 out:
1343         return retval;
1344 }
1345
1346 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1347 {
1348         udc->dev_addr = (u8)setup->wValue;
1349
1350         /* update usb state */
1351         udc->usb_state = USB_STATE_ADDRESS;
1352
1353         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1354                 ep0_stall(udc);
1355 }
1356
1357 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1358         struct usb_ctrlrequest *setup)
1359 {
1360         u16 status;
1361         int retval;
1362
1363         if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1364                 != (USB_DIR_IN | USB_TYPE_STANDARD))
1365                 return;
1366
1367         if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1368                 status = 1 << USB_DEVICE_SELF_POWERED;
1369                 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1370         } else if ((setup->bRequestType & USB_RECIP_MASK)
1371                         == USB_RECIP_INTERFACE) {
1372                 /* get interface status */
1373                 status = 0;
1374         } else if ((setup->bRequestType & USB_RECIP_MASK)
1375                         == USB_RECIP_ENDPOINT) {
1376                 u8 ep_num, direction;
1377
1378                 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1379                 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1380                                 ? EP_DIR_IN : EP_DIR_OUT;
1381                 status = ep_is_stall(udc, ep_num, direction)
1382                                 << USB_ENDPOINT_HALT;
1383         }
1384
1385         retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1386         if (retval)
1387                 ep0_stall(udc);
1388 }
1389
1390 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1391 {
1392         u8 ep_num;
1393         u8 direction;
1394         struct mv_ep *ep;
1395
1396         if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1397                 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1398                 switch (setup->wValue) {
1399                 case USB_DEVICE_REMOTE_WAKEUP:
1400                         udc->remote_wakeup = 0;
1401                         break;
1402                 case USB_DEVICE_TEST_MODE:
1403                         mv_udc_testmode(udc, 0, false);
1404                         break;
1405                 default:
1406                         goto out;
1407                 }
1408         } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1409                 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1410                 switch (setup->wValue) {
1411                 case USB_ENDPOINT_HALT:
1412                         ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1413                         direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1414                                 ? EP_DIR_IN : EP_DIR_OUT;
1415                         if (setup->wValue != 0 || setup->wLength != 0
1416                                 || ep_num > udc->max_eps)
1417                                 goto out;
1418                         ep = &udc->eps[ep_num * 2 + direction];
1419                         if (ep->wedge == 1)
1420                                 break;
1421                         spin_unlock(&udc->lock);
1422                         ep_set_stall(udc, ep_num, direction, 0);
1423                         spin_lock(&udc->lock);
1424                         break;
1425                 default:
1426                         goto out;
1427                 }
1428         } else
1429                 goto out;
1430
1431         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1432                 ep0_stall(udc);
1433         else
1434                 udc->ep0_state = DATA_STATE_XMIT;
1435 out:
1436         return;
1437 }
1438
1439 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1440 {
1441         u8 ep_num;
1442         u8 direction;
1443
1444         if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1445                 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1446                 switch (setup->wValue) {
1447                 case USB_DEVICE_REMOTE_WAKEUP:
1448                         udc->remote_wakeup = 1;
1449                         break;
1450                 case USB_DEVICE_TEST_MODE:
1451                         if (setup->wIndex & 0xFF
1452                                 && udc->gadget.speed != USB_SPEED_HIGH)
1453                                 goto out;
1454                         if (udc->usb_state == USB_STATE_CONFIGURED
1455                                 || udc->usb_state == USB_STATE_ADDRESS
1456                                 || udc->usb_state == USB_STATE_DEFAULT)
1457                                 mv_udc_testmode(udc,
1458                                         setup->wIndex & 0xFF00, true);
1459                         else
1460                                 goto out;
1461                         break;
1462                 default:
1463                         goto out;
1464                 }
1465         } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1466                 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1467                 switch (setup->wValue) {
1468                 case USB_ENDPOINT_HALT:
1469                         ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1470                         direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1471                                 ? EP_DIR_IN : EP_DIR_OUT;
1472                         if (setup->wValue != 0 || setup->wLength != 0
1473                                 || ep_num > udc->max_eps)
1474                                 goto out;
1475                         spin_unlock(&udc->lock);
1476                         ep_set_stall(udc, ep_num, direction, 1);
1477                         spin_lock(&udc->lock);
1478                         break;
1479                 default:
1480                         goto out;
1481                 }
1482         } else
1483                 goto out;
1484
1485         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1486                 ep0_stall(udc);
1487 out:
1488         return;
1489 }
1490
1491 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1492         struct usb_ctrlrequest *setup)
1493 {
1494         bool delegate = false;
1495
1496         nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1497
1498         dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1499                         setup->bRequestType, setup->bRequest,
1500                         setup->wValue, setup->wIndex, setup->wLength);
1501         /* We process some stardard setup requests here */
1502         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1503                 switch (setup->bRequest) {
1504                 case USB_REQ_GET_STATUS:
1505                         ch9getstatus(udc, ep_num, setup);
1506                         break;
1507
1508                 case USB_REQ_SET_ADDRESS:
1509                         ch9setaddress(udc, setup);
1510                         break;
1511
1512                 case USB_REQ_CLEAR_FEATURE:
1513                         ch9clearfeature(udc, setup);
1514                         break;
1515
1516                 case USB_REQ_SET_FEATURE:
1517                         ch9setfeature(udc, setup);
1518                         break;
1519
1520                 default:
1521                         delegate = true;
1522                 }
1523         } else
1524                 delegate = true;
1525
1526         /* delegate USB standard requests to the gadget driver */
1527         if (delegate == true) {
1528                 /* USB requests handled by gadget */
1529                 if (setup->wLength) {
1530                         /* DATA phase from gadget, STATUS phase from udc */
1531                         udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1532                                         ?  EP_DIR_IN : EP_DIR_OUT;
1533                         spin_unlock(&udc->lock);
1534                         if (udc->driver->setup(&udc->gadget,
1535                                 &udc->local_setup_buff) < 0)
1536                                 ep0_stall(udc);
1537                         spin_lock(&udc->lock);
1538                         udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1539                                         ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1540                 } else {
1541                         /* no DATA phase, IN STATUS phase from gadget */
1542                         udc->ep0_dir = EP_DIR_IN;
1543                         spin_unlock(&udc->lock);
1544                         if (udc->driver->setup(&udc->gadget,
1545                                 &udc->local_setup_buff) < 0)
1546                                 ep0_stall(udc);
1547                         spin_lock(&udc->lock);
1548                         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1549                 }
1550         }
1551 }
1552
1553 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1554 static void ep0_req_complete(struct mv_udc *udc,
1555         struct mv_ep *ep0, struct mv_req *req)
1556 {
1557         u32 new_addr;
1558
1559         if (udc->usb_state == USB_STATE_ADDRESS) {
1560                 /* set the new address */
1561                 new_addr = (u32)udc->dev_addr;
1562                 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1563                         &udc->op_regs->deviceaddr);
1564         }
1565
1566         done(ep0, req, 0);
1567
1568         switch (udc->ep0_state) {
1569         case DATA_STATE_XMIT:
1570                 /* receive status phase */
1571                 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1572                         ep0_stall(udc);
1573                 break;
1574         case DATA_STATE_RECV:
1575                 /* send status phase */
1576                 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1577                         ep0_stall(udc);
1578                 break;
1579         case WAIT_FOR_OUT_STATUS:
1580                 udc->ep0_state = WAIT_FOR_SETUP;
1581                 break;
1582         case WAIT_FOR_SETUP:
1583                 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1584                 break;
1585         default:
1586                 ep0_stall(udc);
1587                 break;
1588         }
1589 }
1590
1591 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1592 {
1593         u32 temp;
1594         struct mv_dqh *dqh;
1595
1596         dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1597
1598         /* Clear bit in ENDPTSETUPSTAT */
1599         temp = readl(&udc->op_regs->epsetupstat);
1600         writel(temp | (1 << ep_num), &udc->op_regs->epsetupstat);
1601
1602         /* while a hazard exists when setup package arrives */
1603         do {
1604                 /* Set Setup Tripwire */
1605                 temp = readl(&udc->op_regs->usbcmd);
1606                 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1607
1608                 /* Copy the setup packet to local buffer */
1609                 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1610         } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1611
1612         /* Clear Setup Tripwire */
1613         temp = readl(&udc->op_regs->usbcmd);
1614         writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1615 }
1616
1617 static void irq_process_tr_complete(struct mv_udc *udc)
1618 {
1619         u32 tmp, bit_pos;
1620         int i, ep_num = 0, direction = 0;
1621         struct mv_ep    *curr_ep;
1622         struct mv_req *curr_req, *temp_req;
1623         int status;
1624
1625         /*
1626          * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1627          * because the setup packets are to be read ASAP
1628          */
1629
1630         /* Process all Setup packet received interrupts */
1631         tmp = readl(&udc->op_regs->epsetupstat);
1632
1633         if (tmp) {
1634                 for (i = 0; i < udc->max_eps; i++) {
1635                         if (tmp & (1 << i)) {
1636                                 get_setup_data(udc, i,
1637                                         (u8 *)(&udc->local_setup_buff));
1638                                 handle_setup_packet(udc, i,
1639                                         &udc->local_setup_buff);
1640                         }
1641                 }
1642         }
1643
1644         /* Don't clear the endpoint setup status register here.
1645          * It is cleared as a setup packet is read out of the buffer
1646          */
1647
1648         /* Process non-setup transaction complete interrupts */
1649         tmp = readl(&udc->op_regs->epcomplete);
1650
1651         if (!tmp)
1652                 return;
1653
1654         writel(tmp, &udc->op_regs->epcomplete);
1655
1656         for (i = 0; i < udc->max_eps * 2; i++) {
1657                 ep_num = i >> 1;
1658                 direction = i % 2;
1659
1660                 bit_pos = 1 << (ep_num + 16 * direction);
1661
1662                 if (!(bit_pos & tmp))
1663                         continue;
1664
1665                 if (i == 1)
1666                         curr_ep = &udc->eps[0];
1667                 else
1668                         curr_ep = &udc->eps[i];
1669                 /* process the req queue until an uncomplete request */
1670                 list_for_each_entry_safe(curr_req, temp_req,
1671                         &curr_ep->queue, queue) {
1672                         status = process_ep_req(udc, i, curr_req);
1673                         if (status)
1674                                 break;
1675
1676                         /* write back status to req */
1677                         curr_req->req.status = status;
1678
1679                         /* ep0 request completion */
1680                         if (ep_num == 0) {
1681                                 ep0_req_complete(udc, curr_ep, curr_req);
1682                                 break;
1683                         } else {
1684                                 done(curr_ep, curr_req, status);
1685                         }
1686                 }
1687         }
1688 }
1689
1690 void irq_process_reset(struct mv_udc *udc)
1691 {
1692         u32 tmp;
1693         unsigned int loops;
1694
1695         udc->ep0_dir = EP_DIR_OUT;
1696         udc->ep0_state = WAIT_FOR_SETUP;
1697         udc->remote_wakeup = 0;         /* default to 0 on reset */
1698
1699         /* The address bits are past bit 25-31. Set the address */
1700         tmp = readl(&udc->op_regs->deviceaddr);
1701         tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1702         writel(tmp, &udc->op_regs->deviceaddr);
1703
1704         /* Clear all the setup token semaphores */
1705         tmp = readl(&udc->op_regs->epsetupstat);
1706         writel(tmp, &udc->op_regs->epsetupstat);
1707
1708         /* Clear all the endpoint complete status bits */
1709         tmp = readl(&udc->op_regs->epcomplete);
1710         writel(tmp, &udc->op_regs->epcomplete);
1711
1712         /* wait until all endptprime bits cleared */
1713         loops = LOOPS(PRIME_TIMEOUT);
1714         while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1715                 if (loops == 0) {
1716                         dev_err(&udc->dev->dev,
1717                                 "Timeout for ENDPTPRIME = 0x%x\n",
1718                                 readl(&udc->op_regs->epprime));
1719                         break;
1720                 }
1721                 loops--;
1722                 udelay(LOOPS_USEC);
1723         }
1724
1725         /* Write 1s to the Flush register */
1726         writel((u32)~0, &udc->op_regs->epflush);
1727
1728         if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1729                 dev_info(&udc->dev->dev, "usb bus reset\n");
1730                 udc->usb_state = USB_STATE_DEFAULT;
1731                 /* reset all the queues, stop all USB activities */
1732                 stop_activity(udc, udc->driver);
1733         } else {
1734                 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1735                         readl(&udc->op_regs->portsc));
1736
1737                 /*
1738                  * re-initialize
1739                  * controller reset
1740                  */
1741                 udc_reset(udc);
1742
1743                 /* reset all the queues, stop all USB activities */
1744                 stop_activity(udc, udc->driver);
1745
1746                 /* reset ep0 dQH and endptctrl */
1747                 ep0_reset(udc);
1748
1749                 /* enable interrupt and set controller to run state */
1750                 udc_start(udc);
1751
1752                 udc->usb_state = USB_STATE_ATTACHED;
1753         }
1754 }
1755
1756 static void handle_bus_resume(struct mv_udc *udc)
1757 {
1758         udc->usb_state = udc->resume_state;
1759         udc->resume_state = 0;
1760
1761         /* report resume to the driver */
1762         if (udc->driver) {
1763                 if (udc->driver->resume) {
1764                         spin_unlock(&udc->lock);
1765                         udc->driver->resume(&udc->gadget);
1766                         spin_lock(&udc->lock);
1767                 }
1768         }
1769 }
1770
1771 static void irq_process_suspend(struct mv_udc *udc)
1772 {
1773         udc->resume_state = udc->usb_state;
1774         udc->usb_state = USB_STATE_SUSPENDED;
1775
1776         if (udc->driver->suspend) {
1777                 spin_unlock(&udc->lock);
1778                 udc->driver->suspend(&udc->gadget);
1779                 spin_lock(&udc->lock);
1780         }
1781 }
1782
1783 static void irq_process_port_change(struct mv_udc *udc)
1784 {
1785         u32 portsc;
1786
1787         portsc = readl(&udc->op_regs->portsc[0]);
1788         if (!(portsc & PORTSCX_PORT_RESET)) {
1789                 /* Get the speed */
1790                 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1791                 switch (speed) {
1792                 case PORTSCX_PORT_SPEED_HIGH:
1793                         udc->gadget.speed = USB_SPEED_HIGH;
1794                         break;
1795                 case PORTSCX_PORT_SPEED_FULL:
1796                         udc->gadget.speed = USB_SPEED_FULL;
1797                         break;
1798                 case PORTSCX_PORT_SPEED_LOW:
1799                         udc->gadget.speed = USB_SPEED_LOW;
1800                         break;
1801                 default:
1802                         udc->gadget.speed = USB_SPEED_UNKNOWN;
1803                         break;
1804                 }
1805         }
1806
1807         if (portsc & PORTSCX_PORT_SUSPEND) {
1808                 udc->resume_state = udc->usb_state;
1809                 udc->usb_state = USB_STATE_SUSPENDED;
1810                 if (udc->driver->suspend) {
1811                         spin_unlock(&udc->lock);
1812                         udc->driver->suspend(&udc->gadget);
1813                         spin_lock(&udc->lock);
1814                 }
1815         }
1816
1817         if (!(portsc & PORTSCX_PORT_SUSPEND)
1818                 && udc->usb_state == USB_STATE_SUSPENDED) {
1819                 handle_bus_resume(udc);
1820         }
1821
1822         if (!udc->resume_state)
1823                 udc->usb_state = USB_STATE_DEFAULT;
1824 }
1825
1826 static void irq_process_error(struct mv_udc *udc)
1827 {
1828         /* Increment the error count */
1829         udc->errors++;
1830 }
1831
1832 static irqreturn_t mv_udc_irq(int irq, void *dev)
1833 {
1834         struct mv_udc *udc = (struct mv_udc *)dev;
1835         u32 status, intr;
1836
1837         spin_lock(&udc->lock);
1838
1839         status = readl(&udc->op_regs->usbsts);
1840         intr = readl(&udc->op_regs->usbintr);
1841         status &= intr;
1842
1843         if (status == 0) {
1844                 spin_unlock(&udc->lock);
1845                 return IRQ_NONE;
1846         }
1847
1848         /* Clear all the interrupts occurred */
1849         writel(status, &udc->op_regs->usbsts);
1850
1851         if (status & USBSTS_ERR)
1852                 irq_process_error(udc);
1853
1854         if (status & USBSTS_RESET)
1855                 irq_process_reset(udc);
1856
1857         if (status & USBSTS_PORT_CHANGE)
1858                 irq_process_port_change(udc);
1859
1860         if (status & USBSTS_INT)
1861                 irq_process_tr_complete(udc);
1862
1863         if (status & USBSTS_SUSPEND)
1864                 irq_process_suspend(udc);
1865
1866         spin_unlock(&udc->lock);
1867
1868         return IRQ_HANDLED;
1869 }
1870
1871 /* release device structure */
1872 static void gadget_release(struct device *_dev)
1873 {
1874         struct mv_udc *udc = the_controller;
1875
1876         complete(udc->done);
1877         kfree(udc);
1878 }
1879
1880 static int mv_udc_remove(struct platform_device *dev)
1881 {
1882         struct mv_udc *udc = the_controller;
1883
1884         DECLARE_COMPLETION(done);
1885
1886         udc->done = &done;
1887
1888         /* free memory allocated in probe */
1889         if (udc->dtd_pool)
1890                 dma_pool_destroy(udc->dtd_pool);
1891
1892         if (udc->ep_dqh)
1893                 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
1894                         udc->ep_dqh, udc->ep_dqh_dma);
1895
1896         kfree(udc->eps);
1897
1898         if (udc->irq)
1899                 free_irq(udc->irq, &dev->dev);
1900
1901         if (udc->cap_regs)
1902                 iounmap(udc->cap_regs);
1903         udc->cap_regs = NULL;
1904
1905         if (udc->phy_regs)
1906                 iounmap((void *)udc->phy_regs);
1907         udc->phy_regs = 0;
1908
1909         if (udc->status_req) {
1910                 kfree(udc->status_req->req.buf);
1911                 kfree(udc->status_req);
1912         }
1913
1914         device_unregister(&udc->gadget.dev);
1915
1916         /* free dev, wait for the release() finished */
1917         wait_for_completion(&done);
1918
1919         the_controller = NULL;
1920
1921         return 0;
1922 }
1923
1924 int mv_udc_probe(struct platform_device *dev)
1925 {
1926         struct mv_udc *udc;
1927         int retval = 0;
1928         struct resource *r;
1929         size_t size;
1930
1931         udc = kzalloc(sizeof *udc, GFP_KERNEL);
1932         if (udc == NULL) {
1933                 dev_err(&dev->dev, "failed to allocate memory for udc\n");
1934                 retval = -ENOMEM;
1935                 goto error;
1936         }
1937
1938         spin_lock_init(&udc->lock);
1939
1940         udc->dev = dev;
1941
1942         udc->clk = clk_get(&dev->dev, "U2OCLK");
1943         if (IS_ERR(udc->clk)) {
1944                 retval = PTR_ERR(udc->clk);
1945                 goto error;
1946         }
1947
1948         r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "u2o");
1949         if (r == NULL) {
1950                 dev_err(&dev->dev, "no I/O memory resource defined\n");
1951                 retval = -ENODEV;
1952                 goto error;
1953         }
1954
1955         udc->cap_regs = (struct mv_cap_regs __iomem *)
1956                 ioremap(r->start, resource_size(r));
1957         if (udc->cap_regs == NULL) {
1958                 dev_err(&dev->dev, "failed to map I/O memory\n");
1959                 retval = -EBUSY;
1960                 goto error;
1961         }
1962
1963         r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "u2ophy");
1964         if (r == NULL) {
1965                 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
1966                 retval = -ENODEV;
1967                 goto error;
1968         }
1969
1970         udc->phy_regs = (unsigned int)ioremap(r->start, resource_size(r));
1971         if (udc->phy_regs == 0) {
1972                 dev_err(&dev->dev, "failed to map phy I/O memory\n");
1973                 retval = -EBUSY;
1974                 goto error;
1975         }
1976
1977         /* we will acces controller register, so enable the clk */
1978         clk_enable(udc->clk);
1979         retval = mv_udc_phy_init(udc->phy_regs);
1980         if (retval) {
1981                 dev_err(&dev->dev, "phy initialization error %d\n", retval);
1982                 goto error;
1983         }
1984
1985         udc->op_regs = (struct mv_op_regs __iomem *)((u32)udc->cap_regs
1986                 + (readl(&udc->cap_regs->caplength_hciversion)
1987                         & CAPLENGTH_MASK));
1988         udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
1989
1990         size = udc->max_eps * sizeof(struct mv_dqh) *2;
1991         size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
1992         udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
1993                                         &udc->ep_dqh_dma, GFP_KERNEL);
1994
1995         if (udc->ep_dqh == NULL) {
1996                 dev_err(&dev->dev, "allocate dQH memory failed\n");
1997                 retval = -ENOMEM;
1998                 goto error;
1999         }
2000         udc->ep_dqh_size = size;
2001
2002         /* create dTD dma_pool resource */
2003         udc->dtd_pool = dma_pool_create("mv_dtd",
2004                         &dev->dev,
2005                         sizeof(struct mv_dtd),
2006                         DTD_ALIGNMENT,
2007                         DMA_BOUNDARY);
2008
2009         if (!udc->dtd_pool) {
2010                 retval = -ENOMEM;
2011                 goto error;
2012         }
2013
2014         size = udc->max_eps * sizeof(struct mv_ep) *2;
2015         udc->eps = kzalloc(size, GFP_KERNEL);
2016         if (udc->eps == NULL) {
2017                 dev_err(&dev->dev, "allocate ep memory failed\n");
2018                 retval = -ENOMEM;
2019                 goto error;
2020         }
2021
2022         /* initialize ep0 status request structure */
2023         udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2024         if (!udc->status_req) {
2025                 dev_err(&dev->dev, "allocate status_req memory failed\n");
2026                 retval = -ENOMEM;
2027                 goto error;
2028         }
2029         INIT_LIST_HEAD(&udc->status_req->queue);
2030
2031         /* allocate a small amount of memory to get valid address */
2032         udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2033         udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
2034
2035         udc->resume_state = USB_STATE_NOTATTACHED;
2036         udc->usb_state = USB_STATE_POWERED;
2037         udc->ep0_dir = EP_DIR_OUT;
2038         udc->remote_wakeup = 0;
2039
2040         r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2041         if (r == NULL) {
2042                 dev_err(&dev->dev, "no IRQ resource defined\n");
2043                 retval = -ENODEV;
2044                 goto error;
2045         }
2046         udc->irq = r->start;
2047         if (request_irq(udc->irq, mv_udc_irq,
2048                 IRQF_DISABLED | IRQF_SHARED, driver_name, udc)) {
2049                 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2050                         udc->irq);
2051                 retval = -ENODEV;
2052                 goto error;
2053         }
2054
2055         /* initialize gadget structure */
2056         udc->gadget.ops = &mv_ops;      /* usb_gadget_ops */
2057         udc->gadget.ep0 = &udc->eps[0].ep;      /* gadget ep0 */
2058         INIT_LIST_HEAD(&udc->gadget.ep_list);   /* ep_list */
2059         udc->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
2060         udc->gadget.is_dualspeed = 1;           /* support dual speed */
2061
2062         /* the "gadget" abstracts/virtualizes the controller */
2063         dev_set_name(&udc->gadget.dev, "gadget");
2064         udc->gadget.dev.parent = &dev->dev;
2065         udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2066         udc->gadget.dev.release = gadget_release;
2067         udc->gadget.name = driver_name;         /* gadget name */
2068
2069         retval = device_register(&udc->gadget.dev);
2070         if (retval)
2071                 goto error;
2072
2073         eps_init(udc);
2074
2075         the_controller = udc;
2076
2077         goto out;
2078 error:
2079         if (udc)
2080                 mv_udc_remove(udc->dev);
2081 out:
2082         return retval;
2083 }
2084
2085 #ifdef CONFIG_PM
2086 static int mv_udc_suspend(struct device *_dev)
2087 {
2088         struct mv_udc *udc = the_controller;
2089
2090         udc_stop(udc);
2091
2092         return 0;
2093 }
2094
2095 static int mv_udc_resume(struct device *_dev)
2096 {
2097         struct mv_udc *udc = the_controller;
2098         int retval;
2099
2100         retval = mv_udc_phy_init(udc->phy_regs);
2101         if (retval) {
2102                 dev_err(_dev, "phy initialization error %d\n", retval);
2103                 return retval;
2104         }
2105         udc_reset(udc);
2106         ep0_reset(udc);
2107         udc_start(udc);
2108
2109         return 0;
2110 }
2111
2112 static const struct dev_pm_ops mv_udc_pm_ops = {
2113         .suspend        = mv_udc_suspend,
2114         .resume         = mv_udc_resume,
2115 };
2116 #endif
2117
2118 static struct platform_driver udc_driver = {
2119         .probe          = mv_udc_probe,
2120         .remove         = __exit_p(mv_udc_remove),
2121         .driver         = {
2122                 .owner  = THIS_MODULE,
2123                 .name   = "pxa-u2o",
2124 #ifdef CONFIG_PM
2125                 .pm     = &mv_udc_pm_ops,
2126 #endif
2127         },
2128 };
2129
2130
2131 MODULE_DESCRIPTION(DRIVER_DESC);
2132 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2133 MODULE_VERSION(DRIVER_VERSION);
2134 MODULE_LICENSE("GPL");
2135
2136
2137 static int __init init(void)
2138 {
2139         return platform_driver_register(&udc_driver);
2140 }
2141 module_init(init);
2142
2143
2144 static void __exit cleanup(void)
2145 {
2146         platform_driver_unregister(&udc_driver);
2147 }
2148 module_exit(cleanup);
2149