drivers/usb/gadget/fsl_udc_core.c

   1 /*
   2  * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Author: Li Yang <leoli@freescale.com>
   6  *         Jiang Bo <tanya.jiang@freescale.com>
   7  *
   8  * Description:
   9  * Freescale high-speed USB SOC DR module device controller driver.
  10  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  11  * The driver is previously named as mpc_udc.  Based on bare board
  12  * code from Dave Liu and Shlomi Gridish.
  13  *
  14  * This program is free software; you can redistribute  it and/or modify it
  15  * under  the terms of  the GNU General  Public License as published by the
  16  * Free Software Foundation;  either version 2 of the  License, or (at your
  17  * option) any later version.
  18  */
  19
  20 #undef VERBOSE
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/ioport.h>
  25 #include <linux/types.h>
  26 #include <linux/errno.h>
  27 #include <linux/slab.h>
  28 #include <linux/init.h>
  29 #include <linux/list.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/proc_fs.h>
  32 #include <linux/mm.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include <linux/usb/ch9.h>
  36 #include <linux/usb/gadget.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/fsl_devices.h>
  41 #include <linux/dmapool.h>
  42 #include <linux/delay.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/io.h>
  46 #include <asm/system.h>
  47 #include <asm/unaligned.h>
  48 #include <asm/dma.h>
  49
  50 #include "fsl_usb2_udc.h"
  51
  52 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  53 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  54 #define DRIVER_VERSION  "Apr 20, 2007"
  55
  56 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  57
  58 static const char driver_name[] = "fsl-usb2-udc";
  59 static const char driver_desc[] = DRIVER_DESC;
  60
  61 static struct usb_dr_device *dr_regs;
  62 #ifndef CONFIG_ARCH_MXC
  63 static struct usb_sys_interface *usb_sys_regs;
  64 #endif
  65
  66 /* it is initialized in probe()  */
  67 static struct fsl_udc *udc_controller = NULL;
  68
  69 static const struct usb_endpoint_descriptor
  70 fsl_ep0_desc = {
  71         .bLength =              USB_DT_ENDPOINT_SIZE,
  72         .bDescriptorType =      USB_DT_ENDPOINT,
  73         .bEndpointAddress =     0,
  74         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  75         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  76 };
  77
  78 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  79
  80 #ifdef CONFIG_PPC32
  81 /*
  82  * On some SoCs, the USB controller registers can be big or little endian,
  83  * depending on the version of the chip. In order to be able to run the
  84  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  85  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  86  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  87  * call through those pointers. Platform code for SoCs that have BE USB
  88  * registers should set pdata->big_endian_mmio flag.
  89  *
  90  * This also applies to controller-to-cpu accessors for the USB descriptors,
  91  * since their endianness is also SoC dependant. Platform code for SoCs that
  92  * have BE USB descriptors should set pdata->big_endian_desc flag.
  93  */
  94 static u32 _fsl_readl_be(const unsigned __iomem *p)
  95 {
  96         return in_be32(p);
  97 }
  98
  99 static u32 _fsl_readl_le(const unsigned __iomem *p)
 100 {
 101         return in_le32(p);
 102 }
 103
 104 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
 105 {
 106         out_be32(p, v);
 107 }
 108
 109 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 110 {
 111         out_le32(p, v);
 112 }
 113
 114 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 115 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 116
 117 #define fsl_readl(p)            (*_fsl_readl)((p))
 118 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 119
 120 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 121 {
 122         if (pdata->big_endian_mmio) {
 123                 _fsl_readl = _fsl_readl_be;
 124                 _fsl_writel = _fsl_writel_be;
 125         } else {
 126                 _fsl_readl = _fsl_readl_le;
 127                 _fsl_writel = _fsl_writel_le;
 128         }
 129 }
 130
 131 static inline u32 cpu_to_hc32(const u32 x)
 132 {
 133         return udc_controller->pdata->big_endian_desc
 134                 ? (__force u32)cpu_to_be32(x)
 135                 : (__force u32)cpu_to_le32(x);
 136 }
 137
 138 static inline u32 hc32_to_cpu(const u32 x)
 139 {
 140         return udc_controller->pdata->big_endian_desc
 141                 ? be32_to_cpu((__force __be32)x)
 142                 : le32_to_cpu((__force __le32)x);
 143 }
 144 #else /* !CONFIG_PPC32 */
 145 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 146
 147 #define fsl_readl(addr)         readl(addr)
 148 #define fsl_writel(val32, addr) writel(val32, addr)
 149 #define cpu_to_hc32(x)          cpu_to_le32(x)
 150 #define hc32_to_cpu(x)          le32_to_cpu(x)
 151 #endif /* CONFIG_PPC32 */
 152
 153 /********************************************************************
 154  *      Internal Used Function
 155 ********************************************************************/
 156 /*-----------------------------------------------------------------
 157  * done() - retire a request; caller blocked irqs
 158  * @status : request status to be set, only works when
 159  *      request is still in progress.
 160  *--------------------------------------------------------------*/
 161 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 162 {
 163         struct fsl_udc *udc = NULL;
 164         unsigned char stopped = ep->stopped;
 165         struct ep_td_struct *curr_td, *next_td;
 166         int j;
 167
 168         udc = (struct fsl_udc *)ep->udc;
 169         /* Removed the req from fsl_ep->queue */
 170         list_del_init(&req->queue);
 171
 172         /* req.status should be set as -EINPROGRESS in ep_queue() */
 173         if (req->req.status == -EINPROGRESS)
 174                 req->req.status = status;
 175         else
 176                 status = req->req.status;
 177
 178         /* Free dtd for the request */
 179         next_td = req->head;
 180         for (j = 0; j < req->dtd_count; j++) {
 181                 curr_td = next_td;
 182                 if (j != req->dtd_count - 1) {
 183                         next_td = curr_td->next_td_virt;
 184                 }
 185                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 186         }
 187
 188         if (req->mapped) {
 189                 dma_unmap_single(ep->udc->gadget.dev.parent,
 190                         req->req.dma, req->req.length,
 191                         ep_is_in(ep)
 192                                 ? DMA_TO_DEVICE
 193                                 : DMA_FROM_DEVICE);
 194                 req->req.dma = DMA_ADDR_INVALID;
 195                 req->mapped = 0;
 196         } else
 197                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 198                         req->req.dma, req->req.length,
 199                         ep_is_in(ep)
 200                                 ? DMA_TO_DEVICE
 201                                 : DMA_FROM_DEVICE);
 202
 203         if (status && (status != -ESHUTDOWN))
 204                 VDBG("complete %s req %p stat %d len %u/%u",
 205                         ep->ep.name, &req->req, status,
 206                         req->req.actual, req->req.length);
 207
 208         ep->stopped = 1;
 209
 210         spin_unlock(&ep->udc->lock);
 211         /* complete() is from gadget layer,
 212          * eg fsg->bulk_in_complete() */
 213         if (req->req.complete)
 214                 req->req.complete(&ep->ep, &req->req);
 215
 216         spin_lock(&ep->udc->lock);
 217         ep->stopped = stopped;
 218 }
 219
 220 /*-----------------------------------------------------------------
 221  * nuke(): delete all requests related to this ep
 222  * called with spinlock held
 223  *--------------------------------------------------------------*/
 224 static void nuke(struct fsl_ep *ep, int status)
 225 {
 226         ep->stopped = 1;
 227
 228         /* Flush fifo */
 229         fsl_ep_fifo_flush(&ep->ep);
 230
 231         /* Whether this eq has request linked */
 232         while (!list_empty(&ep->queue)) {
 233                 struct fsl_req *req = NULL;
 234
 235                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 236                 done(ep, req, status);
 237         }
 238 }
 239
 240 /*------------------------------------------------------------------
 241         Internal Hardware related function
 242  ------------------------------------------------------------------*/
 243
 244 static int dr_controller_setup(struct fsl_udc *udc)
 245 {
 246         unsigned int tmp, portctrl, ep_num;
 247         unsigned int max_no_of_ep;
 248 #ifndef CONFIG_ARCH_MXC
 249         unsigned int ctrl;
 250 #endif
 251         unsigned long timeout;
 252 #define FSL_UDC_RESET_TIMEOUT 1000
 253
 254         /* Config PHY interface */
 255         portctrl = fsl_readl(&dr_regs->portsc1);
 256         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 257         switch (udc->phy_mode) {
 258         case FSL_USB2_PHY_ULPI:
 259                 portctrl |= PORTSCX_PTS_ULPI;
 260                 break;
 261         case FSL_USB2_PHY_UTMI_WIDE:
 262                 portctrl |= PORTSCX_PTW_16BIT;
 263                 /* fall through */
 264         case FSL_USB2_PHY_UTMI:
 265                 portctrl |= PORTSCX_PTS_UTMI;
 266                 break;
 267         case FSL_USB2_PHY_SERIAL:
 268                 portctrl |= PORTSCX_PTS_FSLS;
 269                 break;
 270         default:
 271                 return -EINVAL;
 272         }
 273         fsl_writel(portctrl, &dr_regs->portsc1);
 274
 275         /* Stop and reset the usb controller */
 276         tmp = fsl_readl(&dr_regs->usbcmd);
 277         tmp &= ~USB_CMD_RUN_STOP;
 278         fsl_writel(tmp, &dr_regs->usbcmd);
 279
 280         tmp = fsl_readl(&dr_regs->usbcmd);
 281         tmp |= USB_CMD_CTRL_RESET;
 282         fsl_writel(tmp, &dr_regs->usbcmd);
 283
 284         /* Wait for reset to complete */
 285         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 286         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 287                 if (time_after(jiffies, timeout)) {
 288                         ERR("udc reset timeout!\n");
 289                         return -ETIMEDOUT;
 290                 }
 291                 cpu_relax();
 292         }
 293
 294         /* Set the controller as device mode */
 295         tmp = fsl_readl(&dr_regs->usbmode);
 296         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 297         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 298         /* Disable Setup Lockout */
 299         tmp |= USB_MODE_SETUP_LOCK_OFF;
 300         if (udc->pdata->es)
 301                 tmp |= USB_MODE_ES;
 302         fsl_writel(tmp, &dr_regs->usbmode);
 303
 304         /* Clear the setup status */
 305         fsl_writel(0, &dr_regs->usbsts);
 306
 307         tmp = udc->ep_qh_dma;
 308         tmp &= USB_EP_LIST_ADDRESS_MASK;
 309         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 310
 311         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 312                 udc->ep_qh, (int)tmp,
 313                 fsl_readl(&dr_regs->endpointlistaddr));
 314
 315         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 316         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 317                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 318                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 319                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 320                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 321                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 322         }
 323         /* Config control enable i/o output, cpu endian register */
 324 #ifndef CONFIG_ARCH_MXC
 325         if (udc->pdata->have_sysif_regs) {
 326                 ctrl = __raw_readl(&usb_sys_regs->control);
 327                 ctrl |= USB_CTRL_IOENB;
 328                 __raw_writel(ctrl, &usb_sys_regs->control);
 329         }
 330 #endif
 331
 332 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 333         /* Turn on cache snooping hardware, since some PowerPC platforms
 334          * wholly rely on hardware to deal with cache coherent. */
 335
 336         if (udc->pdata->have_sysif_regs) {
 337                 /* Setup Snooping for all the 4GB space */
 338                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 339                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 340                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 341                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 342         }
 343 #endif
 344
 345         return 0;
 346 }
 347
 348 /* Enable DR irq and set controller to run state */
 349 static void dr_controller_run(struct fsl_udc *udc)
 350 {
 351         u32 temp;
 352
 353         /* Enable DR irq reg */
 354         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 355                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 356                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 357
 358         fsl_writel(temp, &dr_regs->usbintr);
 359
 360         /* Clear stopped bit */
 361         udc->stopped = 0;
 362
 363         /* Set the controller as device mode */
 364         temp = fsl_readl(&dr_regs->usbmode);
 365         temp |= USB_MODE_CTRL_MODE_DEVICE;
 366         fsl_writel(temp, &dr_regs->usbmode);
 367
 368         /* Set controller to Run */
 369         temp = fsl_readl(&dr_regs->usbcmd);
 370         temp |= USB_CMD_RUN_STOP;
 371         fsl_writel(temp, &dr_regs->usbcmd);
 372 }
 373
 374 static void dr_controller_stop(struct fsl_udc *udc)
 375 {
 376         unsigned int tmp;
 377
 378         pr_debug("%s\n", __func__);
 379
 380         /* if we're in OTG mode, and the Host is currently using the port,
 381          * stop now and don't rip the controller out from under the
 382          * ehci driver
 383          */
 384         if (udc->gadget.is_otg) {
 385                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 386                         pr_debug("udc: Leaving early\n");
 387                         return;
 388                 }
 389         }
 390
 391         /* disable all INTR */
 392         fsl_writel(0, &dr_regs->usbintr);
 393
 394         /* Set stopped bit for isr */
 395         udc->stopped = 1;
 396
 397         /* disable IO output */
 398 /*      usb_sys_regs->control = 0; */
 399
 400         /* set controller to Stop */
 401         tmp = fsl_readl(&dr_regs->usbcmd);
 402         tmp &= ~USB_CMD_RUN_STOP;
 403         fsl_writel(tmp, &dr_regs->usbcmd);
 404 }
 405
 406 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 407                         unsigned char ep_type)
 408 {
 409         unsigned int tmp_epctrl = 0;
 410
 411         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 412         if (dir) {
 413                 if (ep_num)
 414                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 415                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 416                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 417                 tmp_epctrl |= ((unsigned int)(ep_type)
 418                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 419         } else {
 420                 if (ep_num)
 421                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 422                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 423                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 424                 tmp_epctrl |= ((unsigned int)(ep_type)
 425                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 426         }
 427
 428         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 429 }
 430
 431 static void
 432 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 433 {
 434         u32 tmp_epctrl = 0;
 435
 436         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 437
 438         if (value) {
 439                 /* set the stall bit */
 440                 if (dir)
 441                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 442                 else
 443                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 444         } else {
 445                 /* clear the stall bit and reset data toggle */
 446                 if (dir) {
 447                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 448                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 449                 } else {
 450                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 451                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 452                 }
 453         }
 454         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 455 }
 456
 457 /* Get stall status of a specific ep
 458    Return: 0: not stalled; 1:stalled */
 459 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 460 {
 461         u32 epctrl;
 462
 463         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 464         if (dir)
 465                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 466         else
 467                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 468 }
 469
 470 /********************************************************************
 471         Internal Structure Build up functions
 472 ********************************************************************/
 473
 474 /*------------------------------------------------------------------
 475 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 476  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 477  * @mult: Mult field
 478  ------------------------------------------------------------------*/
 479 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 480                 unsigned char dir, unsigned char ep_type,
 481                 unsigned int max_pkt_len,
 482                 unsigned int zlt, unsigned char mult)
 483 {
 484         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 485         unsigned int tmp = 0;
 486
 487         /* set the Endpoint Capabilites in QH */
 488         switch (ep_type) {
 489         case USB_ENDPOINT_XFER_CONTROL:
 490                 /* Interrupt On Setup (IOS). for control ep  */
 491                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 492                         | EP_QUEUE_HEAD_IOS;
 493                 break;
 494         case USB_ENDPOINT_XFER_ISOC:
 495                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 496                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 497                 break;
 498         case USB_ENDPOINT_XFER_BULK:
 499         case USB_ENDPOINT_XFER_INT:
 500                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 501                 break;
 502         default:
 503                 VDBG("error ep type is %d", ep_type);
 504                 return;
 505         }
 506         if (zlt)
 507                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 508
 509         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 510         p_QH->next_dtd_ptr = 1;
 511         p_QH->size_ioc_int_sts = 0;
 512 }
 513
 514 /* Setup qh structure and ep register for ep0. */
 515 static void ep0_setup(struct fsl_udc *udc)
 516 {
 517         /* the intialization of an ep includes: fields in QH, Regs,
 518          * fsl_ep struct */
 519         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 520                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 521         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 522                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 523         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 524         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 525
 526         return;
 527
 528 }
 529
 530 /***********************************************************************
 531                 Endpoint Management Functions
 532 ***********************************************************************/
 533
 534 /*-------------------------------------------------------------------------
 535  * when configurations are set, or when interface settings change
 536  * for example the do_set_interface() in gadget layer,
 537  * the driver will enable or disable the relevant endpoints
 538  * ep0 doesn't use this routine. It is always enabled.
 539 -------------------------------------------------------------------------*/
 540 static int fsl_ep_enable(struct usb_ep *_ep,
 541                 const struct usb_endpoint_descriptor *desc)
 542 {
 543         struct fsl_udc *udc = NULL;
 544         struct fsl_ep *ep = NULL;
 545         unsigned short max = 0;
 546         unsigned char mult = 0, zlt;
 547         int retval = -EINVAL;
 548         unsigned long flags = 0;
 549
 550         ep = container_of(_ep, struct fsl_ep, ep);
 551
 552         /* catch various bogus parameters */
 553         if (!_ep || !desc || ep->desc
 554                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 555                 return -EINVAL;
 556
 557         udc = ep->udc;
 558
 559         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 560                 return -ESHUTDOWN;
 561
 562         max = usb_endpoint_maxp(desc);
 563
 564         /* Disable automatic zlp generation.  Driver is responsible to indicate
 565          * explicitly through req->req.zero.  This is needed to enable multi-td
 566          * request. */
 567         zlt = 1;
 568
 569         /* Assume the max packet size from gadget is always correct */
 570         switch (desc->bmAttributes & 0x03) {
 571         case USB_ENDPOINT_XFER_CONTROL:
 572         case USB_ENDPOINT_XFER_BULK:
 573         case USB_ENDPOINT_XFER_INT:
 574                 /* mult = 0.  Execute N Transactions as demonstrated by
 575                  * the USB variable length packet protocol where N is
 576                  * computed using the Maximum Packet Length (dQH) and
 577                  * the Total Bytes field (dTD) */
 578                 mult = 0;
 579                 break;
 580         case USB_ENDPOINT_XFER_ISOC:
 581                 /* Calculate transactions needed for high bandwidth iso */
 582                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 583                 max = max & 0x7ff;      /* bit 0~10 */
 584                 /* 3 transactions at most */
 585                 if (mult > 3)
 586                         goto en_done;
 587                 break;
 588         default:
 589                 goto en_done;
 590         }
 591
 592         spin_lock_irqsave(&udc->lock, flags);
 593         ep->ep.maxpacket = max;
 594         ep->desc = desc;
 595         ep->stopped = 0;
 596
 597         /* Controller related setup */
 598         /* Init EPx Queue Head (Ep Capabilites field in QH
 599          * according to max, zlt, mult) */
 600         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 601                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 602                                         ?  USB_SEND : USB_RECV),
 603                         (unsigned char) (desc->bmAttributes
 604                                         & USB_ENDPOINT_XFERTYPE_MASK),
 605                         max, zlt, mult);
 606
 607         /* Init endpoint ctrl register */
 608         dr_ep_setup((unsigned char) ep_index(ep),
 609                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 610                                         ? USB_SEND : USB_RECV),
 611                         (unsigned char) (desc->bmAttributes
 612                                         & USB_ENDPOINT_XFERTYPE_MASK));
 613
 614         spin_unlock_irqrestore(&udc->lock, flags);
 615         retval = 0;
 616
 617         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 618                         ep->desc->bEndpointAddress & 0x0f,
 619                         (desc->bEndpointAddress & USB_DIR_IN)
 620                                 ? "in" : "out", max);
 621 en_done:
 622         return retval;
 623 }
 624
 625 /*---------------------------------------------------------------------
 626  * @ep : the ep being unconfigured. May not be ep0
 627  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 628 *---------------------------------------------------------------------*/
 629 static int fsl_ep_disable(struct usb_ep *_ep)
 630 {
 631         struct fsl_udc *udc = NULL;
 632         struct fsl_ep *ep = NULL;
 633         unsigned long flags = 0;
 634         u32 epctrl;
 635         int ep_num;
 636
 637         ep = container_of(_ep, struct fsl_ep, ep);
 638         if (!_ep || !ep->desc) {
 639                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 640                 return -EINVAL;
 641         }
 642
 643         /* disable ep on controller */
 644         ep_num = ep_index(ep);
 645         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 646         if (ep_is_in(ep)) {
 647                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 648                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 649         } else {
 650                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 651                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 652         }
 653         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 654
 655         udc = (struct fsl_udc *)ep->udc;
 656         spin_lock_irqsave(&udc->lock, flags);
 657
 658         /* nuke all pending requests (does flush) */
 659         nuke(ep, -ESHUTDOWN);
 660
 661         ep->desc = NULL;
 662         ep->stopped = 1;
 663         spin_unlock_irqrestore(&udc->lock, flags);
 664
 665         VDBG("disabled %s OK", _ep->name);
 666         return 0;
 667 }
 668
 669 /*---------------------------------------------------------------------
 670  * allocate a request object used by this endpoint
 671  * the main operation is to insert the req->queue to the eq->queue
 672  * Returns the request, or null if one could not be allocated
 673 *---------------------------------------------------------------------*/
 674 static struct usb_request *
 675 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 676 {
 677         struct fsl_req *req = NULL;
 678
 679         req = kzalloc(sizeof *req, gfp_flags);
 680         if (!req)
 681                 return NULL;
 682
 683         req->req.dma = DMA_ADDR_INVALID;
 684         INIT_LIST_HEAD(&req->queue);
 685
 686         return &req->req;
 687 }
 688
 689 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 690 {
 691         struct fsl_req *req = NULL;
 692
 693         req = container_of(_req, struct fsl_req, req);
 694
 695         if (_req)
 696                 kfree(req);
 697 }
 698
 699 /* Actually add a dTD chain to an empty dQH and let go */
 700 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
 701 {
 702         struct ep_queue_head *qh = get_qh_by_ep(ep);
 703
 704         /* Write dQH next pointer and terminate bit to 0 */
 705         qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
 706                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
 707
 708         /* Clear active and halt bit */
 709         qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 710                                         | EP_QUEUE_HEAD_STATUS_HALT));
 711
 712         /* Ensure that updates to the QH will occur before priming. */
 713         wmb();
 714
 715         /* Prime endpoint by writing correct bit to ENDPTPRIME */
 716         fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
 717                         : (1 << (ep_index(ep))), &dr_regs->endpointprime);
 718 }
 719
 720 /* Add dTD chain to the dQH of an EP */
 721 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 722 {
 723         u32 temp, bitmask, tmp_stat;
 724
 725         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 726         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 727
 728         bitmask = ep_is_in(ep)
 729                 ? (1 << (ep_index(ep) + 16))
 730                 : (1 << (ep_index(ep)));
 731
 732         /* check if the pipe is empty */
 733         if (!(list_empty(&ep->queue))) {
 734                 /* Add td to the end */
 735                 struct fsl_req *lastreq;
 736                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 737                 lastreq->tail->next_td_ptr =
 738                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 739                 /* Read prime bit, if 1 goto done */
 740                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 741                         return;
 742
 743                 do {
 744                         /* Set ATDTW bit in USBCMD */
 745                         temp = fsl_readl(&dr_regs->usbcmd);
 746                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 747
 748                         /* Read correct status bit */
 749                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 750
 751                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 752
 753                 /* Write ATDTW bit to 0 */
 754                 temp = fsl_readl(&dr_regs->usbcmd);
 755                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 756
 757                 if (tmp_stat)
 758                         return;
 759         }
 760
 761         fsl_prime_ep(ep, req->head);
 762 }
 763
 764 /* Fill in the dTD structure
 765  * @req: request that the transfer belongs to
 766  * @length: return actually data length of the dTD
 767  * @dma: return dma address of the dTD
 768  * @is_last: return flag if it is the last dTD of the request
 769  * return: pointer to the built dTD */
 770 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 771                 dma_addr_t *dma, int *is_last)
 772 {
 773         u32 swap_temp;
 774         struct ep_td_struct *dtd;
 775
 776         /* how big will this transfer be? */
 777         *length = min(req->req.length - req->req.actual,
 778                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 779
 780         dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
 781         if (dtd == NULL)
 782                 return dtd;
 783
 784         dtd->td_dma = *dma;
 785         /* Clear reserved field */
 786         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 787         swap_temp &= ~DTD_RESERVED_FIELDS;
 788         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 789
 790         /* Init all of buffer page pointers */
 791         swap_temp = (u32) (req->req.dma + req->req.actual);
 792         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 793         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 794         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 795         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 796         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 797
 798         req->req.actual += *length;
 799
 800         /* zlp is needed if req->req.zero is set */
 801         if (req->req.zero) {
 802                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 803                         *is_last = 1;
 804                 else
 805                         *is_last = 0;
 806         } else if (req->req.length == req->req.actual)
 807                 *is_last = 1;
 808         else
 809                 *is_last = 0;
 810
 811         if ((*is_last) == 0)
 812                 VDBG("multi-dtd request!");
 813         /* Fill in the transfer size; set active bit */
 814         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 815
 816         /* Enable interrupt for the last dtd of a request */
 817         if (*is_last && !req->req.no_interrupt)
 818                 swap_temp |= DTD_IOC;
 819
 820         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 821
 822         mb();
 823
 824         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 825
 826         return dtd;
 827 }
 828
 829 /* Generate dtd chain for a request */
 830 static int fsl_req_to_dtd(struct fsl_req *req)
 831 {
 832         unsigned        count;
 833         int             is_last;
 834         int             is_first =1;
 835         struct ep_td_struct     *last_dtd = NULL, *dtd;
 836         dma_addr_t dma;
 837
 838         do {
 839                 dtd = fsl_build_dtd(req, &count, &dma, &is_last);
 840                 if (dtd == NULL)
 841                         return -ENOMEM;
 842
 843                 if (is_first) {
 844                         is_first = 0;
 845                         req->head = dtd;
 846                 } else {
 847                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 848                         last_dtd->next_td_virt = dtd;
 849                 }
 850                 last_dtd = dtd;
 851
 852                 req->dtd_count++;
 853         } while (!is_last);
 854
 855         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 856
 857         req->tail = dtd;
 858
 859         return 0;
 860 }
 861
 862 /* queues (submits) an I/O request to an endpoint */
 863 static int
 864 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 865 {
 866         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 867         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 868         struct fsl_udc *udc;
 869         unsigned long flags;
 870
 871         /* catch various bogus parameters */
 872         if (!_req || !req->req.complete || !req->req.buf
 873                         || !list_empty(&req->queue)) {
 874                 VDBG("%s, bad params", __func__);
 875                 return -EINVAL;
 876         }
 877         if (unlikely(!_ep || !ep->desc)) {
 878                 VDBG("%s, bad ep", __func__);
 879                 return -EINVAL;
 880         }
 881         if (usb_endpoint_xfer_isoc(ep->desc)) {
 882                 if (req->req.length > ep->ep.maxpacket)
 883                         return -EMSGSIZE;
 884         }
 885
 886         udc = ep->udc;
 887         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 888                 return -ESHUTDOWN;
 889
 890         req->ep = ep;
 891
 892         /* map virtual address to hardware */
 893         if (req->req.dma == DMA_ADDR_INVALID) {
 894                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 895                                         req->req.buf,
 896                                         req->req.length, ep_is_in(ep)
 897                                                 ? DMA_TO_DEVICE
 898                                                 : DMA_FROM_DEVICE);
 899                 req->mapped = 1;
 900         } else {
 901                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 902                                         req->req.dma, req->req.length,
 903                                         ep_is_in(ep)
 904                                                 ? DMA_TO_DEVICE
 905                                                 : DMA_FROM_DEVICE);
 906                 req->mapped = 0;
 907         }
 908
 909         req->req.status = -EINPROGRESS;
 910         req->req.actual = 0;
 911         req->dtd_count = 0;
 912
 913         spin_lock_irqsave(&udc->lock, flags);
 914
 915         /* build dtds and push them to device queue */
 916         if (!fsl_req_to_dtd(req)) {
 917                 fsl_queue_td(ep, req);
 918         } else {
 919                 spin_unlock_irqrestore(&udc->lock, flags);
 920                 return -ENOMEM;
 921         }
 922
 923         /* Update ep0 state */
 924         if ((ep_index(ep) == 0))
 925                 udc->ep0_state = DATA_STATE_XMIT;
 926
 927         /* irq handler advances the queue */
 928         if (req != NULL)
 929                 list_add_tail(&req->queue, &ep->queue);
 930         spin_unlock_irqrestore(&udc->lock, flags);
 931
 932         return 0;
 933 }
 934
 935 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 936 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 937 {
 938         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 939         struct fsl_req *req;
 940         unsigned long flags;
 941         int ep_num, stopped, ret = 0;
 942         u32 epctrl;
 943
 944         if (!_ep || !_req)
 945                 return -EINVAL;
 946
 947         spin_lock_irqsave(&ep->udc->lock, flags);
 948         stopped = ep->stopped;
 949
 950         /* Stop the ep before we deal with the queue */
 951         ep->stopped = 1;
 952         ep_num = ep_index(ep);
 953         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 954         if (ep_is_in(ep))
 955                 epctrl &= ~EPCTRL_TX_ENABLE;
 956         else
 957                 epctrl &= ~EPCTRL_RX_ENABLE;
 958         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 959
 960         /* make sure it's actually queued on this endpoint */
 961         list_for_each_entry(req, &ep->queue, queue) {
 962                 if (&req->req == _req)
 963                         break;
 964         }
 965         if (&req->req != _req) {
 966                 ret = -EINVAL;
 967                 goto out;
 968         }
 969
 970         /* The request is in progress, or completed but not dequeued */
 971         if (ep->queue.next == &req->queue) {
 972                 _req->status = -ECONNRESET;
 973                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 974
 975                 /* The request isn't the last request in this ep queue */
 976                 if (req->queue.next != &ep->queue) {
 977                         struct fsl_req *next_req;
 978
 979                         next_req = list_entry(req->queue.next, struct fsl_req,
 980                                         queue);
 981
 982                         /* prime with dTD of next request */
 983                         fsl_prime_ep(ep, next_req->head);
 984                 }
 985         /* The request hasn't been processed, patch up the TD chain */
 986         } else {
 987                 struct fsl_req *prev_req;
 988
 989                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 990                 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
 991         }
 992
 993         done(ep, req, -ECONNRESET);
 994
 995         /* Enable EP */
 996 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 997         if (ep_is_in(ep))
 998                 epctrl |= EPCTRL_TX_ENABLE;
 999         else
1000                 epctrl |= EPCTRL_RX_ENABLE;
1001         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1002         ep->stopped = stopped;
1003
1004         spin_unlock_irqrestore(&ep->udc->lock, flags);
1005         return ret;
1006 }
1007
1008 /*-------------------------------------------------------------------------*/
1009
1010 /*-----------------------------------------------------------------
1011  * modify the endpoint halt feature
1012  * @ep: the non-isochronous endpoint being stalled
1013  * @value: 1--set halt  0--clear halt
1014  * Returns zero, or a negative error code.
1015 *----------------------------------------------------------------*/
1016 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1017 {
1018         struct fsl_ep *ep = NULL;
1019         unsigned long flags = 0;
1020         int status = -EOPNOTSUPP;       /* operation not supported */
1021         unsigned char ep_dir = 0, ep_num = 0;
1022         struct fsl_udc *udc = NULL;
1023
1024         ep = container_of(_ep, struct fsl_ep, ep);
1025         udc = ep->udc;
1026         if (!_ep || !ep->desc) {
1027                 status = -EINVAL;
1028                 goto out;
1029         }
1030
1031         if (usb_endpoint_xfer_isoc(ep->desc)) {
1032                 status = -EOPNOTSUPP;
1033                 goto out;
1034         }
1035
1036         /* Attempt to halt IN ep will fail if any transfer requests
1037          * are still queue */
1038         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1039                 status = -EAGAIN;
1040                 goto out;
1041         }
1042
1043         status = 0;
1044         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1045         ep_num = (unsigned char)(ep_index(ep));
1046         spin_lock_irqsave(&ep->udc->lock, flags);
1047         dr_ep_change_stall(ep_num, ep_dir, value);
1048         spin_unlock_irqrestore(&ep->udc->lock, flags);
1049
1050         if (ep_index(ep) == 0) {
1051                 udc->ep0_state = WAIT_FOR_SETUP;
1052                 udc->ep0_dir = 0;
1053         }
1054 out:
1055         VDBG(" %s %s halt stat %d", ep->ep.name,
1056                         value ?  "set" : "clear", status);
1057
1058         return status;
1059 }
1060
1061 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1062 {
1063         struct fsl_ep *ep;
1064         struct fsl_udc *udc;
1065         int size = 0;
1066         u32 bitmask;
1067         struct ep_queue_head *qh;
1068
1069         ep = container_of(_ep, struct fsl_ep, ep);
1070         if (!_ep || (!ep->desc && ep_index(ep) != 0))
1071                 return -ENODEV;
1072
1073         udc = (struct fsl_udc *)ep->udc;
1074
1075         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1076                 return -ESHUTDOWN;
1077
1078         qh = get_qh_by_ep(ep);
1079
1080         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1081             (1 << (ep_index(ep)));
1082
1083         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1084                 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1085                     >> DTD_LENGTH_BIT_POS;
1086
1087         pr_debug("%s %u\n", __func__, size);
1088         return size;
1089 }
1090
1091 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1092 {
1093         struct fsl_ep *ep;
1094         int ep_num, ep_dir;
1095         u32 bits;
1096         unsigned long timeout;
1097 #define FSL_UDC_FLUSH_TIMEOUT 1000
1098
1099         if (!_ep) {
1100                 return;
1101         } else {
1102                 ep = container_of(_ep, struct fsl_ep, ep);
1103                 if (!ep->desc)
1104                         return;
1105         }
1106         ep_num = ep_index(ep);
1107         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1108
1109         if (ep_num == 0)
1110                 bits = (1 << 16) | 1;
1111         else if (ep_dir == USB_SEND)
1112                 bits = 1 << (16 + ep_num);
1113         else
1114                 bits = 1 << ep_num;
1115
1116         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1117         do {
1118                 fsl_writel(bits, &dr_regs->endptflush);
1119
1120                 /* Wait until flush complete */
1121                 while (fsl_readl(&dr_regs->endptflush)) {
1122                         if (time_after(jiffies, timeout)) {
1123                                 ERR("ep flush timeout\n");
1124                                 return;
1125                         }
1126                         cpu_relax();
1127                 }
1128                 /* See if we need to flush again */
1129         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1130 }
1131
1132 static struct usb_ep_ops fsl_ep_ops = {
1133         .enable = fsl_ep_enable,
1134         .disable = fsl_ep_disable,
1135
1136         .alloc_request = fsl_alloc_request,
1137         .free_request = fsl_free_request,
1138
1139         .queue = fsl_ep_queue,
1140         .dequeue = fsl_ep_dequeue,
1141
1142         .set_halt = fsl_ep_set_halt,
1143         .fifo_status = fsl_ep_fifo_status,
1144         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1145 };
1146
1147 /*-------------------------------------------------------------------------
1148                 Gadget Driver Layer Operations
1149 -------------------------------------------------------------------------*/
1150
1151 /*----------------------------------------------------------------------
1152  * Get the current frame number (from DR frame_index Reg )
1153  *----------------------------------------------------------------------*/
1154 static int fsl_get_frame(struct usb_gadget *gadget)
1155 {
1156         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1157 }
1158
1159 /*-----------------------------------------------------------------------
1160  * Tries to wake up the host connected to this gadget
1161  -----------------------------------------------------------------------*/
1162 static int fsl_wakeup(struct usb_gadget *gadget)
1163 {
1164         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1165         u32 portsc;
1166
1167         /* Remote wakeup feature not enabled by host */
1168         if (!udc->remote_wakeup)
1169                 return -ENOTSUPP;
1170
1171         portsc = fsl_readl(&dr_regs->portsc1);
1172         /* not suspended? */
1173         if (!(portsc & PORTSCX_PORT_SUSPEND))
1174                 return 0;
1175         /* trigger force resume */
1176         portsc |= PORTSCX_PORT_FORCE_RESUME;
1177         fsl_writel(portsc, &dr_regs->portsc1);
1178         return 0;
1179 }
1180
1181 static int can_pullup(struct fsl_udc *udc)
1182 {
1183         return udc->driver && udc->softconnect && udc->vbus_active;
1184 }
1185
1186 /* Notify controller that VBUS is powered, Called by whatever
1187    detects VBUS sessions */
1188 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1189 {
1190         struct fsl_udc  *udc;
1191         unsigned long   flags;
1192
1193         udc = container_of(gadget, struct fsl_udc, gadget);
1194         spin_lock_irqsave(&udc->lock, flags);
1195         VDBG("VBUS %s", is_active ? "on" : "off");
1196         udc->vbus_active = (is_active != 0);
1197         if (can_pullup(udc))
1198                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1199                                 &dr_regs->usbcmd);
1200         else
1201                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1202                                 &dr_regs->usbcmd);
1203         spin_unlock_irqrestore(&udc->lock, flags);
1204         return 0;
1205 }
1206
1207 /* constrain controller's VBUS power usage
1208  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1209  * reporting how much power the device may consume.  For example, this
1210  * could affect how quickly batteries are recharged.
1211  *
1212  * Returns zero on success, else negative errno.
1213  */
1214 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1215 {
1216         struct fsl_udc *udc;
1217
1218         udc = container_of(gadget, struct fsl_udc, gadget);
1219         if (udc->transceiver)
1220                 return otg_set_power(udc->transceiver, mA);
1221         return -ENOTSUPP;
1222 }
1223
1224 /* Change Data+ pullup status
1225  * this func is used by usb_gadget_connect/disconnet
1226  */
1227 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1228 {
1229         struct fsl_udc *udc;
1230
1231         udc = container_of(gadget, struct fsl_udc, gadget);
1232         udc->softconnect = (is_on != 0);
1233         if (can_pullup(udc))
1234                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1235                                 &dr_regs->usbcmd);
1236         else
1237                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1238                                 &dr_regs->usbcmd);
1239
1240         return 0;
1241 }
1242
1243 static int fsl_start(struct usb_gadget_driver *driver,
1244                 int (*bind)(struct usb_gadget *));
1245 static int fsl_stop(struct usb_gadget_driver *driver);
1246 /* defined in gadget.h */
1247 static struct usb_gadget_ops fsl_gadget_ops = {
1248         .get_frame = fsl_get_frame,
1249         .wakeup = fsl_wakeup,
1250 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1251         .vbus_session = fsl_vbus_session,
1252         .vbus_draw = fsl_vbus_draw,
1253         .pullup = fsl_pullup,
1254         .start = fsl_start,
1255         .stop = fsl_stop,
1256 };
1257
1258 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1259    on new transaction */
1260 static void ep0stall(struct fsl_udc *udc)
1261 {
1262         u32 tmp;
1263
1264         /* must set tx and rx to stall at the same time */
1265         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1266         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1267         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1268         udc->ep0_state = WAIT_FOR_SETUP;
1269         udc->ep0_dir = 0;
1270 }
1271
1272 /* Prime a status phase for ep0 */
1273 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1274 {
1275         struct fsl_req *req = udc->status_req;
1276         struct fsl_ep *ep;
1277
1278         if (direction == EP_DIR_IN)
1279                 udc->ep0_dir = USB_DIR_IN;
1280         else
1281                 udc->ep0_dir = USB_DIR_OUT;
1282
1283         ep = &udc->eps[0];
1284         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1285
1286         req->ep = ep;
1287         req->req.length = 0;
1288         req->req.status = -EINPROGRESS;
1289         req->req.actual = 0;
1290         req->req.complete = NULL;
1291         req->dtd_count = 0;
1292
1293         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1294                         req->req.buf, req->req.length,
1295                         ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1296         req->mapped = 1;
1297
1298         if (fsl_req_to_dtd(req) == 0)
1299                 fsl_queue_td(ep, req);
1300         else
1301                 return -ENOMEM;
1302
1303         list_add_tail(&req->queue, &ep->queue);
1304
1305         return 0;
1306 }
1307
1308 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1309 {
1310         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1311
1312         if (ep->name)
1313                 nuke(ep, -ESHUTDOWN);
1314 }
1315
1316 /*
1317  * ch9 Set address
1318  */
1319 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1320 {
1321         /* Save the new address to device struct */
1322         udc->device_address = (u8) value;
1323         /* Update usb state */
1324         udc->usb_state = USB_STATE_ADDRESS;
1325         /* Status phase */
1326         if (ep0_prime_status(udc, EP_DIR_IN))
1327                 ep0stall(udc);
1328 }
1329
1330 /*
1331  * ch9 Get status
1332  */
1333 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1334                 u16 index, u16 length)
1335 {
1336         u16 tmp = 0;            /* Status, cpu endian */
1337         struct fsl_req *req;
1338         struct fsl_ep *ep;
1339
1340         ep = &udc->eps[0];
1341
1342         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1343                 /* Get device status */
1344                 tmp = 1 << USB_DEVICE_SELF_POWERED;
1345                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1346         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1347                 /* Get interface status */
1348                 /* We don't have interface information in udc driver */
1349                 tmp = 0;
1350         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1351                 /* Get endpoint status */
1352                 struct fsl_ep *target_ep;
1353
1354                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1355
1356                 /* stall if endpoint doesn't exist */
1357                 if (!target_ep->desc)
1358                         goto stall;
1359                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1360                                 << USB_ENDPOINT_HALT;
1361         }
1362
1363         udc->ep0_dir = USB_DIR_IN;
1364         /* Borrow the per device status_req */
1365         req = udc->status_req;
1366         /* Fill in the reqest structure */
1367         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1368
1369         req->ep = ep;
1370         req->req.length = 2;
1371         req->req.status = -EINPROGRESS;
1372         req->req.actual = 0;
1373         req->req.complete = NULL;
1374         req->dtd_count = 0;
1375
1376         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1377                                 req->req.buf, req->req.length,
1378                                 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1379         req->mapped = 1;
1380
1381         /* prime the data phase */
1382         if ((fsl_req_to_dtd(req) == 0))
1383                 fsl_queue_td(ep, req);
1384         else                    /* no mem */
1385                 goto stall;
1386
1387         list_add_tail(&req->queue, &ep->queue);
1388         udc->ep0_state = DATA_STATE_XMIT;
1389         return;
1390 stall:
1391         ep0stall(udc);
1392 }
1393
1394 static void setup_received_irq(struct fsl_udc *udc,
1395                 struct usb_ctrlrequest *setup)
1396 {
1397         u16 wValue = le16_to_cpu(setup->wValue);
1398         u16 wIndex = le16_to_cpu(setup->wIndex);
1399         u16 wLength = le16_to_cpu(setup->wLength);
1400
1401         udc_reset_ep_queue(udc, 0);
1402
1403         /* We process some stardard setup requests here */
1404         switch (setup->bRequest) {
1405         case USB_REQ_GET_STATUS:
1406                 /* Data+Status phase from udc */
1407                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1408                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1409                         break;
1410                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1411                 return;
1412
1413         case USB_REQ_SET_ADDRESS:
1414                 /* Status phase from udc */
1415                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1416                                                 | USB_RECIP_DEVICE))
1417                         break;
1418                 ch9setaddress(udc, wValue, wIndex, wLength);
1419                 return;
1420
1421         case USB_REQ_CLEAR_FEATURE:
1422         case USB_REQ_SET_FEATURE:
1423                 /* Status phase from udc */
1424         {
1425                 int rc = -EOPNOTSUPP;
1426                 u16 ptc = 0;
1427
1428                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1429                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1430                         int pipe = get_pipe_by_windex(wIndex);
1431                         struct fsl_ep *ep;
1432
1433                         if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1434                                 break;
1435                         ep = get_ep_by_pipe(udc, pipe);
1436
1437                         spin_unlock(&udc->lock);
1438                         rc = fsl_ep_set_halt(&ep->ep,
1439                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1440                                                 ? 1 : 0);
1441                         spin_lock(&udc->lock);
1442
1443                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1444                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1445                                 | USB_TYPE_STANDARD)) {
1446                         /* Note: The driver has not include OTG support yet.
1447                          * This will be set when OTG support is added */
1448                         if (wValue == USB_DEVICE_TEST_MODE)
1449                                 ptc = wIndex >> 8;
1450                         else if (gadget_is_otg(&udc->gadget)) {
1451                                 if (setup->bRequest ==
1452                                     USB_DEVICE_B_HNP_ENABLE)
1453                                         udc->gadget.b_hnp_enable = 1;
1454                                 else if (setup->bRequest ==
1455                                          USB_DEVICE_A_HNP_SUPPORT)
1456                                         udc->gadget.a_hnp_support = 1;
1457                                 else if (setup->bRequest ==
1458                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1459                                         udc->gadget.a_alt_hnp_support = 1;
1460                         }
1461                         rc = 0;
1462                 } else
1463                         break;
1464
1465                 if (rc == 0) {
1466                         if (ep0_prime_status(udc, EP_DIR_IN))
1467                                 ep0stall(udc);
1468                 }
1469                 if (ptc) {
1470                         u32 tmp;
1471
1472                         mdelay(10);
1473                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1474                         fsl_writel(tmp, &dr_regs->portsc1);
1475                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1476                 }
1477
1478                 return;
1479         }
1480
1481         default:
1482                 break;
1483         }
1484
1485         /* Requests handled by gadget */
1486         if (wLength) {
1487                 /* Data phase from gadget, status phase from udc */
1488                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1489                                 ?  USB_DIR_IN : USB_DIR_OUT;
1490                 spin_unlock(&udc->lock);
1491                 if (udc->driver->setup(&udc->gadget,
1492                                 &udc->local_setup_buff) < 0)
1493                         ep0stall(udc);
1494                 spin_lock(&udc->lock);
1495                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1496                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1497         } else {
1498                 /* No data phase, IN status from gadget */
1499                 udc->ep0_dir = USB_DIR_IN;
1500                 spin_unlock(&udc->lock);
1501                 if (udc->driver->setup(&udc->gadget,
1502                                 &udc->local_setup_buff) < 0)
1503                         ep0stall(udc);
1504                 spin_lock(&udc->lock);
1505                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1506         }
1507 }
1508
1509 /* Process request for Data or Status phase of ep0
1510  * prime status phase if needed */
1511 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1512                 struct fsl_req *req)
1513 {
1514         if (udc->usb_state == USB_STATE_ADDRESS) {
1515                 /* Set the new address */
1516                 u32 new_address = (u32) udc->device_address;
1517                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1518                                 &dr_regs->deviceaddr);
1519         }
1520
1521         done(ep0, req, 0);
1522
1523         switch (udc->ep0_state) {
1524         case DATA_STATE_XMIT:
1525                 /* receive status phase */
1526                 if (ep0_prime_status(udc, EP_DIR_OUT))
1527                         ep0stall(udc);
1528                 break;
1529         case DATA_STATE_RECV:
1530                 /* send status phase */
1531                 if (ep0_prime_status(udc, EP_DIR_IN))
1532                         ep0stall(udc);
1533                 break;
1534         case WAIT_FOR_OUT_STATUS:
1535                 udc->ep0_state = WAIT_FOR_SETUP;
1536                 break;
1537         case WAIT_FOR_SETUP:
1538                 ERR("Unexpect ep0 packets\n");
1539                 break;
1540         default:
1541                 ep0stall(udc);
1542                 break;
1543         }
1544 }
1545
1546 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1547  * being corrupted by another incoming setup packet */
1548 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1549 {
1550         u32 temp;
1551         struct ep_queue_head *qh;
1552         struct fsl_usb2_platform_data *pdata = udc->pdata;
1553
1554         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1555
1556         /* Clear bit in ENDPTSETUPSTAT */
1557         temp = fsl_readl(&dr_regs->endptsetupstat);
1558         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1559
1560         /* while a hazard exists when setup package arrives */
1561         do {
1562                 /* Set Setup Tripwire */
1563                 temp = fsl_readl(&dr_regs->usbcmd);
1564                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1565
1566                 /* Copy the setup packet to local buffer */
1567                 if (pdata->le_setup_buf) {
1568                         u32 *p = (u32 *)buffer_ptr;
1569                         u32 *s = (u32 *)qh->setup_buffer;
1570
1571                         /* Convert little endian setup buffer to CPU endian */
1572                         *p++ = le32_to_cpu(*s++);
1573                         *p = le32_to_cpu(*s);
1574                 } else {
1575                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1576                 }
1577         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1578
1579         /* Clear Setup Tripwire */
1580         temp = fsl_readl(&dr_regs->usbcmd);
1581         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1582 }
1583
1584 /* process-ep_req(): free the completed Tds for this req */
1585 static int process_ep_req(struct fsl_udc *udc, int pipe,
1586                 struct fsl_req *curr_req)
1587 {
1588         struct ep_td_struct *curr_td;
1589         int     td_complete, actual, remaining_length, j, tmp;
1590         int     status = 0;
1591         int     errors = 0;
1592         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1593         int direction = pipe % 2;
1594
1595         curr_td = curr_req->head;
1596         td_complete = 0;
1597         actual = curr_req->req.length;
1598
1599         for (j = 0; j < curr_req->dtd_count; j++) {
1600                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1601                                         & DTD_PACKET_SIZE)
1602                                 >> DTD_LENGTH_BIT_POS;
1603                 actual -= remaining_length;
1604
1605                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1606                 if (errors & DTD_ERROR_MASK) {
1607                         if (errors & DTD_STATUS_HALTED) {
1608                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1609                                 /* Clear the errors and Halt condition */
1610                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1611                                 tmp &= ~errors;
1612                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1613                                 status = -EPIPE;
1614                                 /* FIXME: continue with next queued TD? */
1615
1616                                 break;
1617                         }
1618                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1619                                 VDBG("Transfer overflow");
1620                                 status = -EPROTO;
1621                                 break;
1622                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1623                                 VDBG("ISO error");
1624                                 status = -EILSEQ;
1625                                 break;
1626                         } else
1627                                 ERR("Unknown error has occurred (0x%x)!\n",
1628                                         errors);
1629
1630                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1631                                 & DTD_STATUS_ACTIVE) {
1632                         VDBG("Request not complete");
1633                         status = REQ_UNCOMPLETE;
1634                         return status;
1635                 } else if (remaining_length) {
1636                         if (direction) {
1637                                 VDBG("Transmit dTD remaining length not zero");
1638                                 status = -EPROTO;
1639                                 break;
1640                         } else {
1641                                 td_complete++;
1642                                 break;
1643                         }
1644                 } else {
1645                         td_complete++;
1646                         VDBG("dTD transmitted successful");
1647                 }
1648
1649                 if (j != curr_req->dtd_count - 1)
1650                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1651         }
1652
1653         if (status)
1654                 return status;
1655
1656         curr_req->req.actual = actual;
1657
1658         return 0;
1659 }
1660
1661 /* Process a DTD completion interrupt */
1662 static void dtd_complete_irq(struct fsl_udc *udc)
1663 {
1664         u32 bit_pos;
1665         int i, ep_num, direction, bit_mask, status;
1666         struct fsl_ep *curr_ep;
1667         struct fsl_req *curr_req, *temp_req;
1668
1669         /* Clear the bits in the register */
1670         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1671         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1672
1673         if (!bit_pos)
1674                 return;
1675
1676         for (i = 0; i < udc->max_ep * 2; i++) {
1677                 ep_num = i >> 1;
1678                 direction = i % 2;
1679
1680                 bit_mask = 1 << (ep_num + 16 * direction);
1681
1682                 if (!(bit_pos & bit_mask))
1683                         continue;
1684
1685                 curr_ep = get_ep_by_pipe(udc, i);
1686
1687                 /* If the ep is configured */
1688                 if (curr_ep->name == NULL) {
1689                         WARNING("Invalid EP?");
1690                         continue;
1691                 }
1692
1693                 /* process the req queue until an uncomplete request */
1694                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1695                                 queue) {
1696                         status = process_ep_req(udc, i, curr_req);
1697
1698                         VDBG("status of process_ep_req= %d, ep = %d",
1699                                         status, ep_num);
1700                         if (status == REQ_UNCOMPLETE)
1701                                 break;
1702                         /* write back status to req */
1703                         curr_req->req.status = status;
1704
1705                         if (ep_num == 0) {
1706                                 ep0_req_complete(udc, curr_ep, curr_req);
1707                                 break;
1708                         } else
1709                                 done(curr_ep, curr_req, status);
1710                 }
1711         }
1712 }
1713
1714 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1715 {
1716         switch (reg & PORTSCX_PORT_SPEED_MASK) {
1717         case PORTSCX_PORT_SPEED_HIGH:
1718                 return USB_SPEED_HIGH;
1719         case PORTSCX_PORT_SPEED_FULL:
1720                 return USB_SPEED_FULL;
1721         case PORTSCX_PORT_SPEED_LOW:
1722                 return USB_SPEED_LOW;
1723         default:
1724                 return USB_SPEED_UNKNOWN;
1725         }
1726 }
1727
1728 /* Process a port change interrupt */
1729 static void port_change_irq(struct fsl_udc *udc)
1730 {
1731         if (udc->bus_reset)
1732                 udc->bus_reset = 0;
1733
1734         /* Bus resetting is finished */
1735         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1736                 /* Get the speed */
1737                 udc->gadget.speed =
1738                         portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1739
1740         /* Update USB state */
1741         if (!udc->resume_state)
1742                 udc->usb_state = USB_STATE_DEFAULT;
1743 }
1744
1745 /* Process suspend interrupt */
1746 static void suspend_irq(struct fsl_udc *udc)
1747 {
1748         udc->resume_state = udc->usb_state;
1749         udc->usb_state = USB_STATE_SUSPENDED;
1750
1751         /* report suspend to the driver, serial.c does not support this */
1752         if (udc->driver->suspend)
1753                 udc->driver->suspend(&udc->gadget);
1754 }
1755
1756 static void bus_resume(struct fsl_udc *udc)
1757 {
1758         udc->usb_state = udc->resume_state;
1759         udc->resume_state = 0;
1760
1761         /* report resume to the driver, serial.c does not support this */
1762         if (udc->driver->resume)
1763                 udc->driver->resume(&udc->gadget);
1764 }
1765
1766 /* Clear up all ep queues */
1767 static int reset_queues(struct fsl_udc *udc)
1768 {
1769         u8 pipe;
1770
1771         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1772                 udc_reset_ep_queue(udc, pipe);
1773
1774         /* report disconnect; the driver is already quiesced */
1775         spin_unlock(&udc->lock);
1776         udc->driver->disconnect(&udc->gadget);
1777         spin_lock(&udc->lock);
1778
1779         return 0;
1780 }
1781
1782 /* Process reset interrupt */
1783 static void reset_irq(struct fsl_udc *udc)
1784 {
1785         u32 temp;
1786         unsigned long timeout;
1787
1788         /* Clear the device address */
1789         temp = fsl_readl(&dr_regs->deviceaddr);
1790         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1791
1792         udc->device_address = 0;
1793
1794         /* Clear usb state */
1795         udc->resume_state = 0;
1796         udc->ep0_dir = 0;
1797         udc->ep0_state = WAIT_FOR_SETUP;
1798         udc->remote_wakeup = 0; /* default to 0 on reset */
1799         udc->gadget.b_hnp_enable = 0;
1800         udc->gadget.a_hnp_support = 0;
1801         udc->gadget.a_alt_hnp_support = 0;
1802
1803         /* Clear all the setup token semaphores */
1804         temp = fsl_readl(&dr_regs->endptsetupstat);
1805         fsl_writel(temp, &dr_regs->endptsetupstat);
1806
1807         /* Clear all the endpoint complete status bits */
1808         temp = fsl_readl(&dr_regs->endptcomplete);
1809         fsl_writel(temp, &dr_regs->endptcomplete);
1810
1811         timeout = jiffies + 100;
1812         while (fsl_readl(&dr_regs->endpointprime)) {
1813                 /* Wait until all endptprime bits cleared */
1814                 if (time_after(jiffies, timeout)) {
1815                         ERR("Timeout for reset\n");
1816                         break;
1817                 }
1818                 cpu_relax();
1819         }
1820
1821         /* Write 1s to the flush register */
1822         fsl_writel(0xffffffff, &dr_regs->endptflush);
1823
1824         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1825                 VDBG("Bus reset");
1826                 /* Bus is reseting */
1827                 udc->bus_reset = 1;
1828                 /* Reset all the queues, include XD, dTD, EP queue
1829                  * head and TR Queue */
1830                 reset_queues(udc);
1831                 udc->usb_state = USB_STATE_DEFAULT;
1832         } else {
1833                 VDBG("Controller reset");
1834                 /* initialize usb hw reg except for regs for EP, not
1835                  * touch usbintr reg */
1836                 dr_controller_setup(udc);
1837
1838                 /* Reset all internal used Queues */
1839                 reset_queues(udc);
1840
1841                 ep0_setup(udc);
1842
1843                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1844                 dr_controller_run(udc);
1845                 udc->usb_state = USB_STATE_ATTACHED;
1846         }
1847 }
1848
1849 /*
1850  * USB device controller interrupt handler
1851  */
1852 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1853 {
1854         struct fsl_udc *udc = _udc;
1855         u32 irq_src;
1856         irqreturn_t status = IRQ_NONE;
1857         unsigned long flags;
1858
1859         /* Disable ISR for OTG host mode */
1860         if (udc->stopped)
1861                 return IRQ_NONE;
1862         spin_lock_irqsave(&udc->lock, flags);
1863         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1864         /* Clear notification bits */
1865         fsl_writel(irq_src, &dr_regs->usbsts);
1866
1867         /* VDBG("irq_src [0x%8x]", irq_src); */
1868
1869         /* Need to resume? */
1870         if (udc->usb_state == USB_STATE_SUSPENDED)
1871                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1872                         bus_resume(udc);
1873
1874         /* USB Interrupt */
1875         if (irq_src & USB_STS_INT) {
1876                 VDBG("Packet int");
1877                 /* Setup package, we only support ep0 as control ep */
1878                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1879                         tripwire_handler(udc, 0,
1880                                         (u8 *) (&udc->local_setup_buff));
1881                         setup_received_irq(udc, &udc->local_setup_buff);
1882                         status = IRQ_HANDLED;
1883                 }
1884
1885                 /* completion of dtd */
1886                 if (fsl_readl(&dr_regs->endptcomplete)) {
1887                         dtd_complete_irq(udc);
1888                         status = IRQ_HANDLED;
1889                 }
1890         }
1891
1892         /* SOF (for ISO transfer) */
1893         if (irq_src & USB_STS_SOF) {
1894                 status = IRQ_HANDLED;
1895         }
1896
1897         /* Port Change */
1898         if (irq_src & USB_STS_PORT_CHANGE) {
1899                 port_change_irq(udc);
1900                 status = IRQ_HANDLED;
1901         }
1902
1903         /* Reset Received */
1904         if (irq_src & USB_STS_RESET) {
1905                 VDBG("reset int");
1906                 reset_irq(udc);
1907                 status = IRQ_HANDLED;
1908         }
1909
1910         /* Sleep Enable (Suspend) */
1911         if (irq_src & USB_STS_SUSPEND) {
1912                 suspend_irq(udc);
1913                 status = IRQ_HANDLED;
1914         }
1915
1916         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1917                 VDBG("Error IRQ %x", irq_src);
1918         }
1919
1920         spin_unlock_irqrestore(&udc->lock, flags);
1921         return status;
1922 }
1923
1924 /*----------------------------------------------------------------*
1925  * Hook to gadget drivers
1926  * Called by initialization code of gadget drivers
1927 *----------------------------------------------------------------*/
1928 static int fsl_start(struct usb_gadget_driver *driver,
1929                 int (*bind)(struct usb_gadget *))
1930 {
1931         int retval = -ENODEV;
1932         unsigned long flags = 0;
1933
1934         if (!udc_controller)
1935                 return -ENODEV;
1936
1937         if (!driver || driver->speed < USB_SPEED_FULL
1938                         || !bind || !driver->disconnect || !driver->setup)
1939                 return -EINVAL;
1940
1941         if (udc_controller->driver)
1942                 return -EBUSY;
1943
1944         /* lock is needed but whether should use this lock or another */
1945         spin_lock_irqsave(&udc_controller->lock, flags);
1946
1947         driver->driver.bus = NULL;
1948         /* hook up the driver */
1949         udc_controller->driver = driver;
1950         udc_controller->gadget.dev.driver = &driver->driver;
1951         spin_unlock_irqrestore(&udc_controller->lock, flags);
1952
1953         /* bind udc driver to gadget driver */
1954         retval = bind(&udc_controller->gadget);
1955         if (retval) {
1956                 VDBG("bind to %s --> %d", driver->driver.name, retval);
1957                 udc_controller->gadget.dev.driver = NULL;
1958                 udc_controller->driver = NULL;
1959                 goto out;
1960         }
1961
1962         if (udc_controller->transceiver) {
1963                 /* Suspend the controller until OTG enable it */
1964                 udc_controller->stopped = 1;
1965                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1966
1967                 /* connect to bus through transceiver */
1968                 if (udc_controller->transceiver) {
1969                         retval = otg_set_peripheral(udc_controller->transceiver,
1970                                                     &udc_controller->gadget);
1971                         if (retval < 0) {
1972                                 ERR("can't bind to transceiver\n");
1973                                 driver->unbind(&udc_controller->gadget);
1974                                 udc_controller->gadget.dev.driver = 0;
1975                                 udc_controller->driver = 0;
1976                                 return retval;
1977                         }
1978                 }
1979         } else {
1980                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1981                 dr_controller_run(udc_controller);
1982                 udc_controller->usb_state = USB_STATE_ATTACHED;
1983                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1984                 udc_controller->ep0_dir = 0;
1985         }
1986         printk(KERN_INFO "%s: bind to driver %s\n",
1987                         udc_controller->gadget.name, driver->driver.name);
1988
1989 out:
1990         if (retval)
1991                 printk(KERN_WARNING "gadget driver register failed %d\n",
1992                        retval);
1993         return retval;
1994 }
1995
1996 /* Disconnect from gadget driver */
1997 static int fsl_stop(struct usb_gadget_driver *driver)
1998 {
1999         struct fsl_ep *loop_ep;
2000         unsigned long flags;
2001
2002         if (!udc_controller)
2003                 return -ENODEV;
2004
2005         if (!driver || driver != udc_controller->driver || !driver->unbind)
2006                 return -EINVAL;
2007
2008         if (udc_controller->transceiver)
2009                 otg_set_peripheral(udc_controller->transceiver, NULL);
2010
2011         /* stop DR, disable intr */
2012         dr_controller_stop(udc_controller);
2013
2014         /* in fact, no needed */
2015         udc_controller->usb_state = USB_STATE_ATTACHED;
2016         udc_controller->ep0_state = WAIT_FOR_SETUP;
2017         udc_controller->ep0_dir = 0;
2018
2019         /* stand operation */
2020         spin_lock_irqsave(&udc_controller->lock, flags);
2021         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2022         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2023         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2024                         ep.ep_list)
2025                 nuke(loop_ep, -ESHUTDOWN);
2026         spin_unlock_irqrestore(&udc_controller->lock, flags);
2027
2028         /* report disconnect; the controller is already quiesced */
2029         driver->disconnect(&udc_controller->gadget);
2030
2031         /* unbind gadget and unhook driver. */
2032         driver->unbind(&udc_controller->gadget);
2033         udc_controller->gadget.dev.driver = NULL;
2034         udc_controller->driver = NULL;
2035
2036         printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2037                driver->driver.name);
2038         return 0;
2039 }
2040
2041 /*-------------------------------------------------------------------------
2042                 PROC File System Support
2043 -------------------------------------------------------------------------*/
2044 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2045
2046 #include <linux/seq_file.h>
2047
2048 static const char proc_filename[] = "driver/fsl_usb2_udc";
2049
2050 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2051                 int *eof, void *_dev)
2052 {
2053         char *buf = page;
2054         char *next = buf;
2055         unsigned size = count;
2056         unsigned long flags;
2057         int t, i;
2058         u32 tmp_reg;
2059         struct fsl_ep *ep = NULL;
2060         struct fsl_req *req;
2061
2062         struct fsl_udc *udc = udc_controller;
2063         if (off != 0)
2064                 return 0;
2065
2066         spin_lock_irqsave(&udc->lock, flags);
2067
2068         /* ------basic driver information ---- */
2069         t = scnprintf(next, size,
2070                         DRIVER_DESC "\n"
2071                         "%s version: %s\n"
2072                         "Gadget driver: %s\n\n",
2073                         driver_name, DRIVER_VERSION,
2074                         udc->driver ? udc->driver->driver.name : "(none)");
2075         size -= t;
2076         next += t;
2077
2078         /* ------ DR Registers ----- */
2079         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2080         t = scnprintf(next, size,
2081                         "USBCMD reg:\n"
2082                         "SetupTW: %d\n"
2083                         "Run/Stop: %s\n\n",
2084                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2085                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2086         size -= t;
2087         next += t;
2088
2089         tmp_reg = fsl_readl(&dr_regs->usbsts);
2090         t = scnprintf(next, size,
2091                         "USB Status Reg:\n"
2092                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2093                         "USB Error Interrupt: %s\n\n",
2094                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2095                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2096                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2097                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2098         size -= t;
2099         next += t;
2100
2101         tmp_reg = fsl_readl(&dr_regs->usbintr);
2102         t = scnprintf(next, size,
2103                         "USB Intrrupt Enable Reg:\n"
2104                         "Sleep Enable: %d SOF Received Enable: %d "
2105                         "Reset Enable: %d\n"
2106                         "System Error Enable: %d "
2107                         "Port Change Dectected Enable: %d\n"
2108                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2109                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2110                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2111                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2112                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2113                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2114                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2115                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2116         size -= t;
2117         next += t;
2118
2119         tmp_reg = fsl_readl(&dr_regs->frindex);
2120         t = scnprintf(next, size,
2121                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2122                         (tmp_reg & USB_FRINDEX_MASKS));
2123         size -= t;
2124         next += t;
2125
2126         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2127         t = scnprintf(next, size,
2128                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2129                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2130         size -= t;
2131         next += t;
2132
2133         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2134         t = scnprintf(next, size,
2135                         "USB Endpoint List Address Reg: "
2136                         "Device Addr is 0x%x\n\n",
2137                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2138         size -= t;
2139         next += t;
2140
2141         tmp_reg = fsl_readl(&dr_regs->portsc1);
2142         t = scnprintf(next, size,
2143                 "USB Port Status&Control Reg:\n"
2144                 "Port Transceiver Type : %s Port Speed: %s\n"
2145                 "PHY Low Power Suspend: %s Port Reset: %s "
2146                 "Port Suspend Mode: %s\n"
2147                 "Over-current Change: %s "
2148                 "Port Enable/Disable Change: %s\n"
2149                 "Port Enabled/Disabled: %s "
2150                 "Current Connect Status: %s\n\n", ( {
2151                         char *s;
2152                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2153                         case PORTSCX_PTS_UTMI:
2154                                 s = "UTMI"; break;
2155                         case PORTSCX_PTS_ULPI:
2156                                 s = "ULPI "; break;
2157                         case PORTSCX_PTS_FSLS:
2158                                 s = "FS/LS Serial"; break;
2159                         default:
2160                                 s = "None"; break;
2161                         }
2162                         s;} ),
2163                 usb_speed_string(portscx_device_speed(tmp_reg)),
2164                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2165                 "Normal PHY mode" : "Low power mode",
2166                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2167                 "Not in Reset",
2168                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2169                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2170                 "No",
2171                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2172                 "Not change",
2173                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2174                 "Not correct",
2175                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2176                 "Attached" : "Not-Att");
2177         size -= t;
2178         next += t;
2179
2180         tmp_reg = fsl_readl(&dr_regs->usbmode);
2181         t = scnprintf(next, size,
2182                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2183                                 char *s;
2184                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2185                                 case USB_MODE_CTRL_MODE_IDLE:
2186                                         s = "Idle"; break;
2187                                 case USB_MODE_CTRL_MODE_DEVICE:
2188                                         s = "Device Controller"; break;
2189                                 case USB_MODE_CTRL_MODE_HOST:
2190                                         s = "Host Controller"; break;
2191                                 default:
2192                                         s = "None"; break;
2193                                 }
2194                                 s;
2195                         } ));
2196         size -= t;
2197         next += t;
2198
2199         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2200         t = scnprintf(next, size,
2201                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2202                         (tmp_reg & EP_SETUP_STATUS_MASK));
2203         size -= t;
2204         next += t;
2205
2206         for (i = 0; i < udc->max_ep / 2; i++) {
2207                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2208                 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2209                                 i, tmp_reg);
2210                 size -= t;
2211                 next += t;
2212         }
2213         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2214         t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2215         size -= t;
2216         next += t;
2217
2218 #ifndef CONFIG_ARCH_MXC
2219         if (udc->pdata->have_sysif_regs) {
2220                 tmp_reg = usb_sys_regs->snoop1;
2221                 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2222                 size -= t;
2223                 next += t;
2224
2225                 tmp_reg = usb_sys_regs->control;
2226                 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2227                                 tmp_reg);
2228                 size -= t;
2229                 next += t;
2230         }
2231 #endif
2232
2233         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2234         ep = &udc->eps[0];
2235         t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2236                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2237         size -= t;
2238         next += t;
2239
2240         if (list_empty(&ep->queue)) {
2241                 t = scnprintf(next, size, "its req queue is empty\n\n");
2242                 size -= t;
2243                 next += t;
2244         } else {
2245                 list_for_each_entry(req, &ep->queue, queue) {
2246                         t = scnprintf(next, size,
2247                                 "req %p actual 0x%x length 0x%x buf %p\n",
2248                                 &req->req, req->req.actual,
2249                                 req->req.length, req->req.buf);
2250                         size -= t;
2251                         next += t;
2252                 }
2253         }
2254         /* other gadget->eplist ep */
2255         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2256                 if (ep->desc) {
2257                         t = scnprintf(next, size,
2258                                         "\nFor %s Maxpkt is 0x%x "
2259                                         "index is 0x%x\n",
2260                                         ep->ep.name, ep_maxpacket(ep),
2261                                         ep_index(ep));
2262                         size -= t;
2263                         next += t;
2264
2265                         if (list_empty(&ep->queue)) {
2266                                 t = scnprintf(next, size,
2267                                                 "its req queue is empty\n\n");
2268                                 size -= t;
2269                                 next += t;
2270                         } else {
2271                                 list_for_each_entry(req, &ep->queue, queue) {
2272                                         t = scnprintf(next, size,
2273                                                 "req %p actual 0x%x length "
2274                                                 "0x%x  buf %p\n",
2275                                                 &req->req, req->req.actual,
2276                                                 req->req.length, req->req.buf);
2277                                         size -= t;
2278                                         next += t;
2279                                         }       /* end for each_entry of ep req */
2280                                 }       /* end for else */
2281                         }       /* end for if(ep->queue) */
2282                 }               /* end (ep->desc) */
2283
2284         spin_unlock_irqrestore(&udc->lock, flags);
2285
2286         *eof = 1;
2287         return count - size;
2288 }
2289
2290 #define create_proc_file()      create_proc_read_entry(proc_filename, \
2291                                 0, NULL, fsl_proc_read, NULL)
2292
2293 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2294
2295 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2296
2297 #define create_proc_file()      do {} while (0)
2298 #define remove_proc_file()      do {} while (0)
2299
2300 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2301
2302 /*-------------------------------------------------------------------------*/
2303
2304 /* Release udc structures */
2305 static void fsl_udc_release(struct device *dev)
2306 {
2307         complete(udc_controller->done);
2308         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2309                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2310         kfree(udc_controller);
2311 }
2312
2313 /******************************************************************
2314         Internal structure setup functions
2315 *******************************************************************/
2316 /*------------------------------------------------------------------
2317  * init resource for globle controller
2318  * Return the udc handle on success or NULL on failure
2319  ------------------------------------------------------------------*/
2320 static int __init struct_udc_setup(struct fsl_udc *udc,
2321                 struct platform_device *pdev)
2322 {
2323         struct fsl_usb2_platform_data *pdata;
2324         size_t size;
2325
2326         pdata = pdev->dev.platform_data;
2327         udc->phy_mode = pdata->phy_mode;
2328
2329         udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2330         if (!udc->eps) {
2331                 ERR("malloc fsl_ep failed\n");
2332                 return -1;
2333         }
2334
2335         /* initialized QHs, take care of alignment */
2336         size = udc->max_ep * sizeof(struct ep_queue_head);
2337         if (size < QH_ALIGNMENT)
2338                 size = QH_ALIGNMENT;
2339         else if ((size % QH_ALIGNMENT) != 0) {
2340                 size += QH_ALIGNMENT + 1;
2341                 size &= ~(QH_ALIGNMENT - 1);
2342         }
2343         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2344                                         &udc->ep_qh_dma, GFP_KERNEL);
2345         if (!udc->ep_qh) {
2346                 ERR("malloc QHs for udc failed\n");
2347                 kfree(udc->eps);
2348                 return -1;
2349         }
2350
2351         udc->ep_qh_size = size;
2352
2353         /* Initialize ep0 status request structure */
2354         /* FIXME: fsl_alloc_request() ignores ep argument */
2355         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2356                         struct fsl_req, req);
2357         /* allocate a small amount of memory to get valid address */
2358         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2359
2360         udc->resume_state = USB_STATE_NOTATTACHED;
2361         udc->usb_state = USB_STATE_POWERED;
2362         udc->ep0_dir = 0;
2363         udc->remote_wakeup = 0; /* default to 0 on reset */
2364
2365         return 0;
2366 }
2367
2368 /*----------------------------------------------------------------
2369  * Setup the fsl_ep struct for eps
2370  * Link fsl_ep->ep to gadget->ep_list
2371  * ep0out is not used so do nothing here
2372  * ep0in should be taken care
2373  *--------------------------------------------------------------*/
2374 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2375                 char *name, int link)
2376 {
2377         struct fsl_ep *ep = &udc->eps[index];
2378
2379         ep->udc = udc;
2380         strcpy(ep->name, name);
2381         ep->ep.name = ep->name;
2382
2383         ep->ep.ops = &fsl_ep_ops;
2384         ep->stopped = 0;
2385
2386         /* for ep0: maxP defined in desc
2387          * for other eps, maxP is set by epautoconfig() called by gadget layer
2388          */
2389         ep->ep.maxpacket = (unsigned short) ~0;
2390
2391         /* the queue lists any req for this ep */
2392         INIT_LIST_HEAD(&ep->queue);
2393
2394         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2395         if (link)
2396                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2397         ep->gadget = &udc->gadget;
2398         ep->qh = &udc->ep_qh[index];
2399
2400         return 0;
2401 }
2402
2403 /* Driver probe function
2404  * all intialization operations implemented here except enabling usb_intr reg
2405  * board setup should have been done in the platform code
2406  */
2407 static int __init fsl_udc_probe(struct platform_device *pdev)
2408 {
2409         struct fsl_usb2_platform_data *pdata;
2410         struct resource *res;
2411         int ret = -ENODEV;
2412         unsigned int i;
2413         u32 dccparams;
2414
2415         if (strcmp(pdev->name, driver_name)) {
2416                 VDBG("Wrong device");
2417                 return -ENODEV;
2418         }
2419
2420         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2421         if (udc_controller == NULL) {
2422                 ERR("malloc udc failed\n");
2423                 return -ENOMEM;
2424         }
2425
2426         pdata = pdev->dev.platform_data;
2427         udc_controller->pdata = pdata;
2428         spin_lock_init(&udc_controller->lock);
2429         udc_controller->stopped = 1;
2430
2431 #ifdef CONFIG_USB_OTG
2432         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2433                 udc_controller->transceiver = otg_get_transceiver();
2434                 if (!udc_controller->transceiver) {
2435                         ERR("Can't find OTG driver!\n");
2436                         ret = -ENODEV;
2437                         goto err_kfree;
2438                 }
2439         }
2440 #endif
2441
2442         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2443         if (!res) {
2444                 ret = -ENXIO;
2445                 goto err_kfree;
2446         }
2447
2448         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2449                 if (!request_mem_region(res->start, resource_size(res),
2450                                         driver_name)) {
2451                         ERR("request mem region for %s failed\n", pdev->name);
2452                         ret = -EBUSY;
2453                         goto err_kfree;
2454                 }
2455         }
2456
2457         dr_regs = ioremap(res->start, resource_size(res));
2458         if (!dr_regs) {
2459                 ret = -ENOMEM;
2460                 goto err_release_mem_region;
2461         }
2462
2463         pdata->regs = (void *)dr_regs;
2464
2465         /*
2466          * do platform specific init: check the clock, grab/config pins, etc.
2467          */
2468         if (pdata->init && pdata->init(pdev)) {
2469                 ret = -ENODEV;
2470                 goto err_iounmap_noclk;
2471         }
2472
2473         /* Set accessors only after pdata->init() ! */
2474         fsl_set_accessors(pdata);
2475
2476 #ifndef CONFIG_ARCH_MXC
2477         if (pdata->have_sysif_regs)
2478                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2479 #endif
2480
2481         /* Initialize USB clocks */
2482         ret = fsl_udc_clk_init(pdev);
2483         if (ret < 0)
2484                 goto err_iounmap_noclk;
2485
2486         /* Read Device Controller Capability Parameters register */
2487         dccparams = fsl_readl(&dr_regs->dccparams);
2488         if (!(dccparams & DCCPARAMS_DC)) {
2489                 ERR("This SOC doesn't support device role\n");
2490                 ret = -ENODEV;
2491                 goto err_iounmap;
2492         }
2493         /* Get max device endpoints */
2494         /* DEN is bidirectional ep number, max_ep doubles the number */
2495         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2496
2497         udc_controller->irq = platform_get_irq(pdev, 0);
2498         if (!udc_controller->irq) {
2499                 ret = -ENODEV;
2500                 goto err_iounmap;
2501         }
2502
2503         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2504                         driver_name, udc_controller);
2505         if (ret != 0) {
2506                 ERR("cannot request irq %d err %d\n",
2507                                 udc_controller->irq, ret);
2508                 goto err_iounmap;
2509         }
2510
2511         /* Initialize the udc structure including QH member and other member */
2512         if (struct_udc_setup(udc_controller, pdev)) {
2513                 ERR("Can't initialize udc data structure\n");
2514                 ret = -ENOMEM;
2515                 goto err_free_irq;
2516         }
2517
2518         if (!udc_controller->transceiver) {
2519                 /* initialize usb hw reg except for regs for EP,
2520                  * leave usbintr reg untouched */
2521                 dr_controller_setup(udc_controller);
2522         }
2523
2524         fsl_udc_clk_finalize(pdev);
2525
2526         /* Setup gadget structure */
2527         udc_controller->gadget.ops = &fsl_gadget_ops;
2528         udc_controller->gadget.is_dualspeed = 1;
2529         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2530         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2531         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2532         udc_controller->gadget.name = driver_name;
2533
2534         /* Setup gadget.dev and register with kernel */
2535         dev_set_name(&udc_controller->gadget.dev, "gadget");
2536         udc_controller->gadget.dev.release = fsl_udc_release;
2537         udc_controller->gadget.dev.parent = &pdev->dev;
2538         ret = device_register(&udc_controller->gadget.dev);
2539         if (ret < 0)
2540                 goto err_free_irq;
2541
2542         if (udc_controller->transceiver)
2543                 udc_controller->gadget.is_otg = 1;
2544
2545         /* setup QH and epctrl for ep0 */
2546         ep0_setup(udc_controller);
2547
2548         /* setup udc->eps[] for ep0 */
2549         struct_ep_setup(udc_controller, 0, "ep0", 0);
2550         /* for ep0: the desc defined here;
2551          * for other eps, gadget layer called ep_enable with defined desc
2552          */
2553         udc_controller->eps[0].desc = &fsl_ep0_desc;
2554         udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2555
2556         /* setup the udc->eps[] for non-control endpoints and link
2557          * to gadget.ep_list */
2558         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2559                 char name[14];
2560
2561                 sprintf(name, "ep%dout", i);
2562                 struct_ep_setup(udc_controller, i * 2, name, 1);
2563                 sprintf(name, "ep%din", i);
2564                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2565         }
2566
2567         /* use dma_pool for TD management */
2568         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2569                         sizeof(struct ep_td_struct),
2570                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2571         if (udc_controller->td_pool == NULL) {
2572                 ret = -ENOMEM;
2573                 goto err_unregister;
2574         }
2575
2576         ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2577         if (ret)
2578                 goto err_del_udc;
2579
2580         create_proc_file();
2581         return 0;
2582
2583 err_del_udc:
2584         dma_pool_destroy(udc_controller->td_pool);
2585 err_unregister:
2586         device_unregister(&udc_controller->gadget.dev);
2587 err_free_irq:
2588         free_irq(udc_controller->irq, udc_controller);
2589 err_iounmap:
2590         if (pdata->exit)
2591                 pdata->exit(pdev);
2592         fsl_udc_clk_release();
2593 err_iounmap_noclk:
2594         iounmap(dr_regs);
2595 err_release_mem_region:
2596         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2597                 release_mem_region(res->start, resource_size(res));
2598 err_kfree:
2599         kfree(udc_controller);
2600         udc_controller = NULL;
2601         return ret;
2602 }
2603
2604 /* Driver removal function
2605  * Free resources and finish pending transactions
2606  */
2607 static int __exit fsl_udc_remove(struct platform_device *pdev)
2608 {
2609         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2610         struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2611
2612         DECLARE_COMPLETION(done);
2613
2614         if (!udc_controller)
2615                 return -ENODEV;
2616
2617         usb_del_gadget_udc(&udc_controller->gadget);
2618         udc_controller->done = &done;
2619
2620         fsl_udc_clk_release();
2621
2622         /* DR has been stopped in usb_gadget_unregister_driver() */
2623         remove_proc_file();
2624
2625         /* Free allocated memory */
2626         kfree(udc_controller->status_req->req.buf);
2627         kfree(udc_controller->status_req);
2628         kfree(udc_controller->eps);
2629
2630         dma_pool_destroy(udc_controller->td_pool);
2631         free_irq(udc_controller->irq, udc_controller);
2632         iounmap(dr_regs);
2633         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2634                 release_mem_region(res->start, resource_size(res));
2635
2636         device_unregister(&udc_controller->gadget.dev);
2637         /* free udc --wait for the release() finished */
2638         wait_for_completion(&done);
2639
2640         /*
2641          * do platform specific un-initialization:
2642          * release iomux pins, etc.
2643          */
2644         if (pdata->exit)
2645                 pdata->exit(pdev);
2646
2647         return 0;
2648 }
2649
2650 /*-----------------------------------------------------------------
2651  * Modify Power management attributes
2652  * Used by OTG statemachine to disable gadget temporarily
2653  -----------------------------------------------------------------*/
2654 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2655 {
2656         dr_controller_stop(udc_controller);
2657         return 0;
2658 }
2659
2660 /*-----------------------------------------------------------------
2661  * Invoked on USB resume. May be called in_interrupt.
2662  * Here we start the DR controller and enable the irq
2663  *-----------------------------------------------------------------*/
2664 static int fsl_udc_resume(struct platform_device *pdev)
2665 {
2666         /* Enable DR irq reg and set controller Run */
2667         if (udc_controller->stopped) {
2668                 dr_controller_setup(udc_controller);
2669                 dr_controller_run(udc_controller);
2670         }
2671         udc_controller->usb_state = USB_STATE_ATTACHED;
2672         udc_controller->ep0_state = WAIT_FOR_SETUP;
2673         udc_controller->ep0_dir = 0;
2674         return 0;
2675 }
2676
2677 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2678 {
2679         struct fsl_udc *udc = udc_controller;
2680         u32 mode, usbcmd;
2681
2682         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2683
2684         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2685
2686         /*
2687          * If the controller is already stopped, then this must be a
2688          * PM suspend.  Remember this fact, so that we will leave the
2689          * controller stopped at PM resume time.
2690          */
2691         if (udc->stopped) {
2692                 pr_debug("gadget already stopped, leaving early\n");
2693                 udc->already_stopped = 1;
2694                 return 0;
2695         }
2696
2697         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2698                 pr_debug("gadget not in device mode, leaving early\n");
2699                 return 0;
2700         }
2701
2702         /* stop the controller */
2703         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2704         fsl_writel(usbcmd, &dr_regs->usbcmd);
2705
2706         udc->stopped = 1;
2707
2708         pr_info("USB Gadget suspended\n");
2709
2710         return 0;
2711 }
2712
2713 static int fsl_udc_otg_resume(struct device *dev)
2714 {
2715         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2716                  udc_controller->stopped, udc_controller->already_stopped);
2717
2718         /*
2719          * If the controller was stopped at suspend time, then
2720          * don't resume it now.
2721          */
2722         if (udc_controller->already_stopped) {
2723                 udc_controller->already_stopped = 0;
2724                 pr_debug("gadget was already stopped, leaving early\n");
2725                 return 0;
2726         }
2727
2728         pr_info("USB Gadget resume\n");
2729
2730         return fsl_udc_resume(NULL);
2731 }
2732
2733 /*-------------------------------------------------------------------------
2734         Register entry point for the peripheral controller driver
2735 --------------------------------------------------------------------------*/
2736
2737 static struct platform_driver udc_driver = {
2738         .remove  = __exit_p(fsl_udc_remove),
2739         /* these suspend and resume are not usb suspend and resume */
2740         .suspend = fsl_udc_suspend,
2741         .resume  = fsl_udc_resume,
2742         .driver  = {
2743                 .name = (char *)driver_name,
2744                 .owner = THIS_MODULE,
2745                 /* udc suspend/resume called from OTG driver */
2746                 .suspend = fsl_udc_otg_suspend,
2747                 .resume  = fsl_udc_otg_resume,
2748         },
2749 };
2750
2751 static int __init udc_init(void)
2752 {
2753         printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2754         return platform_driver_probe(&udc_driver, fsl_udc_probe);
2755 }
2756
2757 module_init(udc_init);
2758
2759 static void __exit udc_exit(void)
2760 {
2761         platform_driver_unregister(&udc_driver);
2762         printk(KERN_WARNING "%s unregistered\n", driver_desc);
2763 }
2764
2765 module_exit(udc_exit);
2766
2767 MODULE_DESCRIPTION(DRIVER_DESC);
2768 MODULE_AUTHOR(DRIVER_AUTHOR);
2769 MODULE_LICENSE("GPL");
2770 MODULE_ALIAS("platform:fsl-usb2-udc");