drivers/usb/gadget/fsl_udc_core.c

   1 /*
   2  * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Author: Li Yang <leoli@freescale.com>
   6  *         Jiang Bo <tanya.jiang@freescale.com>
   7  *
   8  * Description:
   9  * Freescale high-speed USB SOC DR module device controller driver.
  10  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  11  * The driver is previously named as mpc_udc.  Based on bare board
  12  * code from Dave Liu and Shlomi Gridish.
  13  *
  14  * This program is free software; you can redistribute  it and/or modify it
  15  * under  the terms of  the GNU General  Public License as published by the
  16  * Free Software Foundation;  either version 2 of the  License, or (at your
  17  * option) any later version.
  18  */
  19
  20 #undef VERBOSE
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/ioport.h>
  25 #include <linux/types.h>
  26 #include <linux/errno.h>
  27 #include <linux/slab.h>
  28 #include <linux/init.h>
  29 #include <linux/list.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/proc_fs.h>
  32 #include <linux/mm.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include <linux/usb/ch9.h>
  36 #include <linux/usb/gadget.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/fsl_devices.h>
  41 #include <linux/dmapool.h>
  42 #include <linux/delay.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/io.h>
  46 #include <asm/system.h>
  47 #include <asm/unaligned.h>
  48 #include <asm/dma.h>
  49
  50 #include "fsl_usb2_udc.h"
  51
  52 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  53 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  54 #define DRIVER_VERSION  "Apr 20, 2007"
  55
  56 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  57
  58 static const char driver_name[] = "fsl-usb2-udc";
  59 static const char driver_desc[] = DRIVER_DESC;
  60
  61 static struct usb_dr_device *dr_regs;
  62 #ifndef CONFIG_ARCH_MXC
  63 static struct usb_sys_interface *usb_sys_regs;
  64 #endif
  65
  66 /* it is initialized in probe()  */
  67 static struct fsl_udc *udc_controller = NULL;
  68
  69 static const struct usb_endpoint_descriptor
  70 fsl_ep0_desc = {
  71         .bLength =              USB_DT_ENDPOINT_SIZE,
  72         .bDescriptorType =      USB_DT_ENDPOINT,
  73         .bEndpointAddress =     0,
  74         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  75         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  76 };
  77
  78 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  79
  80 #ifdef CONFIG_PPC32
  81 /*
  82  * On some SoCs, the USB controller registers can be big or little endian,
  83  * depending on the version of the chip. In order to be able to run the
  84  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  85  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  86  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  87  * call through those pointers. Platform code for SoCs that have BE USB
  88  * registers should set pdata->big_endian_mmio flag.
  89  *
  90  * This also applies to controller-to-cpu accessors for the USB descriptors,
  91  * since their endianness is also SoC dependant. Platform code for SoCs that
  92  * have BE USB descriptors should set pdata->big_endian_desc flag.
  93  */
  94 static u32 _fsl_readl_be(const unsigned __iomem *p)
  95 {
  96         return in_be32(p);
  97 }
  98
  99 static u32 _fsl_readl_le(const unsigned __iomem *p)
 100 {
 101         return in_le32(p);
 102 }
 103
 104 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
 105 {
 106         out_be32(p, v);
 107 }
 108
 109 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 110 {
 111         out_le32(p, v);
 112 }
 113
 114 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 115 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 116
 117 #define fsl_readl(p)            (*_fsl_readl)((p))
 118 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 119
 120 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 121 {
 122         if (pdata->big_endian_mmio) {
 123                 _fsl_readl = _fsl_readl_be;
 124                 _fsl_writel = _fsl_writel_be;
 125         } else {
 126                 _fsl_readl = _fsl_readl_le;
 127                 _fsl_writel = _fsl_writel_le;
 128         }
 129 }
 130
 131 static inline u32 cpu_to_hc32(const u32 x)
 132 {
 133         return udc_controller->pdata->big_endian_desc
 134                 ? (__force u32)cpu_to_be32(x)
 135                 : (__force u32)cpu_to_le32(x);
 136 }
 137
 138 static inline u32 hc32_to_cpu(const u32 x)
 139 {
 140         return udc_controller->pdata->big_endian_desc
 141                 ? be32_to_cpu((__force __be32)x)
 142                 : le32_to_cpu((__force __le32)x);
 143 }
 144 #else /* !CONFIG_PPC32 */
 145 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 146
 147 #define fsl_readl(addr)         readl(addr)
 148 #define fsl_writel(val32, addr) writel(val32, addr)
 149 #define cpu_to_hc32(x)          cpu_to_le32(x)
 150 #define hc32_to_cpu(x)          le32_to_cpu(x)
 151 #endif /* CONFIG_PPC32 */
 152
 153 /********************************************************************
 154  *      Internal Used Function
 155 ********************************************************************/
 156 /*-----------------------------------------------------------------
 157  * done() - retire a request; caller blocked irqs
 158  * @status : request status to be set, only works when
 159  *      request is still in progress.
 160  *--------------------------------------------------------------*/
 161 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 162 {
 163         struct fsl_udc *udc = NULL;
 164         unsigned char stopped = ep->stopped;
 165         struct ep_td_struct *curr_td, *next_td;
 166         int j;
 167
 168         udc = (struct fsl_udc *)ep->udc;
 169         /* Removed the req from fsl_ep->queue */
 170         list_del_init(&req->queue);
 171
 172         /* req.status should be set as -EINPROGRESS in ep_queue() */
 173         if (req->req.status == -EINPROGRESS)
 174                 req->req.status = status;
 175         else
 176                 status = req->req.status;
 177
 178         /* Free dtd for the request */
 179         next_td = req->head;
 180         for (j = 0; j < req->dtd_count; j++) {
 181                 curr_td = next_td;
 182                 if (j != req->dtd_count - 1) {
 183                         next_td = curr_td->next_td_virt;
 184                 }
 185                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 186         }
 187
 188         if (req->mapped) {
 189                 dma_unmap_single(ep->udc->gadget.dev.parent,
 190                         req->req.dma, req->req.length,
 191                         ep_is_in(ep)
 192                                 ? DMA_TO_DEVICE
 193                                 : DMA_FROM_DEVICE);
 194                 req->req.dma = DMA_ADDR_INVALID;
 195                 req->mapped = 0;
 196         } else
 197                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 198                         req->req.dma, req->req.length,
 199                         ep_is_in(ep)
 200                                 ? DMA_TO_DEVICE
 201                                 : DMA_FROM_DEVICE);
 202
 203         if (status && (status != -ESHUTDOWN))
 204                 VDBG("complete %s req %p stat %d len %u/%u",
 205                         ep->ep.name, &req->req, status,
 206                         req->req.actual, req->req.length);
 207
 208         ep->stopped = 1;
 209
 210         spin_unlock(&ep->udc->lock);
 211         /* complete() is from gadget layer,
 212          * eg fsg->bulk_in_complete() */
 213         if (req->req.complete)
 214                 req->req.complete(&ep->ep, &req->req);
 215
 216         spin_lock(&ep->udc->lock);
 217         ep->stopped = stopped;
 218 }
 219
 220 /*-----------------------------------------------------------------
 221  * nuke(): delete all requests related to this ep
 222  * called with spinlock held
 223  *--------------------------------------------------------------*/
 224 static void nuke(struct fsl_ep *ep, int status)
 225 {
 226         ep->stopped = 1;
 227
 228         /* Flush fifo */
 229         fsl_ep_fifo_flush(&ep->ep);
 230
 231         /* Whether this eq has request linked */
 232         while (!list_empty(&ep->queue)) {
 233                 struct fsl_req *req = NULL;
 234
 235                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 236                 done(ep, req, status);
 237         }
 238 }
 239
 240 /*------------------------------------------------------------------
 241         Internal Hardware related function
 242  ------------------------------------------------------------------*/
 243
 244 static int dr_controller_setup(struct fsl_udc *udc)
 245 {
 246         unsigned int tmp, portctrl, ep_num;
 247         unsigned int max_no_of_ep;
 248 #ifndef CONFIG_ARCH_MXC
 249         unsigned int ctrl;
 250 #endif
 251         unsigned long timeout;
 252 #define FSL_UDC_RESET_TIMEOUT 1000
 253
 254         /* Config PHY interface */
 255         portctrl = fsl_readl(&dr_regs->portsc1);
 256         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 257         switch (udc->phy_mode) {
 258         case FSL_USB2_PHY_ULPI:
 259                 portctrl |= PORTSCX_PTS_ULPI;
 260                 break;
 261         case FSL_USB2_PHY_UTMI_WIDE:
 262                 portctrl |= PORTSCX_PTW_16BIT;
 263                 /* fall through */
 264         case FSL_USB2_PHY_UTMI:
 265                 portctrl |= PORTSCX_PTS_UTMI;
 266                 break;
 267         case FSL_USB2_PHY_SERIAL:
 268                 portctrl |= PORTSCX_PTS_FSLS;
 269                 break;
 270         default:
 271                 return -EINVAL;
 272         }
 273         fsl_writel(portctrl, &dr_regs->portsc1);
 274
 275         /* Stop and reset the usb controller */
 276         tmp = fsl_readl(&dr_regs->usbcmd);
 277         tmp &= ~USB_CMD_RUN_STOP;
 278         fsl_writel(tmp, &dr_regs->usbcmd);
 279
 280         tmp = fsl_readl(&dr_regs->usbcmd);
 281         tmp |= USB_CMD_CTRL_RESET;
 282         fsl_writel(tmp, &dr_regs->usbcmd);
 283
 284         /* Wait for reset to complete */
 285         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 286         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 287                 if (time_after(jiffies, timeout)) {
 288                         ERR("udc reset timeout!\n");
 289                         return -ETIMEDOUT;
 290                 }
 291                 cpu_relax();
 292         }
 293
 294         /* Set the controller as device mode */
 295         tmp = fsl_readl(&dr_regs->usbmode);
 296         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 297         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 298         /* Disable Setup Lockout */
 299         tmp |= USB_MODE_SETUP_LOCK_OFF;
 300         if (udc->pdata->es)
 301                 tmp |= USB_MODE_ES;
 302         fsl_writel(tmp, &dr_regs->usbmode);
 303
 304         /* Clear the setup status */
 305         fsl_writel(0, &dr_regs->usbsts);
 306
 307         tmp = udc->ep_qh_dma;
 308         tmp &= USB_EP_LIST_ADDRESS_MASK;
 309         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 310
 311         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 312                 udc->ep_qh, (int)tmp,
 313                 fsl_readl(&dr_regs->endpointlistaddr));
 314
 315         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 316         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 317                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 318                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 319                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 320                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 321                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 322         }
 323         /* Config control enable i/o output, cpu endian register */
 324 #ifndef CONFIG_ARCH_MXC
 325         if (udc->pdata->have_sysif_regs) {
 326                 ctrl = __raw_readl(&usb_sys_regs->control);
 327                 ctrl |= USB_CTRL_IOENB;
 328                 __raw_writel(ctrl, &usb_sys_regs->control);
 329         }
 330 #endif
 331
 332 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 333         /* Turn on cache snooping hardware, since some PowerPC platforms
 334          * wholly rely on hardware to deal with cache coherent. */
 335
 336         if (udc->pdata->have_sysif_regs) {
 337                 /* Setup Snooping for all the 4GB space */
 338                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 339                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 340                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 341                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 342         }
 343 #endif
 344
 345         return 0;
 346 }
 347
 348 /* Enable DR irq and set controller to run state */
 349 static void dr_controller_run(struct fsl_udc *udc)
 350 {
 351         u32 temp;
 352
 353         /* Enable DR irq reg */
 354         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 355                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 356                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 357
 358         fsl_writel(temp, &dr_regs->usbintr);
 359
 360         /* Clear stopped bit */
 361         udc->stopped = 0;
 362
 363         /* Set the controller as device mode */
 364         temp = fsl_readl(&dr_regs->usbmode);
 365         temp |= USB_MODE_CTRL_MODE_DEVICE;
 366         fsl_writel(temp, &dr_regs->usbmode);
 367
 368         /* Set controller to Run */
 369         temp = fsl_readl(&dr_regs->usbcmd);
 370         temp |= USB_CMD_RUN_STOP;
 371         fsl_writel(temp, &dr_regs->usbcmd);
 372 }
 373
 374 static void dr_controller_stop(struct fsl_udc *udc)
 375 {
 376         unsigned int tmp;
 377
 378         pr_debug("%s\n", __func__);
 379
 380         /* if we're in OTG mode, and the Host is currently using the port,
 381          * stop now and don't rip the controller out from under the
 382          * ehci driver
 383          */
 384         if (udc->gadget.is_otg) {
 385                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 386                         pr_debug("udc: Leaving early\n");
 387                         return;
 388                 }
 389         }
 390
 391         /* disable all INTR */
 392         fsl_writel(0, &dr_regs->usbintr);
 393
 394         /* Set stopped bit for isr */
 395         udc->stopped = 1;
 396
 397         /* disable IO output */
 398 /*      usb_sys_regs->control = 0; */
 399
 400         /* set controller to Stop */
 401         tmp = fsl_readl(&dr_regs->usbcmd);
 402         tmp &= ~USB_CMD_RUN_STOP;
 403         fsl_writel(tmp, &dr_regs->usbcmd);
 404 }
 405
 406 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 407                         unsigned char ep_type)
 408 {
 409         unsigned int tmp_epctrl = 0;
 410
 411         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 412         if (dir) {
 413                 if (ep_num)
 414                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 415                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 416                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 417                 tmp_epctrl |= ((unsigned int)(ep_type)
 418                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 419         } else {
 420                 if (ep_num)
 421                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 422                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 423                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 424                 tmp_epctrl |= ((unsigned int)(ep_type)
 425                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 426         }
 427
 428         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 429 }
 430
 431 static void
 432 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 433 {
 434         u32 tmp_epctrl = 0;
 435
 436         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 437
 438         if (value) {
 439                 /* set the stall bit */
 440                 if (dir)
 441                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 442                 else
 443                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 444         } else {
 445                 /* clear the stall bit and reset data toggle */
 446                 if (dir) {
 447                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 448                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 449                 } else {
 450                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 451                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 452                 }
 453         }
 454         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 455 }
 456
 457 /* Get stall status of a specific ep
 458    Return: 0: not stalled; 1:stalled */
 459 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 460 {
 461         u32 epctrl;
 462
 463         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 464         if (dir)
 465                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 466         else
 467                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 468 }
 469
 470 /********************************************************************
 471         Internal Structure Build up functions
 472 ********************************************************************/
 473
 474 /*------------------------------------------------------------------
 475 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 476  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 477  * @mult: Mult field
 478  ------------------------------------------------------------------*/
 479 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 480                 unsigned char dir, unsigned char ep_type,
 481                 unsigned int max_pkt_len,
 482                 unsigned int zlt, unsigned char mult)
 483 {
 484         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 485         unsigned int tmp = 0;
 486
 487         /* set the Endpoint Capabilites in QH */
 488         switch (ep_type) {
 489         case USB_ENDPOINT_XFER_CONTROL:
 490                 /* Interrupt On Setup (IOS). for control ep  */
 491                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 492                         | EP_QUEUE_HEAD_IOS;
 493                 break;
 494         case USB_ENDPOINT_XFER_ISOC:
 495                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 496                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 497                 break;
 498         case USB_ENDPOINT_XFER_BULK:
 499         case USB_ENDPOINT_XFER_INT:
 500                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 501                 break;
 502         default:
 503                 VDBG("error ep type is %d", ep_type);
 504                 return;
 505         }
 506         if (zlt)
 507                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 508
 509         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 510         p_QH->next_dtd_ptr = 1;
 511         p_QH->size_ioc_int_sts = 0;
 512 }
 513
 514 /* Setup qh structure and ep register for ep0. */
 515 static void ep0_setup(struct fsl_udc *udc)
 516 {
 517         /* the intialization of an ep includes: fields in QH, Regs,
 518          * fsl_ep struct */
 519         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 520                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 521         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 522                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 523         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 524         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 525
 526         return;
 527
 528 }
 529
 530 /***********************************************************************
 531                 Endpoint Management Functions
 532 ***********************************************************************/
 533
 534 /*-------------------------------------------------------------------------
 535  * when configurations are set, or when interface settings change
 536  * for example the do_set_interface() in gadget layer,
 537  * the driver will enable or disable the relevant endpoints
 538  * ep0 doesn't use this routine. It is always enabled.
 539 -------------------------------------------------------------------------*/
 540 static int fsl_ep_enable(struct usb_ep *_ep,
 541                 const struct usb_endpoint_descriptor *desc)
 542 {
 543         struct fsl_udc *udc = NULL;
 544         struct fsl_ep *ep = NULL;
 545         unsigned short max = 0;
 546         unsigned char mult = 0, zlt;
 547         int retval = -EINVAL;
 548         unsigned long flags = 0;
 549
 550         ep = container_of(_ep, struct fsl_ep, ep);
 551
 552         /* catch various bogus parameters */
 553         if (!_ep || !desc || ep->desc
 554                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 555                 return -EINVAL;
 556
 557         udc = ep->udc;
 558
 559         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 560                 return -ESHUTDOWN;
 561
 562         max = le16_to_cpu(desc->wMaxPacketSize);
 563
 564         /* Disable automatic zlp generation.  Driver is responsible to indicate
 565          * explicitly through req->req.zero.  This is needed to enable multi-td
 566          * request. */
 567         zlt = 1;
 568
 569         /* Assume the max packet size from gadget is always correct */
 570         switch (desc->bmAttributes & 0x03) {
 571         case USB_ENDPOINT_XFER_CONTROL:
 572         case USB_ENDPOINT_XFER_BULK:
 573         case USB_ENDPOINT_XFER_INT:
 574                 /* mult = 0.  Execute N Transactions as demonstrated by
 575                  * the USB variable length packet protocol where N is
 576                  * computed using the Maximum Packet Length (dQH) and
 577                  * the Total Bytes field (dTD) */
 578                 mult = 0;
 579                 break;
 580         case USB_ENDPOINT_XFER_ISOC:
 581                 /* Calculate transactions needed for high bandwidth iso */
 582                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 583                 max = max & 0x7ff;      /* bit 0~10 */
 584                 /* 3 transactions at most */
 585                 if (mult > 3)
 586                         goto en_done;
 587                 break;
 588         default:
 589                 goto en_done;
 590         }
 591
 592         spin_lock_irqsave(&udc->lock, flags);
 593         ep->ep.maxpacket = max;
 594         ep->desc = desc;
 595         ep->stopped = 0;
 596
 597         /* Controller related setup */
 598         /* Init EPx Queue Head (Ep Capabilites field in QH
 599          * according to max, zlt, mult) */
 600         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 601                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 602                                         ?  USB_SEND : USB_RECV),
 603                         (unsigned char) (desc->bmAttributes
 604                                         & USB_ENDPOINT_XFERTYPE_MASK),
 605                         max, zlt, mult);
 606
 607         /* Init endpoint ctrl register */
 608         dr_ep_setup((unsigned char) ep_index(ep),
 609                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 610                                         ? USB_SEND : USB_RECV),
 611                         (unsigned char) (desc->bmAttributes
 612                                         & USB_ENDPOINT_XFERTYPE_MASK));
 613
 614         spin_unlock_irqrestore(&udc->lock, flags);
 615         retval = 0;
 616
 617         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 618                         ep->desc->bEndpointAddress & 0x0f,
 619                         (desc->bEndpointAddress & USB_DIR_IN)
 620                                 ? "in" : "out", max);
 621 en_done:
 622         return retval;
 623 }
 624
 625 /*---------------------------------------------------------------------
 626  * @ep : the ep being unconfigured. May not be ep0
 627  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 628 *---------------------------------------------------------------------*/
 629 static int fsl_ep_disable(struct usb_ep *_ep)
 630 {
 631         struct fsl_udc *udc = NULL;
 632         struct fsl_ep *ep = NULL;
 633         unsigned long flags = 0;
 634         u32 epctrl;
 635         int ep_num;
 636
 637         ep = container_of(_ep, struct fsl_ep, ep);
 638         if (!_ep || !ep->desc) {
 639                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 640                 return -EINVAL;
 641         }
 642
 643         /* disable ep on controller */
 644         ep_num = ep_index(ep);
 645         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 646         if (ep_is_in(ep)) {
 647                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 648                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 649         } else {
 650                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 651                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 652         }
 653         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 654
 655         udc = (struct fsl_udc *)ep->udc;
 656         spin_lock_irqsave(&udc->lock, flags);
 657
 658         /* nuke all pending requests (does flush) */
 659         nuke(ep, -ESHUTDOWN);
 660
 661         ep->desc = NULL;
 662         ep->stopped = 1;
 663         spin_unlock_irqrestore(&udc->lock, flags);
 664
 665         VDBG("disabled %s OK", _ep->name);
 666         return 0;
 667 }
 668
 669 /*---------------------------------------------------------------------
 670  * allocate a request object used by this endpoint
 671  * the main operation is to insert the req->queue to the eq->queue
 672  * Returns the request, or null if one could not be allocated
 673 *---------------------------------------------------------------------*/
 674 static struct usb_request *
 675 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 676 {
 677         struct fsl_req *req = NULL;
 678
 679         req = kzalloc(sizeof *req, gfp_flags);
 680         if (!req)
 681                 return NULL;
 682
 683         req->req.dma = DMA_ADDR_INVALID;
 684         INIT_LIST_HEAD(&req->queue);
 685
 686         return &req->req;
 687 }
 688
 689 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 690 {
 691         struct fsl_req *req = NULL;
 692
 693         req = container_of(_req, struct fsl_req, req);
 694
 695         if (_req)
 696                 kfree(req);
 697 }
 698
 699 /*-------------------------------------------------------------------------*/
 700 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 701 {
 702         int i = ep_index(ep) * 2 + ep_is_in(ep);
 703         u32 temp, bitmask, tmp_stat;
 704         struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
 705
 706         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 707         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 708
 709         bitmask = ep_is_in(ep)
 710                 ? (1 << (ep_index(ep) + 16))
 711                 : (1 << (ep_index(ep)));
 712
 713         /* check if the pipe is empty */
 714         if (!(list_empty(&ep->queue))) {
 715                 /* Add td to the end */
 716                 struct fsl_req *lastreq;
 717                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 718                 lastreq->tail->next_td_ptr =
 719                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 720                 /* Read prime bit, if 1 goto done */
 721                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 722                         goto out;
 723
 724                 do {
 725                         /* Set ATDTW bit in USBCMD */
 726                         temp = fsl_readl(&dr_regs->usbcmd);
 727                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 728
 729                         /* Read correct status bit */
 730                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 731
 732                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 733
 734                 /* Write ATDTW bit to 0 */
 735                 temp = fsl_readl(&dr_regs->usbcmd);
 736                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 737
 738                 if (tmp_stat)
 739                         goto out;
 740         }
 741
 742         /* Write dQH next pointer and terminate bit to 0 */
 743         temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 744         dQH->next_dtd_ptr = cpu_to_hc32(temp);
 745
 746         /* Clear active and halt bit */
 747         temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 748                         | EP_QUEUE_HEAD_STATUS_HALT));
 749         dQH->size_ioc_int_sts &= temp;
 750
 751         /* Ensure that updates to the QH will occur before priming. */
 752         wmb();
 753
 754         /* Prime endpoint by writing 1 to ENDPTPRIME */
 755         temp = ep_is_in(ep)
 756                 ? (1 << (ep_index(ep) + 16))
 757                 : (1 << (ep_index(ep)));
 758         fsl_writel(temp, &dr_regs->endpointprime);
 759 out:
 760         return;
 761 }
 762
 763 /* Fill in the dTD structure
 764  * @req: request that the transfer belongs to
 765  * @length: return actually data length of the dTD
 766  * @dma: return dma address of the dTD
 767  * @is_last: return flag if it is the last dTD of the request
 768  * return: pointer to the built dTD */
 769 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 770                 dma_addr_t *dma, int *is_last)
 771 {
 772         u32 swap_temp;
 773         struct ep_td_struct *dtd;
 774
 775         /* how big will this transfer be? */
 776         *length = min(req->req.length - req->req.actual,
 777                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 778
 779         dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
 780         if (dtd == NULL)
 781                 return dtd;
 782
 783         dtd->td_dma = *dma;
 784         /* Clear reserved field */
 785         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 786         swap_temp &= ~DTD_RESERVED_FIELDS;
 787         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 788
 789         /* Init all of buffer page pointers */
 790         swap_temp = (u32) (req->req.dma + req->req.actual);
 791         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 792         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 793         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 794         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 795         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 796
 797         req->req.actual += *length;
 798
 799         /* zlp is needed if req->req.zero is set */
 800         if (req->req.zero) {
 801                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 802                         *is_last = 1;
 803                 else
 804                         *is_last = 0;
 805         } else if (req->req.length == req->req.actual)
 806                 *is_last = 1;
 807         else
 808                 *is_last = 0;
 809
 810         if ((*is_last) == 0)
 811                 VDBG("multi-dtd request!");
 812         /* Fill in the transfer size; set active bit */
 813         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 814
 815         /* Enable interrupt for the last dtd of a request */
 816         if (*is_last && !req->req.no_interrupt)
 817                 swap_temp |= DTD_IOC;
 818
 819         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 820
 821         mb();
 822
 823         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 824
 825         return dtd;
 826 }
 827
 828 /* Generate dtd chain for a request */
 829 static int fsl_req_to_dtd(struct fsl_req *req)
 830 {
 831         unsigned        count;
 832         int             is_last;
 833         int             is_first =1;
 834         struct ep_td_struct     *last_dtd = NULL, *dtd;
 835         dma_addr_t dma;
 836
 837         do {
 838                 dtd = fsl_build_dtd(req, &count, &dma, &is_last);
 839                 if (dtd == NULL)
 840                         return -ENOMEM;
 841
 842                 if (is_first) {
 843                         is_first = 0;
 844                         req->head = dtd;
 845                 } else {
 846                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 847                         last_dtd->next_td_virt = dtd;
 848                 }
 849                 last_dtd = dtd;
 850
 851                 req->dtd_count++;
 852         } while (!is_last);
 853
 854         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 855
 856         req->tail = dtd;
 857
 858         return 0;
 859 }
 860
 861 /* queues (submits) an I/O request to an endpoint */
 862 static int
 863 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 864 {
 865         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 866         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 867         struct fsl_udc *udc;
 868         unsigned long flags;
 869
 870         /* catch various bogus parameters */
 871         if (!_req || !req->req.complete || !req->req.buf
 872                         || !list_empty(&req->queue)) {
 873                 VDBG("%s, bad params", __func__);
 874                 return -EINVAL;
 875         }
 876         if (unlikely(!_ep || !ep->desc)) {
 877                 VDBG("%s, bad ep", __func__);
 878                 return -EINVAL;
 879         }
 880         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 881                 if (req->req.length > ep->ep.maxpacket)
 882                         return -EMSGSIZE;
 883         }
 884
 885         udc = ep->udc;
 886         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 887                 return -ESHUTDOWN;
 888
 889         req->ep = ep;
 890
 891         /* map virtual address to hardware */
 892         if (req->req.dma == DMA_ADDR_INVALID) {
 893                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 894                                         req->req.buf,
 895                                         req->req.length, ep_is_in(ep)
 896                                                 ? DMA_TO_DEVICE
 897                                                 : DMA_FROM_DEVICE);
 898                 req->mapped = 1;
 899         } else {
 900                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 901                                         req->req.dma, req->req.length,
 902                                         ep_is_in(ep)
 903                                                 ? DMA_TO_DEVICE
 904                                                 : DMA_FROM_DEVICE);
 905                 req->mapped = 0;
 906         }
 907
 908         req->req.status = -EINPROGRESS;
 909         req->req.actual = 0;
 910         req->dtd_count = 0;
 911
 912         spin_lock_irqsave(&udc->lock, flags);
 913
 914         /* build dtds and push them to device queue */
 915         if (!fsl_req_to_dtd(req)) {
 916                 fsl_queue_td(ep, req);
 917         } else {
 918                 spin_unlock_irqrestore(&udc->lock, flags);
 919                 return -ENOMEM;
 920         }
 921
 922         /* Update ep0 state */
 923         if ((ep_index(ep) == 0))
 924                 udc->ep0_state = DATA_STATE_XMIT;
 925
 926         /* irq handler advances the queue */
 927         if (req != NULL)
 928                 list_add_tail(&req->queue, &ep->queue);
 929         spin_unlock_irqrestore(&udc->lock, flags);
 930
 931         return 0;
 932 }
 933
 934 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 935 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 936 {
 937         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 938         struct fsl_req *req;
 939         unsigned long flags;
 940         int ep_num, stopped, ret = 0;
 941         u32 epctrl;
 942
 943         if (!_ep || !_req)
 944                 return -EINVAL;
 945
 946         spin_lock_irqsave(&ep->udc->lock, flags);
 947         stopped = ep->stopped;
 948
 949         /* Stop the ep before we deal with the queue */
 950         ep->stopped = 1;
 951         ep_num = ep_index(ep);
 952         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 953         if (ep_is_in(ep))
 954                 epctrl &= ~EPCTRL_TX_ENABLE;
 955         else
 956                 epctrl &= ~EPCTRL_RX_ENABLE;
 957         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 958
 959         /* make sure it's actually queued on this endpoint */
 960         list_for_each_entry(req, &ep->queue, queue) {
 961                 if (&req->req == _req)
 962                         break;
 963         }
 964         if (&req->req != _req) {
 965                 ret = -EINVAL;
 966                 goto out;
 967         }
 968
 969         /* The request is in progress, or completed but not dequeued */
 970         if (ep->queue.next == &req->queue) {
 971                 _req->status = -ECONNRESET;
 972                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 973
 974                 /* The request isn't the last request in this ep queue */
 975                 if (req->queue.next != &ep->queue) {
 976                         struct ep_queue_head *qh;
 977                         struct fsl_req *next_req;
 978
 979                         qh = ep->qh;
 980                         next_req = list_entry(req->queue.next, struct fsl_req,
 981                                         queue);
 982
 983                         /* Point the QH to the first TD of next request */
 984                         fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
 985                 }
 986
 987                 /* The request hasn't been processed, patch up the TD chain */
 988         } else {
 989                 struct fsl_req *prev_req;
 990
 991                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 992                 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
 993                                 &prev_req->tail->next_td_ptr);
 994
 995         }
 996
 997         done(ep, req, -ECONNRESET);
 998
 999         /* Enable EP */
1000 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1001         if (ep_is_in(ep))
1002                 epctrl |= EPCTRL_TX_ENABLE;
1003         else
1004                 epctrl |= EPCTRL_RX_ENABLE;
1005         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1006         ep->stopped = stopped;
1007
1008         spin_unlock_irqrestore(&ep->udc->lock, flags);
1009         return ret;
1010 }
1011
1012 /*-------------------------------------------------------------------------*/
1013
1014 /*-----------------------------------------------------------------
1015  * modify the endpoint halt feature
1016  * @ep: the non-isochronous endpoint being stalled
1017  * @value: 1--set halt  0--clear halt
1018  * Returns zero, or a negative error code.
1019 *----------------------------------------------------------------*/
1020 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1021 {
1022         struct fsl_ep *ep = NULL;
1023         unsigned long flags = 0;
1024         int status = -EOPNOTSUPP;       /* operation not supported */
1025         unsigned char ep_dir = 0, ep_num = 0;
1026         struct fsl_udc *udc = NULL;
1027
1028         ep = container_of(_ep, struct fsl_ep, ep);
1029         udc = ep->udc;
1030         if (!_ep || !ep->desc) {
1031                 status = -EINVAL;
1032                 goto out;
1033         }
1034
1035         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1036                 status = -EOPNOTSUPP;
1037                 goto out;
1038         }
1039
1040         /* Attempt to halt IN ep will fail if any transfer requests
1041          * are still queue */
1042         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1043                 status = -EAGAIN;
1044                 goto out;
1045         }
1046
1047         status = 0;
1048         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1049         ep_num = (unsigned char)(ep_index(ep));
1050         spin_lock_irqsave(&ep->udc->lock, flags);
1051         dr_ep_change_stall(ep_num, ep_dir, value);
1052         spin_unlock_irqrestore(&ep->udc->lock, flags);
1053
1054         if (ep_index(ep) == 0) {
1055                 udc->ep0_state = WAIT_FOR_SETUP;
1056                 udc->ep0_dir = 0;
1057         }
1058 out:
1059         VDBG(" %s %s halt stat %d", ep->ep.name,
1060                         value ?  "set" : "clear", status);
1061
1062         return status;
1063 }
1064
1065 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1066 {
1067         struct fsl_ep *ep;
1068         struct fsl_udc *udc;
1069         int size = 0;
1070         u32 bitmask;
1071         struct ep_queue_head *d_qh;
1072
1073         ep = container_of(_ep, struct fsl_ep, ep);
1074         if (!_ep || (!ep->desc && ep_index(ep) != 0))
1075                 return -ENODEV;
1076
1077         udc = (struct fsl_udc *)ep->udc;
1078
1079         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1080                 return -ESHUTDOWN;
1081
1082         d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1083
1084         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1085             (1 << (ep_index(ep)));
1086
1087         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1088                 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1089                     >> DTD_LENGTH_BIT_POS;
1090
1091         pr_debug("%s %u\n", __func__, size);
1092         return size;
1093 }
1094
1095 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1096 {
1097         struct fsl_ep *ep;
1098         int ep_num, ep_dir;
1099         u32 bits;
1100         unsigned long timeout;
1101 #define FSL_UDC_FLUSH_TIMEOUT 1000
1102
1103         if (!_ep) {
1104                 return;
1105         } else {
1106                 ep = container_of(_ep, struct fsl_ep, ep);
1107                 if (!ep->desc)
1108                         return;
1109         }
1110         ep_num = ep_index(ep);
1111         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1112
1113         if (ep_num == 0)
1114                 bits = (1 << 16) | 1;
1115         else if (ep_dir == USB_SEND)
1116                 bits = 1 << (16 + ep_num);
1117         else
1118                 bits = 1 << ep_num;
1119
1120         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1121         do {
1122                 fsl_writel(bits, &dr_regs->endptflush);
1123
1124                 /* Wait until flush complete */
1125                 while (fsl_readl(&dr_regs->endptflush)) {
1126                         if (time_after(jiffies, timeout)) {
1127                                 ERR("ep flush timeout\n");
1128                                 return;
1129                         }
1130                         cpu_relax();
1131                 }
1132                 /* See if we need to flush again */
1133         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1134 }
1135
1136 static struct usb_ep_ops fsl_ep_ops = {
1137         .enable = fsl_ep_enable,
1138         .disable = fsl_ep_disable,
1139
1140         .alloc_request = fsl_alloc_request,
1141         .free_request = fsl_free_request,
1142
1143         .queue = fsl_ep_queue,
1144         .dequeue = fsl_ep_dequeue,
1145
1146         .set_halt = fsl_ep_set_halt,
1147         .fifo_status = fsl_ep_fifo_status,
1148         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1149 };
1150
1151 /*-------------------------------------------------------------------------
1152                 Gadget Driver Layer Operations
1153 -------------------------------------------------------------------------*/
1154
1155 /*----------------------------------------------------------------------
1156  * Get the current frame number (from DR frame_index Reg )
1157  *----------------------------------------------------------------------*/
1158 static int fsl_get_frame(struct usb_gadget *gadget)
1159 {
1160         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1161 }
1162
1163 /*-----------------------------------------------------------------------
1164  * Tries to wake up the host connected to this gadget
1165  -----------------------------------------------------------------------*/
1166 static int fsl_wakeup(struct usb_gadget *gadget)
1167 {
1168         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1169         u32 portsc;
1170
1171         /* Remote wakeup feature not enabled by host */
1172         if (!udc->remote_wakeup)
1173                 return -ENOTSUPP;
1174
1175         portsc = fsl_readl(&dr_regs->portsc1);
1176         /* not suspended? */
1177         if (!(portsc & PORTSCX_PORT_SUSPEND))
1178                 return 0;
1179         /* trigger force resume */
1180         portsc |= PORTSCX_PORT_FORCE_RESUME;
1181         fsl_writel(portsc, &dr_regs->portsc1);
1182         return 0;
1183 }
1184
1185 static int can_pullup(struct fsl_udc *udc)
1186 {
1187         return udc->driver && udc->softconnect && udc->vbus_active;
1188 }
1189
1190 /* Notify controller that VBUS is powered, Called by whatever
1191    detects VBUS sessions */
1192 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1193 {
1194         struct fsl_udc  *udc;
1195         unsigned long   flags;
1196
1197         udc = container_of(gadget, struct fsl_udc, gadget);
1198         spin_lock_irqsave(&udc->lock, flags);
1199         VDBG("VBUS %s", is_active ? "on" : "off");
1200         udc->vbus_active = (is_active != 0);
1201         if (can_pullup(udc))
1202                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1203                                 &dr_regs->usbcmd);
1204         else
1205                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1206                                 &dr_regs->usbcmd);
1207         spin_unlock_irqrestore(&udc->lock, flags);
1208         return 0;
1209 }
1210
1211 /* constrain controller's VBUS power usage
1212  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1213  * reporting how much power the device may consume.  For example, this
1214  * could affect how quickly batteries are recharged.
1215  *
1216  * Returns zero on success, else negative errno.
1217  */
1218 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1219 {
1220         struct fsl_udc *udc;
1221
1222         udc = container_of(gadget, struct fsl_udc, gadget);
1223         if (udc->transceiver)
1224                 return otg_set_power(udc->transceiver, mA);
1225         return -ENOTSUPP;
1226 }
1227
1228 /* Change Data+ pullup status
1229  * this func is used by usb_gadget_connect/disconnet
1230  */
1231 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1232 {
1233         struct fsl_udc *udc;
1234
1235         udc = container_of(gadget, struct fsl_udc, gadget);
1236         udc->softconnect = (is_on != 0);
1237         if (can_pullup(udc))
1238                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1239                                 &dr_regs->usbcmd);
1240         else
1241                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1242                                 &dr_regs->usbcmd);
1243
1244         return 0;
1245 }
1246
1247 /* defined in gadget.h */
1248 static struct usb_gadget_ops fsl_gadget_ops = {
1249         .get_frame = fsl_get_frame,
1250         .wakeup = fsl_wakeup,
1251 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1252         .vbus_session = fsl_vbus_session,
1253         .vbus_draw = fsl_vbus_draw,
1254         .pullup = fsl_pullup,
1255 };
1256
1257 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1258    on new transaction */
1259 static void ep0stall(struct fsl_udc *udc)
1260 {
1261         u32 tmp;
1262
1263         /* must set tx and rx to stall at the same time */
1264         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1265         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1266         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1267         udc->ep0_state = WAIT_FOR_SETUP;
1268         udc->ep0_dir = 0;
1269 }
1270
1271 /* Prime a status phase for ep0 */
1272 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1273 {
1274         struct fsl_req *req = udc->status_req;
1275         struct fsl_ep *ep;
1276
1277         if (direction == EP_DIR_IN)
1278                 udc->ep0_dir = USB_DIR_IN;
1279         else
1280                 udc->ep0_dir = USB_DIR_OUT;
1281
1282         ep = &udc->eps[0];
1283         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1284
1285         req->ep = ep;
1286         req->req.length = 0;
1287         req->req.status = -EINPROGRESS;
1288         req->req.actual = 0;
1289         req->req.complete = NULL;
1290         req->dtd_count = 0;
1291
1292         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1293                         req->req.buf, req->req.length,
1294                         ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1295         req->mapped = 1;
1296
1297         if (fsl_req_to_dtd(req) == 0)
1298                 fsl_queue_td(ep, req);
1299         else
1300                 return -ENOMEM;
1301
1302         list_add_tail(&req->queue, &ep->queue);
1303
1304         return 0;
1305 }
1306
1307 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1308 {
1309         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1310
1311         if (ep->name)
1312                 nuke(ep, -ESHUTDOWN);
1313 }
1314
1315 /*
1316  * ch9 Set address
1317  */
1318 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1319 {
1320         /* Save the new address to device struct */
1321         udc->device_address = (u8) value;
1322         /* Update usb state */
1323         udc->usb_state = USB_STATE_ADDRESS;
1324         /* Status phase */
1325         if (ep0_prime_status(udc, EP_DIR_IN))
1326                 ep0stall(udc);
1327 }
1328
1329 /*
1330  * ch9 Get status
1331  */
1332 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1333                 u16 index, u16 length)
1334 {
1335         u16 tmp = 0;            /* Status, cpu endian */
1336         struct fsl_req *req;
1337         struct fsl_ep *ep;
1338
1339         ep = &udc->eps[0];
1340
1341         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1342                 /* Get device status */
1343                 tmp = 1 << USB_DEVICE_SELF_POWERED;
1344                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1345         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1346                 /* Get interface status */
1347                 /* We don't have interface information in udc driver */
1348                 tmp = 0;
1349         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1350                 /* Get endpoint status */
1351                 struct fsl_ep *target_ep;
1352
1353                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1354
1355                 /* stall if endpoint doesn't exist */
1356                 if (!target_ep->desc)
1357                         goto stall;
1358                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1359                                 << USB_ENDPOINT_HALT;
1360         }
1361
1362         udc->ep0_dir = USB_DIR_IN;
1363         /* Borrow the per device status_req */
1364         req = udc->status_req;
1365         /* Fill in the reqest structure */
1366         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1367
1368         req->ep = ep;
1369         req->req.length = 2;
1370         req->req.status = -EINPROGRESS;
1371         req->req.actual = 0;
1372         req->req.complete = NULL;
1373         req->dtd_count = 0;
1374
1375         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1376                                 req->req.buf, req->req.length,
1377                                 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1378         req->mapped = 1;
1379
1380         /* prime the data phase */
1381         if ((fsl_req_to_dtd(req) == 0))
1382                 fsl_queue_td(ep, req);
1383         else                    /* no mem */
1384                 goto stall;
1385
1386         list_add_tail(&req->queue, &ep->queue);
1387         udc->ep0_state = DATA_STATE_XMIT;
1388         return;
1389 stall:
1390         ep0stall(udc);
1391 }
1392
1393 static void setup_received_irq(struct fsl_udc *udc,
1394                 struct usb_ctrlrequest *setup)
1395 {
1396         u16 wValue = le16_to_cpu(setup->wValue);
1397         u16 wIndex = le16_to_cpu(setup->wIndex);
1398         u16 wLength = le16_to_cpu(setup->wLength);
1399
1400         udc_reset_ep_queue(udc, 0);
1401
1402         /* We process some stardard setup requests here */
1403         switch (setup->bRequest) {
1404         case USB_REQ_GET_STATUS:
1405                 /* Data+Status phase from udc */
1406                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1407                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1408                         break;
1409                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1410                 return;
1411
1412         case USB_REQ_SET_ADDRESS:
1413                 /* Status phase from udc */
1414                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1415                                                 | USB_RECIP_DEVICE))
1416                         break;
1417                 ch9setaddress(udc, wValue, wIndex, wLength);
1418                 return;
1419
1420         case USB_REQ_CLEAR_FEATURE:
1421         case USB_REQ_SET_FEATURE:
1422                 /* Status phase from udc */
1423         {
1424                 int rc = -EOPNOTSUPP;
1425                 u16 ptc = 0;
1426
1427                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1428                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1429                         int pipe = get_pipe_by_windex(wIndex);
1430                         struct fsl_ep *ep;
1431
1432                         if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1433                                 break;
1434                         ep = get_ep_by_pipe(udc, pipe);
1435
1436                         spin_unlock(&udc->lock);
1437                         rc = fsl_ep_set_halt(&ep->ep,
1438                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1439                                                 ? 1 : 0);
1440                         spin_lock(&udc->lock);
1441
1442                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1443                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1444                                 | USB_TYPE_STANDARD)) {
1445                         /* Note: The driver has not include OTG support yet.
1446                          * This will be set when OTG support is added */
1447                         if (wValue == USB_DEVICE_TEST_MODE)
1448                                 ptc = wIndex >> 8;
1449                         else if (gadget_is_otg(&udc->gadget)) {
1450                                 if (setup->bRequest ==
1451                                     USB_DEVICE_B_HNP_ENABLE)
1452                                         udc->gadget.b_hnp_enable = 1;
1453                                 else if (setup->bRequest ==
1454                                          USB_DEVICE_A_HNP_SUPPORT)
1455                                         udc->gadget.a_hnp_support = 1;
1456                                 else if (setup->bRequest ==
1457                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1458                                         udc->gadget.a_alt_hnp_support = 1;
1459                         }
1460                         rc = 0;
1461                 } else
1462                         break;
1463
1464                 if (rc == 0) {
1465                         if (ep0_prime_status(udc, EP_DIR_IN))
1466                                 ep0stall(udc);
1467                 }
1468                 if (ptc) {
1469                         u32 tmp;
1470
1471                         mdelay(10);
1472                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1473                         fsl_writel(tmp, &dr_regs->portsc1);
1474                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1475                 }
1476
1477                 return;
1478         }
1479
1480         default:
1481                 break;
1482         }
1483
1484         /* Requests handled by gadget */
1485         if (wLength) {
1486                 /* Data phase from gadget, status phase from udc */
1487                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1488                                 ?  USB_DIR_IN : USB_DIR_OUT;
1489                 spin_unlock(&udc->lock);
1490                 if (udc->driver->setup(&udc->gadget,
1491                                 &udc->local_setup_buff) < 0)
1492                         ep0stall(udc);
1493                 spin_lock(&udc->lock);
1494                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1495                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1496         } else {
1497                 /* No data phase, IN status from gadget */
1498                 udc->ep0_dir = USB_DIR_IN;
1499                 spin_unlock(&udc->lock);
1500                 if (udc->driver->setup(&udc->gadget,
1501                                 &udc->local_setup_buff) < 0)
1502                         ep0stall(udc);
1503                 spin_lock(&udc->lock);
1504                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1505         }
1506 }
1507
1508 /* Process request for Data or Status phase of ep0
1509  * prime status phase if needed */
1510 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1511                 struct fsl_req *req)
1512 {
1513         if (udc->usb_state == USB_STATE_ADDRESS) {
1514                 /* Set the new address */
1515                 u32 new_address = (u32) udc->device_address;
1516                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1517                                 &dr_regs->deviceaddr);
1518         }
1519
1520         done(ep0, req, 0);
1521
1522         switch (udc->ep0_state) {
1523         case DATA_STATE_XMIT:
1524                 /* receive status phase */
1525                 if (ep0_prime_status(udc, EP_DIR_OUT))
1526                         ep0stall(udc);
1527                 break;
1528         case DATA_STATE_RECV:
1529                 /* send status phase */
1530                 if (ep0_prime_status(udc, EP_DIR_IN))
1531                         ep0stall(udc);
1532                 break;
1533         case WAIT_FOR_OUT_STATUS:
1534                 udc->ep0_state = WAIT_FOR_SETUP;
1535                 break;
1536         case WAIT_FOR_SETUP:
1537                 ERR("Unexpect ep0 packets\n");
1538                 break;
1539         default:
1540                 ep0stall(udc);
1541                 break;
1542         }
1543 }
1544
1545 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1546  * being corrupted by another incoming setup packet */
1547 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1548 {
1549         u32 temp;
1550         struct ep_queue_head *qh;
1551         struct fsl_usb2_platform_data *pdata = udc->pdata;
1552
1553         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1554
1555         /* Clear bit in ENDPTSETUPSTAT */
1556         temp = fsl_readl(&dr_regs->endptsetupstat);
1557         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1558
1559         /* while a hazard exists when setup package arrives */
1560         do {
1561                 /* Set Setup Tripwire */
1562                 temp = fsl_readl(&dr_regs->usbcmd);
1563                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1564
1565                 /* Copy the setup packet to local buffer */
1566                 if (pdata->le_setup_buf) {
1567                         u32 *p = (u32 *)buffer_ptr;
1568                         u32 *s = (u32 *)qh->setup_buffer;
1569
1570                         /* Convert little endian setup buffer to CPU endian */
1571                         *p++ = le32_to_cpu(*s++);
1572                         *p = le32_to_cpu(*s);
1573                 } else {
1574                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1575                 }
1576         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1577
1578         /* Clear Setup Tripwire */
1579         temp = fsl_readl(&dr_regs->usbcmd);
1580         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1581 }
1582
1583 /* process-ep_req(): free the completed Tds for this req */
1584 static int process_ep_req(struct fsl_udc *udc, int pipe,
1585                 struct fsl_req *curr_req)
1586 {
1587         struct ep_td_struct *curr_td;
1588         int     td_complete, actual, remaining_length, j, tmp;
1589         int     status = 0;
1590         int     errors = 0;
1591         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1592         int direction = pipe % 2;
1593
1594         curr_td = curr_req->head;
1595         td_complete = 0;
1596         actual = curr_req->req.length;
1597
1598         for (j = 0; j < curr_req->dtd_count; j++) {
1599                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1600                                         & DTD_PACKET_SIZE)
1601                                 >> DTD_LENGTH_BIT_POS;
1602                 actual -= remaining_length;
1603
1604                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1605                 if (errors & DTD_ERROR_MASK) {
1606                         if (errors & DTD_STATUS_HALTED) {
1607                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1608                                 /* Clear the errors and Halt condition */
1609                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1610                                 tmp &= ~errors;
1611                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1612                                 status = -EPIPE;
1613                                 /* FIXME: continue with next queued TD? */
1614
1615                                 break;
1616                         }
1617                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1618                                 VDBG("Transfer overflow");
1619                                 status = -EPROTO;
1620                                 break;
1621                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1622                                 VDBG("ISO error");
1623                                 status = -EILSEQ;
1624                                 break;
1625                         } else
1626                                 ERR("Unknown error has occurred (0x%x)!\n",
1627                                         errors);
1628
1629                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1630                                 & DTD_STATUS_ACTIVE) {
1631                         VDBG("Request not complete");
1632                         status = REQ_UNCOMPLETE;
1633                         return status;
1634                 } else if (remaining_length) {
1635                         if (direction) {
1636                                 VDBG("Transmit dTD remaining length not zero");
1637                                 status = -EPROTO;
1638                                 break;
1639                         } else {
1640                                 td_complete++;
1641                                 break;
1642                         }
1643                 } else {
1644                         td_complete++;
1645                         VDBG("dTD transmitted successful");
1646                 }
1647
1648                 if (j != curr_req->dtd_count - 1)
1649                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1650         }
1651
1652         if (status)
1653                 return status;
1654
1655         curr_req->req.actual = actual;
1656
1657         return 0;
1658 }
1659
1660 /* Process a DTD completion interrupt */
1661 static void dtd_complete_irq(struct fsl_udc *udc)
1662 {
1663         u32 bit_pos;
1664         int i, ep_num, direction, bit_mask, status;
1665         struct fsl_ep *curr_ep;
1666         struct fsl_req *curr_req, *temp_req;
1667
1668         /* Clear the bits in the register */
1669         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1670         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1671
1672         if (!bit_pos)
1673                 return;
1674
1675         for (i = 0; i < udc->max_ep * 2; i++) {
1676                 ep_num = i >> 1;
1677                 direction = i % 2;
1678
1679                 bit_mask = 1 << (ep_num + 16 * direction);
1680
1681                 if (!(bit_pos & bit_mask))
1682                         continue;
1683
1684                 curr_ep = get_ep_by_pipe(udc, i);
1685
1686                 /* If the ep is configured */
1687                 if (curr_ep->name == NULL) {
1688                         WARNING("Invalid EP?");
1689                         continue;
1690                 }
1691
1692                 /* process the req queue until an uncomplete request */
1693                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1694                                 queue) {
1695                         status = process_ep_req(udc, i, curr_req);
1696
1697                         VDBG("status of process_ep_req= %d, ep = %d",
1698                                         status, ep_num);
1699                         if (status == REQ_UNCOMPLETE)
1700                                 break;
1701                         /* write back status to req */
1702                         curr_req->req.status = status;
1703
1704                         if (ep_num == 0) {
1705                                 ep0_req_complete(udc, curr_ep, curr_req);
1706                                 break;
1707                         } else
1708                                 done(curr_ep, curr_req, status);
1709                 }
1710         }
1711 }
1712
1713 /* Process a port change interrupt */
1714 static void port_change_irq(struct fsl_udc *udc)
1715 {
1716         u32 speed;
1717
1718         if (udc->bus_reset)
1719                 udc->bus_reset = 0;
1720
1721         /* Bus resetting is finished */
1722         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
1723                 /* Get the speed */
1724                 speed = (fsl_readl(&dr_regs->portsc1)
1725                                 & PORTSCX_PORT_SPEED_MASK);
1726                 switch (speed) {
1727                 case PORTSCX_PORT_SPEED_HIGH:
1728                         udc->gadget.speed = USB_SPEED_HIGH;
1729                         break;
1730                 case PORTSCX_PORT_SPEED_FULL:
1731                         udc->gadget.speed = USB_SPEED_FULL;
1732                         break;
1733                 case PORTSCX_PORT_SPEED_LOW:
1734                         udc->gadget.speed = USB_SPEED_LOW;
1735                         break;
1736                 default:
1737                         udc->gadget.speed = USB_SPEED_UNKNOWN;
1738                         break;
1739                 }
1740         }
1741
1742         /* Update USB state */
1743         if (!udc->resume_state)
1744                 udc->usb_state = USB_STATE_DEFAULT;
1745 }
1746
1747 /* Process suspend interrupt */
1748 static void suspend_irq(struct fsl_udc *udc)
1749 {
1750         udc->resume_state = udc->usb_state;
1751         udc->usb_state = USB_STATE_SUSPENDED;
1752
1753         /* report suspend to the driver, serial.c does not support this */
1754         if (udc->driver->suspend)
1755                 udc->driver->suspend(&udc->gadget);
1756 }
1757
1758 static void bus_resume(struct fsl_udc *udc)
1759 {
1760         udc->usb_state = udc->resume_state;
1761         udc->resume_state = 0;
1762
1763         /* report resume to the driver, serial.c does not support this */
1764         if (udc->driver->resume)
1765                 udc->driver->resume(&udc->gadget);
1766 }
1767
1768 /* Clear up all ep queues */
1769 static int reset_queues(struct fsl_udc *udc)
1770 {
1771         u8 pipe;
1772
1773         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1774                 udc_reset_ep_queue(udc, pipe);
1775
1776         /* report disconnect; the driver is already quiesced */
1777         spin_unlock(&udc->lock);
1778         udc->driver->disconnect(&udc->gadget);
1779         spin_lock(&udc->lock);
1780
1781         return 0;
1782 }
1783
1784 /* Process reset interrupt */
1785 static void reset_irq(struct fsl_udc *udc)
1786 {
1787         u32 temp;
1788         unsigned long timeout;
1789
1790         /* Clear the device address */
1791         temp = fsl_readl(&dr_regs->deviceaddr);
1792         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1793
1794         udc->device_address = 0;
1795
1796         /* Clear usb state */
1797         udc->resume_state = 0;
1798         udc->ep0_dir = 0;
1799         udc->ep0_state = WAIT_FOR_SETUP;
1800         udc->remote_wakeup = 0; /* default to 0 on reset */
1801         udc->gadget.b_hnp_enable = 0;
1802         udc->gadget.a_hnp_support = 0;
1803         udc->gadget.a_alt_hnp_support = 0;
1804
1805         /* Clear all the setup token semaphores */
1806         temp = fsl_readl(&dr_regs->endptsetupstat);
1807         fsl_writel(temp, &dr_regs->endptsetupstat);
1808
1809         /* Clear all the endpoint complete status bits */
1810         temp = fsl_readl(&dr_regs->endptcomplete);
1811         fsl_writel(temp, &dr_regs->endptcomplete);
1812
1813         timeout = jiffies + 100;
1814         while (fsl_readl(&dr_regs->endpointprime)) {
1815                 /* Wait until all endptprime bits cleared */
1816                 if (time_after(jiffies, timeout)) {
1817                         ERR("Timeout for reset\n");
1818                         break;
1819                 }
1820                 cpu_relax();
1821         }
1822
1823         /* Write 1s to the flush register */
1824         fsl_writel(0xffffffff, &dr_regs->endptflush);
1825
1826         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1827                 VDBG("Bus reset");
1828                 /* Bus is reseting */
1829                 udc->bus_reset = 1;
1830                 /* Reset all the queues, include XD, dTD, EP queue
1831                  * head and TR Queue */
1832                 reset_queues(udc);
1833                 udc->usb_state = USB_STATE_DEFAULT;
1834         } else {
1835                 VDBG("Controller reset");
1836                 /* initialize usb hw reg except for regs for EP, not
1837                  * touch usbintr reg */
1838                 dr_controller_setup(udc);
1839
1840                 /* Reset all internal used Queues */
1841                 reset_queues(udc);
1842
1843                 ep0_setup(udc);
1844
1845                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1846                 dr_controller_run(udc);
1847                 udc->usb_state = USB_STATE_ATTACHED;
1848         }
1849 }
1850
1851 /*
1852  * USB device controller interrupt handler
1853  */
1854 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1855 {
1856         struct fsl_udc *udc = _udc;
1857         u32 irq_src;
1858         irqreturn_t status = IRQ_NONE;
1859         unsigned long flags;
1860
1861         /* Disable ISR for OTG host mode */
1862         if (udc->stopped)
1863                 return IRQ_NONE;
1864         spin_lock_irqsave(&udc->lock, flags);
1865         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1866         /* Clear notification bits */
1867         fsl_writel(irq_src, &dr_regs->usbsts);
1868
1869         /* VDBG("irq_src [0x%8x]", irq_src); */
1870
1871         /* Need to resume? */
1872         if (udc->usb_state == USB_STATE_SUSPENDED)
1873                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1874                         bus_resume(udc);
1875
1876         /* USB Interrupt */
1877         if (irq_src & USB_STS_INT) {
1878                 VDBG("Packet int");
1879                 /* Setup package, we only support ep0 as control ep */
1880                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1881                         tripwire_handler(udc, 0,
1882                                         (u8 *) (&udc->local_setup_buff));
1883                         setup_received_irq(udc, &udc->local_setup_buff);
1884                         status = IRQ_HANDLED;
1885                 }
1886
1887                 /* completion of dtd */
1888                 if (fsl_readl(&dr_regs->endptcomplete)) {
1889                         dtd_complete_irq(udc);
1890                         status = IRQ_HANDLED;
1891                 }
1892         }
1893
1894         /* SOF (for ISO transfer) */
1895         if (irq_src & USB_STS_SOF) {
1896                 status = IRQ_HANDLED;
1897         }
1898
1899         /* Port Change */
1900         if (irq_src & USB_STS_PORT_CHANGE) {
1901                 port_change_irq(udc);
1902                 status = IRQ_HANDLED;
1903         }
1904
1905         /* Reset Received */
1906         if (irq_src & USB_STS_RESET) {
1907                 VDBG("reset int");
1908                 reset_irq(udc);
1909                 status = IRQ_HANDLED;
1910         }
1911
1912         /* Sleep Enable (Suspend) */
1913         if (irq_src & USB_STS_SUSPEND) {
1914                 suspend_irq(udc);
1915                 status = IRQ_HANDLED;
1916         }
1917
1918         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1919                 VDBG("Error IRQ %x", irq_src);
1920         }
1921
1922         spin_unlock_irqrestore(&udc->lock, flags);
1923         return status;
1924 }
1925
1926 /*----------------------------------------------------------------*
1927  * Hook to gadget drivers
1928  * Called by initialization code of gadget drivers
1929 *----------------------------------------------------------------*/
1930 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1931                 int (*bind)(struct usb_gadget *))
1932 {
1933         int retval = -ENODEV;
1934         unsigned long flags = 0;
1935
1936         if (!udc_controller)
1937                 return -ENODEV;
1938
1939         if (!driver || (driver->speed != USB_SPEED_FULL
1940                                 && driver->speed != USB_SPEED_HIGH)
1941                         || !bind || !driver->disconnect || !driver->setup)
1942                 return -EINVAL;
1943
1944         if (udc_controller->driver)
1945                 return -EBUSY;
1946
1947         /* lock is needed but whether should use this lock or another */
1948         spin_lock_irqsave(&udc_controller->lock, flags);
1949
1950         driver->driver.bus = NULL;
1951         /* hook up the driver */
1952         udc_controller->driver = driver;
1953         udc_controller->gadget.dev.driver = &driver->driver;
1954         spin_unlock_irqrestore(&udc_controller->lock, flags);
1955
1956         /* bind udc driver to gadget driver */
1957         retval = bind(&udc_controller->gadget);
1958         if (retval) {
1959                 VDBG("bind to %s --> %d", driver->driver.name, retval);
1960                 udc_controller->gadget.dev.driver = NULL;
1961                 udc_controller->driver = NULL;
1962                 goto out;
1963         }
1964
1965         if (udc_controller->transceiver) {
1966                 /* Suspend the controller until OTG enable it */
1967                 udc_controller->stopped = 1;
1968                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1969
1970                 /* connect to bus through transceiver */
1971                 if (udc_controller->transceiver) {
1972                         retval = otg_set_peripheral(udc_controller->transceiver,
1973                                                     &udc_controller->gadget);
1974                         if (retval < 0) {
1975                                 ERR("can't bind to transceiver\n");
1976                                 driver->unbind(&udc_controller->gadget);
1977                                 udc_controller->gadget.dev.driver = 0;
1978                                 udc_controller->driver = 0;
1979                                 return retval;
1980                         }
1981                 }
1982         } else {
1983                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1984                 dr_controller_run(udc_controller);
1985                 udc_controller->usb_state = USB_STATE_ATTACHED;
1986                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1987                 udc_controller->ep0_dir = 0;
1988         }
1989         printk(KERN_INFO "%s: bind to driver %s\n",
1990                         udc_controller->gadget.name, driver->driver.name);
1991
1992 out:
1993         if (retval)
1994                 printk(KERN_WARNING "gadget driver register failed %d\n",
1995                        retval);
1996         return retval;
1997 }
1998 EXPORT_SYMBOL(usb_gadget_probe_driver);
1999
2000 /* Disconnect from gadget driver */
2001 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2002 {
2003         struct fsl_ep *loop_ep;
2004         unsigned long flags;
2005
2006         if (!udc_controller)
2007                 return -ENODEV;
2008
2009         if (!driver || driver != udc_controller->driver || !driver->unbind)
2010                 return -EINVAL;
2011
2012         if (udc_controller->transceiver)
2013                 otg_set_peripheral(udc_controller->transceiver, NULL);
2014
2015         /* stop DR, disable intr */
2016         dr_controller_stop(udc_controller);
2017
2018         /* in fact, no needed */
2019         udc_controller->usb_state = USB_STATE_ATTACHED;
2020         udc_controller->ep0_state = WAIT_FOR_SETUP;
2021         udc_controller->ep0_dir = 0;
2022
2023         /* stand operation */
2024         spin_lock_irqsave(&udc_controller->lock, flags);
2025         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2026         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2027         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2028                         ep.ep_list)
2029                 nuke(loop_ep, -ESHUTDOWN);
2030         spin_unlock_irqrestore(&udc_controller->lock, flags);
2031
2032         /* report disconnect; the controller is already quiesced */
2033         driver->disconnect(&udc_controller->gadget);
2034
2035         /* unbind gadget and unhook driver. */
2036         driver->unbind(&udc_controller->gadget);
2037         udc_controller->gadget.dev.driver = NULL;
2038         udc_controller->driver = NULL;
2039
2040         printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2041                driver->driver.name);
2042         return 0;
2043 }
2044 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2045
2046 /*-------------------------------------------------------------------------
2047                 PROC File System Support
2048 -------------------------------------------------------------------------*/
2049 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2050
2051 #include <linux/seq_file.h>
2052
2053 static const char proc_filename[] = "driver/fsl_usb2_udc";
2054
2055 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2056                 int *eof, void *_dev)
2057 {
2058         char *buf = page;
2059         char *next = buf;
2060         unsigned size = count;
2061         unsigned long flags;
2062         int t, i;
2063         u32 tmp_reg;
2064         struct fsl_ep *ep = NULL;
2065         struct fsl_req *req;
2066
2067         struct fsl_udc *udc = udc_controller;
2068         if (off != 0)
2069                 return 0;
2070
2071         spin_lock_irqsave(&udc->lock, flags);
2072
2073         /* ------basic driver information ---- */
2074         t = scnprintf(next, size,
2075                         DRIVER_DESC "\n"
2076                         "%s version: %s\n"
2077                         "Gadget driver: %s\n\n",
2078                         driver_name, DRIVER_VERSION,
2079                         udc->driver ? udc->driver->driver.name : "(none)");
2080         size -= t;
2081         next += t;
2082
2083         /* ------ DR Registers ----- */
2084         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2085         t = scnprintf(next, size,
2086                         "USBCMD reg:\n"
2087                         "SetupTW: %d\n"
2088                         "Run/Stop: %s\n\n",
2089                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2090                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2091         size -= t;
2092         next += t;
2093
2094         tmp_reg = fsl_readl(&dr_regs->usbsts);
2095         t = scnprintf(next, size,
2096                         "USB Status Reg:\n"
2097                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2098                         "USB Error Interrupt: %s\n\n",
2099                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2100                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2101                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2102                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2103         size -= t;
2104         next += t;
2105
2106         tmp_reg = fsl_readl(&dr_regs->usbintr);
2107         t = scnprintf(next, size,
2108                         "USB Intrrupt Enable Reg:\n"
2109                         "Sleep Enable: %d SOF Received Enable: %d "
2110                         "Reset Enable: %d\n"
2111                         "System Error Enable: %d "
2112                         "Port Change Dectected Enable: %d\n"
2113                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2114                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2115                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2116                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2117                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2118                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2119                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2120                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2121         size -= t;
2122         next += t;
2123
2124         tmp_reg = fsl_readl(&dr_regs->frindex);
2125         t = scnprintf(next, size,
2126                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2127                         (tmp_reg & USB_FRINDEX_MASKS));
2128         size -= t;
2129         next += t;
2130
2131         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2132         t = scnprintf(next, size,
2133                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2134                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2135         size -= t;
2136         next += t;
2137
2138         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2139         t = scnprintf(next, size,
2140                         "USB Endpoint List Address Reg: "
2141                         "Device Addr is 0x%x\n\n",
2142                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2143         size -= t;
2144         next += t;
2145
2146         tmp_reg = fsl_readl(&dr_regs->portsc1);
2147         t = scnprintf(next, size,
2148                 "USB Port Status&Control Reg:\n"
2149                 "Port Transceiver Type : %s Port Speed: %s\n"
2150                 "PHY Low Power Suspend: %s Port Reset: %s "
2151                 "Port Suspend Mode: %s\n"
2152                 "Over-current Change: %s "
2153                 "Port Enable/Disable Change: %s\n"
2154                 "Port Enabled/Disabled: %s "
2155                 "Current Connect Status: %s\n\n", ( {
2156                         char *s;
2157                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2158                         case PORTSCX_PTS_UTMI:
2159                                 s = "UTMI"; break;
2160                         case PORTSCX_PTS_ULPI:
2161                                 s = "ULPI "; break;
2162                         case PORTSCX_PTS_FSLS:
2163                                 s = "FS/LS Serial"; break;
2164                         default:
2165                                 s = "None"; break;
2166                         }
2167                         s;} ), ( {
2168                         char *s;
2169                         switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
2170                         case PORTSCX_PORT_SPEED_FULL:
2171                                 s = "Full Speed"; break;
2172                         case PORTSCX_PORT_SPEED_LOW:
2173                                 s = "Low Speed"; break;
2174                         case PORTSCX_PORT_SPEED_HIGH:
2175                                 s = "High Speed"; break;
2176                         default:
2177                                 s = "Undefined"; break;
2178                         }
2179                         s;
2180                 } ),
2181                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2182                 "Normal PHY mode" : "Low power mode",
2183                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2184                 "Not in Reset",
2185                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2186                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2187                 "No",
2188                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2189                 "Not change",
2190                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2191                 "Not correct",
2192                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2193                 "Attached" : "Not-Att");
2194         size -= t;
2195         next += t;
2196
2197         tmp_reg = fsl_readl(&dr_regs->usbmode);
2198         t = scnprintf(next, size,
2199                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2200                                 char *s;
2201                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2202                                 case USB_MODE_CTRL_MODE_IDLE:
2203                                         s = "Idle"; break;
2204                                 case USB_MODE_CTRL_MODE_DEVICE:
2205                                         s = "Device Controller"; break;
2206                                 case USB_MODE_CTRL_MODE_HOST:
2207                                         s = "Host Controller"; break;
2208                                 default:
2209                                         s = "None"; break;
2210                                 }
2211                                 s;
2212                         } ));
2213         size -= t;
2214         next += t;
2215
2216         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2217         t = scnprintf(next, size,
2218                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2219                         (tmp_reg & EP_SETUP_STATUS_MASK));
2220         size -= t;
2221         next += t;
2222
2223         for (i = 0; i < udc->max_ep / 2; i++) {
2224                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2225                 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2226                                 i, tmp_reg);
2227                 size -= t;
2228                 next += t;
2229         }
2230         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2231         t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2232         size -= t;
2233         next += t;
2234
2235 #ifndef CONFIG_ARCH_MXC
2236         if (udc->pdata->have_sysif_regs) {
2237                 tmp_reg = usb_sys_regs->snoop1;
2238                 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2239                 size -= t;
2240                 next += t;
2241
2242                 tmp_reg = usb_sys_regs->control;
2243                 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2244                                 tmp_reg);
2245                 size -= t;
2246                 next += t;
2247         }
2248 #endif
2249
2250         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2251         ep = &udc->eps[0];
2252         t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2253                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2254         size -= t;
2255         next += t;
2256
2257         if (list_empty(&ep->queue)) {
2258                 t = scnprintf(next, size, "its req queue is empty\n\n");
2259                 size -= t;
2260                 next += t;
2261         } else {
2262                 list_for_each_entry(req, &ep->queue, queue) {
2263                         t = scnprintf(next, size,
2264                                 "req %p actual 0x%x length 0x%x buf %p\n",
2265                                 &req->req, req->req.actual,
2266                                 req->req.length, req->req.buf);
2267                         size -= t;
2268                         next += t;
2269                 }
2270         }
2271         /* other gadget->eplist ep */
2272         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2273                 if (ep->desc) {
2274                         t = scnprintf(next, size,
2275                                         "\nFor %s Maxpkt is 0x%x "
2276                                         "index is 0x%x\n",
2277                                         ep->ep.name, ep_maxpacket(ep),
2278                                         ep_index(ep));
2279                         size -= t;
2280                         next += t;
2281
2282                         if (list_empty(&ep->queue)) {
2283                                 t = scnprintf(next, size,
2284                                                 "its req queue is empty\n\n");
2285                                 size -= t;
2286                                 next += t;
2287                         } else {
2288                                 list_for_each_entry(req, &ep->queue, queue) {
2289                                         t = scnprintf(next, size,
2290                                                 "req %p actual 0x%x length "
2291                                                 "0x%x  buf %p\n",
2292                                                 &req->req, req->req.actual,
2293                                                 req->req.length, req->req.buf);
2294                                         size -= t;
2295                                         next += t;
2296                                         }       /* end for each_entry of ep req */
2297                                 }       /* end for else */
2298                         }       /* end for if(ep->queue) */
2299                 }               /* end (ep->desc) */
2300
2301         spin_unlock_irqrestore(&udc->lock, flags);
2302
2303         *eof = 1;
2304         return count - size;
2305 }
2306
2307 #define create_proc_file()      create_proc_read_entry(proc_filename, \
2308                                 0, NULL, fsl_proc_read, NULL)
2309
2310 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2311
2312 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2313
2314 #define create_proc_file()      do {} while (0)
2315 #define remove_proc_file()      do {} while (0)
2316
2317 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2318
2319 /*-------------------------------------------------------------------------*/
2320
2321 /* Release udc structures */
2322 static void fsl_udc_release(struct device *dev)
2323 {
2324         complete(udc_controller->done);
2325         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2326                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2327         kfree(udc_controller);
2328 }
2329
2330 /******************************************************************
2331         Internal structure setup functions
2332 *******************************************************************/
2333 /*------------------------------------------------------------------
2334  * init resource for globle controller
2335  * Return the udc handle on success or NULL on failure
2336  ------------------------------------------------------------------*/
2337 static int __init struct_udc_setup(struct fsl_udc *udc,
2338                 struct platform_device *pdev)
2339 {
2340         struct fsl_usb2_platform_data *pdata;
2341         size_t size;
2342
2343         pdata = pdev->dev.platform_data;
2344         udc->phy_mode = pdata->phy_mode;
2345
2346         udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2347         if (!udc->eps) {
2348                 ERR("malloc fsl_ep failed\n");
2349                 return -1;
2350         }
2351
2352         /* initialized QHs, take care of alignment */
2353         size = udc->max_ep * sizeof(struct ep_queue_head);
2354         if (size < QH_ALIGNMENT)
2355                 size = QH_ALIGNMENT;
2356         else if ((size % QH_ALIGNMENT) != 0) {
2357                 size += QH_ALIGNMENT + 1;
2358                 size &= ~(QH_ALIGNMENT - 1);
2359         }
2360         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2361                                         &udc->ep_qh_dma, GFP_KERNEL);
2362         if (!udc->ep_qh) {
2363                 ERR("malloc QHs for udc failed\n");
2364                 kfree(udc->eps);
2365                 return -1;
2366         }
2367
2368         udc->ep_qh_size = size;
2369
2370         /* Initialize ep0 status request structure */
2371         /* FIXME: fsl_alloc_request() ignores ep argument */
2372         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2373                         struct fsl_req, req);
2374         /* allocate a small amount of memory to get valid address */
2375         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2376
2377         udc->resume_state = USB_STATE_NOTATTACHED;
2378         udc->usb_state = USB_STATE_POWERED;
2379         udc->ep0_dir = 0;
2380         udc->remote_wakeup = 0; /* default to 0 on reset */
2381
2382         return 0;
2383 }
2384
2385 /*----------------------------------------------------------------
2386  * Setup the fsl_ep struct for eps
2387  * Link fsl_ep->ep to gadget->ep_list
2388  * ep0out is not used so do nothing here
2389  * ep0in should be taken care
2390  *--------------------------------------------------------------*/
2391 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2392                 char *name, int link)
2393 {
2394         struct fsl_ep *ep = &udc->eps[index];
2395
2396         ep->udc = udc;
2397         strcpy(ep->name, name);
2398         ep->ep.name = ep->name;
2399
2400         ep->ep.ops = &fsl_ep_ops;
2401         ep->stopped = 0;
2402
2403         /* for ep0: maxP defined in desc
2404          * for other eps, maxP is set by epautoconfig() called by gadget layer
2405          */
2406         ep->ep.maxpacket = (unsigned short) ~0;
2407
2408         /* the queue lists any req for this ep */
2409         INIT_LIST_HEAD(&ep->queue);
2410
2411         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2412         if (link)
2413                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2414         ep->gadget = &udc->gadget;
2415         ep->qh = &udc->ep_qh[index];
2416
2417         return 0;
2418 }
2419
2420 /* Driver probe function
2421  * all intialization operations implemented here except enabling usb_intr reg
2422  * board setup should have been done in the platform code
2423  */
2424 static int __init fsl_udc_probe(struct platform_device *pdev)
2425 {
2426         struct fsl_usb2_platform_data *pdata;
2427         struct resource *res;
2428         int ret = -ENODEV;
2429         unsigned int i;
2430         u32 dccparams;
2431
2432         if (strcmp(pdev->name, driver_name)) {
2433                 VDBG("Wrong device");
2434                 return -ENODEV;
2435         }
2436
2437         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2438         if (udc_controller == NULL) {
2439                 ERR("malloc udc failed\n");
2440                 return -ENOMEM;
2441         }
2442
2443         pdata = pdev->dev.platform_data;
2444         udc_controller->pdata = pdata;
2445         spin_lock_init(&udc_controller->lock);
2446         udc_controller->stopped = 1;
2447
2448 #ifdef CONFIG_USB_OTG
2449         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2450                 udc_controller->transceiver = otg_get_transceiver();
2451                 if (!udc_controller->transceiver) {
2452                         ERR("Can't find OTG driver!\n");
2453                         ret = -ENODEV;
2454                         goto err_kfree;
2455                 }
2456         }
2457 #endif
2458
2459         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2460         if (!res) {
2461                 ret = -ENXIO;
2462                 goto err_kfree;
2463         }
2464
2465         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2466                 if (!request_mem_region(res->start, res->end - res->start + 1,
2467                                         driver_name)) {
2468                         ERR("request mem region for %s failed\n", pdev->name);
2469                         ret = -EBUSY;
2470                         goto err_kfree;
2471                 }
2472         }
2473
2474         dr_regs = ioremap(res->start, resource_size(res));
2475         if (!dr_regs) {
2476                 ret = -ENOMEM;
2477                 goto err_release_mem_region;
2478         }
2479
2480         pdata->regs = (void *)dr_regs;
2481
2482         /*
2483          * do platform specific init: check the clock, grab/config pins, etc.
2484          */
2485         if (pdata->init && pdata->init(pdev)) {
2486                 ret = -ENODEV;
2487                 goto err_iounmap_noclk;
2488         }
2489
2490         /* Set accessors only after pdata->init() ! */
2491         fsl_set_accessors(pdata);
2492
2493 #ifndef CONFIG_ARCH_MXC
2494         if (pdata->have_sysif_regs)
2495                 usb_sys_regs = (struct usb_sys_interface *)
2496                                 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2497 #endif
2498
2499         /* Initialize USB clocks */
2500         ret = fsl_udc_clk_init(pdev);
2501         if (ret < 0)
2502                 goto err_iounmap_noclk;
2503
2504         /* Read Device Controller Capability Parameters register */
2505         dccparams = fsl_readl(&dr_regs->dccparams);
2506         if (!(dccparams & DCCPARAMS_DC)) {
2507                 ERR("This SOC doesn't support device role\n");
2508                 ret = -ENODEV;
2509                 goto err_iounmap;
2510         }
2511         /* Get max device endpoints */
2512         /* DEN is bidirectional ep number, max_ep doubles the number */
2513         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2514
2515         udc_controller->irq = platform_get_irq(pdev, 0);
2516         if (!udc_controller->irq) {
2517                 ret = -ENODEV;
2518                 goto err_iounmap;
2519         }
2520
2521         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2522                         driver_name, udc_controller);
2523         if (ret != 0) {
2524                 ERR("cannot request irq %d err %d\n",
2525                                 udc_controller->irq, ret);
2526                 goto err_iounmap;
2527         }
2528
2529         /* Initialize the udc structure including QH member and other member */
2530         if (struct_udc_setup(udc_controller, pdev)) {
2531                 ERR("Can't initialize udc data structure\n");
2532                 ret = -ENOMEM;
2533                 goto err_free_irq;
2534         }
2535
2536         if (!udc_controller->transceiver) {
2537                 /* initialize usb hw reg except for regs for EP,
2538                  * leave usbintr reg untouched */
2539                 dr_controller_setup(udc_controller);
2540         }
2541
2542         fsl_udc_clk_finalize(pdev);
2543
2544         /* Setup gadget structure */
2545         udc_controller->gadget.ops = &fsl_gadget_ops;
2546         udc_controller->gadget.is_dualspeed = 1;
2547         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2548         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2549         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2550         udc_controller->gadget.name = driver_name;
2551
2552         /* Setup gadget.dev and register with kernel */
2553         dev_set_name(&udc_controller->gadget.dev, "gadget");
2554         udc_controller->gadget.dev.release = fsl_udc_release;
2555         udc_controller->gadget.dev.parent = &pdev->dev;
2556         ret = device_register(&udc_controller->gadget.dev);
2557         if (ret < 0)
2558                 goto err_free_irq;
2559
2560         if (udc_controller->transceiver)
2561                 udc_controller->gadget.is_otg = 1;
2562
2563         /* setup QH and epctrl for ep0 */
2564         ep0_setup(udc_controller);
2565
2566         /* setup udc->eps[] for ep0 */
2567         struct_ep_setup(udc_controller, 0, "ep0", 0);
2568         /* for ep0: the desc defined here;
2569          * for other eps, gadget layer called ep_enable with defined desc
2570          */
2571         udc_controller->eps[0].desc = &fsl_ep0_desc;
2572         udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2573
2574         /* setup the udc->eps[] for non-control endpoints and link
2575          * to gadget.ep_list */
2576         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2577                 char name[14];
2578
2579                 sprintf(name, "ep%dout", i);
2580                 struct_ep_setup(udc_controller, i * 2, name, 1);
2581                 sprintf(name, "ep%din", i);
2582                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2583         }
2584
2585         /* use dma_pool for TD management */
2586         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2587                         sizeof(struct ep_td_struct),
2588                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2589         if (udc_controller->td_pool == NULL) {
2590                 ret = -ENOMEM;
2591                 goto err_unregister;
2592         }
2593         create_proc_file();
2594         return 0;
2595
2596 err_unregister:
2597         device_unregister(&udc_controller->gadget.dev);
2598 err_free_irq:
2599         free_irq(udc_controller->irq, udc_controller);
2600 err_iounmap:
2601         if (pdata->exit)
2602                 pdata->exit(pdev);
2603         fsl_udc_clk_release();
2604 err_iounmap_noclk:
2605         iounmap(dr_regs);
2606 err_release_mem_region:
2607         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2608                 release_mem_region(res->start, res->end - res->start + 1);
2609 err_kfree:
2610         kfree(udc_controller);
2611         udc_controller = NULL;
2612         return ret;
2613 }
2614
2615 /* Driver removal function
2616  * Free resources and finish pending transactions
2617  */
2618 static int __exit fsl_udc_remove(struct platform_device *pdev)
2619 {
2620         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2621         struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2622
2623         DECLARE_COMPLETION(done);
2624
2625         if (!udc_controller)
2626                 return -ENODEV;
2627         udc_controller->done = &done;
2628
2629         fsl_udc_clk_release();
2630
2631         /* DR has been stopped in usb_gadget_unregister_driver() */
2632         remove_proc_file();
2633
2634         /* Free allocated memory */
2635         kfree(udc_controller->status_req->req.buf);
2636         kfree(udc_controller->status_req);
2637         kfree(udc_controller->eps);
2638
2639         dma_pool_destroy(udc_controller->td_pool);
2640         free_irq(udc_controller->irq, udc_controller);
2641         iounmap(dr_regs);
2642         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2643                 release_mem_region(res->start, res->end - res->start + 1);
2644
2645         device_unregister(&udc_controller->gadget.dev);
2646         /* free udc --wait for the release() finished */
2647         wait_for_completion(&done);
2648
2649         /*
2650          * do platform specific un-initialization:
2651          * release iomux pins, etc.
2652          */
2653         if (pdata->exit)
2654                 pdata->exit(pdev);
2655
2656         return 0;
2657 }
2658
2659 /*-----------------------------------------------------------------
2660  * Modify Power management attributes
2661  * Used by OTG statemachine to disable gadget temporarily
2662  -----------------------------------------------------------------*/
2663 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2664 {
2665         dr_controller_stop(udc_controller);
2666         return 0;
2667 }
2668
2669 /*-----------------------------------------------------------------
2670  * Invoked on USB resume. May be called in_interrupt.
2671  * Here we start the DR controller and enable the irq
2672  *-----------------------------------------------------------------*/
2673 static int fsl_udc_resume(struct platform_device *pdev)
2674 {
2675         /* Enable DR irq reg and set controller Run */
2676         if (udc_controller->stopped) {
2677                 dr_controller_setup(udc_controller);
2678                 dr_controller_run(udc_controller);
2679         }
2680         udc_controller->usb_state = USB_STATE_ATTACHED;
2681         udc_controller->ep0_state = WAIT_FOR_SETUP;
2682         udc_controller->ep0_dir = 0;
2683         return 0;
2684 }
2685
2686 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2687 {
2688         struct fsl_udc *udc = udc_controller;
2689         u32 mode, usbcmd;
2690
2691         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2692
2693         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2694
2695         /*
2696          * If the controller is already stopped, then this must be a
2697          * PM suspend.  Remember this fact, so that we will leave the
2698          * controller stopped at PM resume time.
2699          */
2700         if (udc->stopped) {
2701                 pr_debug("gadget already stopped, leaving early\n");
2702                 udc->already_stopped = 1;
2703                 return 0;
2704         }
2705
2706         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2707                 pr_debug("gadget not in device mode, leaving early\n");
2708                 return 0;
2709         }
2710
2711         /* stop the controller */
2712         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2713         fsl_writel(usbcmd, &dr_regs->usbcmd);
2714
2715         udc->stopped = 1;
2716
2717         pr_info("USB Gadget suspended\n");
2718
2719         return 0;
2720 }
2721
2722 static int fsl_udc_otg_resume(struct device *dev)
2723 {
2724         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2725                  udc_controller->stopped, udc_controller->already_stopped);
2726
2727         /*
2728          * If the controller was stopped at suspend time, then
2729          * don't resume it now.
2730          */
2731         if (udc_controller->already_stopped) {
2732                 udc_controller->already_stopped = 0;
2733                 pr_debug("gadget was already stopped, leaving early\n");
2734                 return 0;
2735         }
2736
2737         pr_info("USB Gadget resume\n");
2738
2739         return fsl_udc_resume(NULL);
2740 }
2741
2742 /*-------------------------------------------------------------------------
2743         Register entry point for the peripheral controller driver
2744 --------------------------------------------------------------------------*/
2745
2746 static struct platform_driver udc_driver = {
2747         .remove  = __exit_p(fsl_udc_remove),
2748         /* these suspend and resume are not usb suspend and resume */
2749         .suspend = fsl_udc_suspend,
2750         .resume  = fsl_udc_resume,
2751         .driver  = {
2752                 .name = (char *)driver_name,
2753                 .owner = THIS_MODULE,
2754                 /* udc suspend/resume called from OTG driver */
2755                 .suspend = fsl_udc_otg_suspend,
2756                 .resume  = fsl_udc_otg_resume,
2757         },
2758 };
2759
2760 static int __init udc_init(void)
2761 {
2762         printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2763         return platform_driver_probe(&udc_driver, fsl_udc_probe);
2764 }
2765
2766 module_init(udc_init);
2767
2768 static void __exit udc_exit(void)
2769 {
2770         platform_driver_unregister(&udc_driver);
2771         printk(KERN_WARNING "%s unregistered\n", driver_desc);
2772 }
2773
2774 module_exit(udc_exit);
2775
2776 MODULE_DESCRIPTION(DRIVER_DESC);
2777 MODULE_AUTHOR(DRIVER_AUTHOR);
2778 MODULE_LICENSE("GPL");
2779 MODULE_ALIAS("platform:fsl-usb2-udc");