drivers/usb/gadget/fsl_udc_core.c

   1 /*
   2  * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Author: Li Yang <leoli@freescale.com>
   6  *         Jiang Bo <tanya.jiang@freescale.com>
   7  *
   8  * Description:
   9  * Freescale high-speed USB SOC DR module device controller driver.
  10  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  11  * The driver is previously named as mpc_udc.  Based on bare board
  12  * code from Dave Liu and Shlomi Gridish.
  13  *
  14  * This program is free software; you can redistribute  it and/or modify it
  15  * under  the terms of  the GNU General  Public License as published by the
  16  * Free Software Foundation;  either version 2 of the  License, or (at your
  17  * option) any later version.
  18  */
  19
  20 #undef VERBOSE
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/ioport.h>
  25 #include <linux/types.h>
  26 #include <linux/errno.h>
  27 #include <linux/slab.h>
  28 #include <linux/init.h>
  29 #include <linux/list.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/proc_fs.h>
  32 #include <linux/mm.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include <linux/usb/ch9.h>
  36 #include <linux/usb/gadget.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/fsl_devices.h>
  41 #include <linux/dmapool.h>
  42 #include <linux/delay.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/io.h>
  46 #include <asm/system.h>
  47 #include <asm/unaligned.h>
  48 #include <asm/dma.h>
  49 #include <asm/cacheflush.h>
  50
  51 #include "fsl_usb2_udc.h"
  52
  53 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  54 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  55 #define DRIVER_VERSION  "Apr 20, 2007"
  56
  57 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  58
  59 static const char driver_name[] = "fsl-usb2-udc";
  60 static const char driver_desc[] = DRIVER_DESC;
  61
  62 static struct usb_dr_device *dr_regs;
  63 #ifndef CONFIG_ARCH_MXC
  64 static struct usb_sys_interface *usb_sys_regs;
  65 #endif
  66
  67 /* it is initialized in probe()  */
  68 static struct fsl_udc *udc_controller = NULL;
  69
  70 static const struct usb_endpoint_descriptor
  71 fsl_ep0_desc = {
  72         .bLength =              USB_DT_ENDPOINT_SIZE,
  73         .bDescriptorType =      USB_DT_ENDPOINT,
  74         .bEndpointAddress =     0,
  75         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  76         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  77 };
  78
  79 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  80
  81 #ifdef CONFIG_PPC32
  82 /*
  83  * On some SoCs, the USB controller registers can be big or little endian,
  84  * depending on the version of the chip. In order to be able to run the
  85  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  86  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  87  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  88  * call through those pointers. Platform code for SoCs that have BE USB
  89  * registers should set pdata->big_endian_mmio flag.
  90  *
  91  * This also applies to controller-to-cpu accessors for the USB descriptors,
  92  * since their endianness is also SoC dependant. Platform code for SoCs that
  93  * have BE USB descriptors should set pdata->big_endian_desc flag.
  94  */
  95 static u32 _fsl_readl_be(const unsigned __iomem *p)
  96 {
  97         return in_be32(p);
  98 }
  99
 100 static u32 _fsl_readl_le(const unsigned __iomem *p)
 101 {
 102         return in_le32(p);
 103 }
 104
 105 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
 106 {
 107         out_be32(p, v);
 108 }
 109
 110 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 111 {
 112         out_le32(p, v);
 113 }
 114
 115 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 116 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 117
 118 #define fsl_readl(p)            (*_fsl_readl)((p))
 119 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 120
 121 static inline u32 cpu_to_hc32(const u32 x)
 122 {
 123         return udc_controller->pdata->big_endian_desc
 124                 ? (__force u32)cpu_to_be32(x)
 125                 : (__force u32)cpu_to_le32(x);
 126 }
 127
 128 static inline u32 hc32_to_cpu(const u32 x)
 129 {
 130         return udc_controller->pdata->big_endian_desc
 131                 ? be32_to_cpu((__force __be32)x)
 132                 : le32_to_cpu((__force __le32)x);
 133 }
 134 #else /* !CONFIG_PPC32 */
 135 #define fsl_readl(addr)         readl(addr)
 136 #define fsl_writel(val32, addr) writel(val32, addr)
 137 #define cpu_to_hc32(x)          cpu_to_le32(x)
 138 #define hc32_to_cpu(x)          le32_to_cpu(x)
 139 #endif /* CONFIG_PPC32 */
 140
 141 /********************************************************************
 142  *      Internal Used Function
 143 ********************************************************************/
 144 /*-----------------------------------------------------------------
 145  * done() - retire a request; caller blocked irqs
 146  * @status : request status to be set, only works when
 147  *      request is still in progress.
 148  *--------------------------------------------------------------*/
 149 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 150 {
 151         struct fsl_udc *udc = NULL;
 152         unsigned char stopped = ep->stopped;
 153         struct ep_td_struct *curr_td, *next_td;
 154         int j;
 155
 156         udc = (struct fsl_udc *)ep->udc;
 157         /* Removed the req from fsl_ep->queue */
 158         list_del_init(&req->queue);
 159
 160         /* req.status should be set as -EINPROGRESS in ep_queue() */
 161         if (req->req.status == -EINPROGRESS)
 162                 req->req.status = status;
 163         else
 164                 status = req->req.status;
 165
 166         /* Free dtd for the request */
 167         next_td = req->head;
 168         for (j = 0; j < req->dtd_count; j++) {
 169                 curr_td = next_td;
 170                 if (j != req->dtd_count - 1) {
 171                         next_td = curr_td->next_td_virt;
 172                 }
 173                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 174         }
 175
 176         if (req->mapped) {
 177                 dma_unmap_single(ep->udc->gadget.dev.parent,
 178                         req->req.dma, req->req.length,
 179                         ep_is_in(ep)
 180                                 ? DMA_TO_DEVICE
 181                                 : DMA_FROM_DEVICE);
 182                 req->req.dma = DMA_ADDR_INVALID;
 183                 req->mapped = 0;
 184         } else
 185                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 186                         req->req.dma, req->req.length,
 187                         ep_is_in(ep)
 188                                 ? DMA_TO_DEVICE
 189                                 : DMA_FROM_DEVICE);
 190
 191         if (status && (status != -ESHUTDOWN))
 192                 VDBG("complete %s req %p stat %d len %u/%u",
 193                         ep->ep.name, &req->req, status,
 194                         req->req.actual, req->req.length);
 195
 196         ep->stopped = 1;
 197
 198         spin_unlock(&ep->udc->lock);
 199         /* complete() is from gadget layer,
 200          * eg fsg->bulk_in_complete() */
 201         if (req->req.complete)
 202                 req->req.complete(&ep->ep, &req->req);
 203
 204         spin_lock(&ep->udc->lock);
 205         ep->stopped = stopped;
 206 }
 207
 208 /*-----------------------------------------------------------------
 209  * nuke(): delete all requests related to this ep
 210  * called with spinlock held
 211  *--------------------------------------------------------------*/
 212 static void nuke(struct fsl_ep *ep, int status)
 213 {
 214         ep->stopped = 1;
 215
 216         /* Flush fifo */
 217         fsl_ep_fifo_flush(&ep->ep);
 218
 219         /* Whether this eq has request linked */
 220         while (!list_empty(&ep->queue)) {
 221                 struct fsl_req *req = NULL;
 222
 223                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 224                 done(ep, req, status);
 225         }
 226 }
 227
 228 /*------------------------------------------------------------------
 229         Internal Hardware related function
 230  ------------------------------------------------------------------*/
 231
 232 static int dr_controller_setup(struct fsl_udc *udc)
 233 {
 234         unsigned int tmp, portctrl, ep_num;
 235         unsigned int max_no_of_ep;
 236 #ifndef CONFIG_ARCH_MXC
 237         unsigned int ctrl;
 238 #endif
 239         unsigned long timeout;
 240 #define FSL_UDC_RESET_TIMEOUT 1000
 241
 242         /* Config PHY interface */
 243         portctrl = fsl_readl(&dr_regs->portsc1);
 244         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 245         switch (udc->phy_mode) {
 246         case FSL_USB2_PHY_ULPI:
 247                 portctrl |= PORTSCX_PTS_ULPI;
 248                 break;
 249         case FSL_USB2_PHY_UTMI_WIDE:
 250                 portctrl |= PORTSCX_PTW_16BIT;
 251                 /* fall through */
 252         case FSL_USB2_PHY_UTMI:
 253                 portctrl |= PORTSCX_PTS_UTMI;
 254                 break;
 255         case FSL_USB2_PHY_SERIAL:
 256                 portctrl |= PORTSCX_PTS_FSLS;
 257                 break;
 258         default:
 259                 return -EINVAL;
 260         }
 261         fsl_writel(portctrl, &dr_regs->portsc1);
 262
 263         /* Stop and reset the usb controller */
 264         tmp = fsl_readl(&dr_regs->usbcmd);
 265         tmp &= ~USB_CMD_RUN_STOP;
 266         fsl_writel(tmp, &dr_regs->usbcmd);
 267
 268         tmp = fsl_readl(&dr_regs->usbcmd);
 269         tmp |= USB_CMD_CTRL_RESET;
 270         fsl_writel(tmp, &dr_regs->usbcmd);
 271
 272         /* Wait for reset to complete */
 273         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 274         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 275                 if (time_after(jiffies, timeout)) {
 276                         ERR("udc reset timeout!\n");
 277                         return -ETIMEDOUT;
 278                 }
 279                 cpu_relax();
 280         }
 281
 282         /* Set the controller as device mode */
 283         tmp = fsl_readl(&dr_regs->usbmode);
 284         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 285         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 286         /* Disable Setup Lockout */
 287         tmp |= USB_MODE_SETUP_LOCK_OFF;
 288         if (udc->pdata->es)
 289                 tmp |= USB_MODE_ES;
 290         fsl_writel(tmp, &dr_regs->usbmode);
 291
 292         /* Clear the setup status */
 293         fsl_writel(0, &dr_regs->usbsts);
 294
 295         tmp = udc->ep_qh_dma;
 296         tmp &= USB_EP_LIST_ADDRESS_MASK;
 297         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 298
 299         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 300                 udc->ep_qh, (int)tmp,
 301                 fsl_readl(&dr_regs->endpointlistaddr));
 302
 303         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 304         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 305                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 306                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 307                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 308                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 309                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 310         }
 311         /* Config control enable i/o output, cpu endian register */
 312 #ifndef CONFIG_ARCH_MXC
 313         if (udc->pdata->have_sysif_regs) {
 314                 ctrl = __raw_readl(&usb_sys_regs->control);
 315                 ctrl |= USB_CTRL_IOENB;
 316                 __raw_writel(ctrl, &usb_sys_regs->control);
 317         }
 318 #endif
 319
 320 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 321         /* Turn on cache snooping hardware, since some PowerPC platforms
 322          * wholly rely on hardware to deal with cache coherent. */
 323
 324         if (udc->pdata->have_sysif_regs) {
 325                 /* Setup Snooping for all the 4GB space */
 326                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 327                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 328                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 329                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 330         }
 331 #endif
 332
 333         return 0;
 334 }
 335
 336 /* Enable DR irq and set controller to run state */
 337 static void dr_controller_run(struct fsl_udc *udc)
 338 {
 339         u32 temp;
 340
 341         /* Enable DR irq reg */
 342         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 343                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 344                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 345
 346         fsl_writel(temp, &dr_regs->usbintr);
 347
 348         /* Clear stopped bit */
 349         udc->stopped = 0;
 350
 351         /* Set the controller as device mode */
 352         temp = fsl_readl(&dr_regs->usbmode);
 353         temp |= USB_MODE_CTRL_MODE_DEVICE;
 354         fsl_writel(temp, &dr_regs->usbmode);
 355
 356         /* Set controller to Run */
 357         temp = fsl_readl(&dr_regs->usbcmd);
 358         temp |= USB_CMD_RUN_STOP;
 359         fsl_writel(temp, &dr_regs->usbcmd);
 360 }
 361
 362 static void dr_controller_stop(struct fsl_udc *udc)
 363 {
 364         unsigned int tmp;
 365
 366         pr_debug("%s\n", __func__);
 367
 368         /* if we're in OTG mode, and the Host is currently using the port,
 369          * stop now and don't rip the controller out from under the
 370          * ehci driver
 371          */
 372         if (udc->gadget.is_otg) {
 373                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 374                         pr_debug("udc: Leaving early\n");
 375                         return;
 376                 }
 377         }
 378
 379         /* disable all INTR */
 380         fsl_writel(0, &dr_regs->usbintr);
 381
 382         /* Set stopped bit for isr */
 383         udc->stopped = 1;
 384
 385         /* disable IO output */
 386 /*      usb_sys_regs->control = 0; */
 387
 388         /* set controller to Stop */
 389         tmp = fsl_readl(&dr_regs->usbcmd);
 390         tmp &= ~USB_CMD_RUN_STOP;
 391         fsl_writel(tmp, &dr_regs->usbcmd);
 392 }
 393
 394 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 395                         unsigned char ep_type)
 396 {
 397         unsigned int tmp_epctrl = 0;
 398
 399         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 400         if (dir) {
 401                 if (ep_num)
 402                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 403                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 404                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 405                 tmp_epctrl |= ((unsigned int)(ep_type)
 406                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 407         } else {
 408                 if (ep_num)
 409                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 410                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 411                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 412                 tmp_epctrl |= ((unsigned int)(ep_type)
 413                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 414         }
 415
 416         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 417 }
 418
 419 static void
 420 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 421 {
 422         u32 tmp_epctrl = 0;
 423
 424         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 425
 426         if (value) {
 427                 /* set the stall bit */
 428                 if (dir)
 429                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 430                 else
 431                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 432         } else {
 433                 /* clear the stall bit and reset data toggle */
 434                 if (dir) {
 435                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 436                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 437                 } else {
 438                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 439                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 440                 }
 441         }
 442         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 443 }
 444
 445 /* Get stall status of a specific ep
 446    Return: 0: not stalled; 1:stalled */
 447 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 448 {
 449         u32 epctrl;
 450
 451         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 452         if (dir)
 453                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 454         else
 455                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 456 }
 457
 458 /********************************************************************
 459         Internal Structure Build up functions
 460 ********************************************************************/
 461
 462 /*------------------------------------------------------------------
 463 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 464  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 465  * @mult: Mult field
 466  ------------------------------------------------------------------*/
 467 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 468                 unsigned char dir, unsigned char ep_type,
 469                 unsigned int max_pkt_len,
 470                 unsigned int zlt, unsigned char mult)
 471 {
 472         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 473         unsigned int tmp = 0;
 474
 475         /* set the Endpoint Capabilites in QH */
 476         switch (ep_type) {
 477         case USB_ENDPOINT_XFER_CONTROL:
 478                 /* Interrupt On Setup (IOS). for control ep  */
 479                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 480                         | EP_QUEUE_HEAD_IOS;
 481                 break;
 482         case USB_ENDPOINT_XFER_ISOC:
 483                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 484                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 485                 break;
 486         case USB_ENDPOINT_XFER_BULK:
 487         case USB_ENDPOINT_XFER_INT:
 488                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 489                 break;
 490         default:
 491                 VDBG("error ep type is %d", ep_type);
 492                 return;
 493         }
 494         if (zlt)
 495                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 496
 497         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 498         p_QH->next_dtd_ptr = 1;
 499         p_QH->size_ioc_int_sts = 0;
 500 }
 501
 502 /* Setup qh structure and ep register for ep0. */
 503 static void ep0_setup(struct fsl_udc *udc)
 504 {
 505         /* the intialization of an ep includes: fields in QH, Regs,
 506          * fsl_ep struct */
 507         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 508                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 509         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 510                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 511         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 512         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 513
 514         return;
 515
 516 }
 517
 518 /***********************************************************************
 519                 Endpoint Management Functions
 520 ***********************************************************************/
 521
 522 /*-------------------------------------------------------------------------
 523  * when configurations are set, or when interface settings change
 524  * for example the do_set_interface() in gadget layer,
 525  * the driver will enable or disable the relevant endpoints
 526  * ep0 doesn't use this routine. It is always enabled.
 527 -------------------------------------------------------------------------*/
 528 static int fsl_ep_enable(struct usb_ep *_ep,
 529                 const struct usb_endpoint_descriptor *desc)
 530 {
 531         struct fsl_udc *udc = NULL;
 532         struct fsl_ep *ep = NULL;
 533         unsigned short max = 0;
 534         unsigned char mult = 0, zlt;
 535         int retval = -EINVAL;
 536         unsigned long flags = 0;
 537
 538         ep = container_of(_ep, struct fsl_ep, ep);
 539
 540         /* catch various bogus parameters */
 541         if (!_ep || !desc || ep->desc
 542                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 543                 return -EINVAL;
 544
 545         udc = ep->udc;
 546
 547         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 548                 return -ESHUTDOWN;
 549
 550         max = le16_to_cpu(desc->wMaxPacketSize);
 551
 552         /* Disable automatic zlp generation.  Driver is responsible to indicate
 553          * explicitly through req->req.zero.  This is needed to enable multi-td
 554          * request. */
 555         zlt = 1;
 556
 557         /* Assume the max packet size from gadget is always correct */
 558         switch (desc->bmAttributes & 0x03) {
 559         case USB_ENDPOINT_XFER_CONTROL:
 560         case USB_ENDPOINT_XFER_BULK:
 561         case USB_ENDPOINT_XFER_INT:
 562                 /* mult = 0.  Execute N Transactions as demonstrated by
 563                  * the USB variable length packet protocol where N is
 564                  * computed using the Maximum Packet Length (dQH) and
 565                  * the Total Bytes field (dTD) */
 566                 mult = 0;
 567                 break;
 568         case USB_ENDPOINT_XFER_ISOC:
 569                 /* Calculate transactions needed for high bandwidth iso */
 570                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 571                 max = max & 0x7ff;      /* bit 0~10 */
 572                 /* 3 transactions at most */
 573                 if (mult > 3)
 574                         goto en_done;
 575                 break;
 576         default:
 577                 goto en_done;
 578         }
 579
 580         spin_lock_irqsave(&udc->lock, flags);
 581         ep->ep.maxpacket = max;
 582         ep->desc = desc;
 583         ep->stopped = 0;
 584
 585         /* Controller related setup */
 586         /* Init EPx Queue Head (Ep Capabilites field in QH
 587          * according to max, zlt, mult) */
 588         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 589                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 590                                         ?  USB_SEND : USB_RECV),
 591                         (unsigned char) (desc->bmAttributes
 592                                         & USB_ENDPOINT_XFERTYPE_MASK),
 593                         max, zlt, mult);
 594
 595         /* Init endpoint ctrl register */
 596         dr_ep_setup((unsigned char) ep_index(ep),
 597                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 598                                         ? USB_SEND : USB_RECV),
 599                         (unsigned char) (desc->bmAttributes
 600                                         & USB_ENDPOINT_XFERTYPE_MASK));
 601
 602         spin_unlock_irqrestore(&udc->lock, flags);
 603         retval = 0;
 604
 605         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 606                         ep->desc->bEndpointAddress & 0x0f,
 607                         (desc->bEndpointAddress & USB_DIR_IN)
 608                                 ? "in" : "out", max);
 609 en_done:
 610         return retval;
 611 }
 612
 613 /*---------------------------------------------------------------------
 614  * @ep : the ep being unconfigured. May not be ep0
 615  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 616 *---------------------------------------------------------------------*/
 617 static int fsl_ep_disable(struct usb_ep *_ep)
 618 {
 619         struct fsl_udc *udc = NULL;
 620         struct fsl_ep *ep = NULL;
 621         unsigned long flags = 0;
 622         u32 epctrl;
 623         int ep_num;
 624
 625         ep = container_of(_ep, struct fsl_ep, ep);
 626         if (!_ep || !ep->desc) {
 627                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 628                 return -EINVAL;
 629         }
 630
 631         /* disable ep on controller */
 632         ep_num = ep_index(ep);
 633         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 634         if (ep_is_in(ep)) {
 635                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 636                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 637         } else {
 638                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 639                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 640         }
 641         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 642
 643         udc = (struct fsl_udc *)ep->udc;
 644         spin_lock_irqsave(&udc->lock, flags);
 645
 646         /* nuke all pending requests (does flush) */
 647         nuke(ep, -ESHUTDOWN);
 648
 649         ep->desc = NULL;
 650         ep->stopped = 1;
 651         spin_unlock_irqrestore(&udc->lock, flags);
 652
 653         VDBG("disabled %s OK", _ep->name);
 654         return 0;
 655 }
 656
 657 /*---------------------------------------------------------------------
 658  * allocate a request object used by this endpoint
 659  * the main operation is to insert the req->queue to the eq->queue
 660  * Returns the request, or null if one could not be allocated
 661 *---------------------------------------------------------------------*/
 662 static struct usb_request *
 663 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 664 {
 665         struct fsl_req *req = NULL;
 666
 667         req = kzalloc(sizeof *req, gfp_flags);
 668         if (!req)
 669                 return NULL;
 670
 671         req->req.dma = DMA_ADDR_INVALID;
 672         INIT_LIST_HEAD(&req->queue);
 673
 674         return &req->req;
 675 }
 676
 677 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 678 {
 679         struct fsl_req *req = NULL;
 680
 681         req = container_of(_req, struct fsl_req, req);
 682
 683         if (_req)
 684                 kfree(req);
 685 }
 686
 687 /*-------------------------------------------------------------------------*/
 688 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 689 {
 690         int i = ep_index(ep) * 2 + ep_is_in(ep);
 691         u32 temp, bitmask, tmp_stat;
 692         struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
 693
 694         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 695         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 696
 697         bitmask = ep_is_in(ep)
 698                 ? (1 << (ep_index(ep) + 16))
 699                 : (1 << (ep_index(ep)));
 700
 701         /* check if the pipe is empty */
 702         if (!(list_empty(&ep->queue))) {
 703                 /* Add td to the end */
 704                 struct fsl_req *lastreq;
 705                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 706                 lastreq->tail->next_td_ptr =
 707                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 708                 /* Read prime bit, if 1 goto done */
 709                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 710                         goto out;
 711
 712                 do {
 713                         /* Set ATDTW bit in USBCMD */
 714                         temp = fsl_readl(&dr_regs->usbcmd);
 715                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 716
 717                         /* Read correct status bit */
 718                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 719
 720                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 721
 722                 /* Write ATDTW bit to 0 */
 723                 temp = fsl_readl(&dr_regs->usbcmd);
 724                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 725
 726                 if (tmp_stat)
 727                         goto out;
 728         }
 729
 730         /* Write dQH next pointer and terminate bit to 0 */
 731         temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 732         dQH->next_dtd_ptr = cpu_to_hc32(temp);
 733
 734         /* Clear active and halt bit */
 735         temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 736                         | EP_QUEUE_HEAD_STATUS_HALT));
 737         dQH->size_ioc_int_sts &= temp;
 738
 739         /* Ensure that updates to the QH will occur before priming. */
 740         wmb();
 741
 742         /* Prime endpoint by writing 1 to ENDPTPRIME */
 743         temp = ep_is_in(ep)
 744                 ? (1 << (ep_index(ep) + 16))
 745                 : (1 << (ep_index(ep)));
 746         fsl_writel(temp, &dr_regs->endpointprime);
 747 out:
 748         return;
 749 }
 750
 751 /* Fill in the dTD structure
 752  * @req: request that the transfer belongs to
 753  * @length: return actually data length of the dTD
 754  * @dma: return dma address of the dTD
 755  * @is_last: return flag if it is the last dTD of the request
 756  * return: pointer to the built dTD */
 757 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 758                 dma_addr_t *dma, int *is_last)
 759 {
 760         u32 swap_temp;
 761         struct ep_td_struct *dtd;
 762
 763         /* how big will this transfer be? */
 764         *length = min(req->req.length - req->req.actual,
 765                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 766
 767         dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
 768         if (dtd == NULL)
 769                 return dtd;
 770
 771         dtd->td_dma = *dma;
 772         /* Clear reserved field */
 773         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 774         swap_temp &= ~DTD_RESERVED_FIELDS;
 775         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 776
 777         /* Init all of buffer page pointers */
 778         swap_temp = (u32) (req->req.dma + req->req.actual);
 779         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 780         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 781         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 782         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 783         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 784
 785         req->req.actual += *length;
 786
 787         /* zlp is needed if req->req.zero is set */
 788         if (req->req.zero) {
 789                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 790                         *is_last = 1;
 791                 else
 792                         *is_last = 0;
 793         } else if (req->req.length == req->req.actual)
 794                 *is_last = 1;
 795         else
 796                 *is_last = 0;
 797
 798         if ((*is_last) == 0)
 799                 VDBG("multi-dtd request!");
 800         /* Fill in the transfer size; set active bit */
 801         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 802
 803         /* Enable interrupt for the last dtd of a request */
 804         if (*is_last && !req->req.no_interrupt)
 805                 swap_temp |= DTD_IOC;
 806
 807         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 808
 809         mb();
 810
 811         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 812
 813         return dtd;
 814 }
 815
 816 /* Generate dtd chain for a request */
 817 static int fsl_req_to_dtd(struct fsl_req *req)
 818 {
 819         unsigned        count;
 820         int             is_last;
 821         int             is_first =1;
 822         struct ep_td_struct     *last_dtd = NULL, *dtd;
 823         dma_addr_t dma;
 824
 825         do {
 826                 dtd = fsl_build_dtd(req, &count, &dma, &is_last);
 827                 if (dtd == NULL)
 828                         return -ENOMEM;
 829
 830                 if (is_first) {
 831                         is_first = 0;
 832                         req->head = dtd;
 833                 } else {
 834                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 835                         last_dtd->next_td_virt = dtd;
 836                 }
 837                 last_dtd = dtd;
 838
 839                 req->dtd_count++;
 840         } while (!is_last);
 841
 842         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 843
 844         req->tail = dtd;
 845
 846         return 0;
 847 }
 848
 849 /* queues (submits) an I/O request to an endpoint */
 850 static int
 851 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 852 {
 853         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 854         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 855         struct fsl_udc *udc;
 856         unsigned long flags;
 857
 858         /* catch various bogus parameters */
 859         if (!_req || !req->req.complete || !req->req.buf
 860                         || !list_empty(&req->queue)) {
 861                 VDBG("%s, bad params", __func__);
 862                 return -EINVAL;
 863         }
 864         if (unlikely(!_ep || !ep->desc)) {
 865                 VDBG("%s, bad ep", __func__);
 866                 return -EINVAL;
 867         }
 868         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 869                 if (req->req.length > ep->ep.maxpacket)
 870                         return -EMSGSIZE;
 871         }
 872
 873         udc = ep->udc;
 874         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 875                 return -ESHUTDOWN;
 876
 877         req->ep = ep;
 878
 879         /* map virtual address to hardware */
 880         if (req->req.dma == DMA_ADDR_INVALID) {
 881                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 882                                         req->req.buf,
 883                                         req->req.length, ep_is_in(ep)
 884                                                 ? DMA_TO_DEVICE
 885                                                 : DMA_FROM_DEVICE);
 886                 req->mapped = 1;
 887         } else {
 888                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 889                                         req->req.dma, req->req.length,
 890                                         ep_is_in(ep)
 891                                                 ? DMA_TO_DEVICE
 892                                                 : DMA_FROM_DEVICE);
 893                 req->mapped = 0;
 894         }
 895
 896         req->req.status = -EINPROGRESS;
 897         req->req.actual = 0;
 898         req->dtd_count = 0;
 899
 900         spin_lock_irqsave(&udc->lock, flags);
 901
 902         /* build dtds and push them to device queue */
 903         if (!fsl_req_to_dtd(req)) {
 904                 fsl_queue_td(ep, req);
 905         } else {
 906                 spin_unlock_irqrestore(&udc->lock, flags);
 907                 return -ENOMEM;
 908         }
 909
 910         /* Update ep0 state */
 911         if ((ep_index(ep) == 0))
 912                 udc->ep0_state = DATA_STATE_XMIT;
 913
 914         /* irq handler advances the queue */
 915         if (req != NULL)
 916                 list_add_tail(&req->queue, &ep->queue);
 917         spin_unlock_irqrestore(&udc->lock, flags);
 918
 919         return 0;
 920 }
 921
 922 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 923 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 924 {
 925         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 926         struct fsl_req *req;
 927         unsigned long flags;
 928         int ep_num, stopped, ret = 0;
 929         u32 epctrl;
 930
 931         if (!_ep || !_req)
 932                 return -EINVAL;
 933
 934         spin_lock_irqsave(&ep->udc->lock, flags);
 935         stopped = ep->stopped;
 936
 937         /* Stop the ep before we deal with the queue */
 938         ep->stopped = 1;
 939         ep_num = ep_index(ep);
 940         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 941         if (ep_is_in(ep))
 942                 epctrl &= ~EPCTRL_TX_ENABLE;
 943         else
 944                 epctrl &= ~EPCTRL_RX_ENABLE;
 945         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 946
 947         /* make sure it's actually queued on this endpoint */
 948         list_for_each_entry(req, &ep->queue, queue) {
 949                 if (&req->req == _req)
 950                         break;
 951         }
 952         if (&req->req != _req) {
 953                 ret = -EINVAL;
 954                 goto out;
 955         }
 956
 957         /* The request is in progress, or completed but not dequeued */
 958         if (ep->queue.next == &req->queue) {
 959                 _req->status = -ECONNRESET;
 960                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 961
 962                 /* The request isn't the last request in this ep queue */
 963                 if (req->queue.next != &ep->queue) {
 964                         struct ep_queue_head *qh;
 965                         struct fsl_req *next_req;
 966
 967                         qh = ep->qh;
 968                         next_req = list_entry(req->queue.next, struct fsl_req,
 969                                         queue);
 970
 971                         /* Point the QH to the first TD of next request */
 972                         fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
 973                 }
 974
 975                 /* The request hasn't been processed, patch up the TD chain */
 976         } else {
 977                 struct fsl_req *prev_req;
 978
 979                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 980                 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
 981                                 &prev_req->tail->next_td_ptr);
 982
 983         }
 984
 985         done(ep, req, -ECONNRESET);
 986
 987         /* Enable EP */
 988 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 989         if (ep_is_in(ep))
 990                 epctrl |= EPCTRL_TX_ENABLE;
 991         else
 992                 epctrl |= EPCTRL_RX_ENABLE;
 993         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 994         ep->stopped = stopped;
 995
 996         spin_unlock_irqrestore(&ep->udc->lock, flags);
 997         return ret;
 998 }
 999
1000 /*-------------------------------------------------------------------------*/
1001
1002 /*-----------------------------------------------------------------
1003  * modify the endpoint halt feature
1004  * @ep: the non-isochronous endpoint being stalled
1005  * @value: 1--set halt  0--clear halt
1006  * Returns zero, or a negative error code.
1007 *----------------------------------------------------------------*/
1008 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1009 {
1010         struct fsl_ep *ep = NULL;
1011         unsigned long flags = 0;
1012         int status = -EOPNOTSUPP;       /* operation not supported */
1013         unsigned char ep_dir = 0, ep_num = 0;
1014         struct fsl_udc *udc = NULL;
1015
1016         ep = container_of(_ep, struct fsl_ep, ep);
1017         udc = ep->udc;
1018         if (!_ep || !ep->desc) {
1019                 status = -EINVAL;
1020                 goto out;
1021         }
1022
1023         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1024                 status = -EOPNOTSUPP;
1025                 goto out;
1026         }
1027
1028         /* Attempt to halt IN ep will fail if any transfer requests
1029          * are still queue */
1030         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1031                 status = -EAGAIN;
1032                 goto out;
1033         }
1034
1035         status = 0;
1036         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1037         ep_num = (unsigned char)(ep_index(ep));
1038         spin_lock_irqsave(&ep->udc->lock, flags);
1039         dr_ep_change_stall(ep_num, ep_dir, value);
1040         spin_unlock_irqrestore(&ep->udc->lock, flags);
1041
1042         if (ep_index(ep) == 0) {
1043                 udc->ep0_state = WAIT_FOR_SETUP;
1044                 udc->ep0_dir = 0;
1045         }
1046 out:
1047         VDBG(" %s %s halt stat %d", ep->ep.name,
1048                         value ?  "set" : "clear", status);
1049
1050         return status;
1051 }
1052
1053 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1054 {
1055         struct fsl_ep *ep;
1056         struct fsl_udc *udc;
1057         int size = 0;
1058         u32 bitmask;
1059         struct ep_queue_head *d_qh;
1060
1061         ep = container_of(_ep, struct fsl_ep, ep);
1062         if (!_ep || (!ep->desc && ep_index(ep) != 0))
1063                 return -ENODEV;
1064
1065         udc = (struct fsl_udc *)ep->udc;
1066
1067         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1068                 return -ESHUTDOWN;
1069
1070         d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1071
1072         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1073             (1 << (ep_index(ep)));
1074
1075         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1076                 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1077                     >> DTD_LENGTH_BIT_POS;
1078
1079         pr_debug("%s %u\n", __func__, size);
1080         return size;
1081 }
1082
1083 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1084 {
1085         struct fsl_ep *ep;
1086         int ep_num, ep_dir;
1087         u32 bits;
1088         unsigned long timeout;
1089 #define FSL_UDC_FLUSH_TIMEOUT 1000
1090
1091         if (!_ep) {
1092                 return;
1093         } else {
1094                 ep = container_of(_ep, struct fsl_ep, ep);
1095                 if (!ep->desc)
1096                         return;
1097         }
1098         ep_num = ep_index(ep);
1099         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1100
1101         if (ep_num == 0)
1102                 bits = (1 << 16) | 1;
1103         else if (ep_dir == USB_SEND)
1104                 bits = 1 << (16 + ep_num);
1105         else
1106                 bits = 1 << ep_num;
1107
1108         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1109         do {
1110                 fsl_writel(bits, &dr_regs->endptflush);
1111
1112                 /* Wait until flush complete */
1113                 while (fsl_readl(&dr_regs->endptflush)) {
1114                         if (time_after(jiffies, timeout)) {
1115                                 ERR("ep flush timeout\n");
1116                                 return;
1117                         }
1118                         cpu_relax();
1119                 }
1120                 /* See if we need to flush again */
1121         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1122 }
1123
1124 static struct usb_ep_ops fsl_ep_ops = {
1125         .enable = fsl_ep_enable,
1126         .disable = fsl_ep_disable,
1127
1128         .alloc_request = fsl_alloc_request,
1129         .free_request = fsl_free_request,
1130
1131         .queue = fsl_ep_queue,
1132         .dequeue = fsl_ep_dequeue,
1133
1134         .set_halt = fsl_ep_set_halt,
1135         .fifo_status = fsl_ep_fifo_status,
1136         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1137 };
1138
1139 /*-------------------------------------------------------------------------
1140                 Gadget Driver Layer Operations
1141 -------------------------------------------------------------------------*/
1142
1143 /*----------------------------------------------------------------------
1144  * Get the current frame number (from DR frame_index Reg )
1145  *----------------------------------------------------------------------*/
1146 static int fsl_get_frame(struct usb_gadget *gadget)
1147 {
1148         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1149 }
1150
1151 /*-----------------------------------------------------------------------
1152  * Tries to wake up the host connected to this gadget
1153  -----------------------------------------------------------------------*/
1154 static int fsl_wakeup(struct usb_gadget *gadget)
1155 {
1156         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1157         u32 portsc;
1158
1159         /* Remote wakeup feature not enabled by host */
1160         if (!udc->remote_wakeup)
1161                 return -ENOTSUPP;
1162
1163         portsc = fsl_readl(&dr_regs->portsc1);
1164         /* not suspended? */
1165         if (!(portsc & PORTSCX_PORT_SUSPEND))
1166                 return 0;
1167         /* trigger force resume */
1168         portsc |= PORTSCX_PORT_FORCE_RESUME;
1169         fsl_writel(portsc, &dr_regs->portsc1);
1170         return 0;
1171 }
1172
1173 static int can_pullup(struct fsl_udc *udc)
1174 {
1175         return udc->driver && udc->softconnect && udc->vbus_active;
1176 }
1177
1178 /* Notify controller that VBUS is powered, Called by whatever
1179    detects VBUS sessions */
1180 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1181 {
1182         struct fsl_udc  *udc;
1183         unsigned long   flags;
1184
1185         udc = container_of(gadget, struct fsl_udc, gadget);
1186         spin_lock_irqsave(&udc->lock, flags);
1187         VDBG("VBUS %s", is_active ? "on" : "off");
1188         udc->vbus_active = (is_active != 0);
1189         if (can_pullup(udc))
1190                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1191                                 &dr_regs->usbcmd);
1192         else
1193                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1194                                 &dr_regs->usbcmd);
1195         spin_unlock_irqrestore(&udc->lock, flags);
1196         return 0;
1197 }
1198
1199 /* constrain controller's VBUS power usage
1200  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1201  * reporting how much power the device may consume.  For example, this
1202  * could affect how quickly batteries are recharged.
1203  *
1204  * Returns zero on success, else negative errno.
1205  */
1206 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1207 {
1208         struct fsl_udc *udc;
1209
1210         udc = container_of(gadget, struct fsl_udc, gadget);
1211         if (udc->transceiver)
1212                 return otg_set_power(udc->transceiver, mA);
1213         return -ENOTSUPP;
1214 }
1215
1216 /* Change Data+ pullup status
1217  * this func is used by usb_gadget_connect/disconnet
1218  */
1219 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1220 {
1221         struct fsl_udc *udc;
1222
1223         udc = container_of(gadget, struct fsl_udc, gadget);
1224         udc->softconnect = (is_on != 0);
1225         if (can_pullup(udc))
1226                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1227                                 &dr_regs->usbcmd);
1228         else
1229                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1230                                 &dr_regs->usbcmd);
1231
1232         return 0;
1233 }
1234
1235 /* defined in gadget.h */
1236 static struct usb_gadget_ops fsl_gadget_ops = {
1237         .get_frame = fsl_get_frame,
1238         .wakeup = fsl_wakeup,
1239 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1240         .vbus_session = fsl_vbus_session,
1241         .vbus_draw = fsl_vbus_draw,
1242         .pullup = fsl_pullup,
1243 };
1244
1245 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1246    on new transaction */
1247 static void ep0stall(struct fsl_udc *udc)
1248 {
1249         u32 tmp;
1250
1251         /* must set tx and rx to stall at the same time */
1252         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1253         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1254         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1255         udc->ep0_state = WAIT_FOR_SETUP;
1256         udc->ep0_dir = 0;
1257 }
1258
1259 /* Prime a status phase for ep0 */
1260 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1261 {
1262         struct fsl_req *req = udc->status_req;
1263         struct fsl_ep *ep;
1264
1265         if (direction == EP_DIR_IN)
1266                 udc->ep0_dir = USB_DIR_IN;
1267         else
1268                 udc->ep0_dir = USB_DIR_OUT;
1269
1270         ep = &udc->eps[0];
1271         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1272
1273         req->ep = ep;
1274         req->req.length = 0;
1275         req->req.status = -EINPROGRESS;
1276         req->req.actual = 0;
1277         req->req.complete = NULL;
1278         req->dtd_count = 0;
1279
1280         if (fsl_req_to_dtd(req) == 0)
1281                 fsl_queue_td(ep, req);
1282         else
1283                 return -ENOMEM;
1284
1285         list_add_tail(&req->queue, &ep->queue);
1286
1287         return 0;
1288 }
1289
1290 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1291 {
1292         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1293
1294         if (ep->name)
1295                 nuke(ep, -ESHUTDOWN);
1296 }
1297
1298 /*
1299  * ch9 Set address
1300  */
1301 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1302 {
1303         /* Save the new address to device struct */
1304         udc->device_address = (u8) value;
1305         /* Update usb state */
1306         udc->usb_state = USB_STATE_ADDRESS;
1307         /* Status phase */
1308         if (ep0_prime_status(udc, EP_DIR_IN))
1309                 ep0stall(udc);
1310 }
1311
1312 /*
1313  * ch9 Get status
1314  */
1315 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1316                 u16 index, u16 length)
1317 {
1318         u16 tmp = 0;            /* Status, cpu endian */
1319         struct fsl_req *req;
1320         struct fsl_ep *ep;
1321
1322         ep = &udc->eps[0];
1323
1324         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1325                 /* Get device status */
1326                 tmp = 1 << USB_DEVICE_SELF_POWERED;
1327                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1328         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1329                 /* Get interface status */
1330                 /* We don't have interface information in udc driver */
1331                 tmp = 0;
1332         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1333                 /* Get endpoint status */
1334                 struct fsl_ep *target_ep;
1335
1336                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1337
1338                 /* stall if endpoint doesn't exist */
1339                 if (!target_ep->desc)
1340                         goto stall;
1341                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1342                                 << USB_ENDPOINT_HALT;
1343         }
1344
1345         udc->ep0_dir = USB_DIR_IN;
1346         /* Borrow the per device status_req */
1347         req = udc->status_req;
1348         /* Fill in the reqest structure */
1349         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1350
1351         /* flush cache for the req buffer */
1352         flush_dcache_range((u32)req->req.buf, (u32)req->req.buf + 8);
1353
1354         req->ep = ep;
1355         req->req.length = 2;
1356         req->req.status = -EINPROGRESS;
1357         req->req.actual = 0;
1358         req->req.complete = NULL;
1359         req->dtd_count = 0;
1360
1361         /* prime the data phase */
1362         if ((fsl_req_to_dtd(req) == 0))
1363                 fsl_queue_td(ep, req);
1364         else                    /* no mem */
1365                 goto stall;
1366
1367         list_add_tail(&req->queue, &ep->queue);
1368         udc->ep0_state = DATA_STATE_XMIT;
1369         return;
1370 stall:
1371         ep0stall(udc);
1372 }
1373
1374 static void setup_received_irq(struct fsl_udc *udc,
1375                 struct usb_ctrlrequest *setup)
1376 {
1377         u16 wValue = le16_to_cpu(setup->wValue);
1378         u16 wIndex = le16_to_cpu(setup->wIndex);
1379         u16 wLength = le16_to_cpu(setup->wLength);
1380
1381         udc_reset_ep_queue(udc, 0);
1382
1383         /* We process some stardard setup requests here */
1384         switch (setup->bRequest) {
1385         case USB_REQ_GET_STATUS:
1386                 /* Data+Status phase from udc */
1387                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1388                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1389                         break;
1390                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1391                 return;
1392
1393         case USB_REQ_SET_ADDRESS:
1394                 /* Status phase from udc */
1395                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1396                                                 | USB_RECIP_DEVICE))
1397                         break;
1398                 ch9setaddress(udc, wValue, wIndex, wLength);
1399                 return;
1400
1401         case USB_REQ_CLEAR_FEATURE:
1402         case USB_REQ_SET_FEATURE:
1403                 /* Status phase from udc */
1404         {
1405                 int rc = -EOPNOTSUPP;
1406                 u16 ptc = 0;
1407
1408                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1409                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1410                         int pipe = get_pipe_by_windex(wIndex);
1411                         struct fsl_ep *ep;
1412
1413                         if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1414                                 break;
1415                         ep = get_ep_by_pipe(udc, pipe);
1416
1417                         spin_unlock(&udc->lock);
1418                         rc = fsl_ep_set_halt(&ep->ep,
1419                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1420                                                 ? 1 : 0);
1421                         spin_lock(&udc->lock);
1422
1423                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1424                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1425                                 | USB_TYPE_STANDARD)) {
1426                         /* Note: The driver has not include OTG support yet.
1427                          * This will be set when OTG support is added */
1428                         if (wValue == USB_DEVICE_TEST_MODE)
1429                                 ptc = wIndex >> 8;
1430                         else if (gadget_is_otg(&udc->gadget)) {
1431                                 if (setup->bRequest ==
1432                                     USB_DEVICE_B_HNP_ENABLE)
1433                                         udc->gadget.b_hnp_enable = 1;
1434                                 else if (setup->bRequest ==
1435                                          USB_DEVICE_A_HNP_SUPPORT)
1436                                         udc->gadget.a_hnp_support = 1;
1437                                 else if (setup->bRequest ==
1438                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1439                                         udc->gadget.a_alt_hnp_support = 1;
1440                         }
1441                         rc = 0;
1442                 } else
1443                         break;
1444
1445                 if (rc == 0) {
1446                         if (ep0_prime_status(udc, EP_DIR_IN))
1447                                 ep0stall(udc);
1448                 }
1449                 if (ptc) {
1450                         u32 tmp;
1451
1452                         mdelay(10);
1453                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1454                         fsl_writel(tmp, &dr_regs->portsc1);
1455                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1456                 }
1457
1458                 return;
1459         }
1460
1461         default:
1462                 break;
1463         }
1464
1465         /* Requests handled by gadget */
1466         if (wLength) {
1467                 /* Data phase from gadget, status phase from udc */
1468                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1469                                 ?  USB_DIR_IN : USB_DIR_OUT;
1470                 spin_unlock(&udc->lock);
1471                 if (udc->driver->setup(&udc->gadget,
1472                                 &udc->local_setup_buff) < 0)
1473                         ep0stall(udc);
1474                 spin_lock(&udc->lock);
1475                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1476                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1477         } else {
1478                 /* No data phase, IN status from gadget */
1479                 udc->ep0_dir = USB_DIR_IN;
1480                 spin_unlock(&udc->lock);
1481                 if (udc->driver->setup(&udc->gadget,
1482                                 &udc->local_setup_buff) < 0)
1483                         ep0stall(udc);
1484                 spin_lock(&udc->lock);
1485                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1486         }
1487 }
1488
1489 /* Process request for Data or Status phase of ep0
1490  * prime status phase if needed */
1491 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1492                 struct fsl_req *req)
1493 {
1494         if (udc->usb_state == USB_STATE_ADDRESS) {
1495                 /* Set the new address */
1496                 u32 new_address = (u32) udc->device_address;
1497                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1498                                 &dr_regs->deviceaddr);
1499         }
1500
1501         done(ep0, req, 0);
1502
1503         switch (udc->ep0_state) {
1504         case DATA_STATE_XMIT:
1505                 /* receive status phase */
1506                 if (ep0_prime_status(udc, EP_DIR_OUT))
1507                         ep0stall(udc);
1508                 break;
1509         case DATA_STATE_RECV:
1510                 /* send status phase */
1511                 if (ep0_prime_status(udc, EP_DIR_IN))
1512                         ep0stall(udc);
1513                 break;
1514         case WAIT_FOR_OUT_STATUS:
1515                 udc->ep0_state = WAIT_FOR_SETUP;
1516                 break;
1517         case WAIT_FOR_SETUP:
1518                 ERR("Unexpect ep0 packets\n");
1519                 break;
1520         default:
1521                 ep0stall(udc);
1522                 break;
1523         }
1524 }
1525
1526 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1527  * being corrupted by another incoming setup packet */
1528 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1529 {
1530         u32 temp;
1531         struct ep_queue_head *qh;
1532         struct fsl_usb2_platform_data *pdata = udc->pdata;
1533
1534         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1535
1536         /* Clear bit in ENDPTSETUPSTAT */
1537         temp = fsl_readl(&dr_regs->endptsetupstat);
1538         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1539
1540         /* while a hazard exists when setup package arrives */
1541         do {
1542                 /* Set Setup Tripwire */
1543                 temp = fsl_readl(&dr_regs->usbcmd);
1544                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1545
1546                 /* Copy the setup packet to local buffer */
1547                 if (pdata->le_setup_buf) {
1548                         u32 *p = (u32 *)buffer_ptr;
1549                         u32 *s = (u32 *)qh->setup_buffer;
1550
1551                         /* Convert little endian setup buffer to CPU endian */
1552                         *p++ = le32_to_cpu(*s++);
1553                         *p = le32_to_cpu(*s);
1554                 } else {
1555                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1556                 }
1557         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1558
1559         /* Clear Setup Tripwire */
1560         temp = fsl_readl(&dr_regs->usbcmd);
1561         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1562 }
1563
1564 /* process-ep_req(): free the completed Tds for this req */
1565 static int process_ep_req(struct fsl_udc *udc, int pipe,
1566                 struct fsl_req *curr_req)
1567 {
1568         struct ep_td_struct *curr_td;
1569         int     td_complete, actual, remaining_length, j, tmp;
1570         int     status = 0;
1571         int     errors = 0;
1572         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1573         int direction = pipe % 2;
1574
1575         curr_td = curr_req->head;
1576         td_complete = 0;
1577         actual = curr_req->req.length;
1578
1579         for (j = 0; j < curr_req->dtd_count; j++) {
1580                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1581                                         & DTD_PACKET_SIZE)
1582                                 >> DTD_LENGTH_BIT_POS;
1583                 actual -= remaining_length;
1584
1585                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1586                 if (errors & DTD_ERROR_MASK) {
1587                         if (errors & DTD_STATUS_HALTED) {
1588                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1589                                 /* Clear the errors and Halt condition */
1590                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1591                                 tmp &= ~errors;
1592                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1593                                 status = -EPIPE;
1594                                 /* FIXME: continue with next queued TD? */
1595
1596                                 break;
1597                         }
1598                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1599                                 VDBG("Transfer overflow");
1600                                 status = -EPROTO;
1601                                 break;
1602                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1603                                 VDBG("ISO error");
1604                                 status = -EILSEQ;
1605                                 break;
1606                         } else
1607                                 ERR("Unknown error has occurred (0x%x)!\n",
1608                                         errors);
1609
1610                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1611                                 & DTD_STATUS_ACTIVE) {
1612                         VDBG("Request not complete");
1613                         status = REQ_UNCOMPLETE;
1614                         return status;
1615                 } else if (remaining_length) {
1616                         if (direction) {
1617                                 VDBG("Transmit dTD remaining length not zero");
1618                                 status = -EPROTO;
1619                                 break;
1620                         } else {
1621                                 td_complete++;
1622                                 break;
1623                         }
1624                 } else {
1625                         td_complete++;
1626                         VDBG("dTD transmitted successful");
1627                 }
1628
1629                 if (j != curr_req->dtd_count - 1)
1630                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1631         }
1632
1633         if (status)
1634                 return status;
1635
1636         curr_req->req.actual = actual;
1637
1638         return 0;
1639 }
1640
1641 /* Process a DTD completion interrupt */
1642 static void dtd_complete_irq(struct fsl_udc *udc)
1643 {
1644         u32 bit_pos;
1645         int i, ep_num, direction, bit_mask, status;
1646         struct fsl_ep *curr_ep;
1647         struct fsl_req *curr_req, *temp_req;
1648
1649         /* Clear the bits in the register */
1650         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1651         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1652
1653         if (!bit_pos)
1654                 return;
1655
1656         for (i = 0; i < udc->max_ep * 2; i++) {
1657                 ep_num = i >> 1;
1658                 direction = i % 2;
1659
1660                 bit_mask = 1 << (ep_num + 16 * direction);
1661
1662                 if (!(bit_pos & bit_mask))
1663                         continue;
1664
1665                 curr_ep = get_ep_by_pipe(udc, i);
1666
1667                 /* If the ep is configured */
1668                 if (curr_ep->name == NULL) {
1669                         WARNING("Invalid EP?");
1670                         continue;
1671                 }
1672
1673                 /* process the req queue until an uncomplete request */
1674                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1675                                 queue) {
1676                         status = process_ep_req(udc, i, curr_req);
1677
1678                         VDBG("status of process_ep_req= %d, ep = %d",
1679                                         status, ep_num);
1680                         if (status == REQ_UNCOMPLETE)
1681                                 break;
1682                         /* write back status to req */
1683                         curr_req->req.status = status;
1684
1685                         if (ep_num == 0) {
1686                                 ep0_req_complete(udc, curr_ep, curr_req);
1687                                 break;
1688                         } else
1689                                 done(curr_ep, curr_req, status);
1690                 }
1691         }
1692 }
1693
1694 /* Process a port change interrupt */
1695 static void port_change_irq(struct fsl_udc *udc)
1696 {
1697         u32 speed;
1698
1699         if (udc->bus_reset)
1700                 udc->bus_reset = 0;
1701
1702         /* Bus resetting is finished */
1703         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
1704                 /* Get the speed */
1705                 speed = (fsl_readl(&dr_regs->portsc1)
1706                                 & PORTSCX_PORT_SPEED_MASK);
1707                 switch (speed) {
1708                 case PORTSCX_PORT_SPEED_HIGH:
1709                         udc->gadget.speed = USB_SPEED_HIGH;
1710                         break;
1711                 case PORTSCX_PORT_SPEED_FULL:
1712                         udc->gadget.speed = USB_SPEED_FULL;
1713                         break;
1714                 case PORTSCX_PORT_SPEED_LOW:
1715                         udc->gadget.speed = USB_SPEED_LOW;
1716                         break;
1717                 default:
1718                         udc->gadget.speed = USB_SPEED_UNKNOWN;
1719                         break;
1720                 }
1721         }
1722
1723         /* Update USB state */
1724         if (!udc->resume_state)
1725                 udc->usb_state = USB_STATE_DEFAULT;
1726 }
1727
1728 /* Process suspend interrupt */
1729 static void suspend_irq(struct fsl_udc *udc)
1730 {
1731         udc->resume_state = udc->usb_state;
1732         udc->usb_state = USB_STATE_SUSPENDED;
1733
1734         /* report suspend to the driver, serial.c does not support this */
1735         if (udc->driver->suspend)
1736                 udc->driver->suspend(&udc->gadget);
1737 }
1738
1739 static void bus_resume(struct fsl_udc *udc)
1740 {
1741         udc->usb_state = udc->resume_state;
1742         udc->resume_state = 0;
1743
1744         /* report resume to the driver, serial.c does not support this */
1745         if (udc->driver->resume)
1746                 udc->driver->resume(&udc->gadget);
1747 }
1748
1749 /* Clear up all ep queues */
1750 static int reset_queues(struct fsl_udc *udc)
1751 {
1752         u8 pipe;
1753
1754         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1755                 udc_reset_ep_queue(udc, pipe);
1756
1757         /* report disconnect; the driver is already quiesced */
1758         spin_unlock(&udc->lock);
1759         udc->driver->disconnect(&udc->gadget);
1760         spin_lock(&udc->lock);
1761
1762         return 0;
1763 }
1764
1765 /* Process reset interrupt */
1766 static void reset_irq(struct fsl_udc *udc)
1767 {
1768         u32 temp;
1769         unsigned long timeout;
1770
1771         /* Clear the device address */
1772         temp = fsl_readl(&dr_regs->deviceaddr);
1773         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1774
1775         udc->device_address = 0;
1776
1777         /* Clear usb state */
1778         udc->resume_state = 0;
1779         udc->ep0_dir = 0;
1780         udc->ep0_state = WAIT_FOR_SETUP;
1781         udc->remote_wakeup = 0; /* default to 0 on reset */
1782         udc->gadget.b_hnp_enable = 0;
1783         udc->gadget.a_hnp_support = 0;
1784         udc->gadget.a_alt_hnp_support = 0;
1785
1786         /* Clear all the setup token semaphores */
1787         temp = fsl_readl(&dr_regs->endptsetupstat);
1788         fsl_writel(temp, &dr_regs->endptsetupstat);
1789
1790         /* Clear all the endpoint complete status bits */
1791         temp = fsl_readl(&dr_regs->endptcomplete);
1792         fsl_writel(temp, &dr_regs->endptcomplete);
1793
1794         timeout = jiffies + 100;
1795         while (fsl_readl(&dr_regs->endpointprime)) {
1796                 /* Wait until all endptprime bits cleared */
1797                 if (time_after(jiffies, timeout)) {
1798                         ERR("Timeout for reset\n");
1799                         break;
1800                 }
1801                 cpu_relax();
1802         }
1803
1804         /* Write 1s to the flush register */
1805         fsl_writel(0xffffffff, &dr_regs->endptflush);
1806
1807         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1808                 VDBG("Bus reset");
1809                 /* Bus is reseting */
1810                 udc->bus_reset = 1;
1811                 /* Reset all the queues, include XD, dTD, EP queue
1812                  * head and TR Queue */
1813                 reset_queues(udc);
1814                 udc->usb_state = USB_STATE_DEFAULT;
1815         } else {
1816                 VDBG("Controller reset");
1817                 /* initialize usb hw reg except for regs for EP, not
1818                  * touch usbintr reg */
1819                 dr_controller_setup(udc);
1820
1821                 /* Reset all internal used Queues */
1822                 reset_queues(udc);
1823
1824                 ep0_setup(udc);
1825
1826                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1827                 dr_controller_run(udc);
1828                 udc->usb_state = USB_STATE_ATTACHED;
1829         }
1830 }
1831
1832 /*
1833  * USB device controller interrupt handler
1834  */
1835 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1836 {
1837         struct fsl_udc *udc = _udc;
1838         u32 irq_src;
1839         irqreturn_t status = IRQ_NONE;
1840         unsigned long flags;
1841
1842         /* Disable ISR for OTG host mode */
1843         if (udc->stopped)
1844                 return IRQ_NONE;
1845         spin_lock_irqsave(&udc->lock, flags);
1846         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1847         /* Clear notification bits */
1848         fsl_writel(irq_src, &dr_regs->usbsts);
1849
1850         /* VDBG("irq_src [0x%8x]", irq_src); */
1851
1852         /* Need to resume? */
1853         if (udc->usb_state == USB_STATE_SUSPENDED)
1854                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1855                         bus_resume(udc);
1856
1857         /* USB Interrupt */
1858         if (irq_src & USB_STS_INT) {
1859                 VDBG("Packet int");
1860                 /* Setup package, we only support ep0 as control ep */
1861                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1862                         tripwire_handler(udc, 0,
1863                                         (u8 *) (&udc->local_setup_buff));
1864                         setup_received_irq(udc, &udc->local_setup_buff);
1865                         status = IRQ_HANDLED;
1866                 }
1867
1868                 /* completion of dtd */
1869                 if (fsl_readl(&dr_regs->endptcomplete)) {
1870                         dtd_complete_irq(udc);
1871                         status = IRQ_HANDLED;
1872                 }
1873         }
1874
1875         /* SOF (for ISO transfer) */
1876         if (irq_src & USB_STS_SOF) {
1877                 status = IRQ_HANDLED;
1878         }
1879
1880         /* Port Change */
1881         if (irq_src & USB_STS_PORT_CHANGE) {
1882                 port_change_irq(udc);
1883                 status = IRQ_HANDLED;
1884         }
1885
1886         /* Reset Received */
1887         if (irq_src & USB_STS_RESET) {
1888                 VDBG("reset int");
1889                 reset_irq(udc);
1890                 status = IRQ_HANDLED;
1891         }
1892
1893         /* Sleep Enable (Suspend) */
1894         if (irq_src & USB_STS_SUSPEND) {
1895                 suspend_irq(udc);
1896                 status = IRQ_HANDLED;
1897         }
1898
1899         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1900                 VDBG("Error IRQ %x", irq_src);
1901         }
1902
1903         spin_unlock_irqrestore(&udc->lock, flags);
1904         return status;
1905 }
1906
1907 /*----------------------------------------------------------------*
1908  * Hook to gadget drivers
1909  * Called by initialization code of gadget drivers
1910 *----------------------------------------------------------------*/
1911 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1912                 int (*bind)(struct usb_gadget *))
1913 {
1914         int retval = -ENODEV;
1915         unsigned long flags = 0;
1916
1917         if (!udc_controller)
1918                 return -ENODEV;
1919
1920         if (!driver || (driver->speed != USB_SPEED_FULL
1921                                 && driver->speed != USB_SPEED_HIGH)
1922                         || !bind || !driver->disconnect || !driver->setup)
1923                 return -EINVAL;
1924
1925         if (udc_controller->driver)
1926                 return -EBUSY;
1927
1928         /* lock is needed but whether should use this lock or another */
1929         spin_lock_irqsave(&udc_controller->lock, flags);
1930
1931         driver->driver.bus = NULL;
1932         /* hook up the driver */
1933         udc_controller->driver = driver;
1934         udc_controller->gadget.dev.driver = &driver->driver;
1935         spin_unlock_irqrestore(&udc_controller->lock, flags);
1936
1937         /* bind udc driver to gadget driver */
1938         retval = bind(&udc_controller->gadget);
1939         if (retval) {
1940                 VDBG("bind to %s --> %d", driver->driver.name, retval);
1941                 udc_controller->gadget.dev.driver = NULL;
1942                 udc_controller->driver = NULL;
1943                 goto out;
1944         }
1945
1946         if (udc_controller->transceiver) {
1947                 /* Suspend the controller until OTG enable it */
1948                 udc_controller->stopped = 1;
1949                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1950
1951                 /* connect to bus through transceiver */
1952                 if (udc_controller->transceiver) {
1953                         retval = otg_set_peripheral(udc_controller->transceiver,
1954                                                     &udc_controller->gadget);
1955                         if (retval < 0) {
1956                                 ERR("can't bind to transceiver\n");
1957                                 driver->unbind(&udc_controller->gadget);
1958                                 udc_controller->gadget.dev.driver = 0;
1959                                 udc_controller->driver = 0;
1960                                 return retval;
1961                         }
1962                 }
1963         } else {
1964                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1965                 dr_controller_run(udc_controller);
1966                 udc_controller->usb_state = USB_STATE_ATTACHED;
1967                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1968                 udc_controller->ep0_dir = 0;
1969         }
1970         printk(KERN_INFO "%s: bind to driver %s\n",
1971                         udc_controller->gadget.name, driver->driver.name);
1972
1973 out:
1974         if (retval)
1975                 printk(KERN_WARNING "gadget driver register failed %d\n",
1976                        retval);
1977         return retval;
1978 }
1979 EXPORT_SYMBOL(usb_gadget_probe_driver);
1980
1981 /* Disconnect from gadget driver */
1982 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1983 {
1984         struct fsl_ep *loop_ep;
1985         unsigned long flags;
1986
1987         if (!udc_controller)
1988                 return -ENODEV;
1989
1990         if (!driver || driver != udc_controller->driver || !driver->unbind)
1991                 return -EINVAL;
1992
1993         if (udc_controller->transceiver)
1994                 otg_set_peripheral(udc_controller->transceiver, NULL);
1995
1996         /* stop DR, disable intr */
1997         dr_controller_stop(udc_controller);
1998
1999         /* in fact, no needed */
2000         udc_controller->usb_state = USB_STATE_ATTACHED;
2001         udc_controller->ep0_state = WAIT_FOR_SETUP;
2002         udc_controller->ep0_dir = 0;
2003
2004         /* stand operation */
2005         spin_lock_irqsave(&udc_controller->lock, flags);
2006         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2007         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2008         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2009                         ep.ep_list)
2010                 nuke(loop_ep, -ESHUTDOWN);
2011         spin_unlock_irqrestore(&udc_controller->lock, flags);
2012
2013         /* report disconnect; the controller is already quiesced */
2014         driver->disconnect(&udc_controller->gadget);
2015
2016         /* unbind gadget and unhook driver. */
2017         driver->unbind(&udc_controller->gadget);
2018         udc_controller->gadget.dev.driver = NULL;
2019         udc_controller->driver = NULL;
2020
2021         printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2022                driver->driver.name);
2023         return 0;
2024 }
2025 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2026
2027 /*-------------------------------------------------------------------------
2028                 PROC File System Support
2029 -------------------------------------------------------------------------*/
2030 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2031
2032 #include <linux/seq_file.h>
2033
2034 static const char proc_filename[] = "driver/fsl_usb2_udc";
2035
2036 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2037                 int *eof, void *_dev)
2038 {
2039         char *buf = page;
2040         char *next = buf;
2041         unsigned size = count;
2042         unsigned long flags;
2043         int t, i;
2044         u32 tmp_reg;
2045         struct fsl_ep *ep = NULL;
2046         struct fsl_req *req;
2047
2048         struct fsl_udc *udc = udc_controller;
2049         if (off != 0)
2050                 return 0;
2051
2052         spin_lock_irqsave(&udc->lock, flags);
2053
2054         /* ------basic driver information ---- */
2055         t = scnprintf(next, size,
2056                         DRIVER_DESC "\n"
2057                         "%s version: %s\n"
2058                         "Gadget driver: %s\n\n",
2059                         driver_name, DRIVER_VERSION,
2060                         udc->driver ? udc->driver->driver.name : "(none)");
2061         size -= t;
2062         next += t;
2063
2064         /* ------ DR Registers ----- */
2065         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2066         t = scnprintf(next, size,
2067                         "USBCMD reg:\n"
2068                         "SetupTW: %d\n"
2069                         "Run/Stop: %s\n\n",
2070                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2071                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2072         size -= t;
2073         next += t;
2074
2075         tmp_reg = fsl_readl(&dr_regs->usbsts);
2076         t = scnprintf(next, size,
2077                         "USB Status Reg:\n"
2078                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2079                         "USB Error Interrupt: %s\n\n",
2080                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2081                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2082                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2083                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2084         size -= t;
2085         next += t;
2086
2087         tmp_reg = fsl_readl(&dr_regs->usbintr);
2088         t = scnprintf(next, size,
2089                         "USB Intrrupt Enable Reg:\n"
2090                         "Sleep Enable: %d SOF Received Enable: %d "
2091                         "Reset Enable: %d\n"
2092                         "System Error Enable: %d "
2093                         "Port Change Dectected Enable: %d\n"
2094                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2095                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2096                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2097                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2098                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2099                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2100                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2101                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2102         size -= t;
2103         next += t;
2104
2105         tmp_reg = fsl_readl(&dr_regs->frindex);
2106         t = scnprintf(next, size,
2107                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2108                         (tmp_reg & USB_FRINDEX_MASKS));
2109         size -= t;
2110         next += t;
2111
2112         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2113         t = scnprintf(next, size,
2114                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2115                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2116         size -= t;
2117         next += t;
2118
2119         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2120         t = scnprintf(next, size,
2121                         "USB Endpoint List Address Reg: "
2122                         "Device Addr is 0x%x\n\n",
2123                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2124         size -= t;
2125         next += t;
2126
2127         tmp_reg = fsl_readl(&dr_regs->portsc1);
2128         t = scnprintf(next, size,
2129                 "USB Port Status&Control Reg:\n"
2130                 "Port Transceiver Type : %s Port Speed: %s\n"
2131                 "PHY Low Power Suspend: %s Port Reset: %s "
2132                 "Port Suspend Mode: %s\n"
2133                 "Over-current Change: %s "
2134                 "Port Enable/Disable Change: %s\n"
2135                 "Port Enabled/Disabled: %s "
2136                 "Current Connect Status: %s\n\n", ( {
2137                         char *s;
2138                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2139                         case PORTSCX_PTS_UTMI:
2140                                 s = "UTMI"; break;
2141                         case PORTSCX_PTS_ULPI:
2142                                 s = "ULPI "; break;
2143                         case PORTSCX_PTS_FSLS:
2144                                 s = "FS/LS Serial"; break;
2145                         default:
2146                                 s = "None"; break;
2147                         }
2148                         s;} ), ( {
2149                         char *s;
2150                         switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
2151                         case PORTSCX_PORT_SPEED_FULL:
2152                                 s = "Full Speed"; break;
2153                         case PORTSCX_PORT_SPEED_LOW:
2154                                 s = "Low Speed"; break;
2155                         case PORTSCX_PORT_SPEED_HIGH:
2156                                 s = "High Speed"; break;
2157                         default:
2158                                 s = "Undefined"; break;
2159                         }
2160                         s;
2161                 } ),
2162                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2163                 "Normal PHY mode" : "Low power mode",
2164                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2165                 "Not in Reset",
2166                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2167                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2168                 "No",
2169                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2170                 "Not change",
2171                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2172                 "Not correct",
2173                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2174                 "Attached" : "Not-Att");
2175         size -= t;
2176         next += t;
2177
2178         tmp_reg = fsl_readl(&dr_regs->usbmode);
2179         t = scnprintf(next, size,
2180                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2181                                 char *s;
2182                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2183                                 case USB_MODE_CTRL_MODE_IDLE:
2184                                         s = "Idle"; break;
2185                                 case USB_MODE_CTRL_MODE_DEVICE:
2186                                         s = "Device Controller"; break;
2187                                 case USB_MODE_CTRL_MODE_HOST:
2188                                         s = "Host Controller"; break;
2189                                 default:
2190                                         s = "None"; break;
2191                                 }
2192                                 s;
2193                         } ));
2194         size -= t;
2195         next += t;
2196
2197         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2198         t = scnprintf(next, size,
2199                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2200                         (tmp_reg & EP_SETUP_STATUS_MASK));
2201         size -= t;
2202         next += t;
2203
2204         for (i = 0; i < udc->max_ep / 2; i++) {
2205                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2206                 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2207                                 i, tmp_reg);
2208                 size -= t;
2209                 next += t;
2210         }
2211         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2212         t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2213         size -= t;
2214         next += t;
2215
2216 #ifndef CONFIG_ARCH_MXC
2217         if (udc->pdata->have_sysif_regs) {
2218                 tmp_reg = usb_sys_regs->snoop1;
2219                 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2220                 size -= t;
2221                 next += t;
2222
2223                 tmp_reg = usb_sys_regs->control;
2224                 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2225                                 tmp_reg);
2226                 size -= t;
2227                 next += t;
2228         }
2229 #endif
2230
2231         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2232         ep = &udc->eps[0];
2233         t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2234                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2235         size -= t;
2236         next += t;
2237
2238         if (list_empty(&ep->queue)) {
2239                 t = scnprintf(next, size, "its req queue is empty\n\n");
2240                 size -= t;
2241                 next += t;
2242         } else {
2243                 list_for_each_entry(req, &ep->queue, queue) {
2244                         t = scnprintf(next, size,
2245                                 "req %p actual 0x%x length 0x%x buf %p\n",
2246                                 &req->req, req->req.actual,
2247                                 req->req.length, req->req.buf);
2248                         size -= t;
2249                         next += t;
2250                 }
2251         }
2252         /* other gadget->eplist ep */
2253         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2254                 if (ep->desc) {
2255                         t = scnprintf(next, size,
2256                                         "\nFor %s Maxpkt is 0x%x "
2257                                         "index is 0x%x\n",
2258                                         ep->ep.name, ep_maxpacket(ep),
2259                                         ep_index(ep));
2260                         size -= t;
2261                         next += t;
2262
2263                         if (list_empty(&ep->queue)) {
2264                                 t = scnprintf(next, size,
2265                                                 "its req queue is empty\n\n");
2266                                 size -= t;
2267                                 next += t;
2268                         } else {
2269                                 list_for_each_entry(req, &ep->queue, queue) {
2270                                         t = scnprintf(next, size,
2271                                                 "req %p actual 0x%x length "
2272                                                 "0x%x  buf %p\n",
2273                                                 &req->req, req->req.actual,
2274                                                 req->req.length, req->req.buf);
2275                                         size -= t;
2276                                         next += t;
2277                                         }       /* end for each_entry of ep req */
2278                                 }       /* end for else */
2279                         }       /* end for if(ep->queue) */
2280                 }               /* end (ep->desc) */
2281
2282         spin_unlock_irqrestore(&udc->lock, flags);
2283
2284         *eof = 1;
2285         return count - size;
2286 }
2287
2288 #define create_proc_file()      create_proc_read_entry(proc_filename, \
2289                                 0, NULL, fsl_proc_read, NULL)
2290
2291 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2292
2293 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2294
2295 #define create_proc_file()      do {} while (0)
2296 #define remove_proc_file()      do {} while (0)
2297
2298 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2299
2300 /*-------------------------------------------------------------------------*/
2301
2302 /* Release udc structures */
2303 static void fsl_udc_release(struct device *dev)
2304 {
2305         complete(udc_controller->done);
2306         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2307                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2308         kfree(udc_controller);
2309 }
2310
2311 /******************************************************************
2312         Internal structure setup functions
2313 *******************************************************************/
2314 /*------------------------------------------------------------------
2315  * init resource for globle controller
2316  * Return the udc handle on success or NULL on failure
2317  ------------------------------------------------------------------*/
2318 static int __init struct_udc_setup(struct fsl_udc *udc,
2319                 struct platform_device *pdev)
2320 {
2321         struct fsl_usb2_platform_data *pdata;
2322         size_t size;
2323
2324         pdata = pdev->dev.platform_data;
2325         udc->phy_mode = pdata->phy_mode;
2326
2327         udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2328         if (!udc->eps) {
2329                 ERR("malloc fsl_ep failed\n");
2330                 return -1;
2331         }
2332
2333         /* initialized QHs, take care of alignment */
2334         size = udc->max_ep * sizeof(struct ep_queue_head);
2335         if (size < QH_ALIGNMENT)
2336                 size = QH_ALIGNMENT;
2337         else if ((size % QH_ALIGNMENT) != 0) {
2338                 size += QH_ALIGNMENT + 1;
2339                 size &= ~(QH_ALIGNMENT - 1);
2340         }
2341         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2342                                         &udc->ep_qh_dma, GFP_KERNEL);
2343         if (!udc->ep_qh) {
2344                 ERR("malloc QHs for udc failed\n");
2345                 kfree(udc->eps);
2346                 return -1;
2347         }
2348
2349         udc->ep_qh_size = size;
2350
2351         /* Initialize ep0 status request structure */
2352         /* FIXME: fsl_alloc_request() ignores ep argument */
2353         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2354                         struct fsl_req, req);
2355         /* allocate a small amount of memory to get valid address */
2356         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2357         udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
2358
2359         udc->resume_state = USB_STATE_NOTATTACHED;
2360         udc->usb_state = USB_STATE_POWERED;
2361         udc->ep0_dir = 0;
2362         udc->remote_wakeup = 0; /* default to 0 on reset */
2363
2364         return 0;
2365 }
2366
2367 /*----------------------------------------------------------------
2368  * Setup the fsl_ep struct for eps
2369  * Link fsl_ep->ep to gadget->ep_list
2370  * ep0out is not used so do nothing here
2371  * ep0in should be taken care
2372  *--------------------------------------------------------------*/
2373 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2374                 char *name, int link)
2375 {
2376         struct fsl_ep *ep = &udc->eps[index];
2377
2378         ep->udc = udc;
2379         strcpy(ep->name, name);
2380         ep->ep.name = ep->name;
2381
2382         ep->ep.ops = &fsl_ep_ops;
2383         ep->stopped = 0;
2384
2385         /* for ep0: maxP defined in desc
2386          * for other eps, maxP is set by epautoconfig() called by gadget layer
2387          */
2388         ep->ep.maxpacket = (unsigned short) ~0;
2389
2390         /* the queue lists any req for this ep */
2391         INIT_LIST_HEAD(&ep->queue);
2392
2393         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2394         if (link)
2395                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2396         ep->gadget = &udc->gadget;
2397         ep->qh = &udc->ep_qh[index];
2398
2399         return 0;
2400 }
2401
2402 /* Driver probe function
2403  * all intialization operations implemented here except enabling usb_intr reg
2404  * board setup should have been done in the platform code
2405  */
2406 static int __init fsl_udc_probe(struct platform_device *pdev)
2407 {
2408         struct fsl_usb2_platform_data *pdata;
2409         struct resource *res;
2410         int ret = -ENODEV;
2411         unsigned int i;
2412         u32 dccparams;
2413
2414         if (strcmp(pdev->name, driver_name)) {
2415                 VDBG("Wrong device");
2416                 return -ENODEV;
2417         }
2418
2419         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2420         if (udc_controller == NULL) {
2421                 ERR("malloc udc failed\n");
2422                 return -ENOMEM;
2423         }
2424
2425         pdata = pdev->dev.platform_data;
2426         udc_controller->pdata = pdata;
2427         spin_lock_init(&udc_controller->lock);
2428         udc_controller->stopped = 1;
2429
2430 #ifdef CONFIG_USB_OTG
2431         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2432                 udc_controller->transceiver = otg_get_transceiver();
2433                 if (!udc_controller->transceiver) {
2434                         ERR("Can't find OTG driver!\n");
2435                         ret = -ENODEV;
2436                         goto err_kfree;
2437                 }
2438         }
2439 #endif
2440
2441         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2442         if (!res) {
2443                 ret = -ENXIO;
2444                 goto err_kfree;
2445         }
2446
2447         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2448                 if (!request_mem_region(res->start, res->end - res->start + 1,
2449                                         driver_name)) {
2450                         ERR("request mem region for %s failed\n", pdev->name);
2451                         ret = -EBUSY;
2452                         goto err_kfree;
2453                 }
2454         }
2455
2456         dr_regs = ioremap(res->start, resource_size(res));
2457         if (!dr_regs) {
2458                 ret = -ENOMEM;
2459                 goto err_release_mem_region;
2460         }
2461
2462         pdata->regs = (void *)dr_regs;
2463
2464         /*
2465          * do platform specific init: check the clock, grab/config pins, etc.
2466          */
2467         if (pdata->init && pdata->init(pdev)) {
2468                 ret = -ENODEV;
2469                 goto err_iounmap_noclk;
2470         }
2471
2472         /* Set accessors only after pdata->init() ! */
2473         if (pdata->big_endian_mmio) {
2474                 _fsl_readl = _fsl_readl_be;
2475                 _fsl_writel = _fsl_writel_be;
2476         } else {
2477                 _fsl_readl = _fsl_readl_le;
2478                 _fsl_writel = _fsl_writel_le;
2479         }
2480
2481 #ifndef CONFIG_ARCH_MXC
2482         if (pdata->have_sysif_regs)
2483                 usb_sys_regs = (struct usb_sys_interface *)
2484                                 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2485 #endif
2486
2487         /* Initialize USB clocks */
2488         ret = fsl_udc_clk_init(pdev);
2489         if (ret < 0)
2490                 goto err_iounmap_noclk;
2491
2492         /* Read Device Controller Capability Parameters register */
2493         dccparams = fsl_readl(&dr_regs->dccparams);
2494         if (!(dccparams & DCCPARAMS_DC)) {
2495                 ERR("This SOC doesn't support device role\n");
2496                 ret = -ENODEV;
2497                 goto err_iounmap;
2498         }
2499         /* Get max device endpoints */
2500         /* DEN is bidirectional ep number, max_ep doubles the number */
2501         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2502
2503         udc_controller->irq = platform_get_irq(pdev, 0);
2504         if (!udc_controller->irq) {
2505                 ret = -ENODEV;
2506                 goto err_iounmap;
2507         }
2508
2509         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2510                         driver_name, udc_controller);
2511         if (ret != 0) {
2512                 ERR("cannot request irq %d err %d\n",
2513                                 udc_controller->irq, ret);
2514                 goto err_iounmap;
2515         }
2516
2517         /* Initialize the udc structure including QH member and other member */
2518         if (struct_udc_setup(udc_controller, pdev)) {
2519                 ERR("Can't initialize udc data structure\n");
2520                 ret = -ENOMEM;
2521                 goto err_free_irq;
2522         }
2523
2524         if (!udc_controller->transceiver) {
2525                 /* initialize usb hw reg except for regs for EP,
2526                  * leave usbintr reg untouched */
2527                 dr_controller_setup(udc_controller);
2528         }
2529
2530         fsl_udc_clk_finalize(pdev);
2531
2532         /* Setup gadget structure */
2533         udc_controller->gadget.ops = &fsl_gadget_ops;
2534         udc_controller->gadget.is_dualspeed = 1;
2535         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2536         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2537         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2538         udc_controller->gadget.name = driver_name;
2539
2540         /* Setup gadget.dev and register with kernel */
2541         dev_set_name(&udc_controller->gadget.dev, "gadget");
2542         udc_controller->gadget.dev.release = fsl_udc_release;
2543         udc_controller->gadget.dev.parent = &pdev->dev;
2544         ret = device_register(&udc_controller->gadget.dev);
2545         if (ret < 0)
2546                 goto err_free_irq;
2547
2548         if (udc_controller->transceiver)
2549                 udc_controller->gadget.is_otg = 1;
2550
2551         /* setup QH and epctrl for ep0 */
2552         ep0_setup(udc_controller);
2553
2554         /* setup udc->eps[] for ep0 */
2555         struct_ep_setup(udc_controller, 0, "ep0", 0);
2556         /* for ep0: the desc defined here;
2557          * for other eps, gadget layer called ep_enable with defined desc
2558          */
2559         udc_controller->eps[0].desc = &fsl_ep0_desc;
2560         udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2561
2562         /* setup the udc->eps[] for non-control endpoints and link
2563          * to gadget.ep_list */
2564         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2565                 char name[14];
2566
2567                 sprintf(name, "ep%dout", i);
2568                 struct_ep_setup(udc_controller, i * 2, name, 1);
2569                 sprintf(name, "ep%din", i);
2570                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2571         }
2572
2573         /* use dma_pool for TD management */
2574         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2575                         sizeof(struct ep_td_struct),
2576                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2577         if (udc_controller->td_pool == NULL) {
2578                 ret = -ENOMEM;
2579                 goto err_unregister;
2580         }
2581         create_proc_file();
2582         return 0;
2583
2584 err_unregister:
2585         device_unregister(&udc_controller->gadget.dev);
2586 err_free_irq:
2587         free_irq(udc_controller->irq, udc_controller);
2588 err_iounmap:
2589         if (pdata->exit)
2590                 pdata->exit(pdev);
2591         fsl_udc_clk_release();
2592 err_iounmap_noclk:
2593         iounmap(dr_regs);
2594 err_release_mem_region:
2595         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2596                 release_mem_region(res->start, res->end - res->start + 1);
2597 err_kfree:
2598         kfree(udc_controller);
2599         udc_controller = NULL;
2600         return ret;
2601 }
2602
2603 /* Driver removal function
2604  * Free resources and finish pending transactions
2605  */
2606 static int __exit fsl_udc_remove(struct platform_device *pdev)
2607 {
2608         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2609         struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2610
2611         DECLARE_COMPLETION(done);
2612
2613         if (!udc_controller)
2614                 return -ENODEV;
2615         udc_controller->done = &done;
2616
2617         fsl_udc_clk_release();
2618
2619         /* DR has been stopped in usb_gadget_unregister_driver() */
2620         remove_proc_file();
2621
2622         /* Free allocated memory */
2623         kfree(udc_controller->status_req->req.buf);
2624         kfree(udc_controller->status_req);
2625         kfree(udc_controller->eps);
2626
2627         dma_pool_destroy(udc_controller->td_pool);
2628         free_irq(udc_controller->irq, udc_controller);
2629         iounmap(dr_regs);
2630         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2631                 release_mem_region(res->start, res->end - res->start + 1);
2632
2633         device_unregister(&udc_controller->gadget.dev);
2634         /* free udc --wait for the release() finished */
2635         wait_for_completion(&done);
2636
2637         /*
2638          * do platform specific un-initialization:
2639          * release iomux pins, etc.
2640          */
2641         if (pdata->exit)
2642                 pdata->exit(pdev);
2643
2644         return 0;
2645 }
2646
2647 /*-----------------------------------------------------------------
2648  * Modify Power management attributes
2649  * Used by OTG statemachine to disable gadget temporarily
2650  -----------------------------------------------------------------*/
2651 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2652 {
2653         dr_controller_stop(udc_controller);
2654         return 0;
2655 }
2656
2657 /*-----------------------------------------------------------------
2658  * Invoked on USB resume. May be called in_interrupt.
2659  * Here we start the DR controller and enable the irq
2660  *-----------------------------------------------------------------*/
2661 static int fsl_udc_resume(struct platform_device *pdev)
2662 {
2663         /* Enable DR irq reg and set controller Run */
2664         if (udc_controller->stopped) {
2665                 dr_controller_setup(udc_controller);
2666                 dr_controller_run(udc_controller);
2667         }
2668         udc_controller->usb_state = USB_STATE_ATTACHED;
2669         udc_controller->ep0_state = WAIT_FOR_SETUP;
2670         udc_controller->ep0_dir = 0;
2671         return 0;
2672 }
2673
2674 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2675 {
2676         struct fsl_udc *udc = udc_controller;
2677         u32 mode, usbcmd;
2678
2679         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2680
2681         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2682
2683         /*
2684          * If the controller is already stopped, then this must be a
2685          * PM suspend.  Remember this fact, so that we will leave the
2686          * controller stopped at PM resume time.
2687          */
2688         if (udc->stopped) {
2689                 pr_debug("gadget already stopped, leaving early\n");
2690                 udc->already_stopped = 1;
2691                 return 0;
2692         }
2693
2694         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2695                 pr_debug("gadget not in device mode, leaving early\n");
2696                 return 0;
2697         }
2698
2699         /* stop the controller */
2700         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2701         fsl_writel(usbcmd, &dr_regs->usbcmd);
2702
2703         udc->stopped = 1;
2704
2705         pr_info("USB Gadget suspended\n");
2706
2707         return 0;
2708 }
2709
2710 static int fsl_udc_otg_resume(struct device *dev)
2711 {
2712         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2713                  udc_controller->stopped, udc_controller->already_stopped);
2714
2715         /*
2716          * If the controller was stopped at suspend time, then
2717          * don't resume it now.
2718          */
2719         if (udc_controller->already_stopped) {
2720                 udc_controller->already_stopped = 0;
2721                 pr_debug("gadget was already stopped, leaving early\n");
2722                 return 0;
2723         }
2724
2725         pr_info("USB Gadget resume\n");
2726
2727         return fsl_udc_resume(NULL);
2728 }
2729
2730 /*-------------------------------------------------------------------------
2731         Register entry point for the peripheral controller driver
2732 --------------------------------------------------------------------------*/
2733
2734 static struct platform_driver udc_driver = {
2735         .remove  = __exit_p(fsl_udc_remove),
2736         /* these suspend and resume are not usb suspend and resume */
2737         .suspend = fsl_udc_suspend,
2738         .resume  = fsl_udc_resume,
2739         .driver  = {
2740                 .name = (char *)driver_name,
2741                 .owner = THIS_MODULE,
2742                 /* udc suspend/resume called from OTG driver */
2743                 .suspend = fsl_udc_otg_suspend,
2744                 .resume  = fsl_udc_otg_resume,
2745         },
2746 };
2747
2748 static int __init udc_init(void)
2749 {
2750         printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2751         return platform_driver_probe(&udc_driver, fsl_udc_probe);
2752 }
2753
2754 module_init(udc_init);
2755
2756 static void __exit udc_exit(void)
2757 {
2758         platform_driver_unregister(&udc_driver);
2759         printk(KERN_WARNING "%s unregistered\n", driver_desc);
2760 }
2761
2762 module_exit(udc_exit);
2763
2764 MODULE_DESCRIPTION(DRIVER_DESC);
2765 MODULE_AUTHOR(DRIVER_AUTHOR);
2766 MODULE_LICENSE("GPL");
2767 MODULE_ALIAS("platform:fsl-usb2-udc");