drivers/usb/gadget/amd5536udc.c

   1 /*
   2  * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
   3  *
   4  * Copyright (C) 2005-2007 AMD (http://www.amd.com)
   5  * Author: Thomas Dahlmann
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23  * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
  24  * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
  25  * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
  26  *
  27  * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
  28  * be used as host port) and UOC bits PAD_EN and APU are set (should be done
  29  * by BIOS init).
  30  *
  31  * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
  32  * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
  33  * can be used with gadget ether.
  34  */
  35
  36 /* debug control */
  37 /* #define UDC_VERBOSE */
  38
  39 /* Driver strings */
  40 #define UDC_MOD_DESCRIPTION             "AMD 5536 UDC - USB Device Controller"
  41 #define UDC_DRIVER_VERSION_STRING       "01.00.0206 - $Revision: #3 $"
  42
  43 /* system */
  44 #include <linux/module.h>
  45 #include <linux/pci.h>
  46 #include <linux/kernel.h>
  47 #include <linux/delay.h>
  48 #include <linux/ioport.h>
  49 #include <linux/sched.h>
  50 #include <linux/slab.h>
  51 #include <linux/errno.h>
  52 #include <linux/init.h>
  53 #include <linux/timer.h>
  54 #include <linux/list.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/ioctl.h>
  57 #include <linux/fs.h>
  58 #include <linux/dmapool.h>
  59 #include <linux/moduleparam.h>
  60 #include <linux/device.h>
  61 #include <linux/io.h>
  62 #include <linux/irq.h>
  63 #include <linux/prefetch.h>
  64
  65 #include <asm/byteorder.h>
  66 #include <asm/system.h>
  67 #include <asm/unaligned.h>
  68
  69 /* gadget stack */
  70 #include <linux/usb/ch9.h>
  71 #include <linux/usb/gadget.h>
  72
  73 /* udc specific */
  74 #include "amd5536udc.h"
  75
  76
  77 static void udc_tasklet_disconnect(unsigned long);
  78 static void empty_req_queue(struct udc_ep *);
  79 static int udc_probe(struct udc *dev);
  80 static void udc_basic_init(struct udc *dev);
  81 static void udc_setup_endpoints(struct udc *dev);
  82 static void udc_soft_reset(struct udc *dev);
  83 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
  84 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
  85 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
  86 static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
  87                                 unsigned long buf_len, gfp_t gfp_flags);
  88 static int udc_remote_wakeup(struct udc *dev);
  89 static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
  90 static void udc_pci_remove(struct pci_dev *pdev);
  91
  92 /* description */
  93 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
  94 static const char name[] = "amd5536udc";
  95
  96 /* structure to hold endpoint function pointers */
  97 static const struct usb_ep_ops udc_ep_ops;
  98
  99 /* received setup data */
 100 static union udc_setup_data setup_data;
 101
 102 /* pointer to device object */
 103 static struct udc *udc;
 104
 105 /* irq spin lock for soft reset */
 106 static DEFINE_SPINLOCK(udc_irq_spinlock);
 107 /* stall spin lock */
 108 static DEFINE_SPINLOCK(udc_stall_spinlock);
 109
 110 /*
 111 * slave mode: pending bytes in rx fifo after nyet,
 112 * used if EPIN irq came but no req was available
 113 */
 114 static unsigned int udc_rxfifo_pending;
 115
 116 /* count soft resets after suspend to avoid loop */
 117 static int soft_reset_occured;
 118 static int soft_reset_after_usbreset_occured;
 119
 120 /* timer */
 121 static struct timer_list udc_timer;
 122 static int stop_timer;
 123
 124 /* set_rde -- Is used to control enabling of RX DMA. Problem is
 125  * that UDC has only one bit (RDE) to enable/disable RX DMA for
 126  * all OUT endpoints. So we have to handle race conditions like
 127  * when OUT data reaches the fifo but no request was queued yet.
 128  * This cannot be solved by letting the RX DMA disabled until a
 129  * request gets queued because there may be other OUT packets
 130  * in the FIFO (important for not blocking control traffic).
 131  * The value of set_rde controls the correspondig timer.
 132  *
 133  * set_rde -1 == not used, means it is alloed to be set to 0 or 1
 134  * set_rde  0 == do not touch RDE, do no start the RDE timer
 135  * set_rde  1 == timer function will look whether FIFO has data
 136  * set_rde  2 == set by timer function to enable RX DMA on next call
 137  */
 138 static int set_rde = -1;
 139
 140 static DECLARE_COMPLETION(on_exit);
 141 static struct timer_list udc_pollstall_timer;
 142 static int stop_pollstall_timer;
 143 static DECLARE_COMPLETION(on_pollstall_exit);
 144
 145 /* tasklet for usb disconnect */
 146 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
 147                 (unsigned long) &udc);
 148
 149
 150 /* endpoint names used for print */
 151 static const char ep0_string[] = "ep0in";
 152 static const char *ep_string[] = {
 153         ep0_string,
 154         "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
 155         "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
 156         "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
 157         "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
 158         "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
 159         "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
 160         "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
 161 };
 162
 163 /* DMA usage flag */
 164 static int use_dma = 1;
 165 /* packet per buffer dma */
 166 static int use_dma_ppb = 1;
 167 /* with per descr. update */
 168 static int use_dma_ppb_du;
 169 /* buffer fill mode */
 170 static int use_dma_bufferfill_mode;
 171 /* full speed only mode */
 172 static int use_fullspeed;
 173 /* tx buffer size for high speed */
 174 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
 175
 176 /* module parameters */
 177 module_param(use_dma, bool, S_IRUGO);
 178 MODULE_PARM_DESC(use_dma, "true for DMA");
 179 module_param(use_dma_ppb, bool, S_IRUGO);
 180 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
 181 module_param(use_dma_ppb_du, bool, S_IRUGO);
 182 MODULE_PARM_DESC(use_dma_ppb_du,
 183         "true for DMA in packet per buffer mode with descriptor update");
 184 module_param(use_fullspeed, bool, S_IRUGO);
 185 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
 186
 187 /*---------------------------------------------------------------------------*/
 188 /* Prints UDC device registers and endpoint irq registers */
 189 static void print_regs(struct udc *dev)
 190 {
 191         DBG(dev, "------- Device registers -------\n");
 192         DBG(dev, "dev config     = %08x\n", readl(&dev->regs->cfg));
 193         DBG(dev, "dev control    = %08x\n", readl(&dev->regs->ctl));
 194         DBG(dev, "dev status     = %08x\n", readl(&dev->regs->sts));
 195         DBG(dev, "\n");
 196         DBG(dev, "dev int's      = %08x\n", readl(&dev->regs->irqsts));
 197         DBG(dev, "dev intmask    = %08x\n", readl(&dev->regs->irqmsk));
 198         DBG(dev, "\n");
 199         DBG(dev, "dev ep int's   = %08x\n", readl(&dev->regs->ep_irqsts));
 200         DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
 201         DBG(dev, "\n");
 202         DBG(dev, "USE DMA        = %d\n", use_dma);
 203         if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
 204                 DBG(dev, "DMA mode       = PPBNDU (packet per buffer "
 205                         "WITHOUT desc. update)\n");
 206                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
 207         } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
 208                 DBG(dev, "DMA mode       = PPBDU (packet per buffer "
 209                         "WITH desc. update)\n");
 210                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
 211         }
 212         if (use_dma && use_dma_bufferfill_mode) {
 213                 DBG(dev, "DMA mode       = BF (buffer fill mode)\n");
 214                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
 215         }
 216         if (!use_dma) {
 217                 dev_info(&dev->pdev->dev, "FIFO mode\n");
 218         }
 219         DBG(dev, "-------------------------------------------------------\n");
 220 }
 221
 222 /* Masks unused interrupts */
 223 static int udc_mask_unused_interrupts(struct udc *dev)
 224 {
 225         u32 tmp;
 226
 227         /* mask all dev interrupts */
 228         tmp =   AMD_BIT(UDC_DEVINT_SVC) |
 229                 AMD_BIT(UDC_DEVINT_ENUM) |
 230                 AMD_BIT(UDC_DEVINT_US) |
 231                 AMD_BIT(UDC_DEVINT_UR) |
 232                 AMD_BIT(UDC_DEVINT_ES) |
 233                 AMD_BIT(UDC_DEVINT_SI) |
 234                 AMD_BIT(UDC_DEVINT_SOF)|
 235                 AMD_BIT(UDC_DEVINT_SC);
 236         writel(tmp, &dev->regs->irqmsk);
 237
 238         /* mask all ep interrupts */
 239         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
 240
 241         return 0;
 242 }
 243
 244 /* Enables endpoint 0 interrupts */
 245 static int udc_enable_ep0_interrupts(struct udc *dev)
 246 {
 247         u32 tmp;
 248
 249         DBG(dev, "udc_enable_ep0_interrupts()\n");
 250
 251         /* read irq mask */
 252         tmp = readl(&dev->regs->ep_irqmsk);
 253         /* enable ep0 irq's */
 254         tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
 255                 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
 256         writel(tmp, &dev->regs->ep_irqmsk);
 257
 258         return 0;
 259 }
 260
 261 /* Enables device interrupts for SET_INTF and SET_CONFIG */
 262 static int udc_enable_dev_setup_interrupts(struct udc *dev)
 263 {
 264         u32 tmp;
 265
 266         DBG(dev, "enable device interrupts for setup data\n");
 267
 268         /* read irq mask */
 269         tmp = readl(&dev->regs->irqmsk);
 270
 271         /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
 272         tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
 273                 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
 274                 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
 275                 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
 276                 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
 277         writel(tmp, &dev->regs->irqmsk);
 278
 279         return 0;
 280 }
 281
 282 /* Calculates fifo start of endpoint based on preceding endpoints */
 283 static int udc_set_txfifo_addr(struct udc_ep *ep)
 284 {
 285         struct udc      *dev;
 286         u32 tmp;
 287         int i;
 288
 289         if (!ep || !(ep->in))
 290                 return -EINVAL;
 291
 292         dev = ep->dev;
 293         ep->txfifo = dev->txfifo;
 294
 295         /* traverse ep's */
 296         for (i = 0; i < ep->num; i++) {
 297                 if (dev->ep[i].regs) {
 298                         /* read fifo size */
 299                         tmp = readl(&dev->ep[i].regs->bufin_framenum);
 300                         tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
 301                         ep->txfifo += tmp;
 302                 }
 303         }
 304         return 0;
 305 }
 306
 307 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
 308 static u32 cnak_pending;
 309
 310 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
 311 {
 312         if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
 313                 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
 314                 cnak_pending |= 1 << (num);
 315                 ep->naking = 1;
 316         } else
 317                 cnak_pending = cnak_pending & (~(1 << (num)));
 318 }
 319
 320
 321 /* Enables endpoint, is called by gadget driver */
 322 static int
 323 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
 324 {
 325         struct udc_ep           *ep;
 326         struct udc              *dev;
 327         u32                     tmp;
 328         unsigned long           iflags;
 329         u8 udc_csr_epix;
 330         unsigned                maxpacket;
 331
 332         if (!usbep
 333                         || usbep->name == ep0_string
 334                         || !desc
 335                         || desc->bDescriptorType != USB_DT_ENDPOINT)
 336                 return -EINVAL;
 337
 338         ep = container_of(usbep, struct udc_ep, ep);
 339         dev = ep->dev;
 340
 341         DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
 342
 343         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
 344                 return -ESHUTDOWN;
 345
 346         spin_lock_irqsave(&dev->lock, iflags);
 347         ep->desc = desc;
 348
 349         ep->halted = 0;
 350
 351         /* set traffic type */
 352         tmp = readl(&dev->ep[ep->num].regs->ctl);
 353         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
 354         writel(tmp, &dev->ep[ep->num].regs->ctl);
 355
 356         /* set max packet size */
 357         maxpacket = le16_to_cpu(desc->wMaxPacketSize);
 358         tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
 359         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
 360         ep->ep.maxpacket = maxpacket;
 361         writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
 362
 363         /* IN ep */
 364         if (ep->in) {
 365
 366                 /* ep ix in UDC CSR register space */
 367                 udc_csr_epix = ep->num;
 368
 369                 /* set buffer size (tx fifo entries) */
 370                 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
 371                 /* double buffering: fifo size = 2 x max packet size */
 372                 tmp = AMD_ADDBITS(
 373                                 tmp,
 374                                 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
 375                                           / UDC_DWORD_BYTES,
 376                                 UDC_EPIN_BUFF_SIZE);
 377                 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
 378
 379                 /* calc. tx fifo base addr */
 380                 udc_set_txfifo_addr(ep);
 381
 382                 /* flush fifo */
 383                 tmp = readl(&ep->regs->ctl);
 384                 tmp |= AMD_BIT(UDC_EPCTL_F);
 385                 writel(tmp, &ep->regs->ctl);
 386
 387         /* OUT ep */
 388         } else {
 389                 /* ep ix in UDC CSR register space */
 390                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
 391
 392                 /* set max packet size UDC CSR  */
 393                 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
 394                 tmp = AMD_ADDBITS(tmp, maxpacket,
 395                                         UDC_CSR_NE_MAX_PKT);
 396                 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
 397
 398                 if (use_dma && !ep->in) {
 399                         /* alloc and init BNA dummy request */
 400                         ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
 401                         ep->bna_occurred = 0;
 402                 }
 403
 404                 if (ep->num != UDC_EP0OUT_IX)
 405                         dev->data_ep_enabled = 1;
 406         }
 407
 408         /* set ep values */
 409         tmp = readl(&dev->csr->ne[udc_csr_epix]);
 410         /* max packet */
 411         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
 412         /* ep number */
 413         tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
 414         /* ep direction */
 415         tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
 416         /* ep type */
 417         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
 418         /* ep config */
 419         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
 420         /* ep interface */
 421         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
 422         /* ep alt */
 423         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
 424         /* write reg */
 425         writel(tmp, &dev->csr->ne[udc_csr_epix]);
 426
 427         /* enable ep irq */
 428         tmp = readl(&dev->regs->ep_irqmsk);
 429         tmp &= AMD_UNMASK_BIT(ep->num);
 430         writel(tmp, &dev->regs->ep_irqmsk);
 431
 432         /*
 433          * clear NAK by writing CNAK
 434          * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
 435          */
 436         if (!use_dma || ep->in) {
 437                 tmp = readl(&ep->regs->ctl);
 438                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
 439                 writel(tmp, &ep->regs->ctl);
 440                 ep->naking = 0;
 441                 UDC_QUEUE_CNAK(ep, ep->num);
 442         }
 443         tmp = desc->bEndpointAddress;
 444         DBG(dev, "%s enabled\n", usbep->name);
 445
 446         spin_unlock_irqrestore(&dev->lock, iflags);
 447         return 0;
 448 }
 449
 450 /* Resets endpoint */
 451 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
 452 {
 453         u32             tmp;
 454
 455         VDBG(ep->dev, "ep-%d reset\n", ep->num);
 456         ep->desc = NULL;
 457         ep->ep.ops = &udc_ep_ops;
 458         INIT_LIST_HEAD(&ep->queue);
 459
 460         ep->ep.maxpacket = (u16) ~0;
 461         /* set NAK */
 462         tmp = readl(&ep->regs->ctl);
 463         tmp |= AMD_BIT(UDC_EPCTL_SNAK);
 464         writel(tmp, &ep->regs->ctl);
 465         ep->naking = 1;
 466
 467         /* disable interrupt */
 468         tmp = readl(&regs->ep_irqmsk);
 469         tmp |= AMD_BIT(ep->num);
 470         writel(tmp, &regs->ep_irqmsk);
 471
 472         if (ep->in) {
 473                 /* unset P and IN bit of potential former DMA */
 474                 tmp = readl(&ep->regs->ctl);
 475                 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
 476                 writel(tmp, &ep->regs->ctl);
 477
 478                 tmp = readl(&ep->regs->sts);
 479                 tmp |= AMD_BIT(UDC_EPSTS_IN);
 480                 writel(tmp, &ep->regs->sts);
 481
 482                 /* flush the fifo */
 483                 tmp = readl(&ep->regs->ctl);
 484                 tmp |= AMD_BIT(UDC_EPCTL_F);
 485                 writel(tmp, &ep->regs->ctl);
 486
 487         }
 488         /* reset desc pointer */
 489         writel(0, &ep->regs->desptr);
 490 }
 491
 492 /* Disables endpoint, is called by gadget driver */
 493 static int udc_ep_disable(struct usb_ep *usbep)
 494 {
 495         struct udc_ep   *ep = NULL;
 496         unsigned long   iflags;
 497
 498         if (!usbep)
 499                 return -EINVAL;
 500
 501         ep = container_of(usbep, struct udc_ep, ep);
 502         if (usbep->name == ep0_string || !ep->desc)
 503                 return -EINVAL;
 504
 505         DBG(ep->dev, "Disable ep-%d\n", ep->num);
 506
 507         spin_lock_irqsave(&ep->dev->lock, iflags);
 508         udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
 509         empty_req_queue(ep);
 510         ep_init(ep->dev->regs, ep);
 511         spin_unlock_irqrestore(&ep->dev->lock, iflags);
 512
 513         return 0;
 514 }
 515
 516 /* Allocates request packet, called by gadget driver */
 517 static struct usb_request *
 518 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
 519 {
 520         struct udc_request      *req;
 521         struct udc_data_dma     *dma_desc;
 522         struct udc_ep   *ep;
 523
 524         if (!usbep)
 525                 return NULL;
 526
 527         ep = container_of(usbep, struct udc_ep, ep);
 528
 529         VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
 530         req = kzalloc(sizeof(struct udc_request), gfp);
 531         if (!req)
 532                 return NULL;
 533
 534         req->req.dma = DMA_DONT_USE;
 535         INIT_LIST_HEAD(&req->queue);
 536
 537         if (ep->dma) {
 538                 /* ep0 in requests are allocated from data pool here */
 539                 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
 540                                                 &req->td_phys);
 541                 if (!dma_desc) {
 542                         kfree(req);
 543                         return NULL;
 544                 }
 545
 546                 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
 547                                 "td_phys = %lx\n",
 548                                 req, dma_desc,
 549                                 (unsigned long)req->td_phys);
 550                 /* prevent from using desc. - set HOST BUSY */
 551                 dma_desc->status = AMD_ADDBITS(dma_desc->status,
 552                                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
 553                                                 UDC_DMA_STP_STS_BS);
 554                 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
 555                 req->td_data = dma_desc;
 556                 req->td_data_last = NULL;
 557                 req->chain_len = 1;
 558         }
 559
 560         return &req->req;
 561 }
 562
 563 /* Frees request packet, called by gadget driver */
 564 static void
 565 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
 566 {
 567         struct udc_ep   *ep;
 568         struct udc_request      *req;
 569
 570         if (!usbep || !usbreq)
 571                 return;
 572
 573         ep = container_of(usbep, struct udc_ep, ep);
 574         req = container_of(usbreq, struct udc_request, req);
 575         VDBG(ep->dev, "free_req req=%p\n", req);
 576         BUG_ON(!list_empty(&req->queue));
 577         if (req->td_data) {
 578                 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
 579
 580                 /* free dma chain if created */
 581                 if (req->chain_len > 1) {
 582                         udc_free_dma_chain(ep->dev, req);
 583                 }
 584
 585                 pci_pool_free(ep->dev->data_requests, req->td_data,
 586                                                         req->td_phys);
 587         }
 588         kfree(req);
 589 }
 590
 591 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
 592 static void udc_init_bna_dummy(struct udc_request *req)
 593 {
 594         if (req) {
 595                 /* set last bit */
 596                 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
 597                 /* set next pointer to itself */
 598                 req->td_data->next = req->td_phys;
 599                 /* set HOST BUSY */
 600                 req->td_data->status
 601                         = AMD_ADDBITS(req->td_data->status,
 602                                         UDC_DMA_STP_STS_BS_DMA_DONE,
 603                                         UDC_DMA_STP_STS_BS);
 604 #ifdef UDC_VERBOSE
 605                 pr_debug("bna desc = %p, sts = %08x\n",
 606                         req->td_data, req->td_data->status);
 607 #endif
 608         }
 609 }
 610
 611 /* Allocate BNA dummy descriptor */
 612 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
 613 {
 614         struct udc_request *req = NULL;
 615         struct usb_request *_req = NULL;
 616
 617         /* alloc the dummy request */
 618         _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
 619         if (_req) {
 620                 req = container_of(_req, struct udc_request, req);
 621                 ep->bna_dummy_req = req;
 622                 udc_init_bna_dummy(req);
 623         }
 624         return req;
 625 }
 626
 627 /* Write data to TX fifo for IN packets */
 628 static void
 629 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
 630 {
 631         u8                      *req_buf;
 632         u32                     *buf;
 633         int                     i, j;
 634         unsigned                bytes = 0;
 635         unsigned                remaining = 0;
 636
 637         if (!req || !ep)
 638                 return;
 639
 640         req_buf = req->buf + req->actual;
 641         prefetch(req_buf);
 642         remaining = req->length - req->actual;
 643
 644         buf = (u32 *) req_buf;
 645
 646         bytes = ep->ep.maxpacket;
 647         if (bytes > remaining)
 648                 bytes = remaining;
 649
 650         /* dwords first */
 651         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) {
 652                 writel(*(buf + i), ep->txfifo);
 653         }
 654
 655         /* remaining bytes must be written by byte access */
 656         for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
 657                 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
 658                                                         ep->txfifo);
 659         }
 660
 661         /* dummy write confirm */
 662         writel(0, &ep->regs->confirm);
 663 }
 664
 665 /* Read dwords from RX fifo for OUT transfers */
 666 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
 667 {
 668         int i;
 669
 670         VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
 671
 672         for (i = 0; i < dwords; i++) {
 673                 *(buf + i) = readl(dev->rxfifo);
 674         }
 675         return 0;
 676 }
 677
 678 /* Read bytes from RX fifo for OUT transfers */
 679 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
 680 {
 681         int i, j;
 682         u32 tmp;
 683
 684         VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
 685
 686         /* dwords first */
 687         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) {
 688                 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
 689         }
 690
 691         /* remaining bytes must be read by byte access */
 692         if (bytes % UDC_DWORD_BYTES) {
 693                 tmp = readl(dev->rxfifo);
 694                 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
 695                         *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
 696                         tmp = tmp >> UDC_BITS_PER_BYTE;
 697                 }
 698         }
 699
 700         return 0;
 701 }
 702
 703 /* Read data from RX fifo for OUT transfers */
 704 static int
 705 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
 706 {
 707         u8 *buf;
 708         unsigned buf_space;
 709         unsigned bytes = 0;
 710         unsigned finished = 0;
 711
 712         /* received number bytes */
 713         bytes = readl(&ep->regs->sts);
 714         bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
 715
 716         buf_space = req->req.length - req->req.actual;
 717         buf = req->req.buf + req->req.actual;
 718         if (bytes > buf_space) {
 719                 if ((buf_space % ep->ep.maxpacket) != 0) {
 720                         DBG(ep->dev,
 721                                 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
 722                                 ep->ep.name, bytes, buf_space);
 723                         req->req.status = -EOVERFLOW;
 724                 }
 725                 bytes = buf_space;
 726         }
 727         req->req.actual += bytes;
 728
 729         /* last packet ? */
 730         if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
 731                 || ((req->req.actual == req->req.length) && !req->req.zero))
 732                 finished = 1;
 733
 734         /* read rx fifo bytes */
 735         VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
 736         udc_rxfifo_read_bytes(ep->dev, buf, bytes);
 737
 738         return finished;
 739 }
 740
 741 /* create/re-init a DMA descriptor or a DMA descriptor chain */
 742 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
 743 {
 744         int     retval = 0;
 745         u32     tmp;
 746
 747         VDBG(ep->dev, "prep_dma\n");
 748         VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
 749                         ep->num, req->td_data);
 750
 751         /* set buffer pointer */
 752         req->td_data->bufptr = req->req.dma;
 753
 754         /* set last bit */
 755         req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
 756
 757         /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
 758         if (use_dma_ppb) {
 759
 760                 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
 761                 if (retval != 0) {
 762                         if (retval == -ENOMEM)
 763                                 DBG(ep->dev, "Out of DMA memory\n");
 764                         return retval;
 765                 }
 766                 if (ep->in) {
 767                         if (req->req.length == ep->ep.maxpacket) {
 768                                 /* write tx bytes */
 769                                 req->td_data->status =
 770                                         AMD_ADDBITS(req->td_data->status,
 771                                                 ep->ep.maxpacket,
 772                                                 UDC_DMA_IN_STS_TXBYTES);
 773
 774                         }
 775                 }
 776
 777         }
 778
 779         if (ep->in) {
 780                 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
 781                                 "maxpacket=%d ep%d\n",
 782                                 use_dma_ppb, req->req.length,
 783                                 ep->ep.maxpacket, ep->num);
 784                 /*
 785                  * if bytes < max packet then tx bytes must
 786                  * be written in packet per buffer mode
 787                  */
 788                 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
 789                                 || ep->num == UDC_EP0OUT_IX
 790                                 || ep->num == UDC_EP0IN_IX) {
 791                         /* write tx bytes */
 792                         req->td_data->status =
 793                                 AMD_ADDBITS(req->td_data->status,
 794                                                 req->req.length,
 795                                                 UDC_DMA_IN_STS_TXBYTES);
 796                         /* reset frame num */
 797                         req->td_data->status =
 798                                 AMD_ADDBITS(req->td_data->status,
 799                                                 0,
 800                                                 UDC_DMA_IN_STS_FRAMENUM);
 801                 }
 802                 /* set HOST BUSY */
 803                 req->td_data->status =
 804                         AMD_ADDBITS(req->td_data->status,
 805                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
 806                                 UDC_DMA_STP_STS_BS);
 807         } else {
 808                 VDBG(ep->dev, "OUT set host ready\n");
 809                 /* set HOST READY */
 810                 req->td_data->status =
 811                         AMD_ADDBITS(req->td_data->status,
 812                                 UDC_DMA_STP_STS_BS_HOST_READY,
 813                                 UDC_DMA_STP_STS_BS);
 814
 815
 816                         /* clear NAK by writing CNAK */
 817                         if (ep->naking) {
 818                                 tmp = readl(&ep->regs->ctl);
 819                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
 820                                 writel(tmp, &ep->regs->ctl);
 821                                 ep->naking = 0;
 822                                 UDC_QUEUE_CNAK(ep, ep->num);
 823                         }
 824
 825         }
 826
 827         return retval;
 828 }
 829
 830 /* Completes request packet ... caller MUST hold lock */
 831 static void
 832 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
 833 __releases(ep->dev->lock)
 834 __acquires(ep->dev->lock)
 835 {
 836         struct udc              *dev;
 837         unsigned                halted;
 838
 839         VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
 840
 841         dev = ep->dev;
 842         /* unmap DMA */
 843         if (req->dma_mapping) {
 844                 if (ep->in)
 845                         pci_unmap_single(dev->pdev,
 846                                         req->req.dma,
 847                                         req->req.length,
 848                                         PCI_DMA_TODEVICE);
 849                 else
 850                         pci_unmap_single(dev->pdev,
 851                                         req->req.dma,
 852                                         req->req.length,
 853                                         PCI_DMA_FROMDEVICE);
 854                 req->dma_mapping = 0;
 855                 req->req.dma = DMA_DONT_USE;
 856         }
 857
 858         halted = ep->halted;
 859         ep->halted = 1;
 860
 861         /* set new status if pending */
 862         if (req->req.status == -EINPROGRESS)
 863                 req->req.status = sts;
 864
 865         /* remove from ep queue */
 866         list_del_init(&req->queue);
 867
 868         VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
 869                 &req->req, req->req.length, ep->ep.name, sts);
 870
 871         spin_unlock(&dev->lock);
 872         req->req.complete(&ep->ep, &req->req);
 873         spin_lock(&dev->lock);
 874         ep->halted = halted;
 875 }
 876
 877 /* frees pci pool descriptors of a DMA chain */
 878 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
 879 {
 880
 881         int ret_val = 0;
 882         struct udc_data_dma     *td;
 883         struct udc_data_dma     *td_last = NULL;
 884         unsigned int i;
 885
 886         DBG(dev, "free chain req = %p\n", req);
 887
 888         /* do not free first desc., will be done by free for request */
 889         td_last = req->td_data;
 890         td = phys_to_virt(td_last->next);
 891
 892         for (i = 1; i < req->chain_len; i++) {
 893
 894                 pci_pool_free(dev->data_requests, td,
 895                                 (dma_addr_t) td_last->next);
 896                 td_last = td;
 897                 td = phys_to_virt(td_last->next);
 898         }
 899
 900         return ret_val;
 901 }
 902
 903 /* Iterates to the end of a DMA chain and returns last descriptor */
 904 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
 905 {
 906         struct udc_data_dma     *td;
 907
 908         td = req->td_data;
 909         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
 910                 td = phys_to_virt(td->next);
 911         }
 912
 913         return td;
 914
 915 }
 916
 917 /* Iterates to the end of a DMA chain and counts bytes received */
 918 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
 919 {
 920         struct udc_data_dma     *td;
 921         u32 count;
 922
 923         td = req->td_data;
 924         /* received number bytes */
 925         count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
 926
 927         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
 928                 td = phys_to_virt(td->next);
 929                 /* received number bytes */
 930                 if (td) {
 931                         count += AMD_GETBITS(td->status,
 932                                 UDC_DMA_OUT_STS_RXBYTES);
 933                 }
 934         }
 935
 936         return count;
 937
 938 }
 939
 940 /* Creates or re-inits a DMA chain */
 941 static int udc_create_dma_chain(
 942         struct udc_ep *ep,
 943         struct udc_request *req,
 944         unsigned long buf_len, gfp_t gfp_flags
 945 )
 946 {
 947         unsigned long bytes = req->req.length;
 948         unsigned int i;
 949         dma_addr_t dma_addr;
 950         struct udc_data_dma     *td = NULL;
 951         struct udc_data_dma     *last = NULL;
 952         unsigned long txbytes;
 953         unsigned create_new_chain = 0;
 954         unsigned len;
 955
 956         VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
 957                         bytes, buf_len);
 958         dma_addr = DMA_DONT_USE;
 959
 960         /* unset L bit in first desc for OUT */
 961         if (!ep->in) {
 962                 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
 963         }
 964
 965         /* alloc only new desc's if not already available */
 966         len = req->req.length / ep->ep.maxpacket;
 967         if (req->req.length % ep->ep.maxpacket) {
 968                 len++;
 969         }
 970
 971         if (len > req->chain_len) {
 972                 /* shorter chain already allocated before */
 973                 if (req->chain_len > 1) {
 974                         udc_free_dma_chain(ep->dev, req);
 975                 }
 976                 req->chain_len = len;
 977                 create_new_chain = 1;
 978         }
 979
 980         td = req->td_data;
 981         /* gen. required number of descriptors and buffers */
 982         for (i = buf_len; i < bytes; i += buf_len) {
 983                 /* create or determine next desc. */
 984                 if (create_new_chain) {
 985
 986                         td = pci_pool_alloc(ep->dev->data_requests,
 987                                         gfp_flags, &dma_addr);
 988                         if (!td)
 989                                 return -ENOMEM;
 990
 991                         td->status = 0;
 992                 } else if (i == buf_len) {
 993                         /* first td */
 994                         td = (struct udc_data_dma *) phys_to_virt(
 995                                                 req->td_data->next);
 996                         td->status = 0;
 997                 } else {
 998                         td = (struct udc_data_dma *) phys_to_virt(last->next);
 999                         td->status = 0;
1000                 }
1001
1002
1003                 if (td)
1004                         td->bufptr = req->req.dma + i; /* assign buffer */
1005                 else
1006                         break;
1007
1008                 /* short packet ? */
1009                 if ((bytes - i) >= buf_len) {
1010                         txbytes = buf_len;
1011                 } else {
1012                         /* short packet */
1013                         txbytes = bytes - i;
1014                 }
1015
1016                 /* link td and assign tx bytes */
1017                 if (i == buf_len) {
1018                         if (create_new_chain) {
1019                                 req->td_data->next = dma_addr;
1020                         } else {
1021                                 /* req->td_data->next = virt_to_phys(td); */
1022                         }
1023                         /* write tx bytes */
1024                         if (ep->in) {
1025                                 /* first desc */
1026                                 req->td_data->status =
1027                                         AMD_ADDBITS(req->td_data->status,
1028                                                         ep->ep.maxpacket,
1029                                                         UDC_DMA_IN_STS_TXBYTES);
1030                                 /* second desc */
1031                                 td->status = AMD_ADDBITS(td->status,
1032                                                         txbytes,
1033                                                         UDC_DMA_IN_STS_TXBYTES);
1034                         }
1035                 } else {
1036                         if (create_new_chain) {
1037                                 last->next = dma_addr;
1038                         } else {
1039                                 /* last->next = virt_to_phys(td); */
1040                         }
1041                         if (ep->in) {
1042                                 /* write tx bytes */
1043                                 td->status = AMD_ADDBITS(td->status,
1044                                                         txbytes,
1045                                                         UDC_DMA_IN_STS_TXBYTES);
1046                         }
1047                 }
1048                 last = td;
1049         }
1050         /* set last bit */
1051         if (td) {
1052                 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1053                 /* last desc. points to itself */
1054                 req->td_data_last = td;
1055         }
1056
1057         return 0;
1058 }
1059
1060 /* Enabling RX DMA */
1061 static void udc_set_rde(struct udc *dev)
1062 {
1063         u32 tmp;
1064
1065         VDBG(dev, "udc_set_rde()\n");
1066         /* stop RDE timer */
1067         if (timer_pending(&udc_timer)) {
1068                 set_rde = 0;
1069                 mod_timer(&udc_timer, jiffies - 1);
1070         }
1071         /* set RDE */
1072         tmp = readl(&dev->regs->ctl);
1073         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1074         writel(tmp, &dev->regs->ctl);
1075 }
1076
1077 /* Queues a request packet, called by gadget driver */
1078 static int
1079 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1080 {
1081         int                     retval = 0;
1082         u8                      open_rxfifo = 0;
1083         unsigned long           iflags;
1084         struct udc_ep           *ep;
1085         struct udc_request      *req;
1086         struct udc              *dev;
1087         u32                     tmp;
1088
1089         /* check the inputs */
1090         req = container_of(usbreq, struct udc_request, req);
1091
1092         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1093                         || !list_empty(&req->queue))
1094                 return -EINVAL;
1095
1096         ep = container_of(usbep, struct udc_ep, ep);
1097         if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1098                 return -EINVAL;
1099
1100         VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1101         dev = ep->dev;
1102
1103         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1104                 return -ESHUTDOWN;
1105
1106         /* map dma (usually done before) */
1107         if (ep->dma && usbreq->length != 0
1108                         && (usbreq->dma == DMA_DONT_USE || usbreq->dma == 0)) {
1109                 VDBG(dev, "DMA map req %p\n", req);
1110                 if (ep->in)
1111                         usbreq->dma = pci_map_single(dev->pdev,
1112                                                 usbreq->buf,
1113                                                 usbreq->length,
1114                                                 PCI_DMA_TODEVICE);
1115                 else
1116                         usbreq->dma = pci_map_single(dev->pdev,
1117                                                 usbreq->buf,
1118                                                 usbreq->length,
1119                                                 PCI_DMA_FROMDEVICE);
1120                 req->dma_mapping = 1;
1121         }
1122
1123         VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1124                         usbep->name, usbreq, usbreq->length,
1125                         req->td_data, usbreq->buf);
1126
1127         spin_lock_irqsave(&dev->lock, iflags);
1128         usbreq->actual = 0;
1129         usbreq->status = -EINPROGRESS;
1130         req->dma_done = 0;
1131
1132         /* on empty queue just do first transfer */
1133         if (list_empty(&ep->queue)) {
1134                 /* zlp */
1135                 if (usbreq->length == 0) {
1136                         /* IN zlp's are handled by hardware */
1137                         complete_req(ep, req, 0);
1138                         VDBG(dev, "%s: zlp\n", ep->ep.name);
1139                         /*
1140                          * if set_config or set_intf is waiting for ack by zlp
1141                          * then set CSR_DONE
1142                          */
1143                         if (dev->set_cfg_not_acked) {
1144                                 tmp = readl(&dev->regs->ctl);
1145                                 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1146                                 writel(tmp, &dev->regs->ctl);
1147                                 dev->set_cfg_not_acked = 0;
1148                         }
1149                         /* setup command is ACK'ed now by zlp */
1150                         if (dev->waiting_zlp_ack_ep0in) {
1151                                 /* clear NAK by writing CNAK in EP0_IN */
1152                                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1153                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1154                                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1155                                 dev->ep[UDC_EP0IN_IX].naking = 0;
1156                                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1157                                                         UDC_EP0IN_IX);
1158                                 dev->waiting_zlp_ack_ep0in = 0;
1159                         }
1160                         goto finished;
1161                 }
1162                 if (ep->dma) {
1163                         retval = prep_dma(ep, req, gfp);
1164                         if (retval != 0)
1165                                 goto finished;
1166                         /* write desc pointer to enable DMA */
1167                         if (ep->in) {
1168                                 /* set HOST READY */
1169                                 req->td_data->status =
1170                                         AMD_ADDBITS(req->td_data->status,
1171                                                 UDC_DMA_IN_STS_BS_HOST_READY,
1172                                                 UDC_DMA_IN_STS_BS);
1173                         }
1174
1175                         /* disabled rx dma while descriptor update */
1176                         if (!ep->in) {
1177                                 /* stop RDE timer */
1178                                 if (timer_pending(&udc_timer)) {
1179                                         set_rde = 0;
1180                                         mod_timer(&udc_timer, jiffies - 1);
1181                                 }
1182                                 /* clear RDE */
1183                                 tmp = readl(&dev->regs->ctl);
1184                                 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1185                                 writel(tmp, &dev->regs->ctl);
1186                                 open_rxfifo = 1;
1187
1188                                 /*
1189                                  * if BNA occurred then let BNA dummy desc.
1190                                  * point to current desc.
1191                                  */
1192                                 if (ep->bna_occurred) {
1193                                         VDBG(dev, "copy to BNA dummy desc.\n");
1194                                         memcpy(ep->bna_dummy_req->td_data,
1195                                                 req->td_data,
1196                                                 sizeof(struct udc_data_dma));
1197                                 }
1198                         }
1199                         /* write desc pointer */
1200                         writel(req->td_phys, &ep->regs->desptr);
1201
1202                         /* clear NAK by writing CNAK */
1203                         if (ep->naking) {
1204                                 tmp = readl(&ep->regs->ctl);
1205                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1206                                 writel(tmp, &ep->regs->ctl);
1207                                 ep->naking = 0;
1208                                 UDC_QUEUE_CNAK(ep, ep->num);
1209                         }
1210
1211                         if (ep->in) {
1212                                 /* enable ep irq */
1213                                 tmp = readl(&dev->regs->ep_irqmsk);
1214                                 tmp &= AMD_UNMASK_BIT(ep->num);
1215                                 writel(tmp, &dev->regs->ep_irqmsk);
1216                         }
1217                 } else if (ep->in) {
1218                                 /* enable ep irq */
1219                                 tmp = readl(&dev->regs->ep_irqmsk);
1220                                 tmp &= AMD_UNMASK_BIT(ep->num);
1221                                 writel(tmp, &dev->regs->ep_irqmsk);
1222                         }
1223
1224         } else if (ep->dma) {
1225
1226                 /*
1227                  * prep_dma not used for OUT ep's, this is not possible
1228                  * for PPB modes, because of chain creation reasons
1229                  */
1230                 if (ep->in) {
1231                         retval = prep_dma(ep, req, gfp);
1232                         if (retval != 0)
1233                                 goto finished;
1234                 }
1235         }
1236         VDBG(dev, "list_add\n");
1237         /* add request to ep queue */
1238         if (req) {
1239
1240                 list_add_tail(&req->queue, &ep->queue);
1241
1242                 /* open rxfifo if out data queued */
1243                 if (open_rxfifo) {
1244                         /* enable DMA */
1245                         req->dma_going = 1;
1246                         udc_set_rde(dev);
1247                         if (ep->num != UDC_EP0OUT_IX)
1248                                 dev->data_ep_queued = 1;
1249                 }
1250                 /* stop OUT naking */
1251                 if (!ep->in) {
1252                         if (!use_dma && udc_rxfifo_pending) {
1253                                 DBG(dev, "udc_queue(): pending bytes in "
1254                                         "rxfifo after nyet\n");
1255                                 /*
1256                                  * read pending bytes afer nyet:
1257                                  * referring to isr
1258                                  */
1259                                 if (udc_rxfifo_read(ep, req)) {
1260                                         /* finish */
1261                                         complete_req(ep, req, 0);
1262                                 }
1263                                 udc_rxfifo_pending = 0;
1264
1265                         }
1266                 }
1267         }
1268
1269 finished:
1270         spin_unlock_irqrestore(&dev->lock, iflags);
1271         return retval;
1272 }
1273
1274 /* Empty request queue of an endpoint; caller holds spinlock */
1275 static void empty_req_queue(struct udc_ep *ep)
1276 {
1277         struct udc_request      *req;
1278
1279         ep->halted = 1;
1280         while (!list_empty(&ep->queue)) {
1281                 req = list_entry(ep->queue.next,
1282                         struct udc_request,
1283                         queue);
1284                 complete_req(ep, req, -ESHUTDOWN);
1285         }
1286 }
1287
1288 /* Dequeues a request packet, called by gadget driver */
1289 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1290 {
1291         struct udc_ep           *ep;
1292         struct udc_request      *req;
1293         unsigned                halted;
1294         unsigned long           iflags;
1295
1296         ep = container_of(usbep, struct udc_ep, ep);
1297         if (!usbep || !usbreq || (!ep->desc && (ep->num != 0
1298                                 && ep->num != UDC_EP0OUT_IX)))
1299                 return -EINVAL;
1300
1301         req = container_of(usbreq, struct udc_request, req);
1302
1303         spin_lock_irqsave(&ep->dev->lock, iflags);
1304         halted = ep->halted;
1305         ep->halted = 1;
1306         /* request in processing or next one */
1307         if (ep->queue.next == &req->queue) {
1308                 if (ep->dma && req->dma_going) {
1309                         if (ep->in)
1310                                 ep->cancel_transfer = 1;
1311                         else {
1312                                 u32 tmp;
1313                                 u32 dma_sts;
1314                                 /* stop potential receive DMA */
1315                                 tmp = readl(&udc->regs->ctl);
1316                                 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1317                                                         &udc->regs->ctl);
1318                                 /*
1319                                  * Cancel transfer later in ISR
1320                                  * if descriptor was touched.
1321                                  */
1322                                 dma_sts = AMD_GETBITS(req->td_data->status,
1323                                                         UDC_DMA_OUT_STS_BS);
1324                                 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1325                                         ep->cancel_transfer = 1;
1326                                 else {
1327                                         udc_init_bna_dummy(ep->req);
1328                                         writel(ep->bna_dummy_req->td_phys,
1329                                                 &ep->regs->desptr);
1330                                 }
1331                                 writel(tmp, &udc->regs->ctl);
1332                         }
1333                 }
1334         }
1335         complete_req(ep, req, -ECONNRESET);
1336         ep->halted = halted;
1337
1338         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1339         return 0;
1340 }
1341
1342 /* Halt or clear halt of endpoint */
1343 static int
1344 udc_set_halt(struct usb_ep *usbep, int halt)
1345 {
1346         struct udc_ep   *ep;
1347         u32 tmp;
1348         unsigned long iflags;
1349         int retval = 0;
1350
1351         if (!usbep)
1352                 return -EINVAL;
1353
1354         pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1355
1356         ep = container_of(usbep, struct udc_ep, ep);
1357         if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1358                 return -EINVAL;
1359         if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1360                 return -ESHUTDOWN;
1361
1362         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1363         /* halt or clear halt */
1364         if (halt) {
1365                 if (ep->num == 0)
1366                         ep->dev->stall_ep0in = 1;
1367                 else {
1368                         /*
1369                          * set STALL
1370                          * rxfifo empty not taken into acount
1371                          */
1372                         tmp = readl(&ep->regs->ctl);
1373                         tmp |= AMD_BIT(UDC_EPCTL_S);
1374                         writel(tmp, &ep->regs->ctl);
1375                         ep->halted = 1;
1376
1377                         /* setup poll timer */
1378                         if (!timer_pending(&udc_pollstall_timer)) {
1379                                 udc_pollstall_timer.expires = jiffies +
1380                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1381                                         / (1000 * 1000);
1382                                 if (!stop_pollstall_timer) {
1383                                         DBG(ep->dev, "start polltimer\n");
1384                                         add_timer(&udc_pollstall_timer);
1385                                 }
1386                         }
1387                 }
1388         } else {
1389                 /* ep is halted by set_halt() before */
1390                 if (ep->halted) {
1391                         tmp = readl(&ep->regs->ctl);
1392                         /* clear stall bit */
1393                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1394                         /* clear NAK by writing CNAK */
1395                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1396                         writel(tmp, &ep->regs->ctl);
1397                         ep->halted = 0;
1398                         UDC_QUEUE_CNAK(ep, ep->num);
1399                 }
1400         }
1401         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1402         return retval;
1403 }
1404
1405 /* gadget interface */
1406 static const struct usb_ep_ops udc_ep_ops = {
1407         .enable         = udc_ep_enable,
1408         .disable        = udc_ep_disable,
1409
1410         .alloc_request  = udc_alloc_request,
1411         .free_request   = udc_free_request,
1412
1413         .queue          = udc_queue,
1414         .dequeue        = udc_dequeue,
1415
1416         .set_halt       = udc_set_halt,
1417         /* fifo ops not implemented */
1418 };
1419
1420 /*-------------------------------------------------------------------------*/
1421
1422 /* Get frame counter (not implemented) */
1423 static int udc_get_frame(struct usb_gadget *gadget)
1424 {
1425         return -EOPNOTSUPP;
1426 }
1427
1428 /* Remote wakeup gadget interface */
1429 static int udc_wakeup(struct usb_gadget *gadget)
1430 {
1431         struct udc              *dev;
1432
1433         if (!gadget)
1434                 return -EINVAL;
1435         dev = container_of(gadget, struct udc, gadget);
1436         udc_remote_wakeup(dev);
1437
1438         return 0;
1439 }
1440
1441 /* gadget operations */
1442 static const struct usb_gadget_ops udc_ops = {
1443         .wakeup         = udc_wakeup,
1444         .get_frame      = udc_get_frame,
1445 };
1446
1447 /* Setups endpoint parameters, adds endpoints to linked list */
1448 static void make_ep_lists(struct udc *dev)
1449 {
1450         /* make gadget ep lists */
1451         INIT_LIST_HEAD(&dev->gadget.ep_list);
1452         list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1453                                                 &dev->gadget.ep_list);
1454         list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1455                                                 &dev->gadget.ep_list);
1456         list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1457                                                 &dev->gadget.ep_list);
1458
1459         /* fifo config */
1460         dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1461         if (dev->gadget.speed == USB_SPEED_FULL)
1462                 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1463         else if (dev->gadget.speed == USB_SPEED_HIGH)
1464                 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1465         dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1466 }
1467
1468 /* init registers at driver load time */
1469 static int startup_registers(struct udc *dev)
1470 {
1471         u32 tmp;
1472
1473         /* init controller by soft reset */
1474         udc_soft_reset(dev);
1475
1476         /* mask not needed interrupts */
1477         udc_mask_unused_interrupts(dev);
1478
1479         /* put into initial config */
1480         udc_basic_init(dev);
1481         /* link up all endpoints */
1482         udc_setup_endpoints(dev);
1483
1484         /* program speed */
1485         tmp = readl(&dev->regs->cfg);
1486         if (use_fullspeed) {
1487                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1488         } else {
1489                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1490         }
1491         writel(tmp, &dev->regs->cfg);
1492
1493         return 0;
1494 }
1495
1496 /* Inits UDC context */
1497 static void udc_basic_init(struct udc *dev)
1498 {
1499         u32     tmp;
1500
1501         DBG(dev, "udc_basic_init()\n");
1502
1503         dev->gadget.speed = USB_SPEED_UNKNOWN;
1504
1505         /* stop RDE timer */
1506         if (timer_pending(&udc_timer)) {
1507                 set_rde = 0;
1508                 mod_timer(&udc_timer, jiffies - 1);
1509         }
1510         /* stop poll stall timer */
1511         if (timer_pending(&udc_pollstall_timer)) {
1512                 mod_timer(&udc_pollstall_timer, jiffies - 1);
1513         }
1514         /* disable DMA */
1515         tmp = readl(&dev->regs->ctl);
1516         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1517         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1518         writel(tmp, &dev->regs->ctl);
1519
1520         /* enable dynamic CSR programming */
1521         tmp = readl(&dev->regs->cfg);
1522         tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1523         /* set self powered */
1524         tmp |= AMD_BIT(UDC_DEVCFG_SP);
1525         /* set remote wakeupable */
1526         tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1527         writel(tmp, &dev->regs->cfg);
1528
1529         make_ep_lists(dev);
1530
1531         dev->data_ep_enabled = 0;
1532         dev->data_ep_queued = 0;
1533 }
1534
1535 /* Sets initial endpoint parameters */
1536 static void udc_setup_endpoints(struct udc *dev)
1537 {
1538         struct udc_ep   *ep;
1539         u32     tmp;
1540         u32     reg;
1541
1542         DBG(dev, "udc_setup_endpoints()\n");
1543
1544         /* read enum speed */
1545         tmp = readl(&dev->regs->sts);
1546         tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1547         if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH) {
1548                 dev->gadget.speed = USB_SPEED_HIGH;
1549         } else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL) {
1550                 dev->gadget.speed = USB_SPEED_FULL;
1551         }
1552
1553         /* set basic ep parameters */
1554         for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1555                 ep = &dev->ep[tmp];
1556                 ep->dev = dev;
1557                 ep->ep.name = ep_string[tmp];
1558                 ep->num = tmp;
1559                 /* txfifo size is calculated at enable time */
1560                 ep->txfifo = dev->txfifo;
1561
1562                 /* fifo size */
1563                 if (tmp < UDC_EPIN_NUM) {
1564                         ep->fifo_depth = UDC_TXFIFO_SIZE;
1565                         ep->in = 1;
1566                 } else {
1567                         ep->fifo_depth = UDC_RXFIFO_SIZE;
1568                         ep->in = 0;
1569
1570                 }
1571                 ep->regs = &dev->ep_regs[tmp];
1572                 /*
1573                  * ep will be reset only if ep was not enabled before to avoid
1574                  * disabling ep interrupts when ENUM interrupt occurs but ep is
1575                  * not enabled by gadget driver
1576                  */
1577                 if (!ep->desc) {
1578                         ep_init(dev->regs, ep);
1579                 }
1580
1581                 if (use_dma) {
1582                         /*
1583                          * ep->dma is not really used, just to indicate that
1584                          * DMA is active: remove this
1585                          * dma regs = dev control regs
1586                          */
1587                         ep->dma = &dev->regs->ctl;
1588
1589                         /* nak OUT endpoints until enable - not for ep0 */
1590                         if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1591                                                 && tmp > UDC_EPIN_NUM) {
1592                                 /* set NAK */
1593                                 reg = readl(&dev->ep[tmp].regs->ctl);
1594                                 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1595                                 writel(reg, &dev->ep[tmp].regs->ctl);
1596                                 dev->ep[tmp].naking = 1;
1597
1598                         }
1599                 }
1600         }
1601         /* EP0 max packet */
1602         if (dev->gadget.speed == USB_SPEED_FULL) {
1603                 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
1604                 dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
1605                                                 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1606         } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1607                 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
1608                 dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
1609         }
1610
1611         /*
1612          * with suspend bug workaround, ep0 params for gadget driver
1613          * are set at gadget driver bind() call
1614          */
1615         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1616         dev->ep[UDC_EP0IN_IX].halted = 0;
1617         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1618
1619         /* init cfg/alt/int */
1620         dev->cur_config = 0;
1621         dev->cur_intf = 0;
1622         dev->cur_alt = 0;
1623 }
1624
1625 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1626 static void usb_connect(struct udc *dev)
1627 {
1628
1629         dev_info(&dev->pdev->dev, "USB Connect\n");
1630
1631         dev->connected = 1;
1632
1633         /* put into initial config */
1634         udc_basic_init(dev);
1635
1636         /* enable device setup interrupts */
1637         udc_enable_dev_setup_interrupts(dev);
1638 }
1639
1640 /*
1641  * Calls gadget with disconnect event and resets the UDC and makes
1642  * initial bringup to be ready for ep0 events
1643  */
1644 static void usb_disconnect(struct udc *dev)
1645 {
1646
1647         dev_info(&dev->pdev->dev, "USB Disconnect\n");
1648
1649         dev->connected = 0;
1650
1651         /* mask interrupts */
1652         udc_mask_unused_interrupts(dev);
1653
1654         /* REVISIT there doesn't seem to be a point to having this
1655          * talk to a tasklet ... do it directly, we already hold
1656          * the spinlock needed to process the disconnect.
1657          */
1658
1659         tasklet_schedule(&disconnect_tasklet);
1660 }
1661
1662 /* Tasklet for disconnect to be outside of interrupt context */
1663 static void udc_tasklet_disconnect(unsigned long par)
1664 {
1665         struct udc *dev = (struct udc *)(*((struct udc **) par));
1666         u32 tmp;
1667
1668         DBG(dev, "Tasklet disconnect\n");
1669         spin_lock_irq(&dev->lock);
1670
1671         if (dev->driver) {
1672                 spin_unlock(&dev->lock);
1673                 dev->driver->disconnect(&dev->gadget);
1674                 spin_lock(&dev->lock);
1675
1676                 /* empty queues */
1677                 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1678                         empty_req_queue(&dev->ep[tmp]);
1679                 }
1680
1681         }
1682
1683         /* disable ep0 */
1684         ep_init(dev->regs,
1685                         &dev->ep[UDC_EP0IN_IX]);
1686
1687
1688         if (!soft_reset_occured) {
1689                 /* init controller by soft reset */
1690                 udc_soft_reset(dev);
1691                 soft_reset_occured++;
1692         }
1693
1694         /* re-enable dev interrupts */
1695         udc_enable_dev_setup_interrupts(dev);
1696         /* back to full speed ? */
1697         if (use_fullspeed) {
1698                 tmp = readl(&dev->regs->cfg);
1699                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1700                 writel(tmp, &dev->regs->cfg);
1701         }
1702
1703         spin_unlock_irq(&dev->lock);
1704 }
1705
1706 /* Reset the UDC core */
1707 static void udc_soft_reset(struct udc *dev)
1708 {
1709         unsigned long   flags;
1710
1711         DBG(dev, "Soft reset\n");
1712         /*
1713          * reset possible waiting interrupts, because int.
1714          * status is lost after soft reset,
1715          * ep int. status reset
1716          */
1717         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1718         /* device int. status reset */
1719         writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1720
1721         spin_lock_irqsave(&udc_irq_spinlock, flags);
1722         writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1723         readl(&dev->regs->cfg);
1724         spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1725
1726 }
1727
1728 /* RDE timer callback to set RDE bit */
1729 static void udc_timer_function(unsigned long v)
1730 {
1731         u32 tmp;
1732
1733         spin_lock_irq(&udc_irq_spinlock);
1734
1735         if (set_rde > 0) {
1736                 /*
1737                  * open the fifo if fifo was filled on last timer call
1738                  * conditionally
1739                  */
1740                 if (set_rde > 1) {
1741                         /* set RDE to receive setup data */
1742                         tmp = readl(&udc->regs->ctl);
1743                         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1744                         writel(tmp, &udc->regs->ctl);
1745                         set_rde = -1;
1746                 } else if (readl(&udc->regs->sts)
1747                                 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1748                         /*
1749                          * if fifo empty setup polling, do not just
1750                          * open the fifo
1751                          */
1752                         udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1753                         if (!stop_timer) {
1754                                 add_timer(&udc_timer);
1755                         }
1756                 } else {
1757                         /*
1758                          * fifo contains data now, setup timer for opening
1759                          * the fifo when timer expires to be able to receive
1760                          * setup packets, when data packets gets queued by
1761                          * gadget layer then timer will forced to expire with
1762                          * set_rde=0 (RDE is set in udc_queue())
1763                          */
1764                         set_rde++;
1765                         /* debug: lhadmot_timer_start = 221070 */
1766                         udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1767                         if (!stop_timer) {
1768                                 add_timer(&udc_timer);
1769                         }
1770                 }
1771
1772         } else
1773                 set_rde = -1; /* RDE was set by udc_queue() */
1774         spin_unlock_irq(&udc_irq_spinlock);
1775         if (stop_timer)
1776                 complete(&on_exit);
1777
1778 }
1779
1780 /* Handle halt state, used in stall poll timer */
1781 static void udc_handle_halt_state(struct udc_ep *ep)
1782 {
1783         u32 tmp;
1784         /* set stall as long not halted */
1785         if (ep->halted == 1) {
1786                 tmp = readl(&ep->regs->ctl);
1787                 /* STALL cleared ? */
1788                 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1789                         /*
1790                          * FIXME: MSC spec requires that stall remains
1791                          * even on receivng of CLEAR_FEATURE HALT. So
1792                          * we would set STALL again here to be compliant.
1793                          * But with current mass storage drivers this does
1794                          * not work (would produce endless host retries).
1795                          * So we clear halt on CLEAR_FEATURE.
1796                          *
1797                         DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1798                         tmp |= AMD_BIT(UDC_EPCTL_S);
1799                         writel(tmp, &ep->regs->ctl);*/
1800
1801                         /* clear NAK by writing CNAK */
1802                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1803                         writel(tmp, &ep->regs->ctl);
1804                         ep->halted = 0;
1805                         UDC_QUEUE_CNAK(ep, ep->num);
1806                 }
1807         }
1808 }
1809
1810 /* Stall timer callback to poll S bit and set it again after */
1811 static void udc_pollstall_timer_function(unsigned long v)
1812 {
1813         struct udc_ep *ep;
1814         int halted = 0;
1815
1816         spin_lock_irq(&udc_stall_spinlock);
1817         /*
1818          * only one IN and OUT endpoints are handled
1819          * IN poll stall
1820          */
1821         ep = &udc->ep[UDC_EPIN_IX];
1822         udc_handle_halt_state(ep);
1823         if (ep->halted)
1824                 halted = 1;
1825         /* OUT poll stall */
1826         ep = &udc->ep[UDC_EPOUT_IX];
1827         udc_handle_halt_state(ep);
1828         if (ep->halted)
1829                 halted = 1;
1830
1831         /* setup timer again when still halted */
1832         if (!stop_pollstall_timer && halted) {
1833                 udc_pollstall_timer.expires = jiffies +
1834                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1835                                         / (1000 * 1000);
1836                 add_timer(&udc_pollstall_timer);
1837         }
1838         spin_unlock_irq(&udc_stall_spinlock);
1839
1840         if (stop_pollstall_timer)
1841                 complete(&on_pollstall_exit);
1842 }
1843
1844 /* Inits endpoint 0 so that SETUP packets are processed */
1845 static void activate_control_endpoints(struct udc *dev)
1846 {
1847         u32 tmp;
1848
1849         DBG(dev, "activate_control_endpoints\n");
1850
1851         /* flush fifo */
1852         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1853         tmp |= AMD_BIT(UDC_EPCTL_F);
1854         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1855
1856         /* set ep0 directions */
1857         dev->ep[UDC_EP0IN_IX].in = 1;
1858         dev->ep[UDC_EP0OUT_IX].in = 0;
1859
1860         /* set buffer size (tx fifo entries) of EP0_IN */
1861         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1862         if (dev->gadget.speed == USB_SPEED_FULL)
1863                 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1864                                         UDC_EPIN_BUFF_SIZE);
1865         else if (dev->gadget.speed == USB_SPEED_HIGH)
1866                 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1867                                         UDC_EPIN_BUFF_SIZE);
1868         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1869
1870         /* set max packet size of EP0_IN */
1871         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1872         if (dev->gadget.speed == USB_SPEED_FULL)
1873                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1874                                         UDC_EP_MAX_PKT_SIZE);
1875         else if (dev->gadget.speed == USB_SPEED_HIGH)
1876                 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1877                                 UDC_EP_MAX_PKT_SIZE);
1878         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1879
1880         /* set max packet size of EP0_OUT */
1881         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1882         if (dev->gadget.speed == USB_SPEED_FULL)
1883                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1884                                         UDC_EP_MAX_PKT_SIZE);
1885         else if (dev->gadget.speed == USB_SPEED_HIGH)
1886                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1887                                         UDC_EP_MAX_PKT_SIZE);
1888         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1889
1890         /* set max packet size of EP0 in UDC CSR */
1891         tmp = readl(&dev->csr->ne[0]);
1892         if (dev->gadget.speed == USB_SPEED_FULL)
1893                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1894                                         UDC_CSR_NE_MAX_PKT);
1895         else if (dev->gadget.speed == USB_SPEED_HIGH)
1896                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1897                                         UDC_CSR_NE_MAX_PKT);
1898         writel(tmp, &dev->csr->ne[0]);
1899
1900         if (use_dma) {
1901                 dev->ep[UDC_EP0OUT_IX].td->status |=
1902                         AMD_BIT(UDC_DMA_OUT_STS_L);
1903                 /* write dma desc address */
1904                 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1905                         &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1906                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1907                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1908                 /* stop RDE timer */
1909                 if (timer_pending(&udc_timer)) {
1910                         set_rde = 0;
1911                         mod_timer(&udc_timer, jiffies - 1);
1912                 }
1913                 /* stop pollstall timer */
1914                 if (timer_pending(&udc_pollstall_timer)) {
1915                         mod_timer(&udc_pollstall_timer, jiffies - 1);
1916                 }
1917                 /* enable DMA */
1918                 tmp = readl(&dev->regs->ctl);
1919                 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1920                                 | AMD_BIT(UDC_DEVCTL_RDE)
1921                                 | AMD_BIT(UDC_DEVCTL_TDE);
1922                 if (use_dma_bufferfill_mode) {
1923                         tmp |= AMD_BIT(UDC_DEVCTL_BF);
1924                 } else if (use_dma_ppb_du) {
1925                         tmp |= AMD_BIT(UDC_DEVCTL_DU);
1926                 }
1927                 writel(tmp, &dev->regs->ctl);
1928         }
1929
1930         /* clear NAK by writing CNAK for EP0IN */
1931         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1932         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1933         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1934         dev->ep[UDC_EP0IN_IX].naking = 0;
1935         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1936
1937         /* clear NAK by writing CNAK for EP0OUT */
1938         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1939         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1940         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1941         dev->ep[UDC_EP0OUT_IX].naking = 0;
1942         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1943 }
1944
1945 /* Make endpoint 0 ready for control traffic */
1946 static int setup_ep0(struct udc *dev)
1947 {
1948         activate_control_endpoints(dev);
1949         /* enable ep0 interrupts */
1950         udc_enable_ep0_interrupts(dev);
1951         /* enable device setup interrupts */
1952         udc_enable_dev_setup_interrupts(dev);
1953
1954         return 0;
1955 }
1956
1957 /* Called by gadget driver to register itself */
1958 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1959                 int (*bind)(struct usb_gadget *))
1960 {
1961         struct udc              *dev = udc;
1962         int                     retval;
1963         u32 tmp;
1964
1965         if (!driver || !bind || !driver->setup
1966                         || driver->speed != USB_SPEED_HIGH)
1967                 return -EINVAL;
1968         if (!dev)
1969                 return -ENODEV;
1970         if (dev->driver)
1971                 return -EBUSY;
1972
1973         driver->driver.bus = NULL;
1974         dev->driver = driver;
1975         dev->gadget.dev.driver = &driver->driver;
1976
1977         retval = bind(&dev->gadget);
1978
1979         /* Some gadget drivers use both ep0 directions.
1980          * NOTE: to gadget driver, ep0 is just one endpoint...
1981          */
1982         dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1983                 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1984
1985         if (retval) {
1986                 DBG(dev, "binding to %s returning %d\n",
1987                                 driver->driver.name, retval);
1988                 dev->driver = NULL;
1989                 dev->gadget.dev.driver = NULL;
1990                 return retval;
1991         }
1992
1993         /* get ready for ep0 traffic */
1994         setup_ep0(dev);
1995
1996         /* clear SD */
1997         tmp = readl(&dev->regs->ctl);
1998         tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1999         writel(tmp, &dev->regs->ctl);
2000
2001         usb_connect(dev);
2002
2003         return 0;
2004 }
2005 EXPORT_SYMBOL(usb_gadget_probe_driver);
2006
2007 /* shutdown requests and disconnect from gadget */
2008 static void
2009 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
2010 __releases(dev->lock)
2011 __acquires(dev->lock)
2012 {
2013         int tmp;
2014
2015         if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
2016                 spin_unlock(&dev->lock);
2017                 driver->disconnect(&dev->gadget);
2018                 spin_lock(&dev->lock);
2019         }
2020
2021         /* empty queues and init hardware */
2022         udc_basic_init(dev);
2023         for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
2024                 empty_req_queue(&dev->ep[tmp]);
2025
2026         udc_setup_endpoints(dev);
2027 }
2028
2029 /* Called by gadget driver to unregister itself */
2030 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2031 {
2032         struct udc      *dev = udc;
2033         unsigned long   flags;
2034         u32 tmp;
2035
2036         if (!dev)
2037                 return -ENODEV;
2038         if (!driver || driver != dev->driver || !driver->unbind)
2039                 return -EINVAL;
2040
2041         spin_lock_irqsave(&dev->lock, flags);
2042         udc_mask_unused_interrupts(dev);
2043         shutdown(dev, driver);
2044         spin_unlock_irqrestore(&dev->lock, flags);
2045
2046         driver->unbind(&dev->gadget);
2047         dev->gadget.dev.driver = NULL;
2048         dev->driver = NULL;
2049
2050         /* set SD */
2051         tmp = readl(&dev->regs->ctl);
2052         tmp |= AMD_BIT(UDC_DEVCTL_SD);
2053         writel(tmp, &dev->regs->ctl);
2054
2055
2056         DBG(dev, "%s: unregistered\n", driver->driver.name);
2057
2058         return 0;
2059 }
2060 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2061
2062
2063 /* Clear pending NAK bits */
2064 static void udc_process_cnak_queue(struct udc *dev)
2065 {
2066         u32 tmp;
2067         u32 reg;
2068
2069         /* check epin's */
2070         DBG(dev, "CNAK pending queue processing\n");
2071         for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2072                 if (cnak_pending & (1 << tmp)) {
2073                         DBG(dev, "CNAK pending for ep%d\n", tmp);
2074                         /* clear NAK by writing CNAK */
2075                         reg = readl(&dev->ep[tmp].regs->ctl);
2076                         reg |= AMD_BIT(UDC_EPCTL_CNAK);
2077                         writel(reg, &dev->ep[tmp].regs->ctl);
2078                         dev->ep[tmp].naking = 0;
2079                         UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2080                 }
2081         }
2082         /* ...  and ep0out */
2083         if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2084                 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2085                 /* clear NAK by writing CNAK */
2086                 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2087                 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2088                 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2089                 dev->ep[UDC_EP0OUT_IX].naking = 0;
2090                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2091                                 dev->ep[UDC_EP0OUT_IX].num);
2092         }
2093 }
2094
2095 /* Enabling RX DMA after setup packet */
2096 static void udc_ep0_set_rde(struct udc *dev)
2097 {
2098         if (use_dma) {
2099                 /*
2100                  * only enable RXDMA when no data endpoint enabled
2101                  * or data is queued
2102                  */
2103                 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2104                         udc_set_rde(dev);
2105                 } else {
2106                         /*
2107                          * setup timer for enabling RDE (to not enable
2108                          * RXFIFO DMA for data endpoints to early)
2109                          */
2110                         if (set_rde != 0 && !timer_pending(&udc_timer)) {
2111                                 udc_timer.expires =
2112                                         jiffies + HZ/UDC_RDE_TIMER_DIV;
2113                                 set_rde = 1;
2114                                 if (!stop_timer) {
2115                                         add_timer(&udc_timer);
2116                                 }
2117                         }
2118                 }
2119         }
2120 }
2121
2122
2123 /* Interrupt handler for data OUT traffic */
2124 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2125 {
2126         irqreturn_t             ret_val = IRQ_NONE;
2127         u32                     tmp;
2128         struct udc_ep           *ep;
2129         struct udc_request      *req;
2130         unsigned int            count;
2131         struct udc_data_dma     *td = NULL;
2132         unsigned                dma_done;
2133
2134         VDBG(dev, "ep%d irq\n", ep_ix);
2135         ep = &dev->ep[ep_ix];
2136
2137         tmp = readl(&ep->regs->sts);
2138         if (use_dma) {
2139                 /* BNA event ? */
2140                 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2141                         DBG(dev, "BNA ep%dout occurred - DESPTR = %x \n",
2142                                         ep->num, readl(&ep->regs->desptr));
2143                         /* clear BNA */
2144                         writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2145                         if (!ep->cancel_transfer)
2146                                 ep->bna_occurred = 1;
2147                         else
2148                                 ep->cancel_transfer = 0;
2149                         ret_val = IRQ_HANDLED;
2150                         goto finished;
2151                 }
2152         }
2153         /* HE event ? */
2154         if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2155                 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
2156
2157                 /* clear HE */
2158                 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2159                 ret_val = IRQ_HANDLED;
2160                 goto finished;
2161         }
2162
2163         if (!list_empty(&ep->queue)) {
2164
2165                 /* next request */
2166                 req = list_entry(ep->queue.next,
2167                         struct udc_request, queue);
2168         } else {
2169                 req = NULL;
2170                 udc_rxfifo_pending = 1;
2171         }
2172         VDBG(dev, "req = %p\n", req);
2173         /* fifo mode */
2174         if (!use_dma) {
2175
2176                 /* read fifo */
2177                 if (req && udc_rxfifo_read(ep, req)) {
2178                         ret_val = IRQ_HANDLED;
2179
2180                         /* finish */
2181                         complete_req(ep, req, 0);
2182                         /* next request */
2183                         if (!list_empty(&ep->queue) && !ep->halted) {
2184                                 req = list_entry(ep->queue.next,
2185                                         struct udc_request, queue);
2186                         } else
2187                                 req = NULL;
2188                 }
2189
2190         /* DMA */
2191         } else if (!ep->cancel_transfer && req != NULL) {
2192                 ret_val = IRQ_HANDLED;
2193
2194                 /* check for DMA done */
2195                 if (!use_dma_ppb) {
2196                         dma_done = AMD_GETBITS(req->td_data->status,
2197                                                 UDC_DMA_OUT_STS_BS);
2198                 /* packet per buffer mode - rx bytes */
2199                 } else {
2200                         /*
2201                          * if BNA occurred then recover desc. from
2202                          * BNA dummy desc.
2203                          */
2204                         if (ep->bna_occurred) {
2205                                 VDBG(dev, "Recover desc. from BNA dummy\n");
2206                                 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2207                                                 sizeof(struct udc_data_dma));
2208                                 ep->bna_occurred = 0;
2209                                 udc_init_bna_dummy(ep->req);
2210                         }
2211                         td = udc_get_last_dma_desc(req);
2212                         dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2213                 }
2214                 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2215                         /* buffer fill mode - rx bytes */
2216                         if (!use_dma_ppb) {
2217                                 /* received number bytes */
2218                                 count = AMD_GETBITS(req->td_data->status,
2219                                                 UDC_DMA_OUT_STS_RXBYTES);
2220                                 VDBG(dev, "rx bytes=%u\n", count);
2221                         /* packet per buffer mode - rx bytes */
2222                         } else {
2223                                 VDBG(dev, "req->td_data=%p\n", req->td_data);
2224                                 VDBG(dev, "last desc = %p\n", td);
2225                                 /* received number bytes */
2226                                 if (use_dma_ppb_du) {
2227                                         /* every desc. counts bytes */
2228                                         count = udc_get_ppbdu_rxbytes(req);
2229                                 } else {
2230                                         /* last desc. counts bytes */
2231                                         count = AMD_GETBITS(td->status,
2232                                                 UDC_DMA_OUT_STS_RXBYTES);
2233                                         if (!count && req->req.length
2234                                                 == UDC_DMA_MAXPACKET) {
2235                                                 /*
2236                                                  * on 64k packets the RXBYTES
2237                                                  * field is zero
2238                                                  */
2239                                                 count = UDC_DMA_MAXPACKET;
2240                                         }
2241                                 }
2242                                 VDBG(dev, "last desc rx bytes=%u\n", count);
2243                         }
2244
2245                         tmp = req->req.length - req->req.actual;
2246                         if (count > tmp) {
2247                                 if ((tmp % ep->ep.maxpacket) != 0) {
2248                                         DBG(dev, "%s: rx %db, space=%db\n",
2249                                                 ep->ep.name, count, tmp);
2250                                         req->req.status = -EOVERFLOW;
2251                                 }
2252                                 count = tmp;
2253                         }
2254                         req->req.actual += count;
2255                         req->dma_going = 0;
2256                         /* complete request */
2257                         complete_req(ep, req, 0);
2258
2259                         /* next request */
2260                         if (!list_empty(&ep->queue) && !ep->halted) {
2261                                 req = list_entry(ep->queue.next,
2262                                         struct udc_request,
2263                                         queue);
2264                                 /*
2265                                  * DMA may be already started by udc_queue()
2266                                  * called by gadget drivers completion
2267                                  * routine. This happens when queue
2268                                  * holds one request only.
2269                                  */
2270                                 if (req->dma_going == 0) {
2271                                         /* next dma */
2272                                         if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2273                                                 goto finished;
2274                                         /* write desc pointer */
2275                                         writel(req->td_phys,
2276                                                 &ep->regs->desptr);
2277                                         req->dma_going = 1;
2278                                         /* enable DMA */
2279                                         udc_set_rde(dev);
2280                                 }
2281                         } else {
2282                                 /*
2283                                  * implant BNA dummy descriptor to allow
2284                                  * RXFIFO opening by RDE
2285                                  */
2286                                 if (ep->bna_dummy_req) {
2287                                         /* write desc pointer */
2288                                         writel(ep->bna_dummy_req->td_phys,
2289                                                 &ep->regs->desptr);
2290                                         ep->bna_occurred = 0;
2291                                 }
2292
2293                                 /*
2294                                  * schedule timer for setting RDE if queue
2295                                  * remains empty to allow ep0 packets pass
2296                                  * through
2297                                  */
2298                                 if (set_rde != 0
2299                                                 && !timer_pending(&udc_timer)) {
2300                                         udc_timer.expires =
2301                                                 jiffies
2302                                                 + HZ*UDC_RDE_TIMER_SECONDS;
2303                                         set_rde = 1;
2304                                         if (!stop_timer) {
2305                                                 add_timer(&udc_timer);
2306                                         }
2307                                 }
2308                                 if (ep->num != UDC_EP0OUT_IX)
2309                                         dev->data_ep_queued = 0;
2310                         }
2311
2312                 } else {
2313                         /*
2314                         * RX DMA must be reenabled for each desc in PPBDU mode
2315                         * and must be enabled for PPBNDU mode in case of BNA
2316                         */
2317                         udc_set_rde(dev);
2318                 }
2319
2320         } else if (ep->cancel_transfer) {
2321                 ret_val = IRQ_HANDLED;
2322                 ep->cancel_transfer = 0;
2323         }
2324
2325         /* check pending CNAKS */
2326         if (cnak_pending) {
2327                 /* CNAk processing when rxfifo empty only */
2328                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
2329                         udc_process_cnak_queue(dev);
2330                 }
2331         }
2332
2333         /* clear OUT bits in ep status */
2334         writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2335 finished:
2336         return ret_val;
2337 }
2338
2339 /* Interrupt handler for data IN traffic */
2340 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2341 {
2342         irqreturn_t ret_val = IRQ_NONE;
2343         u32 tmp;
2344         u32 epsts;
2345         struct udc_ep *ep;
2346         struct udc_request *req;
2347         struct udc_data_dma *td;
2348         unsigned dma_done;
2349         unsigned len;
2350
2351         ep = &dev->ep[ep_ix];
2352
2353         epsts = readl(&ep->regs->sts);
2354         if (use_dma) {
2355                 /* BNA ? */
2356                 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2357                         dev_err(&dev->pdev->dev,
2358                                 "BNA ep%din occurred - DESPTR = %08lx \n",
2359                                 ep->num,
2360                                 (unsigned long) readl(&ep->regs->desptr));
2361
2362                         /* clear BNA */
2363                         writel(epsts, &ep->regs->sts);
2364                         ret_val = IRQ_HANDLED;
2365                         goto finished;
2366                 }
2367         }
2368         /* HE event ? */
2369         if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2370                 dev_err(&dev->pdev->dev,
2371                         "HE ep%dn occurred - DESPTR = %08lx \n",
2372                         ep->num, (unsigned long) readl(&ep->regs->desptr));
2373
2374                 /* clear HE */
2375                 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2376                 ret_val = IRQ_HANDLED;
2377                 goto finished;
2378         }
2379
2380         /* DMA completion */
2381         if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2382                 VDBG(dev, "TDC set- completion\n");
2383                 ret_val = IRQ_HANDLED;
2384                 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2385                         req = list_entry(ep->queue.next,
2386                                         struct udc_request, queue);
2387                         /*
2388                          * length bytes transferred
2389                          * check dma done of last desc. in PPBDU mode
2390                          */
2391                         if (use_dma_ppb_du) {
2392                                 td = udc_get_last_dma_desc(req);
2393                                 if (td) {
2394                                         dma_done =
2395                                                 AMD_GETBITS(td->status,
2396                                                 UDC_DMA_IN_STS_BS);
2397                                         /* don't care DMA done */
2398                                         req->req.actual = req->req.length;
2399                                 }
2400                         } else {
2401                                 /* assume all bytes transferred */
2402                                 req->req.actual = req->req.length;
2403                         }
2404
2405                         if (req->req.actual == req->req.length) {
2406                                 /* complete req */
2407                                 complete_req(ep, req, 0);
2408                                 req->dma_going = 0;
2409                                 /* further request available ? */
2410                                 if (list_empty(&ep->queue)) {
2411                                         /* disable interrupt */
2412                                         tmp = readl(&dev->regs->ep_irqmsk);
2413                                         tmp |= AMD_BIT(ep->num);
2414                                         writel(tmp, &dev->regs->ep_irqmsk);
2415                                 }
2416                         }
2417                 }
2418                 ep->cancel_transfer = 0;
2419
2420         }
2421         /*
2422          * status reg has IN bit set and TDC not set (if TDC was handled,
2423          * IN must not be handled (UDC defect) ?
2424          */
2425         if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2426                         && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2427                 ret_val = IRQ_HANDLED;
2428                 if (!list_empty(&ep->queue)) {
2429                         /* next request */
2430                         req = list_entry(ep->queue.next,
2431                                         struct udc_request, queue);
2432                         /* FIFO mode */
2433                         if (!use_dma) {
2434                                 /* write fifo */
2435                                 udc_txfifo_write(ep, &req->req);
2436                                 len = req->req.length - req->req.actual;
2437                                                 if (len > ep->ep.maxpacket)
2438                                                         len = ep->ep.maxpacket;
2439                                                 req->req.actual += len;
2440                                 if (req->req.actual == req->req.length
2441                                         || (len != ep->ep.maxpacket)) {
2442                                         /* complete req */
2443                                         complete_req(ep, req, 0);
2444                                 }
2445                         /* DMA */
2446                         } else if (req && !req->dma_going) {
2447                                 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2448                                         req, req->td_data);
2449                                 if (req->td_data) {
2450
2451                                         req->dma_going = 1;
2452
2453                                         /*
2454                                          * unset L bit of first desc.
2455                                          * for chain
2456                                          */
2457                                         if (use_dma_ppb && req->req.length >
2458                                                         ep->ep.maxpacket) {
2459                                                 req->td_data->status &=
2460                                                         AMD_CLEAR_BIT(
2461                                                         UDC_DMA_IN_STS_L);
2462                                         }
2463
2464                                         /* write desc pointer */
2465                                         writel(req->td_phys, &ep->regs->desptr);
2466
2467                                         /* set HOST READY */
2468                                         req->td_data->status =
2469                                                 AMD_ADDBITS(
2470                                                 req->td_data->status,
2471                                                 UDC_DMA_IN_STS_BS_HOST_READY,
2472                                                 UDC_DMA_IN_STS_BS);
2473
2474                                         /* set poll demand bit */
2475                                         tmp = readl(&ep->regs->ctl);
2476                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2477                                         writel(tmp, &ep->regs->ctl);
2478                                 }
2479                         }
2480
2481                 } else if (!use_dma && ep->in) {
2482                         /* disable interrupt */
2483                         tmp = readl(
2484                                 &dev->regs->ep_irqmsk);
2485                         tmp |= AMD_BIT(ep->num);
2486                         writel(tmp,
2487                                 &dev->regs->ep_irqmsk);
2488                 }
2489         }
2490         /* clear status bits */
2491         writel(epsts, &ep->regs->sts);
2492
2493 finished:
2494         return ret_val;
2495
2496 }
2497
2498 /* Interrupt handler for Control OUT traffic */
2499 static irqreturn_t udc_control_out_isr(struct udc *dev)
2500 __releases(dev->lock)
2501 __acquires(dev->lock)
2502 {
2503         irqreturn_t ret_val = IRQ_NONE;
2504         u32 tmp;
2505         int setup_supported;
2506         u32 count;
2507         int set = 0;
2508         struct udc_ep   *ep;
2509         struct udc_ep   *ep_tmp;
2510
2511         ep = &dev->ep[UDC_EP0OUT_IX];
2512
2513         /* clear irq */
2514         writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2515
2516         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2517         /* check BNA and clear if set */
2518         if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2519                 VDBG(dev, "ep0: BNA set\n");
2520                 writel(AMD_BIT(UDC_EPSTS_BNA),
2521                         &dev->ep[UDC_EP0OUT_IX].regs->sts);
2522                 ep->bna_occurred = 1;
2523                 ret_val = IRQ_HANDLED;
2524                 goto finished;
2525         }
2526
2527         /* type of data: SETUP or DATA 0 bytes */
2528         tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2529         VDBG(dev, "data_typ = %x\n", tmp);
2530
2531         /* setup data */
2532         if (tmp == UDC_EPSTS_OUT_SETUP) {
2533                 ret_val = IRQ_HANDLED;
2534
2535                 ep->dev->stall_ep0in = 0;
2536                 dev->waiting_zlp_ack_ep0in = 0;
2537
2538                 /* set NAK for EP0_IN */
2539                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2540                 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2541                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2542                 dev->ep[UDC_EP0IN_IX].naking = 1;
2543                 /* get setup data */
2544                 if (use_dma) {
2545
2546                         /* clear OUT bits in ep status */
2547                         writel(UDC_EPSTS_OUT_CLEAR,
2548                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2549
2550                         setup_data.data[0] =
2551                                 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2552                         setup_data.data[1] =
2553                                 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2554                         /* set HOST READY */
2555                         dev->ep[UDC_EP0OUT_IX].td_stp->status =
2556                                         UDC_DMA_STP_STS_BS_HOST_READY;
2557                 } else {
2558                         /* read fifo */
2559                         udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2560                 }
2561
2562                 /* determine direction of control data */
2563                 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2564                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2565                         /* enable RDE */
2566                         udc_ep0_set_rde(dev);
2567                         set = 0;
2568                 } else {
2569                         dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2570                         /*
2571                          * implant BNA dummy descriptor to allow RXFIFO opening
2572                          * by RDE
2573                          */
2574                         if (ep->bna_dummy_req) {
2575                                 /* write desc pointer */
2576                                 writel(ep->bna_dummy_req->td_phys,
2577                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2578                                 ep->bna_occurred = 0;
2579                         }
2580
2581                         set = 1;
2582                         dev->ep[UDC_EP0OUT_IX].naking = 1;
2583                         /*
2584                          * setup timer for enabling RDE (to not enable
2585                          * RXFIFO DMA for data to early)
2586                          */
2587                         set_rde = 1;
2588                         if (!timer_pending(&udc_timer)) {
2589                                 udc_timer.expires = jiffies +
2590                                                         HZ/UDC_RDE_TIMER_DIV;
2591                                 if (!stop_timer) {
2592                                         add_timer(&udc_timer);
2593                                 }
2594                         }
2595                 }
2596
2597                 /*
2598                  * mass storage reset must be processed here because
2599                  * next packet may be a CLEAR_FEATURE HALT which would not
2600                  * clear the stall bit when no STALL handshake was received
2601                  * before (autostall can cause this)
2602                  */
2603                 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2604                                 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2605                         DBG(dev, "MSC Reset\n");
2606                         /*
2607                          * clear stall bits
2608                          * only one IN and OUT endpoints are handled
2609                          */
2610                         ep_tmp = &udc->ep[UDC_EPIN_IX];
2611                         udc_set_halt(&ep_tmp->ep, 0);
2612                         ep_tmp = &udc->ep[UDC_EPOUT_IX];
2613                         udc_set_halt(&ep_tmp->ep, 0);
2614                 }
2615
2616                 /* call gadget with setup data received */
2617                 spin_unlock(&dev->lock);
2618                 setup_supported = dev->driver->setup(&dev->gadget,
2619                                                 &setup_data.request);
2620                 spin_lock(&dev->lock);
2621
2622                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2623                 /* ep0 in returns data (not zlp) on IN phase */
2624                 if (setup_supported >= 0 && setup_supported <
2625                                 UDC_EP0IN_MAXPACKET) {
2626                         /* clear NAK by writing CNAK in EP0_IN */
2627                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2628                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2629                         dev->ep[UDC_EP0IN_IX].naking = 0;
2630                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2631
2632                 /* if unsupported request then stall */
2633                 } else if (setup_supported < 0) {
2634                         tmp |= AMD_BIT(UDC_EPCTL_S);
2635                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2636                 } else
2637                         dev->waiting_zlp_ack_ep0in = 1;
2638
2639
2640                 /* clear NAK by writing CNAK in EP0_OUT */
2641                 if (!set) {
2642                         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2643                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2644                         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2645                         dev->ep[UDC_EP0OUT_IX].naking = 0;
2646                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2647                 }
2648
2649                 if (!use_dma) {
2650                         /* clear OUT bits in ep status */
2651                         writel(UDC_EPSTS_OUT_CLEAR,
2652                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2653                 }
2654
2655         /* data packet 0 bytes */
2656         } else if (tmp == UDC_EPSTS_OUT_DATA) {
2657                 /* clear OUT bits in ep status */
2658                 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2659
2660                 /* get setup data: only 0 packet */
2661                 if (use_dma) {
2662                         /* no req if 0 packet, just reactivate */
2663                         if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2664                                 VDBG(dev, "ZLP\n");
2665
2666                                 /* set HOST READY */
2667                                 dev->ep[UDC_EP0OUT_IX].td->status =
2668                                         AMD_ADDBITS(
2669                                         dev->ep[UDC_EP0OUT_IX].td->status,
2670                                         UDC_DMA_OUT_STS_BS_HOST_READY,
2671                                         UDC_DMA_OUT_STS_BS);
2672                                 /* enable RDE */
2673                                 udc_ep0_set_rde(dev);
2674                                 ret_val = IRQ_HANDLED;
2675
2676                         } else {
2677                                 /* control write */
2678                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2679                                 /* re-program desc. pointer for possible ZLPs */
2680                                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2681                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2682                                 /* enable RDE */
2683                                 udc_ep0_set_rde(dev);
2684                         }
2685                 } else {
2686
2687                         /* received number bytes */
2688                         count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2689                         count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2690                         /* out data for fifo mode not working */
2691                         count = 0;
2692
2693                         /* 0 packet or real data ? */
2694                         if (count != 0) {
2695                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2696                         } else {
2697                                 /* dummy read confirm */
2698                                 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2699                                 ret_val = IRQ_HANDLED;
2700                         }
2701                 }
2702         }
2703
2704         /* check pending CNAKS */
2705         if (cnak_pending) {
2706                 /* CNAk processing when rxfifo empty only */
2707                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
2708                         udc_process_cnak_queue(dev);
2709                 }
2710         }
2711
2712 finished:
2713         return ret_val;
2714 }
2715
2716 /* Interrupt handler for Control IN traffic */
2717 static irqreturn_t udc_control_in_isr(struct udc *dev)
2718 {
2719         irqreturn_t ret_val = IRQ_NONE;
2720         u32 tmp;
2721         struct udc_ep *ep;
2722         struct udc_request *req;
2723         unsigned len;
2724
2725         ep = &dev->ep[UDC_EP0IN_IX];
2726
2727         /* clear irq */
2728         writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2729
2730         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2731         /* DMA completion */
2732         if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2733                 VDBG(dev, "isr: TDC clear \n");
2734                 ret_val = IRQ_HANDLED;
2735
2736                 /* clear TDC bit */
2737                 writel(AMD_BIT(UDC_EPSTS_TDC),
2738                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2739
2740         /* status reg has IN bit set ? */
2741         } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2742                 ret_val = IRQ_HANDLED;
2743
2744                 if (ep->dma) {
2745                         /* clear IN bit */
2746                         writel(AMD_BIT(UDC_EPSTS_IN),
2747                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2748                 }
2749                 if (dev->stall_ep0in) {
2750                         DBG(dev, "stall ep0in\n");
2751                         /* halt ep0in */
2752                         tmp = readl(&ep->regs->ctl);
2753                         tmp |= AMD_BIT(UDC_EPCTL_S);
2754                         writel(tmp, &ep->regs->ctl);
2755                 } else {
2756                         if (!list_empty(&ep->queue)) {
2757                                 /* next request */
2758                                 req = list_entry(ep->queue.next,
2759                                                 struct udc_request, queue);
2760
2761                                 if (ep->dma) {
2762                                         /* write desc pointer */
2763                                         writel(req->td_phys, &ep->regs->desptr);
2764                                         /* set HOST READY */
2765                                         req->td_data->status =
2766                                                 AMD_ADDBITS(
2767                                                 req->td_data->status,
2768                                                 UDC_DMA_STP_STS_BS_HOST_READY,
2769                                                 UDC_DMA_STP_STS_BS);
2770
2771                                         /* set poll demand bit */
2772                                         tmp =
2773                                         readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2774                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2775                                         writel(tmp,
2776                                         &dev->ep[UDC_EP0IN_IX].regs->ctl);
2777
2778                                         /* all bytes will be transferred */
2779                                         req->req.actual = req->req.length;
2780
2781                                         /* complete req */
2782                                         complete_req(ep, req, 0);
2783
2784                                 } else {
2785                                         /* write fifo */
2786                                         udc_txfifo_write(ep, &req->req);
2787
2788                                         /* lengh bytes transferred */
2789                                         len = req->req.length - req->req.actual;
2790                                         if (len > ep->ep.maxpacket)
2791                                                 len = ep->ep.maxpacket;
2792
2793                                         req->req.actual += len;
2794                                         if (req->req.actual == req->req.length
2795                                                 || (len != ep->ep.maxpacket)) {
2796                                                 /* complete req */
2797                                                 complete_req(ep, req, 0);
2798                                         }
2799                                 }
2800
2801                         }
2802                 }
2803                 ep->halted = 0;
2804                 dev->stall_ep0in = 0;
2805                 if (!ep->dma) {
2806                         /* clear IN bit */
2807                         writel(AMD_BIT(UDC_EPSTS_IN),
2808                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2809                 }
2810         }
2811
2812         return ret_val;
2813 }
2814
2815
2816 /* Interrupt handler for global device events */
2817 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2818 __releases(dev->lock)
2819 __acquires(dev->lock)
2820 {
2821         irqreturn_t ret_val = IRQ_NONE;
2822         u32 tmp;
2823         u32 cfg;
2824         struct udc_ep *ep;
2825         u16 i;
2826         u8 udc_csr_epix;
2827
2828         /* SET_CONFIG irq ? */
2829         if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2830                 ret_val = IRQ_HANDLED;
2831
2832                 /* read config value */
2833                 tmp = readl(&dev->regs->sts);
2834                 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2835                 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2836                 dev->cur_config = cfg;
2837                 dev->set_cfg_not_acked = 1;
2838
2839                 /* make usb request for gadget driver */
2840                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2841                 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2842                 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2843
2844                 /* programm the NE registers */
2845                 for (i = 0; i < UDC_EP_NUM; i++) {
2846                         ep = &dev->ep[i];
2847                         if (ep->in) {
2848
2849                                 /* ep ix in UDC CSR register space */
2850                                 udc_csr_epix = ep->num;
2851
2852
2853                         /* OUT ep */
2854                         } else {
2855                                 /* ep ix in UDC CSR register space */
2856                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2857                         }
2858
2859                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2860                         /* ep cfg */
2861                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2862                                                 UDC_CSR_NE_CFG);
2863                         /* write reg */
2864                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2865
2866                         /* clear stall bits */
2867                         ep->halted = 0;
2868                         tmp = readl(&ep->regs->ctl);
2869                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2870                         writel(tmp, &ep->regs->ctl);
2871                 }
2872                 /* call gadget zero with setup data received */
2873                 spin_unlock(&dev->lock);
2874                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2875                 spin_lock(&dev->lock);
2876
2877         } /* SET_INTERFACE ? */
2878         if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2879                 ret_val = IRQ_HANDLED;
2880
2881                 dev->set_cfg_not_acked = 1;
2882                 /* read interface and alt setting values */
2883                 tmp = readl(&dev->regs->sts);
2884                 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2885                 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2886
2887                 /* make usb request for gadget driver */
2888                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2889                 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2890                 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2891                 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2892                 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2893
2894                 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2895                                 dev->cur_alt, dev->cur_intf);
2896
2897                 /* programm the NE registers */
2898                 for (i = 0; i < UDC_EP_NUM; i++) {
2899                         ep = &dev->ep[i];
2900                         if (ep->in) {
2901
2902                                 /* ep ix in UDC CSR register space */
2903                                 udc_csr_epix = ep->num;
2904
2905
2906                         /* OUT ep */
2907                         } else {
2908                                 /* ep ix in UDC CSR register space */
2909                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2910                         }
2911
2912                         /* UDC CSR reg */
2913                         /* set ep values */
2914                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2915                         /* ep interface */
2916                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2917                                                 UDC_CSR_NE_INTF);
2918                         /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2919                         /* ep alt */
2920                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2921                                                 UDC_CSR_NE_ALT);
2922                         /* write reg */
2923                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2924
2925                         /* clear stall bits */
2926                         ep->halted = 0;
2927                         tmp = readl(&ep->regs->ctl);
2928                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2929                         writel(tmp, &ep->regs->ctl);
2930                 }
2931
2932                 /* call gadget zero with setup data received */
2933                 spin_unlock(&dev->lock);
2934                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2935                 spin_lock(&dev->lock);
2936
2937         } /* USB reset */
2938         if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2939                 DBG(dev, "USB Reset interrupt\n");
2940                 ret_val = IRQ_HANDLED;
2941
2942                 /* allow soft reset when suspend occurs */
2943                 soft_reset_occured = 0;
2944
2945                 dev->waiting_zlp_ack_ep0in = 0;
2946                 dev->set_cfg_not_acked = 0;
2947
2948                 /* mask not needed interrupts */
2949                 udc_mask_unused_interrupts(dev);
2950
2951                 /* call gadget to resume and reset configs etc. */
2952                 spin_unlock(&dev->lock);
2953                 if (dev->sys_suspended && dev->driver->resume) {
2954                         dev->driver->resume(&dev->gadget);
2955                         dev->sys_suspended = 0;
2956                 }
2957                 dev->driver->disconnect(&dev->gadget);
2958                 spin_lock(&dev->lock);
2959
2960                 /* disable ep0 to empty req queue */
2961                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2962                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2963
2964                 /* soft reset when rxfifo not empty */
2965                 tmp = readl(&dev->regs->sts);
2966                 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2967                                 && !soft_reset_after_usbreset_occured) {
2968                         udc_soft_reset(dev);
2969                         soft_reset_after_usbreset_occured++;
2970                 }
2971
2972                 /*
2973                  * DMA reset to kill potential old DMA hw hang,
2974                  * POLL bit is already reset by ep_init() through
2975                  * disconnect()
2976                  */
2977                 DBG(dev, "DMA machine reset\n");
2978                 tmp = readl(&dev->regs->cfg);
2979                 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2980                 writel(tmp, &dev->regs->cfg);
2981
2982                 /* put into initial config */
2983                 udc_basic_init(dev);
2984
2985                 /* enable device setup interrupts */
2986                 udc_enable_dev_setup_interrupts(dev);
2987
2988                 /* enable suspend interrupt */
2989                 tmp = readl(&dev->regs->irqmsk);
2990                 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2991                 writel(tmp, &dev->regs->irqmsk);
2992
2993         } /* USB suspend */
2994         if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2995                 DBG(dev, "USB Suspend interrupt\n");
2996                 ret_val = IRQ_HANDLED;
2997                 if (dev->driver->suspend) {
2998                         spin_unlock(&dev->lock);
2999                         dev->sys_suspended = 1;
3000                         dev->driver->suspend(&dev->gadget);
3001                         spin_lock(&dev->lock);
3002                 }
3003         } /* new speed ? */
3004         if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
3005                 DBG(dev, "ENUM interrupt\n");
3006                 ret_val = IRQ_HANDLED;
3007                 soft_reset_after_usbreset_occured = 0;
3008
3009                 /* disable ep0 to empty req queue */
3010                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
3011                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
3012
3013                 /* link up all endpoints */
3014                 udc_setup_endpoints(dev);
3015                 if (dev->gadget.speed == USB_SPEED_HIGH) {
3016                         dev_info(&dev->pdev->dev, "Connect: speed = %s\n",
3017                                 "high");
3018                 } else if (dev->gadget.speed == USB_SPEED_FULL) {
3019                         dev_info(&dev->pdev->dev, "Connect: speed = %s\n",
3020                                 "full");
3021                 }
3022
3023                 /* init ep 0 */
3024                 activate_control_endpoints(dev);
3025
3026                 /* enable ep0 interrupts */
3027                 udc_enable_ep0_interrupts(dev);
3028         }
3029         /* session valid change interrupt */
3030         if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
3031                 DBG(dev, "USB SVC interrupt\n");
3032                 ret_val = IRQ_HANDLED;
3033
3034                 /* check that session is not valid to detect disconnect */
3035                 tmp = readl(&dev->regs->sts);
3036                 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
3037                         /* disable suspend interrupt */
3038                         tmp = readl(&dev->regs->irqmsk);
3039                         tmp |= AMD_BIT(UDC_DEVINT_US);
3040                         writel(tmp, &dev->regs->irqmsk);
3041                         DBG(dev, "USB Disconnect (session valid low)\n");
3042                         /* cleanup on disconnect */
3043                         usb_disconnect(udc);
3044                 }
3045
3046         }
3047
3048         return ret_val;
3049 }
3050
3051 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3052 static irqreturn_t udc_irq(int irq, void *pdev)
3053 {
3054         struct udc *dev = pdev;
3055         u32 reg;
3056         u16 i;
3057         u32 ep_irq;
3058         irqreturn_t ret_val = IRQ_NONE;
3059
3060         spin_lock(&dev->lock);
3061
3062         /* check for ep irq */
3063         reg = readl(&dev->regs->ep_irqsts);
3064         if (reg) {
3065                 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3066                         ret_val |= udc_control_out_isr(dev);
3067                 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3068                         ret_val |= udc_control_in_isr(dev);
3069
3070                 /*
3071                  * data endpoint
3072                  * iterate ep's
3073                  */
3074                 for (i = 1; i < UDC_EP_NUM; i++) {
3075                         ep_irq = 1 << i;
3076                         if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3077                                 continue;
3078
3079                         /* clear irq status */
3080                         writel(ep_irq, &dev->regs->ep_irqsts);
3081
3082                         /* irq for out ep ? */
3083                         if (i > UDC_EPIN_NUM)
3084                                 ret_val |= udc_data_out_isr(dev, i);
3085                         else
3086                                 ret_val |= udc_data_in_isr(dev, i);
3087                 }
3088
3089         }
3090
3091
3092         /* check for dev irq */
3093         reg = readl(&dev->regs->irqsts);
3094         if (reg) {
3095                 /* clear irq */
3096                 writel(reg, &dev->regs->irqsts);
3097                 ret_val |= udc_dev_isr(dev, reg);
3098         }
3099
3100
3101         spin_unlock(&dev->lock);
3102         return ret_val;
3103 }
3104
3105 /* Tears down device */
3106 static void gadget_release(struct device *pdev)
3107 {
3108         struct amd5536udc *dev = dev_get_drvdata(pdev);
3109         kfree(dev);
3110 }
3111
3112 /* Cleanup on device remove */
3113 static void udc_remove(struct udc *dev)
3114 {
3115         /* remove timer */
3116         stop_timer++;
3117         if (timer_pending(&udc_timer))
3118                 wait_for_completion(&on_exit);
3119         if (udc_timer.data)
3120                 del_timer_sync(&udc_timer);
3121         /* remove pollstall timer */
3122         stop_pollstall_timer++;
3123         if (timer_pending(&udc_pollstall_timer))
3124                 wait_for_completion(&on_pollstall_exit);
3125         if (udc_pollstall_timer.data)
3126                 del_timer_sync(&udc_pollstall_timer);
3127         udc = NULL;
3128 }
3129
3130 /* Reset all pci context */
3131 static void udc_pci_remove(struct pci_dev *pdev)
3132 {
3133         struct udc              *dev;
3134
3135         dev = pci_get_drvdata(pdev);
3136
3137         /* gadget driver must not be registered */
3138         BUG_ON(dev->driver != NULL);
3139
3140         /* dma pool cleanup */
3141         if (dev->data_requests)
3142                 pci_pool_destroy(dev->data_requests);
3143
3144         if (dev->stp_requests) {
3145                 /* cleanup DMA desc's for ep0in */
3146                 pci_pool_free(dev->stp_requests,
3147                         dev->ep[UDC_EP0OUT_IX].td_stp,
3148                         dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3149                 pci_pool_free(dev->stp_requests,
3150                         dev->ep[UDC_EP0OUT_IX].td,
3151                         dev->ep[UDC_EP0OUT_IX].td_phys);
3152
3153                 pci_pool_destroy(dev->stp_requests);
3154         }
3155
3156         /* reset controller */
3157         writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3158         if (dev->irq_registered)
3159                 free_irq(pdev->irq, dev);
3160         if (dev->regs)
3161                 iounmap(dev->regs);
3162         if (dev->mem_region)
3163                 release_mem_region(pci_resource_start(pdev, 0),
3164                                 pci_resource_len(pdev, 0));
3165         if (dev->active)
3166                 pci_disable_device(pdev);
3167
3168         device_unregister(&dev->gadget.dev);
3169         pci_set_drvdata(pdev, NULL);
3170
3171         udc_remove(dev);
3172 }
3173
3174 /* create dma pools on init */
3175 static int init_dma_pools(struct udc *dev)
3176 {
3177         struct udc_stp_dma      *td_stp;
3178         struct udc_data_dma     *td_data;
3179         int retval;
3180
3181         /* consistent DMA mode setting ? */
3182         if (use_dma_ppb) {
3183                 use_dma_bufferfill_mode = 0;
3184         } else {
3185                 use_dma_ppb_du = 0;
3186                 use_dma_bufferfill_mode = 1;
3187         }
3188
3189         /* DMA setup */
3190         dev->data_requests = dma_pool_create("data_requests", NULL,
3191                 sizeof(struct udc_data_dma), 0, 0);
3192         if (!dev->data_requests) {
3193                 DBG(dev, "can't get request data pool\n");
3194                 retval = -ENOMEM;
3195                 goto finished;
3196         }
3197
3198         /* EP0 in dma regs = dev control regs */
3199         dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3200
3201         /* dma desc for setup data */
3202         dev->stp_requests = dma_pool_create("setup requests", NULL,
3203                 sizeof(struct udc_stp_dma), 0, 0);
3204         if (!dev->stp_requests) {
3205                 DBG(dev, "can't get stp request pool\n");
3206                 retval = -ENOMEM;
3207                 goto finished;
3208         }
3209         /* setup */
3210         td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3211                                 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3212         if (td_stp == NULL) {
3213                 retval = -ENOMEM;
3214                 goto finished;
3215         }
3216         dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3217
3218         /* data: 0 packets !? */
3219         td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3220                                 &dev->ep[UDC_EP0OUT_IX].td_phys);
3221         if (td_data == NULL) {
3222                 retval = -ENOMEM;
3223                 goto finished;
3224         }
3225         dev->ep[UDC_EP0OUT_IX].td = td_data;
3226         return 0;
3227
3228 finished:
3229         return retval;
3230 }
3231
3232 /* Called by pci bus driver to init pci context */
3233 static int udc_pci_probe(
3234         struct pci_dev *pdev,
3235         const struct pci_device_id *id
3236 )
3237 {
3238         struct udc              *dev;
3239         unsigned long           resource;
3240         unsigned long           len;
3241         int                     retval = 0;
3242
3243         /* one udc only */
3244         if (udc) {
3245                 dev_dbg(&pdev->dev, "already probed\n");
3246                 return -EBUSY;
3247         }
3248
3249         /* init */
3250         dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3251         if (!dev) {
3252                 retval = -ENOMEM;
3253                 goto finished;
3254         }
3255
3256         /* pci setup */
3257         if (pci_enable_device(pdev) < 0) {
3258                 kfree(dev);
3259                 dev = NULL;
3260                 retval = -ENODEV;
3261                 goto finished;
3262         }
3263         dev->active = 1;
3264
3265         /* PCI resource allocation */
3266         resource = pci_resource_start(pdev, 0);
3267         len = pci_resource_len(pdev, 0);
3268
3269         if (!request_mem_region(resource, len, name)) {
3270                 dev_dbg(&pdev->dev, "pci device used already\n");
3271                 kfree(dev);
3272                 dev = NULL;
3273                 retval = -EBUSY;
3274                 goto finished;
3275         }
3276         dev->mem_region = 1;
3277
3278         dev->virt_addr = ioremap_nocache(resource, len);
3279         if (dev->virt_addr == NULL) {
3280                 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3281                 kfree(dev);
3282                 dev = NULL;
3283                 retval = -EFAULT;
3284                 goto finished;
3285         }
3286
3287         if (!pdev->irq) {
3288                 dev_err(&dev->pdev->dev, "irq not set\n");
3289                 kfree(dev);
3290                 dev = NULL;
3291                 retval = -ENODEV;
3292                 goto finished;
3293         }
3294
3295         spin_lock_init(&dev->lock);
3296         /* udc csr registers base */
3297         dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3298         /* dev registers base */
3299         dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3300         /* ep registers base */
3301         dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3302         /* fifo's base */
3303         dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3304         dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3305
3306         if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3307                 dev_dbg(&dev->pdev->dev, "request_irq(%d) fail\n", pdev->irq);
3308                 kfree(dev);
3309                 dev = NULL;
3310                 retval = -EBUSY;
3311                 goto finished;
3312         }
3313         dev->irq_registered = 1;
3314
3315         pci_set_drvdata(pdev, dev);
3316
3317         /* chip revision for Hs AMD5536 */
3318         dev->chiprev = pdev->revision;
3319
3320         pci_set_master(pdev);
3321         pci_try_set_mwi(pdev);
3322
3323         /* init dma pools */
3324         if (use_dma) {
3325                 retval = init_dma_pools(dev);
3326                 if (retval != 0)
3327                         goto finished;
3328         }
3329
3330         dev->phys_addr = resource;
3331         dev->irq = pdev->irq;
3332         dev->pdev = pdev;
3333         dev->gadget.dev.parent = &pdev->dev;
3334         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3335
3336         /* general probing */
3337         if (udc_probe(dev) == 0)
3338                 return 0;
3339
3340 finished:
3341         if (dev)
3342                 udc_pci_remove(pdev);
3343         return retval;
3344 }
3345
3346 /* general probe */
3347 static int udc_probe(struct udc *dev)
3348 {
3349         char            tmp[128];
3350         u32             reg;
3351         int             retval;
3352
3353         /* mark timer as not initialized */
3354         udc_timer.data = 0;
3355         udc_pollstall_timer.data = 0;
3356
3357         /* device struct setup */
3358         dev->gadget.ops = &udc_ops;
3359
3360         dev_set_name(&dev->gadget.dev, "gadget");
3361         dev->gadget.dev.release = gadget_release;
3362         dev->gadget.name = name;
3363         dev->gadget.is_dualspeed = 1;
3364
3365         /* init registers, interrupts, ... */
3366         startup_registers(dev);
3367
3368         dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3369
3370         snprintf(tmp, sizeof tmp, "%d", dev->irq);
3371         dev_info(&dev->pdev->dev,
3372                 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3373                 tmp, dev->phys_addr, dev->chiprev,
3374                 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3375         strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3376         if (dev->chiprev == UDC_HSA0_REV) {
3377                 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3378                 retval = -ENODEV;
3379                 goto finished;
3380         }
3381         dev_info(&dev->pdev->dev,
3382                 "driver version: %s(for Geode5536 B1)\n", tmp);
3383         udc = dev;
3384
3385         retval = device_register(&dev->gadget.dev);
3386         if (retval) {
3387                 put_device(&dev->gadget.dev);
3388                 goto finished;
3389         }
3390
3391         /* timer init */
3392         init_timer(&udc_timer);
3393         udc_timer.function = udc_timer_function;
3394         udc_timer.data = 1;
3395         /* timer pollstall init */
3396         init_timer(&udc_pollstall_timer);
3397         udc_pollstall_timer.function = udc_pollstall_timer_function;
3398         udc_pollstall_timer.data = 1;
3399
3400         /* set SD */
3401         reg = readl(&dev->regs->ctl);
3402         reg |= AMD_BIT(UDC_DEVCTL_SD);
3403         writel(reg, &dev->regs->ctl);
3404
3405         /* print dev register info */
3406         print_regs(dev);
3407
3408         return 0;
3409
3410 finished:
3411         return retval;
3412 }
3413
3414 /* Initiates a remote wakeup */
3415 static int udc_remote_wakeup(struct udc *dev)
3416 {
3417         unsigned long flags;
3418         u32 tmp;
3419
3420         DBG(dev, "UDC initiates remote wakeup\n");
3421
3422         spin_lock_irqsave(&dev->lock, flags);
3423
3424         tmp = readl(&dev->regs->ctl);
3425         tmp |= AMD_BIT(UDC_DEVCTL_RES);
3426         writel(tmp, &dev->regs->ctl);
3427         tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3428         writel(tmp, &dev->regs->ctl);
3429
3430         spin_unlock_irqrestore(&dev->lock, flags);
3431         return 0;
3432 }
3433
3434 /* PCI device parameters */
3435 static const struct pci_device_id pci_id[] = {
3436         {
3437                 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3438                 .class =        (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3439                 .class_mask =   0xffffffff,
3440         },
3441         {},
3442 };
3443 MODULE_DEVICE_TABLE(pci, pci_id);
3444
3445 /* PCI functions */
3446 static struct pci_driver udc_pci_driver = {
3447         .name =         (char *) name,
3448         .id_table =     pci_id,
3449         .probe =        udc_pci_probe,
3450         .remove =       udc_pci_remove,
3451 };
3452
3453 /* Inits driver */
3454 static int __init init(void)
3455 {
3456         return pci_register_driver(&udc_pci_driver);
3457 }
3458 module_init(init);
3459
3460 /* Cleans driver */
3461 static void __exit cleanup(void)
3462 {
3463         pci_unregister_driver(&udc_pci_driver);
3464 }
3465 module_exit(cleanup);
3466
3467 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3468 MODULE_AUTHOR("Thomas Dahlmann");
3469 MODULE_LICENSE("GPL");
3470