drivers/tty/serial/mfd.c

   1 /*
   2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
   3  *
   4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
   5  *
   6  * (C) Copyright 2010 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; version 2
  11  * of the License.
  12  */
  13
  14 /* Notes:
  15  * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
  16  *    2/3 chan to port 1, 4/5 chan to port 3. Even number chans
  17  *    are used for RX, odd chans for TX
  18  *
  19  * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
  20  *    asserted, only when the HW is reset the DDCD and DDSR will
  21  *    be triggered
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/console.h>
  27 #include <linux/sysrq.h>
  28 #include <linux/slab.h>
  29 #include <linux/serial_reg.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/serial_core.h>
  36 #include <linux/serial_mfd.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/pci.h>
  39 #include <linux/io.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/pm_runtime.h>
  42
  43 #define HSU_DMA_BUF_SIZE        2048
  44
  45 #define chan_readl(chan, offset)        readl(chan->reg + offset)
  46 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
  47
  48 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
  49 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
  50
  51 static int hsu_dma_enable;
  52 module_param(hsu_dma_enable, int, 0);
  53 MODULE_PARM_DESC(hsu_dma_enable,
  54                  "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
  55
  56 struct hsu_dma_buffer {
  57         u8              *buf;
  58         dma_addr_t      dma_addr;
  59         u32             dma_size;
  60         u32             ofs;
  61 };
  62
  63 struct hsu_dma_chan {
  64         u32     id;
  65         enum dma_data_direction dirt;
  66         struct uart_hsu_port    *uport;
  67         void __iomem            *reg;
  68 };
  69
  70 struct uart_hsu_port {
  71         struct uart_port        port;
  72         unsigned char           ier;
  73         unsigned char           lcr;
  74         unsigned char           mcr;
  75         unsigned int            lsr_break_flag;
  76         char                    name[12];
  77         int                     index;
  78         struct device           *dev;
  79
  80         struct hsu_dma_chan     *txc;
  81         struct hsu_dma_chan     *rxc;
  82         struct hsu_dma_buffer   txbuf;
  83         struct hsu_dma_buffer   rxbuf;
  84         int                     use_dma;        /* flag for DMA/PIO */
  85         int                     running;
  86         int                     dma_tx_on;
  87 };
  88
  89 /* Top level data structure of HSU */
  90 struct hsu_port {
  91         void __iomem    *reg;
  92         unsigned long   paddr;
  93         unsigned long   iolen;
  94         u32             irq;
  95
  96         struct uart_hsu_port    port[3];
  97         struct hsu_dma_chan     chans[10];
  98
  99         struct dentry *debugfs;
 100 };
 101
 102 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
 103 {
 104         unsigned int val;
 105
 106         if (offset > UART_MSR) {
 107                 offset <<= 2;
 108                 val = readl(up->port.membase + offset);
 109         } else
 110                 val = (unsigned int)readb(up->port.membase + offset);
 111
 112         return val;
 113 }
 114
 115 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
 116 {
 117         if (offset > UART_MSR) {
 118                 offset <<= 2;
 119                 writel(value, up->port.membase + offset);
 120         } else {
 121                 unsigned char val = value & 0xff;
 122                 writeb(val, up->port.membase + offset);
 123         }
 124 }
 125
 126 #ifdef CONFIG_DEBUG_FS
 127
 128 #define HSU_REGS_BUFSIZE        1024
 129
 130 static int hsu_show_regs_open(struct inode *inode, struct file *file)
 131 {
 132         file->private_data = inode->i_private;
 133         return 0;
 134 }
 135
 136 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 137                                 size_t count, loff_t *ppos)
 138 {
 139         struct uart_hsu_port *up = file->private_data;
 140         char *buf;
 141         u32 len = 0;
 142         ssize_t ret;
 143
 144         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 145         if (!buf)
 146                 return 0;
 147
 148         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 149                         "MFD HSU port[%d] regs:\n", up->index);
 150
 151         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 152                         "=================================\n");
 153         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 154                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
 155         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 156                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
 157         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 158                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
 159         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 160                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
 161         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 162                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
 163         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 164                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
 165         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 166                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
 167         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 168                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
 169         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 170                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
 171         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 172                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
 173
 174         if (len > HSU_REGS_BUFSIZE)
 175                 len = HSU_REGS_BUFSIZE;
 176
 177         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 178         kfree(buf);
 179         return ret;
 180 }
 181
 182 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
 183                                 size_t count, loff_t *ppos)
 184 {
 185         struct hsu_dma_chan *chan = file->private_data;
 186         char *buf;
 187         u32 len = 0;
 188         ssize_t ret;
 189
 190         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 191         if (!buf)
 192                 return 0;
 193
 194         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 195                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
 196
 197         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 198                         "=================================\n");
 199         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 200                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
 201         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 202                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
 203         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 204                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
 205         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 206                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
 207         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 208                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
 209         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 210                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
 211         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 212                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
 213         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 214                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
 215         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 216                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
 217         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 218                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
 219         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 220                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
 221         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 222                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
 223
 224         if (len > HSU_REGS_BUFSIZE)
 225                 len = HSU_REGS_BUFSIZE;
 226
 227         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 228         kfree(buf);
 229         return ret;
 230 }
 231
 232 static const struct file_operations port_regs_ops = {
 233         .owner          = THIS_MODULE,
 234         .open           = hsu_show_regs_open,
 235         .read           = port_show_regs,
 236         .llseek         = default_llseek,
 237 };
 238
 239 static const struct file_operations dma_regs_ops = {
 240         .owner          = THIS_MODULE,
 241         .open           = hsu_show_regs_open,
 242         .read           = dma_show_regs,
 243         .llseek         = default_llseek,
 244 };
 245
 246 static int hsu_debugfs_init(struct hsu_port *hsu)
 247 {
 248         int i;
 249         char name[32];
 250
 251         hsu->debugfs = debugfs_create_dir("hsu", NULL);
 252         if (!hsu->debugfs)
 253                 return -ENOMEM;
 254
 255         for (i = 0; i < 3; i++) {
 256                 snprintf(name, sizeof(name), "port_%d_regs", i);
 257                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 258                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
 259         }
 260
 261         for (i = 0; i < 6; i++) {
 262                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
 263                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 264                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
 265         }
 266
 267         return 0;
 268 }
 269
 270 static void hsu_debugfs_remove(struct hsu_port *hsu)
 271 {
 272         if (hsu->debugfs)
 273                 debugfs_remove_recursive(hsu->debugfs);
 274 }
 275
 276 #else
 277 static inline int hsu_debugfs_init(struct hsu_port *hsu)
 278 {
 279         return 0;
 280 }
 281
 282 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
 283 {
 284 }
 285 #endif /* CONFIG_DEBUG_FS */
 286
 287 static void serial_hsu_enable_ms(struct uart_port *port)
 288 {
 289         struct uart_hsu_port *up =
 290                 container_of(port, struct uart_hsu_port, port);
 291
 292         up->ier |= UART_IER_MSI;
 293         serial_out(up, UART_IER, up->ier);
 294 }
 295
 296 void hsu_dma_tx(struct uart_hsu_port *up)
 297 {
 298         struct circ_buf *xmit = &up->port.state->xmit;
 299         struct hsu_dma_buffer *dbuf = &up->txbuf;
 300         int count;
 301
 302         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
 303         if (up->dma_tx_on)
 304                 return;
 305
 306         /* Update the circ buf info */
 307         xmit->tail += dbuf->ofs;
 308         xmit->tail &= UART_XMIT_SIZE - 1;
 309
 310         up->port.icount.tx += dbuf->ofs;
 311         dbuf->ofs = 0;
 312
 313         /* Disable the channel */
 314         chan_writel(up->txc, HSU_CH_CR, 0x0);
 315
 316         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
 317                 dma_sync_single_for_device(up->port.dev,
 318                                            dbuf->dma_addr,
 319                                            dbuf->dma_size,
 320                                            DMA_TO_DEVICE);
 321
 322                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 323                 dbuf->ofs = count;
 324
 325                 /* Reprogram the channel */
 326                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
 327                 chan_writel(up->txc, HSU_CH_D0TSR, count);
 328
 329                 /* Reenable the channel */
 330                 chan_writel(up->txc, HSU_CH_DCR, 0x1
 331                                                  | (0x1 << 8)
 332                                                  | (0x1 << 16)
 333                                                  | (0x1 << 24));
 334                 up->dma_tx_on = 1;
 335                 chan_writel(up->txc, HSU_CH_CR, 0x1);
 336         }
 337
 338         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 339                 uart_write_wakeup(&up->port);
 340 }
 341
 342 /* The buffer is already cache coherent */
 343 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
 344 {
 345         dbuf->ofs = 0;
 346
 347         chan_writel(rxc, HSU_CH_BSR, 32);
 348         chan_writel(rxc, HSU_CH_MOTSR, 4);
 349
 350         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
 351         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
 352         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
 353                                          | (0x1 << 16)
 354                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 355                                          );
 356         chan_writel(rxc, HSU_CH_CR, 0x3);
 357 }
 358
 359 /* Protected by spin_lock_irqsave(port->lock) */
 360 static void serial_hsu_start_tx(struct uart_port *port)
 361 {
 362         struct uart_hsu_port *up =
 363                 container_of(port, struct uart_hsu_port, port);
 364
 365         if (up->use_dma) {
 366                 hsu_dma_tx(up);
 367         } else if (!(up->ier & UART_IER_THRI)) {
 368                 up->ier |= UART_IER_THRI;
 369                 serial_out(up, UART_IER, up->ier);
 370         }
 371 }
 372
 373 static void serial_hsu_stop_tx(struct uart_port *port)
 374 {
 375         struct uart_hsu_port *up =
 376                 container_of(port, struct uart_hsu_port, port);
 377         struct hsu_dma_chan *txc = up->txc;
 378
 379         if (up->use_dma)
 380                 chan_writel(txc, HSU_CH_CR, 0x0);
 381         else if (up->ier & UART_IER_THRI) {
 382                 up->ier &= ~UART_IER_THRI;
 383                 serial_out(up, UART_IER, up->ier);
 384         }
 385 }
 386
 387 /* This is always called in spinlock protected mode, so
 388  * modify timeout timer is safe here */
 389 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
 390 {
 391         struct hsu_dma_buffer *dbuf = &up->rxbuf;
 392         struct hsu_dma_chan *chan = up->rxc;
 393         struct uart_port *port = &up->port;
 394         struct tty_struct *tty = port->state->port.tty;
 395         int count;
 396
 397         if (!tty)
 398                 return;
 399
 400         /*
 401          * First need to know how many is already transferred,
 402          * then check if its a timeout DMA irq, and return
 403          * the trail bytes out, push them up and reenable the
 404          * channel
 405          */
 406
 407         /* Timeout IRQ, need wait some time, see Errata 2 */
 408         if (int_sts & 0xf00)
 409                 udelay(2);
 410
 411         /* Stop the channel */
 412         chan_writel(chan, HSU_CH_CR, 0x0);
 413
 414         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
 415         if (!count) {
 416                 /* Restart the channel before we leave */
 417                 chan_writel(chan, HSU_CH_CR, 0x3);
 418                 return;
 419         }
 420
 421         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
 422                         dbuf->dma_size, DMA_FROM_DEVICE);
 423
 424         /*
 425          * Head will only wrap around when we recycle
 426          * the DMA buffer, and when that happens, we
 427          * explicitly set tail to 0. So head will
 428          * always be greater than tail.
 429          */
 430         tty_insert_flip_string(tty, dbuf->buf, count);
 431         port->icount.rx += count;
 432
 433         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
 434                         dbuf->dma_size, DMA_FROM_DEVICE);
 435
 436         /* Reprogram the channel */
 437         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
 438         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
 439         chan_writel(chan, HSU_CH_DCR, 0x1
 440                                          | (0x1 << 8)
 441                                          | (0x1 << 16)
 442                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 443                                          );
 444         tty_flip_buffer_push(tty);
 445
 446         chan_writel(chan, HSU_CH_CR, 0x3);
 447
 448 }
 449
 450 static void serial_hsu_stop_rx(struct uart_port *port)
 451 {
 452         struct uart_hsu_port *up =
 453                 container_of(port, struct uart_hsu_port, port);
 454         struct hsu_dma_chan *chan = up->rxc;
 455
 456         if (up->use_dma)
 457                 chan_writel(chan, HSU_CH_CR, 0x2);
 458         else {
 459                 up->ier &= ~UART_IER_RLSI;
 460                 up->port.read_status_mask &= ~UART_LSR_DR;
 461                 serial_out(up, UART_IER, up->ier);
 462         }
 463 }
 464
 465 static inline void receive_chars(struct uart_hsu_port *up, int *status)
 466 {
 467         struct tty_struct *tty = up->port.state->port.tty;
 468         unsigned int ch, flag;
 469         unsigned int max_count = 256;
 470
 471         if (!tty)
 472                 return;
 473
 474         do {
 475                 ch = serial_in(up, UART_RX);
 476                 flag = TTY_NORMAL;
 477                 up->port.icount.rx++;
 478
 479                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
 480                                        UART_LSR_FE | UART_LSR_OE))) {
 481
 482                         dev_warn(up->dev, "We really rush into ERR/BI case"
 483                                 "status = 0x%02x", *status);
 484                         /* For statistics only */
 485                         if (*status & UART_LSR_BI) {
 486                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
 487                                 up->port.icount.brk++;
 488                                 /*
 489                                  * We do the SysRQ and SAK checking
 490                                  * here because otherwise the break
 491                                  * may get masked by ignore_status_mask
 492                                  * or read_status_mask.
 493                                  */
 494                                 if (uart_handle_break(&up->port))
 495                                         goto ignore_char;
 496                         } else if (*status & UART_LSR_PE)
 497                                 up->port.icount.parity++;
 498                         else if (*status & UART_LSR_FE)
 499                                 up->port.icount.frame++;
 500                         if (*status & UART_LSR_OE)
 501                                 up->port.icount.overrun++;
 502
 503                         /* Mask off conditions which should be ignored. */
 504                         *status &= up->port.read_status_mask;
 505
 506 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
 507                         if (up->port.cons &&
 508                                 up->port.cons->index == up->port.line) {
 509                                 /* Recover the break flag from console xmit */
 510                                 *status |= up->lsr_break_flag;
 511                                 up->lsr_break_flag = 0;
 512                         }
 513 #endif
 514                         if (*status & UART_LSR_BI) {
 515                                 flag = TTY_BREAK;
 516                         } else if (*status & UART_LSR_PE)
 517                                 flag = TTY_PARITY;
 518                         else if (*status & UART_LSR_FE)
 519                                 flag = TTY_FRAME;
 520                 }
 521
 522                 if (uart_handle_sysrq_char(&up->port, ch))
 523                         goto ignore_char;
 524
 525                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
 526         ignore_char:
 527                 *status = serial_in(up, UART_LSR);
 528         } while ((*status & UART_LSR_DR) && max_count--);
 529         tty_flip_buffer_push(tty);
 530 }
 531
 532 static void transmit_chars(struct uart_hsu_port *up)
 533 {
 534         struct circ_buf *xmit = &up->port.state->xmit;
 535         int count;
 536
 537         if (up->port.x_char) {
 538                 serial_out(up, UART_TX, up->port.x_char);
 539                 up->port.icount.tx++;
 540                 up->port.x_char = 0;
 541                 return;
 542         }
 543         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 544                 serial_hsu_stop_tx(&up->port);
 545                 return;
 546         }
 547
 548         /* The IRQ is for TX FIFO half-empty */
 549         count = up->port.fifosize / 2;
 550
 551         do {
 552                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 553                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 554
 555                 up->port.icount.tx++;
 556                 if (uart_circ_empty(xmit))
 557                         break;
 558         } while (--count > 0);
 559
 560         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 561                 uart_write_wakeup(&up->port);
 562
 563         if (uart_circ_empty(xmit))
 564                 serial_hsu_stop_tx(&up->port);
 565 }
 566
 567 static inline void check_modem_status(struct uart_hsu_port *up)
 568 {
 569         int status;
 570
 571         status = serial_in(up, UART_MSR);
 572
 573         if ((status & UART_MSR_ANY_DELTA) == 0)
 574                 return;
 575
 576         if (status & UART_MSR_TERI)
 577                 up->port.icount.rng++;
 578         if (status & UART_MSR_DDSR)
 579                 up->port.icount.dsr++;
 580         /* We may only get DDCD when HW init and reset */
 581         if (status & UART_MSR_DDCD)
 582                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
 583         /* Will start/stop_tx accordingly */
 584         if (status & UART_MSR_DCTS)
 585                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
 586
 587         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 588 }
 589
 590 /*
 591  * This handles the interrupt from one port.
 592  */
 593 static irqreturn_t port_irq(int irq, void *dev_id)
 594 {
 595         struct uart_hsu_port *up = dev_id;
 596         unsigned int iir, lsr;
 597         unsigned long flags;
 598
 599         if (unlikely(!up->running))
 600                 return IRQ_NONE;
 601
 602         spin_lock_irqsave(&up->port.lock, flags);
 603         if (up->use_dma) {
 604                 lsr = serial_in(up, UART_LSR);
 605                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
 606                                        UART_LSR_FE | UART_LSR_OE)))
 607                         dev_warn(up->dev,
 608                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
 609                                 lsr);
 610                 check_modem_status(up);
 611                 spin_unlock_irqrestore(&up->port.lock, flags);
 612                 return IRQ_HANDLED;
 613         }
 614
 615         iir = serial_in(up, UART_IIR);
 616         if (iir & UART_IIR_NO_INT) {
 617                 spin_unlock_irqrestore(&up->port.lock, flags);
 618                 return IRQ_NONE;
 619         }
 620
 621         lsr = serial_in(up, UART_LSR);
 622         if (lsr & UART_LSR_DR)
 623                 receive_chars(up, &lsr);
 624         check_modem_status(up);
 625
 626         /* lsr will be renewed during the receive_chars */
 627         if (lsr & UART_LSR_THRE)
 628                 transmit_chars(up);
 629
 630         spin_unlock_irqrestore(&up->port.lock, flags);
 631         return IRQ_HANDLED;
 632 }
 633
 634 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
 635 {
 636         struct uart_hsu_port *up = chan->uport;
 637         unsigned long flags;
 638         u32 int_sts;
 639
 640         spin_lock_irqsave(&up->port.lock, flags);
 641
 642         if (!up->use_dma || !up->running)
 643                 goto exit;
 644
 645         /*
 646          * No matter what situation, need read clear the IRQ status
 647          * There is a bug, see Errata 5, HSD 2900918
 648          */
 649         int_sts = chan_readl(chan, HSU_CH_SR);
 650
 651         /* Rx channel */
 652         if (chan->dirt == DMA_FROM_DEVICE)
 653                 hsu_dma_rx(up, int_sts);
 654
 655         /* Tx channel */
 656         if (chan->dirt == DMA_TO_DEVICE) {
 657                 chan_writel(chan, HSU_CH_CR, 0x0);
 658                 up->dma_tx_on = 0;
 659                 hsu_dma_tx(up);
 660         }
 661
 662 exit:
 663         spin_unlock_irqrestore(&up->port.lock, flags);
 664         return;
 665 }
 666
 667 static irqreturn_t dma_irq(int irq, void *dev_id)
 668 {
 669         struct hsu_port *hsu = dev_id;
 670         u32 int_sts, i;
 671
 672         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
 673
 674         /* Currently we only have 6 channels may be used */
 675         for (i = 0; i < 6; i++) {
 676                 if (int_sts & 0x1)
 677                         dma_chan_irq(&hsu->chans[i]);
 678                 int_sts >>= 1;
 679         }
 680
 681         return IRQ_HANDLED;
 682 }
 683
 684 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
 685 {
 686         struct uart_hsu_port *up =
 687                 container_of(port, struct uart_hsu_port, port);
 688         unsigned long flags;
 689         unsigned int ret;
 690
 691         spin_lock_irqsave(&up->port.lock, flags);
 692         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 693         spin_unlock_irqrestore(&up->port.lock, flags);
 694
 695         return ret;
 696 }
 697
 698 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
 699 {
 700         struct uart_hsu_port *up =
 701                 container_of(port, struct uart_hsu_port, port);
 702         unsigned char status;
 703         unsigned int ret;
 704
 705         status = serial_in(up, UART_MSR);
 706
 707         ret = 0;
 708         if (status & UART_MSR_DCD)
 709                 ret |= TIOCM_CAR;
 710         if (status & UART_MSR_RI)
 711                 ret |= TIOCM_RNG;
 712         if (status & UART_MSR_DSR)
 713                 ret |= TIOCM_DSR;
 714         if (status & UART_MSR_CTS)
 715                 ret |= TIOCM_CTS;
 716         return ret;
 717 }
 718
 719 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
 720 {
 721         struct uart_hsu_port *up =
 722                 container_of(port, struct uart_hsu_port, port);
 723         unsigned char mcr = 0;
 724
 725         if (mctrl & TIOCM_RTS)
 726                 mcr |= UART_MCR_RTS;
 727         if (mctrl & TIOCM_DTR)
 728                 mcr |= UART_MCR_DTR;
 729         if (mctrl & TIOCM_OUT1)
 730                 mcr |= UART_MCR_OUT1;
 731         if (mctrl & TIOCM_OUT2)
 732                 mcr |= UART_MCR_OUT2;
 733         if (mctrl & TIOCM_LOOP)
 734                 mcr |= UART_MCR_LOOP;
 735
 736         mcr |= up->mcr;
 737
 738         serial_out(up, UART_MCR, mcr);
 739 }
 740
 741 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
 742 {
 743         struct uart_hsu_port *up =
 744                 container_of(port, struct uart_hsu_port, port);
 745         unsigned long flags;
 746
 747         spin_lock_irqsave(&up->port.lock, flags);
 748         if (break_state == -1)
 749                 up->lcr |= UART_LCR_SBC;
 750         else
 751                 up->lcr &= ~UART_LCR_SBC;
 752         serial_out(up, UART_LCR, up->lcr);
 753         spin_unlock_irqrestore(&up->port.lock, flags);
 754 }
 755
 756 /*
 757  * What special to do:
 758  * 1. chose the 64B fifo mode
 759  * 2. start dma or pio depends on configuration
 760  * 3. we only allocate dma memory when needed
 761  */
 762 static int serial_hsu_startup(struct uart_port *port)
 763 {
 764         struct uart_hsu_port *up =
 765                 container_of(port, struct uart_hsu_port, port);
 766         unsigned long flags;
 767
 768         pm_runtime_get_sync(up->dev);
 769
 770         /*
 771          * Clear the FIFO buffers and disable them.
 772          * (they will be reenabled in set_termios())
 773          */
 774         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 775         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 776                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 777         serial_out(up, UART_FCR, 0);
 778
 779         /* Clear the interrupt registers. */
 780         (void) serial_in(up, UART_LSR);
 781         (void) serial_in(up, UART_RX);
 782         (void) serial_in(up, UART_IIR);
 783         (void) serial_in(up, UART_MSR);
 784
 785         /* Now, initialize the UART, default is 8n1 */
 786         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 787
 788         spin_lock_irqsave(&up->port.lock, flags);
 789
 790         up->port.mctrl |= TIOCM_OUT2;
 791         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 792
 793         /*
 794          * Finally, enable interrupts.  Note: Modem status interrupts
 795          * are set via set_termios(), which will be occurring imminently
 796          * anyway, so we don't enable them here.
 797          */
 798         if (!up->use_dma)
 799                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
 800         else
 801                 up->ier = 0;
 802         serial_out(up, UART_IER, up->ier);
 803
 804         spin_unlock_irqrestore(&up->port.lock, flags);
 805
 806         /* DMA init */
 807         if (up->use_dma) {
 808                 struct hsu_dma_buffer *dbuf;
 809                 struct circ_buf *xmit = &port->state->xmit;
 810
 811                 up->dma_tx_on = 0;
 812
 813                 /* First allocate the RX buffer */
 814                 dbuf = &up->rxbuf;
 815                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
 816                 if (!dbuf->buf) {
 817                         up->use_dma = 0;
 818                         goto exit;
 819                 }
 820                 dbuf->dma_addr = dma_map_single(port->dev,
 821                                                 dbuf->buf,
 822                                                 HSU_DMA_BUF_SIZE,
 823                                                 DMA_FROM_DEVICE);
 824                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
 825
 826                 /* Start the RX channel right now */
 827                 hsu_dma_start_rx_chan(up->rxc, dbuf);
 828
 829                 /* Next init the TX DMA */
 830                 dbuf = &up->txbuf;
 831                 dbuf->buf = xmit->buf;
 832                 dbuf->dma_addr = dma_map_single(port->dev,
 833                                                dbuf->buf,
 834                                                UART_XMIT_SIZE,
 835                                                DMA_TO_DEVICE);
 836                 dbuf->dma_size = UART_XMIT_SIZE;
 837
 838                 /* This should not be changed all around */
 839                 chan_writel(up->txc, HSU_CH_BSR, 32);
 840                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
 841                 dbuf->ofs = 0;
 842         }
 843
 844 exit:
 845          /* And clear the interrupt registers again for luck. */
 846         (void) serial_in(up, UART_LSR);
 847         (void) serial_in(up, UART_RX);
 848         (void) serial_in(up, UART_IIR);
 849         (void) serial_in(up, UART_MSR);
 850
 851         up->running = 1;
 852         return 0;
 853 }
 854
 855 static void serial_hsu_shutdown(struct uart_port *port)
 856 {
 857         struct uart_hsu_port *up =
 858                 container_of(port, struct uart_hsu_port, port);
 859         unsigned long flags;
 860
 861         /* Disable interrupts from this port */
 862         up->ier = 0;
 863         serial_out(up, UART_IER, 0);
 864         up->running = 0;
 865
 866         spin_lock_irqsave(&up->port.lock, flags);
 867         up->port.mctrl &= ~TIOCM_OUT2;
 868         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 869         spin_unlock_irqrestore(&up->port.lock, flags);
 870
 871         /* Disable break condition and FIFOs */
 872         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 873         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 874                                   UART_FCR_CLEAR_RCVR |
 875                                   UART_FCR_CLEAR_XMIT);
 876         serial_out(up, UART_FCR, 0);
 877
 878         pm_runtime_put(up->dev);
 879 }
 880
 881 static void
 882 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
 883                        struct ktermios *old)
 884 {
 885         struct uart_hsu_port *up =
 886                         container_of(port, struct uart_hsu_port, port);
 887         unsigned char cval, fcr = 0;
 888         unsigned long flags;
 889         unsigned int baud, quot;
 890         u32 ps, mul;
 891
 892         switch (termios->c_cflag & CSIZE) {
 893         case CS5:
 894                 cval = UART_LCR_WLEN5;
 895                 break;
 896         case CS6:
 897                 cval = UART_LCR_WLEN6;
 898                 break;
 899         case CS7:
 900                 cval = UART_LCR_WLEN7;
 901                 break;
 902         default:
 903         case CS8:
 904                 cval = UART_LCR_WLEN8;
 905                 break;
 906         }
 907
 908         /* CMSPAR isn't supported by this driver */
 909         termios->c_cflag &= ~CMSPAR;
 910
 911         if (termios->c_cflag & CSTOPB)
 912                 cval |= UART_LCR_STOP;
 913         if (termios->c_cflag & PARENB)
 914                 cval |= UART_LCR_PARITY;
 915         if (!(termios->c_cflag & PARODD))
 916                 cval |= UART_LCR_EPAR;
 917
 918         /*
 919          * The base clk is 50Mhz, and the baud rate come from:
 920          *      baud = 50M * MUL / (DIV * PS * DLAB)
 921          *
 922          * For those basic low baud rate we can get the direct
 923          * scalar from 2746800, like 115200 = 2746800/24. For those
 924          * higher baud rate, we handle them case by case, mainly by
 925          * adjusting the MUL/PS registers, and DIV register is kept
 926          * as default value 0x3d09 to make things simple
 927          */
 928         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 929
 930         quot = 1;
 931         ps = 0x10;
 932         mul = 0x3600;
 933         switch (baud) {
 934         case 3500000:
 935                 mul = 0x3345;
 936                 ps = 0xC;
 937                 break;
 938         case 1843200:
 939                 mul = 0x2400;
 940                 break;
 941         case 3000000:
 942         case 2500000:
 943         case 2000000:
 944         case 1500000:
 945         case 1000000:
 946         case 500000:
 947                 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
 948                 mul = baud / 500000 * 0x9C4;
 949                 break;
 950         default:
 951                 /* Use uart_get_divisor to get quot for other baud rates */
 952                 quot = 0;
 953         }
 954
 955         if (!quot)
 956                 quot = uart_get_divisor(port, baud);
 957
 958         if ((up->port.uartclk / quot) < (2400 * 16))
 959                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
 960         else if ((up->port.uartclk / quot) < (230400 * 16))
 961                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
 962         else
 963                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
 964
 965         fcr |= UART_FCR_HSU_64B_FIFO;
 966
 967         /*
 968          * Ok, we're now changing the port state.  Do it with
 969          * interrupts disabled.
 970          */
 971         spin_lock_irqsave(&up->port.lock, flags);
 972
 973         /* Update the per-port timeout */
 974         uart_update_timeout(port, termios->c_cflag, baud);
 975
 976         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 977         if (termios->c_iflag & INPCK)
 978                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 979         if (termios->c_iflag & (BRKINT | PARMRK))
 980                 up->port.read_status_mask |= UART_LSR_BI;
 981
 982         /* Characters to ignore */
 983         up->port.ignore_status_mask = 0;
 984         if (termios->c_iflag & IGNPAR)
 985                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 986         if (termios->c_iflag & IGNBRK) {
 987                 up->port.ignore_status_mask |= UART_LSR_BI;
 988                 /*
 989                  * If we're ignoring parity and break indicators,
 990                  * ignore overruns too (for real raw support).
 991                  */
 992                 if (termios->c_iflag & IGNPAR)
 993                         up->port.ignore_status_mask |= UART_LSR_OE;
 994         }
 995
 996         /* Ignore all characters if CREAD is not set */
 997         if ((termios->c_cflag & CREAD) == 0)
 998                 up->port.ignore_status_mask |= UART_LSR_DR;
 999
1000         /*
1001          * CTS flow control flag and modem status interrupts, disable
1002          * MSI by default
1003          */
1004         up->ier &= ~UART_IER_MSI;
1005         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1006                 up->ier |= UART_IER_MSI;
1007
1008         serial_out(up, UART_IER, up->ier);
1009
1010         if (termios->c_cflag & CRTSCTS)
1011                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1012         else
1013                 up->mcr &= ~UART_MCR_AFE;
1014
1015         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1016         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1017         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1018         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1019         serial_out(up, UART_MUL, mul);                  /* set MUL */
1020         serial_out(up, UART_PS, ps);                    /* set PS */
1021         up->lcr = cval;                                 /* Save LCR */
1022         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1023         serial_out(up, UART_FCR, fcr);
1024         spin_unlock_irqrestore(&up->port.lock, flags);
1025 }
1026
1027 static void
1028 serial_hsu_pm(struct uart_port *port, unsigned int state,
1029               unsigned int oldstate)
1030 {
1031 }
1032
1033 static void serial_hsu_release_port(struct uart_port *port)
1034 {
1035 }
1036
1037 static int serial_hsu_request_port(struct uart_port *port)
1038 {
1039         return 0;
1040 }
1041
1042 static void serial_hsu_config_port(struct uart_port *port, int flags)
1043 {
1044         struct uart_hsu_port *up =
1045                 container_of(port, struct uart_hsu_port, port);
1046         up->port.type = PORT_MFD;
1047 }
1048
1049 static int
1050 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1051 {
1052         /* We don't want the core code to modify any port params */
1053         return -EINVAL;
1054 }
1055
1056 static const char *
1057 serial_hsu_type(struct uart_port *port)
1058 {
1059         struct uart_hsu_port *up =
1060                 container_of(port, struct uart_hsu_port, port);
1061         return up->name;
1062 }
1063
1064 /* Mainly for uart console use */
1065 static struct uart_hsu_port *serial_hsu_ports[3];
1066 static struct uart_driver serial_hsu_reg;
1067
1068 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1069
1070 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1071
1072 /* Wait for transmitter & holding register to empty */
1073 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1074 {
1075         unsigned int status, tmout = 1000;
1076
1077         /* Wait up to 1ms for the character to be sent. */
1078         do {
1079                 status = serial_in(up, UART_LSR);
1080
1081                 if (status & UART_LSR_BI)
1082                         up->lsr_break_flag = UART_LSR_BI;
1083
1084                 if (--tmout == 0)
1085                         break;
1086                 udelay(1);
1087         } while (!(status & BOTH_EMPTY));
1088
1089         /* Wait up to 1s for flow control if necessary */
1090         if (up->port.flags & UPF_CONS_FLOW) {
1091                 tmout = 1000000;
1092                 while (--tmout &&
1093                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1094                         udelay(1);
1095         }
1096 }
1097
1098 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1099 {
1100         struct uart_hsu_port *up =
1101                 container_of(port, struct uart_hsu_port, port);
1102
1103         wait_for_xmitr(up);
1104         serial_out(up, UART_TX, ch);
1105 }
1106
1107 /*
1108  * Print a string to the serial port trying not to disturb
1109  * any possible real use of the port...
1110  *
1111  *      The console_lock must be held when we get here.
1112  */
1113 static void
1114 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1115 {
1116         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1117         unsigned long flags;
1118         unsigned int ier;
1119         int locked = 1;
1120
1121         local_irq_save(flags);
1122         if (up->port.sysrq)
1123                 locked = 0;
1124         else if (oops_in_progress) {
1125                 locked = spin_trylock(&up->port.lock);
1126         } else
1127                 spin_lock(&up->port.lock);
1128
1129         /* First save the IER then disable the interrupts */
1130         ier = serial_in(up, UART_IER);
1131         serial_out(up, UART_IER, 0);
1132
1133         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1134
1135         /*
1136          * Finally, wait for transmitter to become empty
1137          * and restore the IER
1138          */
1139         wait_for_xmitr(up);
1140         serial_out(up, UART_IER, ier);
1141
1142         if (locked)
1143                 spin_unlock(&up->port.lock);
1144         local_irq_restore(flags);
1145 }
1146
1147 static struct console serial_hsu_console;
1148
1149 static int __init
1150 serial_hsu_console_setup(struct console *co, char *options)
1151 {
1152         struct uart_hsu_port *up;
1153         int baud = 115200;
1154         int bits = 8;
1155         int parity = 'n';
1156         int flow = 'n';
1157         int ret;
1158
1159         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1160                 co->index = 0;
1161         up = serial_hsu_ports[co->index];
1162         if (!up)
1163                 return -ENODEV;
1164
1165         if (options)
1166                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1167
1168         ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1169
1170         return ret;
1171 }
1172
1173 static struct console serial_hsu_console = {
1174         .name           = "ttyMFD",
1175         .write          = serial_hsu_console_write,
1176         .device         = uart_console_device,
1177         .setup          = serial_hsu_console_setup,
1178         .flags          = CON_PRINTBUFFER,
1179         .index          = 2,
1180         .data           = &serial_hsu_reg,
1181 };
1182 #endif
1183
1184 struct uart_ops serial_hsu_pops = {
1185         .tx_empty       = serial_hsu_tx_empty,
1186         .set_mctrl      = serial_hsu_set_mctrl,
1187         .get_mctrl      = serial_hsu_get_mctrl,
1188         .stop_tx        = serial_hsu_stop_tx,
1189         .start_tx       = serial_hsu_start_tx,
1190         .stop_rx        = serial_hsu_stop_rx,
1191         .enable_ms      = serial_hsu_enable_ms,
1192         .break_ctl      = serial_hsu_break_ctl,
1193         .startup        = serial_hsu_startup,
1194         .shutdown       = serial_hsu_shutdown,
1195         .set_termios    = serial_hsu_set_termios,
1196         .pm             = serial_hsu_pm,
1197         .type           = serial_hsu_type,
1198         .release_port   = serial_hsu_release_port,
1199         .request_port   = serial_hsu_request_port,
1200         .config_port    = serial_hsu_config_port,
1201         .verify_port    = serial_hsu_verify_port,
1202 };
1203
1204 static struct uart_driver serial_hsu_reg = {
1205         .owner          = THIS_MODULE,
1206         .driver_name    = "MFD serial",
1207         .dev_name       = "ttyMFD",
1208         .major          = TTY_MAJOR,
1209         .minor          = 128,
1210         .nr             = 3,
1211 };
1212
1213 #ifdef CONFIG_PM
1214 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1215 {
1216         void *priv = pci_get_drvdata(pdev);
1217         struct uart_hsu_port *up;
1218
1219         /* Make sure this is not the internal dma controller */
1220         if (priv && (pdev->device != 0x081E)) {
1221                 up = priv;
1222                 uart_suspend_port(&serial_hsu_reg, &up->port);
1223         }
1224
1225         pci_save_state(pdev);
1226         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1227         return 0;
1228 }
1229
1230 static int serial_hsu_resume(struct pci_dev *pdev)
1231 {
1232         void *priv = pci_get_drvdata(pdev);
1233         struct uart_hsu_port *up;
1234         int ret;
1235
1236         pci_set_power_state(pdev, PCI_D0);
1237         pci_restore_state(pdev);
1238
1239         ret = pci_enable_device(pdev);
1240         if (ret)
1241                 dev_warn(&pdev->dev,
1242                         "HSU: can't re-enable device, try to continue\n");
1243
1244         if (priv && (pdev->device != 0x081E)) {
1245                 up = priv;
1246                 uart_resume_port(&serial_hsu_reg, &up->port);
1247         }
1248         return 0;
1249 }
1250 #else
1251 #define serial_hsu_suspend      NULL
1252 #define serial_hsu_resume       NULL
1253 #endif
1254
1255 #ifdef CONFIG_PM_RUNTIME
1256 static int serial_hsu_runtime_idle(struct device *dev)
1257 {
1258         int err;
1259
1260         err = pm_schedule_suspend(dev, 500);
1261         if (err)
1262                 return -EBUSY;
1263
1264         return 0;
1265 }
1266
1267 static int serial_hsu_runtime_suspend(struct device *dev)
1268 {
1269         return 0;
1270 }
1271
1272 static int serial_hsu_runtime_resume(struct device *dev)
1273 {
1274         return 0;
1275 }
1276 #else
1277 #define serial_hsu_runtime_idle         NULL
1278 #define serial_hsu_runtime_suspend      NULL
1279 #define serial_hsu_runtime_resume       NULL
1280 #endif
1281
1282 static const struct dev_pm_ops serial_hsu_pm_ops = {
1283         .runtime_suspend = serial_hsu_runtime_suspend,
1284         .runtime_resume = serial_hsu_runtime_resume,
1285         .runtime_idle = serial_hsu_runtime_idle,
1286 };
1287
1288 /* temp global pointer before we settle down on using one or four PCI dev */
1289 static struct hsu_port *phsu;
1290
1291 static int serial_hsu_probe(struct pci_dev *pdev,
1292                                 const struct pci_device_id *ent)
1293 {
1294         struct uart_hsu_port *uport;
1295         int index, ret;
1296
1297         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1298                 pdev->vendor, pdev->device);
1299
1300         switch (pdev->device) {
1301         case 0x081B:
1302                 index = 0;
1303                 break;
1304         case 0x081C:
1305                 index = 1;
1306                 break;
1307         case 0x081D:
1308                 index = 2;
1309                 break;
1310         case 0x081E:
1311                 /* internal DMA controller */
1312                 index = 3;
1313                 break;
1314         default:
1315                 dev_err(&pdev->dev, "HSU: out of index!");
1316                 return -ENODEV;
1317         }
1318
1319         ret = pci_enable_device(pdev);
1320         if (ret)
1321                 return ret;
1322
1323         if (index == 3) {
1324                 /* DMA controller */
1325                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1326                 if (ret) {
1327                         dev_err(&pdev->dev, "can not get IRQ\n");
1328                         goto err_disable;
1329                 }
1330                 pci_set_drvdata(pdev, phsu);
1331         } else {
1332                 /* UART port 0~2 */
1333                 uport = &phsu->port[index];
1334                 uport->port.irq = pdev->irq;
1335                 uport->port.dev = &pdev->dev;
1336                 uport->dev = &pdev->dev;
1337
1338                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1339                 if (ret) {
1340                         dev_err(&pdev->dev, "can not get IRQ\n");
1341                         goto err_disable;
1342                 }
1343                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1344
1345 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1346                 if (index == 2) {
1347                         register_console(&serial_hsu_console);
1348                         uport->port.cons = &serial_hsu_console;
1349                 }
1350 #endif
1351                 pci_set_drvdata(pdev, uport);
1352         }
1353
1354         pm_runtime_put_noidle(&pdev->dev);
1355         pm_runtime_allow(&pdev->dev);
1356
1357         return 0;
1358
1359 err_disable:
1360         pci_disable_device(pdev);
1361         return ret;
1362 }
1363
1364 static void hsu_global_init(void)
1365 {
1366         struct hsu_port *hsu;
1367         struct uart_hsu_port *uport;
1368         struct hsu_dma_chan *dchan;
1369         int i, ret;
1370
1371         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1372         if (!hsu)
1373                 return;
1374
1375         /* Get basic io resource and map it */
1376         hsu->paddr = 0xffa28000;
1377         hsu->iolen = 0x1000;
1378
1379         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1380                 pr_warning("HSU: error in request mem region\n");
1381
1382         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1383         if (!hsu->reg) {
1384                 pr_err("HSU: error in ioremap\n");
1385                 ret = -ENOMEM;
1386                 goto err_free_region;
1387         }
1388
1389         /* Initialise the 3 UART ports */
1390         uport = hsu->port;
1391         for (i = 0; i < 3; i++) {
1392                 uport->port.type = PORT_MFD;
1393                 uport->port.iotype = UPIO_MEM;
1394                 uport->port.mapbase = (resource_size_t)hsu->paddr
1395                                         + HSU_PORT_REG_OFFSET
1396                                         + i * HSU_PORT_REG_LENGTH;
1397                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1398                                         + i * HSU_PORT_REG_LENGTH;
1399
1400                 sprintf(uport->name, "hsu_port%d", i);
1401                 uport->port.fifosize = 64;
1402                 uport->port.ops = &serial_hsu_pops;
1403                 uport->port.line = i;
1404                 uport->port.flags = UPF_IOREMAP;
1405                 /* set the scalable maxim support rate to 2746800 bps */
1406                 uport->port.uartclk = 115200 * 24 * 16;
1407
1408                 uport->running = 0;
1409                 uport->txc = &hsu->chans[i * 2];
1410                 uport->rxc = &hsu->chans[i * 2 + 1];
1411
1412                 serial_hsu_ports[i] = uport;
1413                 uport->index = i;
1414
1415                 if (hsu_dma_enable & (1<<i))
1416                         uport->use_dma = 1;
1417                 else
1418                         uport->use_dma = 0;
1419
1420                 uport++;
1421         }
1422
1423         /* Initialise 6 dma channels */
1424         dchan = hsu->chans;
1425         for (i = 0; i < 6; i++) {
1426                 dchan->id = i;
1427                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1428                 dchan->uport = &hsu->port[i/2];
1429                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1430                                 i * HSU_DMA_CHANS_REG_LENGTH;
1431
1432                 dchan++;
1433         }
1434
1435         phsu = hsu;
1436         hsu_debugfs_init(hsu);
1437         return;
1438
1439 err_free_region:
1440         release_mem_region(hsu->paddr, hsu->iolen);
1441         kfree(hsu);
1442         return;
1443 }
1444
1445 static void serial_hsu_remove(struct pci_dev *pdev)
1446 {
1447         void *priv = pci_get_drvdata(pdev);
1448         struct uart_hsu_port *up;
1449
1450         if (!priv)
1451                 return;
1452
1453         pm_runtime_forbid(&pdev->dev);
1454         pm_runtime_get_noresume(&pdev->dev);
1455
1456         /* For port 0/1/2, priv is the address of uart_hsu_port */
1457         if (pdev->device != 0x081E) {
1458                 up = priv;
1459                 uart_remove_one_port(&serial_hsu_reg, &up->port);
1460         }
1461
1462         pci_set_drvdata(pdev, NULL);
1463         free_irq(pdev->irq, priv);
1464         pci_disable_device(pdev);
1465 }
1466
1467 /* First 3 are UART ports, and the 4th is the DMA */
1468 static const struct pci_device_id pci_ids[] __devinitconst = {
1469         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1470         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1471         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1472         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1473         {},
1474 };
1475
1476 static struct pci_driver hsu_pci_driver = {
1477         .name =         "HSU serial",
1478         .id_table =     pci_ids,
1479         .probe =        serial_hsu_probe,
1480         .remove =       __devexit_p(serial_hsu_remove),
1481         .suspend =      serial_hsu_suspend,
1482         .resume =       serial_hsu_resume,
1483         .driver = {
1484                 .pm = &serial_hsu_pm_ops,
1485         },
1486 };
1487
1488 static int __init hsu_pci_init(void)
1489 {
1490         int ret;
1491
1492         hsu_global_init();
1493
1494         ret = uart_register_driver(&serial_hsu_reg);
1495         if (ret)
1496                 return ret;
1497
1498         return pci_register_driver(&hsu_pci_driver);
1499 }
1500
1501 static void __exit hsu_pci_exit(void)
1502 {
1503         pci_unregister_driver(&hsu_pci_driver);
1504         uart_unregister_driver(&serial_hsu_reg);
1505
1506         hsu_debugfs_remove(phsu);
1507
1508         kfree(phsu);
1509 }
1510
1511 module_init(hsu_pci_init);
1512 module_exit(hsu_pci_exit);
1513
1514 MODULE_LICENSE("GPL v2");
1515 MODULE_ALIAS("platform:medfield-hsu");