drivers/tty/serial/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/bitops.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26
  27 #include "8250.h"
  28
  29 #undef SERIAL_DEBUG_PCI
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*probe)(struct pci_dev *dev);
  43         int     (*init)(struct pci_dev *dev);
  44         int     (*setup)(struct serial_private *,
  45                          const struct pciserial_board *,
  46                          struct uart_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static int pci_default_setup(struct serial_private*,
  61           const struct pciserial_board*, struct uart_port*, int);
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING
  66                "%s: %s\n"
  67                "Please send the output of lspci -vv, this\n"
  68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  69                "manufacturer and name of serial board or\n"
  70                "modem board to <linux-serial@vger.kernel.org>.\n",
  71                pci_name(dev), str, dev->vendor, dev->device,
  72                dev->subsystem_vendor, dev->subsystem_device);
  73 }
  74
  75 static int
  76 setup_port(struct serial_private *priv, struct uart_port *port,
  77            int bar, int offset, int regshift)
  78 {
  79         struct pci_dev *dev = priv->dev;
  80         unsigned long base, len;
  81
  82         if (bar >= PCI_NUM_BAR_RESOURCES)
  83                 return -EINVAL;
  84
  85         base = pci_resource_start(dev, bar);
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 len =  pci_resource_len(dev, bar);
  89
  90                 if (!priv->remapped_bar[bar])
  91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  92                 if (!priv->remapped_bar[bar])
  93                         return -ENOMEM;
  94
  95                 port->iotype = UPIO_MEM;
  96                 port->iobase = 0;
  97                 port->mapbase = base + offset;
  98                 port->membase = priv->remapped_bar[bar] + offset;
  99                 port->regshift = regshift;
 100         } else {
 101                 port->iotype = UPIO_PORT;
 102                 port->iobase = base + offset;
 103                 port->mapbase = 0;
 104                 port->membase = NULL;
 105                 port->regshift = 0;
 106         }
 107         return 0;
 108 }
 109
 110 /*
 111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 112  */
 113 static int addidata_apci7800_setup(struct serial_private *priv,
 114                                 const struct pciserial_board *board,
 115                                 struct uart_port *port, int idx)
 116 {
 117         unsigned int bar = 0, offset = board->first_offset;
 118         bar = FL_GET_BASE(board->flags);
 119
 120         if (idx < 2) {
 121                 offset += idx * board->uart_offset;
 122         } else if ((idx >= 2) && (idx < 4)) {
 123                 bar += 1;
 124                 offset += ((idx - 2) * board->uart_offset);
 125         } else if ((idx >= 4) && (idx < 6)) {
 126                 bar += 2;
 127                 offset += ((idx - 4) * board->uart_offset);
 128         } else if (idx >= 6) {
 129                 bar += 3;
 130                 offset += ((idx - 6) * board->uart_offset);
 131         }
 132
 133         return setup_port(priv, port, bar, offset, board->reg_shift);
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 142               struct uart_port *port, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(priv, port, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 183                 rc = 1;
 184                 break;
 185         }
 186
 187         return rc;
 188 }
 189
 190 /*
 191  * HP's Diva chip puts the 4th/5th serial port further out, and
 192  * some serial ports are supposed to be hidden on certain models.
 193  */
 194 static int
 195 pci_hp_diva_setup(struct serial_private *priv,
 196                 const struct pciserial_board *board,
 197                 struct uart_port *port, int idx)
 198 {
 199         unsigned int offset = board->first_offset;
 200         unsigned int bar = FL_GET_BASE(board->flags);
 201
 202         switch (priv->dev->subsystem_device) {
 203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 204                 if (idx == 3)
 205                         idx++;
 206                 break;
 207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 208                 if (idx > 0)
 209                         idx++;
 210                 if (idx > 2)
 211                         idx++;
 212                 break;
 213         }
 214         if (idx > 2)
 215                 offset = 0x18;
 216
 217         offset += idx * board->uart_offset;
 218
 219         return setup_port(priv, port, bar, offset, board->reg_shift);
 220 }
 221
 222 /*
 223  * Added for EKF Intel i960 serial boards
 224  */
 225 static int pci_inteli960ni_init(struct pci_dev *dev)
 226 {
 227         unsigned long oldval;
 228
 229         if (!(dev->subsystem_device & 0x1000))
 230                 return -ENODEV;
 231
 232         /* is firmware started? */
 233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 234         if (oldval == 0x00001000L) { /* RESET value */
 235                 printk(KERN_DEBUG "Local i960 firmware missing");
 236                 return -ENODEV;
 237         }
 238         return 0;
 239 }
 240
 241 /*
 242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 243  * that the card interrupt be explicitly enabled or disabled.  This
 244  * seems to be mainly needed on card using the PLX which also use I/O
 245  * mapped memory.
 246  */
 247 static int pci_plx9050_init(struct pci_dev *dev)
 248 {
 249         u8 irq_config;
 250         void __iomem *p;
 251
 252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 253                 moan_device("no memory in bar 0", dev);
 254                 return 0;
 255         }
 256
 257         irq_config = 0x41;
 258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 260                 irq_config = 0x43;
 261
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         /*
 274          * enable/disable interrupts
 275          */
 276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 277         if (p == NULL)
 278                 return -ENOMEM;
 279         writel(irq_config, p + 0x4c);
 280
 281         /*
 282          * Read the register back to ensure that it took effect.
 283          */
 284         readl(p + 0x4c);
 285         iounmap(p);
 286
 287         return 0;
 288 }
 289
 290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 291 {
 292         u8 __iomem *p;
 293
 294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 295                 return;
 296
 297         /*
 298          * disable interrupts
 299          */
 300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 301         if (p != NULL) {
 302                 writel(0, p + 0x4c);
 303
 304                 /*
 305                  * Read the register back to ensure that it took effect.
 306                  */
 307                 readl(p + 0x4c);
 308                 iounmap(p);
 309         }
 310 }
 311
 312 #define NI8420_INT_ENABLE_REG   0x38
 313 #define NI8420_INT_ENABLE_BIT   0x2000
 314
 315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 316 {
 317         void __iomem *p;
 318         unsigned long base, len;
 319         unsigned int bar = 0;
 320
 321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 322                 moan_device("no memory in bar", dev);
 323                 return;
 324         }
 325
 326         base = pci_resource_start(dev, bar);
 327         len =  pci_resource_len(dev, bar);
 328         p = ioremap_nocache(base, len);
 329         if (p == NULL)
 330                 return;
 331
 332         /* Disable the CPU Interrupt */
 333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 334                p + NI8420_INT_ENABLE_REG);
 335         iounmap(p);
 336 }
 337
 338
 339 /* MITE registers */
 340 #define MITE_IOWBSR1    0xc4
 341 #define MITE_IOWCR1     0xf4
 342 #define MITE_LCIMR1     0x08
 343 #define MITE_LCIMR2     0x10
 344
 345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 346
 347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 348 {
 349         void __iomem *p;
 350         unsigned long base, len;
 351         unsigned int bar = 0;
 352
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357
 358         base = pci_resource_start(dev, bar);
 359         len =  pci_resource_len(dev, bar);
 360         p = ioremap_nocache(base, len);
 361         if (p == NULL)
 362                 return;
 363
 364         /* Disable the CPU Interrupt */
 365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366         iounmap(p);
 367 }
 368
 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370 static int
 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                 struct uart_port *port, int idx)
 373 {
 374         unsigned int bar, offset = board->first_offset;
 375
 376         bar = 0;
 377
 378         if (idx < 4) {
 379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                 offset += idx * board->uart_offset;
 381         } else if (idx < 8) {
 382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                 offset += idx * board->uart_offset + 0xC00;
 384         } else /* we have only 8 ports on PMC-OCTALPRO */
 385                 return 1;
 386
 387         return setup_port(priv, port, bar, offset, board->reg_shift);
 388 }
 389
 390 /*
 391 * This does initialization for PMC OCTALPRO cards:
 392 * maps the device memory, resets the UARTs (needed, bc
 393 * if the module is removed and inserted again, the card
 394 * is in the sleep mode) and enables global interrupt.
 395 */
 396
 397 /* global control register offset for SBS PMC-OctalPro */
 398 #define OCT_REG_CR_OFF          0x500
 399
 400 static int sbs_init(struct pci_dev *dev)
 401 {
 402         u8 __iomem *p;
 403
 404         p = pci_ioremap_bar(dev, 0);
 405
 406         if (p == NULL)
 407                 return -ENOMEM;
 408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409         writeb(0x10, p + OCT_REG_CR_OFF);
 410         udelay(50);
 411         writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413         /* Set bit-2 (INTENABLE) of Control Register */
 414         writeb(0x4, p + OCT_REG_CR_OFF);
 415         iounmap(p);
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Disables the global interrupt of PMC-OctalPro
 422  */
 423
 424 static void __devexit sbs_exit(struct pci_dev *dev)
 425 {
 426         u8 __iomem *p;
 427
 428         p = pci_ioremap_bar(dev, 0);
 429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430         if (p != NULL)
 431                 writeb(0, p + OCT_REG_CR_OFF);
 432         iounmap(p);
 433 }
 434
 435 /*
 436  * SIIG serial cards have an PCI interface chip which also controls
 437  * the UART clocking frequency. Each UART can be clocked independently
 438  * (except cards equipped with 4 UARTs) and initial clocking settings
 439  * are stored in the EEPROM chip. It can cause problems because this
 440  * version of serial driver doesn't support differently clocked UART's
 441  * on single PCI card. To prevent this, initialization functions set
 442  * high frequency clocking for all UART's on given card. It is safe (I
 443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444  * with other OSes (like M$ DOS).
 445  *
 446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447  *
 448  * There is two family of SIIG serial cards with different PCI
 449  * interface chip and different configuration methods:
 450  *     - 10x cards have control registers in IO and/or memory space;
 451  *     - 20x cards have control registers in standard PCI configuration space.
 452  *
 453  * Note: all 10x cards have PCI device ids 0x10..
 454  *       all 20x cards have PCI device ids 0x20..
 455  *
 456  * There are also Quartet Serial cards which use Oxford Semiconductor
 457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458  *
 459  * Note: some SIIG cards are probed by the parport_serial object.
 460  */
 461
 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465 static int pci_siig10x_init(struct pci_dev *dev)
 466 {
 467         u16 data;
 468         void __iomem *p;
 469
 470         switch (dev->device & 0xfff8) {
 471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                 data = 0xffdf;
 473                 break;
 474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                 data = 0xf7ff;
 476                 break;
 477         default:                        /* 1S1P, 4S */
 478                 data = 0xfffb;
 479                 break;
 480         }
 481
 482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 483         if (p == NULL)
 484                 return -ENOMEM;
 485
 486         writew(readw(p + 0x28) & data, p + 0x28);
 487         readw(p + 0x28);
 488         iounmap(p);
 489         return 0;
 490 }
 491
 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495 static int pci_siig20x_init(struct pci_dev *dev)
 496 {
 497         u8 data;
 498
 499         /* Change clock frequency for the first UART. */
 500         pci_read_config_byte(dev, 0x6f, &data);
 501         pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503         /* If this card has 2 UART, we have to do the same with second UART. */
 504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                 pci_read_config_byte(dev, 0x73, &data);
 507                 pci_write_config_byte(dev, 0x73, data & 0xef);
 508         }
 509         return 0;
 510 }
 511
 512 static int pci_siig_init(struct pci_dev *dev)
 513 {
 514         unsigned int type = dev->device & 0xff00;
 515
 516         if (type == 0x1000)
 517                 return pci_siig10x_init(dev);
 518         else if (type == 0x2000)
 519                 return pci_siig20x_init(dev);
 520
 521         moan_device("Unknown SIIG card", dev);
 522         return -ENODEV;
 523 }
 524
 525 static int pci_siig_setup(struct serial_private *priv,
 526                           const struct pciserial_board *board,
 527                           struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531         if (idx > 3) {
 532                 bar = 4;
 533                 offset = (idx - 4) * 8;
 534         }
 535
 536         return setup_port(priv, port, bar, offset, 0);
 537 }
 538
 539 /*
 540  * Timedia has an explosion of boards, and to avoid the PCI table from
 541  * growing *huge*, we use this function to collapse some 70 entries
 542  * in the PCI table into one, for sanity's and compactness's sake.
 543  */
 544 static const unsigned short timedia_single_port[] = {
 545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546 };
 547
 548 static const unsigned short timedia_dual_port[] = {
 549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553         0xD079, 0
 554 };
 555
 556 static const unsigned short timedia_quad_port[] = {
 557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560         0xB157, 0
 561 };
 562
 563 static const unsigned short timedia_eight_port[] = {
 564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566 };
 567
 568 static const struct timedia_struct {
 569         int num;
 570         const unsigned short *ids;
 571 } timedia_data[] = {
 572         { 1, timedia_single_port },
 573         { 2, timedia_dual_port },
 574         { 4, timedia_quad_port },
 575         { 8, timedia_eight_port }
 576 };
 577
 578 /*
 579  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 580  * listing them individually, this driver merely grabs them all with
 581  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 582  * and should be left free to be claimed by parport_serial instead.
 583  */
 584 static int pci_timedia_probe(struct pci_dev *dev)
 585 {
 586         /*
 587          * Check the third digit of the subdevice ID
 588          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 589          */
 590         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 591                 dev_info(&dev->dev,
 592                         "ignoring Timedia subdevice %04x for parport_serial\n",
 593                         dev->subsystem_device);
 594                 return -ENODEV;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int pci_timedia_init(struct pci_dev *dev)
 601 {
 602         const unsigned short *ids;
 603         int i, j;
 604
 605         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 606                 ids = timedia_data[i].ids;
 607                 for (j = 0; ids[j]; j++)
 608                         if (dev->subsystem_device == ids[j])
 609                                 return timedia_data[i].num;
 610         }
 611         return 0;
 612 }
 613
 614 /*
 615  * Timedia/SUNIX uses a mixture of BARs and offsets
 616  * Ugh, this is ugly as all hell --- TYT
 617  */
 618 static int
 619 pci_timedia_setup(struct serial_private *priv,
 620                   const struct pciserial_board *board,
 621                   struct uart_port *port, int idx)
 622 {
 623         unsigned int bar = 0, offset = board->first_offset;
 624
 625         switch (idx) {
 626         case 0:
 627                 bar = 0;
 628                 break;
 629         case 1:
 630                 offset = board->uart_offset;
 631                 bar = 0;
 632                 break;
 633         case 2:
 634                 bar = 1;
 635                 break;
 636         case 3:
 637                 offset = board->uart_offset;
 638                 /* FALLTHROUGH */
 639         case 4: /* BAR 2 */
 640         case 5: /* BAR 3 */
 641         case 6: /* BAR 4 */
 642         case 7: /* BAR 5 */
 643                 bar = idx - 2;
 644         }
 645
 646         return setup_port(priv, port, bar, offset, board->reg_shift);
 647 }
 648
 649 /*
 650  * Some Titan cards are also a little weird
 651  */
 652 static int
 653 titan_400l_800l_setup(struct serial_private *priv,
 654                       const struct pciserial_board *board,
 655                       struct uart_port *port, int idx)
 656 {
 657         unsigned int bar, offset = board->first_offset;
 658
 659         switch (idx) {
 660         case 0:
 661                 bar = 1;
 662                 break;
 663         case 1:
 664                 bar = 2;
 665                 break;
 666         default:
 667                 bar = 4;
 668                 offset = (idx - 2) * board->uart_offset;
 669         }
 670
 671         return setup_port(priv, port, bar, offset, board->reg_shift);
 672 }
 673
 674 static int pci_xircom_init(struct pci_dev *dev)
 675 {
 676         msleep(100);
 677         return 0;
 678 }
 679
 680 static int pci_ni8420_init(struct pci_dev *dev)
 681 {
 682         void __iomem *p;
 683         unsigned long base, len;
 684         unsigned int bar = 0;
 685
 686         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 687                 moan_device("no memory in bar", dev);
 688                 return 0;
 689         }
 690
 691         base = pci_resource_start(dev, bar);
 692         len =  pci_resource_len(dev, bar);
 693         p = ioremap_nocache(base, len);
 694         if (p == NULL)
 695                 return -ENOMEM;
 696
 697         /* Enable CPU Interrupt */
 698         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 699                p + NI8420_INT_ENABLE_REG);
 700
 701         iounmap(p);
 702         return 0;
 703 }
 704
 705 #define MITE_IOWBSR1_WSIZE      0xa
 706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 707 #define MITE_IOWBSR1_WENAB      (1 << 7)
 708 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 709 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 711
 712 static int pci_ni8430_init(struct pci_dev *dev)
 713 {
 714         void __iomem *p;
 715         unsigned long base, len;
 716         u32 device_window;
 717         unsigned int bar = 0;
 718
 719         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 720                 moan_device("no memory in bar", dev);
 721                 return 0;
 722         }
 723
 724         base = pci_resource_start(dev, bar);
 725         len =  pci_resource_len(dev, bar);
 726         p = ioremap_nocache(base, len);
 727         if (p == NULL)
 728                 return -ENOMEM;
 729
 730         /* Set device window address and size in BAR0 */
 731         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 732                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 733         writel(device_window, p + MITE_IOWBSR1);
 734
 735         /* Set window access to go to RAMSEL IO address space */
 736         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 737                p + MITE_IOWCR1);
 738
 739         /* Enable IO Bus Interrupt 0 */
 740         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 741
 742         /* Enable CPU Interrupt */
 743         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 744
 745         iounmap(p);
 746         return 0;
 747 }
 748
 749 /* UART Port Control Register */
 750 #define NI8430_PORTCON  0x0f
 751 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 752
 753 static int
 754 pci_ni8430_setup(struct serial_private *priv,
 755                  const struct pciserial_board *board,
 756                  struct uart_port *port, int idx)
 757 {
 758         void __iomem *p;
 759         unsigned long base, len;
 760         unsigned int bar, offset = board->first_offset;
 761
 762         if (idx >= board->num_ports)
 763                 return 1;
 764
 765         bar = FL_GET_BASE(board->flags);
 766         offset += idx * board->uart_offset;
 767
 768         base = pci_resource_start(priv->dev, bar);
 769         len =  pci_resource_len(priv->dev, bar);
 770         p = ioremap_nocache(base, len);
 771
 772         /* enable the transceiver */
 773         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 774                p + offset + NI8430_PORTCON);
 775
 776         iounmap(p);
 777
 778         return setup_port(priv, port, bar, offset, board->reg_shift);
 779 }
 780
 781 static int pci_netmos_9900_setup(struct serial_private *priv,
 782                                 const struct pciserial_board *board,
 783                                 struct uart_port *port, int idx)
 784 {
 785         unsigned int bar;
 786
 787         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 788                 /* netmos apparently orders BARs by datasheet layout, so serial
 789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 790                  */
 791                 bar = 3 * idx;
 792
 793                 return setup_port(priv, port, bar, 0, board->reg_shift);
 794         } else {
 795                 return pci_default_setup(priv, board, port, idx);
 796         }
 797 }
 798
 799 /* the 99xx series comes with a range of device IDs and a variety
 800  * of capabilities:
 801  *
 802  * 9900 has varying capabilities and can cascade to sub-controllers
 803  *   (cascading should be purely internal)
 804  * 9904 is hardwired with 4 serial ports
 805  * 9912 and 9922 are hardwired with 2 serial ports
 806  */
 807 static int pci_netmos_9900_numports(struct pci_dev *dev)
 808 {
 809         unsigned int c = dev->class;
 810         unsigned int pi;
 811         unsigned short sub_serports;
 812
 813         pi = (c & 0xff);
 814
 815         if (pi == 2) {
 816                 return 1;
 817         } else if ((pi == 0) &&
 818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 819                 /* two possibilities: 0x30ps encodes number of parallel and
 820                  * serial ports, or 0x1000 indicates *something*. This is not
 821                  * immediately obvious, since the 2s1p+4s configuration seems
 822                  * to offer all functionality on functions 0..2, while still
 823                  * advertising the same function 3 as the 4s+2s1p config.
 824                  */
 825                 sub_serports = dev->subsystem_device & 0xf;
 826                 if (sub_serports > 0) {
 827                         return sub_serports;
 828                 } else {
 829                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                         return 0;
 831                 }
 832         }
 833
 834         moan_device("unknown NetMos/Mostech program interface", dev);
 835         return 0;
 836 }
 837
 838 static int pci_netmos_init(struct pci_dev *dev)
 839 {
 840         /* subdevice 0x00PS means <P> parallel, <S> serial */
 841         unsigned int num_serial = dev->subsystem_device & 0xf;
 842
 843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 845                 return 0;
 846
 847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 848                         dev->subsystem_device == 0x0299)
 849                 return 0;
 850
 851         switch (dev->device) { /* FALLTHROUGH on all */
 852                 case PCI_DEVICE_ID_NETMOS_9904:
 853                 case PCI_DEVICE_ID_NETMOS_9912:
 854                 case PCI_DEVICE_ID_NETMOS_9922:
 855                 case PCI_DEVICE_ID_NETMOS_9900:
 856                         num_serial = pci_netmos_9900_numports(dev);
 857                         break;
 858
 859                 default:
 860                         if (num_serial == 0 ) {
 861                                 moan_device("unknown NetMos/Mostech device", dev);
 862                         }
 863         }
 864
 865         if (num_serial == 0)
 866                 return -ENODEV;
 867
 868         return num_serial;
 869 }
 870
 871 /*
 872  * These chips are available with optionally one parallel port and up to
 873  * two serial ports. Unfortunately they all have the same product id.
 874  *
 875  * Basic configuration is done over a region of 32 I/O ports. The base
 876  * ioport is called INTA or INTC, depending on docs/other drivers.
 877  *
 878  * The region of the 32 I/O ports is configured in POSIO0R...
 879  */
 880
 881 /* registers */
 882 #define ITE_887x_MISCR          0x9c
 883 #define ITE_887x_INTCBAR        0x78
 884 #define ITE_887x_UARTBAR        0x7c
 885 #define ITE_887x_PS0BAR         0x10
 886 #define ITE_887x_POSIO0         0x60
 887
 888 /* I/O space size */
 889 #define ITE_887x_IOSIZE         32
 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 895 #define ITE_887x_POSIO_SPEED            (3 << 29)
 896 /* enable IO_Space bit */
 897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 898
 899 static int pci_ite887x_init(struct pci_dev *dev)
 900 {
 901         /* inta_addr are the configuration addresses of the ITE */
 902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 903                                                         0x200, 0x280, 0 };
 904         int ret, i, type;
 905         struct resource *iobase = NULL;
 906         u32 miscr, uartbar, ioport;
 907
 908         /* search for the base-ioport */
 909         i = 0;
 910         while (inta_addr[i] && iobase == NULL) {
 911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 912                                                                 "ite887x");
 913                 if (iobase != NULL) {
 914                         /* write POSIO0R - speed | size | ioport */
 915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 918                         /* write INTCBAR - ioport */
 919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 920                                                                 inta_addr[i]);
 921                         ret = inb(inta_addr[i]);
 922                         if (ret != 0xff) {
 923                                 /* ioport connected */
 924                                 break;
 925                         }
 926                         release_region(iobase->start, ITE_887x_IOSIZE);
 927                         iobase = NULL;
 928                 }
 929                 i++;
 930         }
 931
 932         if (!inta_addr[i]) {
 933                 printk(KERN_ERR "ite887x: could not find iobase\n");
 934                 return -ENODEV;
 935         }
 936
 937         /* start of undocumented type checking (see parport_pc.c) */
 938         type = inb(iobase->start + 0x18) & 0x0f;
 939
 940         switch (type) {
 941         case 0x2:       /* ITE8871 (1P) */
 942         case 0xa:       /* ITE8875 (1P) */
 943                 ret = 0;
 944                 break;
 945         case 0xe:       /* ITE8872 (2S1P) */
 946                 ret = 2;
 947                 break;
 948         case 0x6:       /* ITE8873 (1S) */
 949                 ret = 1;
 950                 break;
 951         case 0x8:       /* ITE8874 (2S) */
 952                 ret = 2;
 953                 break;
 954         default:
 955                 moan_device("Unknown ITE887x", dev);
 956                 ret = -ENODEV;
 957         }
 958
 959         /* configure all serial ports */
 960         for (i = 0; i < ret; i++) {
 961                 /* read the I/O port from the device */
 962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 963                                                                 &ioport);
 964                 ioport &= 0x0000FF00;   /* the actual base address */
 965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 968
 969                 /* write the ioport to the UARTBAR */
 970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 974
 975                 /* get current config */
 976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 977                 /* disable interrupts (UARTx_Routing[3:0]) */
 978                 miscr &= ~(0xf << (12 - 4 * i));
 979                 /* activate the UART (UARTx_En) */
 980                 miscr |= 1 << (23 - i);
 981                 /* write new config with activated UART */
 982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 983         }
 984
 985         if (ret <= 0) {
 986                 /* the device has no UARTs if we get here */
 987                 release_region(iobase->start, ITE_887x_IOSIZE);
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 994 {
 995         u32 ioport;
 996         /* the ioport is bit 0-15 in POSIO0R */
 997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 998         ioport &= 0xffff;
 999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 printk(KERN_DEBUG
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                                                                 number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_port *port, int idx)
1038 {
1039         unsigned int bar, offset = board->first_offset, maxnr;
1040
1041         bar = FL_GET_BASE(board->flags);
1042         if (board->flags & FL_BASE_BARS)
1043                 bar += idx;
1044         else
1045                 offset += idx * board->uart_offset;
1046
1047         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048                 (board->reg_shift + 3);
1049
1050         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051                 return 1;
1052
1053         return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058                   const struct pciserial_board *board,
1059                   struct uart_port *port, int idx)
1060 {
1061         int ret;
1062
1063         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064         port->iotype = UPIO_MEM32;
1065         port->type = PORT_XSCALE;
1066         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067         port->regshift = 2;
1068
1069         return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074                       const struct pciserial_board *board,
1075                       struct uart_port *port, int idx)
1076 {
1077         return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int
1081 pci_brcm_trumanage_setup(struct serial_private *priv,
1082                          const struct pciserial_board *board,
1083                          struct uart_port *port, int idx)
1084 {
1085         int ret = pci_default_setup(priv, board, port, idx);
1086
1087         port->type = PORT_BRCM_TRUMANAGE;
1088         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1089         return ret;
1090 }
1091
1092 static int skip_tx_en_setup(struct serial_private *priv,
1093                         const struct pciserial_board *board,
1094                         struct uart_port *port, int idx)
1095 {
1096         port->flags |= UPF_NO_TXEN_TEST;
1097         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1098                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1099                           priv->dev->vendor,
1100                           priv->dev->device,
1101                           priv->dev->subsystem_vendor,
1102                           priv->dev->subsystem_device);
1103
1104         return pci_default_setup(priv, board, port, idx);
1105 }
1106
1107 static int pci_eg20t_init(struct pci_dev *dev)
1108 {
1109 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1110         return -ENODEV;
1111 #else
1112         return 0;
1113 #endif
1114 }
1115
1116 static int
1117 pci_xr17c154_setup(struct serial_private *priv,
1118                   const struct pciserial_board *board,
1119                   struct uart_port *port, int idx)
1120 {
1121         port->flags |= UPF_EXAR_EFR;
1122         return pci_default_setup(priv, board, port, idx);
1123 }
1124
1125 /* This should be in linux/pci_ids.h */
1126 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1127 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1128 #define PCI_DEVICE_ID_OCTPRO            0x0001
1129 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1130 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1131 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1132 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1133 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1134 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1135 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1136 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1137 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1138 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1139 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1140 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1141 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1142 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1143 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1144 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1145 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1146 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1147 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1148 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1149 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1150 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1151 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1152 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1153 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1154 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1155 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1156 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1157 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1158 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1159
1160 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1161 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1162 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1163
1164 /*
1165  * Master list of serial port init/setup/exit quirks.
1166  * This does not describe the general nature of the port.
1167  * (ie, baud base, number and location of ports, etc)
1168  *
1169  * This list is ordered alphabetically by vendor then device.
1170  * Specific entries must come before more generic entries.
1171  */
1172 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1173         /*
1174         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1175         */
1176         {
1177                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1178                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1179                 .subvendor      = PCI_ANY_ID,
1180                 .subdevice      = PCI_ANY_ID,
1181                 .setup          = addidata_apci7800_setup,
1182         },
1183         /*
1184          * AFAVLAB cards - these may be called via parport_serial
1185          *  It is not clear whether this applies to all products.
1186          */
1187         {
1188                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1189                 .device         = PCI_ANY_ID,
1190                 .subvendor      = PCI_ANY_ID,
1191                 .subdevice      = PCI_ANY_ID,
1192                 .setup          = afavlab_setup,
1193         },
1194         /*
1195          * HP Diva
1196          */
1197         {
1198                 .vendor         = PCI_VENDOR_ID_HP,
1199                 .device         = PCI_DEVICE_ID_HP_DIVA,
1200                 .subvendor      = PCI_ANY_ID,
1201                 .subdevice      = PCI_ANY_ID,
1202                 .init           = pci_hp_diva_init,
1203                 .setup          = pci_hp_diva_setup,
1204         },
1205         /*
1206          * Intel
1207          */
1208         {
1209                 .vendor         = PCI_VENDOR_ID_INTEL,
1210                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1211                 .subvendor      = 0xe4bf,
1212                 .subdevice      = PCI_ANY_ID,
1213                 .init           = pci_inteli960ni_init,
1214                 .setup          = pci_default_setup,
1215         },
1216         {
1217                 .vendor         = PCI_VENDOR_ID_INTEL,
1218                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1219                 .subvendor      = PCI_ANY_ID,
1220                 .subdevice      = PCI_ANY_ID,
1221                 .setup          = skip_tx_en_setup,
1222         },
1223         {
1224                 .vendor         = PCI_VENDOR_ID_INTEL,
1225                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1226                 .subvendor      = PCI_ANY_ID,
1227                 .subdevice      = PCI_ANY_ID,
1228                 .setup          = skip_tx_en_setup,
1229         },
1230         {
1231                 .vendor         = PCI_VENDOR_ID_INTEL,
1232                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1233                 .subvendor      = PCI_ANY_ID,
1234                 .subdevice      = PCI_ANY_ID,
1235                 .setup          = skip_tx_en_setup,
1236         },
1237         {
1238                 .vendor         = PCI_VENDOR_ID_INTEL,
1239                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1240                 .subvendor      = PCI_ANY_ID,
1241                 .subdevice      = PCI_ANY_ID,
1242                 .setup          = ce4100_serial_setup,
1243         },
1244         /*
1245          * ITE
1246          */
1247         {
1248                 .vendor         = PCI_VENDOR_ID_ITE,
1249                 .device         = PCI_DEVICE_ID_ITE_8872,
1250                 .subvendor      = PCI_ANY_ID,
1251                 .subdevice      = PCI_ANY_ID,
1252                 .init           = pci_ite887x_init,
1253                 .setup          = pci_default_setup,
1254                 .exit           = __devexit_p(pci_ite887x_exit),
1255         },
1256         /*
1257          * National Instruments
1258          */
1259         {
1260                 .vendor         = PCI_VENDOR_ID_NI,
1261                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1262                 .subvendor      = PCI_ANY_ID,
1263                 .subdevice      = PCI_ANY_ID,
1264                 .init           = pci_ni8420_init,
1265                 .setup          = pci_default_setup,
1266                 .exit           = __devexit_p(pci_ni8420_exit),
1267         },
1268         {
1269                 .vendor         = PCI_VENDOR_ID_NI,
1270                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1271                 .subvendor      = PCI_ANY_ID,
1272                 .subdevice      = PCI_ANY_ID,
1273                 .init           = pci_ni8420_init,
1274                 .setup          = pci_default_setup,
1275                 .exit           = __devexit_p(pci_ni8420_exit),
1276         },
1277         {
1278                 .vendor         = PCI_VENDOR_ID_NI,
1279                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1280                 .subvendor      = PCI_ANY_ID,
1281                 .subdevice      = PCI_ANY_ID,
1282                 .init           = pci_ni8420_init,
1283                 .setup          = pci_default_setup,
1284                 .exit           = __devexit_p(pci_ni8420_exit),
1285         },
1286         {
1287                 .vendor         = PCI_VENDOR_ID_NI,
1288                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1289                 .subvendor      = PCI_ANY_ID,
1290                 .subdevice      = PCI_ANY_ID,
1291                 .init           = pci_ni8420_init,
1292                 .setup          = pci_default_setup,
1293                 .exit           = __devexit_p(pci_ni8420_exit),
1294         },
1295         {
1296                 .vendor         = PCI_VENDOR_ID_NI,
1297                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1298                 .subvendor      = PCI_ANY_ID,
1299                 .subdevice      = PCI_ANY_ID,
1300                 .init           = pci_ni8420_init,
1301                 .setup          = pci_default_setup,
1302                 .exit           = __devexit_p(pci_ni8420_exit),
1303         },
1304         {
1305                 .vendor         = PCI_VENDOR_ID_NI,
1306                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1307                 .subvendor      = PCI_ANY_ID,
1308                 .subdevice      = PCI_ANY_ID,
1309                 .init           = pci_ni8420_init,
1310                 .setup          = pci_default_setup,
1311                 .exit           = __devexit_p(pci_ni8420_exit),
1312         },
1313         {
1314                 .vendor         = PCI_VENDOR_ID_NI,
1315                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1316                 .subvendor      = PCI_ANY_ID,
1317                 .subdevice      = PCI_ANY_ID,
1318                 .init           = pci_ni8420_init,
1319                 .setup          = pci_default_setup,
1320                 .exit           = __devexit_p(pci_ni8420_exit),
1321         },
1322         {
1323                 .vendor         = PCI_VENDOR_ID_NI,
1324                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1325                 .subvendor      = PCI_ANY_ID,
1326                 .subdevice      = PCI_ANY_ID,
1327                 .init           = pci_ni8420_init,
1328                 .setup          = pci_default_setup,
1329                 .exit           = __devexit_p(pci_ni8420_exit),
1330         },
1331         {
1332                 .vendor         = PCI_VENDOR_ID_NI,
1333                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1334                 .subvendor      = PCI_ANY_ID,
1335                 .subdevice      = PCI_ANY_ID,
1336                 .init           = pci_ni8420_init,
1337                 .setup          = pci_default_setup,
1338                 .exit           = __devexit_p(pci_ni8420_exit),
1339         },
1340         {
1341                 .vendor         = PCI_VENDOR_ID_NI,
1342                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1343                 .subvendor      = PCI_ANY_ID,
1344                 .subdevice      = PCI_ANY_ID,
1345                 .init           = pci_ni8420_init,
1346                 .setup          = pci_default_setup,
1347                 .exit           = __devexit_p(pci_ni8420_exit),
1348         },
1349         {
1350                 .vendor         = PCI_VENDOR_ID_NI,
1351                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1352                 .subvendor      = PCI_ANY_ID,
1353                 .subdevice      = PCI_ANY_ID,
1354                 .init           = pci_ni8420_init,
1355                 .setup          = pci_default_setup,
1356                 .exit           = __devexit_p(pci_ni8420_exit),
1357         },
1358         {
1359                 .vendor         = PCI_VENDOR_ID_NI,
1360                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1361                 .subvendor      = PCI_ANY_ID,
1362                 .subdevice      = PCI_ANY_ID,
1363                 .init           = pci_ni8420_init,
1364                 .setup          = pci_default_setup,
1365                 .exit           = __devexit_p(pci_ni8420_exit),
1366         },
1367         {
1368                 .vendor         = PCI_VENDOR_ID_NI,
1369                 .device         = PCI_ANY_ID,
1370                 .subvendor      = PCI_ANY_ID,
1371                 .subdevice      = PCI_ANY_ID,
1372                 .init           = pci_ni8430_init,
1373                 .setup          = pci_ni8430_setup,
1374                 .exit           = __devexit_p(pci_ni8430_exit),
1375         },
1376         /*
1377          * Panacom
1378          */
1379         {
1380                 .vendor         = PCI_VENDOR_ID_PANACOM,
1381                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1382                 .subvendor      = PCI_ANY_ID,
1383                 .subdevice      = PCI_ANY_ID,
1384                 .init           = pci_plx9050_init,
1385                 .setup          = pci_default_setup,
1386                 .exit           = __devexit_p(pci_plx9050_exit),
1387         },
1388         {
1389                 .vendor         = PCI_VENDOR_ID_PANACOM,
1390                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1391                 .subvendor      = PCI_ANY_ID,
1392                 .subdevice      = PCI_ANY_ID,
1393                 .init           = pci_plx9050_init,
1394                 .setup          = pci_default_setup,
1395                 .exit           = __devexit_p(pci_plx9050_exit),
1396         },
1397         /*
1398          * PLX
1399          */
1400         {
1401                 .vendor         = PCI_VENDOR_ID_PLX,
1402                 .device         = PCI_DEVICE_ID_PLX_9030,
1403                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1404                 .subdevice      = PCI_ANY_ID,
1405                 .setup          = pci_default_setup,
1406         },
1407         {
1408                 .vendor         = PCI_VENDOR_ID_PLX,
1409                 .device         = PCI_DEVICE_ID_PLX_9050,
1410                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1411                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1412                 .init           = pci_plx9050_init,
1413                 .setup          = pci_default_setup,
1414                 .exit           = __devexit_p(pci_plx9050_exit),
1415         },
1416         {
1417                 .vendor         = PCI_VENDOR_ID_PLX,
1418                 .device         = PCI_DEVICE_ID_PLX_9050,
1419                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1420                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1421                 .init           = pci_plx9050_init,
1422                 .setup          = pci_default_setup,
1423                 .exit           = __devexit_p(pci_plx9050_exit),
1424         },
1425         {
1426                 .vendor         = PCI_VENDOR_ID_PLX,
1427                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1428                 .subvendor      = PCI_VENDOR_ID_PLX,
1429                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1430                 .init           = pci_plx9050_init,
1431                 .setup          = pci_default_setup,
1432                 .exit           = __devexit_p(pci_plx9050_exit),
1433         },
1434         /*
1435          * SBS Technologies, Inc., PMC-OCTALPRO 232
1436          */
1437         {
1438                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1439                 .device         = PCI_DEVICE_ID_OCTPRO,
1440                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1441                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1442                 .init           = sbs_init,
1443                 .setup          = sbs_setup,
1444                 .exit           = __devexit_p(sbs_exit),
1445         },
1446         /*
1447          * SBS Technologies, Inc., PMC-OCTALPRO 422
1448          */
1449         {
1450                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1451                 .device         = PCI_DEVICE_ID_OCTPRO,
1452                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1453                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1454                 .init           = sbs_init,
1455                 .setup          = sbs_setup,
1456                 .exit           = __devexit_p(sbs_exit),
1457         },
1458         /*
1459          * SBS Technologies, Inc., P-Octal 232
1460          */
1461         {
1462                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1463                 .device         = PCI_DEVICE_ID_OCTPRO,
1464                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1465                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1466                 .init           = sbs_init,
1467                 .setup          = sbs_setup,
1468                 .exit           = __devexit_p(sbs_exit),
1469         },
1470         /*
1471          * SBS Technologies, Inc., P-Octal 422
1472          */
1473         {
1474                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1475                 .device         = PCI_DEVICE_ID_OCTPRO,
1476                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1477                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1478                 .init           = sbs_init,
1479                 .setup          = sbs_setup,
1480                 .exit           = __devexit_p(sbs_exit),
1481         },
1482         /*
1483          * SIIG cards - these may be called via parport_serial
1484          */
1485         {
1486                 .vendor         = PCI_VENDOR_ID_SIIG,
1487                 .device         = PCI_ANY_ID,
1488                 .subvendor      = PCI_ANY_ID,
1489                 .subdevice      = PCI_ANY_ID,
1490                 .init           = pci_siig_init,
1491                 .setup          = pci_siig_setup,
1492         },
1493         /*
1494          * Titan cards
1495          */
1496         {
1497                 .vendor         = PCI_VENDOR_ID_TITAN,
1498                 .device         = PCI_DEVICE_ID_TITAN_400L,
1499                 .subvendor      = PCI_ANY_ID,
1500                 .subdevice      = PCI_ANY_ID,
1501                 .setup          = titan_400l_800l_setup,
1502         },
1503         {
1504                 .vendor         = PCI_VENDOR_ID_TITAN,
1505                 .device         = PCI_DEVICE_ID_TITAN_800L,
1506                 .subvendor      = PCI_ANY_ID,
1507                 .subdevice      = PCI_ANY_ID,
1508                 .setup          = titan_400l_800l_setup,
1509         },
1510         /*
1511          * Timedia cards
1512          */
1513         {
1514                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1515                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1516                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1517                 .subdevice      = PCI_ANY_ID,
1518                 .probe          = pci_timedia_probe,
1519                 .init           = pci_timedia_init,
1520                 .setup          = pci_timedia_setup,
1521         },
1522         {
1523                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1524                 .device         = PCI_ANY_ID,
1525                 .subvendor      = PCI_ANY_ID,
1526                 .subdevice      = PCI_ANY_ID,
1527                 .setup          = pci_timedia_setup,
1528         },
1529         /*
1530          * Exar cards
1531          */
1532         {
1533                 .vendor = PCI_VENDOR_ID_EXAR,
1534                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1535                 .subvendor      = PCI_ANY_ID,
1536                 .subdevice      = PCI_ANY_ID,
1537                 .setup          = pci_xr17c154_setup,
1538         },
1539         {
1540                 .vendor = PCI_VENDOR_ID_EXAR,
1541                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1542                 .subvendor      = PCI_ANY_ID,
1543                 .subdevice      = PCI_ANY_ID,
1544                 .setup          = pci_xr17c154_setup,
1545         },
1546         {
1547                 .vendor = PCI_VENDOR_ID_EXAR,
1548                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1549                 .subvendor      = PCI_ANY_ID,
1550                 .subdevice      = PCI_ANY_ID,
1551                 .setup          = pci_xr17c154_setup,
1552         },
1553         /*
1554          * Xircom cards
1555          */
1556         {
1557                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1558                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1559                 .subvendor      = PCI_ANY_ID,
1560                 .subdevice      = PCI_ANY_ID,
1561                 .init           = pci_xircom_init,
1562                 .setup          = pci_default_setup,
1563         },
1564         /*
1565          * Netmos cards - these may be called via parport_serial
1566          */
1567         {
1568                 .vendor         = PCI_VENDOR_ID_NETMOS,
1569                 .device         = PCI_ANY_ID,
1570                 .subvendor      = PCI_ANY_ID,
1571                 .subdevice      = PCI_ANY_ID,
1572                 .init           = pci_netmos_init,
1573                 .setup          = pci_netmos_9900_setup,
1574         },
1575         /*
1576          * For Oxford Semiconductor Tornado based devices
1577          */
1578         {
1579                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1580                 .device         = PCI_ANY_ID,
1581                 .subvendor      = PCI_ANY_ID,
1582                 .subdevice      = PCI_ANY_ID,
1583                 .init           = pci_oxsemi_tornado_init,
1584                 .setup          = pci_default_setup,
1585         },
1586         {
1587                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1588                 .device         = PCI_ANY_ID,
1589                 .subvendor      = PCI_ANY_ID,
1590                 .subdevice      = PCI_ANY_ID,
1591                 .init           = pci_oxsemi_tornado_init,
1592                 .setup          = pci_default_setup,
1593         },
1594         {
1595                 .vendor         = PCI_VENDOR_ID_DIGI,
1596                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1597                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1598                 .subdevice              = PCI_ANY_ID,
1599                 .init                   = pci_oxsemi_tornado_init,
1600                 .setup          = pci_default_setup,
1601         },
1602         {
1603                 .vendor         = PCI_VENDOR_ID_INTEL,
1604                 .device         = 0x8811,
1605                 .subvendor      = PCI_ANY_ID,
1606                 .subdevice      = PCI_ANY_ID,
1607                 .init           = pci_eg20t_init,
1608                 .setup          = pci_default_setup,
1609         },
1610         {
1611                 .vendor         = PCI_VENDOR_ID_INTEL,
1612                 .device         = 0x8812,
1613                 .subvendor      = PCI_ANY_ID,
1614                 .subdevice      = PCI_ANY_ID,
1615                 .init           = pci_eg20t_init,
1616                 .setup          = pci_default_setup,
1617         },
1618         {
1619                 .vendor         = PCI_VENDOR_ID_INTEL,
1620                 .device         = 0x8813,
1621                 .subvendor      = PCI_ANY_ID,
1622                 .subdevice      = PCI_ANY_ID,
1623                 .init           = pci_eg20t_init,
1624                 .setup          = pci_default_setup,
1625         },
1626         {
1627                 .vendor         = PCI_VENDOR_ID_INTEL,
1628                 .device         = 0x8814,
1629                 .subvendor      = PCI_ANY_ID,
1630                 .subdevice      = PCI_ANY_ID,
1631                 .init           = pci_eg20t_init,
1632                 .setup          = pci_default_setup,
1633         },
1634         {
1635                 .vendor         = 0x10DB,
1636                 .device         = 0x8027,
1637                 .subvendor      = PCI_ANY_ID,
1638                 .subdevice      = PCI_ANY_ID,
1639                 .init           = pci_eg20t_init,
1640                 .setup          = pci_default_setup,
1641         },
1642         {
1643                 .vendor         = 0x10DB,
1644                 .device         = 0x8028,
1645                 .subvendor      = PCI_ANY_ID,
1646                 .subdevice      = PCI_ANY_ID,
1647                 .init           = pci_eg20t_init,
1648                 .setup          = pci_default_setup,
1649         },
1650         {
1651                 .vendor         = 0x10DB,
1652                 .device         = 0x8029,
1653                 .subvendor      = PCI_ANY_ID,
1654                 .subdevice      = PCI_ANY_ID,
1655                 .init           = pci_eg20t_init,
1656                 .setup          = pci_default_setup,
1657         },
1658         {
1659                 .vendor         = 0x10DB,
1660                 .device         = 0x800C,
1661                 .subvendor      = PCI_ANY_ID,
1662                 .subdevice      = PCI_ANY_ID,
1663                 .init           = pci_eg20t_init,
1664                 .setup          = pci_default_setup,
1665         },
1666         {
1667                 .vendor         = 0x10DB,
1668                 .device         = 0x800D,
1669                 .subvendor      = PCI_ANY_ID,
1670                 .subdevice      = PCI_ANY_ID,
1671                 .init           = pci_eg20t_init,
1672                 .setup          = pci_default_setup,
1673         },
1674         /*
1675          * Cronyx Omega PCI (PLX-chip based)
1676          */
1677         {
1678                 .vendor         = PCI_VENDOR_ID_PLX,
1679                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1680                 .subvendor      = PCI_ANY_ID,
1681                 .subdevice      = PCI_ANY_ID,
1682                 .setup          = pci_omegapci_setup,
1683          },
1684         /*
1685          * Broadcom TruManage (NetXtreme)
1686          */
1687         {
1688                 .vendor         = PCI_VENDOR_ID_BROADCOM,
1689                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
1690                 .subvendor      = PCI_ANY_ID,
1691                 .subdevice      = PCI_ANY_ID,
1692                 .setup          = pci_brcm_trumanage_setup,
1693         },
1694
1695         /*
1696          * Default "match everything" terminator entry
1697          */
1698         {
1699                 .vendor         = PCI_ANY_ID,
1700                 .device         = PCI_ANY_ID,
1701                 .subvendor      = PCI_ANY_ID,
1702                 .subdevice      = PCI_ANY_ID,
1703                 .setup          = pci_default_setup,
1704         }
1705 };
1706
1707 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1708 {
1709         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1710 }
1711
1712 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1713 {
1714         struct pci_serial_quirk *quirk;
1715
1716         for (quirk = pci_serial_quirks; ; quirk++)
1717                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1718                     quirk_id_matches(quirk->device, dev->device) &&
1719                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1720                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1721                         break;
1722         return quirk;
1723 }
1724
1725 static inline int get_pci_irq(struct pci_dev *dev,
1726                                 const struct pciserial_board *board)
1727 {
1728         if (board->flags & FL_NOIRQ)
1729                 return 0;
1730         else
1731                 return dev->irq;
1732 }
1733
1734 /*
1735  * This is the configuration table for all of the PCI serial boards
1736  * which we support.  It is directly indexed by the pci_board_num_t enum
1737  * value, which is encoded in the pci_device_id PCI probe table's
1738  * driver_data member.
1739  *
1740  * The makeup of these names are:
1741  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1742  *
1743  *  bn          = PCI BAR number
1744  *  bt          = Index using PCI BARs
1745  *  n           = number of serial ports
1746  *  baud        = baud rate
1747  *  offsetinhex = offset for each sequential port (in hex)
1748  *
1749  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1750  *
1751  * Please note: in theory if n = 1, _bt infix should make no difference.
1752  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1753  */
1754 enum pci_board_num_t {
1755         pbn_default = 0,
1756
1757         pbn_b0_1_115200,
1758         pbn_b0_2_115200,
1759         pbn_b0_4_115200,
1760         pbn_b0_5_115200,
1761         pbn_b0_8_115200,
1762
1763         pbn_b0_1_921600,
1764         pbn_b0_2_921600,
1765         pbn_b0_4_921600,
1766
1767         pbn_b0_2_1130000,
1768
1769         pbn_b0_4_1152000,
1770
1771         pbn_b0_4_1250000,
1772
1773         pbn_b0_2_1843200,
1774         pbn_b0_4_1843200,
1775
1776         pbn_b0_2_1843200_200,
1777         pbn_b0_4_1843200_200,
1778         pbn_b0_8_1843200_200,
1779
1780         pbn_b0_1_4000000,
1781
1782         pbn_b0_bt_1_115200,
1783         pbn_b0_bt_2_115200,
1784         pbn_b0_bt_4_115200,
1785         pbn_b0_bt_8_115200,
1786
1787         pbn_b0_bt_1_460800,
1788         pbn_b0_bt_2_460800,
1789         pbn_b0_bt_4_460800,
1790
1791         pbn_b0_bt_1_921600,
1792         pbn_b0_bt_2_921600,
1793         pbn_b0_bt_4_921600,
1794         pbn_b0_bt_8_921600,
1795
1796         pbn_b1_1_115200,
1797         pbn_b1_2_115200,
1798         pbn_b1_4_115200,
1799         pbn_b1_8_115200,
1800         pbn_b1_16_115200,
1801
1802         pbn_b1_1_921600,
1803         pbn_b1_2_921600,
1804         pbn_b1_4_921600,
1805         pbn_b1_8_921600,
1806
1807         pbn_b1_2_1250000,
1808
1809         pbn_b1_bt_1_115200,
1810         pbn_b1_bt_2_115200,
1811         pbn_b1_bt_4_115200,
1812
1813         pbn_b1_bt_2_921600,
1814
1815         pbn_b1_1_1382400,
1816         pbn_b1_2_1382400,
1817         pbn_b1_4_1382400,
1818         pbn_b1_8_1382400,
1819
1820         pbn_b2_1_115200,
1821         pbn_b2_2_115200,
1822         pbn_b2_4_115200,
1823         pbn_b2_8_115200,
1824
1825         pbn_b2_1_460800,
1826         pbn_b2_4_460800,
1827         pbn_b2_8_460800,
1828         pbn_b2_16_460800,
1829
1830         pbn_b2_1_921600,
1831         pbn_b2_4_921600,
1832         pbn_b2_8_921600,
1833
1834         pbn_b2_8_1152000,
1835
1836         pbn_b2_bt_1_115200,
1837         pbn_b2_bt_2_115200,
1838         pbn_b2_bt_4_115200,
1839
1840         pbn_b2_bt_2_921600,
1841         pbn_b2_bt_4_921600,
1842
1843         pbn_b3_2_115200,
1844         pbn_b3_4_115200,
1845         pbn_b3_8_115200,
1846
1847         pbn_b4_bt_2_921600,
1848         pbn_b4_bt_4_921600,
1849         pbn_b4_bt_8_921600,
1850
1851         /*
1852          * Board-specific versions.
1853          */
1854         pbn_panacom,
1855         pbn_panacom2,
1856         pbn_panacom4,
1857         pbn_exsys_4055,
1858         pbn_plx_romulus,
1859         pbn_oxsemi,
1860         pbn_oxsemi_1_4000000,
1861         pbn_oxsemi_2_4000000,
1862         pbn_oxsemi_4_4000000,
1863         pbn_oxsemi_8_4000000,
1864         pbn_intel_i960,
1865         pbn_sgi_ioc3,
1866         pbn_computone_4,
1867         pbn_computone_6,
1868         pbn_computone_8,
1869         pbn_sbsxrsio,
1870         pbn_exar_XR17C152,
1871         pbn_exar_XR17C154,
1872         pbn_exar_XR17C158,
1873         pbn_exar_ibm_saturn,
1874         pbn_pasemi_1682M,
1875         pbn_ni8430_2,
1876         pbn_ni8430_4,
1877         pbn_ni8430_8,
1878         pbn_ni8430_16,
1879         pbn_ADDIDATA_PCIe_1_3906250,
1880         pbn_ADDIDATA_PCIe_2_3906250,
1881         pbn_ADDIDATA_PCIe_4_3906250,
1882         pbn_ADDIDATA_PCIe_8_3906250,
1883         pbn_ce4100_1_115200,
1884         pbn_omegapci,
1885         pbn_NETMOS9900_2s_115200,
1886         pbn_brcm_trumanage,
1887 };
1888
1889 /*
1890  * uart_offset - the space between channels
1891  * reg_shift   - describes how the UART registers are mapped
1892  *               to PCI memory by the card.
1893  * For example IER register on SBS, Inc. PMC-OctPro is located at
1894  * offset 0x10 from the UART base, while UART_IER is defined as 1
1895  * in include/linux/serial_reg.h,
1896  * see first lines of serial_in() and serial_out() in 8250.c
1897 */
1898
1899 static struct pciserial_board pci_boards[] __devinitdata = {
1900         [pbn_default] = {
1901                 .flags          = FL_BASE0,
1902                 .num_ports      = 1,
1903                 .base_baud      = 115200,
1904                 .uart_offset    = 8,
1905         },
1906         [pbn_b0_1_115200] = {
1907                 .flags          = FL_BASE0,
1908                 .num_ports      = 1,
1909                 .base_baud      = 115200,
1910                 .uart_offset    = 8,
1911         },
1912         [pbn_b0_2_115200] = {
1913                 .flags          = FL_BASE0,
1914                 .num_ports      = 2,
1915                 .base_baud      = 115200,
1916                 .uart_offset    = 8,
1917         },
1918         [pbn_b0_4_115200] = {
1919                 .flags          = FL_BASE0,
1920                 .num_ports      = 4,
1921                 .base_baud      = 115200,
1922                 .uart_offset    = 8,
1923         },
1924         [pbn_b0_5_115200] = {
1925                 .flags          = FL_BASE0,
1926                 .num_ports      = 5,
1927                 .base_baud      = 115200,
1928                 .uart_offset    = 8,
1929         },
1930         [pbn_b0_8_115200] = {
1931                 .flags          = FL_BASE0,
1932                 .num_ports      = 8,
1933                 .base_baud      = 115200,
1934                 .uart_offset    = 8,
1935         },
1936         [pbn_b0_1_921600] = {
1937                 .flags          = FL_BASE0,
1938                 .num_ports      = 1,
1939                 .base_baud      = 921600,
1940                 .uart_offset    = 8,
1941         },
1942         [pbn_b0_2_921600] = {
1943                 .flags          = FL_BASE0,
1944                 .num_ports      = 2,
1945                 .base_baud      = 921600,
1946                 .uart_offset    = 8,
1947         },
1948         [pbn_b0_4_921600] = {
1949                 .flags          = FL_BASE0,
1950                 .num_ports      = 4,
1951                 .base_baud      = 921600,
1952                 .uart_offset    = 8,
1953         },
1954
1955         [pbn_b0_2_1130000] = {
1956                 .flags          = FL_BASE0,
1957                 .num_ports      = 2,
1958                 .base_baud      = 1130000,
1959                 .uart_offset    = 8,
1960         },
1961
1962         [pbn_b0_4_1152000] = {
1963                 .flags          = FL_BASE0,
1964                 .num_ports      = 4,
1965                 .base_baud      = 1152000,
1966                 .uart_offset    = 8,
1967         },
1968
1969         [pbn_b0_4_1250000] = {
1970                 .flags          = FL_BASE0,
1971                 .num_ports      = 4,
1972                 .base_baud      = 1250000,
1973                 .uart_offset    = 8,
1974         },
1975
1976         [pbn_b0_2_1843200] = {
1977                 .flags          = FL_BASE0,
1978                 .num_ports      = 2,
1979                 .base_baud      = 1843200,
1980                 .uart_offset    = 8,
1981         },
1982         [pbn_b0_4_1843200] = {
1983                 .flags          = FL_BASE0,
1984                 .num_ports      = 4,
1985                 .base_baud      = 1843200,
1986                 .uart_offset    = 8,
1987         },
1988
1989         [pbn_b0_2_1843200_200] = {
1990                 .flags          = FL_BASE0,
1991                 .num_ports      = 2,
1992                 .base_baud      = 1843200,
1993                 .uart_offset    = 0x200,
1994         },
1995         [pbn_b0_4_1843200_200] = {
1996                 .flags          = FL_BASE0,
1997                 .num_ports      = 4,
1998                 .base_baud      = 1843200,
1999                 .uart_offset    = 0x200,
2000         },
2001         [pbn_b0_8_1843200_200] = {
2002                 .flags          = FL_BASE0,
2003                 .num_ports      = 8,
2004                 .base_baud      = 1843200,
2005                 .uart_offset    = 0x200,
2006         },
2007         [pbn_b0_1_4000000] = {
2008                 .flags          = FL_BASE0,
2009                 .num_ports      = 1,
2010                 .base_baud      = 4000000,
2011                 .uart_offset    = 8,
2012         },
2013
2014         [pbn_b0_bt_1_115200] = {
2015                 .flags          = FL_BASE0|FL_BASE_BARS,
2016                 .num_ports      = 1,
2017                 .base_baud      = 115200,
2018                 .uart_offset    = 8,
2019         },
2020         [pbn_b0_bt_2_115200] = {
2021                 .flags          = FL_BASE0|FL_BASE_BARS,
2022                 .num_ports      = 2,
2023                 .base_baud      = 115200,
2024                 .uart_offset    = 8,
2025         },
2026         [pbn_b0_bt_4_115200] = {
2027                 .flags          = FL_BASE0|FL_BASE_BARS,
2028                 .num_ports      = 4,
2029                 .base_baud      = 115200,
2030                 .uart_offset    = 8,
2031         },
2032         [pbn_b0_bt_8_115200] = {
2033                 .flags          = FL_BASE0|FL_BASE_BARS,
2034                 .num_ports      = 8,
2035                 .base_baud      = 115200,
2036                 .uart_offset    = 8,
2037         },
2038
2039         [pbn_b0_bt_1_460800] = {
2040                 .flags          = FL_BASE0|FL_BASE_BARS,
2041                 .num_ports      = 1,
2042                 .base_baud      = 460800,
2043                 .uart_offset    = 8,
2044         },
2045         [pbn_b0_bt_2_460800] = {
2046                 .flags          = FL_BASE0|FL_BASE_BARS,
2047                 .num_ports      = 2,
2048                 .base_baud      = 460800,
2049                 .uart_offset    = 8,
2050         },
2051         [pbn_b0_bt_4_460800] = {
2052                 .flags          = FL_BASE0|FL_BASE_BARS,
2053                 .num_ports      = 4,
2054                 .base_baud      = 460800,
2055                 .uart_offset    = 8,
2056         },
2057
2058         [pbn_b0_bt_1_921600] = {
2059                 .flags          = FL_BASE0|FL_BASE_BARS,
2060                 .num_ports      = 1,
2061                 .base_baud      = 921600,
2062                 .uart_offset    = 8,
2063         },
2064         [pbn_b0_bt_2_921600] = {
2065                 .flags          = FL_BASE0|FL_BASE_BARS,
2066                 .num_ports      = 2,
2067                 .base_baud      = 921600,
2068                 .uart_offset    = 8,
2069         },
2070         [pbn_b0_bt_4_921600] = {
2071                 .flags          = FL_BASE0|FL_BASE_BARS,
2072                 .num_ports      = 4,
2073                 .base_baud      = 921600,
2074                 .uart_offset    = 8,
2075         },
2076         [pbn_b0_bt_8_921600] = {
2077                 .flags          = FL_BASE0|FL_BASE_BARS,
2078                 .num_ports      = 8,
2079                 .base_baud      = 921600,
2080                 .uart_offset    = 8,
2081         },
2082
2083         [pbn_b1_1_115200] = {
2084                 .flags          = FL_BASE1,
2085                 .num_ports      = 1,
2086                 .base_baud      = 115200,
2087                 .uart_offset    = 8,
2088         },
2089         [pbn_b1_2_115200] = {
2090                 .flags          = FL_BASE1,
2091                 .num_ports      = 2,
2092                 .base_baud      = 115200,
2093                 .uart_offset    = 8,
2094         },
2095         [pbn_b1_4_115200] = {
2096                 .flags          = FL_BASE1,
2097                 .num_ports      = 4,
2098                 .base_baud      = 115200,
2099                 .uart_offset    = 8,
2100         },
2101         [pbn_b1_8_115200] = {
2102                 .flags          = FL_BASE1,
2103                 .num_ports      = 8,
2104                 .base_baud      = 115200,
2105                 .uart_offset    = 8,
2106         },
2107         [pbn_b1_16_115200] = {
2108                 .flags          = FL_BASE1,
2109                 .num_ports      = 16,
2110                 .base_baud      = 115200,
2111                 .uart_offset    = 8,
2112         },
2113
2114         [pbn_b1_1_921600] = {
2115                 .flags          = FL_BASE1,
2116                 .num_ports      = 1,
2117                 .base_baud      = 921600,
2118                 .uart_offset    = 8,
2119         },
2120         [pbn_b1_2_921600] = {
2121                 .flags          = FL_BASE1,
2122                 .num_ports      = 2,
2123                 .base_baud      = 921600,
2124                 .uart_offset    = 8,
2125         },
2126         [pbn_b1_4_921600] = {
2127                 .flags          = FL_BASE1,
2128                 .num_ports      = 4,
2129                 .base_baud      = 921600,
2130                 .uart_offset    = 8,
2131         },
2132         [pbn_b1_8_921600] = {
2133                 .flags          = FL_BASE1,
2134                 .num_ports      = 8,
2135                 .base_baud      = 921600,
2136                 .uart_offset    = 8,
2137         },
2138         [pbn_b1_2_1250000] = {
2139                 .flags          = FL_BASE1,
2140                 .num_ports      = 2,
2141                 .base_baud      = 1250000,
2142                 .uart_offset    = 8,
2143         },
2144
2145         [pbn_b1_bt_1_115200] = {
2146                 .flags          = FL_BASE1|FL_BASE_BARS,
2147                 .num_ports      = 1,
2148                 .base_baud      = 115200,
2149                 .uart_offset    = 8,
2150         },
2151         [pbn_b1_bt_2_115200] = {
2152                 .flags          = FL_BASE1|FL_BASE_BARS,
2153                 .num_ports      = 2,
2154                 .base_baud      = 115200,
2155                 .uart_offset    = 8,
2156         },
2157         [pbn_b1_bt_4_115200] = {
2158                 .flags          = FL_BASE1|FL_BASE_BARS,
2159                 .num_ports      = 4,
2160                 .base_baud      = 115200,
2161                 .uart_offset    = 8,
2162         },
2163
2164         [pbn_b1_bt_2_921600] = {
2165                 .flags          = FL_BASE1|FL_BASE_BARS,
2166                 .num_ports      = 2,
2167                 .base_baud      = 921600,
2168                 .uart_offset    = 8,
2169         },
2170
2171         [pbn_b1_1_1382400] = {
2172                 .flags          = FL_BASE1,
2173                 .num_ports      = 1,
2174                 .base_baud      = 1382400,
2175                 .uart_offset    = 8,
2176         },
2177         [pbn_b1_2_1382400] = {
2178                 .flags          = FL_BASE1,
2179                 .num_ports      = 2,
2180                 .base_baud      = 1382400,
2181                 .uart_offset    = 8,
2182         },
2183         [pbn_b1_4_1382400] = {
2184                 .flags          = FL_BASE1,
2185                 .num_ports      = 4,
2186                 .base_baud      = 1382400,
2187                 .uart_offset    = 8,
2188         },
2189         [pbn_b1_8_1382400] = {
2190                 .flags          = FL_BASE1,
2191                 .num_ports      = 8,
2192                 .base_baud      = 1382400,
2193                 .uart_offset    = 8,
2194         },
2195
2196         [pbn_b2_1_115200] = {
2197                 .flags          = FL_BASE2,
2198                 .num_ports      = 1,
2199                 .base_baud      = 115200,
2200                 .uart_offset    = 8,
2201         },
2202         [pbn_b2_2_115200] = {
2203                 .flags          = FL_BASE2,
2204                 .num_ports      = 2,
2205                 .base_baud      = 115200,
2206                 .uart_offset    = 8,
2207         },
2208         [pbn_b2_4_115200] = {
2209                 .flags          = FL_BASE2,
2210                 .num_ports      = 4,
2211                 .base_baud      = 115200,
2212                 .uart_offset    = 8,
2213         },
2214         [pbn_b2_8_115200] = {
2215                 .flags          = FL_BASE2,
2216                 .num_ports      = 8,
2217                 .base_baud      = 115200,
2218                 .uart_offset    = 8,
2219         },
2220
2221         [pbn_b2_1_460800] = {
2222                 .flags          = FL_BASE2,
2223                 .num_ports      = 1,
2224                 .base_baud      = 460800,
2225                 .uart_offset    = 8,
2226         },
2227         [pbn_b2_4_460800] = {
2228                 .flags          = FL_BASE2,
2229                 .num_ports      = 4,
2230                 .base_baud      = 460800,
2231                 .uart_offset    = 8,
2232         },
2233         [pbn_b2_8_460800] = {
2234                 .flags          = FL_BASE2,
2235                 .num_ports      = 8,
2236                 .base_baud      = 460800,
2237                 .uart_offset    = 8,
2238         },
2239         [pbn_b2_16_460800] = {
2240                 .flags          = FL_BASE2,
2241                 .num_ports      = 16,
2242                 .base_baud      = 460800,
2243                 .uart_offset    = 8,
2244          },
2245
2246         [pbn_b2_1_921600] = {
2247                 .flags          = FL_BASE2,
2248                 .num_ports      = 1,
2249                 .base_baud      = 921600,
2250                 .uart_offset    = 8,
2251         },
2252         [pbn_b2_4_921600] = {
2253                 .flags          = FL_BASE2,
2254                 .num_ports      = 4,
2255                 .base_baud      = 921600,
2256                 .uart_offset    = 8,
2257         },
2258         [pbn_b2_8_921600] = {
2259                 .flags          = FL_BASE2,
2260                 .num_ports      = 8,
2261                 .base_baud      = 921600,
2262                 .uart_offset    = 8,
2263         },
2264
2265         [pbn_b2_8_1152000] = {
2266                 .flags          = FL_BASE2,
2267                 .num_ports      = 8,
2268                 .base_baud      = 1152000,
2269                 .uart_offset    = 8,
2270         },
2271
2272         [pbn_b2_bt_1_115200] = {
2273                 .flags          = FL_BASE2|FL_BASE_BARS,
2274                 .num_ports      = 1,
2275                 .base_baud      = 115200,
2276                 .uart_offset    = 8,
2277         },
2278         [pbn_b2_bt_2_115200] = {
2279                 .flags          = FL_BASE2|FL_BASE_BARS,
2280                 .num_ports      = 2,
2281                 .base_baud      = 115200,
2282                 .uart_offset    = 8,
2283         },
2284         [pbn_b2_bt_4_115200] = {
2285                 .flags          = FL_BASE2|FL_BASE_BARS,
2286                 .num_ports      = 4,
2287                 .base_baud      = 115200,
2288                 .uart_offset    = 8,
2289         },
2290
2291         [pbn_b2_bt_2_921600] = {
2292                 .flags          = FL_BASE2|FL_BASE_BARS,
2293                 .num_ports      = 2,
2294                 .base_baud      = 921600,
2295                 .uart_offset    = 8,
2296         },
2297         [pbn_b2_bt_4_921600] = {
2298                 .flags          = FL_BASE2|FL_BASE_BARS,
2299                 .num_ports      = 4,
2300                 .base_baud      = 921600,
2301                 .uart_offset    = 8,
2302         },
2303
2304         [pbn_b3_2_115200] = {
2305                 .flags          = FL_BASE3,
2306                 .num_ports      = 2,
2307                 .base_baud      = 115200,
2308                 .uart_offset    = 8,
2309         },
2310         [pbn_b3_4_115200] = {
2311                 .flags          = FL_BASE3,
2312                 .num_ports      = 4,
2313                 .base_baud      = 115200,
2314                 .uart_offset    = 8,
2315         },
2316         [pbn_b3_8_115200] = {
2317                 .flags          = FL_BASE3,
2318                 .num_ports      = 8,
2319                 .base_baud      = 115200,
2320                 .uart_offset    = 8,
2321         },
2322
2323         [pbn_b4_bt_2_921600] = {
2324                 .flags          = FL_BASE4,
2325                 .num_ports      = 2,
2326                 .base_baud      = 921600,
2327                 .uart_offset    = 8,
2328         },
2329         [pbn_b4_bt_4_921600] = {
2330                 .flags          = FL_BASE4,
2331                 .num_ports      = 4,
2332                 .base_baud      = 921600,
2333                 .uart_offset    = 8,
2334         },
2335         [pbn_b4_bt_8_921600] = {
2336                 .flags          = FL_BASE4,
2337                 .num_ports      = 8,
2338                 .base_baud      = 921600,
2339                 .uart_offset    = 8,
2340         },
2341
2342         /*
2343          * Entries following this are board-specific.
2344          */
2345
2346         /*
2347          * Panacom - IOMEM
2348          */
2349         [pbn_panacom] = {
2350                 .flags          = FL_BASE2,
2351                 .num_ports      = 2,
2352                 .base_baud      = 921600,
2353                 .uart_offset    = 0x400,
2354                 .reg_shift      = 7,
2355         },
2356         [pbn_panacom2] = {
2357                 .flags          = FL_BASE2|FL_BASE_BARS,
2358                 .num_ports      = 2,
2359                 .base_baud      = 921600,
2360                 .uart_offset    = 0x400,
2361                 .reg_shift      = 7,
2362         },
2363         [pbn_panacom4] = {
2364                 .flags          = FL_BASE2|FL_BASE_BARS,
2365                 .num_ports      = 4,
2366                 .base_baud      = 921600,
2367                 .uart_offset    = 0x400,
2368                 .reg_shift      = 7,
2369         },
2370
2371         [pbn_exsys_4055] = {
2372                 .flags          = FL_BASE2,
2373                 .num_ports      = 4,
2374                 .base_baud      = 115200,
2375                 .uart_offset    = 8,
2376         },
2377
2378         /* I think this entry is broken - the first_offset looks wrong --rmk */
2379         [pbn_plx_romulus] = {
2380                 .flags          = FL_BASE2,
2381                 .num_ports      = 4,
2382                 .base_baud      = 921600,
2383                 .uart_offset    = 8 << 2,
2384                 .reg_shift      = 2,
2385                 .first_offset   = 0x03,
2386         },
2387
2388         /*
2389          * This board uses the size of PCI Base region 0 to
2390          * signal now many ports are available
2391          */
2392         [pbn_oxsemi] = {
2393                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2394                 .num_ports      = 32,
2395                 .base_baud      = 115200,
2396                 .uart_offset    = 8,
2397         },
2398         [pbn_oxsemi_1_4000000] = {
2399                 .flags          = FL_BASE0,
2400                 .num_ports      = 1,
2401                 .base_baud      = 4000000,
2402                 .uart_offset    = 0x200,
2403                 .first_offset   = 0x1000,
2404         },
2405         [pbn_oxsemi_2_4000000] = {
2406                 .flags          = FL_BASE0,
2407                 .num_ports      = 2,
2408                 .base_baud      = 4000000,
2409                 .uart_offset    = 0x200,
2410                 .first_offset   = 0x1000,
2411         },
2412         [pbn_oxsemi_4_4000000] = {
2413                 .flags          = FL_BASE0,
2414                 .num_ports      = 4,
2415                 .base_baud      = 4000000,
2416                 .uart_offset    = 0x200,
2417                 .first_offset   = 0x1000,
2418         },
2419         [pbn_oxsemi_8_4000000] = {
2420                 .flags          = FL_BASE0,
2421                 .num_ports      = 8,
2422                 .base_baud      = 4000000,
2423                 .uart_offset    = 0x200,
2424                 .first_offset   = 0x1000,
2425         },
2426
2427
2428         /*
2429          * EKF addition for i960 Boards form EKF with serial port.
2430          * Max 256 ports.
2431          */
2432         [pbn_intel_i960] = {
2433                 .flags          = FL_BASE0,
2434                 .num_ports      = 32,
2435                 .base_baud      = 921600,
2436                 .uart_offset    = 8 << 2,
2437                 .reg_shift      = 2,
2438                 .first_offset   = 0x10000,
2439         },
2440         [pbn_sgi_ioc3] = {
2441                 .flags          = FL_BASE0|FL_NOIRQ,
2442                 .num_ports      = 1,
2443                 .base_baud      = 458333,
2444                 .uart_offset    = 8,
2445                 .reg_shift      = 0,
2446                 .first_offset   = 0x20178,
2447         },
2448
2449         /*
2450          * Computone - uses IOMEM.
2451          */
2452         [pbn_computone_4] = {
2453                 .flags          = FL_BASE0,
2454                 .num_ports      = 4,
2455                 .base_baud      = 921600,
2456                 .uart_offset    = 0x40,
2457                 .reg_shift      = 2,
2458                 .first_offset   = 0x200,
2459         },
2460         [pbn_computone_6] = {
2461                 .flags          = FL_BASE0,
2462                 .num_ports      = 6,
2463                 .base_baud      = 921600,
2464                 .uart_offset    = 0x40,
2465                 .reg_shift      = 2,
2466                 .first_offset   = 0x200,
2467         },
2468         [pbn_computone_8] = {
2469                 .flags          = FL_BASE0,
2470                 .num_ports      = 8,
2471                 .base_baud      = 921600,
2472                 .uart_offset    = 0x40,
2473                 .reg_shift      = 2,
2474                 .first_offset   = 0x200,
2475         },
2476         [pbn_sbsxrsio] = {
2477                 .flags          = FL_BASE0,
2478                 .num_ports      = 8,
2479                 .base_baud      = 460800,
2480                 .uart_offset    = 256,
2481                 .reg_shift      = 4,
2482         },
2483         /*
2484          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2485          *  Only basic 16550A support.
2486          *  XR17C15[24] are not tested, but they should work.
2487          */
2488         [pbn_exar_XR17C152] = {
2489                 .flags          = FL_BASE0,
2490                 .num_ports      = 2,
2491                 .base_baud      = 921600,
2492                 .uart_offset    = 0x200,
2493         },
2494         [pbn_exar_XR17C154] = {
2495                 .flags          = FL_BASE0,
2496                 .num_ports      = 4,
2497                 .base_baud      = 921600,
2498                 .uart_offset    = 0x200,
2499         },
2500         [pbn_exar_XR17C158] = {
2501                 .flags          = FL_BASE0,
2502                 .num_ports      = 8,
2503                 .base_baud      = 921600,
2504                 .uart_offset    = 0x200,
2505         },
2506         [pbn_exar_ibm_saturn] = {
2507                 .flags          = FL_BASE0,
2508                 .num_ports      = 1,
2509                 .base_baud      = 921600,
2510                 .uart_offset    = 0x200,
2511         },
2512
2513         /*
2514          * PA Semi PWRficient PA6T-1682M on-chip UART
2515          */
2516         [pbn_pasemi_1682M] = {
2517                 .flags          = FL_BASE0,
2518                 .num_ports      = 1,
2519                 .base_baud      = 8333333,
2520         },
2521         /*
2522          * National Instruments 843x
2523          */
2524         [pbn_ni8430_16] = {
2525                 .flags          = FL_BASE0,
2526                 .num_ports      = 16,
2527                 .base_baud      = 3686400,
2528                 .uart_offset    = 0x10,
2529                 .first_offset   = 0x800,
2530         },
2531         [pbn_ni8430_8] = {
2532                 .flags          = FL_BASE0,
2533                 .num_ports      = 8,
2534                 .base_baud      = 3686400,
2535                 .uart_offset    = 0x10,
2536                 .first_offset   = 0x800,
2537         },
2538         [pbn_ni8430_4] = {
2539                 .flags          = FL_BASE0,
2540                 .num_ports      = 4,
2541                 .base_baud      = 3686400,
2542                 .uart_offset    = 0x10,
2543                 .first_offset   = 0x800,
2544         },
2545         [pbn_ni8430_2] = {
2546                 .flags          = FL_BASE0,
2547                 .num_ports      = 2,
2548                 .base_baud      = 3686400,
2549                 .uart_offset    = 0x10,
2550                 .first_offset   = 0x800,
2551         },
2552         /*
2553          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2554          */
2555         [pbn_ADDIDATA_PCIe_1_3906250] = {
2556                 .flags          = FL_BASE0,
2557                 .num_ports      = 1,
2558                 .base_baud      = 3906250,
2559                 .uart_offset    = 0x200,
2560                 .first_offset   = 0x1000,
2561         },
2562         [pbn_ADDIDATA_PCIe_2_3906250] = {
2563                 .flags          = FL_BASE0,
2564                 .num_ports      = 2,
2565                 .base_baud      = 3906250,
2566                 .uart_offset    = 0x200,
2567                 .first_offset   = 0x1000,
2568         },
2569         [pbn_ADDIDATA_PCIe_4_3906250] = {
2570                 .flags          = FL_BASE0,
2571                 .num_ports      = 4,
2572                 .base_baud      = 3906250,
2573                 .uart_offset    = 0x200,
2574                 .first_offset   = 0x1000,
2575         },
2576         [pbn_ADDIDATA_PCIe_8_3906250] = {
2577                 .flags          = FL_BASE0,
2578                 .num_ports      = 8,
2579                 .base_baud      = 3906250,
2580                 .uart_offset    = 0x200,
2581                 .first_offset   = 0x1000,
2582         },
2583         [pbn_ce4100_1_115200] = {
2584                 .flags          = FL_BASE0,
2585                 .num_ports      = 1,
2586                 .base_baud      = 921600,
2587                 .reg_shift      = 2,
2588         },
2589         [pbn_omegapci] = {
2590                 .flags          = FL_BASE0,
2591                 .num_ports      = 8,
2592                 .base_baud      = 115200,
2593                 .uart_offset    = 0x200,
2594         },
2595         [pbn_NETMOS9900_2s_115200] = {
2596                 .flags          = FL_BASE0,
2597                 .num_ports      = 2,
2598                 .base_baud      = 115200,
2599         },
2600         [pbn_brcm_trumanage] = {
2601                 .flags          = FL_BASE0,
2602                 .num_ports      = 1,
2603                 .reg_shift      = 2,
2604                 .base_baud      = 115200,
2605         },
2606 };
2607
2608 static const struct pci_device_id softmodem_blacklist[] = {
2609         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2610         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2611         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2612 };
2613
2614 /*
2615  * Given a complete unknown PCI device, try to use some heuristics to
2616  * guess what the configuration might be, based on the pitiful PCI
2617  * serial specs.  Returns 0 on success, 1 on failure.
2618  */
2619 static int __devinit
2620 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2621 {
2622         const struct pci_device_id *blacklist;
2623         int num_iomem, num_port, first_port = -1, i;
2624
2625         /*
2626          * If it is not a communications device or the programming
2627          * interface is greater than 6, give up.
2628          *
2629          * (Should we try to make guesses for multiport serial devices
2630          * later?)
2631          */
2632         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2633              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2634             (dev->class & 0xff) > 6)
2635                 return -ENODEV;
2636
2637         /*
2638          * Do not access blacklisted devices that are known not to
2639          * feature serial ports.
2640          */
2641         for (blacklist = softmodem_blacklist;
2642              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2643              blacklist++) {
2644                 if (dev->vendor == blacklist->vendor &&
2645                     dev->device == blacklist->device)
2646                         return -ENODEV;
2647         }
2648
2649         num_iomem = num_port = 0;
2650         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2651                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2652                         num_port++;
2653                         if (first_port == -1)
2654                                 first_port = i;
2655                 }
2656                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2657                         num_iomem++;
2658         }
2659
2660         /*
2661          * If there is 1 or 0 iomem regions, and exactly one port,
2662          * use it.  We guess the number of ports based on the IO
2663          * region size.
2664          */
2665         if (num_iomem <= 1 && num_port == 1) {
2666                 board->flags = first_port;
2667                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2668                 return 0;
2669         }
2670
2671         /*
2672          * Now guess if we've got a board which indexes by BARs.
2673          * Each IO BAR should be 8 bytes, and they should follow
2674          * consecutively.
2675          */
2676         first_port = -1;
2677         num_port = 0;
2678         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2679                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2680                     pci_resource_len(dev, i) == 8 &&
2681                     (first_port == -1 || (first_port + num_port) == i)) {
2682                         num_port++;
2683                         if (first_port == -1)
2684                                 first_port = i;
2685                 }
2686         }
2687
2688         if (num_port > 1) {
2689                 board->flags = first_port | FL_BASE_BARS;
2690                 board->num_ports = num_port;
2691                 return 0;
2692         }
2693
2694         return -ENODEV;
2695 }
2696
2697 static inline int
2698 serial_pci_matches(const struct pciserial_board *board,
2699                    const struct pciserial_board *guessed)
2700 {
2701         return
2702             board->num_ports == guessed->num_ports &&
2703             board->base_baud == guessed->base_baud &&
2704             board->uart_offset == guessed->uart_offset &&
2705             board->reg_shift == guessed->reg_shift &&
2706             board->first_offset == guessed->first_offset;
2707 }
2708
2709 struct serial_private *
2710 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2711 {
2712         struct uart_port serial_port;
2713         struct serial_private *priv;
2714         struct pci_serial_quirk *quirk;
2715         int rc, nr_ports, i;
2716
2717         nr_ports = board->num_ports;
2718
2719         /*
2720          * Find an init and setup quirks.
2721          */
2722         quirk = find_quirk(dev);
2723
2724         /*
2725          * Run the new-style initialization function.
2726          * The initialization function returns:
2727          *  <0  - error
2728          *   0  - use board->num_ports
2729          *  >0  - number of ports
2730          */
2731         if (quirk->init) {
2732                 rc = quirk->init(dev);
2733                 if (rc < 0) {
2734                         priv = ERR_PTR(rc);
2735                         goto err_out;
2736                 }
2737                 if (rc)
2738                         nr_ports = rc;
2739         }
2740
2741         priv = kzalloc(sizeof(struct serial_private) +
2742                        sizeof(unsigned int) * nr_ports,
2743                        GFP_KERNEL);
2744         if (!priv) {
2745                 priv = ERR_PTR(-ENOMEM);
2746                 goto err_deinit;
2747         }
2748
2749         priv->dev = dev;
2750         priv->quirk = quirk;
2751
2752         memset(&serial_port, 0, sizeof(struct uart_port));
2753         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2754         serial_port.uartclk = board->base_baud * 16;
2755         serial_port.irq = get_pci_irq(dev, board);
2756         serial_port.dev = &dev->dev;
2757
2758         for (i = 0; i < nr_ports; i++) {
2759                 if (quirk->setup(priv, board, &serial_port, i))
2760                         break;
2761
2762 #ifdef SERIAL_DEBUG_PCI
2763                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2764                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2765 #endif
2766
2767                 priv->line[i] = serial8250_register_port(&serial_port);
2768                 if (priv->line[i] < 0) {
2769                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2770                         break;
2771                 }
2772         }
2773         priv->nr = i;
2774         return priv;
2775
2776 err_deinit:
2777         if (quirk->exit)
2778                 quirk->exit(dev);
2779 err_out:
2780         return priv;
2781 }
2782 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2783
2784 void pciserial_remove_ports(struct serial_private *priv)
2785 {
2786         struct pci_serial_quirk *quirk;
2787         int i;
2788
2789         for (i = 0; i < priv->nr; i++)
2790                 serial8250_unregister_port(priv->line[i]);
2791
2792         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2793                 if (priv->remapped_bar[i])
2794                         iounmap(priv->remapped_bar[i]);
2795                 priv->remapped_bar[i] = NULL;
2796         }
2797
2798         /*
2799          * Find the exit quirks.
2800          */
2801         quirk = find_quirk(priv->dev);
2802         if (quirk->exit)
2803                 quirk->exit(priv->dev);
2804
2805         kfree(priv);
2806 }
2807 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2808
2809 void pciserial_suspend_ports(struct serial_private *priv)
2810 {
2811         int i;
2812
2813         for (i = 0; i < priv->nr; i++)
2814                 if (priv->line[i] >= 0)
2815                         serial8250_suspend_port(priv->line[i]);
2816 }
2817 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2818
2819 void pciserial_resume_ports(struct serial_private *priv)
2820 {
2821         int i;
2822
2823         /*
2824          * Ensure that the board is correctly configured.
2825          */
2826         if (priv->quirk->init)
2827                 priv->quirk->init(priv->dev);
2828
2829         for (i = 0; i < priv->nr; i++)
2830                 if (priv->line[i] >= 0)
2831                         serial8250_resume_port(priv->line[i]);
2832 }
2833 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2834
2835 /*
2836  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2837  * to the arrangement of serial ports on a PCI card.
2838  */
2839 static int __devinit
2840 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2841 {
2842         struct pci_serial_quirk *quirk;
2843         struct serial_private *priv;
2844         const struct pciserial_board *board;
2845         struct pciserial_board tmp;
2846         int rc;
2847
2848         quirk = find_quirk(dev);
2849         if (quirk->probe) {
2850                 rc = quirk->probe(dev);
2851                 if (rc)
2852                         return rc;
2853         }
2854
2855         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2856                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2857                         ent->driver_data);
2858                 return -EINVAL;
2859         }
2860
2861         board = &pci_boards[ent->driver_data];
2862
2863         rc = pci_enable_device(dev);
2864         pci_save_state(dev);
2865         if (rc)
2866                 return rc;
2867
2868         if (ent->driver_data == pbn_default) {
2869                 /*
2870                  * Use a copy of the pci_board entry for this;
2871                  * avoid changing entries in the table.
2872                  */
2873                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2874                 board = &tmp;
2875
2876                 /*
2877                  * We matched one of our class entries.  Try to
2878                  * determine the parameters of this board.
2879                  */
2880                 rc = serial_pci_guess_board(dev, &tmp);
2881                 if (rc)
2882                         goto disable;
2883         } else {
2884                 /*
2885                  * We matched an explicit entry.  If we are able to
2886                  * detect this boards settings with our heuristic,
2887                  * then we no longer need this entry.
2888                  */
2889                 memcpy(&tmp, &pci_boards[pbn_default],
2890                        sizeof(struct pciserial_board));
2891                 rc = serial_pci_guess_board(dev, &tmp);
2892                 if (rc == 0 && serial_pci_matches(board, &tmp))
2893                         moan_device("Redundant entry in serial pci_table.",
2894                                     dev);
2895         }
2896
2897         priv = pciserial_init_ports(dev, board);
2898         if (!IS_ERR(priv)) {
2899                 pci_set_drvdata(dev, priv);
2900                 return 0;
2901         }
2902
2903         rc = PTR_ERR(priv);
2904
2905  disable:
2906         pci_disable_device(dev);
2907         return rc;
2908 }
2909
2910 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2911 {
2912         struct serial_private *priv = pci_get_drvdata(dev);
2913
2914         pci_set_drvdata(dev, NULL);
2915
2916         pciserial_remove_ports(priv);
2917
2918         pci_disable_device(dev);
2919 }
2920
2921 #ifdef CONFIG_PM
2922 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2923 {
2924         struct serial_private *priv = pci_get_drvdata(dev);
2925
2926         if (priv)
2927                 pciserial_suspend_ports(priv);
2928
2929         pci_save_state(dev);
2930         pci_set_power_state(dev, pci_choose_state(dev, state));
2931         return 0;
2932 }
2933
2934 static int pciserial_resume_one(struct pci_dev *dev)
2935 {
2936         int err;
2937         struct serial_private *priv = pci_get_drvdata(dev);
2938
2939         pci_set_power_state(dev, PCI_D0);
2940         pci_restore_state(dev);
2941
2942         if (priv) {
2943                 /*
2944                  * The device may have been disabled.  Re-enable it.
2945                  */
2946                 err = pci_enable_device(dev);
2947                 /* FIXME: We cannot simply error out here */
2948                 if (err)
2949                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2950                 pciserial_resume_ports(priv);
2951         }
2952         return 0;
2953 }
2954 #endif
2955
2956 static struct pci_device_id serial_pci_tbl[] = {
2957         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2958         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2959                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2960                 pbn_b2_8_921600 },
2961         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2962                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2963                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2964                 pbn_b1_8_1382400 },
2965         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2966                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2967                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2968                 pbn_b1_4_1382400 },
2969         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2970                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2971                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2972                 pbn_b1_2_1382400 },
2973         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2974                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2975                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2976                 pbn_b1_8_1382400 },
2977         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2978                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2979                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2980                 pbn_b1_4_1382400 },
2981         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2982                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2983                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2984                 pbn_b1_2_1382400 },
2985         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2986                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2987                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2988                 pbn_b1_8_921600 },
2989         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2990                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2991                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2992                 pbn_b1_8_921600 },
2993         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2994                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2995                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2996                 pbn_b1_4_921600 },
2997         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2998                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2999                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3000                 pbn_b1_4_921600 },
3001         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3002                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3003                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3004                 pbn_b1_2_921600 },
3005         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3006                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3007                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3008                 pbn_b1_8_921600 },
3009         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3010                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3011                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3012                 pbn_b1_8_921600 },
3013         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3014                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3015                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3016                 pbn_b1_4_921600 },
3017         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3018                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3019                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3020                 pbn_b1_2_1250000 },
3021         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3022                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3023                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3024                 pbn_b0_2_1843200 },
3025         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3026                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3027                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3028                 pbn_b0_4_1843200 },
3029         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3030                 PCI_VENDOR_ID_AFAVLAB,
3031                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3032                 pbn_b0_4_1152000 },
3033         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3034                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3035                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3036                 pbn_b0_2_1843200_200 },
3037         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3038                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3039                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3040                 pbn_b0_4_1843200_200 },
3041         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3042                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3043                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3044                 pbn_b0_8_1843200_200 },
3045         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3046                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3047                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3048                 pbn_b0_2_1843200_200 },
3049         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3050                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3051                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3052                 pbn_b0_4_1843200_200 },
3053         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3054                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3055                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3056                 pbn_b0_8_1843200_200 },
3057         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3058                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3059                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3060                 pbn_b0_2_1843200_200 },
3061         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3062                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3063                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3064                 pbn_b0_4_1843200_200 },
3065         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3066                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3067                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3068                 pbn_b0_8_1843200_200 },
3069         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3070                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3071                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3072                 pbn_b0_2_1843200_200 },
3073         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3074                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3075                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3076                 pbn_b0_4_1843200_200 },
3077         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3078                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3079                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3080                 pbn_b0_8_1843200_200 },
3081         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3082                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3083                 0, 0, pbn_exar_ibm_saturn },
3084
3085         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087                 pbn_b2_bt_1_115200 },
3088         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3090                 pbn_b2_bt_2_115200 },
3091         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3092                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3093                 pbn_b2_bt_4_115200 },
3094         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3095                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3096                 pbn_b2_bt_2_115200 },
3097         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3099                 pbn_b2_bt_4_115200 },
3100         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3101                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3102                 pbn_b2_8_115200 },
3103         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3104                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3105                 pbn_b2_8_460800 },
3106         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3107                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3108                 pbn_b2_8_115200 },
3109
3110         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3111                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3112                 pbn_b2_bt_2_115200 },
3113         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3114                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115                 pbn_b2_bt_2_921600 },
3116         /*
3117          * VScom SPCOM800, from sl@s.pl
3118          */
3119         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3121                 pbn_b2_8_921600 },
3122         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3123                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124                 pbn_b2_4_921600 },
3125         /* Unknown card - subdevice 0x1584 */
3126         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3127                 PCI_VENDOR_ID_PLX,
3128                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3129                 pbn_b2_4_115200 },
3130         /* Unknown card - subdevice 0x1588 */
3131         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3132                 PCI_VENDOR_ID_PLX,
3133                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3134                 pbn_b2_8_115200 },
3135         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3136                 PCI_SUBVENDOR_ID_KEYSPAN,
3137                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3138                 pbn_panacom },
3139         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3141                 pbn_panacom4 },
3142         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3144                 pbn_panacom2 },
3145         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3146                 PCI_VENDOR_ID_ESDGMBH,
3147                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3148                 pbn_b2_4_115200 },
3149         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3150                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3151                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3152                 pbn_b2_4_460800 },
3153         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3154                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3155                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3156                 pbn_b2_8_460800 },
3157         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3158                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3159                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3160                 pbn_b2_16_460800 },
3161         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3162                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3163                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3164                 pbn_b2_16_460800 },
3165         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3166                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3167                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3168                 pbn_b2_4_460800 },
3169         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3170                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3171                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3172                 pbn_b2_8_460800 },
3173         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3174                 PCI_SUBVENDOR_ID_EXSYS,
3175                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3176                 pbn_exsys_4055 },
3177         /*
3178          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3179          * (Exoray@isys.ca)
3180          */
3181         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3182                 0x10b5, 0x106a, 0, 0,
3183                 pbn_plx_romulus },
3184         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3185                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3186                 pbn_b1_4_115200 },
3187         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3188                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3189                 pbn_b1_2_115200 },
3190         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3191                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3192                 pbn_b1_8_115200 },
3193         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3194                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3195                 pbn_b1_8_115200 },
3196         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3197                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3198                 0, 0,
3199                 pbn_b0_4_921600 },
3200         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3201                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3202                 0, 0,
3203                 pbn_b0_4_1152000 },
3204         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206                 pbn_b0_bt_2_921600 },
3207
3208                 /*
3209                  * The below card is a little controversial since it is the
3210                  * subject of a PCI vendor/device ID clash.  (See
3211                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3212                  * For now just used the hex ID 0x950a.
3213                  */
3214         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3215                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3216                 0, 0, pbn_b0_2_115200 },
3217         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3218                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3219                 0, 0, pbn_b0_2_115200 },
3220         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3222                 pbn_b0_2_1130000 },
3223         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3224                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3225                 pbn_b0_1_921600 },
3226         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3227                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228                 pbn_b0_4_115200 },
3229         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3230                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3231                 pbn_b0_bt_2_921600 },
3232         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3233                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3234                 pbn_b2_8_1152000 },
3235
3236         /*
3237          * Oxford Semiconductor Inc. Tornado PCI express device range.
3238          */
3239         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3240                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241                 pbn_b0_1_4000000 },
3242         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244                 pbn_b0_1_4000000 },
3245         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3246                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3247                 pbn_oxsemi_1_4000000 },
3248         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3249                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250                 pbn_oxsemi_1_4000000 },
3251         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3252                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253                 pbn_b0_1_4000000 },
3254         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3255                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256                 pbn_b0_1_4000000 },
3257         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3258                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259                 pbn_oxsemi_1_4000000 },
3260         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262                 pbn_oxsemi_1_4000000 },
3263         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3264                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265                 pbn_b0_1_4000000 },
3266         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268                 pbn_b0_1_4000000 },
3269         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3270                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271                 pbn_b0_1_4000000 },
3272         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3273                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274                 pbn_b0_1_4000000 },
3275         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3276                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3277                 pbn_oxsemi_2_4000000 },
3278         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3279                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3280                 pbn_oxsemi_2_4000000 },
3281         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3282                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3283                 pbn_oxsemi_4_4000000 },
3284         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3285                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3286                 pbn_oxsemi_4_4000000 },
3287         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3288                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3289                 pbn_oxsemi_8_4000000 },
3290         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3292                 pbn_oxsemi_8_4000000 },
3293         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3294                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3295                 pbn_oxsemi_1_4000000 },
3296         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3297                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298                 pbn_oxsemi_1_4000000 },
3299         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3300                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301                 pbn_oxsemi_1_4000000 },
3302         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3303                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304                 pbn_oxsemi_1_4000000 },
3305         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307                 pbn_oxsemi_1_4000000 },
3308         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3309                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3310                 pbn_oxsemi_1_4000000 },
3311         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3312                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3313                 pbn_oxsemi_1_4000000 },
3314         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3315                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3316                 pbn_oxsemi_1_4000000 },
3317         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3319                 pbn_oxsemi_1_4000000 },
3320         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3322                 pbn_oxsemi_1_4000000 },
3323         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3325                 pbn_oxsemi_1_4000000 },
3326         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328                 pbn_oxsemi_1_4000000 },
3329         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3331                 pbn_oxsemi_1_4000000 },
3332         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334                 pbn_oxsemi_1_4000000 },
3335         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3337                 pbn_oxsemi_1_4000000 },
3338         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3340                 pbn_oxsemi_1_4000000 },
3341         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3342                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3343                 pbn_oxsemi_1_4000000 },
3344         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3346                 pbn_oxsemi_1_4000000 },
3347         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3348                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3349                 pbn_oxsemi_1_4000000 },
3350         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3351                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3352                 pbn_oxsemi_1_4000000 },
3353         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3354                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3355                 pbn_oxsemi_1_4000000 },
3356         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3357                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3358                 pbn_oxsemi_1_4000000 },
3359         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3361                 pbn_oxsemi_1_4000000 },
3362         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3364                 pbn_oxsemi_1_4000000 },
3365         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3366                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3367                 pbn_oxsemi_1_4000000 },
3368         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3369                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370                 pbn_oxsemi_1_4000000 },
3371         /*
3372          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3373          */
3374         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3375                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3376                 pbn_oxsemi_1_4000000 },
3377         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3378                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3379                 pbn_oxsemi_2_4000000 },
3380         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3381                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3382                 pbn_oxsemi_4_4000000 },
3383         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3384                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3385                 pbn_oxsemi_8_4000000 },
3386
3387         /*
3388          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3389          */
3390         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3391                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3392                 pbn_oxsemi_2_4000000 },
3393
3394         /*
3395          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3396          * from skokodyn@yahoo.com
3397          */
3398         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3399                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3400                 pbn_sbsxrsio },
3401         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3402                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3403                 pbn_sbsxrsio },
3404         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3405                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3406                 pbn_sbsxrsio },
3407         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3408                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3409                 pbn_sbsxrsio },
3410
3411         /*
3412          * Digitan DS560-558, from jimd@esoft.com
3413          */
3414         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3415                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416                 pbn_b1_1_115200 },
3417
3418         /*
3419          * Titan Electronic cards
3420          *  The 400L and 800L have a custom setup quirk.
3421          */
3422         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3423                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3424                 pbn_b0_1_921600 },
3425         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3427                 pbn_b0_2_921600 },
3428         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3429                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3430                 pbn_b0_4_921600 },
3431         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3432                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3433                 pbn_b0_4_921600 },
3434         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436                 pbn_b1_1_921600 },
3437         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3439                 pbn_b1_bt_2_921600 },
3440         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3441                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442                 pbn_b0_bt_4_921600 },
3443         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445                 pbn_b0_bt_8_921600 },
3446         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448                 pbn_b4_bt_2_921600 },
3449         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3451                 pbn_b4_bt_4_921600 },
3452         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3453                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454                 pbn_b4_bt_8_921600 },
3455         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3457                 pbn_b0_4_921600 },
3458         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460                 pbn_b0_4_921600 },
3461         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3463                 pbn_b0_4_921600 },
3464         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3465                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3466                 pbn_oxsemi_1_4000000 },
3467         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3468                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3469                 pbn_oxsemi_2_4000000 },
3470         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472                 pbn_oxsemi_4_4000000 },
3473         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3474                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475                 pbn_oxsemi_8_4000000 },
3476         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3477                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478                 pbn_oxsemi_2_4000000 },
3479         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481                 pbn_oxsemi_2_4000000 },
3482         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
3483                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3484                 pbn_b0_bt_2_921600 },
3485         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487                 pbn_b0_4_921600 },
3488         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490                 pbn_b0_4_921600 },
3491         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3492                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493                 pbn_b0_4_921600 },
3494         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3495                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3496                 pbn_b0_4_921600 },
3497
3498         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3499                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3500                 pbn_b2_1_460800 },
3501         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3502                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3503                 pbn_b2_1_460800 },
3504         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3505                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3506                 pbn_b2_1_460800 },
3507         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3508                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3509                 pbn_b2_bt_2_921600 },
3510         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3511                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3512                 pbn_b2_bt_2_921600 },
3513         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3514                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3515                 pbn_b2_bt_2_921600 },
3516         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3517                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3518                 pbn_b2_bt_4_921600 },
3519         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3520                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3521                 pbn_b2_bt_4_921600 },
3522         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3523                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3524                 pbn_b2_bt_4_921600 },
3525         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3526                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3527                 pbn_b0_1_921600 },
3528         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3529                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3530                 pbn_b0_1_921600 },
3531         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3532                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3533                 pbn_b0_1_921600 },
3534         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3535                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3536                 pbn_b0_bt_2_921600 },
3537         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3538                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3539                 pbn_b0_bt_2_921600 },
3540         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3541                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3542                 pbn_b0_bt_2_921600 },
3543         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3544                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3545                 pbn_b0_bt_4_921600 },
3546         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3547                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548                 pbn_b0_bt_4_921600 },
3549         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3550                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551                 pbn_b0_bt_4_921600 },
3552         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3553                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554                 pbn_b0_bt_8_921600 },
3555         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3556                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557                 pbn_b0_bt_8_921600 },
3558         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3559                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560                 pbn_b0_bt_8_921600 },
3561
3562         /*
3563          * Computone devices submitted by Doug McNash dmcnash@computone.com
3564          */
3565         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3566                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3567                 0, 0, pbn_computone_4 },
3568         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3569                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3570                 0, 0, pbn_computone_8 },
3571         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3572                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3573                 0, 0, pbn_computone_6 },
3574
3575         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577                 pbn_oxsemi },
3578         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3579                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3580                 pbn_b0_bt_1_921600 },
3581
3582         /*
3583          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3584          */
3585         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3586                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3587                 pbn_b0_bt_8_115200 },
3588         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3589                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3590                 pbn_b0_bt_8_115200 },
3591
3592         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3593                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3594                 pbn_b0_bt_2_115200 },
3595         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3596                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3597                 pbn_b0_bt_2_115200 },
3598         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3599                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3600                 pbn_b0_bt_2_115200 },
3601         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3602                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3603                 pbn_b0_bt_2_115200 },
3604         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3605                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3606                 pbn_b0_bt_2_115200 },
3607         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3608                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3609                 pbn_b0_bt_4_460800 },
3610         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3611                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3612                 pbn_b0_bt_4_460800 },
3613         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3614                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3615                 pbn_b0_bt_2_460800 },
3616         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3617                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3618                 pbn_b0_bt_2_460800 },
3619         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3620                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3621                 pbn_b0_bt_2_460800 },
3622         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3623                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3624                 pbn_b0_bt_1_115200 },
3625         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3626                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3627                 pbn_b0_bt_1_460800 },
3628
3629         /*
3630          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3631          * Cards are identified by their subsystem vendor IDs, which
3632          * (in hex) match the model number.
3633          *
3634          * Note that JC140x are RS422/485 cards which require ox950
3635          * ACR = 0x10, and as such are not currently fully supported.
3636          */
3637         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3638                 0x1204, 0x0004, 0, 0,
3639                 pbn_b0_4_921600 },
3640         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3641                 0x1208, 0x0004, 0, 0,
3642                 pbn_b0_4_921600 },
3643 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3644                 0x1402, 0x0002, 0, 0,
3645                 pbn_b0_2_921600 }, */
3646 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3647                 0x1404, 0x0004, 0, 0,
3648                 pbn_b0_4_921600 }, */
3649         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3650                 0x1208, 0x0004, 0, 0,
3651                 pbn_b0_4_921600 },
3652
3653         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3654                 0x1204, 0x0004, 0, 0,
3655                 pbn_b0_4_921600 },
3656         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3657                 0x1208, 0x0004, 0, 0,
3658                 pbn_b0_4_921600 },
3659         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3660                 0x1208, 0x0004, 0, 0,
3661                 pbn_b0_4_921600 },
3662         /*
3663          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3664          */
3665         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3666                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3667                 pbn_b1_1_1382400 },
3668
3669         /*
3670          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3671          */
3672         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3673                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3674                 pbn_b1_1_1382400 },
3675
3676         /*
3677          * RAStel 2 port modem, gerg@moreton.com.au
3678          */
3679         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3680                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3681                 pbn_b2_bt_2_115200 },
3682
3683         /*
3684          * EKF addition for i960 Boards form EKF with serial port
3685          */
3686         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3687                 0xE4BF, PCI_ANY_ID, 0, 0,
3688                 pbn_intel_i960 },
3689
3690         /*
3691          * Xircom Cardbus/Ethernet combos
3692          */
3693         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3695                 pbn_b0_1_115200 },
3696         /*
3697          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3698          */
3699         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3701                 pbn_b0_1_115200 },
3702
3703         /*
3704          * Untested PCI modems, sent in from various folks...
3705          */
3706
3707         /*
3708          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3709          */
3710         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3711                 0x1048, 0x1500, 0, 0,
3712                 pbn_b1_1_115200 },
3713
3714         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3715                 0xFF00, 0, 0, 0,
3716                 pbn_sgi_ioc3 },
3717
3718         /*
3719          * HP Diva card
3720          */
3721         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3722                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3723                 pbn_b1_1_115200 },
3724         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3725                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3726                 pbn_b0_5_115200 },
3727         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3729                 pbn_b2_1_115200 },
3730
3731         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3732                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3733                 pbn_b3_2_115200 },
3734         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3735                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3736                 pbn_b3_4_115200 },
3737         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3738                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3739                 pbn_b3_8_115200 },
3740
3741         /*
3742          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3743          */
3744         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3745                 PCI_ANY_ID, PCI_ANY_ID,
3746                 0,
3747                 0, pbn_exar_XR17C152 },
3748         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3749                 PCI_ANY_ID, PCI_ANY_ID,
3750                 0,
3751                 0, pbn_exar_XR17C154 },
3752         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3753                 PCI_ANY_ID, PCI_ANY_ID,
3754                 0,
3755                 0, pbn_exar_XR17C158 },
3756
3757         /*
3758          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3759          */
3760         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3761                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3762                 pbn_b0_1_115200 },
3763         /*
3764          * ITE
3765          */
3766         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3767                 PCI_ANY_ID, PCI_ANY_ID,
3768                 0, 0,
3769                 pbn_b1_bt_1_115200 },
3770
3771         /*
3772          * IntaShield IS-200
3773          */
3774         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3775                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3776                 pbn_b2_2_115200 },
3777         /*
3778          * IntaShield IS-400
3779          */
3780         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3781                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3782                 pbn_b2_4_115200 },
3783         /*
3784          * Perle PCI-RAS cards
3785          */
3786         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3787                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3788                 0, 0, pbn_b2_4_921600 },
3789         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3790                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3791                 0, 0, pbn_b2_8_921600 },
3792
3793         /*
3794          * Mainpine series cards: Fairly standard layout but fools
3795          * parts of the autodetect in some cases and uses otherwise
3796          * unmatched communications subclasses in the PCI Express case
3797          */
3798
3799         {       /* RockForceDUO */
3800                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3801                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3802                 0, 0, pbn_b0_2_115200 },
3803         {       /* RockForceQUATRO */
3804                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3805                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3806                 0, 0, pbn_b0_4_115200 },
3807         {       /* RockForceDUO+ */
3808                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3809                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3810                 0, 0, pbn_b0_2_115200 },
3811         {       /* RockForceQUATRO+ */
3812                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3813                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3814                 0, 0, pbn_b0_4_115200 },
3815         {       /* RockForce+ */
3816                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3817                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3818                 0, 0, pbn_b0_2_115200 },
3819         {       /* RockForce+ */
3820                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3821                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3822                 0, 0, pbn_b0_4_115200 },
3823         {       /* RockForceOCTO+ */
3824                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3825                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3826                 0, 0, pbn_b0_8_115200 },
3827         {       /* RockForceDUO+ */
3828                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3829                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3830                 0, 0, pbn_b0_2_115200 },
3831         {       /* RockForceQUARTRO+ */
3832                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3833                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3834                 0, 0, pbn_b0_4_115200 },
3835         {       /* RockForceOCTO+ */
3836                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3837                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3838                 0, 0, pbn_b0_8_115200 },
3839         {       /* RockForceD1 */
3840                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3841                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3842                 0, 0, pbn_b0_1_115200 },
3843         {       /* RockForceF1 */
3844                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3845                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3846                 0, 0, pbn_b0_1_115200 },
3847         {       /* RockForceD2 */
3848                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3849                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3850                 0, 0, pbn_b0_2_115200 },
3851         {       /* RockForceF2 */
3852                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3853                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3854                 0, 0, pbn_b0_2_115200 },
3855         {       /* RockForceD4 */
3856                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3857                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3858                 0, 0, pbn_b0_4_115200 },
3859         {       /* RockForceF4 */
3860                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3861                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3862                 0, 0, pbn_b0_4_115200 },
3863         {       /* RockForceD8 */
3864                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3865                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3866                 0, 0, pbn_b0_8_115200 },
3867         {       /* RockForceF8 */
3868                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3869                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3870                 0, 0, pbn_b0_8_115200 },
3871         {       /* IQ Express D1 */
3872                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3873                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3874                 0, 0, pbn_b0_1_115200 },
3875         {       /* IQ Express F1 */
3876                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3877                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3878                 0, 0, pbn_b0_1_115200 },
3879         {       /* IQ Express D2 */
3880                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3881                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3882                 0, 0, pbn_b0_2_115200 },
3883         {       /* IQ Express F2 */
3884                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3885                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3886                 0, 0, pbn_b0_2_115200 },
3887         {       /* IQ Express D4 */
3888                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3889                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3890                 0, 0, pbn_b0_4_115200 },
3891         {       /* IQ Express F4 */
3892                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3893                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3894                 0, 0, pbn_b0_4_115200 },
3895         {       /* IQ Express D8 */
3896                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3897                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3898                 0, 0, pbn_b0_8_115200 },
3899         {       /* IQ Express F8 */
3900                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3901                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3902                 0, 0, pbn_b0_8_115200 },
3903
3904
3905         /*
3906          * PA Semi PA6T-1682M on-chip UART
3907          */
3908         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3909                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3910                 pbn_pasemi_1682M },
3911
3912         /*
3913          * National Instruments
3914          */
3915         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3916                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3917                 pbn_b1_16_115200 },
3918         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3919                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3920                 pbn_b1_8_115200 },
3921         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3922                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3923                 pbn_b1_bt_4_115200 },
3924         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3925                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3926                 pbn_b1_bt_2_115200 },
3927         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3928                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3929                 pbn_b1_bt_4_115200 },
3930         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3931                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3932                 pbn_b1_bt_2_115200 },
3933         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3934                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935                 pbn_b1_16_115200 },
3936         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3938                 pbn_b1_8_115200 },
3939         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3940                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3941                 pbn_b1_bt_4_115200 },
3942         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944                 pbn_b1_bt_2_115200 },
3945         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3947                 pbn_b1_bt_4_115200 },
3948         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3949                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950                 pbn_b1_bt_2_115200 },
3951         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953                 pbn_ni8430_2 },
3954         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3955                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956                 pbn_ni8430_2 },
3957         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3959                 pbn_ni8430_4 },
3960         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3961                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962                 pbn_ni8430_4 },
3963         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3964                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965                 pbn_ni8430_8 },
3966         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3967                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968                 pbn_ni8430_8 },
3969         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971                 pbn_ni8430_16 },
3972         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3973                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974                 pbn_ni8430_16 },
3975         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977                 pbn_ni8430_2 },
3978         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3979                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980                 pbn_ni8430_2 },
3981         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3982                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983                 pbn_ni8430_4 },
3984         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986                 pbn_ni8430_4 },
3987
3988         /*
3989         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3990         */
3991         {       PCI_VENDOR_ID_ADDIDATA,
3992                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3993                 PCI_ANY_ID,
3994                 PCI_ANY_ID,
3995                 0,
3996                 0,
3997                 pbn_b0_4_115200 },
3998
3999         {       PCI_VENDOR_ID_ADDIDATA,
4000                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4001                 PCI_ANY_ID,
4002                 PCI_ANY_ID,
4003                 0,
4004                 0,
4005                 pbn_b0_2_115200 },
4006
4007         {       PCI_VENDOR_ID_ADDIDATA,
4008                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4009                 PCI_ANY_ID,
4010                 PCI_ANY_ID,
4011                 0,
4012                 0,
4013                 pbn_b0_1_115200 },
4014
4015         {       PCI_VENDOR_ID_ADDIDATA_OLD,
4016                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4017                 PCI_ANY_ID,
4018                 PCI_ANY_ID,
4019                 0,
4020                 0,
4021                 pbn_b1_8_115200 },
4022
4023         {       PCI_VENDOR_ID_ADDIDATA,
4024                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4025                 PCI_ANY_ID,
4026                 PCI_ANY_ID,
4027                 0,
4028                 0,
4029                 pbn_b0_4_115200 },
4030
4031         {       PCI_VENDOR_ID_ADDIDATA,
4032                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4033                 PCI_ANY_ID,
4034                 PCI_ANY_ID,
4035                 0,
4036                 0,
4037                 pbn_b0_2_115200 },
4038
4039         {       PCI_VENDOR_ID_ADDIDATA,
4040                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4041                 PCI_ANY_ID,
4042                 PCI_ANY_ID,
4043                 0,
4044                 0,
4045                 pbn_b0_1_115200 },
4046
4047         {       PCI_VENDOR_ID_ADDIDATA,
4048                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4049                 PCI_ANY_ID,
4050                 PCI_ANY_ID,
4051                 0,
4052                 0,
4053                 pbn_b0_4_115200 },
4054
4055         {       PCI_VENDOR_ID_ADDIDATA,
4056                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4057                 PCI_ANY_ID,
4058                 PCI_ANY_ID,
4059                 0,
4060                 0,
4061                 pbn_b0_2_115200 },
4062
4063         {       PCI_VENDOR_ID_ADDIDATA,
4064                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4065                 PCI_ANY_ID,
4066                 PCI_ANY_ID,
4067                 0,
4068                 0,
4069                 pbn_b0_1_115200 },
4070
4071         {       PCI_VENDOR_ID_ADDIDATA,
4072                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4073                 PCI_ANY_ID,
4074                 PCI_ANY_ID,
4075                 0,
4076                 0,
4077                 pbn_b0_8_115200 },
4078
4079         {       PCI_VENDOR_ID_ADDIDATA,
4080                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4081                 PCI_ANY_ID,
4082                 PCI_ANY_ID,
4083                 0,
4084                 0,
4085                 pbn_ADDIDATA_PCIe_4_3906250 },
4086
4087         {       PCI_VENDOR_ID_ADDIDATA,
4088                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4089                 PCI_ANY_ID,
4090                 PCI_ANY_ID,
4091                 0,
4092                 0,
4093                 pbn_ADDIDATA_PCIe_2_3906250 },
4094
4095         {       PCI_VENDOR_ID_ADDIDATA,
4096                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4097                 PCI_ANY_ID,
4098                 PCI_ANY_ID,
4099                 0,
4100                 0,
4101                 pbn_ADDIDATA_PCIe_1_3906250 },
4102
4103         {       PCI_VENDOR_ID_ADDIDATA,
4104                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4105                 PCI_ANY_ID,
4106                 PCI_ANY_ID,
4107                 0,
4108                 0,
4109                 pbn_ADDIDATA_PCIe_8_3906250 },
4110
4111         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4112                 PCI_VENDOR_ID_IBM, 0x0299,
4113                 0, 0, pbn_b0_bt_2_115200 },
4114
4115         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4116                 0xA000, 0x1000,
4117                 0, 0, pbn_b0_1_115200 },
4118
4119         /* the 9901 is a rebranded 9912 */
4120         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4121                 0xA000, 0x1000,
4122                 0, 0, pbn_b0_1_115200 },
4123
4124         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4125                 0xA000, 0x1000,
4126                 0, 0, pbn_b0_1_115200 },
4127
4128         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4129                 0xA000, 0x1000,
4130                 0, 0, pbn_b0_1_115200 },
4131
4132         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4133                 0xA000, 0x1000,
4134                 0, 0, pbn_b0_1_115200 },
4135
4136         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4137                 0xA000, 0x3002,
4138                 0, 0, pbn_NETMOS9900_2s_115200 },
4139
4140         /*
4141          * Best Connectivity and Rosewill PCI Multi I/O cards
4142          */
4143
4144         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4145                 0xA000, 0x1000,
4146                 0, 0, pbn_b0_1_115200 },
4147
4148         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4149                 0xA000, 0x3002,
4150                 0, 0, pbn_b0_bt_2_115200 },
4151
4152         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4153                 0xA000, 0x3004,
4154                 0, 0, pbn_b0_bt_4_115200 },
4155         /* Intel CE4100 */
4156         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4157                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4158                 pbn_ce4100_1_115200 },
4159
4160         /*
4161          * Cronyx Omega PCI
4162          */
4163         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4164                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4165                 pbn_omegapci },
4166
4167         /*
4168          * Broadcom TruManage
4169          */
4170         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172                 pbn_brcm_trumanage },
4173
4174         /* MKS Tenta SCOM-080x serial cards */
4175         { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
4176         { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
4177
4178         /*
4179          * These entries match devices with class COMMUNICATION_SERIAL,
4180          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4181          */
4182         {       PCI_ANY_ID, PCI_ANY_ID,
4183                 PCI_ANY_ID, PCI_ANY_ID,
4184                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4185                 0xffff00, pbn_default },
4186         {       PCI_ANY_ID, PCI_ANY_ID,
4187                 PCI_ANY_ID, PCI_ANY_ID,
4188                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4189                 0xffff00, pbn_default },
4190         {       PCI_ANY_ID, PCI_ANY_ID,
4191                 PCI_ANY_ID, PCI_ANY_ID,
4192                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4193                 0xffff00, pbn_default },
4194         { 0, }
4195 };
4196
4197 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4198                                                 pci_channel_state_t state)
4199 {
4200         struct serial_private *priv = pci_get_drvdata(dev);
4201
4202         if (state == pci_channel_io_perm_failure)
4203                 return PCI_ERS_RESULT_DISCONNECT;
4204
4205         if (priv)
4206                 pciserial_suspend_ports(priv);
4207
4208         pci_disable_device(dev);
4209
4210         return PCI_ERS_RESULT_NEED_RESET;
4211 }
4212
4213 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4214 {
4215         int rc;
4216
4217         rc = pci_enable_device(dev);
4218
4219         if (rc)
4220                 return PCI_ERS_RESULT_DISCONNECT;
4221
4222         pci_restore_state(dev);
4223         pci_save_state(dev);
4224
4225         return PCI_ERS_RESULT_RECOVERED;
4226 }
4227
4228 static void serial8250_io_resume(struct pci_dev *dev)
4229 {
4230         struct serial_private *priv = pci_get_drvdata(dev);
4231
4232         if (priv)
4233                 pciserial_resume_ports(priv);
4234 }
4235
4236 static struct pci_error_handlers serial8250_err_handler = {
4237         .error_detected = serial8250_io_error_detected,
4238         .slot_reset = serial8250_io_slot_reset,
4239         .resume = serial8250_io_resume,
4240 };
4241
4242 static struct pci_driver serial_pci_driver = {
4243         .name           = "serial",
4244         .probe          = pciserial_init_one,
4245         .remove         = __devexit_p(pciserial_remove_one),
4246 #ifdef CONFIG_PM
4247         .suspend        = pciserial_suspend_one,
4248         .resume         = pciserial_resume_one,
4249 #endif
4250         .id_table       = serial_pci_tbl,
4251         .err_handler    = &serial8250_err_handler,
4252 };
4253
4254 static int __init serial8250_pci_init(void)
4255 {
4256         return pci_register_driver(&serial_pci_driver);
4257 }
4258
4259 static void __exit serial8250_pci_exit(void)
4260 {
4261         pci_unregister_driver(&serial_pci_driver);
4262 }
4263
4264 module_init(serial8250_pci_init);
4265 module_exit(serial8250_pci_exit);
4266
4267 MODULE_LICENSE("GPL");
4268 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4269 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);