drivers/tty/serial/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/bitops.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26
  27 #include "8250.h"
  28
  29 #undef SERIAL_DEBUG_PCI
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*probe)(struct pci_dev *dev);
  43         int     (*init)(struct pci_dev *dev);
  44         int     (*setup)(struct serial_private *,
  45                          const struct pciserial_board *,
  46                          struct uart_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static int pci_default_setup(struct serial_private*,
  61           const struct pciserial_board*, struct uart_port*, int);
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING
  66                "%s: %s\n"
  67                "Please send the output of lspci -vv, this\n"
  68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  69                "manufacturer and name of serial board or\n"
  70                "modem board to rmk+serial@arm.linux.org.uk.\n",
  71                pci_name(dev), str, dev->vendor, dev->device,
  72                dev->subsystem_vendor, dev->subsystem_device);
  73 }
  74
  75 static int
  76 setup_port(struct serial_private *priv, struct uart_port *port,
  77            int bar, int offset, int regshift)
  78 {
  79         struct pci_dev *dev = priv->dev;
  80         unsigned long base, len;
  81
  82         if (bar >= PCI_NUM_BAR_RESOURCES)
  83                 return -EINVAL;
  84
  85         base = pci_resource_start(dev, bar);
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 len =  pci_resource_len(dev, bar);
  89
  90                 if (!priv->remapped_bar[bar])
  91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  92                 if (!priv->remapped_bar[bar])
  93                         return -ENOMEM;
  94
  95                 port->iotype = UPIO_MEM;
  96                 port->iobase = 0;
  97                 port->mapbase = base + offset;
  98                 port->membase = priv->remapped_bar[bar] + offset;
  99                 port->regshift = regshift;
 100         } else {
 101                 port->iotype = UPIO_PORT;
 102                 port->iobase = base + offset;
 103                 port->mapbase = 0;
 104                 port->membase = NULL;
 105                 port->regshift = 0;
 106         }
 107         return 0;
 108 }
 109
 110 /*
 111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 112  */
 113 static int addidata_apci7800_setup(struct serial_private *priv,
 114                                 const struct pciserial_board *board,
 115                                 struct uart_port *port, int idx)
 116 {
 117         unsigned int bar = 0, offset = board->first_offset;
 118         bar = FL_GET_BASE(board->flags);
 119
 120         if (idx < 2) {
 121                 offset += idx * board->uart_offset;
 122         } else if ((idx >= 2) && (idx < 4)) {
 123                 bar += 1;
 124                 offset += ((idx - 2) * board->uart_offset);
 125         } else if ((idx >= 4) && (idx < 6)) {
 126                 bar += 2;
 127                 offset += ((idx - 4) * board->uart_offset);
 128         } else if (idx >= 6) {
 129                 bar += 3;
 130                 offset += ((idx - 6) * board->uart_offset);
 131         }
 132
 133         return setup_port(priv, port, bar, offset, board->reg_shift);
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 142               struct uart_port *port, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(priv, port, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 183                 rc = 1;
 184                 break;
 185         }
 186
 187         return rc;
 188 }
 189
 190 /*
 191  * HP's Diva chip puts the 4th/5th serial port further out, and
 192  * some serial ports are supposed to be hidden on certain models.
 193  */
 194 static int
 195 pci_hp_diva_setup(struct serial_private *priv,
 196                 const struct pciserial_board *board,
 197                 struct uart_port *port, int idx)
 198 {
 199         unsigned int offset = board->first_offset;
 200         unsigned int bar = FL_GET_BASE(board->flags);
 201
 202         switch (priv->dev->subsystem_device) {
 203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 204                 if (idx == 3)
 205                         idx++;
 206                 break;
 207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 208                 if (idx > 0)
 209                         idx++;
 210                 if (idx > 2)
 211                         idx++;
 212                 break;
 213         }
 214         if (idx > 2)
 215                 offset = 0x18;
 216
 217         offset += idx * board->uart_offset;
 218
 219         return setup_port(priv, port, bar, offset, board->reg_shift);
 220 }
 221
 222 /*
 223  * Added for EKF Intel i960 serial boards
 224  */
 225 static int pci_inteli960ni_init(struct pci_dev *dev)
 226 {
 227         unsigned long oldval;
 228
 229         if (!(dev->subsystem_device & 0x1000))
 230                 return -ENODEV;
 231
 232         /* is firmware started? */
 233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 234         if (oldval == 0x00001000L) { /* RESET value */
 235                 printk(KERN_DEBUG "Local i960 firmware missing");
 236                 return -ENODEV;
 237         }
 238         return 0;
 239 }
 240
 241 /*
 242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 243  * that the card interrupt be explicitly enabled or disabled.  This
 244  * seems to be mainly needed on card using the PLX which also use I/O
 245  * mapped memory.
 246  */
 247 static int pci_plx9050_init(struct pci_dev *dev)
 248 {
 249         u8 irq_config;
 250         void __iomem *p;
 251
 252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 253                 moan_device("no memory in bar 0", dev);
 254                 return 0;
 255         }
 256
 257         irq_config = 0x41;
 258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 260                 irq_config = 0x43;
 261
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         /*
 274          * enable/disable interrupts
 275          */
 276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 277         if (p == NULL)
 278                 return -ENOMEM;
 279         writel(irq_config, p + 0x4c);
 280
 281         /*
 282          * Read the register back to ensure that it took effect.
 283          */
 284         readl(p + 0x4c);
 285         iounmap(p);
 286
 287         return 0;
 288 }
 289
 290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 291 {
 292         u8 __iomem *p;
 293
 294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 295                 return;
 296
 297         /*
 298          * disable interrupts
 299          */
 300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 301         if (p != NULL) {
 302                 writel(0, p + 0x4c);
 303
 304                 /*
 305                  * Read the register back to ensure that it took effect.
 306                  */
 307                 readl(p + 0x4c);
 308                 iounmap(p);
 309         }
 310 }
 311
 312 #define NI8420_INT_ENABLE_REG   0x38
 313 #define NI8420_INT_ENABLE_BIT   0x2000
 314
 315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 316 {
 317         void __iomem *p;
 318         unsigned long base, len;
 319         unsigned int bar = 0;
 320
 321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 322                 moan_device("no memory in bar", dev);
 323                 return;
 324         }
 325
 326         base = pci_resource_start(dev, bar);
 327         len =  pci_resource_len(dev, bar);
 328         p = ioremap_nocache(base, len);
 329         if (p == NULL)
 330                 return;
 331
 332         /* Disable the CPU Interrupt */
 333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 334                p + NI8420_INT_ENABLE_REG);
 335         iounmap(p);
 336 }
 337
 338
 339 /* MITE registers */
 340 #define MITE_IOWBSR1    0xc4
 341 #define MITE_IOWCR1     0xf4
 342 #define MITE_LCIMR1     0x08
 343 #define MITE_LCIMR2     0x10
 344
 345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 346
 347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 348 {
 349         void __iomem *p;
 350         unsigned long base, len;
 351         unsigned int bar = 0;
 352
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357
 358         base = pci_resource_start(dev, bar);
 359         len =  pci_resource_len(dev, bar);
 360         p = ioremap_nocache(base, len);
 361         if (p == NULL)
 362                 return;
 363
 364         /* Disable the CPU Interrupt */
 365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366         iounmap(p);
 367 }
 368
 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370 static int
 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                 struct uart_port *port, int idx)
 373 {
 374         unsigned int bar, offset = board->first_offset;
 375
 376         bar = 0;
 377
 378         if (idx < 4) {
 379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                 offset += idx * board->uart_offset;
 381         } else if (idx < 8) {
 382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                 offset += idx * board->uart_offset + 0xC00;
 384         } else /* we have only 8 ports on PMC-OCTALPRO */
 385                 return 1;
 386
 387         return setup_port(priv, port, bar, offset, board->reg_shift);
 388 }
 389
 390 /*
 391 * This does initialization for PMC OCTALPRO cards:
 392 * maps the device memory, resets the UARTs (needed, bc
 393 * if the module is removed and inserted again, the card
 394 * is in the sleep mode) and enables global interrupt.
 395 */
 396
 397 /* global control register offset for SBS PMC-OctalPro */
 398 #define OCT_REG_CR_OFF          0x500
 399
 400 static int sbs_init(struct pci_dev *dev)
 401 {
 402         u8 __iomem *p;
 403
 404         p = pci_ioremap_bar(dev, 0);
 405
 406         if (p == NULL)
 407                 return -ENOMEM;
 408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409         writeb(0x10, p + OCT_REG_CR_OFF);
 410         udelay(50);
 411         writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413         /* Set bit-2 (INTENABLE) of Control Register */
 414         writeb(0x4, p + OCT_REG_CR_OFF);
 415         iounmap(p);
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Disables the global interrupt of PMC-OctalPro
 422  */
 423
 424 static void __devexit sbs_exit(struct pci_dev *dev)
 425 {
 426         u8 __iomem *p;
 427
 428         p = pci_ioremap_bar(dev, 0);
 429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430         if (p != NULL)
 431                 writeb(0, p + OCT_REG_CR_OFF);
 432         iounmap(p);
 433 }
 434
 435 /*
 436  * SIIG serial cards have an PCI interface chip which also controls
 437  * the UART clocking frequency. Each UART can be clocked independently
 438  * (except cards equipped with 4 UARTs) and initial clocking settings
 439  * are stored in the EEPROM chip. It can cause problems because this
 440  * version of serial driver doesn't support differently clocked UART's
 441  * on single PCI card. To prevent this, initialization functions set
 442  * high frequency clocking for all UART's on given card. It is safe (I
 443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444  * with other OSes (like M$ DOS).
 445  *
 446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447  *
 448  * There is two family of SIIG serial cards with different PCI
 449  * interface chip and different configuration methods:
 450  *     - 10x cards have control registers in IO and/or memory space;
 451  *     - 20x cards have control registers in standard PCI configuration space.
 452  *
 453  * Note: all 10x cards have PCI device ids 0x10..
 454  *       all 20x cards have PCI device ids 0x20..
 455  *
 456  * There are also Quartet Serial cards which use Oxford Semiconductor
 457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458  *
 459  * Note: some SIIG cards are probed by the parport_serial object.
 460  */
 461
 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465 static int pci_siig10x_init(struct pci_dev *dev)
 466 {
 467         u16 data;
 468         void __iomem *p;
 469
 470         switch (dev->device & 0xfff8) {
 471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                 data = 0xffdf;
 473                 break;
 474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                 data = 0xf7ff;
 476                 break;
 477         default:                        /* 1S1P, 4S */
 478                 data = 0xfffb;
 479                 break;
 480         }
 481
 482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 483         if (p == NULL)
 484                 return -ENOMEM;
 485
 486         writew(readw(p + 0x28) & data, p + 0x28);
 487         readw(p + 0x28);
 488         iounmap(p);
 489         return 0;
 490 }
 491
 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495 static int pci_siig20x_init(struct pci_dev *dev)
 496 {
 497         u8 data;
 498
 499         /* Change clock frequency for the first UART. */
 500         pci_read_config_byte(dev, 0x6f, &data);
 501         pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503         /* If this card has 2 UART, we have to do the same with second UART. */
 504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                 pci_read_config_byte(dev, 0x73, &data);
 507                 pci_write_config_byte(dev, 0x73, data & 0xef);
 508         }
 509         return 0;
 510 }
 511
 512 static int pci_siig_init(struct pci_dev *dev)
 513 {
 514         unsigned int type = dev->device & 0xff00;
 515
 516         if (type == 0x1000)
 517                 return pci_siig10x_init(dev);
 518         else if (type == 0x2000)
 519                 return pci_siig20x_init(dev);
 520
 521         moan_device("Unknown SIIG card", dev);
 522         return -ENODEV;
 523 }
 524
 525 static int pci_siig_setup(struct serial_private *priv,
 526                           const struct pciserial_board *board,
 527                           struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531         if (idx > 3) {
 532                 bar = 4;
 533                 offset = (idx - 4) * 8;
 534         }
 535
 536         return setup_port(priv, port, bar, offset, 0);
 537 }
 538
 539 /*
 540  * Timedia has an explosion of boards, and to avoid the PCI table from
 541  * growing *huge*, we use this function to collapse some 70 entries
 542  * in the PCI table into one, for sanity's and compactness's sake.
 543  */
 544 static const unsigned short timedia_single_port[] = {
 545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546 };
 547
 548 static const unsigned short timedia_dual_port[] = {
 549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553         0xD079, 0
 554 };
 555
 556 static const unsigned short timedia_quad_port[] = {
 557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560         0xB157, 0
 561 };
 562
 563 static const unsigned short timedia_eight_port[] = {
 564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566 };
 567
 568 static const struct timedia_struct {
 569         int num;
 570         const unsigned short *ids;
 571 } timedia_data[] = {
 572         { 1, timedia_single_port },
 573         { 2, timedia_dual_port },
 574         { 4, timedia_quad_port },
 575         { 8, timedia_eight_port }
 576 };
 577
 578 /*
 579  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 580  * listing them individually, this driver merely grabs them all with
 581  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 582  * and should be left free to be claimed by parport_serial instead.
 583  */
 584 static int pci_timedia_probe(struct pci_dev *dev)
 585 {
 586         /*
 587          * Check the third digit of the subdevice ID
 588          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 589          */
 590         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 591                 dev_info(&dev->dev,
 592                         "ignoring Timedia subdevice %04x for parport_serial\n",
 593                         dev->subsystem_device);
 594                 return -ENODEV;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int pci_timedia_init(struct pci_dev *dev)
 601 {
 602         const unsigned short *ids;
 603         int i, j;
 604
 605         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 606                 ids = timedia_data[i].ids;
 607                 for (j = 0; ids[j]; j++)
 608                         if (dev->subsystem_device == ids[j])
 609                                 return timedia_data[i].num;
 610         }
 611         return 0;
 612 }
 613
 614 /*
 615  * Timedia/SUNIX uses a mixture of BARs and offsets
 616  * Ugh, this is ugly as all hell --- TYT
 617  */
 618 static int
 619 pci_timedia_setup(struct serial_private *priv,
 620                   const struct pciserial_board *board,
 621                   struct uart_port *port, int idx)
 622 {
 623         unsigned int bar = 0, offset = board->first_offset;
 624
 625         switch (idx) {
 626         case 0:
 627                 bar = 0;
 628                 break;
 629         case 1:
 630                 offset = board->uart_offset;
 631                 bar = 0;
 632                 break;
 633         case 2:
 634                 bar = 1;
 635                 break;
 636         case 3:
 637                 offset = board->uart_offset;
 638                 /* FALLTHROUGH */
 639         case 4: /* BAR 2 */
 640         case 5: /* BAR 3 */
 641         case 6: /* BAR 4 */
 642         case 7: /* BAR 5 */
 643                 bar = idx - 2;
 644         }
 645
 646         return setup_port(priv, port, bar, offset, board->reg_shift);
 647 }
 648
 649 /*
 650  * Some Titan cards are also a little weird
 651  */
 652 static int
 653 titan_400l_800l_setup(struct serial_private *priv,
 654                       const struct pciserial_board *board,
 655                       struct uart_port *port, int idx)
 656 {
 657         unsigned int bar, offset = board->first_offset;
 658
 659         switch (idx) {
 660         case 0:
 661                 bar = 1;
 662                 break;
 663         case 1:
 664                 bar = 2;
 665                 break;
 666         default:
 667                 bar = 4;
 668                 offset = (idx - 2) * board->uart_offset;
 669         }
 670
 671         return setup_port(priv, port, bar, offset, board->reg_shift);
 672 }
 673
 674 static int pci_xircom_init(struct pci_dev *dev)
 675 {
 676         msleep(100);
 677         return 0;
 678 }
 679
 680 static int pci_ni8420_init(struct pci_dev *dev)
 681 {
 682         void __iomem *p;
 683         unsigned long base, len;
 684         unsigned int bar = 0;
 685
 686         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 687                 moan_device("no memory in bar", dev);
 688                 return 0;
 689         }
 690
 691         base = pci_resource_start(dev, bar);
 692         len =  pci_resource_len(dev, bar);
 693         p = ioremap_nocache(base, len);
 694         if (p == NULL)
 695                 return -ENOMEM;
 696
 697         /* Enable CPU Interrupt */
 698         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 699                p + NI8420_INT_ENABLE_REG);
 700
 701         iounmap(p);
 702         return 0;
 703 }
 704
 705 #define MITE_IOWBSR1_WSIZE      0xa
 706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 707 #define MITE_IOWBSR1_WENAB      (1 << 7)
 708 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 709 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 711
 712 static int pci_ni8430_init(struct pci_dev *dev)
 713 {
 714         void __iomem *p;
 715         unsigned long base, len;
 716         u32 device_window;
 717         unsigned int bar = 0;
 718
 719         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 720                 moan_device("no memory in bar", dev);
 721                 return 0;
 722         }
 723
 724         base = pci_resource_start(dev, bar);
 725         len =  pci_resource_len(dev, bar);
 726         p = ioremap_nocache(base, len);
 727         if (p == NULL)
 728                 return -ENOMEM;
 729
 730         /* Set device window address and size in BAR0 */
 731         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 732                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 733         writel(device_window, p + MITE_IOWBSR1);
 734
 735         /* Set window access to go to RAMSEL IO address space */
 736         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 737                p + MITE_IOWCR1);
 738
 739         /* Enable IO Bus Interrupt 0 */
 740         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 741
 742         /* Enable CPU Interrupt */
 743         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 744
 745         iounmap(p);
 746         return 0;
 747 }
 748
 749 /* UART Port Control Register */
 750 #define NI8430_PORTCON  0x0f
 751 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 752
 753 static int
 754 pci_ni8430_setup(struct serial_private *priv,
 755                  const struct pciserial_board *board,
 756                  struct uart_port *port, int idx)
 757 {
 758         void __iomem *p;
 759         unsigned long base, len;
 760         unsigned int bar, offset = board->first_offset;
 761
 762         if (idx >= board->num_ports)
 763                 return 1;
 764
 765         bar = FL_GET_BASE(board->flags);
 766         offset += idx * board->uart_offset;
 767
 768         base = pci_resource_start(priv->dev, bar);
 769         len =  pci_resource_len(priv->dev, bar);
 770         p = ioremap_nocache(base, len);
 771
 772         /* enable the transceiver */
 773         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 774                p + offset + NI8430_PORTCON);
 775
 776         iounmap(p);
 777
 778         return setup_port(priv, port, bar, offset, board->reg_shift);
 779 }
 780
 781 static int pci_netmos_9900_setup(struct serial_private *priv,
 782                                 const struct pciserial_board *board,
 783                                 struct uart_port *port, int idx)
 784 {
 785         unsigned int bar;
 786
 787         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 788                 /* netmos apparently orders BARs by datasheet layout, so serial
 789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 790                  */
 791                 bar = 3 * idx;
 792
 793                 return setup_port(priv, port, bar, 0, board->reg_shift);
 794         } else {
 795                 return pci_default_setup(priv, board, port, idx);
 796         }
 797 }
 798
 799 /* the 99xx series comes with a range of device IDs and a variety
 800  * of capabilities:
 801  *
 802  * 9900 has varying capabilities and can cascade to sub-controllers
 803  *   (cascading should be purely internal)
 804  * 9904 is hardwired with 4 serial ports
 805  * 9912 and 9922 are hardwired with 2 serial ports
 806  */
 807 static int pci_netmos_9900_numports(struct pci_dev *dev)
 808 {
 809         unsigned int c = dev->class;
 810         unsigned int pi;
 811         unsigned short sub_serports;
 812
 813         pi = (c & 0xff);
 814
 815         if (pi == 2) {
 816                 return 1;
 817         } else if ((pi == 0) &&
 818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 819                 /* two possibilities: 0x30ps encodes number of parallel and
 820                  * serial ports, or 0x1000 indicates *something*. This is not
 821                  * immediately obvious, since the 2s1p+4s configuration seems
 822                  * to offer all functionality on functions 0..2, while still
 823                  * advertising the same function 3 as the 4s+2s1p config.
 824                  */
 825                 sub_serports = dev->subsystem_device & 0xf;
 826                 if (sub_serports > 0) {
 827                         return sub_serports;
 828                 } else {
 829                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                         return 0;
 831                 }
 832         }
 833
 834         moan_device("unknown NetMos/Mostech program interface", dev);
 835         return 0;
 836 }
 837
 838 static int pci_netmos_init(struct pci_dev *dev)
 839 {
 840         /* subdevice 0x00PS means <P> parallel, <S> serial */
 841         unsigned int num_serial = dev->subsystem_device & 0xf;
 842
 843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 845                 return 0;
 846
 847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 848                         dev->subsystem_device == 0x0299)
 849                 return 0;
 850
 851         switch (dev->device) { /* FALLTHROUGH on all */
 852                 case PCI_DEVICE_ID_NETMOS_9904:
 853                 case PCI_DEVICE_ID_NETMOS_9912:
 854                 case PCI_DEVICE_ID_NETMOS_9922:
 855                 case PCI_DEVICE_ID_NETMOS_9900:
 856                         num_serial = pci_netmos_9900_numports(dev);
 857                         break;
 858
 859                 default:
 860                         if (num_serial == 0 ) {
 861                                 moan_device("unknown NetMos/Mostech device", dev);
 862                         }
 863         }
 864
 865         if (num_serial == 0)
 866                 return -ENODEV;
 867
 868         return num_serial;
 869 }
 870
 871 /*
 872  * These chips are available with optionally one parallel port and up to
 873  * two serial ports. Unfortunately they all have the same product id.
 874  *
 875  * Basic configuration is done over a region of 32 I/O ports. The base
 876  * ioport is called INTA or INTC, depending on docs/other drivers.
 877  *
 878  * The region of the 32 I/O ports is configured in POSIO0R...
 879  */
 880
 881 /* registers */
 882 #define ITE_887x_MISCR          0x9c
 883 #define ITE_887x_INTCBAR        0x78
 884 #define ITE_887x_UARTBAR        0x7c
 885 #define ITE_887x_PS0BAR         0x10
 886 #define ITE_887x_POSIO0         0x60
 887
 888 /* I/O space size */
 889 #define ITE_887x_IOSIZE         32
 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 895 #define ITE_887x_POSIO_SPEED            (3 << 29)
 896 /* enable IO_Space bit */
 897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 898
 899 static int pci_ite887x_init(struct pci_dev *dev)
 900 {
 901         /* inta_addr are the configuration addresses of the ITE */
 902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 903                                                         0x200, 0x280, 0 };
 904         int ret, i, type;
 905         struct resource *iobase = NULL;
 906         u32 miscr, uartbar, ioport;
 907
 908         /* search for the base-ioport */
 909         i = 0;
 910         while (inta_addr[i] && iobase == NULL) {
 911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 912                                                                 "ite887x");
 913                 if (iobase != NULL) {
 914                         /* write POSIO0R - speed | size | ioport */
 915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 918                         /* write INTCBAR - ioport */
 919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 920                                                                 inta_addr[i]);
 921                         ret = inb(inta_addr[i]);
 922                         if (ret != 0xff) {
 923                                 /* ioport connected */
 924                                 break;
 925                         }
 926                         release_region(iobase->start, ITE_887x_IOSIZE);
 927                         iobase = NULL;
 928                 }
 929                 i++;
 930         }
 931
 932         if (!inta_addr[i]) {
 933                 printk(KERN_ERR "ite887x: could not find iobase\n");
 934                 return -ENODEV;
 935         }
 936
 937         /* start of undocumented type checking (see parport_pc.c) */
 938         type = inb(iobase->start + 0x18) & 0x0f;
 939
 940         switch (type) {
 941         case 0x2:       /* ITE8871 (1P) */
 942         case 0xa:       /* ITE8875 (1P) */
 943                 ret = 0;
 944                 break;
 945         case 0xe:       /* ITE8872 (2S1P) */
 946                 ret = 2;
 947                 break;
 948         case 0x6:       /* ITE8873 (1S) */
 949                 ret = 1;
 950                 break;
 951         case 0x8:       /* ITE8874 (2S) */
 952                 ret = 2;
 953                 break;
 954         default:
 955                 moan_device("Unknown ITE887x", dev);
 956                 ret = -ENODEV;
 957         }
 958
 959         /* configure all serial ports */
 960         for (i = 0; i < ret; i++) {
 961                 /* read the I/O port from the device */
 962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 963                                                                 &ioport);
 964                 ioport &= 0x0000FF00;   /* the actual base address */
 965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 968
 969                 /* write the ioport to the UARTBAR */
 970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 974
 975                 /* get current config */
 976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 977                 /* disable interrupts (UARTx_Routing[3:0]) */
 978                 miscr &= ~(0xf << (12 - 4 * i));
 979                 /* activate the UART (UARTx_En) */
 980                 miscr |= 1 << (23 - i);
 981                 /* write new config with activated UART */
 982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 983         }
 984
 985         if (ret <= 0) {
 986                 /* the device has no UARTs if we get here */
 987                 release_region(iobase->start, ITE_887x_IOSIZE);
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 994 {
 995         u32 ioport;
 996         /* the ioport is bit 0-15 in POSIO0R */
 997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 998         ioport &= 0xffff;
 999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 printk(KERN_DEBUG
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                                                                 number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_port *port, int idx)
1038 {
1039         unsigned int bar, offset = board->first_offset, maxnr;
1040
1041         bar = FL_GET_BASE(board->flags);
1042         if (board->flags & FL_BASE_BARS)
1043                 bar += idx;
1044         else
1045                 offset += idx * board->uart_offset;
1046
1047         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048                 (board->reg_shift + 3);
1049
1050         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051                 return 1;
1052
1053         return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058                   const struct pciserial_board *board,
1059                   struct uart_port *port, int idx)
1060 {
1061         int ret;
1062
1063         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064         port->iotype = UPIO_MEM32;
1065         port->type = PORT_XSCALE;
1066         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067         port->regshift = 2;
1068
1069         return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074                       const struct pciserial_board *board,
1075                       struct uart_port *port, int idx)
1076 {
1077         return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int skip_tx_en_setup(struct serial_private *priv,
1081                         const struct pciserial_board *board,
1082                         struct uart_port *port, int idx)
1083 {
1084         port->flags |= UPF_NO_TXEN_TEST;
1085         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1087                           priv->dev->vendor,
1088                           priv->dev->device,
1089                           priv->dev->subsystem_vendor,
1090                           priv->dev->subsystem_device);
1091
1092         return pci_default_setup(priv, board, port, idx);
1093 }
1094
1095 static int pci_eg20t_init(struct pci_dev *dev)
1096 {
1097 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1098         return -ENODEV;
1099 #else
1100         return 0;
1101 #endif
1102 }
1103
1104 static int
1105 pci_xr17c154_setup(struct serial_private *priv,
1106                   const struct pciserial_board *board,
1107                   struct uart_port *port, int idx)
1108 {
1109         port->flags |= UPF_EXAR_EFR;
1110         return pci_default_setup(priv, board, port, idx);
1111 }
1112
1113 /* This should be in linux/pci_ids.h */
1114 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1115 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1116 #define PCI_DEVICE_ID_OCTPRO            0x0001
1117 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1118 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1119 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1120 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1121 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1122 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1123 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1124 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1125 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1126 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1127 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1128 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1129 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1130 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1131 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1132 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1133 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1134 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1135 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1136 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1137 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1138 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1139
1140 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1141 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1142
1143 /*
1144  * Master list of serial port init/setup/exit quirks.
1145  * This does not describe the general nature of the port.
1146  * (ie, baud base, number and location of ports, etc)
1147  *
1148  * This list is ordered alphabetically by vendor then device.
1149  * Specific entries must come before more generic entries.
1150  */
1151 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1152         /*
1153         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1154         */
1155         {
1156                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1157                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1158                 .subvendor      = PCI_ANY_ID,
1159                 .subdevice      = PCI_ANY_ID,
1160                 .setup          = addidata_apci7800_setup,
1161         },
1162         /*
1163          * AFAVLAB cards - these may be called via parport_serial
1164          *  It is not clear whether this applies to all products.
1165          */
1166         {
1167                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1168                 .device         = PCI_ANY_ID,
1169                 .subvendor      = PCI_ANY_ID,
1170                 .subdevice      = PCI_ANY_ID,
1171                 .setup          = afavlab_setup,
1172         },
1173         /*
1174          * HP Diva
1175          */
1176         {
1177                 .vendor         = PCI_VENDOR_ID_HP,
1178                 .device         = PCI_DEVICE_ID_HP_DIVA,
1179                 .subvendor      = PCI_ANY_ID,
1180                 .subdevice      = PCI_ANY_ID,
1181                 .init           = pci_hp_diva_init,
1182                 .setup          = pci_hp_diva_setup,
1183         },
1184         /*
1185          * Intel
1186          */
1187         {
1188                 .vendor         = PCI_VENDOR_ID_INTEL,
1189                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1190                 .subvendor      = 0xe4bf,
1191                 .subdevice      = PCI_ANY_ID,
1192                 .init           = pci_inteli960ni_init,
1193                 .setup          = pci_default_setup,
1194         },
1195         {
1196                 .vendor         = PCI_VENDOR_ID_INTEL,
1197                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1198                 .subvendor      = PCI_ANY_ID,
1199                 .subdevice      = PCI_ANY_ID,
1200                 .setup          = skip_tx_en_setup,
1201         },
1202         {
1203                 .vendor         = PCI_VENDOR_ID_INTEL,
1204                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1205                 .subvendor      = PCI_ANY_ID,
1206                 .subdevice      = PCI_ANY_ID,
1207                 .setup          = skip_tx_en_setup,
1208         },
1209         {
1210                 .vendor         = PCI_VENDOR_ID_INTEL,
1211                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1212                 .subvendor      = PCI_ANY_ID,
1213                 .subdevice      = PCI_ANY_ID,
1214                 .setup          = skip_tx_en_setup,
1215         },
1216         {
1217                 .vendor         = PCI_VENDOR_ID_INTEL,
1218                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1219                 .subvendor      = PCI_ANY_ID,
1220                 .subdevice      = PCI_ANY_ID,
1221                 .setup          = ce4100_serial_setup,
1222         },
1223         /*
1224          * ITE
1225          */
1226         {
1227                 .vendor         = PCI_VENDOR_ID_ITE,
1228                 .device         = PCI_DEVICE_ID_ITE_8872,
1229                 .subvendor      = PCI_ANY_ID,
1230                 .subdevice      = PCI_ANY_ID,
1231                 .init           = pci_ite887x_init,
1232                 .setup          = pci_default_setup,
1233                 .exit           = __devexit_p(pci_ite887x_exit),
1234         },
1235         /*
1236          * National Instruments
1237          */
1238         {
1239                 .vendor         = PCI_VENDOR_ID_NI,
1240                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1241                 .subvendor      = PCI_ANY_ID,
1242                 .subdevice      = PCI_ANY_ID,
1243                 .init           = pci_ni8420_init,
1244                 .setup          = pci_default_setup,
1245                 .exit           = __devexit_p(pci_ni8420_exit),
1246         },
1247         {
1248                 .vendor         = PCI_VENDOR_ID_NI,
1249                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1250                 .subvendor      = PCI_ANY_ID,
1251                 .subdevice      = PCI_ANY_ID,
1252                 .init           = pci_ni8420_init,
1253                 .setup          = pci_default_setup,
1254                 .exit           = __devexit_p(pci_ni8420_exit),
1255         },
1256         {
1257                 .vendor         = PCI_VENDOR_ID_NI,
1258                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1259                 .subvendor      = PCI_ANY_ID,
1260                 .subdevice      = PCI_ANY_ID,
1261                 .init           = pci_ni8420_init,
1262                 .setup          = pci_default_setup,
1263                 .exit           = __devexit_p(pci_ni8420_exit),
1264         },
1265         {
1266                 .vendor         = PCI_VENDOR_ID_NI,
1267                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1268                 .subvendor      = PCI_ANY_ID,
1269                 .subdevice      = PCI_ANY_ID,
1270                 .init           = pci_ni8420_init,
1271                 .setup          = pci_default_setup,
1272                 .exit           = __devexit_p(pci_ni8420_exit),
1273         },
1274         {
1275                 .vendor         = PCI_VENDOR_ID_NI,
1276                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1277                 .subvendor      = PCI_ANY_ID,
1278                 .subdevice      = PCI_ANY_ID,
1279                 .init           = pci_ni8420_init,
1280                 .setup          = pci_default_setup,
1281                 .exit           = __devexit_p(pci_ni8420_exit),
1282         },
1283         {
1284                 .vendor         = PCI_VENDOR_ID_NI,
1285                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1286                 .subvendor      = PCI_ANY_ID,
1287                 .subdevice      = PCI_ANY_ID,
1288                 .init           = pci_ni8420_init,
1289                 .setup          = pci_default_setup,
1290                 .exit           = __devexit_p(pci_ni8420_exit),
1291         },
1292         {
1293                 .vendor         = PCI_VENDOR_ID_NI,
1294                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1295                 .subvendor      = PCI_ANY_ID,
1296                 .subdevice      = PCI_ANY_ID,
1297                 .init           = pci_ni8420_init,
1298                 .setup          = pci_default_setup,
1299                 .exit           = __devexit_p(pci_ni8420_exit),
1300         },
1301         {
1302                 .vendor         = PCI_VENDOR_ID_NI,
1303                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1304                 .subvendor      = PCI_ANY_ID,
1305                 .subdevice      = PCI_ANY_ID,
1306                 .init           = pci_ni8420_init,
1307                 .setup          = pci_default_setup,
1308                 .exit           = __devexit_p(pci_ni8420_exit),
1309         },
1310         {
1311                 .vendor         = PCI_VENDOR_ID_NI,
1312                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1313                 .subvendor      = PCI_ANY_ID,
1314                 .subdevice      = PCI_ANY_ID,
1315                 .init           = pci_ni8420_init,
1316                 .setup          = pci_default_setup,
1317                 .exit           = __devexit_p(pci_ni8420_exit),
1318         },
1319         {
1320                 .vendor         = PCI_VENDOR_ID_NI,
1321                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1322                 .subvendor      = PCI_ANY_ID,
1323                 .subdevice      = PCI_ANY_ID,
1324                 .init           = pci_ni8420_init,
1325                 .setup          = pci_default_setup,
1326                 .exit           = __devexit_p(pci_ni8420_exit),
1327         },
1328         {
1329                 .vendor         = PCI_VENDOR_ID_NI,
1330                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1331                 .subvendor      = PCI_ANY_ID,
1332                 .subdevice      = PCI_ANY_ID,
1333                 .init           = pci_ni8420_init,
1334                 .setup          = pci_default_setup,
1335                 .exit           = __devexit_p(pci_ni8420_exit),
1336         },
1337         {
1338                 .vendor         = PCI_VENDOR_ID_NI,
1339                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1340                 .subvendor      = PCI_ANY_ID,
1341                 .subdevice      = PCI_ANY_ID,
1342                 .init           = pci_ni8420_init,
1343                 .setup          = pci_default_setup,
1344                 .exit           = __devexit_p(pci_ni8420_exit),
1345         },
1346         {
1347                 .vendor         = PCI_VENDOR_ID_NI,
1348                 .device         = PCI_ANY_ID,
1349                 .subvendor      = PCI_ANY_ID,
1350                 .subdevice      = PCI_ANY_ID,
1351                 .init           = pci_ni8430_init,
1352                 .setup          = pci_ni8430_setup,
1353                 .exit           = __devexit_p(pci_ni8430_exit),
1354         },
1355         /*
1356          * Panacom
1357          */
1358         {
1359                 .vendor         = PCI_VENDOR_ID_PANACOM,
1360                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1361                 .subvendor      = PCI_ANY_ID,
1362                 .subdevice      = PCI_ANY_ID,
1363                 .init           = pci_plx9050_init,
1364                 .setup          = pci_default_setup,
1365                 .exit           = __devexit_p(pci_plx9050_exit),
1366         },
1367         {
1368                 .vendor         = PCI_VENDOR_ID_PANACOM,
1369                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1370                 .subvendor      = PCI_ANY_ID,
1371                 .subdevice      = PCI_ANY_ID,
1372                 .init           = pci_plx9050_init,
1373                 .setup          = pci_default_setup,
1374                 .exit           = __devexit_p(pci_plx9050_exit),
1375         },
1376         /*
1377          * PLX
1378          */
1379         {
1380                 .vendor         = PCI_VENDOR_ID_PLX,
1381                 .device         = PCI_DEVICE_ID_PLX_9030,
1382                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1383                 .subdevice      = PCI_ANY_ID,
1384                 .setup          = pci_default_setup,
1385         },
1386         {
1387                 .vendor         = PCI_VENDOR_ID_PLX,
1388                 .device         = PCI_DEVICE_ID_PLX_9050,
1389                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1390                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1391                 .init           = pci_plx9050_init,
1392                 .setup          = pci_default_setup,
1393                 .exit           = __devexit_p(pci_plx9050_exit),
1394         },
1395         {
1396                 .vendor         = PCI_VENDOR_ID_PLX,
1397                 .device         = PCI_DEVICE_ID_PLX_9050,
1398                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1399                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1400                 .init           = pci_plx9050_init,
1401                 .setup          = pci_default_setup,
1402                 .exit           = __devexit_p(pci_plx9050_exit),
1403         },
1404         {
1405                 .vendor         = PCI_VENDOR_ID_PLX,
1406                 .device         = PCI_DEVICE_ID_PLX_9050,
1407                 .subvendor      = PCI_VENDOR_ID_PLX,
1408                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1409                 .init           = pci_plx9050_init,
1410                 .setup          = pci_default_setup,
1411                 .exit           = __devexit_p(pci_plx9050_exit),
1412         },
1413         {
1414                 .vendor         = PCI_VENDOR_ID_PLX,
1415                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1416                 .subvendor      = PCI_VENDOR_ID_PLX,
1417                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1418                 .init           = pci_plx9050_init,
1419                 .setup          = pci_default_setup,
1420                 .exit           = __devexit_p(pci_plx9050_exit),
1421         },
1422         /*
1423          * SBS Technologies, Inc., PMC-OCTALPRO 232
1424          */
1425         {
1426                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1427                 .device         = PCI_DEVICE_ID_OCTPRO,
1428                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1429                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1430                 .init           = sbs_init,
1431                 .setup          = sbs_setup,
1432                 .exit           = __devexit_p(sbs_exit),
1433         },
1434         /*
1435          * SBS Technologies, Inc., PMC-OCTALPRO 422
1436          */
1437         {
1438                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1439                 .device         = PCI_DEVICE_ID_OCTPRO,
1440                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1441                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1442                 .init           = sbs_init,
1443                 .setup          = sbs_setup,
1444                 .exit           = __devexit_p(sbs_exit),
1445         },
1446         /*
1447          * SBS Technologies, Inc., P-Octal 232
1448          */
1449         {
1450                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1451                 .device         = PCI_DEVICE_ID_OCTPRO,
1452                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1453                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1454                 .init           = sbs_init,
1455                 .setup          = sbs_setup,
1456                 .exit           = __devexit_p(sbs_exit),
1457         },
1458         /*
1459          * SBS Technologies, Inc., P-Octal 422
1460          */
1461         {
1462                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1463                 .device         = PCI_DEVICE_ID_OCTPRO,
1464                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1465                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1466                 .init           = sbs_init,
1467                 .setup          = sbs_setup,
1468                 .exit           = __devexit_p(sbs_exit),
1469         },
1470         /*
1471          * SIIG cards - these may be called via parport_serial
1472          */
1473         {
1474                 .vendor         = PCI_VENDOR_ID_SIIG,
1475                 .device         = PCI_ANY_ID,
1476                 .subvendor      = PCI_ANY_ID,
1477                 .subdevice      = PCI_ANY_ID,
1478                 .init           = pci_siig_init,
1479                 .setup          = pci_siig_setup,
1480         },
1481         /*
1482          * Titan cards
1483          */
1484         {
1485                 .vendor         = PCI_VENDOR_ID_TITAN,
1486                 .device         = PCI_DEVICE_ID_TITAN_400L,
1487                 .subvendor      = PCI_ANY_ID,
1488                 .subdevice      = PCI_ANY_ID,
1489                 .setup          = titan_400l_800l_setup,
1490         },
1491         {
1492                 .vendor         = PCI_VENDOR_ID_TITAN,
1493                 .device         = PCI_DEVICE_ID_TITAN_800L,
1494                 .subvendor      = PCI_ANY_ID,
1495                 .subdevice      = PCI_ANY_ID,
1496                 .setup          = titan_400l_800l_setup,
1497         },
1498         /*
1499          * Timedia cards
1500          */
1501         {
1502                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1503                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1504                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1505                 .subdevice      = PCI_ANY_ID,
1506                 .probe          = pci_timedia_probe,
1507                 .init           = pci_timedia_init,
1508                 .setup          = pci_timedia_setup,
1509         },
1510         {
1511                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1512                 .device         = PCI_ANY_ID,
1513                 .subvendor      = PCI_ANY_ID,
1514                 .subdevice      = PCI_ANY_ID,
1515                 .setup          = pci_timedia_setup,
1516         },
1517         /*
1518          * Exar cards
1519          */
1520         {
1521                 .vendor = PCI_VENDOR_ID_EXAR,
1522                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1523                 .subvendor      = PCI_ANY_ID,
1524                 .subdevice      = PCI_ANY_ID,
1525                 .setup          = pci_xr17c154_setup,
1526         },
1527         {
1528                 .vendor = PCI_VENDOR_ID_EXAR,
1529                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1530                 .subvendor      = PCI_ANY_ID,
1531                 .subdevice      = PCI_ANY_ID,
1532                 .setup          = pci_xr17c154_setup,
1533         },
1534         {
1535                 .vendor = PCI_VENDOR_ID_EXAR,
1536                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1537                 .subvendor      = PCI_ANY_ID,
1538                 .subdevice      = PCI_ANY_ID,
1539                 .setup          = pci_xr17c154_setup,
1540         },
1541         /*
1542          * Xircom cards
1543          */
1544         {
1545                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1546                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1547                 .subvendor      = PCI_ANY_ID,
1548                 .subdevice      = PCI_ANY_ID,
1549                 .init           = pci_xircom_init,
1550                 .setup          = pci_default_setup,
1551         },
1552         /*
1553          * Netmos cards - these may be called via parport_serial
1554          */
1555         {
1556                 .vendor         = PCI_VENDOR_ID_NETMOS,
1557                 .device         = PCI_ANY_ID,
1558                 .subvendor      = PCI_ANY_ID,
1559                 .subdevice      = PCI_ANY_ID,
1560                 .init           = pci_netmos_init,
1561                 .setup          = pci_netmos_9900_setup,
1562         },
1563         /*
1564          * For Oxford Semiconductor Tornado based devices
1565          */
1566         {
1567                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1568                 .device         = PCI_ANY_ID,
1569                 .subvendor      = PCI_ANY_ID,
1570                 .subdevice      = PCI_ANY_ID,
1571                 .init           = pci_oxsemi_tornado_init,
1572                 .setup          = pci_default_setup,
1573         },
1574         {
1575                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1576                 .device         = PCI_ANY_ID,
1577                 .subvendor      = PCI_ANY_ID,
1578                 .subdevice      = PCI_ANY_ID,
1579                 .init           = pci_oxsemi_tornado_init,
1580                 .setup          = pci_default_setup,
1581         },
1582         {
1583                 .vendor         = PCI_VENDOR_ID_DIGI,
1584                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1585                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1586                 .subdevice              = PCI_ANY_ID,
1587                 .init                   = pci_oxsemi_tornado_init,
1588                 .setup          = pci_default_setup,
1589         },
1590         {
1591                 .vendor         = PCI_VENDOR_ID_INTEL,
1592                 .device         = 0x8811,
1593                 .init           = pci_eg20t_init,
1594                 .setup          = pci_default_setup,
1595         },
1596         {
1597                 .vendor         = PCI_VENDOR_ID_INTEL,
1598                 .device         = 0x8812,
1599                 .init           = pci_eg20t_init,
1600                 .setup          = pci_default_setup,
1601         },
1602         {
1603                 .vendor         = PCI_VENDOR_ID_INTEL,
1604                 .device         = 0x8813,
1605                 .init           = pci_eg20t_init,
1606                 .setup          = pci_default_setup,
1607         },
1608         {
1609                 .vendor         = PCI_VENDOR_ID_INTEL,
1610                 .device         = 0x8814,
1611                 .init           = pci_eg20t_init,
1612                 .setup          = pci_default_setup,
1613         },
1614         {
1615                 .vendor         = 0x10DB,
1616                 .device         = 0x8027,
1617                 .init           = pci_eg20t_init,
1618                 .setup          = pci_default_setup,
1619         },
1620         {
1621                 .vendor         = 0x10DB,
1622                 .device         = 0x8028,
1623                 .init           = pci_eg20t_init,
1624                 .setup          = pci_default_setup,
1625         },
1626         {
1627                 .vendor         = 0x10DB,
1628                 .device         = 0x8029,
1629                 .init           = pci_eg20t_init,
1630                 .setup          = pci_default_setup,
1631         },
1632         {
1633                 .vendor         = 0x10DB,
1634                 .device         = 0x800C,
1635                 .init           = pci_eg20t_init,
1636                 .setup          = pci_default_setup,
1637         },
1638         {
1639                 .vendor         = 0x10DB,
1640                 .device         = 0x800D,
1641                 .init           = pci_eg20t_init,
1642                 .setup          = pci_default_setup,
1643         },
1644         /*
1645          * Cronyx Omega PCI (PLX-chip based)
1646          */
1647         {
1648                 .vendor         = PCI_VENDOR_ID_PLX,
1649                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1650                 .subvendor      = PCI_ANY_ID,
1651                 .subdevice      = PCI_ANY_ID,
1652                 .setup          = pci_omegapci_setup,
1653          },
1654         /*
1655          * Default "match everything" terminator entry
1656          */
1657         {
1658                 .vendor         = PCI_ANY_ID,
1659                 .device         = PCI_ANY_ID,
1660                 .subvendor      = PCI_ANY_ID,
1661                 .subdevice      = PCI_ANY_ID,
1662                 .setup          = pci_default_setup,
1663         }
1664 };
1665
1666 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1667 {
1668         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1669 }
1670
1671 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1672 {
1673         struct pci_serial_quirk *quirk;
1674
1675         for (quirk = pci_serial_quirks; ; quirk++)
1676                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1677                     quirk_id_matches(quirk->device, dev->device) &&
1678                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1679                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1680                         break;
1681         return quirk;
1682 }
1683
1684 static inline int get_pci_irq(struct pci_dev *dev,
1685                                 const struct pciserial_board *board)
1686 {
1687         if (board->flags & FL_NOIRQ)
1688                 return 0;
1689         else
1690                 return dev->irq;
1691 }
1692
1693 /*
1694  * This is the configuration table for all of the PCI serial boards
1695  * which we support.  It is directly indexed by the pci_board_num_t enum
1696  * value, which is encoded in the pci_device_id PCI probe table's
1697  * driver_data member.
1698  *
1699  * The makeup of these names are:
1700  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1701  *
1702  *  bn          = PCI BAR number
1703  *  bt          = Index using PCI BARs
1704  *  n           = number of serial ports
1705  *  baud        = baud rate
1706  *  offsetinhex = offset for each sequential port (in hex)
1707  *
1708  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1709  *
1710  * Please note: in theory if n = 1, _bt infix should make no difference.
1711  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1712  */
1713 enum pci_board_num_t {
1714         pbn_default = 0,
1715
1716         pbn_b0_1_115200,
1717         pbn_b0_2_115200,
1718         pbn_b0_4_115200,
1719         pbn_b0_5_115200,
1720         pbn_b0_8_115200,
1721
1722         pbn_b0_1_921600,
1723         pbn_b0_2_921600,
1724         pbn_b0_4_921600,
1725
1726         pbn_b0_2_1130000,
1727
1728         pbn_b0_4_1152000,
1729
1730         pbn_b0_2_1843200,
1731         pbn_b0_4_1843200,
1732
1733         pbn_b0_2_1843200_200,
1734         pbn_b0_4_1843200_200,
1735         pbn_b0_8_1843200_200,
1736
1737         pbn_b0_1_4000000,
1738
1739         pbn_b0_bt_1_115200,
1740         pbn_b0_bt_2_115200,
1741         pbn_b0_bt_4_115200,
1742         pbn_b0_bt_8_115200,
1743
1744         pbn_b0_bt_1_460800,
1745         pbn_b0_bt_2_460800,
1746         pbn_b0_bt_4_460800,
1747
1748         pbn_b0_bt_1_921600,
1749         pbn_b0_bt_2_921600,
1750         pbn_b0_bt_4_921600,
1751         pbn_b0_bt_8_921600,
1752
1753         pbn_b1_1_115200,
1754         pbn_b1_2_115200,
1755         pbn_b1_4_115200,
1756         pbn_b1_8_115200,
1757         pbn_b1_16_115200,
1758
1759         pbn_b1_1_921600,
1760         pbn_b1_2_921600,
1761         pbn_b1_4_921600,
1762         pbn_b1_8_921600,
1763
1764         pbn_b1_2_1250000,
1765
1766         pbn_b1_bt_1_115200,
1767         pbn_b1_bt_2_115200,
1768         pbn_b1_bt_4_115200,
1769
1770         pbn_b1_bt_2_921600,
1771
1772         pbn_b1_1_1382400,
1773         pbn_b1_2_1382400,
1774         pbn_b1_4_1382400,
1775         pbn_b1_8_1382400,
1776
1777         pbn_b2_1_115200,
1778         pbn_b2_2_115200,
1779         pbn_b2_4_115200,
1780         pbn_b2_8_115200,
1781
1782         pbn_b2_1_460800,
1783         pbn_b2_4_460800,
1784         pbn_b2_8_460800,
1785         pbn_b2_16_460800,
1786
1787         pbn_b2_1_921600,
1788         pbn_b2_4_921600,
1789         pbn_b2_8_921600,
1790
1791         pbn_b2_8_1152000,
1792
1793         pbn_b2_bt_1_115200,
1794         pbn_b2_bt_2_115200,
1795         pbn_b2_bt_4_115200,
1796
1797         pbn_b2_bt_2_921600,
1798         pbn_b2_bt_4_921600,
1799
1800         pbn_b3_2_115200,
1801         pbn_b3_4_115200,
1802         pbn_b3_8_115200,
1803
1804         pbn_b4_bt_2_921600,
1805         pbn_b4_bt_4_921600,
1806         pbn_b4_bt_8_921600,
1807
1808         /*
1809          * Board-specific versions.
1810          */
1811         pbn_panacom,
1812         pbn_panacom2,
1813         pbn_panacom4,
1814         pbn_exsys_4055,
1815         pbn_plx_romulus,
1816         pbn_oxsemi,
1817         pbn_oxsemi_1_4000000,
1818         pbn_oxsemi_2_4000000,
1819         pbn_oxsemi_4_4000000,
1820         pbn_oxsemi_8_4000000,
1821         pbn_intel_i960,
1822         pbn_sgi_ioc3,
1823         pbn_computone_4,
1824         pbn_computone_6,
1825         pbn_computone_8,
1826         pbn_sbsxrsio,
1827         pbn_exar_XR17C152,
1828         pbn_exar_XR17C154,
1829         pbn_exar_XR17C158,
1830         pbn_exar_ibm_saturn,
1831         pbn_pasemi_1682M,
1832         pbn_ni8430_2,
1833         pbn_ni8430_4,
1834         pbn_ni8430_8,
1835         pbn_ni8430_16,
1836         pbn_ADDIDATA_PCIe_1_3906250,
1837         pbn_ADDIDATA_PCIe_2_3906250,
1838         pbn_ADDIDATA_PCIe_4_3906250,
1839         pbn_ADDIDATA_PCIe_8_3906250,
1840         pbn_ce4100_1_115200,
1841         pbn_omegapci,
1842         pbn_NETMOS9900_2s_115200,
1843 };
1844
1845 /*
1846  * uart_offset - the space between channels
1847  * reg_shift   - describes how the UART registers are mapped
1848  *               to PCI memory by the card.
1849  * For example IER register on SBS, Inc. PMC-OctPro is located at
1850  * offset 0x10 from the UART base, while UART_IER is defined as 1
1851  * in include/linux/serial_reg.h,
1852  * see first lines of serial_in() and serial_out() in 8250.c
1853 */
1854
1855 static struct pciserial_board pci_boards[] __devinitdata = {
1856         [pbn_default] = {
1857                 .flags          = FL_BASE0,
1858                 .num_ports      = 1,
1859                 .base_baud      = 115200,
1860                 .uart_offset    = 8,
1861         },
1862         [pbn_b0_1_115200] = {
1863                 .flags          = FL_BASE0,
1864                 .num_ports      = 1,
1865                 .base_baud      = 115200,
1866                 .uart_offset    = 8,
1867         },
1868         [pbn_b0_2_115200] = {
1869                 .flags          = FL_BASE0,
1870                 .num_ports      = 2,
1871                 .base_baud      = 115200,
1872                 .uart_offset    = 8,
1873         },
1874         [pbn_b0_4_115200] = {
1875                 .flags          = FL_BASE0,
1876                 .num_ports      = 4,
1877                 .base_baud      = 115200,
1878                 .uart_offset    = 8,
1879         },
1880         [pbn_b0_5_115200] = {
1881                 .flags          = FL_BASE0,
1882                 .num_ports      = 5,
1883                 .base_baud      = 115200,
1884                 .uart_offset    = 8,
1885         },
1886         [pbn_b0_8_115200] = {
1887                 .flags          = FL_BASE0,
1888                 .num_ports      = 8,
1889                 .base_baud      = 115200,
1890                 .uart_offset    = 8,
1891         },
1892         [pbn_b0_1_921600] = {
1893                 .flags          = FL_BASE0,
1894                 .num_ports      = 1,
1895                 .base_baud      = 921600,
1896                 .uart_offset    = 8,
1897         },
1898         [pbn_b0_2_921600] = {
1899                 .flags          = FL_BASE0,
1900                 .num_ports      = 2,
1901                 .base_baud      = 921600,
1902                 .uart_offset    = 8,
1903         },
1904         [pbn_b0_4_921600] = {
1905                 .flags          = FL_BASE0,
1906                 .num_ports      = 4,
1907                 .base_baud      = 921600,
1908                 .uart_offset    = 8,
1909         },
1910
1911         [pbn_b0_2_1130000] = {
1912                 .flags          = FL_BASE0,
1913                 .num_ports      = 2,
1914                 .base_baud      = 1130000,
1915                 .uart_offset    = 8,
1916         },
1917
1918         [pbn_b0_4_1152000] = {
1919                 .flags          = FL_BASE0,
1920                 .num_ports      = 4,
1921                 .base_baud      = 1152000,
1922                 .uart_offset    = 8,
1923         },
1924
1925         [pbn_b0_2_1843200] = {
1926                 .flags          = FL_BASE0,
1927                 .num_ports      = 2,
1928                 .base_baud      = 1843200,
1929                 .uart_offset    = 8,
1930         },
1931         [pbn_b0_4_1843200] = {
1932                 .flags          = FL_BASE0,
1933                 .num_ports      = 4,
1934                 .base_baud      = 1843200,
1935                 .uart_offset    = 8,
1936         },
1937
1938         [pbn_b0_2_1843200_200] = {
1939                 .flags          = FL_BASE0,
1940                 .num_ports      = 2,
1941                 .base_baud      = 1843200,
1942                 .uart_offset    = 0x200,
1943         },
1944         [pbn_b0_4_1843200_200] = {
1945                 .flags          = FL_BASE0,
1946                 .num_ports      = 4,
1947                 .base_baud      = 1843200,
1948                 .uart_offset    = 0x200,
1949         },
1950         [pbn_b0_8_1843200_200] = {
1951                 .flags          = FL_BASE0,
1952                 .num_ports      = 8,
1953                 .base_baud      = 1843200,
1954                 .uart_offset    = 0x200,
1955         },
1956         [pbn_b0_1_4000000] = {
1957                 .flags          = FL_BASE0,
1958                 .num_ports      = 1,
1959                 .base_baud      = 4000000,
1960                 .uart_offset    = 8,
1961         },
1962
1963         [pbn_b0_bt_1_115200] = {
1964                 .flags          = FL_BASE0|FL_BASE_BARS,
1965                 .num_ports      = 1,
1966                 .base_baud      = 115200,
1967                 .uart_offset    = 8,
1968         },
1969         [pbn_b0_bt_2_115200] = {
1970                 .flags          = FL_BASE0|FL_BASE_BARS,
1971                 .num_ports      = 2,
1972                 .base_baud      = 115200,
1973                 .uart_offset    = 8,
1974         },
1975         [pbn_b0_bt_4_115200] = {
1976                 .flags          = FL_BASE0|FL_BASE_BARS,
1977                 .num_ports      = 4,
1978                 .base_baud      = 115200,
1979                 .uart_offset    = 8,
1980         },
1981         [pbn_b0_bt_8_115200] = {
1982                 .flags          = FL_BASE0|FL_BASE_BARS,
1983                 .num_ports      = 8,
1984                 .base_baud      = 115200,
1985                 .uart_offset    = 8,
1986         },
1987
1988         [pbn_b0_bt_1_460800] = {
1989                 .flags          = FL_BASE0|FL_BASE_BARS,
1990                 .num_ports      = 1,
1991                 .base_baud      = 460800,
1992                 .uart_offset    = 8,
1993         },
1994         [pbn_b0_bt_2_460800] = {
1995                 .flags          = FL_BASE0|FL_BASE_BARS,
1996                 .num_ports      = 2,
1997                 .base_baud      = 460800,
1998                 .uart_offset    = 8,
1999         },
2000         [pbn_b0_bt_4_460800] = {
2001                 .flags          = FL_BASE0|FL_BASE_BARS,
2002                 .num_ports      = 4,
2003                 .base_baud      = 460800,
2004                 .uart_offset    = 8,
2005         },
2006
2007         [pbn_b0_bt_1_921600] = {
2008                 .flags          = FL_BASE0|FL_BASE_BARS,
2009                 .num_ports      = 1,
2010                 .base_baud      = 921600,
2011                 .uart_offset    = 8,
2012         },
2013         [pbn_b0_bt_2_921600] = {
2014                 .flags          = FL_BASE0|FL_BASE_BARS,
2015                 .num_ports      = 2,
2016                 .base_baud      = 921600,
2017                 .uart_offset    = 8,
2018         },
2019         [pbn_b0_bt_4_921600] = {
2020                 .flags          = FL_BASE0|FL_BASE_BARS,
2021                 .num_ports      = 4,
2022                 .base_baud      = 921600,
2023                 .uart_offset    = 8,
2024         },
2025         [pbn_b0_bt_8_921600] = {
2026                 .flags          = FL_BASE0|FL_BASE_BARS,
2027                 .num_ports      = 8,
2028                 .base_baud      = 921600,
2029                 .uart_offset    = 8,
2030         },
2031
2032         [pbn_b1_1_115200] = {
2033                 .flags          = FL_BASE1,
2034                 .num_ports      = 1,
2035                 .base_baud      = 115200,
2036                 .uart_offset    = 8,
2037         },
2038         [pbn_b1_2_115200] = {
2039                 .flags          = FL_BASE1,
2040                 .num_ports      = 2,
2041                 .base_baud      = 115200,
2042                 .uart_offset    = 8,
2043         },
2044         [pbn_b1_4_115200] = {
2045                 .flags          = FL_BASE1,
2046                 .num_ports      = 4,
2047                 .base_baud      = 115200,
2048                 .uart_offset    = 8,
2049         },
2050         [pbn_b1_8_115200] = {
2051                 .flags          = FL_BASE1,
2052                 .num_ports      = 8,
2053                 .base_baud      = 115200,
2054                 .uart_offset    = 8,
2055         },
2056         [pbn_b1_16_115200] = {
2057                 .flags          = FL_BASE1,
2058                 .num_ports      = 16,
2059                 .base_baud      = 115200,
2060                 .uart_offset    = 8,
2061         },
2062
2063         [pbn_b1_1_921600] = {
2064                 .flags          = FL_BASE1,
2065                 .num_ports      = 1,
2066                 .base_baud      = 921600,
2067                 .uart_offset    = 8,
2068         },
2069         [pbn_b1_2_921600] = {
2070                 .flags          = FL_BASE1,
2071                 .num_ports      = 2,
2072                 .base_baud      = 921600,
2073                 .uart_offset    = 8,
2074         },
2075         [pbn_b1_4_921600] = {
2076                 .flags          = FL_BASE1,
2077                 .num_ports      = 4,
2078                 .base_baud      = 921600,
2079                 .uart_offset    = 8,
2080         },
2081         [pbn_b1_8_921600] = {
2082                 .flags          = FL_BASE1,
2083                 .num_ports      = 8,
2084                 .base_baud      = 921600,
2085                 .uart_offset    = 8,
2086         },
2087         [pbn_b1_2_1250000] = {
2088                 .flags          = FL_BASE1,
2089                 .num_ports      = 2,
2090                 .base_baud      = 1250000,
2091                 .uart_offset    = 8,
2092         },
2093
2094         [pbn_b1_bt_1_115200] = {
2095                 .flags          = FL_BASE1|FL_BASE_BARS,
2096                 .num_ports      = 1,
2097                 .base_baud      = 115200,
2098                 .uart_offset    = 8,
2099         },
2100         [pbn_b1_bt_2_115200] = {
2101                 .flags          = FL_BASE1|FL_BASE_BARS,
2102                 .num_ports      = 2,
2103                 .base_baud      = 115200,
2104                 .uart_offset    = 8,
2105         },
2106         [pbn_b1_bt_4_115200] = {
2107                 .flags          = FL_BASE1|FL_BASE_BARS,
2108                 .num_ports      = 4,
2109                 .base_baud      = 115200,
2110                 .uart_offset    = 8,
2111         },
2112
2113         [pbn_b1_bt_2_921600] = {
2114                 .flags          = FL_BASE1|FL_BASE_BARS,
2115                 .num_ports      = 2,
2116                 .base_baud      = 921600,
2117                 .uart_offset    = 8,
2118         },
2119
2120         [pbn_b1_1_1382400] = {
2121                 .flags          = FL_BASE1,
2122                 .num_ports      = 1,
2123                 .base_baud      = 1382400,
2124                 .uart_offset    = 8,
2125         },
2126         [pbn_b1_2_1382400] = {
2127                 .flags          = FL_BASE1,
2128                 .num_ports      = 2,
2129                 .base_baud      = 1382400,
2130                 .uart_offset    = 8,
2131         },
2132         [pbn_b1_4_1382400] = {
2133                 .flags          = FL_BASE1,
2134                 .num_ports      = 4,
2135                 .base_baud      = 1382400,
2136                 .uart_offset    = 8,
2137         },
2138         [pbn_b1_8_1382400] = {
2139                 .flags          = FL_BASE1,
2140                 .num_ports      = 8,
2141                 .base_baud      = 1382400,
2142                 .uart_offset    = 8,
2143         },
2144
2145         [pbn_b2_1_115200] = {
2146                 .flags          = FL_BASE2,
2147                 .num_ports      = 1,
2148                 .base_baud      = 115200,
2149                 .uart_offset    = 8,
2150         },
2151         [pbn_b2_2_115200] = {
2152                 .flags          = FL_BASE2,
2153                 .num_ports      = 2,
2154                 .base_baud      = 115200,
2155                 .uart_offset    = 8,
2156         },
2157         [pbn_b2_4_115200] = {
2158                 .flags          = FL_BASE2,
2159                 .num_ports      = 4,
2160                 .base_baud      = 115200,
2161                 .uart_offset    = 8,
2162         },
2163         [pbn_b2_8_115200] = {
2164                 .flags          = FL_BASE2,
2165                 .num_ports      = 8,
2166                 .base_baud      = 115200,
2167                 .uart_offset    = 8,
2168         },
2169
2170         [pbn_b2_1_460800] = {
2171                 .flags          = FL_BASE2,
2172                 .num_ports      = 1,
2173                 .base_baud      = 460800,
2174                 .uart_offset    = 8,
2175         },
2176         [pbn_b2_4_460800] = {
2177                 .flags          = FL_BASE2,
2178                 .num_ports      = 4,
2179                 .base_baud      = 460800,
2180                 .uart_offset    = 8,
2181         },
2182         [pbn_b2_8_460800] = {
2183                 .flags          = FL_BASE2,
2184                 .num_ports      = 8,
2185                 .base_baud      = 460800,
2186                 .uart_offset    = 8,
2187         },
2188         [pbn_b2_16_460800] = {
2189                 .flags          = FL_BASE2,
2190                 .num_ports      = 16,
2191                 .base_baud      = 460800,
2192                 .uart_offset    = 8,
2193          },
2194
2195         [pbn_b2_1_921600] = {
2196                 .flags          = FL_BASE2,
2197                 .num_ports      = 1,
2198                 .base_baud      = 921600,
2199                 .uart_offset    = 8,
2200         },
2201         [pbn_b2_4_921600] = {
2202                 .flags          = FL_BASE2,
2203                 .num_ports      = 4,
2204                 .base_baud      = 921600,
2205                 .uart_offset    = 8,
2206         },
2207         [pbn_b2_8_921600] = {
2208                 .flags          = FL_BASE2,
2209                 .num_ports      = 8,
2210                 .base_baud      = 921600,
2211                 .uart_offset    = 8,
2212         },
2213
2214         [pbn_b2_8_1152000] = {
2215                 .flags          = FL_BASE2,
2216                 .num_ports      = 8,
2217                 .base_baud      = 1152000,
2218                 .uart_offset    = 8,
2219         },
2220
2221         [pbn_b2_bt_1_115200] = {
2222                 .flags          = FL_BASE2|FL_BASE_BARS,
2223                 .num_ports      = 1,
2224                 .base_baud      = 115200,
2225                 .uart_offset    = 8,
2226         },
2227         [pbn_b2_bt_2_115200] = {
2228                 .flags          = FL_BASE2|FL_BASE_BARS,
2229                 .num_ports      = 2,
2230                 .base_baud      = 115200,
2231                 .uart_offset    = 8,
2232         },
2233         [pbn_b2_bt_4_115200] = {
2234                 .flags          = FL_BASE2|FL_BASE_BARS,
2235                 .num_ports      = 4,
2236                 .base_baud      = 115200,
2237                 .uart_offset    = 8,
2238         },
2239
2240         [pbn_b2_bt_2_921600] = {
2241                 .flags          = FL_BASE2|FL_BASE_BARS,
2242                 .num_ports      = 2,
2243                 .base_baud      = 921600,
2244                 .uart_offset    = 8,
2245         },
2246         [pbn_b2_bt_4_921600] = {
2247                 .flags          = FL_BASE2|FL_BASE_BARS,
2248                 .num_ports      = 4,
2249                 .base_baud      = 921600,
2250                 .uart_offset    = 8,
2251         },
2252
2253         [pbn_b3_2_115200] = {
2254                 .flags          = FL_BASE3,
2255                 .num_ports      = 2,
2256                 .base_baud      = 115200,
2257                 .uart_offset    = 8,
2258         },
2259         [pbn_b3_4_115200] = {
2260                 .flags          = FL_BASE3,
2261                 .num_ports      = 4,
2262                 .base_baud      = 115200,
2263                 .uart_offset    = 8,
2264         },
2265         [pbn_b3_8_115200] = {
2266                 .flags          = FL_BASE3,
2267                 .num_ports      = 8,
2268                 .base_baud      = 115200,
2269                 .uart_offset    = 8,
2270         },
2271
2272         [pbn_b4_bt_2_921600] = {
2273                 .flags          = FL_BASE4,
2274                 .num_ports      = 2,
2275                 .base_baud      = 921600,
2276                 .uart_offset    = 8,
2277         },
2278         [pbn_b4_bt_4_921600] = {
2279                 .flags          = FL_BASE4,
2280                 .num_ports      = 4,
2281                 .base_baud      = 921600,
2282                 .uart_offset    = 8,
2283         },
2284         [pbn_b4_bt_8_921600] = {
2285                 .flags          = FL_BASE4,
2286                 .num_ports      = 8,
2287                 .base_baud      = 921600,
2288                 .uart_offset    = 8,
2289         },
2290
2291         /*
2292          * Entries following this are board-specific.
2293          */
2294
2295         /*
2296          * Panacom - IOMEM
2297          */
2298         [pbn_panacom] = {
2299                 .flags          = FL_BASE2,
2300                 .num_ports      = 2,
2301                 .base_baud      = 921600,
2302                 .uart_offset    = 0x400,
2303                 .reg_shift      = 7,
2304         },
2305         [pbn_panacom2] = {
2306                 .flags          = FL_BASE2|FL_BASE_BARS,
2307                 .num_ports      = 2,
2308                 .base_baud      = 921600,
2309                 .uart_offset    = 0x400,
2310                 .reg_shift      = 7,
2311         },
2312         [pbn_panacom4] = {
2313                 .flags          = FL_BASE2|FL_BASE_BARS,
2314                 .num_ports      = 4,
2315                 .base_baud      = 921600,
2316                 .uart_offset    = 0x400,
2317                 .reg_shift      = 7,
2318         },
2319
2320         [pbn_exsys_4055] = {
2321                 .flags          = FL_BASE2,
2322                 .num_ports      = 4,
2323                 .base_baud      = 115200,
2324                 .uart_offset    = 8,
2325         },
2326
2327         /* I think this entry is broken - the first_offset looks wrong --rmk */
2328         [pbn_plx_romulus] = {
2329                 .flags          = FL_BASE2,
2330                 .num_ports      = 4,
2331                 .base_baud      = 921600,
2332                 .uart_offset    = 8 << 2,
2333                 .reg_shift      = 2,
2334                 .first_offset   = 0x03,
2335         },
2336
2337         /*
2338          * This board uses the size of PCI Base region 0 to
2339          * signal now many ports are available
2340          */
2341         [pbn_oxsemi] = {
2342                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2343                 .num_ports      = 32,
2344                 .base_baud      = 115200,
2345                 .uart_offset    = 8,
2346         },
2347         [pbn_oxsemi_1_4000000] = {
2348                 .flags          = FL_BASE0,
2349                 .num_ports      = 1,
2350                 .base_baud      = 4000000,
2351                 .uart_offset    = 0x200,
2352                 .first_offset   = 0x1000,
2353         },
2354         [pbn_oxsemi_2_4000000] = {
2355                 .flags          = FL_BASE0,
2356                 .num_ports      = 2,
2357                 .base_baud      = 4000000,
2358                 .uart_offset    = 0x200,
2359                 .first_offset   = 0x1000,
2360         },
2361         [pbn_oxsemi_4_4000000] = {
2362                 .flags          = FL_BASE0,
2363                 .num_ports      = 4,
2364                 .base_baud      = 4000000,
2365                 .uart_offset    = 0x200,
2366                 .first_offset   = 0x1000,
2367         },
2368         [pbn_oxsemi_8_4000000] = {
2369                 .flags          = FL_BASE0,
2370                 .num_ports      = 8,
2371                 .base_baud      = 4000000,
2372                 .uart_offset    = 0x200,
2373                 .first_offset   = 0x1000,
2374         },
2375
2376
2377         /*
2378          * EKF addition for i960 Boards form EKF with serial port.
2379          * Max 256 ports.
2380          */
2381         [pbn_intel_i960] = {
2382                 .flags          = FL_BASE0,
2383                 .num_ports      = 32,
2384                 .base_baud      = 921600,
2385                 .uart_offset    = 8 << 2,
2386                 .reg_shift      = 2,
2387                 .first_offset   = 0x10000,
2388         },
2389         [pbn_sgi_ioc3] = {
2390                 .flags          = FL_BASE0|FL_NOIRQ,
2391                 .num_ports      = 1,
2392                 .base_baud      = 458333,
2393                 .uart_offset    = 8,
2394                 .reg_shift      = 0,
2395                 .first_offset   = 0x20178,
2396         },
2397
2398         /*
2399          * Computone - uses IOMEM.
2400          */
2401         [pbn_computone_4] = {
2402                 .flags          = FL_BASE0,
2403                 .num_ports      = 4,
2404                 .base_baud      = 921600,
2405                 .uart_offset    = 0x40,
2406                 .reg_shift      = 2,
2407                 .first_offset   = 0x200,
2408         },
2409         [pbn_computone_6] = {
2410                 .flags          = FL_BASE0,
2411                 .num_ports      = 6,
2412                 .base_baud      = 921600,
2413                 .uart_offset    = 0x40,
2414                 .reg_shift      = 2,
2415                 .first_offset   = 0x200,
2416         },
2417         [pbn_computone_8] = {
2418                 .flags          = FL_BASE0,
2419                 .num_ports      = 8,
2420                 .base_baud      = 921600,
2421                 .uart_offset    = 0x40,
2422                 .reg_shift      = 2,
2423                 .first_offset   = 0x200,
2424         },
2425         [pbn_sbsxrsio] = {
2426                 .flags          = FL_BASE0,
2427                 .num_ports      = 8,
2428                 .base_baud      = 460800,
2429                 .uart_offset    = 256,
2430                 .reg_shift      = 4,
2431         },
2432         /*
2433          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2434          *  Only basic 16550A support.
2435          *  XR17C15[24] are not tested, but they should work.
2436          */
2437         [pbn_exar_XR17C152] = {
2438                 .flags          = FL_BASE0,
2439                 .num_ports      = 2,
2440                 .base_baud      = 921600,
2441                 .uart_offset    = 0x200,
2442         },
2443         [pbn_exar_XR17C154] = {
2444                 .flags          = FL_BASE0,
2445                 .num_ports      = 4,
2446                 .base_baud      = 921600,
2447                 .uart_offset    = 0x200,
2448         },
2449         [pbn_exar_XR17C158] = {
2450                 .flags          = FL_BASE0,
2451                 .num_ports      = 8,
2452                 .base_baud      = 921600,
2453                 .uart_offset    = 0x200,
2454         },
2455         [pbn_exar_ibm_saturn] = {
2456                 .flags          = FL_BASE0,
2457                 .num_ports      = 1,
2458                 .base_baud      = 921600,
2459                 .uart_offset    = 0x200,
2460         },
2461
2462         /*
2463          * PA Semi PWRficient PA6T-1682M on-chip UART
2464          */
2465         [pbn_pasemi_1682M] = {
2466                 .flags          = FL_BASE0,
2467                 .num_ports      = 1,
2468                 .base_baud      = 8333333,
2469         },
2470         /*
2471          * National Instruments 843x
2472          */
2473         [pbn_ni8430_16] = {
2474                 .flags          = FL_BASE0,
2475                 .num_ports      = 16,
2476                 .base_baud      = 3686400,
2477                 .uart_offset    = 0x10,
2478                 .first_offset   = 0x800,
2479         },
2480         [pbn_ni8430_8] = {
2481                 .flags          = FL_BASE0,
2482                 .num_ports      = 8,
2483                 .base_baud      = 3686400,
2484                 .uart_offset    = 0x10,
2485                 .first_offset   = 0x800,
2486         },
2487         [pbn_ni8430_4] = {
2488                 .flags          = FL_BASE0,
2489                 .num_ports      = 4,
2490                 .base_baud      = 3686400,
2491                 .uart_offset    = 0x10,
2492                 .first_offset   = 0x800,
2493         },
2494         [pbn_ni8430_2] = {
2495                 .flags          = FL_BASE0,
2496                 .num_ports      = 2,
2497                 .base_baud      = 3686400,
2498                 .uart_offset    = 0x10,
2499                 .first_offset   = 0x800,
2500         },
2501         /*
2502          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2503          */
2504         [pbn_ADDIDATA_PCIe_1_3906250] = {
2505                 .flags          = FL_BASE0,
2506                 .num_ports      = 1,
2507                 .base_baud      = 3906250,
2508                 .uart_offset    = 0x200,
2509                 .first_offset   = 0x1000,
2510         },
2511         [pbn_ADDIDATA_PCIe_2_3906250] = {
2512                 .flags          = FL_BASE0,
2513                 .num_ports      = 2,
2514                 .base_baud      = 3906250,
2515                 .uart_offset    = 0x200,
2516                 .first_offset   = 0x1000,
2517         },
2518         [pbn_ADDIDATA_PCIe_4_3906250] = {
2519                 .flags          = FL_BASE0,
2520                 .num_ports      = 4,
2521                 .base_baud      = 3906250,
2522                 .uart_offset    = 0x200,
2523                 .first_offset   = 0x1000,
2524         },
2525         [pbn_ADDIDATA_PCIe_8_3906250] = {
2526                 .flags          = FL_BASE0,
2527                 .num_ports      = 8,
2528                 .base_baud      = 3906250,
2529                 .uart_offset    = 0x200,
2530                 .first_offset   = 0x1000,
2531         },
2532         [pbn_ce4100_1_115200] = {
2533                 .flags          = FL_BASE0,
2534                 .num_ports      = 1,
2535                 .base_baud      = 921600,
2536                 .reg_shift      = 2,
2537         },
2538         [pbn_omegapci] = {
2539                 .flags          = FL_BASE0,
2540                 .num_ports      = 8,
2541                 .base_baud      = 115200,
2542                 .uart_offset    = 0x200,
2543         },
2544         [pbn_NETMOS9900_2s_115200] = {
2545                 .flags          = FL_BASE0,
2546                 .num_ports      = 2,
2547                 .base_baud      = 115200,
2548         },
2549 };
2550
2551 static const struct pci_device_id softmodem_blacklist[] = {
2552         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2553         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2554         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2555 };
2556
2557 /*
2558  * Given a complete unknown PCI device, try to use some heuristics to
2559  * guess what the configuration might be, based on the pitiful PCI
2560  * serial specs.  Returns 0 on success, 1 on failure.
2561  */
2562 static int __devinit
2563 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2564 {
2565         const struct pci_device_id *blacklist;
2566         int num_iomem, num_port, first_port = -1, i;
2567
2568         /*
2569          * If it is not a communications device or the programming
2570          * interface is greater than 6, give up.
2571          *
2572          * (Should we try to make guesses for multiport serial devices
2573          * later?)
2574          */
2575         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2576              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2577             (dev->class & 0xff) > 6)
2578                 return -ENODEV;
2579
2580         /*
2581          * Do not access blacklisted devices that are known not to
2582          * feature serial ports.
2583          */
2584         for (blacklist = softmodem_blacklist;
2585              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2586              blacklist++) {
2587                 if (dev->vendor == blacklist->vendor &&
2588                     dev->device == blacklist->device)
2589                         return -ENODEV;
2590         }
2591
2592         num_iomem = num_port = 0;
2593         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2594                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2595                         num_port++;
2596                         if (first_port == -1)
2597                                 first_port = i;
2598                 }
2599                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2600                         num_iomem++;
2601         }
2602
2603         /*
2604          * If there is 1 or 0 iomem regions, and exactly one port,
2605          * use it.  We guess the number of ports based on the IO
2606          * region size.
2607          */
2608         if (num_iomem <= 1 && num_port == 1) {
2609                 board->flags = first_port;
2610                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2611                 return 0;
2612         }
2613
2614         /*
2615          * Now guess if we've got a board which indexes by BARs.
2616          * Each IO BAR should be 8 bytes, and they should follow
2617          * consecutively.
2618          */
2619         first_port = -1;
2620         num_port = 0;
2621         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2622                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2623                     pci_resource_len(dev, i) == 8 &&
2624                     (first_port == -1 || (first_port + num_port) == i)) {
2625                         num_port++;
2626                         if (first_port == -1)
2627                                 first_port = i;
2628                 }
2629         }
2630
2631         if (num_port > 1) {
2632                 board->flags = first_port | FL_BASE_BARS;
2633                 board->num_ports = num_port;
2634                 return 0;
2635         }
2636
2637         return -ENODEV;
2638 }
2639
2640 static inline int
2641 serial_pci_matches(const struct pciserial_board *board,
2642                    const struct pciserial_board *guessed)
2643 {
2644         return
2645             board->num_ports == guessed->num_ports &&
2646             board->base_baud == guessed->base_baud &&
2647             board->uart_offset == guessed->uart_offset &&
2648             board->reg_shift == guessed->reg_shift &&
2649             board->first_offset == guessed->first_offset;
2650 }
2651
2652 struct serial_private *
2653 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2654 {
2655         struct uart_port serial_port;
2656         struct serial_private *priv;
2657         struct pci_serial_quirk *quirk;
2658         int rc, nr_ports, i;
2659
2660         nr_ports = board->num_ports;
2661
2662         /*
2663          * Find an init and setup quirks.
2664          */
2665         quirk = find_quirk(dev);
2666
2667         /*
2668          * Run the new-style initialization function.
2669          * The initialization function returns:
2670          *  <0  - error
2671          *   0  - use board->num_ports
2672          *  >0  - number of ports
2673          */
2674         if (quirk->init) {
2675                 rc = quirk->init(dev);
2676                 if (rc < 0) {
2677                         priv = ERR_PTR(rc);
2678                         goto err_out;
2679                 }
2680                 if (rc)
2681                         nr_ports = rc;
2682         }
2683
2684         priv = kzalloc(sizeof(struct serial_private) +
2685                        sizeof(unsigned int) * nr_ports,
2686                        GFP_KERNEL);
2687         if (!priv) {
2688                 priv = ERR_PTR(-ENOMEM);
2689                 goto err_deinit;
2690         }
2691
2692         priv->dev = dev;
2693         priv->quirk = quirk;
2694
2695         memset(&serial_port, 0, sizeof(struct uart_port));
2696         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2697         serial_port.uartclk = board->base_baud * 16;
2698         serial_port.irq = get_pci_irq(dev, board);
2699         serial_port.dev = &dev->dev;
2700
2701         for (i = 0; i < nr_ports; i++) {
2702                 if (quirk->setup(priv, board, &serial_port, i))
2703                         break;
2704
2705 #ifdef SERIAL_DEBUG_PCI
2706                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2707                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2708 #endif
2709
2710                 priv->line[i] = serial8250_register_port(&serial_port);
2711                 if (priv->line[i] < 0) {
2712                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2713                         break;
2714                 }
2715         }
2716         priv->nr = i;
2717         return priv;
2718
2719 err_deinit:
2720         if (quirk->exit)
2721                 quirk->exit(dev);
2722 err_out:
2723         return priv;
2724 }
2725 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2726
2727 void pciserial_remove_ports(struct serial_private *priv)
2728 {
2729         struct pci_serial_quirk *quirk;
2730         int i;
2731
2732         for (i = 0; i < priv->nr; i++)
2733                 serial8250_unregister_port(priv->line[i]);
2734
2735         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2736                 if (priv->remapped_bar[i])
2737                         iounmap(priv->remapped_bar[i]);
2738                 priv->remapped_bar[i] = NULL;
2739         }
2740
2741         /*
2742          * Find the exit quirks.
2743          */
2744         quirk = find_quirk(priv->dev);
2745         if (quirk->exit)
2746                 quirk->exit(priv->dev);
2747
2748         kfree(priv);
2749 }
2750 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2751
2752 void pciserial_suspend_ports(struct serial_private *priv)
2753 {
2754         int i;
2755
2756         for (i = 0; i < priv->nr; i++)
2757                 if (priv->line[i] >= 0)
2758                         serial8250_suspend_port(priv->line[i]);
2759 }
2760 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2761
2762 void pciserial_resume_ports(struct serial_private *priv)
2763 {
2764         int i;
2765
2766         /*
2767          * Ensure that the board is correctly configured.
2768          */
2769         if (priv->quirk->init)
2770                 priv->quirk->init(priv->dev);
2771
2772         for (i = 0; i < priv->nr; i++)
2773                 if (priv->line[i] >= 0)
2774                         serial8250_resume_port(priv->line[i]);
2775 }
2776 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2777
2778 /*
2779  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2780  * to the arrangement of serial ports on a PCI card.
2781  */
2782 static int __devinit
2783 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2784 {
2785         struct pci_serial_quirk *quirk;
2786         struct serial_private *priv;
2787         const struct pciserial_board *board;
2788         struct pciserial_board tmp;
2789         int rc;
2790
2791         quirk = find_quirk(dev);
2792         if (quirk->probe) {
2793                 rc = quirk->probe(dev);
2794                 if (rc)
2795                         return rc;
2796         }
2797
2798         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2799                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2800                         ent->driver_data);
2801                 return -EINVAL;
2802         }
2803
2804         board = &pci_boards[ent->driver_data];
2805
2806         rc = pci_enable_device(dev);
2807         pci_save_state(dev);
2808         if (rc)
2809                 return rc;
2810
2811         if (ent->driver_data == pbn_default) {
2812                 /*
2813                  * Use a copy of the pci_board entry for this;
2814                  * avoid changing entries in the table.
2815                  */
2816                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2817                 board = &tmp;
2818
2819                 /*
2820                  * We matched one of our class entries.  Try to
2821                  * determine the parameters of this board.
2822                  */
2823                 rc = serial_pci_guess_board(dev, &tmp);
2824                 if (rc)
2825                         goto disable;
2826         } else {
2827                 /*
2828                  * We matched an explicit entry.  If we are able to
2829                  * detect this boards settings with our heuristic,
2830                  * then we no longer need this entry.
2831                  */
2832                 memcpy(&tmp, &pci_boards[pbn_default],
2833                        sizeof(struct pciserial_board));
2834                 rc = serial_pci_guess_board(dev, &tmp);
2835                 if (rc == 0 && serial_pci_matches(board, &tmp))
2836                         moan_device("Redundant entry in serial pci_table.",
2837                                     dev);
2838         }
2839
2840         priv = pciserial_init_ports(dev, board);
2841         if (!IS_ERR(priv)) {
2842                 pci_set_drvdata(dev, priv);
2843                 return 0;
2844         }
2845
2846         rc = PTR_ERR(priv);
2847
2848  disable:
2849         pci_disable_device(dev);
2850         return rc;
2851 }
2852
2853 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2854 {
2855         struct serial_private *priv = pci_get_drvdata(dev);
2856
2857         pci_set_drvdata(dev, NULL);
2858
2859         pciserial_remove_ports(priv);
2860
2861         pci_disable_device(dev);
2862 }
2863
2864 #ifdef CONFIG_PM
2865 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2866 {
2867         struct serial_private *priv = pci_get_drvdata(dev);
2868
2869         if (priv)
2870                 pciserial_suspend_ports(priv);
2871
2872         pci_save_state(dev);
2873         pci_set_power_state(dev, pci_choose_state(dev, state));
2874         return 0;
2875 }
2876
2877 static int pciserial_resume_one(struct pci_dev *dev)
2878 {
2879         int err;
2880         struct serial_private *priv = pci_get_drvdata(dev);
2881
2882         pci_set_power_state(dev, PCI_D0);
2883         pci_restore_state(dev);
2884
2885         if (priv) {
2886                 /*
2887                  * The device may have been disabled.  Re-enable it.
2888                  */
2889                 err = pci_enable_device(dev);
2890                 /* FIXME: We cannot simply error out here */
2891                 if (err)
2892                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2893                 pciserial_resume_ports(priv);
2894         }
2895         return 0;
2896 }
2897 #endif
2898
2899 static struct pci_device_id serial_pci_tbl[] = {
2900         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2901         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2902                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2903                 pbn_b2_8_921600 },
2904         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2905                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2906                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2907                 pbn_b1_8_1382400 },
2908         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2909                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2910                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2911                 pbn_b1_4_1382400 },
2912         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2913                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2914                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2915                 pbn_b1_2_1382400 },
2916         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2917                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2918                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2919                 pbn_b1_8_1382400 },
2920         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2921                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2922                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2923                 pbn_b1_4_1382400 },
2924         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2925                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2926                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2927                 pbn_b1_2_1382400 },
2928         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2929                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2930                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2931                 pbn_b1_8_921600 },
2932         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2933                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2934                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2935                 pbn_b1_8_921600 },
2936         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2937                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2938                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2939                 pbn_b1_4_921600 },
2940         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2941                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2942                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2943                 pbn_b1_4_921600 },
2944         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2945                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2946                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2947                 pbn_b1_2_921600 },
2948         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2949                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2950                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2951                 pbn_b1_8_921600 },
2952         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2953                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2954                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2955                 pbn_b1_8_921600 },
2956         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2957                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2958                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2959                 pbn_b1_4_921600 },
2960         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2961                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2962                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2963                 pbn_b1_2_1250000 },
2964         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2965                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2966                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2967                 pbn_b0_2_1843200 },
2968         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2969                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2970                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2971                 pbn_b0_4_1843200 },
2972         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2973                 PCI_VENDOR_ID_AFAVLAB,
2974                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2975                 pbn_b0_4_1152000 },
2976         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2977                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2978                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2979                 pbn_b0_2_1843200_200 },
2980         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2981                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2982                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2983                 pbn_b0_4_1843200_200 },
2984         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2985                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2986                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2987                 pbn_b0_8_1843200_200 },
2988         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2989                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2990                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2991                 pbn_b0_2_1843200_200 },
2992         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2993                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2994                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2995                 pbn_b0_4_1843200_200 },
2996         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2997                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2998                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2999                 pbn_b0_8_1843200_200 },
3000         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3001                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3002                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3003                 pbn_b0_2_1843200_200 },
3004         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3005                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3006                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3007                 pbn_b0_4_1843200_200 },
3008         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3009                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3010                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3011                 pbn_b0_8_1843200_200 },
3012         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3013                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3014                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3015                 pbn_b0_2_1843200_200 },
3016         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3017                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3018                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3019                 pbn_b0_4_1843200_200 },
3020         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3021                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3022                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3023                 pbn_b0_8_1843200_200 },
3024         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3025                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3026                 0, 0, pbn_exar_ibm_saturn },
3027
3028         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3029                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3030                 pbn_b2_bt_1_115200 },
3031         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3032                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3033                 pbn_b2_bt_2_115200 },
3034         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3035                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3036                 pbn_b2_bt_4_115200 },
3037         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3038                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3039                 pbn_b2_bt_2_115200 },
3040         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3041                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3042                 pbn_b2_bt_4_115200 },
3043         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3045                 pbn_b2_8_115200 },
3046         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3047                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3048                 pbn_b2_8_460800 },
3049         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3050                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3051                 pbn_b2_8_115200 },
3052
3053         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3054                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3055                 pbn_b2_bt_2_115200 },
3056         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3057                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3058                 pbn_b2_bt_2_921600 },
3059         /*
3060          * VScom SPCOM800, from sl@s.pl
3061          */
3062         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3063                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3064                 pbn_b2_8_921600 },
3065         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3066                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3067                 pbn_b2_4_921600 },
3068         /* Unknown card - subdevice 0x1584 */
3069         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3070                 PCI_VENDOR_ID_PLX,
3071                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3072                 pbn_b0_4_115200 },
3073         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3074                 PCI_SUBVENDOR_ID_KEYSPAN,
3075                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3076                 pbn_panacom },
3077         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3078                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3079                 pbn_panacom4 },
3080         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3082                 pbn_panacom2 },
3083         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3084                 PCI_VENDOR_ID_ESDGMBH,
3085                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3086                 pbn_b2_4_115200 },
3087         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3088                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3089                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3090                 pbn_b2_4_460800 },
3091         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3092                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3093                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3094                 pbn_b2_8_460800 },
3095         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3096                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3097                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3098                 pbn_b2_16_460800 },
3099         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3100                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3101                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3102                 pbn_b2_16_460800 },
3103         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3104                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3105                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3106                 pbn_b2_4_460800 },
3107         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3108                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3109                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3110                 pbn_b2_8_460800 },
3111         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3112                 PCI_SUBVENDOR_ID_EXSYS,
3113                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3114                 pbn_exsys_4055 },
3115         /*
3116          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3117          * (Exoray@isys.ca)
3118          */
3119         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3120                 0x10b5, 0x106a, 0, 0,
3121                 pbn_plx_romulus },
3122         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3123                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124                 pbn_b1_4_115200 },
3125         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3126                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3127                 pbn_b1_2_115200 },
3128         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3130                 pbn_b1_8_115200 },
3131         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3132                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3133                 pbn_b1_8_115200 },
3134         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3135                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3136                 0, 0,
3137                 pbn_b0_4_921600 },
3138         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3139                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3140                 0, 0,
3141                 pbn_b0_4_1152000 },
3142         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3144                 pbn_b0_bt_2_921600 },
3145
3146                 /*
3147                  * The below card is a little controversial since it is the
3148                  * subject of a PCI vendor/device ID clash.  (See
3149                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3150                  * For now just used the hex ID 0x950a.
3151                  */
3152         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3153                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3154                 pbn_b0_2_115200 },
3155         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3157                 pbn_b0_2_1130000 },
3158         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3159                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3160                 pbn_b0_1_921600 },
3161         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3162                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163                 pbn_b0_4_115200 },
3164         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3165                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3166                 pbn_b0_bt_2_921600 },
3167         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3168                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3169                 pbn_b2_8_1152000 },
3170
3171         /*
3172          * Oxford Semiconductor Inc. Tornado PCI express device range.
3173          */
3174         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176                 pbn_b0_1_4000000 },
3177         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3179                 pbn_b0_1_4000000 },
3180         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3182                 pbn_oxsemi_1_4000000 },
3183         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3184                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3185                 pbn_oxsemi_1_4000000 },
3186         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3187                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3188                 pbn_b0_1_4000000 },
3189         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3190                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3191                 pbn_b0_1_4000000 },
3192         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3193                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3194                 pbn_oxsemi_1_4000000 },
3195         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3196                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3197                 pbn_oxsemi_1_4000000 },
3198         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3199                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3200                 pbn_b0_1_4000000 },
3201         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3202                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3203                 pbn_b0_1_4000000 },
3204         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206                 pbn_b0_1_4000000 },
3207         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3209                 pbn_b0_1_4000000 },
3210         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3211                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212                 pbn_oxsemi_2_4000000 },
3213         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3214                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215                 pbn_oxsemi_2_4000000 },
3216         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3217                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218                 pbn_oxsemi_4_4000000 },
3219         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3220                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221                 pbn_oxsemi_4_4000000 },
3222         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3223                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3224                 pbn_oxsemi_8_4000000 },
3225         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3226                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227                 pbn_oxsemi_8_4000000 },
3228         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230                 pbn_oxsemi_1_4000000 },
3231         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233                 pbn_oxsemi_1_4000000 },
3234         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236                 pbn_oxsemi_1_4000000 },
3237         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239                 pbn_oxsemi_1_4000000 },
3240         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242                 pbn_oxsemi_1_4000000 },
3243         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245                 pbn_oxsemi_1_4000000 },
3246         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248                 pbn_oxsemi_1_4000000 },
3249         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251                 pbn_oxsemi_1_4000000 },
3252         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254                 pbn_oxsemi_1_4000000 },
3255         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257                 pbn_oxsemi_1_4000000 },
3258         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_oxsemi_1_4000000 },
3261         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263                 pbn_oxsemi_1_4000000 },
3264         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266                 pbn_oxsemi_1_4000000 },
3267         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269                 pbn_oxsemi_1_4000000 },
3270         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272                 pbn_oxsemi_1_4000000 },
3273         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275                 pbn_oxsemi_1_4000000 },
3276         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3277                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278                 pbn_oxsemi_1_4000000 },
3279         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281                 pbn_oxsemi_1_4000000 },
3282         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284                 pbn_oxsemi_1_4000000 },
3285         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287                 pbn_oxsemi_1_4000000 },
3288         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290                 pbn_oxsemi_1_4000000 },
3291         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293                 pbn_oxsemi_1_4000000 },
3294         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3295                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296                 pbn_oxsemi_1_4000000 },
3297         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299                 pbn_oxsemi_1_4000000 },
3300         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3301                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302                 pbn_oxsemi_1_4000000 },
3303         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3304                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305                 pbn_oxsemi_1_4000000 },
3306         /*
3307          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3308          */
3309         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3310                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3311                 pbn_oxsemi_1_4000000 },
3312         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3313                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3314                 pbn_oxsemi_2_4000000 },
3315         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3316                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3317                 pbn_oxsemi_4_4000000 },
3318         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3319                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3320                 pbn_oxsemi_8_4000000 },
3321
3322         /*
3323          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3324          */
3325         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3326                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3327                 pbn_oxsemi_2_4000000 },
3328
3329         /*
3330          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3331          * from skokodyn@yahoo.com
3332          */
3333         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3334                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3335                 pbn_sbsxrsio },
3336         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3337                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3338                 pbn_sbsxrsio },
3339         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3340                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3341                 pbn_sbsxrsio },
3342         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3343                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3344                 pbn_sbsxrsio },
3345
3346         /*
3347          * Digitan DS560-558, from jimd@esoft.com
3348          */
3349         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3351                 pbn_b1_1_115200 },
3352
3353         /*
3354          * Titan Electronic cards
3355          *  The 400L and 800L have a custom setup quirk.
3356          */
3357         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3358                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359                 pbn_b0_1_921600 },
3360         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3361                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3362                 pbn_b0_2_921600 },
3363         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3364                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3365                 pbn_b0_4_921600 },
3366         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3367                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3368                 pbn_b0_4_921600 },
3369         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3370                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3371                 pbn_b1_1_921600 },
3372         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3373                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3374                 pbn_b1_bt_2_921600 },
3375         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3376                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3377                 pbn_b0_bt_4_921600 },
3378         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3379                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3380                 pbn_b0_bt_8_921600 },
3381         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3382                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3383                 pbn_b4_bt_2_921600 },
3384         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3385                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3386                 pbn_b4_bt_4_921600 },
3387         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3388                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3389                 pbn_b4_bt_8_921600 },
3390         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3391                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392                 pbn_b0_4_921600 },
3393         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3394                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395                 pbn_b0_4_921600 },
3396         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3397                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398                 pbn_b0_4_921600 },
3399         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3400                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401                 pbn_oxsemi_1_4000000 },
3402         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3403                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404                 pbn_oxsemi_2_4000000 },
3405         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3406                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407                 pbn_oxsemi_4_4000000 },
3408         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3409                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410                 pbn_oxsemi_8_4000000 },
3411         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3412                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413                 pbn_oxsemi_2_4000000 },
3414         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3415                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416                 pbn_oxsemi_2_4000000 },
3417
3418         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3419                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420                 pbn_b2_1_460800 },
3421         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3422                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423                 pbn_b2_1_460800 },
3424         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3425                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3426                 pbn_b2_1_460800 },
3427         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3428                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3429                 pbn_b2_bt_2_921600 },
3430         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3431                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3432                 pbn_b2_bt_2_921600 },
3433         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3434                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435                 pbn_b2_bt_2_921600 },
3436         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438                 pbn_b2_bt_4_921600 },
3439         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3440                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3441                 pbn_b2_bt_4_921600 },
3442         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3443                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3444                 pbn_b2_bt_4_921600 },
3445         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3446                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3447                 pbn_b0_1_921600 },
3448         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3449                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3450                 pbn_b0_1_921600 },
3451         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3452                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3453                 pbn_b0_1_921600 },
3454         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3455                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3456                 pbn_b0_bt_2_921600 },
3457         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3458                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3459                 pbn_b0_bt_2_921600 },
3460         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3461                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3462                 pbn_b0_bt_2_921600 },
3463         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465                 pbn_b0_bt_4_921600 },
3466         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3467                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468                 pbn_b0_bt_4_921600 },
3469         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471                 pbn_b0_bt_4_921600 },
3472         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474                 pbn_b0_bt_8_921600 },
3475         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477                 pbn_b0_bt_8_921600 },
3478         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480                 pbn_b0_bt_8_921600 },
3481
3482         /*
3483          * Computone devices submitted by Doug McNash dmcnash@computone.com
3484          */
3485         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3486                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3487                 0, 0, pbn_computone_4 },
3488         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3489                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3490                 0, 0, pbn_computone_8 },
3491         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3492                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3493                 0, 0, pbn_computone_6 },
3494
3495         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3496                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3497                 pbn_oxsemi },
3498         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3499                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3500                 pbn_b0_bt_1_921600 },
3501
3502         /*
3503          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3504          */
3505         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507                 pbn_b0_bt_8_115200 },
3508         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510                 pbn_b0_bt_8_115200 },
3511
3512         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3513                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3514                 pbn_b0_bt_2_115200 },
3515         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3517                 pbn_b0_bt_2_115200 },
3518         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3519                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3520                 pbn_b0_bt_2_115200 },
3521         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3522                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3523                 pbn_b0_bt_2_115200 },
3524         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3525                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3526                 pbn_b0_bt_2_115200 },
3527         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3529                 pbn_b0_bt_4_460800 },
3530         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3531                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3532                 pbn_b0_bt_4_460800 },
3533         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3535                 pbn_b0_bt_2_460800 },
3536         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3537                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3538                 pbn_b0_bt_2_460800 },
3539         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3540                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3541                 pbn_b0_bt_2_460800 },
3542         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3544                 pbn_b0_bt_1_115200 },
3545         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3546                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3547                 pbn_b0_bt_1_460800 },
3548
3549         /*
3550          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3551          * Cards are identified by their subsystem vendor IDs, which
3552          * (in hex) match the model number.
3553          *
3554          * Note that JC140x are RS422/485 cards which require ox950
3555          * ACR = 0x10, and as such are not currently fully supported.
3556          */
3557         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3558                 0x1204, 0x0004, 0, 0,
3559                 pbn_b0_4_921600 },
3560         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3561                 0x1208, 0x0004, 0, 0,
3562                 pbn_b0_4_921600 },
3563 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3564                 0x1402, 0x0002, 0, 0,
3565                 pbn_b0_2_921600 }, */
3566 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3567                 0x1404, 0x0004, 0, 0,
3568                 pbn_b0_4_921600 }, */
3569         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3570                 0x1208, 0x0004, 0, 0,
3571                 pbn_b0_4_921600 },
3572
3573         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3574                 0x1204, 0x0004, 0, 0,
3575                 pbn_b0_4_921600 },
3576         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3577                 0x1208, 0x0004, 0, 0,
3578                 pbn_b0_4_921600 },
3579         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3580                 0x1208, 0x0004, 0, 0,
3581                 pbn_b0_4_921600 },
3582         /*
3583          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3584          */
3585         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3586                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3587                 pbn_b1_1_1382400 },
3588
3589         /*
3590          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3591          */
3592         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3593                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3594                 pbn_b1_1_1382400 },
3595
3596         /*
3597          * RAStel 2 port modem, gerg@moreton.com.au
3598          */
3599         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3600                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601                 pbn_b2_bt_2_115200 },
3602
3603         /*
3604          * EKF addition for i960 Boards form EKF with serial port
3605          */
3606         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3607                 0xE4BF, PCI_ANY_ID, 0, 0,
3608                 pbn_intel_i960 },
3609
3610         /*
3611          * Xircom Cardbus/Ethernet combos
3612          */
3613         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3614                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3615                 pbn_b0_1_115200 },
3616         /*
3617          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3618          */
3619         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3620                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3621                 pbn_b0_1_115200 },
3622
3623         /*
3624          * Untested PCI modems, sent in from various folks...
3625          */
3626
3627         /*
3628          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3629          */
3630         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3631                 0x1048, 0x1500, 0, 0,
3632                 pbn_b1_1_115200 },
3633
3634         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3635                 0xFF00, 0, 0, 0,
3636                 pbn_sgi_ioc3 },
3637
3638         /*
3639          * HP Diva card
3640          */
3641         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3642                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3643                 pbn_b1_1_115200 },
3644         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3645                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3646                 pbn_b0_5_115200 },
3647         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3648                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3649                 pbn_b2_1_115200 },
3650
3651         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3652                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3653                 pbn_b3_2_115200 },
3654         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3655                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3656                 pbn_b3_4_115200 },
3657         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3658                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3659                 pbn_b3_8_115200 },
3660
3661         /*
3662          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3663          */
3664         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3665                 PCI_ANY_ID, PCI_ANY_ID,
3666                 0,
3667                 0, pbn_exar_XR17C152 },
3668         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3669                 PCI_ANY_ID, PCI_ANY_ID,
3670                 0,
3671                 0, pbn_exar_XR17C154 },
3672         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3673                 PCI_ANY_ID, PCI_ANY_ID,
3674                 0,
3675                 0, pbn_exar_XR17C158 },
3676
3677         /*
3678          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3679          */
3680         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3681                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3682                 pbn_b0_1_115200 },
3683         /*
3684          * ITE
3685          */
3686         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3687                 PCI_ANY_ID, PCI_ANY_ID,
3688                 0, 0,
3689                 pbn_b1_bt_1_115200 },
3690
3691         /*
3692          * IntaShield IS-200
3693          */
3694         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3695                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3696                 pbn_b2_2_115200 },
3697         /*
3698          * IntaShield IS-400
3699          */
3700         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3701                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3702                 pbn_b2_4_115200 },
3703         /*
3704          * Perle PCI-RAS cards
3705          */
3706         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3707                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3708                 0, 0, pbn_b2_4_921600 },
3709         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3710                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3711                 0, 0, pbn_b2_8_921600 },
3712
3713         /*
3714          * Mainpine series cards: Fairly standard layout but fools
3715          * parts of the autodetect in some cases and uses otherwise
3716          * unmatched communications subclasses in the PCI Express case
3717          */
3718
3719         {       /* RockForceDUO */
3720                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3721                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3722                 0, 0, pbn_b0_2_115200 },
3723         {       /* RockForceQUATRO */
3724                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3725                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3726                 0, 0, pbn_b0_4_115200 },
3727         {       /* RockForceDUO+ */
3728                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3729                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3730                 0, 0, pbn_b0_2_115200 },
3731         {       /* RockForceQUATRO+ */
3732                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3733                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3734                 0, 0, pbn_b0_4_115200 },
3735         {       /* RockForce+ */
3736                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3737                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3738                 0, 0, pbn_b0_2_115200 },
3739         {       /* RockForce+ */
3740                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3741                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3742                 0, 0, pbn_b0_4_115200 },
3743         {       /* RockForceOCTO+ */
3744                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3745                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3746                 0, 0, pbn_b0_8_115200 },
3747         {       /* RockForceDUO+ */
3748                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3749                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3750                 0, 0, pbn_b0_2_115200 },
3751         {       /* RockForceQUARTRO+ */
3752                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3753                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3754                 0, 0, pbn_b0_4_115200 },
3755         {       /* RockForceOCTO+ */
3756                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3757                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3758                 0, 0, pbn_b0_8_115200 },
3759         {       /* RockForceD1 */
3760                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3761                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3762                 0, 0, pbn_b0_1_115200 },
3763         {       /* RockForceF1 */
3764                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3765                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3766                 0, 0, pbn_b0_1_115200 },
3767         {       /* RockForceD2 */
3768                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3769                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3770                 0, 0, pbn_b0_2_115200 },
3771         {       /* RockForceF2 */
3772                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3773                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3774                 0, 0, pbn_b0_2_115200 },
3775         {       /* RockForceD4 */
3776                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3777                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3778                 0, 0, pbn_b0_4_115200 },
3779         {       /* RockForceF4 */
3780                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3781                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3782                 0, 0, pbn_b0_4_115200 },
3783         {       /* RockForceD8 */
3784                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3785                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3786                 0, 0, pbn_b0_8_115200 },
3787         {       /* RockForceF8 */
3788                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3789                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3790                 0, 0, pbn_b0_8_115200 },
3791         {       /* IQ Express D1 */
3792                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3793                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3794                 0, 0, pbn_b0_1_115200 },
3795         {       /* IQ Express F1 */
3796                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3797                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3798                 0, 0, pbn_b0_1_115200 },
3799         {       /* IQ Express D2 */
3800                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3801                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3802                 0, 0, pbn_b0_2_115200 },
3803         {       /* IQ Express F2 */
3804                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3805                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3806                 0, 0, pbn_b0_2_115200 },
3807         {       /* IQ Express D4 */
3808                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3809                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3810                 0, 0, pbn_b0_4_115200 },
3811         {       /* IQ Express F4 */
3812                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3813                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3814                 0, 0, pbn_b0_4_115200 },
3815         {       /* IQ Express D8 */
3816                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3817                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3818                 0, 0, pbn_b0_8_115200 },
3819         {       /* IQ Express F8 */
3820                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3821                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3822                 0, 0, pbn_b0_8_115200 },
3823
3824
3825         /*
3826          * PA Semi PA6T-1682M on-chip UART
3827          */
3828         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3830                 pbn_pasemi_1682M },
3831
3832         /*
3833          * National Instruments
3834          */
3835         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3836                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3837                 pbn_b1_16_115200 },
3838         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3839                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3840                 pbn_b1_8_115200 },
3841         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3842                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3843                 pbn_b1_bt_4_115200 },
3844         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3846                 pbn_b1_bt_2_115200 },
3847         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3849                 pbn_b1_bt_4_115200 },
3850         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3851                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3852                 pbn_b1_bt_2_115200 },
3853         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3854                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3855                 pbn_b1_16_115200 },
3856         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3858                 pbn_b1_8_115200 },
3859         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3861                 pbn_b1_bt_4_115200 },
3862         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3863                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3864                 pbn_b1_bt_2_115200 },
3865         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3866                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3867                 pbn_b1_bt_4_115200 },
3868         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3869                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3870                 pbn_b1_bt_2_115200 },
3871         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3873                 pbn_ni8430_2 },
3874         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3875                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3876                 pbn_ni8430_2 },
3877         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3878                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3879                 pbn_ni8430_4 },
3880         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3882                 pbn_ni8430_4 },
3883         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3885                 pbn_ni8430_8 },
3886         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3888                 pbn_ni8430_8 },
3889         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891                 pbn_ni8430_16 },
3892         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3894                 pbn_ni8430_16 },
3895         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3897                 pbn_ni8430_2 },
3898         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3900                 pbn_ni8430_2 },
3901         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3903                 pbn_ni8430_4 },
3904         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3906                 pbn_ni8430_4 },
3907
3908         /*
3909         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3910         */
3911         {       PCI_VENDOR_ID_ADDIDATA,
3912                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3913                 PCI_ANY_ID,
3914                 PCI_ANY_ID,
3915                 0,
3916                 0,
3917                 pbn_b0_4_115200 },
3918
3919         {       PCI_VENDOR_ID_ADDIDATA,
3920                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3921                 PCI_ANY_ID,
3922                 PCI_ANY_ID,
3923                 0,
3924                 0,
3925                 pbn_b0_2_115200 },
3926
3927         {       PCI_VENDOR_ID_ADDIDATA,
3928                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3929                 PCI_ANY_ID,
3930                 PCI_ANY_ID,
3931                 0,
3932                 0,
3933                 pbn_b0_1_115200 },
3934
3935         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3936                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3937                 PCI_ANY_ID,
3938                 PCI_ANY_ID,
3939                 0,
3940                 0,
3941                 pbn_b1_8_115200 },
3942
3943         {       PCI_VENDOR_ID_ADDIDATA,
3944                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3945                 PCI_ANY_ID,
3946                 PCI_ANY_ID,
3947                 0,
3948                 0,
3949                 pbn_b0_4_115200 },
3950
3951         {       PCI_VENDOR_ID_ADDIDATA,
3952                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3953                 PCI_ANY_ID,
3954                 PCI_ANY_ID,
3955                 0,
3956                 0,
3957                 pbn_b0_2_115200 },
3958
3959         {       PCI_VENDOR_ID_ADDIDATA,
3960                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3961                 PCI_ANY_ID,
3962                 PCI_ANY_ID,
3963                 0,
3964                 0,
3965                 pbn_b0_1_115200 },
3966
3967         {       PCI_VENDOR_ID_ADDIDATA,
3968                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3969                 PCI_ANY_ID,
3970                 PCI_ANY_ID,
3971                 0,
3972                 0,
3973                 pbn_b0_4_115200 },
3974
3975         {       PCI_VENDOR_ID_ADDIDATA,
3976                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3977                 PCI_ANY_ID,
3978                 PCI_ANY_ID,
3979                 0,
3980                 0,
3981                 pbn_b0_2_115200 },
3982
3983         {       PCI_VENDOR_ID_ADDIDATA,
3984                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3985                 PCI_ANY_ID,
3986                 PCI_ANY_ID,
3987                 0,
3988                 0,
3989                 pbn_b0_1_115200 },
3990
3991         {       PCI_VENDOR_ID_ADDIDATA,
3992                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3993                 PCI_ANY_ID,
3994                 PCI_ANY_ID,
3995                 0,
3996                 0,
3997                 pbn_b0_8_115200 },
3998
3999         {       PCI_VENDOR_ID_ADDIDATA,
4000                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4001                 PCI_ANY_ID,
4002                 PCI_ANY_ID,
4003                 0,
4004                 0,
4005                 pbn_ADDIDATA_PCIe_4_3906250 },
4006
4007         {       PCI_VENDOR_ID_ADDIDATA,
4008                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4009                 PCI_ANY_ID,
4010                 PCI_ANY_ID,
4011                 0,
4012                 0,
4013                 pbn_ADDIDATA_PCIe_2_3906250 },
4014
4015         {       PCI_VENDOR_ID_ADDIDATA,
4016                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4017                 PCI_ANY_ID,
4018                 PCI_ANY_ID,
4019                 0,
4020                 0,
4021                 pbn_ADDIDATA_PCIe_1_3906250 },
4022
4023         {       PCI_VENDOR_ID_ADDIDATA,
4024                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4025                 PCI_ANY_ID,
4026                 PCI_ANY_ID,
4027                 0,
4028                 0,
4029                 pbn_ADDIDATA_PCIe_8_3906250 },
4030
4031         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4032                 PCI_VENDOR_ID_IBM, 0x0299,
4033                 0, 0, pbn_b0_bt_2_115200 },
4034
4035         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4036                 0xA000, 0x1000,
4037                 0, 0, pbn_b0_1_115200 },
4038
4039         /* the 9901 is a rebranded 9912 */
4040         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4041                 0xA000, 0x1000,
4042                 0, 0, pbn_b0_1_115200 },
4043
4044         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4045                 0xA000, 0x1000,
4046                 0, 0, pbn_b0_1_115200 },
4047
4048         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4049                 0xA000, 0x1000,
4050                 0, 0, pbn_b0_1_115200 },
4051
4052         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4053                 0xA000, 0x1000,
4054                 0, 0, pbn_b0_1_115200 },
4055
4056         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4057                 0xA000, 0x3002,
4058                 0, 0, pbn_NETMOS9900_2s_115200 },
4059
4060         /*
4061          * Best Connectivity and Rosewill PCI Multi I/O cards
4062          */
4063
4064         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4065                 0xA000, 0x1000,
4066                 0, 0, pbn_b0_1_115200 },
4067
4068         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4069                 0xA000, 0x3002,
4070                 0, 0, pbn_b0_bt_2_115200 },
4071
4072         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4073                 0xA000, 0x3004,
4074                 0, 0, pbn_b0_bt_4_115200 },
4075         /* Intel CE4100 */
4076         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4077                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4078                 pbn_ce4100_1_115200 },
4079
4080         /*
4081          * Cronyx Omega PCI
4082          */
4083         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4084                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085                 pbn_omegapci },
4086
4087         /*
4088          * These entries match devices with class COMMUNICATION_SERIAL,
4089          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4090          */
4091         {       PCI_ANY_ID, PCI_ANY_ID,
4092                 PCI_ANY_ID, PCI_ANY_ID,
4093                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4094                 0xffff00, pbn_default },
4095         {       PCI_ANY_ID, PCI_ANY_ID,
4096                 PCI_ANY_ID, PCI_ANY_ID,
4097                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4098                 0xffff00, pbn_default },
4099         {       PCI_ANY_ID, PCI_ANY_ID,
4100                 PCI_ANY_ID, PCI_ANY_ID,
4101                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4102                 0xffff00, pbn_default },
4103         { 0, }
4104 };
4105
4106 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4107                                                 pci_channel_state_t state)
4108 {
4109         struct serial_private *priv = pci_get_drvdata(dev);
4110
4111         if (state == pci_channel_io_perm_failure)
4112                 return PCI_ERS_RESULT_DISCONNECT;
4113
4114         if (priv)
4115                 pciserial_suspend_ports(priv);
4116
4117         pci_disable_device(dev);
4118
4119         return PCI_ERS_RESULT_NEED_RESET;
4120 }
4121
4122 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4123 {
4124         int rc;
4125
4126         rc = pci_enable_device(dev);
4127
4128         if (rc)
4129                 return PCI_ERS_RESULT_DISCONNECT;
4130
4131         pci_restore_state(dev);
4132         pci_save_state(dev);
4133
4134         return PCI_ERS_RESULT_RECOVERED;
4135 }
4136
4137 static void serial8250_io_resume(struct pci_dev *dev)
4138 {
4139         struct serial_private *priv = pci_get_drvdata(dev);
4140
4141         if (priv)
4142                 pciserial_resume_ports(priv);
4143 }
4144
4145 static struct pci_error_handlers serial8250_err_handler = {
4146         .error_detected = serial8250_io_error_detected,
4147         .slot_reset = serial8250_io_slot_reset,
4148         .resume = serial8250_io_resume,
4149 };
4150
4151 static struct pci_driver serial_pci_driver = {
4152         .name           = "serial",
4153         .probe          = pciserial_init_one,
4154         .remove         = __devexit_p(pciserial_remove_one),
4155 #ifdef CONFIG_PM
4156         .suspend        = pciserial_suspend_one,
4157         .resume         = pciserial_resume_one,
4158 #endif
4159         .id_table       = serial_pci_tbl,
4160         .err_handler    = &serial8250_err_handler,
4161 };
4162
4163 static int __init serial8250_pci_init(void)
4164 {
4165         return pci_register_driver(&serial_pci_driver);
4166 }
4167
4168 static void __exit serial8250_pci_exit(void)
4169 {
4170         pci_unregister_driver(&serial_pci_driver);
4171 }
4172
4173 module_init(serial8250_pci_init);
4174 module_exit(serial8250_pci_exit);
4175
4176 MODULE_LICENSE("GPL");
4177 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4178 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);