drivers/tty/serial/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/bitops.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26
  27 #include "8250.h"
  28
  29 #undef SERIAL_DEBUG_PCI
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*probe)(struct pci_dev *dev);
  43         int     (*init)(struct pci_dev *dev);
  44         int     (*setup)(struct serial_private *,
  45                          const struct pciserial_board *,
  46                          struct uart_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static int pci_default_setup(struct serial_private*,
  61           const struct pciserial_board*, struct uart_port*, int);
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING
  66                "%s: %s\n"
  67                "Please send the output of lspci -vv, this\n"
  68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  69                "manufacturer and name of serial board or\n"
  70                "modem board to rmk+serial@arm.linux.org.uk.\n",
  71                pci_name(dev), str, dev->vendor, dev->device,
  72                dev->subsystem_vendor, dev->subsystem_device);
  73 }
  74
  75 static int
  76 setup_port(struct serial_private *priv, struct uart_port *port,
  77            int bar, int offset, int regshift)
  78 {
  79         struct pci_dev *dev = priv->dev;
  80         unsigned long base, len;
  81
  82         if (bar >= PCI_NUM_BAR_RESOURCES)
  83                 return -EINVAL;
  84
  85         base = pci_resource_start(dev, bar);
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 len =  pci_resource_len(dev, bar);
  89
  90                 if (!priv->remapped_bar[bar])
  91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  92                 if (!priv->remapped_bar[bar])
  93                         return -ENOMEM;
  94
  95                 port->iotype = UPIO_MEM;
  96                 port->iobase = 0;
  97                 port->mapbase = base + offset;
  98                 port->membase = priv->remapped_bar[bar] + offset;
  99                 port->regshift = regshift;
 100         } else {
 101                 port->iotype = UPIO_PORT;
 102                 port->iobase = base + offset;
 103                 port->mapbase = 0;
 104                 port->membase = NULL;
 105                 port->regshift = 0;
 106         }
 107         return 0;
 108 }
 109
 110 /*
 111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 112  */
 113 static int addidata_apci7800_setup(struct serial_private *priv,
 114                                 const struct pciserial_board *board,
 115                                 struct uart_port *port, int idx)
 116 {
 117         unsigned int bar = 0, offset = board->first_offset;
 118         bar = FL_GET_BASE(board->flags);
 119
 120         if (idx < 2) {
 121                 offset += idx * board->uart_offset;
 122         } else if ((idx >= 2) && (idx < 4)) {
 123                 bar += 1;
 124                 offset += ((idx - 2) * board->uart_offset);
 125         } else if ((idx >= 4) && (idx < 6)) {
 126                 bar += 2;
 127                 offset += ((idx - 4) * board->uart_offset);
 128         } else if (idx >= 6) {
 129                 bar += 3;
 130                 offset += ((idx - 6) * board->uart_offset);
 131         }
 132
 133         return setup_port(priv, port, bar, offset, board->reg_shift);
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 142               struct uart_port *port, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(priv, port, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 183                 rc = 1;
 184                 break;
 185         }
 186
 187         return rc;
 188 }
 189
 190 /*
 191  * HP's Diva chip puts the 4th/5th serial port further out, and
 192  * some serial ports are supposed to be hidden on certain models.
 193  */
 194 static int
 195 pci_hp_diva_setup(struct serial_private *priv,
 196                 const struct pciserial_board *board,
 197                 struct uart_port *port, int idx)
 198 {
 199         unsigned int offset = board->first_offset;
 200         unsigned int bar = FL_GET_BASE(board->flags);
 201
 202         switch (priv->dev->subsystem_device) {
 203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 204                 if (idx == 3)
 205                         idx++;
 206                 break;
 207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 208                 if (idx > 0)
 209                         idx++;
 210                 if (idx > 2)
 211                         idx++;
 212                 break;
 213         }
 214         if (idx > 2)
 215                 offset = 0x18;
 216
 217         offset += idx * board->uart_offset;
 218
 219         return setup_port(priv, port, bar, offset, board->reg_shift);
 220 }
 221
 222 /*
 223  * Added for EKF Intel i960 serial boards
 224  */
 225 static int pci_inteli960ni_init(struct pci_dev *dev)
 226 {
 227         unsigned long oldval;
 228
 229         if (!(dev->subsystem_device & 0x1000))
 230                 return -ENODEV;
 231
 232         /* is firmware started? */
 233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 234         if (oldval == 0x00001000L) { /* RESET value */
 235                 printk(KERN_DEBUG "Local i960 firmware missing");
 236                 return -ENODEV;
 237         }
 238         return 0;
 239 }
 240
 241 /*
 242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 243  * that the card interrupt be explicitly enabled or disabled.  This
 244  * seems to be mainly needed on card using the PLX which also use I/O
 245  * mapped memory.
 246  */
 247 static int pci_plx9050_init(struct pci_dev *dev)
 248 {
 249         u8 irq_config;
 250         void __iomem *p;
 251
 252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 253                 moan_device("no memory in bar 0", dev);
 254                 return 0;
 255         }
 256
 257         irq_config = 0x41;
 258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 260                 irq_config = 0x43;
 261
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         /*
 274          * enable/disable interrupts
 275          */
 276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 277         if (p == NULL)
 278                 return -ENOMEM;
 279         writel(irq_config, p + 0x4c);
 280
 281         /*
 282          * Read the register back to ensure that it took effect.
 283          */
 284         readl(p + 0x4c);
 285         iounmap(p);
 286
 287         return 0;
 288 }
 289
 290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 291 {
 292         u8 __iomem *p;
 293
 294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 295                 return;
 296
 297         /*
 298          * disable interrupts
 299          */
 300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 301         if (p != NULL) {
 302                 writel(0, p + 0x4c);
 303
 304                 /*
 305                  * Read the register back to ensure that it took effect.
 306                  */
 307                 readl(p + 0x4c);
 308                 iounmap(p);
 309         }
 310 }
 311
 312 #define NI8420_INT_ENABLE_REG   0x38
 313 #define NI8420_INT_ENABLE_BIT   0x2000
 314
 315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 316 {
 317         void __iomem *p;
 318         unsigned long base, len;
 319         unsigned int bar = 0;
 320
 321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 322                 moan_device("no memory in bar", dev);
 323                 return;
 324         }
 325
 326         base = pci_resource_start(dev, bar);
 327         len =  pci_resource_len(dev, bar);
 328         p = ioremap_nocache(base, len);
 329         if (p == NULL)
 330                 return;
 331
 332         /* Disable the CPU Interrupt */
 333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 334                p + NI8420_INT_ENABLE_REG);
 335         iounmap(p);
 336 }
 337
 338
 339 /* MITE registers */
 340 #define MITE_IOWBSR1    0xc4
 341 #define MITE_IOWCR1     0xf4
 342 #define MITE_LCIMR1     0x08
 343 #define MITE_LCIMR2     0x10
 344
 345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 346
 347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 348 {
 349         void __iomem *p;
 350         unsigned long base, len;
 351         unsigned int bar = 0;
 352
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357
 358         base = pci_resource_start(dev, bar);
 359         len =  pci_resource_len(dev, bar);
 360         p = ioremap_nocache(base, len);
 361         if (p == NULL)
 362                 return;
 363
 364         /* Disable the CPU Interrupt */
 365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366         iounmap(p);
 367 }
 368
 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370 static int
 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                 struct uart_port *port, int idx)
 373 {
 374         unsigned int bar, offset = board->first_offset;
 375
 376         bar = 0;
 377
 378         if (idx < 4) {
 379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                 offset += idx * board->uart_offset;
 381         } else if (idx < 8) {
 382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                 offset += idx * board->uart_offset + 0xC00;
 384         } else /* we have only 8 ports on PMC-OCTALPRO */
 385                 return 1;
 386
 387         return setup_port(priv, port, bar, offset, board->reg_shift);
 388 }
 389
 390 /*
 391 * This does initialization for PMC OCTALPRO cards:
 392 * maps the device memory, resets the UARTs (needed, bc
 393 * if the module is removed and inserted again, the card
 394 * is in the sleep mode) and enables global interrupt.
 395 */
 396
 397 /* global control register offset for SBS PMC-OctalPro */
 398 #define OCT_REG_CR_OFF          0x500
 399
 400 static int sbs_init(struct pci_dev *dev)
 401 {
 402         u8 __iomem *p;
 403
 404         p = pci_ioremap_bar(dev, 0);
 405
 406         if (p == NULL)
 407                 return -ENOMEM;
 408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409         writeb(0x10, p + OCT_REG_CR_OFF);
 410         udelay(50);
 411         writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413         /* Set bit-2 (INTENABLE) of Control Register */
 414         writeb(0x4, p + OCT_REG_CR_OFF);
 415         iounmap(p);
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Disables the global interrupt of PMC-OctalPro
 422  */
 423
 424 static void __devexit sbs_exit(struct pci_dev *dev)
 425 {
 426         u8 __iomem *p;
 427
 428         p = pci_ioremap_bar(dev, 0);
 429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430         if (p != NULL)
 431                 writeb(0, p + OCT_REG_CR_OFF);
 432         iounmap(p);
 433 }
 434
 435 /*
 436  * SIIG serial cards have an PCI interface chip which also controls
 437  * the UART clocking frequency. Each UART can be clocked independently
 438  * (except cards equipped with 4 UARTs) and initial clocking settings
 439  * are stored in the EEPROM chip. It can cause problems because this
 440  * version of serial driver doesn't support differently clocked UART's
 441  * on single PCI card. To prevent this, initialization functions set
 442  * high frequency clocking for all UART's on given card. It is safe (I
 443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444  * with other OSes (like M$ DOS).
 445  *
 446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447  *
 448  * There is two family of SIIG serial cards with different PCI
 449  * interface chip and different configuration methods:
 450  *     - 10x cards have control registers in IO and/or memory space;
 451  *     - 20x cards have control registers in standard PCI configuration space.
 452  *
 453  * Note: all 10x cards have PCI device ids 0x10..
 454  *       all 20x cards have PCI device ids 0x20..
 455  *
 456  * There are also Quartet Serial cards which use Oxford Semiconductor
 457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458  *
 459  * Note: some SIIG cards are probed by the parport_serial object.
 460  */
 461
 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465 static int pci_siig10x_init(struct pci_dev *dev)
 466 {
 467         u16 data;
 468         void __iomem *p;
 469
 470         switch (dev->device & 0xfff8) {
 471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                 data = 0xffdf;
 473                 break;
 474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                 data = 0xf7ff;
 476                 break;
 477         default:                        /* 1S1P, 4S */
 478                 data = 0xfffb;
 479                 break;
 480         }
 481
 482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 483         if (p == NULL)
 484                 return -ENOMEM;
 485
 486         writew(readw(p + 0x28) & data, p + 0x28);
 487         readw(p + 0x28);
 488         iounmap(p);
 489         return 0;
 490 }
 491
 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495 static int pci_siig20x_init(struct pci_dev *dev)
 496 {
 497         u8 data;
 498
 499         /* Change clock frequency for the first UART. */
 500         pci_read_config_byte(dev, 0x6f, &data);
 501         pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503         /* If this card has 2 UART, we have to do the same with second UART. */
 504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                 pci_read_config_byte(dev, 0x73, &data);
 507                 pci_write_config_byte(dev, 0x73, data & 0xef);
 508         }
 509         return 0;
 510 }
 511
 512 static int pci_siig_init(struct pci_dev *dev)
 513 {
 514         unsigned int type = dev->device & 0xff00;
 515
 516         if (type == 0x1000)
 517                 return pci_siig10x_init(dev);
 518         else if (type == 0x2000)
 519                 return pci_siig20x_init(dev);
 520
 521         moan_device("Unknown SIIG card", dev);
 522         return -ENODEV;
 523 }
 524
 525 static int pci_siig_setup(struct serial_private *priv,
 526                           const struct pciserial_board *board,
 527                           struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531         if (idx > 3) {
 532                 bar = 4;
 533                 offset = (idx - 4) * 8;
 534         }
 535
 536         return setup_port(priv, port, bar, offset, 0);
 537 }
 538
 539 /*
 540  * Timedia has an explosion of boards, and to avoid the PCI table from
 541  * growing *huge*, we use this function to collapse some 70 entries
 542  * in the PCI table into one, for sanity's and compactness's sake.
 543  */
 544 static const unsigned short timedia_single_port[] = {
 545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546 };
 547
 548 static const unsigned short timedia_dual_port[] = {
 549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553         0xD079, 0
 554 };
 555
 556 static const unsigned short timedia_quad_port[] = {
 557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560         0xB157, 0
 561 };
 562
 563 static const unsigned short timedia_eight_port[] = {
 564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566 };
 567
 568 static const struct timedia_struct {
 569         int num;
 570         const unsigned short *ids;
 571 } timedia_data[] = {
 572         { 1, timedia_single_port },
 573         { 2, timedia_dual_port },
 574         { 4, timedia_quad_port },
 575         { 8, timedia_eight_port }
 576 };
 577
 578 /*
 579  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 580  * listing them individually, this driver merely grabs them all with
 581  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 582  * and should be left free to be claimed by parport_serial instead.
 583  */
 584 static int pci_timedia_probe(struct pci_dev *dev)
 585 {
 586         /*
 587          * Check the third digit of the subdevice ID
 588          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 589          */
 590         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 591                 dev_info(&dev->dev,
 592                         "ignoring Timedia subdevice %04x for parport_serial\n",
 593                         dev->subsystem_device);
 594                 return -ENODEV;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int pci_timedia_init(struct pci_dev *dev)
 601 {
 602         const unsigned short *ids;
 603         int i, j;
 604
 605         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 606                 ids = timedia_data[i].ids;
 607                 for (j = 0; ids[j]; j++)
 608                         if (dev->subsystem_device == ids[j])
 609                                 return timedia_data[i].num;
 610         }
 611         return 0;
 612 }
 613
 614 /*
 615  * Timedia/SUNIX uses a mixture of BARs and offsets
 616  * Ugh, this is ugly as all hell --- TYT
 617  */
 618 static int
 619 pci_timedia_setup(struct serial_private *priv,
 620                   const struct pciserial_board *board,
 621                   struct uart_port *port, int idx)
 622 {
 623         unsigned int bar = 0, offset = board->first_offset;
 624
 625         switch (idx) {
 626         case 0:
 627                 bar = 0;
 628                 break;
 629         case 1:
 630                 offset = board->uart_offset;
 631                 bar = 0;
 632                 break;
 633         case 2:
 634                 bar = 1;
 635                 break;
 636         case 3:
 637                 offset = board->uart_offset;
 638                 /* FALLTHROUGH */
 639         case 4: /* BAR 2 */
 640         case 5: /* BAR 3 */
 641         case 6: /* BAR 4 */
 642         case 7: /* BAR 5 */
 643                 bar = idx - 2;
 644         }
 645
 646         return setup_port(priv, port, bar, offset, board->reg_shift);
 647 }
 648
 649 /*
 650  * Some Titan cards are also a little weird
 651  */
 652 static int
 653 titan_400l_800l_setup(struct serial_private *priv,
 654                       const struct pciserial_board *board,
 655                       struct uart_port *port, int idx)
 656 {
 657         unsigned int bar, offset = board->first_offset;
 658
 659         switch (idx) {
 660         case 0:
 661                 bar = 1;
 662                 break;
 663         case 1:
 664                 bar = 2;
 665                 break;
 666         default:
 667                 bar = 4;
 668                 offset = (idx - 2) * board->uart_offset;
 669         }
 670
 671         return setup_port(priv, port, bar, offset, board->reg_shift);
 672 }
 673
 674 static int pci_xircom_init(struct pci_dev *dev)
 675 {
 676         msleep(100);
 677         return 0;
 678 }
 679
 680 static int pci_ni8420_init(struct pci_dev *dev)
 681 {
 682         void __iomem *p;
 683         unsigned long base, len;
 684         unsigned int bar = 0;
 685
 686         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 687                 moan_device("no memory in bar", dev);
 688                 return 0;
 689         }
 690
 691         base = pci_resource_start(dev, bar);
 692         len =  pci_resource_len(dev, bar);
 693         p = ioremap_nocache(base, len);
 694         if (p == NULL)
 695                 return -ENOMEM;
 696
 697         /* Enable CPU Interrupt */
 698         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 699                p + NI8420_INT_ENABLE_REG);
 700
 701         iounmap(p);
 702         return 0;
 703 }
 704
 705 #define MITE_IOWBSR1_WSIZE      0xa
 706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 707 #define MITE_IOWBSR1_WENAB      (1 << 7)
 708 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 709 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 711
 712 static int pci_ni8430_init(struct pci_dev *dev)
 713 {
 714         void __iomem *p;
 715         unsigned long base, len;
 716         u32 device_window;
 717         unsigned int bar = 0;
 718
 719         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 720                 moan_device("no memory in bar", dev);
 721                 return 0;
 722         }
 723
 724         base = pci_resource_start(dev, bar);
 725         len =  pci_resource_len(dev, bar);
 726         p = ioremap_nocache(base, len);
 727         if (p == NULL)
 728                 return -ENOMEM;
 729
 730         /* Set device window address and size in BAR0 */
 731         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 732                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 733         writel(device_window, p + MITE_IOWBSR1);
 734
 735         /* Set window access to go to RAMSEL IO address space */
 736         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 737                p + MITE_IOWCR1);
 738
 739         /* Enable IO Bus Interrupt 0 */
 740         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 741
 742         /* Enable CPU Interrupt */
 743         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 744
 745         iounmap(p);
 746         return 0;
 747 }
 748
 749 /* UART Port Control Register */
 750 #define NI8430_PORTCON  0x0f
 751 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 752
 753 static int
 754 pci_ni8430_setup(struct serial_private *priv,
 755                  const struct pciserial_board *board,
 756                  struct uart_port *port, int idx)
 757 {
 758         void __iomem *p;
 759         unsigned long base, len;
 760         unsigned int bar, offset = board->first_offset;
 761
 762         if (idx >= board->num_ports)
 763                 return 1;
 764
 765         bar = FL_GET_BASE(board->flags);
 766         offset += idx * board->uart_offset;
 767
 768         base = pci_resource_start(priv->dev, bar);
 769         len =  pci_resource_len(priv->dev, bar);
 770         p = ioremap_nocache(base, len);
 771
 772         /* enable the transceiver */
 773         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 774                p + offset + NI8430_PORTCON);
 775
 776         iounmap(p);
 777
 778         return setup_port(priv, port, bar, offset, board->reg_shift);
 779 }
 780
 781 static int pci_netmos_9900_setup(struct serial_private *priv,
 782                                 const struct pciserial_board *board,
 783                                 struct uart_port *port, int idx)
 784 {
 785         unsigned int bar;
 786
 787         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 788                 /* netmos apparently orders BARs by datasheet layout, so serial
 789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 790                  */
 791                 bar = 3 * idx;
 792
 793                 return setup_port(priv, port, bar, 0, board->reg_shift);
 794         } else {
 795                 return pci_default_setup(priv, board, port, idx);
 796         }
 797 }
 798
 799 /* the 99xx series comes with a range of device IDs and a variety
 800  * of capabilities:
 801  *
 802  * 9900 has varying capabilities and can cascade to sub-controllers
 803  *   (cascading should be purely internal)
 804  * 9904 is hardwired with 4 serial ports
 805  * 9912 and 9922 are hardwired with 2 serial ports
 806  */
 807 static int pci_netmos_9900_numports(struct pci_dev *dev)
 808 {
 809         unsigned int c = dev->class;
 810         unsigned int pi;
 811         unsigned short sub_serports;
 812
 813         pi = (c & 0xff);
 814
 815         if (pi == 2) {
 816                 return 1;
 817         } else if ((pi == 0) &&
 818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 819                 /* two possibilities: 0x30ps encodes number of parallel and
 820                  * serial ports, or 0x1000 indicates *something*. This is not
 821                  * immediately obvious, since the 2s1p+4s configuration seems
 822                  * to offer all functionality on functions 0..2, while still
 823                  * advertising the same function 3 as the 4s+2s1p config.
 824                  */
 825                 sub_serports = dev->subsystem_device & 0xf;
 826                 if (sub_serports > 0) {
 827                         return sub_serports;
 828                 } else {
 829                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                         return 0;
 831                 }
 832         }
 833
 834         moan_device("unknown NetMos/Mostech program interface", dev);
 835         return 0;
 836 }
 837
 838 static int pci_netmos_init(struct pci_dev *dev)
 839 {
 840         /* subdevice 0x00PS means <P> parallel, <S> serial */
 841         unsigned int num_serial = dev->subsystem_device & 0xf;
 842
 843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 845                 return 0;
 846
 847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 848                         dev->subsystem_device == 0x0299)
 849                 return 0;
 850
 851         switch (dev->device) { /* FALLTHROUGH on all */
 852                 case PCI_DEVICE_ID_NETMOS_9904:
 853                 case PCI_DEVICE_ID_NETMOS_9912:
 854                 case PCI_DEVICE_ID_NETMOS_9922:
 855                 case PCI_DEVICE_ID_NETMOS_9900:
 856                         num_serial = pci_netmos_9900_numports(dev);
 857                         break;
 858
 859                 default:
 860                         if (num_serial == 0 ) {
 861                                 moan_device("unknown NetMos/Mostech device", dev);
 862                         }
 863         }
 864
 865         if (num_serial == 0)
 866                 return -ENODEV;
 867
 868         return num_serial;
 869 }
 870
 871 /*
 872  * These chips are available with optionally one parallel port and up to
 873  * two serial ports. Unfortunately they all have the same product id.
 874  *
 875  * Basic configuration is done over a region of 32 I/O ports. The base
 876  * ioport is called INTA or INTC, depending on docs/other drivers.
 877  *
 878  * The region of the 32 I/O ports is configured in POSIO0R...
 879  */
 880
 881 /* registers */
 882 #define ITE_887x_MISCR          0x9c
 883 #define ITE_887x_INTCBAR        0x78
 884 #define ITE_887x_UARTBAR        0x7c
 885 #define ITE_887x_PS0BAR         0x10
 886 #define ITE_887x_POSIO0         0x60
 887
 888 /* I/O space size */
 889 #define ITE_887x_IOSIZE         32
 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 895 #define ITE_887x_POSIO_SPEED            (3 << 29)
 896 /* enable IO_Space bit */
 897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 898
 899 static int pci_ite887x_init(struct pci_dev *dev)
 900 {
 901         /* inta_addr are the configuration addresses of the ITE */
 902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 903                                                         0x200, 0x280, 0 };
 904         int ret, i, type;
 905         struct resource *iobase = NULL;
 906         u32 miscr, uartbar, ioport;
 907
 908         /* search for the base-ioport */
 909         i = 0;
 910         while (inta_addr[i] && iobase == NULL) {
 911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 912                                                                 "ite887x");
 913                 if (iobase != NULL) {
 914                         /* write POSIO0R - speed | size | ioport */
 915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 918                         /* write INTCBAR - ioport */
 919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 920                                                                 inta_addr[i]);
 921                         ret = inb(inta_addr[i]);
 922                         if (ret != 0xff) {
 923                                 /* ioport connected */
 924                                 break;
 925                         }
 926                         release_region(iobase->start, ITE_887x_IOSIZE);
 927                         iobase = NULL;
 928                 }
 929                 i++;
 930         }
 931
 932         if (!inta_addr[i]) {
 933                 printk(KERN_ERR "ite887x: could not find iobase\n");
 934                 return -ENODEV;
 935         }
 936
 937         /* start of undocumented type checking (see parport_pc.c) */
 938         type = inb(iobase->start + 0x18) & 0x0f;
 939
 940         switch (type) {
 941         case 0x2:       /* ITE8871 (1P) */
 942         case 0xa:       /* ITE8875 (1P) */
 943                 ret = 0;
 944                 break;
 945         case 0xe:       /* ITE8872 (2S1P) */
 946                 ret = 2;
 947                 break;
 948         case 0x6:       /* ITE8873 (1S) */
 949                 ret = 1;
 950                 break;
 951         case 0x8:       /* ITE8874 (2S) */
 952                 ret = 2;
 953                 break;
 954         default:
 955                 moan_device("Unknown ITE887x", dev);
 956                 ret = -ENODEV;
 957         }
 958
 959         /* configure all serial ports */
 960         for (i = 0; i < ret; i++) {
 961                 /* read the I/O port from the device */
 962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 963                                                                 &ioport);
 964                 ioport &= 0x0000FF00;   /* the actual base address */
 965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 968
 969                 /* write the ioport to the UARTBAR */
 970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 974
 975                 /* get current config */
 976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 977                 /* disable interrupts (UARTx_Routing[3:0]) */
 978                 miscr &= ~(0xf << (12 - 4 * i));
 979                 /* activate the UART (UARTx_En) */
 980                 miscr |= 1 << (23 - i);
 981                 /* write new config with activated UART */
 982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 983         }
 984
 985         if (ret <= 0) {
 986                 /* the device has no UARTs if we get here */
 987                 release_region(iobase->start, ITE_887x_IOSIZE);
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 994 {
 995         u32 ioport;
 996         /* the ioport is bit 0-15 in POSIO0R */
 997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 998         ioport &= 0xffff;
 999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 printk(KERN_DEBUG
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                                                                 number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_port *port, int idx)
1038 {
1039         unsigned int bar, offset = board->first_offset, maxnr;
1040
1041         bar = FL_GET_BASE(board->flags);
1042         if (board->flags & FL_BASE_BARS)
1043                 bar += idx;
1044         else
1045                 offset += idx * board->uart_offset;
1046
1047         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048                 (board->reg_shift + 3);
1049
1050         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051                 return 1;
1052
1053         return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058                   const struct pciserial_board *board,
1059                   struct uart_port *port, int idx)
1060 {
1061         int ret;
1062
1063         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064         port->iotype = UPIO_MEM32;
1065         port->type = PORT_XSCALE;
1066         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067         port->regshift = 2;
1068
1069         return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074                       const struct pciserial_board *board,
1075                       struct uart_port *port, int idx)
1076 {
1077         return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int
1081 pci_brcm_trumanage_setup(struct serial_private *priv,
1082                          const struct pciserial_board *board,
1083                          struct uart_port *port, int idx)
1084 {
1085         int ret = pci_default_setup(priv, board, port, idx);
1086
1087         port->type = PORT_BRCM_TRUMANAGE;
1088         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1089         return ret;
1090 }
1091
1092 static int skip_tx_en_setup(struct serial_private *priv,
1093                         const struct pciserial_board *board,
1094                         struct uart_port *port, int idx)
1095 {
1096         port->flags |= UPF_NO_TXEN_TEST;
1097         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1098                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1099                           priv->dev->vendor,
1100                           priv->dev->device,
1101                           priv->dev->subsystem_vendor,
1102                           priv->dev->subsystem_device);
1103
1104         return pci_default_setup(priv, board, port, idx);
1105 }
1106
1107 static int pci_eg20t_init(struct pci_dev *dev)
1108 {
1109 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1110         return -ENODEV;
1111 #else
1112         return 0;
1113 #endif
1114 }
1115
1116 static int
1117 pci_xr17c154_setup(struct serial_private *priv,
1118                   const struct pciserial_board *board,
1119                   struct uart_port *port, int idx)
1120 {
1121         port->flags |= UPF_EXAR_EFR;
1122         return pci_default_setup(priv, board, port, idx);
1123 }
1124
1125 /* This should be in linux/pci_ids.h */
1126 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1127 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1128 #define PCI_DEVICE_ID_OCTPRO            0x0001
1129 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1130 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1131 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1132 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1133 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1134 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1135 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1136 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1137 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1138 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1139 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1140 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1141 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1142 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1143 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1144 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1145 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1146 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1147 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1148 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1149 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1150 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1151 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1152 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1153 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1154
1155 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1156 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1157 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1158
1159 /*
1160  * Master list of serial port init/setup/exit quirks.
1161  * This does not describe the general nature of the port.
1162  * (ie, baud base, number and location of ports, etc)
1163  *
1164  * This list is ordered alphabetically by vendor then device.
1165  * Specific entries must come before more generic entries.
1166  */
1167 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1168         /*
1169         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1170         */
1171         {
1172                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1173                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1174                 .subvendor      = PCI_ANY_ID,
1175                 .subdevice      = PCI_ANY_ID,
1176                 .setup          = addidata_apci7800_setup,
1177         },
1178         /*
1179          * AFAVLAB cards - these may be called via parport_serial
1180          *  It is not clear whether this applies to all products.
1181          */
1182         {
1183                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1184                 .device         = PCI_ANY_ID,
1185                 .subvendor      = PCI_ANY_ID,
1186                 .subdevice      = PCI_ANY_ID,
1187                 .setup          = afavlab_setup,
1188         },
1189         /*
1190          * HP Diva
1191          */
1192         {
1193                 .vendor         = PCI_VENDOR_ID_HP,
1194                 .device         = PCI_DEVICE_ID_HP_DIVA,
1195                 .subvendor      = PCI_ANY_ID,
1196                 .subdevice      = PCI_ANY_ID,
1197                 .init           = pci_hp_diva_init,
1198                 .setup          = pci_hp_diva_setup,
1199         },
1200         /*
1201          * Intel
1202          */
1203         {
1204                 .vendor         = PCI_VENDOR_ID_INTEL,
1205                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1206                 .subvendor      = 0xe4bf,
1207                 .subdevice      = PCI_ANY_ID,
1208                 .init           = pci_inteli960ni_init,
1209                 .setup          = pci_default_setup,
1210         },
1211         {
1212                 .vendor         = PCI_VENDOR_ID_INTEL,
1213                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1214                 .subvendor      = PCI_ANY_ID,
1215                 .subdevice      = PCI_ANY_ID,
1216                 .setup          = skip_tx_en_setup,
1217         },
1218         {
1219                 .vendor         = PCI_VENDOR_ID_INTEL,
1220                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1221                 .subvendor      = PCI_ANY_ID,
1222                 .subdevice      = PCI_ANY_ID,
1223                 .setup          = skip_tx_en_setup,
1224         },
1225         {
1226                 .vendor         = PCI_VENDOR_ID_INTEL,
1227                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1228                 .subvendor      = PCI_ANY_ID,
1229                 .subdevice      = PCI_ANY_ID,
1230                 .setup          = skip_tx_en_setup,
1231         },
1232         {
1233                 .vendor         = PCI_VENDOR_ID_INTEL,
1234                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1235                 .subvendor      = PCI_ANY_ID,
1236                 .subdevice      = PCI_ANY_ID,
1237                 .setup          = ce4100_serial_setup,
1238         },
1239         /*
1240          * ITE
1241          */
1242         {
1243                 .vendor         = PCI_VENDOR_ID_ITE,
1244                 .device         = PCI_DEVICE_ID_ITE_8872,
1245                 .subvendor      = PCI_ANY_ID,
1246                 .subdevice      = PCI_ANY_ID,
1247                 .init           = pci_ite887x_init,
1248                 .setup          = pci_default_setup,
1249                 .exit           = __devexit_p(pci_ite887x_exit),
1250         },
1251         /*
1252          * National Instruments
1253          */
1254         {
1255                 .vendor         = PCI_VENDOR_ID_NI,
1256                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1257                 .subvendor      = PCI_ANY_ID,
1258                 .subdevice      = PCI_ANY_ID,
1259                 .init           = pci_ni8420_init,
1260                 .setup          = pci_default_setup,
1261                 .exit           = __devexit_p(pci_ni8420_exit),
1262         },
1263         {
1264                 .vendor         = PCI_VENDOR_ID_NI,
1265                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1266                 .subvendor      = PCI_ANY_ID,
1267                 .subdevice      = PCI_ANY_ID,
1268                 .init           = pci_ni8420_init,
1269                 .setup          = pci_default_setup,
1270                 .exit           = __devexit_p(pci_ni8420_exit),
1271         },
1272         {
1273                 .vendor         = PCI_VENDOR_ID_NI,
1274                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1275                 .subvendor      = PCI_ANY_ID,
1276                 .subdevice      = PCI_ANY_ID,
1277                 .init           = pci_ni8420_init,
1278                 .setup          = pci_default_setup,
1279                 .exit           = __devexit_p(pci_ni8420_exit),
1280         },
1281         {
1282                 .vendor         = PCI_VENDOR_ID_NI,
1283                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1284                 .subvendor      = PCI_ANY_ID,
1285                 .subdevice      = PCI_ANY_ID,
1286                 .init           = pci_ni8420_init,
1287                 .setup          = pci_default_setup,
1288                 .exit           = __devexit_p(pci_ni8420_exit),
1289         },
1290         {
1291                 .vendor         = PCI_VENDOR_ID_NI,
1292                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1293                 .subvendor      = PCI_ANY_ID,
1294                 .subdevice      = PCI_ANY_ID,
1295                 .init           = pci_ni8420_init,
1296                 .setup          = pci_default_setup,
1297                 .exit           = __devexit_p(pci_ni8420_exit),
1298         },
1299         {
1300                 .vendor         = PCI_VENDOR_ID_NI,
1301                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1302                 .subvendor      = PCI_ANY_ID,
1303                 .subdevice      = PCI_ANY_ID,
1304                 .init           = pci_ni8420_init,
1305                 .setup          = pci_default_setup,
1306                 .exit           = __devexit_p(pci_ni8420_exit),
1307         },
1308         {
1309                 .vendor         = PCI_VENDOR_ID_NI,
1310                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1311                 .subvendor      = PCI_ANY_ID,
1312                 .subdevice      = PCI_ANY_ID,
1313                 .init           = pci_ni8420_init,
1314                 .setup          = pci_default_setup,
1315                 .exit           = __devexit_p(pci_ni8420_exit),
1316         },
1317         {
1318                 .vendor         = PCI_VENDOR_ID_NI,
1319                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1320                 .subvendor      = PCI_ANY_ID,
1321                 .subdevice      = PCI_ANY_ID,
1322                 .init           = pci_ni8420_init,
1323                 .setup          = pci_default_setup,
1324                 .exit           = __devexit_p(pci_ni8420_exit),
1325         },
1326         {
1327                 .vendor         = PCI_VENDOR_ID_NI,
1328                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1329                 .subvendor      = PCI_ANY_ID,
1330                 .subdevice      = PCI_ANY_ID,
1331                 .init           = pci_ni8420_init,
1332                 .setup          = pci_default_setup,
1333                 .exit           = __devexit_p(pci_ni8420_exit),
1334         },
1335         {
1336                 .vendor         = PCI_VENDOR_ID_NI,
1337                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1338                 .subvendor      = PCI_ANY_ID,
1339                 .subdevice      = PCI_ANY_ID,
1340                 .init           = pci_ni8420_init,
1341                 .setup          = pci_default_setup,
1342                 .exit           = __devexit_p(pci_ni8420_exit),
1343         },
1344         {
1345                 .vendor         = PCI_VENDOR_ID_NI,
1346                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1347                 .subvendor      = PCI_ANY_ID,
1348                 .subdevice      = PCI_ANY_ID,
1349                 .init           = pci_ni8420_init,
1350                 .setup          = pci_default_setup,
1351                 .exit           = __devexit_p(pci_ni8420_exit),
1352         },
1353         {
1354                 .vendor         = PCI_VENDOR_ID_NI,
1355                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1356                 .subvendor      = PCI_ANY_ID,
1357                 .subdevice      = PCI_ANY_ID,
1358                 .init           = pci_ni8420_init,
1359                 .setup          = pci_default_setup,
1360                 .exit           = __devexit_p(pci_ni8420_exit),
1361         },
1362         {
1363                 .vendor         = PCI_VENDOR_ID_NI,
1364                 .device         = PCI_ANY_ID,
1365                 .subvendor      = PCI_ANY_ID,
1366                 .subdevice      = PCI_ANY_ID,
1367                 .init           = pci_ni8430_init,
1368                 .setup          = pci_ni8430_setup,
1369                 .exit           = __devexit_p(pci_ni8430_exit),
1370         },
1371         /*
1372          * Panacom
1373          */
1374         {
1375                 .vendor         = PCI_VENDOR_ID_PANACOM,
1376                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1377                 .subvendor      = PCI_ANY_ID,
1378                 .subdevice      = PCI_ANY_ID,
1379                 .init           = pci_plx9050_init,
1380                 .setup          = pci_default_setup,
1381                 .exit           = __devexit_p(pci_plx9050_exit),
1382         },
1383         {
1384                 .vendor         = PCI_VENDOR_ID_PANACOM,
1385                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1386                 .subvendor      = PCI_ANY_ID,
1387                 .subdevice      = PCI_ANY_ID,
1388                 .init           = pci_plx9050_init,
1389                 .setup          = pci_default_setup,
1390                 .exit           = __devexit_p(pci_plx9050_exit),
1391         },
1392         /*
1393          * PLX
1394          */
1395         {
1396                 .vendor         = PCI_VENDOR_ID_PLX,
1397                 .device         = PCI_DEVICE_ID_PLX_9030,
1398                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1399                 .subdevice      = PCI_ANY_ID,
1400                 .setup          = pci_default_setup,
1401         },
1402         {
1403                 .vendor         = PCI_VENDOR_ID_PLX,
1404                 .device         = PCI_DEVICE_ID_PLX_9050,
1405                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1406                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1407                 .init           = pci_plx9050_init,
1408                 .setup          = pci_default_setup,
1409                 .exit           = __devexit_p(pci_plx9050_exit),
1410         },
1411         {
1412                 .vendor         = PCI_VENDOR_ID_PLX,
1413                 .device         = PCI_DEVICE_ID_PLX_9050,
1414                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1415                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1416                 .init           = pci_plx9050_init,
1417                 .setup          = pci_default_setup,
1418                 .exit           = __devexit_p(pci_plx9050_exit),
1419         },
1420         {
1421                 .vendor         = PCI_VENDOR_ID_PLX,
1422                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1423                 .subvendor      = PCI_VENDOR_ID_PLX,
1424                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1425                 .init           = pci_plx9050_init,
1426                 .setup          = pci_default_setup,
1427                 .exit           = __devexit_p(pci_plx9050_exit),
1428         },
1429         /*
1430          * SBS Technologies, Inc., PMC-OCTALPRO 232
1431          */
1432         {
1433                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1434                 .device         = PCI_DEVICE_ID_OCTPRO,
1435                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1436                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1437                 .init           = sbs_init,
1438                 .setup          = sbs_setup,
1439                 .exit           = __devexit_p(sbs_exit),
1440         },
1441         /*
1442          * SBS Technologies, Inc., PMC-OCTALPRO 422
1443          */
1444         {
1445                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1446                 .device         = PCI_DEVICE_ID_OCTPRO,
1447                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1448                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1449                 .init           = sbs_init,
1450                 .setup          = sbs_setup,
1451                 .exit           = __devexit_p(sbs_exit),
1452         },
1453         /*
1454          * SBS Technologies, Inc., P-Octal 232
1455          */
1456         {
1457                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1458                 .device         = PCI_DEVICE_ID_OCTPRO,
1459                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1460                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1461                 .init           = sbs_init,
1462                 .setup          = sbs_setup,
1463                 .exit           = __devexit_p(sbs_exit),
1464         },
1465         /*
1466          * SBS Technologies, Inc., P-Octal 422
1467          */
1468         {
1469                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1470                 .device         = PCI_DEVICE_ID_OCTPRO,
1471                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1472                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1473                 .init           = sbs_init,
1474                 .setup          = sbs_setup,
1475                 .exit           = __devexit_p(sbs_exit),
1476         },
1477         /*
1478          * SIIG cards - these may be called via parport_serial
1479          */
1480         {
1481                 .vendor         = PCI_VENDOR_ID_SIIG,
1482                 .device         = PCI_ANY_ID,
1483                 .subvendor      = PCI_ANY_ID,
1484                 .subdevice      = PCI_ANY_ID,
1485                 .init           = pci_siig_init,
1486                 .setup          = pci_siig_setup,
1487         },
1488         /*
1489          * Titan cards
1490          */
1491         {
1492                 .vendor         = PCI_VENDOR_ID_TITAN,
1493                 .device         = PCI_DEVICE_ID_TITAN_400L,
1494                 .subvendor      = PCI_ANY_ID,
1495                 .subdevice      = PCI_ANY_ID,
1496                 .setup          = titan_400l_800l_setup,
1497         },
1498         {
1499                 .vendor         = PCI_VENDOR_ID_TITAN,
1500                 .device         = PCI_DEVICE_ID_TITAN_800L,
1501                 .subvendor      = PCI_ANY_ID,
1502                 .subdevice      = PCI_ANY_ID,
1503                 .setup          = titan_400l_800l_setup,
1504         },
1505         /*
1506          * Timedia cards
1507          */
1508         {
1509                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1510                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1511                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1512                 .subdevice      = PCI_ANY_ID,
1513                 .probe          = pci_timedia_probe,
1514                 .init           = pci_timedia_init,
1515                 .setup          = pci_timedia_setup,
1516         },
1517         {
1518                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1519                 .device         = PCI_ANY_ID,
1520                 .subvendor      = PCI_ANY_ID,
1521                 .subdevice      = PCI_ANY_ID,
1522                 .setup          = pci_timedia_setup,
1523         },
1524         /*
1525          * Exar cards
1526          */
1527         {
1528                 .vendor = PCI_VENDOR_ID_EXAR,
1529                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1530                 .subvendor      = PCI_ANY_ID,
1531                 .subdevice      = PCI_ANY_ID,
1532                 .setup          = pci_xr17c154_setup,
1533         },
1534         {
1535                 .vendor = PCI_VENDOR_ID_EXAR,
1536                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1537                 .subvendor      = PCI_ANY_ID,
1538                 .subdevice      = PCI_ANY_ID,
1539                 .setup          = pci_xr17c154_setup,
1540         },
1541         {
1542                 .vendor = PCI_VENDOR_ID_EXAR,
1543                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1544                 .subvendor      = PCI_ANY_ID,
1545                 .subdevice      = PCI_ANY_ID,
1546                 .setup          = pci_xr17c154_setup,
1547         },
1548         /*
1549          * Xircom cards
1550          */
1551         {
1552                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1553                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1554                 .subvendor      = PCI_ANY_ID,
1555                 .subdevice      = PCI_ANY_ID,
1556                 .init           = pci_xircom_init,
1557                 .setup          = pci_default_setup,
1558         },
1559         /*
1560          * Netmos cards - these may be called via parport_serial
1561          */
1562         {
1563                 .vendor         = PCI_VENDOR_ID_NETMOS,
1564                 .device         = PCI_ANY_ID,
1565                 .subvendor      = PCI_ANY_ID,
1566                 .subdevice      = PCI_ANY_ID,
1567                 .init           = pci_netmos_init,
1568                 .setup          = pci_netmos_9900_setup,
1569         },
1570         /*
1571          * For Oxford Semiconductor Tornado based devices
1572          */
1573         {
1574                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1575                 .device         = PCI_ANY_ID,
1576                 .subvendor      = PCI_ANY_ID,
1577                 .subdevice      = PCI_ANY_ID,
1578                 .init           = pci_oxsemi_tornado_init,
1579                 .setup          = pci_default_setup,
1580         },
1581         {
1582                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1583                 .device         = PCI_ANY_ID,
1584                 .subvendor      = PCI_ANY_ID,
1585                 .subdevice      = PCI_ANY_ID,
1586                 .init           = pci_oxsemi_tornado_init,
1587                 .setup          = pci_default_setup,
1588         },
1589         {
1590                 .vendor         = PCI_VENDOR_ID_DIGI,
1591                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1592                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1593                 .subdevice              = PCI_ANY_ID,
1594                 .init                   = pci_oxsemi_tornado_init,
1595                 .setup          = pci_default_setup,
1596         },
1597         {
1598                 .vendor         = PCI_VENDOR_ID_INTEL,
1599                 .device         = 0x8811,
1600                 .subvendor      = PCI_ANY_ID,
1601                 .subdevice      = PCI_ANY_ID,
1602                 .init           = pci_eg20t_init,
1603                 .setup          = pci_default_setup,
1604         },
1605         {
1606                 .vendor         = PCI_VENDOR_ID_INTEL,
1607                 .device         = 0x8812,
1608                 .subvendor      = PCI_ANY_ID,
1609                 .subdevice      = PCI_ANY_ID,
1610                 .init           = pci_eg20t_init,
1611                 .setup          = pci_default_setup,
1612         },
1613         {
1614                 .vendor         = PCI_VENDOR_ID_INTEL,
1615                 .device         = 0x8813,
1616                 .subvendor      = PCI_ANY_ID,
1617                 .subdevice      = PCI_ANY_ID,
1618                 .init           = pci_eg20t_init,
1619                 .setup          = pci_default_setup,
1620         },
1621         {
1622                 .vendor         = PCI_VENDOR_ID_INTEL,
1623                 .device         = 0x8814,
1624                 .subvendor      = PCI_ANY_ID,
1625                 .subdevice      = PCI_ANY_ID,
1626                 .init           = pci_eg20t_init,
1627                 .setup          = pci_default_setup,
1628         },
1629         {
1630                 .vendor         = 0x10DB,
1631                 .device         = 0x8027,
1632                 .subvendor      = PCI_ANY_ID,
1633                 .subdevice      = PCI_ANY_ID,
1634                 .init           = pci_eg20t_init,
1635                 .setup          = pci_default_setup,
1636         },
1637         {
1638                 .vendor         = 0x10DB,
1639                 .device         = 0x8028,
1640                 .subvendor      = PCI_ANY_ID,
1641                 .subdevice      = PCI_ANY_ID,
1642                 .init           = pci_eg20t_init,
1643                 .setup          = pci_default_setup,
1644         },
1645         {
1646                 .vendor         = 0x10DB,
1647                 .device         = 0x8029,
1648                 .subvendor      = PCI_ANY_ID,
1649                 .subdevice      = PCI_ANY_ID,
1650                 .init           = pci_eg20t_init,
1651                 .setup          = pci_default_setup,
1652         },
1653         {
1654                 .vendor         = 0x10DB,
1655                 .device         = 0x800C,
1656                 .subvendor      = PCI_ANY_ID,
1657                 .subdevice      = PCI_ANY_ID,
1658                 .init           = pci_eg20t_init,
1659                 .setup          = pci_default_setup,
1660         },
1661         {
1662                 .vendor         = 0x10DB,
1663                 .device         = 0x800D,
1664                 .subvendor      = PCI_ANY_ID,
1665                 .subdevice      = PCI_ANY_ID,
1666                 .init           = pci_eg20t_init,
1667                 .setup          = pci_default_setup,
1668         },
1669         /*
1670          * Cronyx Omega PCI (PLX-chip based)
1671          */
1672         {
1673                 .vendor         = PCI_VENDOR_ID_PLX,
1674                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1675                 .subvendor      = PCI_ANY_ID,
1676                 .subdevice      = PCI_ANY_ID,
1677                 .setup          = pci_omegapci_setup,
1678          },
1679         /*
1680          * Broadcom TruManage (NetXtreme)
1681          */
1682         {
1683                 .vendor         = PCI_VENDOR_ID_BROADCOM,
1684                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
1685                 .subvendor      = PCI_ANY_ID,
1686                 .subdevice      = PCI_ANY_ID,
1687                 .setup          = pci_brcm_trumanage_setup,
1688         },
1689
1690         /*
1691          * Default "match everything" terminator entry
1692          */
1693         {
1694                 .vendor         = PCI_ANY_ID,
1695                 .device         = PCI_ANY_ID,
1696                 .subvendor      = PCI_ANY_ID,
1697                 .subdevice      = PCI_ANY_ID,
1698                 .setup          = pci_default_setup,
1699         }
1700 };
1701
1702 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1703 {
1704         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1705 }
1706
1707 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1708 {
1709         struct pci_serial_quirk *quirk;
1710
1711         for (quirk = pci_serial_quirks; ; quirk++)
1712                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1713                     quirk_id_matches(quirk->device, dev->device) &&
1714                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1715                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1716                         break;
1717         return quirk;
1718 }
1719
1720 static inline int get_pci_irq(struct pci_dev *dev,
1721                                 const struct pciserial_board *board)
1722 {
1723         if (board->flags & FL_NOIRQ)
1724                 return 0;
1725         else
1726                 return dev->irq;
1727 }
1728
1729 /*
1730  * This is the configuration table for all of the PCI serial boards
1731  * which we support.  It is directly indexed by the pci_board_num_t enum
1732  * value, which is encoded in the pci_device_id PCI probe table's
1733  * driver_data member.
1734  *
1735  * The makeup of these names are:
1736  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1737  *
1738  *  bn          = PCI BAR number
1739  *  bt          = Index using PCI BARs
1740  *  n           = number of serial ports
1741  *  baud        = baud rate
1742  *  offsetinhex = offset for each sequential port (in hex)
1743  *
1744  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1745  *
1746  * Please note: in theory if n = 1, _bt infix should make no difference.
1747  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1748  */
1749 enum pci_board_num_t {
1750         pbn_default = 0,
1751
1752         pbn_b0_1_115200,
1753         pbn_b0_2_115200,
1754         pbn_b0_4_115200,
1755         pbn_b0_5_115200,
1756         pbn_b0_8_115200,
1757
1758         pbn_b0_1_921600,
1759         pbn_b0_2_921600,
1760         pbn_b0_4_921600,
1761
1762         pbn_b0_2_1130000,
1763
1764         pbn_b0_4_1152000,
1765
1766         pbn_b0_2_1843200,
1767         pbn_b0_4_1843200,
1768
1769         pbn_b0_2_1843200_200,
1770         pbn_b0_4_1843200_200,
1771         pbn_b0_8_1843200_200,
1772
1773         pbn_b0_1_4000000,
1774
1775         pbn_b0_bt_1_115200,
1776         pbn_b0_bt_2_115200,
1777         pbn_b0_bt_4_115200,
1778         pbn_b0_bt_8_115200,
1779
1780         pbn_b0_bt_1_460800,
1781         pbn_b0_bt_2_460800,
1782         pbn_b0_bt_4_460800,
1783
1784         pbn_b0_bt_1_921600,
1785         pbn_b0_bt_2_921600,
1786         pbn_b0_bt_4_921600,
1787         pbn_b0_bt_8_921600,
1788
1789         pbn_b1_1_115200,
1790         pbn_b1_2_115200,
1791         pbn_b1_4_115200,
1792         pbn_b1_8_115200,
1793         pbn_b1_16_115200,
1794
1795         pbn_b1_1_921600,
1796         pbn_b1_2_921600,
1797         pbn_b1_4_921600,
1798         pbn_b1_8_921600,
1799
1800         pbn_b1_2_1250000,
1801
1802         pbn_b1_bt_1_115200,
1803         pbn_b1_bt_2_115200,
1804         pbn_b1_bt_4_115200,
1805
1806         pbn_b1_bt_2_921600,
1807
1808         pbn_b1_1_1382400,
1809         pbn_b1_2_1382400,
1810         pbn_b1_4_1382400,
1811         pbn_b1_8_1382400,
1812
1813         pbn_b2_1_115200,
1814         pbn_b2_2_115200,
1815         pbn_b2_4_115200,
1816         pbn_b2_8_115200,
1817
1818         pbn_b2_1_460800,
1819         pbn_b2_4_460800,
1820         pbn_b2_8_460800,
1821         pbn_b2_16_460800,
1822
1823         pbn_b2_1_921600,
1824         pbn_b2_4_921600,
1825         pbn_b2_8_921600,
1826
1827         pbn_b2_8_1152000,
1828
1829         pbn_b2_bt_1_115200,
1830         pbn_b2_bt_2_115200,
1831         pbn_b2_bt_4_115200,
1832
1833         pbn_b2_bt_2_921600,
1834         pbn_b2_bt_4_921600,
1835
1836         pbn_b3_2_115200,
1837         pbn_b3_4_115200,
1838         pbn_b3_8_115200,
1839
1840         pbn_b4_bt_2_921600,
1841         pbn_b4_bt_4_921600,
1842         pbn_b4_bt_8_921600,
1843
1844         /*
1845          * Board-specific versions.
1846          */
1847         pbn_panacom,
1848         pbn_panacom2,
1849         pbn_panacom4,
1850         pbn_exsys_4055,
1851         pbn_plx_romulus,
1852         pbn_oxsemi,
1853         pbn_oxsemi_1_4000000,
1854         pbn_oxsemi_2_4000000,
1855         pbn_oxsemi_4_4000000,
1856         pbn_oxsemi_8_4000000,
1857         pbn_intel_i960,
1858         pbn_sgi_ioc3,
1859         pbn_computone_4,
1860         pbn_computone_6,
1861         pbn_computone_8,
1862         pbn_sbsxrsio,
1863         pbn_exar_XR17C152,
1864         pbn_exar_XR17C154,
1865         pbn_exar_XR17C158,
1866         pbn_exar_ibm_saturn,
1867         pbn_pasemi_1682M,
1868         pbn_ni8430_2,
1869         pbn_ni8430_4,
1870         pbn_ni8430_8,
1871         pbn_ni8430_16,
1872         pbn_ADDIDATA_PCIe_1_3906250,
1873         pbn_ADDIDATA_PCIe_2_3906250,
1874         pbn_ADDIDATA_PCIe_4_3906250,
1875         pbn_ADDIDATA_PCIe_8_3906250,
1876         pbn_ce4100_1_115200,
1877         pbn_omegapci,
1878         pbn_NETMOS9900_2s_115200,
1879         pbn_brcm_trumanage,
1880 };
1881
1882 /*
1883  * uart_offset - the space between channels
1884  * reg_shift   - describes how the UART registers are mapped
1885  *               to PCI memory by the card.
1886  * For example IER register on SBS, Inc. PMC-OctPro is located at
1887  * offset 0x10 from the UART base, while UART_IER is defined as 1
1888  * in include/linux/serial_reg.h,
1889  * see first lines of serial_in() and serial_out() in 8250.c
1890 */
1891
1892 static struct pciserial_board pci_boards[] __devinitdata = {
1893         [pbn_default] = {
1894                 .flags          = FL_BASE0,
1895                 .num_ports      = 1,
1896                 .base_baud      = 115200,
1897                 .uart_offset    = 8,
1898         },
1899         [pbn_b0_1_115200] = {
1900                 .flags          = FL_BASE0,
1901                 .num_ports      = 1,
1902                 .base_baud      = 115200,
1903                 .uart_offset    = 8,
1904         },
1905         [pbn_b0_2_115200] = {
1906                 .flags          = FL_BASE0,
1907                 .num_ports      = 2,
1908                 .base_baud      = 115200,
1909                 .uart_offset    = 8,
1910         },
1911         [pbn_b0_4_115200] = {
1912                 .flags          = FL_BASE0,
1913                 .num_ports      = 4,
1914                 .base_baud      = 115200,
1915                 .uart_offset    = 8,
1916         },
1917         [pbn_b0_5_115200] = {
1918                 .flags          = FL_BASE0,
1919                 .num_ports      = 5,
1920                 .base_baud      = 115200,
1921                 .uart_offset    = 8,
1922         },
1923         [pbn_b0_8_115200] = {
1924                 .flags          = FL_BASE0,
1925                 .num_ports      = 8,
1926                 .base_baud      = 115200,
1927                 .uart_offset    = 8,
1928         },
1929         [pbn_b0_1_921600] = {
1930                 .flags          = FL_BASE0,
1931                 .num_ports      = 1,
1932                 .base_baud      = 921600,
1933                 .uart_offset    = 8,
1934         },
1935         [pbn_b0_2_921600] = {
1936                 .flags          = FL_BASE0,
1937                 .num_ports      = 2,
1938                 .base_baud      = 921600,
1939                 .uart_offset    = 8,
1940         },
1941         [pbn_b0_4_921600] = {
1942                 .flags          = FL_BASE0,
1943                 .num_ports      = 4,
1944                 .base_baud      = 921600,
1945                 .uart_offset    = 8,
1946         },
1947
1948         [pbn_b0_2_1130000] = {
1949                 .flags          = FL_BASE0,
1950                 .num_ports      = 2,
1951                 .base_baud      = 1130000,
1952                 .uart_offset    = 8,
1953         },
1954
1955         [pbn_b0_4_1152000] = {
1956                 .flags          = FL_BASE0,
1957                 .num_ports      = 4,
1958                 .base_baud      = 1152000,
1959                 .uart_offset    = 8,
1960         },
1961
1962         [pbn_b0_2_1843200] = {
1963                 .flags          = FL_BASE0,
1964                 .num_ports      = 2,
1965                 .base_baud      = 1843200,
1966                 .uart_offset    = 8,
1967         },
1968         [pbn_b0_4_1843200] = {
1969                 .flags          = FL_BASE0,
1970                 .num_ports      = 4,
1971                 .base_baud      = 1843200,
1972                 .uart_offset    = 8,
1973         },
1974
1975         [pbn_b0_2_1843200_200] = {
1976                 .flags          = FL_BASE0,
1977                 .num_ports      = 2,
1978                 .base_baud      = 1843200,
1979                 .uart_offset    = 0x200,
1980         },
1981         [pbn_b0_4_1843200_200] = {
1982                 .flags          = FL_BASE0,
1983                 .num_ports      = 4,
1984                 .base_baud      = 1843200,
1985                 .uart_offset    = 0x200,
1986         },
1987         [pbn_b0_8_1843200_200] = {
1988                 .flags          = FL_BASE0,
1989                 .num_ports      = 8,
1990                 .base_baud      = 1843200,
1991                 .uart_offset    = 0x200,
1992         },
1993         [pbn_b0_1_4000000] = {
1994                 .flags          = FL_BASE0,
1995                 .num_ports      = 1,
1996                 .base_baud      = 4000000,
1997                 .uart_offset    = 8,
1998         },
1999
2000         [pbn_b0_bt_1_115200] = {
2001                 .flags          = FL_BASE0|FL_BASE_BARS,
2002                 .num_ports      = 1,
2003                 .base_baud      = 115200,
2004                 .uart_offset    = 8,
2005         },
2006         [pbn_b0_bt_2_115200] = {
2007                 .flags          = FL_BASE0|FL_BASE_BARS,
2008                 .num_ports      = 2,
2009                 .base_baud      = 115200,
2010                 .uart_offset    = 8,
2011         },
2012         [pbn_b0_bt_4_115200] = {
2013                 .flags          = FL_BASE0|FL_BASE_BARS,
2014                 .num_ports      = 4,
2015                 .base_baud      = 115200,
2016                 .uart_offset    = 8,
2017         },
2018         [pbn_b0_bt_8_115200] = {
2019                 .flags          = FL_BASE0|FL_BASE_BARS,
2020                 .num_ports      = 8,
2021                 .base_baud      = 115200,
2022                 .uart_offset    = 8,
2023         },
2024
2025         [pbn_b0_bt_1_460800] = {
2026                 .flags          = FL_BASE0|FL_BASE_BARS,
2027                 .num_ports      = 1,
2028                 .base_baud      = 460800,
2029                 .uart_offset    = 8,
2030         },
2031         [pbn_b0_bt_2_460800] = {
2032                 .flags          = FL_BASE0|FL_BASE_BARS,
2033                 .num_ports      = 2,
2034                 .base_baud      = 460800,
2035                 .uart_offset    = 8,
2036         },
2037         [pbn_b0_bt_4_460800] = {
2038                 .flags          = FL_BASE0|FL_BASE_BARS,
2039                 .num_ports      = 4,
2040                 .base_baud      = 460800,
2041                 .uart_offset    = 8,
2042         },
2043
2044         [pbn_b0_bt_1_921600] = {
2045                 .flags          = FL_BASE0|FL_BASE_BARS,
2046                 .num_ports      = 1,
2047                 .base_baud      = 921600,
2048                 .uart_offset    = 8,
2049         },
2050         [pbn_b0_bt_2_921600] = {
2051                 .flags          = FL_BASE0|FL_BASE_BARS,
2052                 .num_ports      = 2,
2053                 .base_baud      = 921600,
2054                 .uart_offset    = 8,
2055         },
2056         [pbn_b0_bt_4_921600] = {
2057                 .flags          = FL_BASE0|FL_BASE_BARS,
2058                 .num_ports      = 4,
2059                 .base_baud      = 921600,
2060                 .uart_offset    = 8,
2061         },
2062         [pbn_b0_bt_8_921600] = {
2063                 .flags          = FL_BASE0|FL_BASE_BARS,
2064                 .num_ports      = 8,
2065                 .base_baud      = 921600,
2066                 .uart_offset    = 8,
2067         },
2068
2069         [pbn_b1_1_115200] = {
2070                 .flags          = FL_BASE1,
2071                 .num_ports      = 1,
2072                 .base_baud      = 115200,
2073                 .uart_offset    = 8,
2074         },
2075         [pbn_b1_2_115200] = {
2076                 .flags          = FL_BASE1,
2077                 .num_ports      = 2,
2078                 .base_baud      = 115200,
2079                 .uart_offset    = 8,
2080         },
2081         [pbn_b1_4_115200] = {
2082                 .flags          = FL_BASE1,
2083                 .num_ports      = 4,
2084                 .base_baud      = 115200,
2085                 .uart_offset    = 8,
2086         },
2087         [pbn_b1_8_115200] = {
2088                 .flags          = FL_BASE1,
2089                 .num_ports      = 8,
2090                 .base_baud      = 115200,
2091                 .uart_offset    = 8,
2092         },
2093         [pbn_b1_16_115200] = {
2094                 .flags          = FL_BASE1,
2095                 .num_ports      = 16,
2096                 .base_baud      = 115200,
2097                 .uart_offset    = 8,
2098         },
2099
2100         [pbn_b1_1_921600] = {
2101                 .flags          = FL_BASE1,
2102                 .num_ports      = 1,
2103                 .base_baud      = 921600,
2104                 .uart_offset    = 8,
2105         },
2106         [pbn_b1_2_921600] = {
2107                 .flags          = FL_BASE1,
2108                 .num_ports      = 2,
2109                 .base_baud      = 921600,
2110                 .uart_offset    = 8,
2111         },
2112         [pbn_b1_4_921600] = {
2113                 .flags          = FL_BASE1,
2114                 .num_ports      = 4,
2115                 .base_baud      = 921600,
2116                 .uart_offset    = 8,
2117         },
2118         [pbn_b1_8_921600] = {
2119                 .flags          = FL_BASE1,
2120                 .num_ports      = 8,
2121                 .base_baud      = 921600,
2122                 .uart_offset    = 8,
2123         },
2124         [pbn_b1_2_1250000] = {
2125                 .flags          = FL_BASE1,
2126                 .num_ports      = 2,
2127                 .base_baud      = 1250000,
2128                 .uart_offset    = 8,
2129         },
2130
2131         [pbn_b1_bt_1_115200] = {
2132                 .flags          = FL_BASE1|FL_BASE_BARS,
2133                 .num_ports      = 1,
2134                 .base_baud      = 115200,
2135                 .uart_offset    = 8,
2136         },
2137         [pbn_b1_bt_2_115200] = {
2138                 .flags          = FL_BASE1|FL_BASE_BARS,
2139                 .num_ports      = 2,
2140                 .base_baud      = 115200,
2141                 .uart_offset    = 8,
2142         },
2143         [pbn_b1_bt_4_115200] = {
2144                 .flags          = FL_BASE1|FL_BASE_BARS,
2145                 .num_ports      = 4,
2146                 .base_baud      = 115200,
2147                 .uart_offset    = 8,
2148         },
2149
2150         [pbn_b1_bt_2_921600] = {
2151                 .flags          = FL_BASE1|FL_BASE_BARS,
2152                 .num_ports      = 2,
2153                 .base_baud      = 921600,
2154                 .uart_offset    = 8,
2155         },
2156
2157         [pbn_b1_1_1382400] = {
2158                 .flags          = FL_BASE1,
2159                 .num_ports      = 1,
2160                 .base_baud      = 1382400,
2161                 .uart_offset    = 8,
2162         },
2163         [pbn_b1_2_1382400] = {
2164                 .flags          = FL_BASE1,
2165                 .num_ports      = 2,
2166                 .base_baud      = 1382400,
2167                 .uart_offset    = 8,
2168         },
2169         [pbn_b1_4_1382400] = {
2170                 .flags          = FL_BASE1,
2171                 .num_ports      = 4,
2172                 .base_baud      = 1382400,
2173                 .uart_offset    = 8,
2174         },
2175         [pbn_b1_8_1382400] = {
2176                 .flags          = FL_BASE1,
2177                 .num_ports      = 8,
2178                 .base_baud      = 1382400,
2179                 .uart_offset    = 8,
2180         },
2181
2182         [pbn_b2_1_115200] = {
2183                 .flags          = FL_BASE2,
2184                 .num_ports      = 1,
2185                 .base_baud      = 115200,
2186                 .uart_offset    = 8,
2187         },
2188         [pbn_b2_2_115200] = {
2189                 .flags          = FL_BASE2,
2190                 .num_ports      = 2,
2191                 .base_baud      = 115200,
2192                 .uart_offset    = 8,
2193         },
2194         [pbn_b2_4_115200] = {
2195                 .flags          = FL_BASE2,
2196                 .num_ports      = 4,
2197                 .base_baud      = 115200,
2198                 .uart_offset    = 8,
2199         },
2200         [pbn_b2_8_115200] = {
2201                 .flags          = FL_BASE2,
2202                 .num_ports      = 8,
2203                 .base_baud      = 115200,
2204                 .uart_offset    = 8,
2205         },
2206
2207         [pbn_b2_1_460800] = {
2208                 .flags          = FL_BASE2,
2209                 .num_ports      = 1,
2210                 .base_baud      = 460800,
2211                 .uart_offset    = 8,
2212         },
2213         [pbn_b2_4_460800] = {
2214                 .flags          = FL_BASE2,
2215                 .num_ports      = 4,
2216                 .base_baud      = 460800,
2217                 .uart_offset    = 8,
2218         },
2219         [pbn_b2_8_460800] = {
2220                 .flags          = FL_BASE2,
2221                 .num_ports      = 8,
2222                 .base_baud      = 460800,
2223                 .uart_offset    = 8,
2224         },
2225         [pbn_b2_16_460800] = {
2226                 .flags          = FL_BASE2,
2227                 .num_ports      = 16,
2228                 .base_baud      = 460800,
2229                 .uart_offset    = 8,
2230          },
2231
2232         [pbn_b2_1_921600] = {
2233                 .flags          = FL_BASE2,
2234                 .num_ports      = 1,
2235                 .base_baud      = 921600,
2236                 .uart_offset    = 8,
2237         },
2238         [pbn_b2_4_921600] = {
2239                 .flags          = FL_BASE2,
2240                 .num_ports      = 4,
2241                 .base_baud      = 921600,
2242                 .uart_offset    = 8,
2243         },
2244         [pbn_b2_8_921600] = {
2245                 .flags          = FL_BASE2,
2246                 .num_ports      = 8,
2247                 .base_baud      = 921600,
2248                 .uart_offset    = 8,
2249         },
2250
2251         [pbn_b2_8_1152000] = {
2252                 .flags          = FL_BASE2,
2253                 .num_ports      = 8,
2254                 .base_baud      = 1152000,
2255                 .uart_offset    = 8,
2256         },
2257
2258         [pbn_b2_bt_1_115200] = {
2259                 .flags          = FL_BASE2|FL_BASE_BARS,
2260                 .num_ports      = 1,
2261                 .base_baud      = 115200,
2262                 .uart_offset    = 8,
2263         },
2264         [pbn_b2_bt_2_115200] = {
2265                 .flags          = FL_BASE2|FL_BASE_BARS,
2266                 .num_ports      = 2,
2267                 .base_baud      = 115200,
2268                 .uart_offset    = 8,
2269         },
2270         [pbn_b2_bt_4_115200] = {
2271                 .flags          = FL_BASE2|FL_BASE_BARS,
2272                 .num_ports      = 4,
2273                 .base_baud      = 115200,
2274                 .uart_offset    = 8,
2275         },
2276
2277         [pbn_b2_bt_2_921600] = {
2278                 .flags          = FL_BASE2|FL_BASE_BARS,
2279                 .num_ports      = 2,
2280                 .base_baud      = 921600,
2281                 .uart_offset    = 8,
2282         },
2283         [pbn_b2_bt_4_921600] = {
2284                 .flags          = FL_BASE2|FL_BASE_BARS,
2285                 .num_ports      = 4,
2286                 .base_baud      = 921600,
2287                 .uart_offset    = 8,
2288         },
2289
2290         [pbn_b3_2_115200] = {
2291                 .flags          = FL_BASE3,
2292                 .num_ports      = 2,
2293                 .base_baud      = 115200,
2294                 .uart_offset    = 8,
2295         },
2296         [pbn_b3_4_115200] = {
2297                 .flags          = FL_BASE3,
2298                 .num_ports      = 4,
2299                 .base_baud      = 115200,
2300                 .uart_offset    = 8,
2301         },
2302         [pbn_b3_8_115200] = {
2303                 .flags          = FL_BASE3,
2304                 .num_ports      = 8,
2305                 .base_baud      = 115200,
2306                 .uart_offset    = 8,
2307         },
2308
2309         [pbn_b4_bt_2_921600] = {
2310                 .flags          = FL_BASE4,
2311                 .num_ports      = 2,
2312                 .base_baud      = 921600,
2313                 .uart_offset    = 8,
2314         },
2315         [pbn_b4_bt_4_921600] = {
2316                 .flags          = FL_BASE4,
2317                 .num_ports      = 4,
2318                 .base_baud      = 921600,
2319                 .uart_offset    = 8,
2320         },
2321         [pbn_b4_bt_8_921600] = {
2322                 .flags          = FL_BASE4,
2323                 .num_ports      = 8,
2324                 .base_baud      = 921600,
2325                 .uart_offset    = 8,
2326         },
2327
2328         /*
2329          * Entries following this are board-specific.
2330          */
2331
2332         /*
2333          * Panacom - IOMEM
2334          */
2335         [pbn_panacom] = {
2336                 .flags          = FL_BASE2,
2337                 .num_ports      = 2,
2338                 .base_baud      = 921600,
2339                 .uart_offset    = 0x400,
2340                 .reg_shift      = 7,
2341         },
2342         [pbn_panacom2] = {
2343                 .flags          = FL_BASE2|FL_BASE_BARS,
2344                 .num_ports      = 2,
2345                 .base_baud      = 921600,
2346                 .uart_offset    = 0x400,
2347                 .reg_shift      = 7,
2348         },
2349         [pbn_panacom4] = {
2350                 .flags          = FL_BASE2|FL_BASE_BARS,
2351                 .num_ports      = 4,
2352                 .base_baud      = 921600,
2353                 .uart_offset    = 0x400,
2354                 .reg_shift      = 7,
2355         },
2356
2357         [pbn_exsys_4055] = {
2358                 .flags          = FL_BASE2,
2359                 .num_ports      = 4,
2360                 .base_baud      = 115200,
2361                 .uart_offset    = 8,
2362         },
2363
2364         /* I think this entry is broken - the first_offset looks wrong --rmk */
2365         [pbn_plx_romulus] = {
2366                 .flags          = FL_BASE2,
2367                 .num_ports      = 4,
2368                 .base_baud      = 921600,
2369                 .uart_offset    = 8 << 2,
2370                 .reg_shift      = 2,
2371                 .first_offset   = 0x03,
2372         },
2373
2374         /*
2375          * This board uses the size of PCI Base region 0 to
2376          * signal now many ports are available
2377          */
2378         [pbn_oxsemi] = {
2379                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2380                 .num_ports      = 32,
2381                 .base_baud      = 115200,
2382                 .uart_offset    = 8,
2383         },
2384         [pbn_oxsemi_1_4000000] = {
2385                 .flags          = FL_BASE0,
2386                 .num_ports      = 1,
2387                 .base_baud      = 4000000,
2388                 .uart_offset    = 0x200,
2389                 .first_offset   = 0x1000,
2390         },
2391         [pbn_oxsemi_2_4000000] = {
2392                 .flags          = FL_BASE0,
2393                 .num_ports      = 2,
2394                 .base_baud      = 4000000,
2395                 .uart_offset    = 0x200,
2396                 .first_offset   = 0x1000,
2397         },
2398         [pbn_oxsemi_4_4000000] = {
2399                 .flags          = FL_BASE0,
2400                 .num_ports      = 4,
2401                 .base_baud      = 4000000,
2402                 .uart_offset    = 0x200,
2403                 .first_offset   = 0x1000,
2404         },
2405         [pbn_oxsemi_8_4000000] = {
2406                 .flags          = FL_BASE0,
2407                 .num_ports      = 8,
2408                 .base_baud      = 4000000,
2409                 .uart_offset    = 0x200,
2410                 .first_offset   = 0x1000,
2411         },
2412
2413
2414         /*
2415          * EKF addition for i960 Boards form EKF with serial port.
2416          * Max 256 ports.
2417          */
2418         [pbn_intel_i960] = {
2419                 .flags          = FL_BASE0,
2420                 .num_ports      = 32,
2421                 .base_baud      = 921600,
2422                 .uart_offset    = 8 << 2,
2423                 .reg_shift      = 2,
2424                 .first_offset   = 0x10000,
2425         },
2426         [pbn_sgi_ioc3] = {
2427                 .flags          = FL_BASE0|FL_NOIRQ,
2428                 .num_ports      = 1,
2429                 .base_baud      = 458333,
2430                 .uart_offset    = 8,
2431                 .reg_shift      = 0,
2432                 .first_offset   = 0x20178,
2433         },
2434
2435         /*
2436          * Computone - uses IOMEM.
2437          */
2438         [pbn_computone_4] = {
2439                 .flags          = FL_BASE0,
2440                 .num_ports      = 4,
2441                 .base_baud      = 921600,
2442                 .uart_offset    = 0x40,
2443                 .reg_shift      = 2,
2444                 .first_offset   = 0x200,
2445         },
2446         [pbn_computone_6] = {
2447                 .flags          = FL_BASE0,
2448                 .num_ports      = 6,
2449                 .base_baud      = 921600,
2450                 .uart_offset    = 0x40,
2451                 .reg_shift      = 2,
2452                 .first_offset   = 0x200,
2453         },
2454         [pbn_computone_8] = {
2455                 .flags          = FL_BASE0,
2456                 .num_ports      = 8,
2457                 .base_baud      = 921600,
2458                 .uart_offset    = 0x40,
2459                 .reg_shift      = 2,
2460                 .first_offset   = 0x200,
2461         },
2462         [pbn_sbsxrsio] = {
2463                 .flags          = FL_BASE0,
2464                 .num_ports      = 8,
2465                 .base_baud      = 460800,
2466                 .uart_offset    = 256,
2467                 .reg_shift      = 4,
2468         },
2469         /*
2470          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2471          *  Only basic 16550A support.
2472          *  XR17C15[24] are not tested, but they should work.
2473          */
2474         [pbn_exar_XR17C152] = {
2475                 .flags          = FL_BASE0,
2476                 .num_ports      = 2,
2477                 .base_baud      = 921600,
2478                 .uart_offset    = 0x200,
2479         },
2480         [pbn_exar_XR17C154] = {
2481                 .flags          = FL_BASE0,
2482                 .num_ports      = 4,
2483                 .base_baud      = 921600,
2484                 .uart_offset    = 0x200,
2485         },
2486         [pbn_exar_XR17C158] = {
2487                 .flags          = FL_BASE0,
2488                 .num_ports      = 8,
2489                 .base_baud      = 921600,
2490                 .uart_offset    = 0x200,
2491         },
2492         [pbn_exar_ibm_saturn] = {
2493                 .flags          = FL_BASE0,
2494                 .num_ports      = 1,
2495                 .base_baud      = 921600,
2496                 .uart_offset    = 0x200,
2497         },
2498
2499         /*
2500          * PA Semi PWRficient PA6T-1682M on-chip UART
2501          */
2502         [pbn_pasemi_1682M] = {
2503                 .flags          = FL_BASE0,
2504                 .num_ports      = 1,
2505                 .base_baud      = 8333333,
2506         },
2507         /*
2508          * National Instruments 843x
2509          */
2510         [pbn_ni8430_16] = {
2511                 .flags          = FL_BASE0,
2512                 .num_ports      = 16,
2513                 .base_baud      = 3686400,
2514                 .uart_offset    = 0x10,
2515                 .first_offset   = 0x800,
2516         },
2517         [pbn_ni8430_8] = {
2518                 .flags          = FL_BASE0,
2519                 .num_ports      = 8,
2520                 .base_baud      = 3686400,
2521                 .uart_offset    = 0x10,
2522                 .first_offset   = 0x800,
2523         },
2524         [pbn_ni8430_4] = {
2525                 .flags          = FL_BASE0,
2526                 .num_ports      = 4,
2527                 .base_baud      = 3686400,
2528                 .uart_offset    = 0x10,
2529                 .first_offset   = 0x800,
2530         },
2531         [pbn_ni8430_2] = {
2532                 .flags          = FL_BASE0,
2533                 .num_ports      = 2,
2534                 .base_baud      = 3686400,
2535                 .uart_offset    = 0x10,
2536                 .first_offset   = 0x800,
2537         },
2538         /*
2539          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2540          */
2541         [pbn_ADDIDATA_PCIe_1_3906250] = {
2542                 .flags          = FL_BASE0,
2543                 .num_ports      = 1,
2544                 .base_baud      = 3906250,
2545                 .uart_offset    = 0x200,
2546                 .first_offset   = 0x1000,
2547         },
2548         [pbn_ADDIDATA_PCIe_2_3906250] = {
2549                 .flags          = FL_BASE0,
2550                 .num_ports      = 2,
2551                 .base_baud      = 3906250,
2552                 .uart_offset    = 0x200,
2553                 .first_offset   = 0x1000,
2554         },
2555         [pbn_ADDIDATA_PCIe_4_3906250] = {
2556                 .flags          = FL_BASE0,
2557                 .num_ports      = 4,
2558                 .base_baud      = 3906250,
2559                 .uart_offset    = 0x200,
2560                 .first_offset   = 0x1000,
2561         },
2562         [pbn_ADDIDATA_PCIe_8_3906250] = {
2563                 .flags          = FL_BASE0,
2564                 .num_ports      = 8,
2565                 .base_baud      = 3906250,
2566                 .uart_offset    = 0x200,
2567                 .first_offset   = 0x1000,
2568         },
2569         [pbn_ce4100_1_115200] = {
2570                 .flags          = FL_BASE0,
2571                 .num_ports      = 1,
2572                 .base_baud      = 921600,
2573                 .reg_shift      = 2,
2574         },
2575         [pbn_omegapci] = {
2576                 .flags          = FL_BASE0,
2577                 .num_ports      = 8,
2578                 .base_baud      = 115200,
2579                 .uart_offset    = 0x200,
2580         },
2581         [pbn_NETMOS9900_2s_115200] = {
2582                 .flags          = FL_BASE0,
2583                 .num_ports      = 2,
2584                 .base_baud      = 115200,
2585         },
2586         [pbn_brcm_trumanage] = {
2587                 .flags          = FL_BASE0,
2588                 .num_ports      = 1,
2589                 .reg_shift      = 2,
2590                 .base_baud      = 115200,
2591         },
2592 };
2593
2594 static const struct pci_device_id softmodem_blacklist[] = {
2595         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2596         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2597         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2598 };
2599
2600 /*
2601  * Given a complete unknown PCI device, try to use some heuristics to
2602  * guess what the configuration might be, based on the pitiful PCI
2603  * serial specs.  Returns 0 on success, 1 on failure.
2604  */
2605 static int __devinit
2606 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2607 {
2608         const struct pci_device_id *blacklist;
2609         int num_iomem, num_port, first_port = -1, i;
2610
2611         /*
2612          * If it is not a communications device or the programming
2613          * interface is greater than 6, give up.
2614          *
2615          * (Should we try to make guesses for multiport serial devices
2616          * later?)
2617          */
2618         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2619              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2620             (dev->class & 0xff) > 6)
2621                 return -ENODEV;
2622
2623         /*
2624          * Do not access blacklisted devices that are known not to
2625          * feature serial ports.
2626          */
2627         for (blacklist = softmodem_blacklist;
2628              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2629              blacklist++) {
2630                 if (dev->vendor == blacklist->vendor &&
2631                     dev->device == blacklist->device)
2632                         return -ENODEV;
2633         }
2634
2635         num_iomem = num_port = 0;
2636         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2637                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2638                         num_port++;
2639                         if (first_port == -1)
2640                                 first_port = i;
2641                 }
2642                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2643                         num_iomem++;
2644         }
2645
2646         /*
2647          * If there is 1 or 0 iomem regions, and exactly one port,
2648          * use it.  We guess the number of ports based on the IO
2649          * region size.
2650          */
2651         if (num_iomem <= 1 && num_port == 1) {
2652                 board->flags = first_port;
2653                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2654                 return 0;
2655         }
2656
2657         /*
2658          * Now guess if we've got a board which indexes by BARs.
2659          * Each IO BAR should be 8 bytes, and they should follow
2660          * consecutively.
2661          */
2662         first_port = -1;
2663         num_port = 0;
2664         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2665                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2666                     pci_resource_len(dev, i) == 8 &&
2667                     (first_port == -1 || (first_port + num_port) == i)) {
2668                         num_port++;
2669                         if (first_port == -1)
2670                                 first_port = i;
2671                 }
2672         }
2673
2674         if (num_port > 1) {
2675                 board->flags = first_port | FL_BASE_BARS;
2676                 board->num_ports = num_port;
2677                 return 0;
2678         }
2679
2680         return -ENODEV;
2681 }
2682
2683 static inline int
2684 serial_pci_matches(const struct pciserial_board *board,
2685                    const struct pciserial_board *guessed)
2686 {
2687         return
2688             board->num_ports == guessed->num_ports &&
2689             board->base_baud == guessed->base_baud &&
2690             board->uart_offset == guessed->uart_offset &&
2691             board->reg_shift == guessed->reg_shift &&
2692             board->first_offset == guessed->first_offset;
2693 }
2694
2695 struct serial_private *
2696 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2697 {
2698         struct uart_port serial_port;
2699         struct serial_private *priv;
2700         struct pci_serial_quirk *quirk;
2701         int rc, nr_ports, i;
2702
2703         nr_ports = board->num_ports;
2704
2705         /*
2706          * Find an init and setup quirks.
2707          */
2708         quirk = find_quirk(dev);
2709
2710         /*
2711          * Run the new-style initialization function.
2712          * The initialization function returns:
2713          *  <0  - error
2714          *   0  - use board->num_ports
2715          *  >0  - number of ports
2716          */
2717         if (quirk->init) {
2718                 rc = quirk->init(dev);
2719                 if (rc < 0) {
2720                         priv = ERR_PTR(rc);
2721                         goto err_out;
2722                 }
2723                 if (rc)
2724                         nr_ports = rc;
2725         }
2726
2727         priv = kzalloc(sizeof(struct serial_private) +
2728                        sizeof(unsigned int) * nr_ports,
2729                        GFP_KERNEL);
2730         if (!priv) {
2731                 priv = ERR_PTR(-ENOMEM);
2732                 goto err_deinit;
2733         }
2734
2735         priv->dev = dev;
2736         priv->quirk = quirk;
2737
2738         memset(&serial_port, 0, sizeof(struct uart_port));
2739         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2740         serial_port.uartclk = board->base_baud * 16;
2741         serial_port.irq = get_pci_irq(dev, board);
2742         serial_port.dev = &dev->dev;
2743
2744         for (i = 0; i < nr_ports; i++) {
2745                 if (quirk->setup(priv, board, &serial_port, i))
2746                         break;
2747
2748 #ifdef SERIAL_DEBUG_PCI
2749                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2750                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2751 #endif
2752
2753                 priv->line[i] = serial8250_register_port(&serial_port);
2754                 if (priv->line[i] < 0) {
2755                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2756                         break;
2757                 }
2758         }
2759         priv->nr = i;
2760         return priv;
2761
2762 err_deinit:
2763         if (quirk->exit)
2764                 quirk->exit(dev);
2765 err_out:
2766         return priv;
2767 }
2768 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2769
2770 void pciserial_remove_ports(struct serial_private *priv)
2771 {
2772         struct pci_serial_quirk *quirk;
2773         int i;
2774
2775         for (i = 0; i < priv->nr; i++)
2776                 serial8250_unregister_port(priv->line[i]);
2777
2778         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2779                 if (priv->remapped_bar[i])
2780                         iounmap(priv->remapped_bar[i]);
2781                 priv->remapped_bar[i] = NULL;
2782         }
2783
2784         /*
2785          * Find the exit quirks.
2786          */
2787         quirk = find_quirk(priv->dev);
2788         if (quirk->exit)
2789                 quirk->exit(priv->dev);
2790
2791         kfree(priv);
2792 }
2793 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2794
2795 void pciserial_suspend_ports(struct serial_private *priv)
2796 {
2797         int i;
2798
2799         for (i = 0; i < priv->nr; i++)
2800                 if (priv->line[i] >= 0)
2801                         serial8250_suspend_port(priv->line[i]);
2802 }
2803 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2804
2805 void pciserial_resume_ports(struct serial_private *priv)
2806 {
2807         int i;
2808
2809         /*
2810          * Ensure that the board is correctly configured.
2811          */
2812         if (priv->quirk->init)
2813                 priv->quirk->init(priv->dev);
2814
2815         for (i = 0; i < priv->nr; i++)
2816                 if (priv->line[i] >= 0)
2817                         serial8250_resume_port(priv->line[i]);
2818 }
2819 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2820
2821 /*
2822  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2823  * to the arrangement of serial ports on a PCI card.
2824  */
2825 static int __devinit
2826 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2827 {
2828         struct pci_serial_quirk *quirk;
2829         struct serial_private *priv;
2830         const struct pciserial_board *board;
2831         struct pciserial_board tmp;
2832         int rc;
2833
2834         quirk = find_quirk(dev);
2835         if (quirk->probe) {
2836                 rc = quirk->probe(dev);
2837                 if (rc)
2838                         return rc;
2839         }
2840
2841         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2842                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2843                         ent->driver_data);
2844                 return -EINVAL;
2845         }
2846
2847         board = &pci_boards[ent->driver_data];
2848
2849         rc = pci_enable_device(dev);
2850         pci_save_state(dev);
2851         if (rc)
2852                 return rc;
2853
2854         if (ent->driver_data == pbn_default) {
2855                 /*
2856                  * Use a copy of the pci_board entry for this;
2857                  * avoid changing entries in the table.
2858                  */
2859                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2860                 board = &tmp;
2861
2862                 /*
2863                  * We matched one of our class entries.  Try to
2864                  * determine the parameters of this board.
2865                  */
2866                 rc = serial_pci_guess_board(dev, &tmp);
2867                 if (rc)
2868                         goto disable;
2869         } else {
2870                 /*
2871                  * We matched an explicit entry.  If we are able to
2872                  * detect this boards settings with our heuristic,
2873                  * then we no longer need this entry.
2874                  */
2875                 memcpy(&tmp, &pci_boards[pbn_default],
2876                        sizeof(struct pciserial_board));
2877                 rc = serial_pci_guess_board(dev, &tmp);
2878                 if (rc == 0 && serial_pci_matches(board, &tmp))
2879                         moan_device("Redundant entry in serial pci_table.",
2880                                     dev);
2881         }
2882
2883         priv = pciserial_init_ports(dev, board);
2884         if (!IS_ERR(priv)) {
2885                 pci_set_drvdata(dev, priv);
2886                 return 0;
2887         }
2888
2889         rc = PTR_ERR(priv);
2890
2891  disable:
2892         pci_disable_device(dev);
2893         return rc;
2894 }
2895
2896 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2897 {
2898         struct serial_private *priv = pci_get_drvdata(dev);
2899
2900         pci_set_drvdata(dev, NULL);
2901
2902         pciserial_remove_ports(priv);
2903
2904         pci_disable_device(dev);
2905 }
2906
2907 #ifdef CONFIG_PM
2908 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2909 {
2910         struct serial_private *priv = pci_get_drvdata(dev);
2911
2912         if (priv)
2913                 pciserial_suspend_ports(priv);
2914
2915         pci_save_state(dev);
2916         pci_set_power_state(dev, pci_choose_state(dev, state));
2917         return 0;
2918 }
2919
2920 static int pciserial_resume_one(struct pci_dev *dev)
2921 {
2922         int err;
2923         struct serial_private *priv = pci_get_drvdata(dev);
2924
2925         pci_set_power_state(dev, PCI_D0);
2926         pci_restore_state(dev);
2927
2928         if (priv) {
2929                 /*
2930                  * The device may have been disabled.  Re-enable it.
2931                  */
2932                 err = pci_enable_device(dev);
2933                 /* FIXME: We cannot simply error out here */
2934                 if (err)
2935                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2936                 pciserial_resume_ports(priv);
2937         }
2938         return 0;
2939 }
2940 #endif
2941
2942 static struct pci_device_id serial_pci_tbl[] = {
2943         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2944         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2945                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2946                 pbn_b2_8_921600 },
2947         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2948                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2949                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2950                 pbn_b1_8_1382400 },
2951         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2952                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2953                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2954                 pbn_b1_4_1382400 },
2955         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2956                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2957                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2958                 pbn_b1_2_1382400 },
2959         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2960                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2961                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2962                 pbn_b1_8_1382400 },
2963         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2964                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2965                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2966                 pbn_b1_4_1382400 },
2967         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2968                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2969                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2970                 pbn_b1_2_1382400 },
2971         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2972                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2973                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2974                 pbn_b1_8_921600 },
2975         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2976                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2977                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2978                 pbn_b1_8_921600 },
2979         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2980                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2981                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2982                 pbn_b1_4_921600 },
2983         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2984                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2985                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2986                 pbn_b1_4_921600 },
2987         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2988                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2989                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2990                 pbn_b1_2_921600 },
2991         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2992                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2993                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2994                 pbn_b1_8_921600 },
2995         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2996                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2997                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2998                 pbn_b1_8_921600 },
2999         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3000                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3001                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3002                 pbn_b1_4_921600 },
3003         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3004                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3005                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3006                 pbn_b1_2_1250000 },
3007         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3008                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3009                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3010                 pbn_b0_2_1843200 },
3011         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3012                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3013                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3014                 pbn_b0_4_1843200 },
3015         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3016                 PCI_VENDOR_ID_AFAVLAB,
3017                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3018                 pbn_b0_4_1152000 },
3019         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3020                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3021                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3022                 pbn_b0_2_1843200_200 },
3023         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3024                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3025                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3026                 pbn_b0_4_1843200_200 },
3027         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3028                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3029                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3030                 pbn_b0_8_1843200_200 },
3031         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3032                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3033                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3034                 pbn_b0_2_1843200_200 },
3035         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3036                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3037                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3038                 pbn_b0_4_1843200_200 },
3039         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3040                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3041                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3042                 pbn_b0_8_1843200_200 },
3043         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3044                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3045                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3046                 pbn_b0_2_1843200_200 },
3047         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3048                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3049                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3050                 pbn_b0_4_1843200_200 },
3051         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3052                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3053                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3054                 pbn_b0_8_1843200_200 },
3055         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3056                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3057                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3058                 pbn_b0_2_1843200_200 },
3059         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3060                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3061                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3062                 pbn_b0_4_1843200_200 },
3063         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3064                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3065                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3066                 pbn_b0_8_1843200_200 },
3067         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3068                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3069                 0, 0, pbn_exar_ibm_saturn },
3070
3071         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3072                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3073                 pbn_b2_bt_1_115200 },
3074         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3075                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3076                 pbn_b2_bt_2_115200 },
3077         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3078                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3079                 pbn_b2_bt_4_115200 },
3080         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3082                 pbn_b2_bt_2_115200 },
3083         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3084                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3085                 pbn_b2_bt_4_115200 },
3086         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3087                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3088                 pbn_b2_8_115200 },
3089         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3090                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3091                 pbn_b2_8_460800 },
3092         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3093                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3094                 pbn_b2_8_115200 },
3095
3096         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3098                 pbn_b2_bt_2_115200 },
3099         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3101                 pbn_b2_bt_2_921600 },
3102         /*
3103          * VScom SPCOM800, from sl@s.pl
3104          */
3105         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3107                 pbn_b2_8_921600 },
3108         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3110                 pbn_b2_4_921600 },
3111         /* Unknown card - subdevice 0x1584 */
3112         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3113                 PCI_VENDOR_ID_PLX,
3114                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3115                 pbn_b2_4_115200 },
3116         /* Unknown card - subdevice 0x1588 */
3117         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3118                 PCI_VENDOR_ID_PLX,
3119                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3120                 pbn_b2_8_115200 },
3121         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3122                 PCI_SUBVENDOR_ID_KEYSPAN,
3123                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3124                 pbn_panacom },
3125         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3126                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3127                 pbn_panacom4 },
3128         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3130                 pbn_panacom2 },
3131         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3132                 PCI_VENDOR_ID_ESDGMBH,
3133                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3134                 pbn_b2_4_115200 },
3135         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3136                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3137                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3138                 pbn_b2_4_460800 },
3139         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3140                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3141                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3142                 pbn_b2_8_460800 },
3143         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3144                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3145                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3146                 pbn_b2_16_460800 },
3147         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3148                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3149                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3150                 pbn_b2_16_460800 },
3151         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3152                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3153                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3154                 pbn_b2_4_460800 },
3155         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3156                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3157                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3158                 pbn_b2_8_460800 },
3159         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3160                 PCI_SUBVENDOR_ID_EXSYS,
3161                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3162                 pbn_exsys_4055 },
3163         /*
3164          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3165          * (Exoray@isys.ca)
3166          */
3167         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3168                 0x10b5, 0x106a, 0, 0,
3169                 pbn_plx_romulus },
3170         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172                 pbn_b1_4_115200 },
3173         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175                 pbn_b1_2_115200 },
3176         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178                 pbn_b1_8_115200 },
3179         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181                 pbn_b1_8_115200 },
3182         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3183                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3184                 0, 0,
3185                 pbn_b0_4_921600 },
3186         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3187                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3188                 0, 0,
3189                 pbn_b0_4_1152000 },
3190         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3191                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3192                 pbn_b0_bt_2_921600 },
3193
3194                 /*
3195                  * The below card is a little controversial since it is the
3196                  * subject of a PCI vendor/device ID clash.  (See
3197                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3198                  * For now just used the hex ID 0x950a.
3199                  */
3200         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3201                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3202                 0, 0, pbn_b0_2_115200 },
3203         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3204                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3205                 0, 0, pbn_b0_2_115200 },
3206         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3207                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208                 pbn_b0_2_1130000 },
3209         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3210                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3211                 pbn_b0_1_921600 },
3212         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3213                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214                 pbn_b0_4_115200 },
3215         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217                 pbn_b0_bt_2_921600 },
3218         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3219                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3220                 pbn_b2_8_1152000 },
3221
3222         /*
3223          * Oxford Semiconductor Inc. Tornado PCI express device range.
3224          */
3225         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3226                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227                 pbn_b0_1_4000000 },
3228         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230                 pbn_b0_1_4000000 },
3231         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233                 pbn_oxsemi_1_4000000 },
3234         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236                 pbn_oxsemi_1_4000000 },
3237         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239                 pbn_b0_1_4000000 },
3240         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242                 pbn_b0_1_4000000 },
3243         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245                 pbn_oxsemi_1_4000000 },
3246         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248                 pbn_oxsemi_1_4000000 },
3249         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251                 pbn_b0_1_4000000 },
3252         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254                 pbn_b0_1_4000000 },
3255         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257                 pbn_b0_1_4000000 },
3258         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_b0_1_4000000 },
3261         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263                 pbn_oxsemi_2_4000000 },
3264         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266                 pbn_oxsemi_2_4000000 },
3267         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269                 pbn_oxsemi_4_4000000 },
3270         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272                 pbn_oxsemi_4_4000000 },
3273         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275                 pbn_oxsemi_8_4000000 },
3276         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3277                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278                 pbn_oxsemi_8_4000000 },
3279         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281                 pbn_oxsemi_1_4000000 },
3282         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284                 pbn_oxsemi_1_4000000 },
3285         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287                 pbn_oxsemi_1_4000000 },
3288         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290                 pbn_oxsemi_1_4000000 },
3291         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293                 pbn_oxsemi_1_4000000 },
3294         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3295                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296                 pbn_oxsemi_1_4000000 },
3297         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299                 pbn_oxsemi_1_4000000 },
3300         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3301                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302                 pbn_oxsemi_1_4000000 },
3303         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3304                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305                 pbn_oxsemi_1_4000000 },
3306         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3307                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3308                 pbn_oxsemi_1_4000000 },
3309         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3310                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311                 pbn_oxsemi_1_4000000 },
3312         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3313                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314                 pbn_oxsemi_1_4000000 },
3315         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3316                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317                 pbn_oxsemi_1_4000000 },
3318         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3319                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320                 pbn_oxsemi_1_4000000 },
3321         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3322                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3323                 pbn_oxsemi_1_4000000 },
3324         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3325                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326                 pbn_oxsemi_1_4000000 },
3327         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3328                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3329                 pbn_oxsemi_1_4000000 },
3330         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3331                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3332                 pbn_oxsemi_1_4000000 },
3333         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3334                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3335                 pbn_oxsemi_1_4000000 },
3336         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3337                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3338                 pbn_oxsemi_1_4000000 },
3339         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3340                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3341                 pbn_oxsemi_1_4000000 },
3342         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3343                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3344                 pbn_oxsemi_1_4000000 },
3345         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3346                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3347                 pbn_oxsemi_1_4000000 },
3348         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3349                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3350                 pbn_oxsemi_1_4000000 },
3351         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3352                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3353                 pbn_oxsemi_1_4000000 },
3354         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3355                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3356                 pbn_oxsemi_1_4000000 },
3357         /*
3358          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3359          */
3360         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3361                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3362                 pbn_oxsemi_1_4000000 },
3363         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3364                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3365                 pbn_oxsemi_2_4000000 },
3366         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3367                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3368                 pbn_oxsemi_4_4000000 },
3369         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3370                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3371                 pbn_oxsemi_8_4000000 },
3372
3373         /*
3374          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3375          */
3376         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3377                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3378                 pbn_oxsemi_2_4000000 },
3379
3380         /*
3381          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3382          * from skokodyn@yahoo.com
3383          */
3384         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3385                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3386                 pbn_sbsxrsio },
3387         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3388                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3389                 pbn_sbsxrsio },
3390         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3391                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3392                 pbn_sbsxrsio },
3393         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3394                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3395                 pbn_sbsxrsio },
3396
3397         /*
3398          * Digitan DS560-558, from jimd@esoft.com
3399          */
3400         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3401                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3402                 pbn_b1_1_115200 },
3403
3404         /*
3405          * Titan Electronic cards
3406          *  The 400L and 800L have a custom setup quirk.
3407          */
3408         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3409                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410                 pbn_b0_1_921600 },
3411         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3412                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413                 pbn_b0_2_921600 },
3414         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3415                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416                 pbn_b0_4_921600 },
3417         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3418                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419                 pbn_b0_4_921600 },
3420         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3421                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422                 pbn_b1_1_921600 },
3423         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3424                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425                 pbn_b1_bt_2_921600 },
3426         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3427                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428                 pbn_b0_bt_4_921600 },
3429         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3430                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431                 pbn_b0_bt_8_921600 },
3432         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3433                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434                 pbn_b4_bt_2_921600 },
3435         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3436                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437                 pbn_b4_bt_4_921600 },
3438         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3439                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440                 pbn_b4_bt_8_921600 },
3441         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3442                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443                 pbn_b0_4_921600 },
3444         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3445                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446                 pbn_b0_4_921600 },
3447         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3448                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449                 pbn_b0_4_921600 },
3450         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3451                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452                 pbn_oxsemi_1_4000000 },
3453         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3454                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455                 pbn_oxsemi_2_4000000 },
3456         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458                 pbn_oxsemi_4_4000000 },
3459         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3460                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461                 pbn_oxsemi_8_4000000 },
3462         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3463                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464                 pbn_oxsemi_2_4000000 },
3465         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3466                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3467                 pbn_oxsemi_2_4000000 },
3468
3469         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471                 pbn_b2_1_460800 },
3472         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474                 pbn_b2_1_460800 },
3475         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477                 pbn_b2_1_460800 },
3478         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480                 pbn_b2_bt_2_921600 },
3481         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483                 pbn_b2_bt_2_921600 },
3484         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486                 pbn_b2_bt_2_921600 },
3487         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489                 pbn_b2_bt_4_921600 },
3490         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492                 pbn_b2_bt_4_921600 },
3493         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495                 pbn_b2_bt_4_921600 },
3496         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498                 pbn_b0_1_921600 },
3499         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501                 pbn_b0_1_921600 },
3502         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3504                 pbn_b0_1_921600 },
3505         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507                 pbn_b0_bt_2_921600 },
3508         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510                 pbn_b0_bt_2_921600 },
3511         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3513                 pbn_b0_bt_2_921600 },
3514         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3516                 pbn_b0_bt_4_921600 },
3517         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3519                 pbn_b0_bt_4_921600 },
3520         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522                 pbn_b0_bt_4_921600 },
3523         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525                 pbn_b0_bt_8_921600 },
3526         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3527                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3528                 pbn_b0_bt_8_921600 },
3529         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3530                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3531                 pbn_b0_bt_8_921600 },
3532
3533         /*
3534          * Computone devices submitted by Doug McNash dmcnash@computone.com
3535          */
3536         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3537                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3538                 0, 0, pbn_computone_4 },
3539         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3540                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3541                 0, 0, pbn_computone_8 },
3542         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3543                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3544                 0, 0, pbn_computone_6 },
3545
3546         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3547                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548                 pbn_oxsemi },
3549         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3550                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3551                 pbn_b0_bt_1_921600 },
3552
3553         /*
3554          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3555          */
3556         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3557                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3558                 pbn_b0_bt_8_115200 },
3559         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3560                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3561                 pbn_b0_bt_8_115200 },
3562
3563         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3564                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3565                 pbn_b0_bt_2_115200 },
3566         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568                 pbn_b0_bt_2_115200 },
3569         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571                 pbn_b0_bt_2_115200 },
3572         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574                 pbn_b0_bt_2_115200 },
3575         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577                 pbn_b0_bt_2_115200 },
3578         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580                 pbn_b0_bt_4_460800 },
3581         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583                 pbn_b0_bt_4_460800 },
3584         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586                 pbn_b0_bt_2_460800 },
3587         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589                 pbn_b0_bt_2_460800 },
3590         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3591                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592                 pbn_b0_bt_2_460800 },
3593         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3594                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3595                 pbn_b0_bt_1_115200 },
3596         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3597                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3598                 pbn_b0_bt_1_460800 },
3599
3600         /*
3601          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3602          * Cards are identified by their subsystem vendor IDs, which
3603          * (in hex) match the model number.
3604          *
3605          * Note that JC140x are RS422/485 cards which require ox950
3606          * ACR = 0x10, and as such are not currently fully supported.
3607          */
3608         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3609                 0x1204, 0x0004, 0, 0,
3610                 pbn_b0_4_921600 },
3611         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3612                 0x1208, 0x0004, 0, 0,
3613                 pbn_b0_4_921600 },
3614 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3615                 0x1402, 0x0002, 0, 0,
3616                 pbn_b0_2_921600 }, */
3617 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3618                 0x1404, 0x0004, 0, 0,
3619                 pbn_b0_4_921600 }, */
3620         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3621                 0x1208, 0x0004, 0, 0,
3622                 pbn_b0_4_921600 },
3623
3624         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3625                 0x1204, 0x0004, 0, 0,
3626                 pbn_b0_4_921600 },
3627         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3628                 0x1208, 0x0004, 0, 0,
3629                 pbn_b0_4_921600 },
3630         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3631                 0x1208, 0x0004, 0, 0,
3632                 pbn_b0_4_921600 },
3633         /*
3634          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3635          */
3636         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3637                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3638                 pbn_b1_1_1382400 },
3639
3640         /*
3641          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3642          */
3643         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3644                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3645                 pbn_b1_1_1382400 },
3646
3647         /*
3648          * RAStel 2 port modem, gerg@moreton.com.au
3649          */
3650         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3651                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3652                 pbn_b2_bt_2_115200 },
3653
3654         /*
3655          * EKF addition for i960 Boards form EKF with serial port
3656          */
3657         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3658                 0xE4BF, PCI_ANY_ID, 0, 0,
3659                 pbn_intel_i960 },
3660
3661         /*
3662          * Xircom Cardbus/Ethernet combos
3663          */
3664         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3665                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3666                 pbn_b0_1_115200 },
3667         /*
3668          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3669          */
3670         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3671                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3672                 pbn_b0_1_115200 },
3673
3674         /*
3675          * Untested PCI modems, sent in from various folks...
3676          */
3677
3678         /*
3679          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3680          */
3681         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3682                 0x1048, 0x1500, 0, 0,
3683                 pbn_b1_1_115200 },
3684
3685         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3686                 0xFF00, 0, 0, 0,
3687                 pbn_sgi_ioc3 },
3688
3689         /*
3690          * HP Diva card
3691          */
3692         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3693                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3694                 pbn_b1_1_115200 },
3695         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3696                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3697                 pbn_b0_5_115200 },
3698         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3699                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3700                 pbn_b2_1_115200 },
3701
3702         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3703                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3704                 pbn_b3_2_115200 },
3705         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3706                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3707                 pbn_b3_4_115200 },
3708         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3709                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3710                 pbn_b3_8_115200 },
3711
3712         /*
3713          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3714          */
3715         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3716                 PCI_ANY_ID, PCI_ANY_ID,
3717                 0,
3718                 0, pbn_exar_XR17C152 },
3719         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3720                 PCI_ANY_ID, PCI_ANY_ID,
3721                 0,
3722                 0, pbn_exar_XR17C154 },
3723         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3724                 PCI_ANY_ID, PCI_ANY_ID,
3725                 0,
3726                 0, pbn_exar_XR17C158 },
3727
3728         /*
3729          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3730          */
3731         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3732                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3733                 pbn_b0_1_115200 },
3734         /*
3735          * ITE
3736          */
3737         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3738                 PCI_ANY_ID, PCI_ANY_ID,
3739                 0, 0,
3740                 pbn_b1_bt_1_115200 },
3741
3742         /*
3743          * IntaShield IS-200
3744          */
3745         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3747                 pbn_b2_2_115200 },
3748         /*
3749          * IntaShield IS-400
3750          */
3751         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3753                 pbn_b2_4_115200 },
3754         /*
3755          * Perle PCI-RAS cards
3756          */
3757         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3758                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3759                 0, 0, pbn_b2_4_921600 },
3760         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3761                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3762                 0, 0, pbn_b2_8_921600 },
3763
3764         /*
3765          * Mainpine series cards: Fairly standard layout but fools
3766          * parts of the autodetect in some cases and uses otherwise
3767          * unmatched communications subclasses in the PCI Express case
3768          */
3769
3770         {       /* RockForceDUO */
3771                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3772                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3773                 0, 0, pbn_b0_2_115200 },
3774         {       /* RockForceQUATRO */
3775                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3776                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3777                 0, 0, pbn_b0_4_115200 },
3778         {       /* RockForceDUO+ */
3779                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3780                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3781                 0, 0, pbn_b0_2_115200 },
3782         {       /* RockForceQUATRO+ */
3783                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3784                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3785                 0, 0, pbn_b0_4_115200 },
3786         {       /* RockForce+ */
3787                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3788                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3789                 0, 0, pbn_b0_2_115200 },
3790         {       /* RockForce+ */
3791                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3792                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3793                 0, 0, pbn_b0_4_115200 },
3794         {       /* RockForceOCTO+ */
3795                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3796                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3797                 0, 0, pbn_b0_8_115200 },
3798         {       /* RockForceDUO+ */
3799                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3800                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3801                 0, 0, pbn_b0_2_115200 },
3802         {       /* RockForceQUARTRO+ */
3803                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3804                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3805                 0, 0, pbn_b0_4_115200 },
3806         {       /* RockForceOCTO+ */
3807                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3808                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3809                 0, 0, pbn_b0_8_115200 },
3810         {       /* RockForceD1 */
3811                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3812                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3813                 0, 0, pbn_b0_1_115200 },
3814         {       /* RockForceF1 */
3815                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3816                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3817                 0, 0, pbn_b0_1_115200 },
3818         {       /* RockForceD2 */
3819                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3820                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3821                 0, 0, pbn_b0_2_115200 },
3822         {       /* RockForceF2 */
3823                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3824                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3825                 0, 0, pbn_b0_2_115200 },
3826         {       /* RockForceD4 */
3827                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3828                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3829                 0, 0, pbn_b0_4_115200 },
3830         {       /* RockForceF4 */
3831                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3832                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3833                 0, 0, pbn_b0_4_115200 },
3834         {       /* RockForceD8 */
3835                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3836                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3837                 0, 0, pbn_b0_8_115200 },
3838         {       /* RockForceF8 */
3839                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3840                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3841                 0, 0, pbn_b0_8_115200 },
3842         {       /* IQ Express D1 */
3843                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3844                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3845                 0, 0, pbn_b0_1_115200 },
3846         {       /* IQ Express F1 */
3847                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3848                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3849                 0, 0, pbn_b0_1_115200 },
3850         {       /* IQ Express D2 */
3851                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3852                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3853                 0, 0, pbn_b0_2_115200 },
3854         {       /* IQ Express F2 */
3855                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3856                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3857                 0, 0, pbn_b0_2_115200 },
3858         {       /* IQ Express D4 */
3859                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3860                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3861                 0, 0, pbn_b0_4_115200 },
3862         {       /* IQ Express F4 */
3863                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3864                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3865                 0, 0, pbn_b0_4_115200 },
3866         {       /* IQ Express D8 */
3867                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3868                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3869                 0, 0, pbn_b0_8_115200 },
3870         {       /* IQ Express F8 */
3871                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3872                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3873                 0, 0, pbn_b0_8_115200 },
3874
3875
3876         /*
3877          * PA Semi PA6T-1682M on-chip UART
3878          */
3879         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3880                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3881                 pbn_pasemi_1682M },
3882
3883         /*
3884          * National Instruments
3885          */
3886         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3888                 pbn_b1_16_115200 },
3889         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891                 pbn_b1_8_115200 },
3892         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3894                 pbn_b1_bt_4_115200 },
3895         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3897                 pbn_b1_bt_2_115200 },
3898         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3900                 pbn_b1_bt_4_115200 },
3901         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3903                 pbn_b1_bt_2_115200 },
3904         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3906                 pbn_b1_16_115200 },
3907         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3909                 pbn_b1_8_115200 },
3910         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3912                 pbn_b1_bt_4_115200 },
3913         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3915                 pbn_b1_bt_2_115200 },
3916         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3918                 pbn_b1_bt_4_115200 },
3919         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3921                 pbn_b1_bt_2_115200 },
3922         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3924                 pbn_ni8430_2 },
3925         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3926                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3927                 pbn_ni8430_2 },
3928         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3929                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3930                 pbn_ni8430_4 },
3931         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3932                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3933                 pbn_ni8430_4 },
3934         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3935                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3936                 pbn_ni8430_8 },
3937         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3939                 pbn_ni8430_8 },
3940         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3941                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3942                 pbn_ni8430_16 },
3943         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3945                 pbn_ni8430_16 },
3946         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948                 pbn_ni8430_2 },
3949         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3951                 pbn_ni8430_2 },
3952         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3953                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3954                 pbn_ni8430_4 },
3955         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3956                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3957                 pbn_ni8430_4 },
3958
3959         /*
3960         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3961         */
3962         {       PCI_VENDOR_ID_ADDIDATA,
3963                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3964                 PCI_ANY_ID,
3965                 PCI_ANY_ID,
3966                 0,
3967                 0,
3968                 pbn_b0_4_115200 },
3969
3970         {       PCI_VENDOR_ID_ADDIDATA,
3971                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3972                 PCI_ANY_ID,
3973                 PCI_ANY_ID,
3974                 0,
3975                 0,
3976                 pbn_b0_2_115200 },
3977
3978         {       PCI_VENDOR_ID_ADDIDATA,
3979                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3980                 PCI_ANY_ID,
3981                 PCI_ANY_ID,
3982                 0,
3983                 0,
3984                 pbn_b0_1_115200 },
3985
3986         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3987                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3988                 PCI_ANY_ID,
3989                 PCI_ANY_ID,
3990                 0,
3991                 0,
3992                 pbn_b1_8_115200 },
3993
3994         {       PCI_VENDOR_ID_ADDIDATA,
3995                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3996                 PCI_ANY_ID,
3997                 PCI_ANY_ID,
3998                 0,
3999                 0,
4000                 pbn_b0_4_115200 },
4001
4002         {       PCI_VENDOR_ID_ADDIDATA,
4003                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4004                 PCI_ANY_ID,
4005                 PCI_ANY_ID,
4006                 0,
4007                 0,
4008                 pbn_b0_2_115200 },
4009
4010         {       PCI_VENDOR_ID_ADDIDATA,
4011                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4012                 PCI_ANY_ID,
4013                 PCI_ANY_ID,
4014                 0,
4015                 0,
4016                 pbn_b0_1_115200 },
4017
4018         {       PCI_VENDOR_ID_ADDIDATA,
4019                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4020                 PCI_ANY_ID,
4021                 PCI_ANY_ID,
4022                 0,
4023                 0,
4024                 pbn_b0_4_115200 },
4025
4026         {       PCI_VENDOR_ID_ADDIDATA,
4027                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4028                 PCI_ANY_ID,
4029                 PCI_ANY_ID,
4030                 0,
4031                 0,
4032                 pbn_b0_2_115200 },
4033
4034         {       PCI_VENDOR_ID_ADDIDATA,
4035                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4036                 PCI_ANY_ID,
4037                 PCI_ANY_ID,
4038                 0,
4039                 0,
4040                 pbn_b0_1_115200 },
4041
4042         {       PCI_VENDOR_ID_ADDIDATA,
4043                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4044                 PCI_ANY_ID,
4045                 PCI_ANY_ID,
4046                 0,
4047                 0,
4048                 pbn_b0_8_115200 },
4049
4050         {       PCI_VENDOR_ID_ADDIDATA,
4051                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4052                 PCI_ANY_ID,
4053                 PCI_ANY_ID,
4054                 0,
4055                 0,
4056                 pbn_ADDIDATA_PCIe_4_3906250 },
4057
4058         {       PCI_VENDOR_ID_ADDIDATA,
4059                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4060                 PCI_ANY_ID,
4061                 PCI_ANY_ID,
4062                 0,
4063                 0,
4064                 pbn_ADDIDATA_PCIe_2_3906250 },
4065
4066         {       PCI_VENDOR_ID_ADDIDATA,
4067                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4068                 PCI_ANY_ID,
4069                 PCI_ANY_ID,
4070                 0,
4071                 0,
4072                 pbn_ADDIDATA_PCIe_1_3906250 },
4073
4074         {       PCI_VENDOR_ID_ADDIDATA,
4075                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4076                 PCI_ANY_ID,
4077                 PCI_ANY_ID,
4078                 0,
4079                 0,
4080                 pbn_ADDIDATA_PCIe_8_3906250 },
4081
4082         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4083                 PCI_VENDOR_ID_IBM, 0x0299,
4084                 0, 0, pbn_b0_bt_2_115200 },
4085
4086         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4087                 0xA000, 0x1000,
4088                 0, 0, pbn_b0_1_115200 },
4089
4090         /* the 9901 is a rebranded 9912 */
4091         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4092                 0xA000, 0x1000,
4093                 0, 0, pbn_b0_1_115200 },
4094
4095         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4096                 0xA000, 0x1000,
4097                 0, 0, pbn_b0_1_115200 },
4098
4099         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4100                 0xA000, 0x1000,
4101                 0, 0, pbn_b0_1_115200 },
4102
4103         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4104                 0xA000, 0x1000,
4105                 0, 0, pbn_b0_1_115200 },
4106
4107         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4108                 0xA000, 0x3002,
4109                 0, 0, pbn_NETMOS9900_2s_115200 },
4110
4111         /*
4112          * Best Connectivity and Rosewill PCI Multi I/O cards
4113          */
4114
4115         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4116                 0xA000, 0x1000,
4117                 0, 0, pbn_b0_1_115200 },
4118
4119         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4120                 0xA000, 0x3002,
4121                 0, 0, pbn_b0_bt_2_115200 },
4122
4123         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4124                 0xA000, 0x3004,
4125                 0, 0, pbn_b0_bt_4_115200 },
4126         /* Intel CE4100 */
4127         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4128                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4129                 pbn_ce4100_1_115200 },
4130
4131         /*
4132          * Cronyx Omega PCI
4133          */
4134         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4135                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4136                 pbn_omegapci },
4137
4138         /*
4139          * Broadcom TruManage
4140          */
4141         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4142                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143                 pbn_brcm_trumanage },
4144
4145         /*
4146          * These entries match devices with class COMMUNICATION_SERIAL,
4147          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4148          */
4149         {       PCI_ANY_ID, PCI_ANY_ID,
4150                 PCI_ANY_ID, PCI_ANY_ID,
4151                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4152                 0xffff00, pbn_default },
4153         {       PCI_ANY_ID, PCI_ANY_ID,
4154                 PCI_ANY_ID, PCI_ANY_ID,
4155                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4156                 0xffff00, pbn_default },
4157         {       PCI_ANY_ID, PCI_ANY_ID,
4158                 PCI_ANY_ID, PCI_ANY_ID,
4159                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4160                 0xffff00, pbn_default },
4161         { 0, }
4162 };
4163
4164 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4165                                                 pci_channel_state_t state)
4166 {
4167         struct serial_private *priv = pci_get_drvdata(dev);
4168
4169         if (state == pci_channel_io_perm_failure)
4170                 return PCI_ERS_RESULT_DISCONNECT;
4171
4172         if (priv)
4173                 pciserial_suspend_ports(priv);
4174
4175         pci_disable_device(dev);
4176
4177         return PCI_ERS_RESULT_NEED_RESET;
4178 }
4179
4180 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4181 {
4182         int rc;
4183
4184         rc = pci_enable_device(dev);
4185
4186         if (rc)
4187                 return PCI_ERS_RESULT_DISCONNECT;
4188
4189         pci_restore_state(dev);
4190         pci_save_state(dev);
4191
4192         return PCI_ERS_RESULT_RECOVERED;
4193 }
4194
4195 static void serial8250_io_resume(struct pci_dev *dev)
4196 {
4197         struct serial_private *priv = pci_get_drvdata(dev);
4198
4199         if (priv)
4200                 pciserial_resume_ports(priv);
4201 }
4202
4203 static struct pci_error_handlers serial8250_err_handler = {
4204         .error_detected = serial8250_io_error_detected,
4205         .slot_reset = serial8250_io_slot_reset,
4206         .resume = serial8250_io_resume,
4207 };
4208
4209 static struct pci_driver serial_pci_driver = {
4210         .name           = "serial",
4211         .probe          = pciserial_init_one,
4212         .remove         = __devexit_p(pciserial_remove_one),
4213 #ifdef CONFIG_PM
4214         .suspend        = pciserial_suspend_one,
4215         .resume         = pciserial_resume_one,
4216 #endif
4217         .id_table       = serial_pci_tbl,
4218         .err_handler    = &serial8250_err_handler,
4219 };
4220
4221 static int __init serial8250_pci_init(void)
4222 {
4223         return pci_register_driver(&serial_pci_driver);
4224 }
4225
4226 static void __exit serial8250_pci_exit(void)
4227 {
4228         pci_unregister_driver(&serial_pci_driver);
4229 }
4230
4231 module_init(serial8250_pci_init);
4232 module_exit(serial8250_pci_exit);
4233
4234 MODULE_LICENSE("GPL");
4235 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4236 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);