drivers/tty/serial/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/bitops.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26
  27 #include "8250.h"
  28
  29 #undef SERIAL_DEBUG_PCI
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*probe)(struct pci_dev *dev);
  43         int     (*init)(struct pci_dev *dev);
  44         int     (*setup)(struct serial_private *,
  45                          const struct pciserial_board *,
  46                          struct uart_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static int pci_default_setup(struct serial_private*,
  61           const struct pciserial_board*, struct uart_port*, int);
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING
  66                "%s: %s\n"
  67                "Please send the output of lspci -vv, this\n"
  68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  69                "manufacturer and name of serial board or\n"
  70                "modem board to rmk+serial@arm.linux.org.uk.\n",
  71                pci_name(dev), str, dev->vendor, dev->device,
  72                dev->subsystem_vendor, dev->subsystem_device);
  73 }
  74
  75 static int
  76 setup_port(struct serial_private *priv, struct uart_port *port,
  77            int bar, int offset, int regshift)
  78 {
  79         struct pci_dev *dev = priv->dev;
  80         unsigned long base, len;
  81
  82         if (bar >= PCI_NUM_BAR_RESOURCES)
  83                 return -EINVAL;
  84
  85         base = pci_resource_start(dev, bar);
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 len =  pci_resource_len(dev, bar);
  89
  90                 if (!priv->remapped_bar[bar])
  91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  92                 if (!priv->remapped_bar[bar])
  93                         return -ENOMEM;
  94
  95                 port->iotype = UPIO_MEM;
  96                 port->iobase = 0;
  97                 port->mapbase = base + offset;
  98                 port->membase = priv->remapped_bar[bar] + offset;
  99                 port->regshift = regshift;
 100         } else {
 101                 port->iotype = UPIO_PORT;
 102                 port->iobase = base + offset;
 103                 port->mapbase = 0;
 104                 port->membase = NULL;
 105                 port->regshift = 0;
 106         }
 107         return 0;
 108 }
 109
 110 /*
 111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 112  */
 113 static int addidata_apci7800_setup(struct serial_private *priv,
 114                                 const struct pciserial_board *board,
 115                                 struct uart_port *port, int idx)
 116 {
 117         unsigned int bar = 0, offset = board->first_offset;
 118         bar = FL_GET_BASE(board->flags);
 119
 120         if (idx < 2) {
 121                 offset += idx * board->uart_offset;
 122         } else if ((idx >= 2) && (idx < 4)) {
 123                 bar += 1;
 124                 offset += ((idx - 2) * board->uart_offset);
 125         } else if ((idx >= 4) && (idx < 6)) {
 126                 bar += 2;
 127                 offset += ((idx - 4) * board->uart_offset);
 128         } else if (idx >= 6) {
 129                 bar += 3;
 130                 offset += ((idx - 6) * board->uart_offset);
 131         }
 132
 133         return setup_port(priv, port, bar, offset, board->reg_shift);
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 142               struct uart_port *port, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(priv, port, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 183                 rc = 1;
 184                 break;
 185         }
 186
 187         return rc;
 188 }
 189
 190 /*
 191  * HP's Diva chip puts the 4th/5th serial port further out, and
 192  * some serial ports are supposed to be hidden on certain models.
 193  */
 194 static int
 195 pci_hp_diva_setup(struct serial_private *priv,
 196                 const struct pciserial_board *board,
 197                 struct uart_port *port, int idx)
 198 {
 199         unsigned int offset = board->first_offset;
 200         unsigned int bar = FL_GET_BASE(board->flags);
 201
 202         switch (priv->dev->subsystem_device) {
 203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 204                 if (idx == 3)
 205                         idx++;
 206                 break;
 207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 208                 if (idx > 0)
 209                         idx++;
 210                 if (idx > 2)
 211                         idx++;
 212                 break;
 213         }
 214         if (idx > 2)
 215                 offset = 0x18;
 216
 217         offset += idx * board->uart_offset;
 218
 219         return setup_port(priv, port, bar, offset, board->reg_shift);
 220 }
 221
 222 /*
 223  * Added for EKF Intel i960 serial boards
 224  */
 225 static int pci_inteli960ni_init(struct pci_dev *dev)
 226 {
 227         unsigned long oldval;
 228
 229         if (!(dev->subsystem_device & 0x1000))
 230                 return -ENODEV;
 231
 232         /* is firmware started? */
 233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 234         if (oldval == 0x00001000L) { /* RESET value */
 235                 printk(KERN_DEBUG "Local i960 firmware missing");
 236                 return -ENODEV;
 237         }
 238         return 0;
 239 }
 240
 241 /*
 242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 243  * that the card interrupt be explicitly enabled or disabled.  This
 244  * seems to be mainly needed on card using the PLX which also use I/O
 245  * mapped memory.
 246  */
 247 static int pci_plx9050_init(struct pci_dev *dev)
 248 {
 249         u8 irq_config;
 250         void __iomem *p;
 251
 252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 253                 moan_device("no memory in bar 0", dev);
 254                 return 0;
 255         }
 256
 257         irq_config = 0x41;
 258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 260                 irq_config = 0x43;
 261
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         /*
 274          * enable/disable interrupts
 275          */
 276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 277         if (p == NULL)
 278                 return -ENOMEM;
 279         writel(irq_config, p + 0x4c);
 280
 281         /*
 282          * Read the register back to ensure that it took effect.
 283          */
 284         readl(p + 0x4c);
 285         iounmap(p);
 286
 287         return 0;
 288 }
 289
 290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 291 {
 292         u8 __iomem *p;
 293
 294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 295                 return;
 296
 297         /*
 298          * disable interrupts
 299          */
 300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 301         if (p != NULL) {
 302                 writel(0, p + 0x4c);
 303
 304                 /*
 305                  * Read the register back to ensure that it took effect.
 306                  */
 307                 readl(p + 0x4c);
 308                 iounmap(p);
 309         }
 310 }
 311
 312 #define NI8420_INT_ENABLE_REG   0x38
 313 #define NI8420_INT_ENABLE_BIT   0x2000
 314
 315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 316 {
 317         void __iomem *p;
 318         unsigned long base, len;
 319         unsigned int bar = 0;
 320
 321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 322                 moan_device("no memory in bar", dev);
 323                 return;
 324         }
 325
 326         base = pci_resource_start(dev, bar);
 327         len =  pci_resource_len(dev, bar);
 328         p = ioremap_nocache(base, len);
 329         if (p == NULL)
 330                 return;
 331
 332         /* Disable the CPU Interrupt */
 333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 334                p + NI8420_INT_ENABLE_REG);
 335         iounmap(p);
 336 }
 337
 338
 339 /* MITE registers */
 340 #define MITE_IOWBSR1    0xc4
 341 #define MITE_IOWCR1     0xf4
 342 #define MITE_LCIMR1     0x08
 343 #define MITE_LCIMR2     0x10
 344
 345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 346
 347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 348 {
 349         void __iomem *p;
 350         unsigned long base, len;
 351         unsigned int bar = 0;
 352
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357
 358         base = pci_resource_start(dev, bar);
 359         len =  pci_resource_len(dev, bar);
 360         p = ioremap_nocache(base, len);
 361         if (p == NULL)
 362                 return;
 363
 364         /* Disable the CPU Interrupt */
 365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366         iounmap(p);
 367 }
 368
 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370 static int
 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                 struct uart_port *port, int idx)
 373 {
 374         unsigned int bar, offset = board->first_offset;
 375
 376         bar = 0;
 377
 378         if (idx < 4) {
 379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                 offset += idx * board->uart_offset;
 381         } else if (idx < 8) {
 382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                 offset += idx * board->uart_offset + 0xC00;
 384         } else /* we have only 8 ports on PMC-OCTALPRO */
 385                 return 1;
 386
 387         return setup_port(priv, port, bar, offset, board->reg_shift);
 388 }
 389
 390 /*
 391 * This does initialization for PMC OCTALPRO cards:
 392 * maps the device memory, resets the UARTs (needed, bc
 393 * if the module is removed and inserted again, the card
 394 * is in the sleep mode) and enables global interrupt.
 395 */
 396
 397 /* global control register offset for SBS PMC-OctalPro */
 398 #define OCT_REG_CR_OFF          0x500
 399
 400 static int sbs_init(struct pci_dev *dev)
 401 {
 402         u8 __iomem *p;
 403
 404         p = pci_ioremap_bar(dev, 0);
 405
 406         if (p == NULL)
 407                 return -ENOMEM;
 408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409         writeb(0x10, p + OCT_REG_CR_OFF);
 410         udelay(50);
 411         writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413         /* Set bit-2 (INTENABLE) of Control Register */
 414         writeb(0x4, p + OCT_REG_CR_OFF);
 415         iounmap(p);
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Disables the global interrupt of PMC-OctalPro
 422  */
 423
 424 static void __devexit sbs_exit(struct pci_dev *dev)
 425 {
 426         u8 __iomem *p;
 427
 428         p = pci_ioremap_bar(dev, 0);
 429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430         if (p != NULL)
 431                 writeb(0, p + OCT_REG_CR_OFF);
 432         iounmap(p);
 433 }
 434
 435 /*
 436  * SIIG serial cards have an PCI interface chip which also controls
 437  * the UART clocking frequency. Each UART can be clocked independently
 438  * (except cards equipped with 4 UARTs) and initial clocking settings
 439  * are stored in the EEPROM chip. It can cause problems because this
 440  * version of serial driver doesn't support differently clocked UART's
 441  * on single PCI card. To prevent this, initialization functions set
 442  * high frequency clocking for all UART's on given card. It is safe (I
 443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444  * with other OSes (like M$ DOS).
 445  *
 446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447  *
 448  * There is two family of SIIG serial cards with different PCI
 449  * interface chip and different configuration methods:
 450  *     - 10x cards have control registers in IO and/or memory space;
 451  *     - 20x cards have control registers in standard PCI configuration space.
 452  *
 453  * Note: all 10x cards have PCI device ids 0x10..
 454  *       all 20x cards have PCI device ids 0x20..
 455  *
 456  * There are also Quartet Serial cards which use Oxford Semiconductor
 457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458  *
 459  * Note: some SIIG cards are probed by the parport_serial object.
 460  */
 461
 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465 static int pci_siig10x_init(struct pci_dev *dev)
 466 {
 467         u16 data;
 468         void __iomem *p;
 469
 470         switch (dev->device & 0xfff8) {
 471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                 data = 0xffdf;
 473                 break;
 474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                 data = 0xf7ff;
 476                 break;
 477         default:                        /* 1S1P, 4S */
 478                 data = 0xfffb;
 479                 break;
 480         }
 481
 482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 483         if (p == NULL)
 484                 return -ENOMEM;
 485
 486         writew(readw(p + 0x28) & data, p + 0x28);
 487         readw(p + 0x28);
 488         iounmap(p);
 489         return 0;
 490 }
 491
 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495 static int pci_siig20x_init(struct pci_dev *dev)
 496 {
 497         u8 data;
 498
 499         /* Change clock frequency for the first UART. */
 500         pci_read_config_byte(dev, 0x6f, &data);
 501         pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503         /* If this card has 2 UART, we have to do the same with second UART. */
 504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                 pci_read_config_byte(dev, 0x73, &data);
 507                 pci_write_config_byte(dev, 0x73, data & 0xef);
 508         }
 509         return 0;
 510 }
 511
 512 static int pci_siig_init(struct pci_dev *dev)
 513 {
 514         unsigned int type = dev->device & 0xff00;
 515
 516         if (type == 0x1000)
 517                 return pci_siig10x_init(dev);
 518         else if (type == 0x2000)
 519                 return pci_siig20x_init(dev);
 520
 521         moan_device("Unknown SIIG card", dev);
 522         return -ENODEV;
 523 }
 524
 525 static int pci_siig_setup(struct serial_private *priv,
 526                           const struct pciserial_board *board,
 527                           struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531         if (idx > 3) {
 532                 bar = 4;
 533                 offset = (idx - 4) * 8;
 534         }
 535
 536         return setup_port(priv, port, bar, offset, 0);
 537 }
 538
 539 /*
 540  * Timedia has an explosion of boards, and to avoid the PCI table from
 541  * growing *huge*, we use this function to collapse some 70 entries
 542  * in the PCI table into one, for sanity's and compactness's sake.
 543  */
 544 static const unsigned short timedia_single_port[] = {
 545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546 };
 547
 548 static const unsigned short timedia_dual_port[] = {
 549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553         0xD079, 0
 554 };
 555
 556 static const unsigned short timedia_quad_port[] = {
 557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560         0xB157, 0
 561 };
 562
 563 static const unsigned short timedia_eight_port[] = {
 564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566 };
 567
 568 static const struct timedia_struct {
 569         int num;
 570         const unsigned short *ids;
 571 } timedia_data[] = {
 572         { 1, timedia_single_port },
 573         { 2, timedia_dual_port },
 574         { 4, timedia_quad_port },
 575         { 8, timedia_eight_port }
 576 };
 577
 578 /*
 579  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 580  * listing them individually, this driver merely grabs them all with
 581  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 582  * and should be left free to be claimed by parport_serial instead.
 583  */
 584 static int pci_timedia_probe(struct pci_dev *dev)
 585 {
 586         /*
 587          * Check the third digit of the subdevice ID
 588          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 589          */
 590         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 591                 dev_info(&dev->dev,
 592                         "ignoring Timedia subdevice %04x for parport_serial\n",
 593                         dev->subsystem_device);
 594                 return -ENODEV;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int pci_timedia_init(struct pci_dev *dev)
 601 {
 602         const unsigned short *ids;
 603         int i, j;
 604
 605         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 606                 ids = timedia_data[i].ids;
 607                 for (j = 0; ids[j]; j++)
 608                         if (dev->subsystem_device == ids[j])
 609                                 return timedia_data[i].num;
 610         }
 611         return 0;
 612 }
 613
 614 /*
 615  * Timedia/SUNIX uses a mixture of BARs and offsets
 616  * Ugh, this is ugly as all hell --- TYT
 617  */
 618 static int
 619 pci_timedia_setup(struct serial_private *priv,
 620                   const struct pciserial_board *board,
 621                   struct uart_port *port, int idx)
 622 {
 623         unsigned int bar = 0, offset = board->first_offset;
 624
 625         switch (idx) {
 626         case 0:
 627                 bar = 0;
 628                 break;
 629         case 1:
 630                 offset = board->uart_offset;
 631                 bar = 0;
 632                 break;
 633         case 2:
 634                 bar = 1;
 635                 break;
 636         case 3:
 637                 offset = board->uart_offset;
 638                 /* FALLTHROUGH */
 639         case 4: /* BAR 2 */
 640         case 5: /* BAR 3 */
 641         case 6: /* BAR 4 */
 642         case 7: /* BAR 5 */
 643                 bar = idx - 2;
 644         }
 645
 646         return setup_port(priv, port, bar, offset, board->reg_shift);
 647 }
 648
 649 /*
 650  * Some Titan cards are also a little weird
 651  */
 652 static int
 653 titan_400l_800l_setup(struct serial_private *priv,
 654                       const struct pciserial_board *board,
 655                       struct uart_port *port, int idx)
 656 {
 657         unsigned int bar, offset = board->first_offset;
 658
 659         switch (idx) {
 660         case 0:
 661                 bar = 1;
 662                 break;
 663         case 1:
 664                 bar = 2;
 665                 break;
 666         default:
 667                 bar = 4;
 668                 offset = (idx - 2) * board->uart_offset;
 669         }
 670
 671         return setup_port(priv, port, bar, offset, board->reg_shift);
 672 }
 673
 674 static int pci_xircom_init(struct pci_dev *dev)
 675 {
 676         msleep(100);
 677         return 0;
 678 }
 679
 680 static int pci_ni8420_init(struct pci_dev *dev)
 681 {
 682         void __iomem *p;
 683         unsigned long base, len;
 684         unsigned int bar = 0;
 685
 686         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 687                 moan_device("no memory in bar", dev);
 688                 return 0;
 689         }
 690
 691         base = pci_resource_start(dev, bar);
 692         len =  pci_resource_len(dev, bar);
 693         p = ioremap_nocache(base, len);
 694         if (p == NULL)
 695                 return -ENOMEM;
 696
 697         /* Enable CPU Interrupt */
 698         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 699                p + NI8420_INT_ENABLE_REG);
 700
 701         iounmap(p);
 702         return 0;
 703 }
 704
 705 #define MITE_IOWBSR1_WSIZE      0xa
 706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 707 #define MITE_IOWBSR1_WENAB      (1 << 7)
 708 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 709 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 711
 712 static int pci_ni8430_init(struct pci_dev *dev)
 713 {
 714         void __iomem *p;
 715         unsigned long base, len;
 716         u32 device_window;
 717         unsigned int bar = 0;
 718
 719         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 720                 moan_device("no memory in bar", dev);
 721                 return 0;
 722         }
 723
 724         base = pci_resource_start(dev, bar);
 725         len =  pci_resource_len(dev, bar);
 726         p = ioremap_nocache(base, len);
 727         if (p == NULL)
 728                 return -ENOMEM;
 729
 730         /* Set device window address and size in BAR0 */
 731         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 732                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 733         writel(device_window, p + MITE_IOWBSR1);
 734
 735         /* Set window access to go to RAMSEL IO address space */
 736         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 737                p + MITE_IOWCR1);
 738
 739         /* Enable IO Bus Interrupt 0 */
 740         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 741
 742         /* Enable CPU Interrupt */
 743         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 744
 745         iounmap(p);
 746         return 0;
 747 }
 748
 749 /* UART Port Control Register */
 750 #define NI8430_PORTCON  0x0f
 751 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 752
 753 static int
 754 pci_ni8430_setup(struct serial_private *priv,
 755                  const struct pciserial_board *board,
 756                  struct uart_port *port, int idx)
 757 {
 758         void __iomem *p;
 759         unsigned long base, len;
 760         unsigned int bar, offset = board->first_offset;
 761
 762         if (idx >= board->num_ports)
 763                 return 1;
 764
 765         bar = FL_GET_BASE(board->flags);
 766         offset += idx * board->uart_offset;
 767
 768         base = pci_resource_start(priv->dev, bar);
 769         len =  pci_resource_len(priv->dev, bar);
 770         p = ioremap_nocache(base, len);
 771
 772         /* enable the transceiver */
 773         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 774                p + offset + NI8430_PORTCON);
 775
 776         iounmap(p);
 777
 778         return setup_port(priv, port, bar, offset, board->reg_shift);
 779 }
 780
 781 static int pci_netmos_9900_setup(struct serial_private *priv,
 782                                 const struct pciserial_board *board,
 783                                 struct uart_port *port, int idx)
 784 {
 785         unsigned int bar;
 786
 787         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 788                 /* netmos apparently orders BARs by datasheet layout, so serial
 789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 790                  */
 791                 bar = 3 * idx;
 792
 793                 return setup_port(priv, port, bar, 0, board->reg_shift);
 794         } else {
 795                 return pci_default_setup(priv, board, port, idx);
 796         }
 797 }
 798
 799 /* the 99xx series comes with a range of device IDs and a variety
 800  * of capabilities:
 801  *
 802  * 9900 has varying capabilities and can cascade to sub-controllers
 803  *   (cascading should be purely internal)
 804  * 9904 is hardwired with 4 serial ports
 805  * 9912 and 9922 are hardwired with 2 serial ports
 806  */
 807 static int pci_netmos_9900_numports(struct pci_dev *dev)
 808 {
 809         unsigned int c = dev->class;
 810         unsigned int pi;
 811         unsigned short sub_serports;
 812
 813         pi = (c & 0xff);
 814
 815         if (pi == 2) {
 816                 return 1;
 817         } else if ((pi == 0) &&
 818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 819                 /* two possibilities: 0x30ps encodes number of parallel and
 820                  * serial ports, or 0x1000 indicates *something*. This is not
 821                  * immediately obvious, since the 2s1p+4s configuration seems
 822                  * to offer all functionality on functions 0..2, while still
 823                  * advertising the same function 3 as the 4s+2s1p config.
 824                  */
 825                 sub_serports = dev->subsystem_device & 0xf;
 826                 if (sub_serports > 0) {
 827                         return sub_serports;
 828                 } else {
 829                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                         return 0;
 831                 }
 832         }
 833
 834         moan_device("unknown NetMos/Mostech program interface", dev);
 835         return 0;
 836 }
 837
 838 static int pci_netmos_init(struct pci_dev *dev)
 839 {
 840         /* subdevice 0x00PS means <P> parallel, <S> serial */
 841         unsigned int num_serial = dev->subsystem_device & 0xf;
 842
 843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 845                 return 0;
 846
 847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 848                         dev->subsystem_device == 0x0299)
 849                 return 0;
 850
 851         switch (dev->device) { /* FALLTHROUGH on all */
 852                 case PCI_DEVICE_ID_NETMOS_9904:
 853                 case PCI_DEVICE_ID_NETMOS_9912:
 854                 case PCI_DEVICE_ID_NETMOS_9922:
 855                 case PCI_DEVICE_ID_NETMOS_9900:
 856                         num_serial = pci_netmos_9900_numports(dev);
 857                         break;
 858
 859                 default:
 860                         if (num_serial == 0 ) {
 861                                 moan_device("unknown NetMos/Mostech device", dev);
 862                         }
 863         }
 864
 865         if (num_serial == 0)
 866                 return -ENODEV;
 867
 868         return num_serial;
 869 }
 870
 871 /*
 872  * These chips are available with optionally one parallel port and up to
 873  * two serial ports. Unfortunately they all have the same product id.
 874  *
 875  * Basic configuration is done over a region of 32 I/O ports. The base
 876  * ioport is called INTA or INTC, depending on docs/other drivers.
 877  *
 878  * The region of the 32 I/O ports is configured in POSIO0R...
 879  */
 880
 881 /* registers */
 882 #define ITE_887x_MISCR          0x9c
 883 #define ITE_887x_INTCBAR        0x78
 884 #define ITE_887x_UARTBAR        0x7c
 885 #define ITE_887x_PS0BAR         0x10
 886 #define ITE_887x_POSIO0         0x60
 887
 888 /* I/O space size */
 889 #define ITE_887x_IOSIZE         32
 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 895 #define ITE_887x_POSIO_SPEED            (3 << 29)
 896 /* enable IO_Space bit */
 897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 898
 899 static int pci_ite887x_init(struct pci_dev *dev)
 900 {
 901         /* inta_addr are the configuration addresses of the ITE */
 902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 903                                                         0x200, 0x280, 0 };
 904         int ret, i, type;
 905         struct resource *iobase = NULL;
 906         u32 miscr, uartbar, ioport;
 907
 908         /* search for the base-ioport */
 909         i = 0;
 910         while (inta_addr[i] && iobase == NULL) {
 911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 912                                                                 "ite887x");
 913                 if (iobase != NULL) {
 914                         /* write POSIO0R - speed | size | ioport */
 915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 918                         /* write INTCBAR - ioport */
 919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 920                                                                 inta_addr[i]);
 921                         ret = inb(inta_addr[i]);
 922                         if (ret != 0xff) {
 923                                 /* ioport connected */
 924                                 break;
 925                         }
 926                         release_region(iobase->start, ITE_887x_IOSIZE);
 927                         iobase = NULL;
 928                 }
 929                 i++;
 930         }
 931
 932         if (!inta_addr[i]) {
 933                 printk(KERN_ERR "ite887x: could not find iobase\n");
 934                 return -ENODEV;
 935         }
 936
 937         /* start of undocumented type checking (see parport_pc.c) */
 938         type = inb(iobase->start + 0x18) & 0x0f;
 939
 940         switch (type) {
 941         case 0x2:       /* ITE8871 (1P) */
 942         case 0xa:       /* ITE8875 (1P) */
 943                 ret = 0;
 944                 break;
 945         case 0xe:       /* ITE8872 (2S1P) */
 946                 ret = 2;
 947                 break;
 948         case 0x6:       /* ITE8873 (1S) */
 949                 ret = 1;
 950                 break;
 951         case 0x8:       /* ITE8874 (2S) */
 952                 ret = 2;
 953                 break;
 954         default:
 955                 moan_device("Unknown ITE887x", dev);
 956                 ret = -ENODEV;
 957         }
 958
 959         /* configure all serial ports */
 960         for (i = 0; i < ret; i++) {
 961                 /* read the I/O port from the device */
 962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 963                                                                 &ioport);
 964                 ioport &= 0x0000FF00;   /* the actual base address */
 965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 968
 969                 /* write the ioport to the UARTBAR */
 970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 974
 975                 /* get current config */
 976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 977                 /* disable interrupts (UARTx_Routing[3:0]) */
 978                 miscr &= ~(0xf << (12 - 4 * i));
 979                 /* activate the UART (UARTx_En) */
 980                 miscr |= 1 << (23 - i);
 981                 /* write new config with activated UART */
 982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 983         }
 984
 985         if (ret <= 0) {
 986                 /* the device has no UARTs if we get here */
 987                 release_region(iobase->start, ITE_887x_IOSIZE);
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 994 {
 995         u32 ioport;
 996         /* the ioport is bit 0-15 in POSIO0R */
 997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 998         ioport &= 0xffff;
 999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 printk(KERN_DEBUG
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                                                                 number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_port *port, int idx)
1038 {
1039         unsigned int bar, offset = board->first_offset, maxnr;
1040
1041         bar = FL_GET_BASE(board->flags);
1042         if (board->flags & FL_BASE_BARS)
1043                 bar += idx;
1044         else
1045                 offset += idx * board->uart_offset;
1046
1047         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048                 (board->reg_shift + 3);
1049
1050         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051                 return 1;
1052
1053         return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058                   const struct pciserial_board *board,
1059                   struct uart_port *port, int idx)
1060 {
1061         int ret;
1062
1063         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064         port->iotype = UPIO_MEM32;
1065         port->type = PORT_XSCALE;
1066         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067         port->regshift = 2;
1068
1069         return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074                       const struct pciserial_board *board,
1075                       struct uart_port *port, int idx)
1076 {
1077         return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int skip_tx_en_setup(struct serial_private *priv,
1081                         const struct pciserial_board *board,
1082                         struct uart_port *port, int idx)
1083 {
1084         port->flags |= UPF_NO_TXEN_TEST;
1085         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1087                           priv->dev->vendor,
1088                           priv->dev->device,
1089                           priv->dev->subsystem_vendor,
1090                           priv->dev->subsystem_device);
1091
1092         return pci_default_setup(priv, board, port, idx);
1093 }
1094
1095 static int pci_eg20t_init(struct pci_dev *dev)
1096 {
1097 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1098         return -ENODEV;
1099 #else
1100         return 0;
1101 #endif
1102 }
1103
1104 /* This should be in linux/pci_ids.h */
1105 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1106 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1107 #define PCI_DEVICE_ID_OCTPRO            0x0001
1108 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1109 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1110 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1111 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1112 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1113 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1114 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1115 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1116 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1117 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1118 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1119 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1120 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1121 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1122 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1123 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1124 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1125 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1126 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1127 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1128 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1129 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1130
1131 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1132 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1133
1134 /*
1135  * Master list of serial port init/setup/exit quirks.
1136  * This does not describe the general nature of the port.
1137  * (ie, baud base, number and location of ports, etc)
1138  *
1139  * This list is ordered alphabetically by vendor then device.
1140  * Specific entries must come before more generic entries.
1141  */
1142 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1143         /*
1144         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1145         */
1146         {
1147                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1148                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1149                 .subvendor      = PCI_ANY_ID,
1150                 .subdevice      = PCI_ANY_ID,
1151                 .setup          = addidata_apci7800_setup,
1152         },
1153         /*
1154          * AFAVLAB cards - these may be called via parport_serial
1155          *  It is not clear whether this applies to all products.
1156          */
1157         {
1158                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1159                 .device         = PCI_ANY_ID,
1160                 .subvendor      = PCI_ANY_ID,
1161                 .subdevice      = PCI_ANY_ID,
1162                 .setup          = afavlab_setup,
1163         },
1164         /*
1165          * HP Diva
1166          */
1167         {
1168                 .vendor         = PCI_VENDOR_ID_HP,
1169                 .device         = PCI_DEVICE_ID_HP_DIVA,
1170                 .subvendor      = PCI_ANY_ID,
1171                 .subdevice      = PCI_ANY_ID,
1172                 .init           = pci_hp_diva_init,
1173                 .setup          = pci_hp_diva_setup,
1174         },
1175         /*
1176          * Intel
1177          */
1178         {
1179                 .vendor         = PCI_VENDOR_ID_INTEL,
1180                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1181                 .subvendor      = 0xe4bf,
1182                 .subdevice      = PCI_ANY_ID,
1183                 .init           = pci_inteli960ni_init,
1184                 .setup          = pci_default_setup,
1185         },
1186         {
1187                 .vendor         = PCI_VENDOR_ID_INTEL,
1188                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1189                 .subvendor      = PCI_ANY_ID,
1190                 .subdevice      = PCI_ANY_ID,
1191                 .setup          = skip_tx_en_setup,
1192         },
1193         {
1194                 .vendor         = PCI_VENDOR_ID_INTEL,
1195                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1196                 .subvendor      = PCI_ANY_ID,
1197                 .subdevice      = PCI_ANY_ID,
1198                 .setup          = skip_tx_en_setup,
1199         },
1200         {
1201                 .vendor         = PCI_VENDOR_ID_INTEL,
1202                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1203                 .subvendor      = PCI_ANY_ID,
1204                 .subdevice      = PCI_ANY_ID,
1205                 .setup          = skip_tx_en_setup,
1206         },
1207         {
1208                 .vendor         = PCI_VENDOR_ID_INTEL,
1209                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1210                 .subvendor      = PCI_ANY_ID,
1211                 .subdevice      = PCI_ANY_ID,
1212                 .setup          = ce4100_serial_setup,
1213         },
1214         /*
1215          * ITE
1216          */
1217         {
1218                 .vendor         = PCI_VENDOR_ID_ITE,
1219                 .device         = PCI_DEVICE_ID_ITE_8872,
1220                 .subvendor      = PCI_ANY_ID,
1221                 .subdevice      = PCI_ANY_ID,
1222                 .init           = pci_ite887x_init,
1223                 .setup          = pci_default_setup,
1224                 .exit           = __devexit_p(pci_ite887x_exit),
1225         },
1226         /*
1227          * National Instruments
1228          */
1229         {
1230                 .vendor         = PCI_VENDOR_ID_NI,
1231                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1232                 .subvendor      = PCI_ANY_ID,
1233                 .subdevice      = PCI_ANY_ID,
1234                 .init           = pci_ni8420_init,
1235                 .setup          = pci_default_setup,
1236                 .exit           = __devexit_p(pci_ni8420_exit),
1237         },
1238         {
1239                 .vendor         = PCI_VENDOR_ID_NI,
1240                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1241                 .subvendor      = PCI_ANY_ID,
1242                 .subdevice      = PCI_ANY_ID,
1243                 .init           = pci_ni8420_init,
1244                 .setup          = pci_default_setup,
1245                 .exit           = __devexit_p(pci_ni8420_exit),
1246         },
1247         {
1248                 .vendor         = PCI_VENDOR_ID_NI,
1249                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1250                 .subvendor      = PCI_ANY_ID,
1251                 .subdevice      = PCI_ANY_ID,
1252                 .init           = pci_ni8420_init,
1253                 .setup          = pci_default_setup,
1254                 .exit           = __devexit_p(pci_ni8420_exit),
1255         },
1256         {
1257                 .vendor         = PCI_VENDOR_ID_NI,
1258                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1259                 .subvendor      = PCI_ANY_ID,
1260                 .subdevice      = PCI_ANY_ID,
1261                 .init           = pci_ni8420_init,
1262                 .setup          = pci_default_setup,
1263                 .exit           = __devexit_p(pci_ni8420_exit),
1264         },
1265         {
1266                 .vendor         = PCI_VENDOR_ID_NI,
1267                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1268                 .subvendor      = PCI_ANY_ID,
1269                 .subdevice      = PCI_ANY_ID,
1270                 .init           = pci_ni8420_init,
1271                 .setup          = pci_default_setup,
1272                 .exit           = __devexit_p(pci_ni8420_exit),
1273         },
1274         {
1275                 .vendor         = PCI_VENDOR_ID_NI,
1276                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1277                 .subvendor      = PCI_ANY_ID,
1278                 .subdevice      = PCI_ANY_ID,
1279                 .init           = pci_ni8420_init,
1280                 .setup          = pci_default_setup,
1281                 .exit           = __devexit_p(pci_ni8420_exit),
1282         },
1283         {
1284                 .vendor         = PCI_VENDOR_ID_NI,
1285                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1286                 .subvendor      = PCI_ANY_ID,
1287                 .subdevice      = PCI_ANY_ID,
1288                 .init           = pci_ni8420_init,
1289                 .setup          = pci_default_setup,
1290                 .exit           = __devexit_p(pci_ni8420_exit),
1291         },
1292         {
1293                 .vendor         = PCI_VENDOR_ID_NI,
1294                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1295                 .subvendor      = PCI_ANY_ID,
1296                 .subdevice      = PCI_ANY_ID,
1297                 .init           = pci_ni8420_init,
1298                 .setup          = pci_default_setup,
1299                 .exit           = __devexit_p(pci_ni8420_exit),
1300         },
1301         {
1302                 .vendor         = PCI_VENDOR_ID_NI,
1303                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1304                 .subvendor      = PCI_ANY_ID,
1305                 .subdevice      = PCI_ANY_ID,
1306                 .init           = pci_ni8420_init,
1307                 .setup          = pci_default_setup,
1308                 .exit           = __devexit_p(pci_ni8420_exit),
1309         },
1310         {
1311                 .vendor         = PCI_VENDOR_ID_NI,
1312                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1313                 .subvendor      = PCI_ANY_ID,
1314                 .subdevice      = PCI_ANY_ID,
1315                 .init           = pci_ni8420_init,
1316                 .setup          = pci_default_setup,
1317                 .exit           = __devexit_p(pci_ni8420_exit),
1318         },
1319         {
1320                 .vendor         = PCI_VENDOR_ID_NI,
1321                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1322                 .subvendor      = PCI_ANY_ID,
1323                 .subdevice      = PCI_ANY_ID,
1324                 .init           = pci_ni8420_init,
1325                 .setup          = pci_default_setup,
1326                 .exit           = __devexit_p(pci_ni8420_exit),
1327         },
1328         {
1329                 .vendor         = PCI_VENDOR_ID_NI,
1330                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1331                 .subvendor      = PCI_ANY_ID,
1332                 .subdevice      = PCI_ANY_ID,
1333                 .init           = pci_ni8420_init,
1334                 .setup          = pci_default_setup,
1335                 .exit           = __devexit_p(pci_ni8420_exit),
1336         },
1337         {
1338                 .vendor         = PCI_VENDOR_ID_NI,
1339                 .device         = PCI_ANY_ID,
1340                 .subvendor      = PCI_ANY_ID,
1341                 .subdevice      = PCI_ANY_ID,
1342                 .init           = pci_ni8430_init,
1343                 .setup          = pci_ni8430_setup,
1344                 .exit           = __devexit_p(pci_ni8430_exit),
1345         },
1346         /*
1347          * Panacom
1348          */
1349         {
1350                 .vendor         = PCI_VENDOR_ID_PANACOM,
1351                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1352                 .subvendor      = PCI_ANY_ID,
1353                 .subdevice      = PCI_ANY_ID,
1354                 .init           = pci_plx9050_init,
1355                 .setup          = pci_default_setup,
1356                 .exit           = __devexit_p(pci_plx9050_exit),
1357         },
1358         {
1359                 .vendor         = PCI_VENDOR_ID_PANACOM,
1360                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1361                 .subvendor      = PCI_ANY_ID,
1362                 .subdevice      = PCI_ANY_ID,
1363                 .init           = pci_plx9050_init,
1364                 .setup          = pci_default_setup,
1365                 .exit           = __devexit_p(pci_plx9050_exit),
1366         },
1367         /*
1368          * PLX
1369          */
1370         {
1371                 .vendor         = PCI_VENDOR_ID_PLX,
1372                 .device         = PCI_DEVICE_ID_PLX_9030,
1373                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1374                 .subdevice      = PCI_ANY_ID,
1375                 .setup          = pci_default_setup,
1376         },
1377         {
1378                 .vendor         = PCI_VENDOR_ID_PLX,
1379                 .device         = PCI_DEVICE_ID_PLX_9050,
1380                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1381                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1382                 .init           = pci_plx9050_init,
1383                 .setup          = pci_default_setup,
1384                 .exit           = __devexit_p(pci_plx9050_exit),
1385         },
1386         {
1387                 .vendor         = PCI_VENDOR_ID_PLX,
1388                 .device         = PCI_DEVICE_ID_PLX_9050,
1389                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1390                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1391                 .init           = pci_plx9050_init,
1392                 .setup          = pci_default_setup,
1393                 .exit           = __devexit_p(pci_plx9050_exit),
1394         },
1395         {
1396                 .vendor         = PCI_VENDOR_ID_PLX,
1397                 .device         = PCI_DEVICE_ID_PLX_9050,
1398                 .subvendor      = PCI_VENDOR_ID_PLX,
1399                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1400                 .init           = pci_plx9050_init,
1401                 .setup          = pci_default_setup,
1402                 .exit           = __devexit_p(pci_plx9050_exit),
1403         },
1404         {
1405                 .vendor         = PCI_VENDOR_ID_PLX,
1406                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1407                 .subvendor      = PCI_VENDOR_ID_PLX,
1408                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1409                 .init           = pci_plx9050_init,
1410                 .setup          = pci_default_setup,
1411                 .exit           = __devexit_p(pci_plx9050_exit),
1412         },
1413         /*
1414          * SBS Technologies, Inc., PMC-OCTALPRO 232
1415          */
1416         {
1417                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1418                 .device         = PCI_DEVICE_ID_OCTPRO,
1419                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1420                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1421                 .init           = sbs_init,
1422                 .setup          = sbs_setup,
1423                 .exit           = __devexit_p(sbs_exit),
1424         },
1425         /*
1426          * SBS Technologies, Inc., PMC-OCTALPRO 422
1427          */
1428         {
1429                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1430                 .device         = PCI_DEVICE_ID_OCTPRO,
1431                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1432                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1433                 .init           = sbs_init,
1434                 .setup          = sbs_setup,
1435                 .exit           = __devexit_p(sbs_exit),
1436         },
1437         /*
1438          * SBS Technologies, Inc., P-Octal 232
1439          */
1440         {
1441                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1442                 .device         = PCI_DEVICE_ID_OCTPRO,
1443                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1444                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1445                 .init           = sbs_init,
1446                 .setup          = sbs_setup,
1447                 .exit           = __devexit_p(sbs_exit),
1448         },
1449         /*
1450          * SBS Technologies, Inc., P-Octal 422
1451          */
1452         {
1453                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1454                 .device         = PCI_DEVICE_ID_OCTPRO,
1455                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1456                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1457                 .init           = sbs_init,
1458                 .setup          = sbs_setup,
1459                 .exit           = __devexit_p(sbs_exit),
1460         },
1461         /*
1462          * SIIG cards - these may be called via parport_serial
1463          */
1464         {
1465                 .vendor         = PCI_VENDOR_ID_SIIG,
1466                 .device         = PCI_ANY_ID,
1467                 .subvendor      = PCI_ANY_ID,
1468                 .subdevice      = PCI_ANY_ID,
1469                 .init           = pci_siig_init,
1470                 .setup          = pci_siig_setup,
1471         },
1472         /*
1473          * Titan cards
1474          */
1475         {
1476                 .vendor         = PCI_VENDOR_ID_TITAN,
1477                 .device         = PCI_DEVICE_ID_TITAN_400L,
1478                 .subvendor      = PCI_ANY_ID,
1479                 .subdevice      = PCI_ANY_ID,
1480                 .setup          = titan_400l_800l_setup,
1481         },
1482         {
1483                 .vendor         = PCI_VENDOR_ID_TITAN,
1484                 .device         = PCI_DEVICE_ID_TITAN_800L,
1485                 .subvendor      = PCI_ANY_ID,
1486                 .subdevice      = PCI_ANY_ID,
1487                 .setup          = titan_400l_800l_setup,
1488         },
1489         /*
1490          * Timedia cards
1491          */
1492         {
1493                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1494                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1495                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1496                 .subdevice      = PCI_ANY_ID,
1497                 .probe          = pci_timedia_probe,
1498                 .init           = pci_timedia_init,
1499                 .setup          = pci_timedia_setup,
1500         },
1501         {
1502                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1503                 .device         = PCI_ANY_ID,
1504                 .subvendor      = PCI_ANY_ID,
1505                 .subdevice      = PCI_ANY_ID,
1506                 .setup          = pci_timedia_setup,
1507         },
1508         /*
1509          * Xircom cards
1510          */
1511         {
1512                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1513                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1514                 .subvendor      = PCI_ANY_ID,
1515                 .subdevice      = PCI_ANY_ID,
1516                 .init           = pci_xircom_init,
1517                 .setup          = pci_default_setup,
1518         },
1519         /*
1520          * Netmos cards - these may be called via parport_serial
1521          */
1522         {
1523                 .vendor         = PCI_VENDOR_ID_NETMOS,
1524                 .device         = PCI_ANY_ID,
1525                 .subvendor      = PCI_ANY_ID,
1526                 .subdevice      = PCI_ANY_ID,
1527                 .init           = pci_netmos_init,
1528                 .setup          = pci_netmos_9900_setup,
1529         },
1530         /*
1531          * For Oxford Semiconductor Tornado based devices
1532          */
1533         {
1534                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1535                 .device         = PCI_ANY_ID,
1536                 .subvendor      = PCI_ANY_ID,
1537                 .subdevice      = PCI_ANY_ID,
1538                 .init           = pci_oxsemi_tornado_init,
1539                 .setup          = pci_default_setup,
1540         },
1541         {
1542                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1543                 .device         = PCI_ANY_ID,
1544                 .subvendor      = PCI_ANY_ID,
1545                 .subdevice      = PCI_ANY_ID,
1546                 .init           = pci_oxsemi_tornado_init,
1547                 .setup          = pci_default_setup,
1548         },
1549         {
1550                 .vendor         = PCI_VENDOR_ID_DIGI,
1551                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1552                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1553                 .subdevice              = PCI_ANY_ID,
1554                 .init                   = pci_oxsemi_tornado_init,
1555                 .setup          = pci_default_setup,
1556         },
1557         {
1558                 .vendor         = PCI_VENDOR_ID_INTEL,
1559                 .device         = 0x8811,
1560                 .init           = pci_eg20t_init,
1561         },
1562         {
1563                 .vendor         = PCI_VENDOR_ID_INTEL,
1564                 .device         = 0x8812,
1565                 .init           = pci_eg20t_init,
1566         },
1567         {
1568                 .vendor         = PCI_VENDOR_ID_INTEL,
1569                 .device         = 0x8813,
1570                 .init           = pci_eg20t_init,
1571         },
1572         {
1573                 .vendor         = PCI_VENDOR_ID_INTEL,
1574                 .device         = 0x8814,
1575                 .init           = pci_eg20t_init,
1576         },
1577         {
1578                 .vendor         = 0x10DB,
1579                 .device         = 0x8027,
1580                 .init           = pci_eg20t_init,
1581         },
1582         {
1583                 .vendor         = 0x10DB,
1584                 .device         = 0x8028,
1585                 .init           = pci_eg20t_init,
1586         },
1587         {
1588                 .vendor         = 0x10DB,
1589                 .device         = 0x8029,
1590                 .init           = pci_eg20t_init,
1591         },
1592         {
1593                 .vendor         = 0x10DB,
1594                 .device         = 0x800C,
1595                 .init           = pci_eg20t_init,
1596         },
1597         {
1598                 .vendor         = 0x10DB,
1599                 .device         = 0x800D,
1600                 .init           = pci_eg20t_init,
1601         },
1602         {
1603                 .vendor         = 0x10DB,
1604                 .device         = 0x800D,
1605                 .init           = pci_eg20t_init,
1606         },
1607         /*
1608          * Cronyx Omega PCI (PLX-chip based)
1609          */
1610         {
1611                 .vendor         = PCI_VENDOR_ID_PLX,
1612                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1613                 .subvendor      = PCI_ANY_ID,
1614                 .subdevice      = PCI_ANY_ID,
1615                 .setup          = pci_omegapci_setup,
1616          },
1617         /*
1618          * Default "match everything" terminator entry
1619          */
1620         {
1621                 .vendor         = PCI_ANY_ID,
1622                 .device         = PCI_ANY_ID,
1623                 .subvendor      = PCI_ANY_ID,
1624                 .subdevice      = PCI_ANY_ID,
1625                 .setup          = pci_default_setup,
1626         }
1627 };
1628
1629 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1630 {
1631         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1632 }
1633
1634 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1635 {
1636         struct pci_serial_quirk *quirk;
1637
1638         for (quirk = pci_serial_quirks; ; quirk++)
1639                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1640                     quirk_id_matches(quirk->device, dev->device) &&
1641                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1642                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1643                         break;
1644         return quirk;
1645 }
1646
1647 static inline int get_pci_irq(struct pci_dev *dev,
1648                                 const struct pciserial_board *board)
1649 {
1650         if (board->flags & FL_NOIRQ)
1651                 return 0;
1652         else
1653                 return dev->irq;
1654 }
1655
1656 /*
1657  * This is the configuration table for all of the PCI serial boards
1658  * which we support.  It is directly indexed by the pci_board_num_t enum
1659  * value, which is encoded in the pci_device_id PCI probe table's
1660  * driver_data member.
1661  *
1662  * The makeup of these names are:
1663  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1664  *
1665  *  bn          = PCI BAR number
1666  *  bt          = Index using PCI BARs
1667  *  n           = number of serial ports
1668  *  baud        = baud rate
1669  *  offsetinhex = offset for each sequential port (in hex)
1670  *
1671  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1672  *
1673  * Please note: in theory if n = 1, _bt infix should make no difference.
1674  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1675  */
1676 enum pci_board_num_t {
1677         pbn_default = 0,
1678
1679         pbn_b0_1_115200,
1680         pbn_b0_2_115200,
1681         pbn_b0_4_115200,
1682         pbn_b0_5_115200,
1683         pbn_b0_8_115200,
1684
1685         pbn_b0_1_921600,
1686         pbn_b0_2_921600,
1687         pbn_b0_4_921600,
1688
1689         pbn_b0_2_1130000,
1690
1691         pbn_b0_4_1152000,
1692
1693         pbn_b0_2_1843200,
1694         pbn_b0_4_1843200,
1695
1696         pbn_b0_2_1843200_200,
1697         pbn_b0_4_1843200_200,
1698         pbn_b0_8_1843200_200,
1699
1700         pbn_b0_1_4000000,
1701
1702         pbn_b0_bt_1_115200,
1703         pbn_b0_bt_2_115200,
1704         pbn_b0_bt_4_115200,
1705         pbn_b0_bt_8_115200,
1706
1707         pbn_b0_bt_1_460800,
1708         pbn_b0_bt_2_460800,
1709         pbn_b0_bt_4_460800,
1710
1711         pbn_b0_bt_1_921600,
1712         pbn_b0_bt_2_921600,
1713         pbn_b0_bt_4_921600,
1714         pbn_b0_bt_8_921600,
1715
1716         pbn_b1_1_115200,
1717         pbn_b1_2_115200,
1718         pbn_b1_4_115200,
1719         pbn_b1_8_115200,
1720         pbn_b1_16_115200,
1721
1722         pbn_b1_1_921600,
1723         pbn_b1_2_921600,
1724         pbn_b1_4_921600,
1725         pbn_b1_8_921600,
1726
1727         pbn_b1_2_1250000,
1728
1729         pbn_b1_bt_1_115200,
1730         pbn_b1_bt_2_115200,
1731         pbn_b1_bt_4_115200,
1732
1733         pbn_b1_bt_2_921600,
1734
1735         pbn_b1_1_1382400,
1736         pbn_b1_2_1382400,
1737         pbn_b1_4_1382400,
1738         pbn_b1_8_1382400,
1739
1740         pbn_b2_1_115200,
1741         pbn_b2_2_115200,
1742         pbn_b2_4_115200,
1743         pbn_b2_8_115200,
1744
1745         pbn_b2_1_460800,
1746         pbn_b2_4_460800,
1747         pbn_b2_8_460800,
1748         pbn_b2_16_460800,
1749
1750         pbn_b2_1_921600,
1751         pbn_b2_4_921600,
1752         pbn_b2_8_921600,
1753
1754         pbn_b2_8_1152000,
1755
1756         pbn_b2_bt_1_115200,
1757         pbn_b2_bt_2_115200,
1758         pbn_b2_bt_4_115200,
1759
1760         pbn_b2_bt_2_921600,
1761         pbn_b2_bt_4_921600,
1762
1763         pbn_b3_2_115200,
1764         pbn_b3_4_115200,
1765         pbn_b3_8_115200,
1766
1767         pbn_b4_bt_2_921600,
1768         pbn_b4_bt_4_921600,
1769         pbn_b4_bt_8_921600,
1770
1771         /*
1772          * Board-specific versions.
1773          */
1774         pbn_panacom,
1775         pbn_panacom2,
1776         pbn_panacom4,
1777         pbn_exsys_4055,
1778         pbn_plx_romulus,
1779         pbn_oxsemi,
1780         pbn_oxsemi_1_4000000,
1781         pbn_oxsemi_2_4000000,
1782         pbn_oxsemi_4_4000000,
1783         pbn_oxsemi_8_4000000,
1784         pbn_intel_i960,
1785         pbn_sgi_ioc3,
1786         pbn_computone_4,
1787         pbn_computone_6,
1788         pbn_computone_8,
1789         pbn_sbsxrsio,
1790         pbn_exar_XR17C152,
1791         pbn_exar_XR17C154,
1792         pbn_exar_XR17C158,
1793         pbn_exar_ibm_saturn,
1794         pbn_pasemi_1682M,
1795         pbn_ni8430_2,
1796         pbn_ni8430_4,
1797         pbn_ni8430_8,
1798         pbn_ni8430_16,
1799         pbn_ADDIDATA_PCIe_1_3906250,
1800         pbn_ADDIDATA_PCIe_2_3906250,
1801         pbn_ADDIDATA_PCIe_4_3906250,
1802         pbn_ADDIDATA_PCIe_8_3906250,
1803         pbn_ce4100_1_115200,
1804         pbn_omegapci,
1805         pbn_NETMOS9900_2s_115200,
1806 };
1807
1808 /*
1809  * uart_offset - the space between channels
1810  * reg_shift   - describes how the UART registers are mapped
1811  *               to PCI memory by the card.
1812  * For example IER register on SBS, Inc. PMC-OctPro is located at
1813  * offset 0x10 from the UART base, while UART_IER is defined as 1
1814  * in include/linux/serial_reg.h,
1815  * see first lines of serial_in() and serial_out() in 8250.c
1816 */
1817
1818 static struct pciserial_board pci_boards[] __devinitdata = {
1819         [pbn_default] = {
1820                 .flags          = FL_BASE0,
1821                 .num_ports      = 1,
1822                 .base_baud      = 115200,
1823                 .uart_offset    = 8,
1824         },
1825         [pbn_b0_1_115200] = {
1826                 .flags          = FL_BASE0,
1827                 .num_ports      = 1,
1828                 .base_baud      = 115200,
1829                 .uart_offset    = 8,
1830         },
1831         [pbn_b0_2_115200] = {
1832                 .flags          = FL_BASE0,
1833                 .num_ports      = 2,
1834                 .base_baud      = 115200,
1835                 .uart_offset    = 8,
1836         },
1837         [pbn_b0_4_115200] = {
1838                 .flags          = FL_BASE0,
1839                 .num_ports      = 4,
1840                 .base_baud      = 115200,
1841                 .uart_offset    = 8,
1842         },
1843         [pbn_b0_5_115200] = {
1844                 .flags          = FL_BASE0,
1845                 .num_ports      = 5,
1846                 .base_baud      = 115200,
1847                 .uart_offset    = 8,
1848         },
1849         [pbn_b0_8_115200] = {
1850                 .flags          = FL_BASE0,
1851                 .num_ports      = 8,
1852                 .base_baud      = 115200,
1853                 .uart_offset    = 8,
1854         },
1855         [pbn_b0_1_921600] = {
1856                 .flags          = FL_BASE0,
1857                 .num_ports      = 1,
1858                 .base_baud      = 921600,
1859                 .uart_offset    = 8,
1860         },
1861         [pbn_b0_2_921600] = {
1862                 .flags          = FL_BASE0,
1863                 .num_ports      = 2,
1864                 .base_baud      = 921600,
1865                 .uart_offset    = 8,
1866         },
1867         [pbn_b0_4_921600] = {
1868                 .flags          = FL_BASE0,
1869                 .num_ports      = 4,
1870                 .base_baud      = 921600,
1871                 .uart_offset    = 8,
1872         },
1873
1874         [pbn_b0_2_1130000] = {
1875                 .flags          = FL_BASE0,
1876                 .num_ports      = 2,
1877                 .base_baud      = 1130000,
1878                 .uart_offset    = 8,
1879         },
1880
1881         [pbn_b0_4_1152000] = {
1882                 .flags          = FL_BASE0,
1883                 .num_ports      = 4,
1884                 .base_baud      = 1152000,
1885                 .uart_offset    = 8,
1886         },
1887
1888         [pbn_b0_2_1843200] = {
1889                 .flags          = FL_BASE0,
1890                 .num_ports      = 2,
1891                 .base_baud      = 1843200,
1892                 .uart_offset    = 8,
1893         },
1894         [pbn_b0_4_1843200] = {
1895                 .flags          = FL_BASE0,
1896                 .num_ports      = 4,
1897                 .base_baud      = 1843200,
1898                 .uart_offset    = 8,
1899         },
1900
1901         [pbn_b0_2_1843200_200] = {
1902                 .flags          = FL_BASE0,
1903                 .num_ports      = 2,
1904                 .base_baud      = 1843200,
1905                 .uart_offset    = 0x200,
1906         },
1907         [pbn_b0_4_1843200_200] = {
1908                 .flags          = FL_BASE0,
1909                 .num_ports      = 4,
1910                 .base_baud      = 1843200,
1911                 .uart_offset    = 0x200,
1912         },
1913         [pbn_b0_8_1843200_200] = {
1914                 .flags          = FL_BASE0,
1915                 .num_ports      = 8,
1916                 .base_baud      = 1843200,
1917                 .uart_offset    = 0x200,
1918         },
1919         [pbn_b0_1_4000000] = {
1920                 .flags          = FL_BASE0,
1921                 .num_ports      = 1,
1922                 .base_baud      = 4000000,
1923                 .uart_offset    = 8,
1924         },
1925
1926         [pbn_b0_bt_1_115200] = {
1927                 .flags          = FL_BASE0|FL_BASE_BARS,
1928                 .num_ports      = 1,
1929                 .base_baud      = 115200,
1930                 .uart_offset    = 8,
1931         },
1932         [pbn_b0_bt_2_115200] = {
1933                 .flags          = FL_BASE0|FL_BASE_BARS,
1934                 .num_ports      = 2,
1935                 .base_baud      = 115200,
1936                 .uart_offset    = 8,
1937         },
1938         [pbn_b0_bt_4_115200] = {
1939                 .flags          = FL_BASE0|FL_BASE_BARS,
1940                 .num_ports      = 4,
1941                 .base_baud      = 115200,
1942                 .uart_offset    = 8,
1943         },
1944         [pbn_b0_bt_8_115200] = {
1945                 .flags          = FL_BASE0|FL_BASE_BARS,
1946                 .num_ports      = 8,
1947                 .base_baud      = 115200,
1948                 .uart_offset    = 8,
1949         },
1950
1951         [pbn_b0_bt_1_460800] = {
1952                 .flags          = FL_BASE0|FL_BASE_BARS,
1953                 .num_ports      = 1,
1954                 .base_baud      = 460800,
1955                 .uart_offset    = 8,
1956         },
1957         [pbn_b0_bt_2_460800] = {
1958                 .flags          = FL_BASE0|FL_BASE_BARS,
1959                 .num_ports      = 2,
1960                 .base_baud      = 460800,
1961                 .uart_offset    = 8,
1962         },
1963         [pbn_b0_bt_4_460800] = {
1964                 .flags          = FL_BASE0|FL_BASE_BARS,
1965                 .num_ports      = 4,
1966                 .base_baud      = 460800,
1967                 .uart_offset    = 8,
1968         },
1969
1970         [pbn_b0_bt_1_921600] = {
1971                 .flags          = FL_BASE0|FL_BASE_BARS,
1972                 .num_ports      = 1,
1973                 .base_baud      = 921600,
1974                 .uart_offset    = 8,
1975         },
1976         [pbn_b0_bt_2_921600] = {
1977                 .flags          = FL_BASE0|FL_BASE_BARS,
1978                 .num_ports      = 2,
1979                 .base_baud      = 921600,
1980                 .uart_offset    = 8,
1981         },
1982         [pbn_b0_bt_4_921600] = {
1983                 .flags          = FL_BASE0|FL_BASE_BARS,
1984                 .num_ports      = 4,
1985                 .base_baud      = 921600,
1986                 .uart_offset    = 8,
1987         },
1988         [pbn_b0_bt_8_921600] = {
1989                 .flags          = FL_BASE0|FL_BASE_BARS,
1990                 .num_ports      = 8,
1991                 .base_baud      = 921600,
1992                 .uart_offset    = 8,
1993         },
1994
1995         [pbn_b1_1_115200] = {
1996                 .flags          = FL_BASE1,
1997                 .num_ports      = 1,
1998                 .base_baud      = 115200,
1999                 .uart_offset    = 8,
2000         },
2001         [pbn_b1_2_115200] = {
2002                 .flags          = FL_BASE1,
2003                 .num_ports      = 2,
2004                 .base_baud      = 115200,
2005                 .uart_offset    = 8,
2006         },
2007         [pbn_b1_4_115200] = {
2008                 .flags          = FL_BASE1,
2009                 .num_ports      = 4,
2010                 .base_baud      = 115200,
2011                 .uart_offset    = 8,
2012         },
2013         [pbn_b1_8_115200] = {
2014                 .flags          = FL_BASE1,
2015                 .num_ports      = 8,
2016                 .base_baud      = 115200,
2017                 .uart_offset    = 8,
2018         },
2019         [pbn_b1_16_115200] = {
2020                 .flags          = FL_BASE1,
2021                 .num_ports      = 16,
2022                 .base_baud      = 115200,
2023                 .uart_offset    = 8,
2024         },
2025
2026         [pbn_b1_1_921600] = {
2027                 .flags          = FL_BASE1,
2028                 .num_ports      = 1,
2029                 .base_baud      = 921600,
2030                 .uart_offset    = 8,
2031         },
2032         [pbn_b1_2_921600] = {
2033                 .flags          = FL_BASE1,
2034                 .num_ports      = 2,
2035                 .base_baud      = 921600,
2036                 .uart_offset    = 8,
2037         },
2038         [pbn_b1_4_921600] = {
2039                 .flags          = FL_BASE1,
2040                 .num_ports      = 4,
2041                 .base_baud      = 921600,
2042                 .uart_offset    = 8,
2043         },
2044         [pbn_b1_8_921600] = {
2045                 .flags          = FL_BASE1,
2046                 .num_ports      = 8,
2047                 .base_baud      = 921600,
2048                 .uart_offset    = 8,
2049         },
2050         [pbn_b1_2_1250000] = {
2051                 .flags          = FL_BASE1,
2052                 .num_ports      = 2,
2053                 .base_baud      = 1250000,
2054                 .uart_offset    = 8,
2055         },
2056
2057         [pbn_b1_bt_1_115200] = {
2058                 .flags          = FL_BASE1|FL_BASE_BARS,
2059                 .num_ports      = 1,
2060                 .base_baud      = 115200,
2061                 .uart_offset    = 8,
2062         },
2063         [pbn_b1_bt_2_115200] = {
2064                 .flags          = FL_BASE1|FL_BASE_BARS,
2065                 .num_ports      = 2,
2066                 .base_baud      = 115200,
2067                 .uart_offset    = 8,
2068         },
2069         [pbn_b1_bt_4_115200] = {
2070                 .flags          = FL_BASE1|FL_BASE_BARS,
2071                 .num_ports      = 4,
2072                 .base_baud      = 115200,
2073                 .uart_offset    = 8,
2074         },
2075
2076         [pbn_b1_bt_2_921600] = {
2077                 .flags          = FL_BASE1|FL_BASE_BARS,
2078                 .num_ports      = 2,
2079                 .base_baud      = 921600,
2080                 .uart_offset    = 8,
2081         },
2082
2083         [pbn_b1_1_1382400] = {
2084                 .flags          = FL_BASE1,
2085                 .num_ports      = 1,
2086                 .base_baud      = 1382400,
2087                 .uart_offset    = 8,
2088         },
2089         [pbn_b1_2_1382400] = {
2090                 .flags          = FL_BASE1,
2091                 .num_ports      = 2,
2092                 .base_baud      = 1382400,
2093                 .uart_offset    = 8,
2094         },
2095         [pbn_b1_4_1382400] = {
2096                 .flags          = FL_BASE1,
2097                 .num_ports      = 4,
2098                 .base_baud      = 1382400,
2099                 .uart_offset    = 8,
2100         },
2101         [pbn_b1_8_1382400] = {
2102                 .flags          = FL_BASE1,
2103                 .num_ports      = 8,
2104                 .base_baud      = 1382400,
2105                 .uart_offset    = 8,
2106         },
2107
2108         [pbn_b2_1_115200] = {
2109                 .flags          = FL_BASE2,
2110                 .num_ports      = 1,
2111                 .base_baud      = 115200,
2112                 .uart_offset    = 8,
2113         },
2114         [pbn_b2_2_115200] = {
2115                 .flags          = FL_BASE2,
2116                 .num_ports      = 2,
2117                 .base_baud      = 115200,
2118                 .uart_offset    = 8,
2119         },
2120         [pbn_b2_4_115200] = {
2121                 .flags          = FL_BASE2,
2122                 .num_ports      = 4,
2123                 .base_baud      = 115200,
2124                 .uart_offset    = 8,
2125         },
2126         [pbn_b2_8_115200] = {
2127                 .flags          = FL_BASE2,
2128                 .num_ports      = 8,
2129                 .base_baud      = 115200,
2130                 .uart_offset    = 8,
2131         },
2132
2133         [pbn_b2_1_460800] = {
2134                 .flags          = FL_BASE2,
2135                 .num_ports      = 1,
2136                 .base_baud      = 460800,
2137                 .uart_offset    = 8,
2138         },
2139         [pbn_b2_4_460800] = {
2140                 .flags          = FL_BASE2,
2141                 .num_ports      = 4,
2142                 .base_baud      = 460800,
2143                 .uart_offset    = 8,
2144         },
2145         [pbn_b2_8_460800] = {
2146                 .flags          = FL_BASE2,
2147                 .num_ports      = 8,
2148                 .base_baud      = 460800,
2149                 .uart_offset    = 8,
2150         },
2151         [pbn_b2_16_460800] = {
2152                 .flags          = FL_BASE2,
2153                 .num_ports      = 16,
2154                 .base_baud      = 460800,
2155                 .uart_offset    = 8,
2156          },
2157
2158         [pbn_b2_1_921600] = {
2159                 .flags          = FL_BASE2,
2160                 .num_ports      = 1,
2161                 .base_baud      = 921600,
2162                 .uart_offset    = 8,
2163         },
2164         [pbn_b2_4_921600] = {
2165                 .flags          = FL_BASE2,
2166                 .num_ports      = 4,
2167                 .base_baud      = 921600,
2168                 .uart_offset    = 8,
2169         },
2170         [pbn_b2_8_921600] = {
2171                 .flags          = FL_BASE2,
2172                 .num_ports      = 8,
2173                 .base_baud      = 921600,
2174                 .uart_offset    = 8,
2175         },
2176
2177         [pbn_b2_8_1152000] = {
2178                 .flags          = FL_BASE2,
2179                 .num_ports      = 8,
2180                 .base_baud      = 1152000,
2181                 .uart_offset    = 8,
2182         },
2183
2184         [pbn_b2_bt_1_115200] = {
2185                 .flags          = FL_BASE2|FL_BASE_BARS,
2186                 .num_ports      = 1,
2187                 .base_baud      = 115200,
2188                 .uart_offset    = 8,
2189         },
2190         [pbn_b2_bt_2_115200] = {
2191                 .flags          = FL_BASE2|FL_BASE_BARS,
2192                 .num_ports      = 2,
2193                 .base_baud      = 115200,
2194                 .uart_offset    = 8,
2195         },
2196         [pbn_b2_bt_4_115200] = {
2197                 .flags          = FL_BASE2|FL_BASE_BARS,
2198                 .num_ports      = 4,
2199                 .base_baud      = 115200,
2200                 .uart_offset    = 8,
2201         },
2202
2203         [pbn_b2_bt_2_921600] = {
2204                 .flags          = FL_BASE2|FL_BASE_BARS,
2205                 .num_ports      = 2,
2206                 .base_baud      = 921600,
2207                 .uart_offset    = 8,
2208         },
2209         [pbn_b2_bt_4_921600] = {
2210                 .flags          = FL_BASE2|FL_BASE_BARS,
2211                 .num_ports      = 4,
2212                 .base_baud      = 921600,
2213                 .uart_offset    = 8,
2214         },
2215
2216         [pbn_b3_2_115200] = {
2217                 .flags          = FL_BASE3,
2218                 .num_ports      = 2,
2219                 .base_baud      = 115200,
2220                 .uart_offset    = 8,
2221         },
2222         [pbn_b3_4_115200] = {
2223                 .flags          = FL_BASE3,
2224                 .num_ports      = 4,
2225                 .base_baud      = 115200,
2226                 .uart_offset    = 8,
2227         },
2228         [pbn_b3_8_115200] = {
2229                 .flags          = FL_BASE3,
2230                 .num_ports      = 8,
2231                 .base_baud      = 115200,
2232                 .uart_offset    = 8,
2233         },
2234
2235         [pbn_b4_bt_2_921600] = {
2236                 .flags          = FL_BASE4,
2237                 .num_ports      = 2,
2238                 .base_baud      = 921600,
2239                 .uart_offset    = 8,
2240         },
2241         [pbn_b4_bt_4_921600] = {
2242                 .flags          = FL_BASE4,
2243                 .num_ports      = 4,
2244                 .base_baud      = 921600,
2245                 .uart_offset    = 8,
2246         },
2247         [pbn_b4_bt_8_921600] = {
2248                 .flags          = FL_BASE4,
2249                 .num_ports      = 8,
2250                 .base_baud      = 921600,
2251                 .uart_offset    = 8,
2252         },
2253
2254         /*
2255          * Entries following this are board-specific.
2256          */
2257
2258         /*
2259          * Panacom - IOMEM
2260          */
2261         [pbn_panacom] = {
2262                 .flags          = FL_BASE2,
2263                 .num_ports      = 2,
2264                 .base_baud      = 921600,
2265                 .uart_offset    = 0x400,
2266                 .reg_shift      = 7,
2267         },
2268         [pbn_panacom2] = {
2269                 .flags          = FL_BASE2|FL_BASE_BARS,
2270                 .num_ports      = 2,
2271                 .base_baud      = 921600,
2272                 .uart_offset    = 0x400,
2273                 .reg_shift      = 7,
2274         },
2275         [pbn_panacom4] = {
2276                 .flags          = FL_BASE2|FL_BASE_BARS,
2277                 .num_ports      = 4,
2278                 .base_baud      = 921600,
2279                 .uart_offset    = 0x400,
2280                 .reg_shift      = 7,
2281         },
2282
2283         [pbn_exsys_4055] = {
2284                 .flags          = FL_BASE2,
2285                 .num_ports      = 4,
2286                 .base_baud      = 115200,
2287                 .uart_offset    = 8,
2288         },
2289
2290         /* I think this entry is broken - the first_offset looks wrong --rmk */
2291         [pbn_plx_romulus] = {
2292                 .flags          = FL_BASE2,
2293                 .num_ports      = 4,
2294                 .base_baud      = 921600,
2295                 .uart_offset    = 8 << 2,
2296                 .reg_shift      = 2,
2297                 .first_offset   = 0x03,
2298         },
2299
2300         /*
2301          * This board uses the size of PCI Base region 0 to
2302          * signal now many ports are available
2303          */
2304         [pbn_oxsemi] = {
2305                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2306                 .num_ports      = 32,
2307                 .base_baud      = 115200,
2308                 .uart_offset    = 8,
2309         },
2310         [pbn_oxsemi_1_4000000] = {
2311                 .flags          = FL_BASE0,
2312                 .num_ports      = 1,
2313                 .base_baud      = 4000000,
2314                 .uart_offset    = 0x200,
2315                 .first_offset   = 0x1000,
2316         },
2317         [pbn_oxsemi_2_4000000] = {
2318                 .flags          = FL_BASE0,
2319                 .num_ports      = 2,
2320                 .base_baud      = 4000000,
2321                 .uart_offset    = 0x200,
2322                 .first_offset   = 0x1000,
2323         },
2324         [pbn_oxsemi_4_4000000] = {
2325                 .flags          = FL_BASE0,
2326                 .num_ports      = 4,
2327                 .base_baud      = 4000000,
2328                 .uart_offset    = 0x200,
2329                 .first_offset   = 0x1000,
2330         },
2331         [pbn_oxsemi_8_4000000] = {
2332                 .flags          = FL_BASE0,
2333                 .num_ports      = 8,
2334                 .base_baud      = 4000000,
2335                 .uart_offset    = 0x200,
2336                 .first_offset   = 0x1000,
2337         },
2338
2339
2340         /*
2341          * EKF addition for i960 Boards form EKF with serial port.
2342          * Max 256 ports.
2343          */
2344         [pbn_intel_i960] = {
2345                 .flags          = FL_BASE0,
2346                 .num_ports      = 32,
2347                 .base_baud      = 921600,
2348                 .uart_offset    = 8 << 2,
2349                 .reg_shift      = 2,
2350                 .first_offset   = 0x10000,
2351         },
2352         [pbn_sgi_ioc3] = {
2353                 .flags          = FL_BASE0|FL_NOIRQ,
2354                 .num_ports      = 1,
2355                 .base_baud      = 458333,
2356                 .uart_offset    = 8,
2357                 .reg_shift      = 0,
2358                 .first_offset   = 0x20178,
2359         },
2360
2361         /*
2362          * Computone - uses IOMEM.
2363          */
2364         [pbn_computone_4] = {
2365                 .flags          = FL_BASE0,
2366                 .num_ports      = 4,
2367                 .base_baud      = 921600,
2368                 .uart_offset    = 0x40,
2369                 .reg_shift      = 2,
2370                 .first_offset   = 0x200,
2371         },
2372         [pbn_computone_6] = {
2373                 .flags          = FL_BASE0,
2374                 .num_ports      = 6,
2375                 .base_baud      = 921600,
2376                 .uart_offset    = 0x40,
2377                 .reg_shift      = 2,
2378                 .first_offset   = 0x200,
2379         },
2380         [pbn_computone_8] = {
2381                 .flags          = FL_BASE0,
2382                 .num_ports      = 8,
2383                 .base_baud      = 921600,
2384                 .uart_offset    = 0x40,
2385                 .reg_shift      = 2,
2386                 .first_offset   = 0x200,
2387         },
2388         [pbn_sbsxrsio] = {
2389                 .flags          = FL_BASE0,
2390                 .num_ports      = 8,
2391                 .base_baud      = 460800,
2392                 .uart_offset    = 256,
2393                 .reg_shift      = 4,
2394         },
2395         /*
2396          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2397          *  Only basic 16550A support.
2398          *  XR17C15[24] are not tested, but they should work.
2399          */
2400         [pbn_exar_XR17C152] = {
2401                 .flags          = FL_BASE0,
2402                 .num_ports      = 2,
2403                 .base_baud      = 921600,
2404                 .uart_offset    = 0x200,
2405         },
2406         [pbn_exar_XR17C154] = {
2407                 .flags          = FL_BASE0,
2408                 .num_ports      = 4,
2409                 .base_baud      = 921600,
2410                 .uart_offset    = 0x200,
2411         },
2412         [pbn_exar_XR17C158] = {
2413                 .flags          = FL_BASE0,
2414                 .num_ports      = 8,
2415                 .base_baud      = 921600,
2416                 .uart_offset    = 0x200,
2417         },
2418         [pbn_exar_ibm_saturn] = {
2419                 .flags          = FL_BASE0,
2420                 .num_ports      = 1,
2421                 .base_baud      = 921600,
2422                 .uart_offset    = 0x200,
2423         },
2424
2425         /*
2426          * PA Semi PWRficient PA6T-1682M on-chip UART
2427          */
2428         [pbn_pasemi_1682M] = {
2429                 .flags          = FL_BASE0,
2430                 .num_ports      = 1,
2431                 .base_baud      = 8333333,
2432         },
2433         /*
2434          * National Instruments 843x
2435          */
2436         [pbn_ni8430_16] = {
2437                 .flags          = FL_BASE0,
2438                 .num_ports      = 16,
2439                 .base_baud      = 3686400,
2440                 .uart_offset    = 0x10,
2441                 .first_offset   = 0x800,
2442         },
2443         [pbn_ni8430_8] = {
2444                 .flags          = FL_BASE0,
2445                 .num_ports      = 8,
2446                 .base_baud      = 3686400,
2447                 .uart_offset    = 0x10,
2448                 .first_offset   = 0x800,
2449         },
2450         [pbn_ni8430_4] = {
2451                 .flags          = FL_BASE0,
2452                 .num_ports      = 4,
2453                 .base_baud      = 3686400,
2454                 .uart_offset    = 0x10,
2455                 .first_offset   = 0x800,
2456         },
2457         [pbn_ni8430_2] = {
2458                 .flags          = FL_BASE0,
2459                 .num_ports      = 2,
2460                 .base_baud      = 3686400,
2461                 .uart_offset    = 0x10,
2462                 .first_offset   = 0x800,
2463         },
2464         /*
2465          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2466          */
2467         [pbn_ADDIDATA_PCIe_1_3906250] = {
2468                 .flags          = FL_BASE0,
2469                 .num_ports      = 1,
2470                 .base_baud      = 3906250,
2471                 .uart_offset    = 0x200,
2472                 .first_offset   = 0x1000,
2473         },
2474         [pbn_ADDIDATA_PCIe_2_3906250] = {
2475                 .flags          = FL_BASE0,
2476                 .num_ports      = 2,
2477                 .base_baud      = 3906250,
2478                 .uart_offset    = 0x200,
2479                 .first_offset   = 0x1000,
2480         },
2481         [pbn_ADDIDATA_PCIe_4_3906250] = {
2482                 .flags          = FL_BASE0,
2483                 .num_ports      = 4,
2484                 .base_baud      = 3906250,
2485                 .uart_offset    = 0x200,
2486                 .first_offset   = 0x1000,
2487         },
2488         [pbn_ADDIDATA_PCIe_8_3906250] = {
2489                 .flags          = FL_BASE0,
2490                 .num_ports      = 8,
2491                 .base_baud      = 3906250,
2492                 .uart_offset    = 0x200,
2493                 .first_offset   = 0x1000,
2494         },
2495         [pbn_ce4100_1_115200] = {
2496                 .flags          = FL_BASE0,
2497                 .num_ports      = 1,
2498                 .base_baud      = 921600,
2499                 .reg_shift      = 2,
2500         },
2501         [pbn_omegapci] = {
2502                 .flags          = FL_BASE0,
2503                 .num_ports      = 8,
2504                 .base_baud      = 115200,
2505                 .uart_offset    = 0x200,
2506         },
2507         [pbn_NETMOS9900_2s_115200] = {
2508                 .flags          = FL_BASE0,
2509                 .num_ports      = 2,
2510                 .base_baud      = 115200,
2511         },
2512 };
2513
2514 static const struct pci_device_id softmodem_blacklist[] = {
2515         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2516         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2517         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2518 };
2519
2520 /*
2521  * Given a complete unknown PCI device, try to use some heuristics to
2522  * guess what the configuration might be, based on the pitiful PCI
2523  * serial specs.  Returns 0 on success, 1 on failure.
2524  */
2525 static int __devinit
2526 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2527 {
2528         const struct pci_device_id *blacklist;
2529         int num_iomem, num_port, first_port = -1, i;
2530
2531         /*
2532          * If it is not a communications device or the programming
2533          * interface is greater than 6, give up.
2534          *
2535          * (Should we try to make guesses for multiport serial devices
2536          * later?)
2537          */
2538         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2539              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2540             (dev->class & 0xff) > 6)
2541                 return -ENODEV;
2542
2543         /*
2544          * Do not access blacklisted devices that are known not to
2545          * feature serial ports.
2546          */
2547         for (blacklist = softmodem_blacklist;
2548              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2549              blacklist++) {
2550                 if (dev->vendor == blacklist->vendor &&
2551                     dev->device == blacklist->device)
2552                         return -ENODEV;
2553         }
2554
2555         num_iomem = num_port = 0;
2556         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2557                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2558                         num_port++;
2559                         if (first_port == -1)
2560                                 first_port = i;
2561                 }
2562                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2563                         num_iomem++;
2564         }
2565
2566         /*
2567          * If there is 1 or 0 iomem regions, and exactly one port,
2568          * use it.  We guess the number of ports based on the IO
2569          * region size.
2570          */
2571         if (num_iomem <= 1 && num_port == 1) {
2572                 board->flags = first_port;
2573                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2574                 return 0;
2575         }
2576
2577         /*
2578          * Now guess if we've got a board which indexes by BARs.
2579          * Each IO BAR should be 8 bytes, and they should follow
2580          * consecutively.
2581          */
2582         first_port = -1;
2583         num_port = 0;
2584         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2585                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2586                     pci_resource_len(dev, i) == 8 &&
2587                     (first_port == -1 || (first_port + num_port) == i)) {
2588                         num_port++;
2589                         if (first_port == -1)
2590                                 first_port = i;
2591                 }
2592         }
2593
2594         if (num_port > 1) {
2595                 board->flags = first_port | FL_BASE_BARS;
2596                 board->num_ports = num_port;
2597                 return 0;
2598         }
2599
2600         return -ENODEV;
2601 }
2602
2603 static inline int
2604 serial_pci_matches(const struct pciserial_board *board,
2605                    const struct pciserial_board *guessed)
2606 {
2607         return
2608             board->num_ports == guessed->num_ports &&
2609             board->base_baud == guessed->base_baud &&
2610             board->uart_offset == guessed->uart_offset &&
2611             board->reg_shift == guessed->reg_shift &&
2612             board->first_offset == guessed->first_offset;
2613 }
2614
2615 struct serial_private *
2616 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2617 {
2618         struct uart_port serial_port;
2619         struct serial_private *priv;
2620         struct pci_serial_quirk *quirk;
2621         int rc, nr_ports, i;
2622
2623         nr_ports = board->num_ports;
2624
2625         /*
2626          * Find an init and setup quirks.
2627          */
2628         quirk = find_quirk(dev);
2629
2630         /*
2631          * Run the new-style initialization function.
2632          * The initialization function returns:
2633          *  <0  - error
2634          *   0  - use board->num_ports
2635          *  >0  - number of ports
2636          */
2637         if (quirk->init) {
2638                 rc = quirk->init(dev);
2639                 if (rc < 0) {
2640                         priv = ERR_PTR(rc);
2641                         goto err_out;
2642                 }
2643                 if (rc)
2644                         nr_ports = rc;
2645         }
2646
2647         priv = kzalloc(sizeof(struct serial_private) +
2648                        sizeof(unsigned int) * nr_ports,
2649                        GFP_KERNEL);
2650         if (!priv) {
2651                 priv = ERR_PTR(-ENOMEM);
2652                 goto err_deinit;
2653         }
2654
2655         priv->dev = dev;
2656         priv->quirk = quirk;
2657
2658         memset(&serial_port, 0, sizeof(struct uart_port));
2659         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2660         serial_port.uartclk = board->base_baud * 16;
2661         serial_port.irq = get_pci_irq(dev, board);
2662         serial_port.dev = &dev->dev;
2663
2664         for (i = 0; i < nr_ports; i++) {
2665                 if (quirk->setup(priv, board, &serial_port, i))
2666                         break;
2667
2668 #ifdef SERIAL_DEBUG_PCI
2669                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2670                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2671 #endif
2672
2673                 priv->line[i] = serial8250_register_port(&serial_port);
2674                 if (priv->line[i] < 0) {
2675                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2676                         break;
2677                 }
2678         }
2679         priv->nr = i;
2680         return priv;
2681
2682 err_deinit:
2683         if (quirk->exit)
2684                 quirk->exit(dev);
2685 err_out:
2686         return priv;
2687 }
2688 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2689
2690 void pciserial_remove_ports(struct serial_private *priv)
2691 {
2692         struct pci_serial_quirk *quirk;
2693         int i;
2694
2695         for (i = 0; i < priv->nr; i++)
2696                 serial8250_unregister_port(priv->line[i]);
2697
2698         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2699                 if (priv->remapped_bar[i])
2700                         iounmap(priv->remapped_bar[i]);
2701                 priv->remapped_bar[i] = NULL;
2702         }
2703
2704         /*
2705          * Find the exit quirks.
2706          */
2707         quirk = find_quirk(priv->dev);
2708         if (quirk->exit)
2709                 quirk->exit(priv->dev);
2710
2711         kfree(priv);
2712 }
2713 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2714
2715 void pciserial_suspend_ports(struct serial_private *priv)
2716 {
2717         int i;
2718
2719         for (i = 0; i < priv->nr; i++)
2720                 if (priv->line[i] >= 0)
2721                         serial8250_suspend_port(priv->line[i]);
2722 }
2723 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2724
2725 void pciserial_resume_ports(struct serial_private *priv)
2726 {
2727         int i;
2728
2729         /*
2730          * Ensure that the board is correctly configured.
2731          */
2732         if (priv->quirk->init)
2733                 priv->quirk->init(priv->dev);
2734
2735         for (i = 0; i < priv->nr; i++)
2736                 if (priv->line[i] >= 0)
2737                         serial8250_resume_port(priv->line[i]);
2738 }
2739 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2740
2741 /*
2742  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2743  * to the arrangement of serial ports on a PCI card.
2744  */
2745 static int __devinit
2746 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2747 {
2748         struct pci_serial_quirk *quirk;
2749         struct serial_private *priv;
2750         const struct pciserial_board *board;
2751         struct pciserial_board tmp;
2752         int rc;
2753
2754         quirk = find_quirk(dev);
2755         if (quirk->probe) {
2756                 rc = quirk->probe(dev);
2757                 if (rc)
2758                         return rc;
2759         }
2760
2761         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2762                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2763                         ent->driver_data);
2764                 return -EINVAL;
2765         }
2766
2767         board = &pci_boards[ent->driver_data];
2768
2769         rc = pci_enable_device(dev);
2770         pci_save_state(dev);
2771         if (rc)
2772                 return rc;
2773
2774         if (ent->driver_data == pbn_default) {
2775                 /*
2776                  * Use a copy of the pci_board entry for this;
2777                  * avoid changing entries in the table.
2778                  */
2779                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2780                 board = &tmp;
2781
2782                 /*
2783                  * We matched one of our class entries.  Try to
2784                  * determine the parameters of this board.
2785                  */
2786                 rc = serial_pci_guess_board(dev, &tmp);
2787                 if (rc)
2788                         goto disable;
2789         } else {
2790                 /*
2791                  * We matched an explicit entry.  If we are able to
2792                  * detect this boards settings with our heuristic,
2793                  * then we no longer need this entry.
2794                  */
2795                 memcpy(&tmp, &pci_boards[pbn_default],
2796                        sizeof(struct pciserial_board));
2797                 rc = serial_pci_guess_board(dev, &tmp);
2798                 if (rc == 0 && serial_pci_matches(board, &tmp))
2799                         moan_device("Redundant entry in serial pci_table.",
2800                                     dev);
2801         }
2802
2803         priv = pciserial_init_ports(dev, board);
2804         if (!IS_ERR(priv)) {
2805                 pci_set_drvdata(dev, priv);
2806                 return 0;
2807         }
2808
2809         rc = PTR_ERR(priv);
2810
2811  disable:
2812         pci_disable_device(dev);
2813         return rc;
2814 }
2815
2816 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2817 {
2818         struct serial_private *priv = pci_get_drvdata(dev);
2819
2820         pci_set_drvdata(dev, NULL);
2821
2822         pciserial_remove_ports(priv);
2823
2824         pci_disable_device(dev);
2825 }
2826
2827 #ifdef CONFIG_PM
2828 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2829 {
2830         struct serial_private *priv = pci_get_drvdata(dev);
2831
2832         if (priv)
2833                 pciserial_suspend_ports(priv);
2834
2835         pci_save_state(dev);
2836         pci_set_power_state(dev, pci_choose_state(dev, state));
2837         return 0;
2838 }
2839
2840 static int pciserial_resume_one(struct pci_dev *dev)
2841 {
2842         int err;
2843         struct serial_private *priv = pci_get_drvdata(dev);
2844
2845         pci_set_power_state(dev, PCI_D0);
2846         pci_restore_state(dev);
2847
2848         if (priv) {
2849                 /*
2850                  * The device may have been disabled.  Re-enable it.
2851                  */
2852                 err = pci_enable_device(dev);
2853                 /* FIXME: We cannot simply error out here */
2854                 if (err)
2855                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2856                 pciserial_resume_ports(priv);
2857         }
2858         return 0;
2859 }
2860 #endif
2861
2862 static struct pci_device_id serial_pci_tbl[] = {
2863         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2864         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2865                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2866                 pbn_b2_8_921600 },
2867         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2868                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2869                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2870                 pbn_b1_8_1382400 },
2871         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2872                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2873                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2874                 pbn_b1_4_1382400 },
2875         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2876                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2877                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2878                 pbn_b1_2_1382400 },
2879         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2880                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2881                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2882                 pbn_b1_8_1382400 },
2883         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2884                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2885                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2886                 pbn_b1_4_1382400 },
2887         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2888                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2889                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2890                 pbn_b1_2_1382400 },
2891         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2892                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2893                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2894                 pbn_b1_8_921600 },
2895         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2896                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2897                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2898                 pbn_b1_8_921600 },
2899         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2900                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2901                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2902                 pbn_b1_4_921600 },
2903         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2904                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2905                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2906                 pbn_b1_4_921600 },
2907         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2908                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2909                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2910                 pbn_b1_2_921600 },
2911         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2912                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2913                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2914                 pbn_b1_8_921600 },
2915         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2916                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2917                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2918                 pbn_b1_8_921600 },
2919         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2920                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2921                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2922                 pbn_b1_4_921600 },
2923         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2924                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2925                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2926                 pbn_b1_2_1250000 },
2927         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2928                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2929                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2930                 pbn_b0_2_1843200 },
2931         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2932                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2933                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2934                 pbn_b0_4_1843200 },
2935         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2936                 PCI_VENDOR_ID_AFAVLAB,
2937                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2938                 pbn_b0_4_1152000 },
2939         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2940                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2941                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2942                 pbn_b0_2_1843200_200 },
2943         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2944                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2945                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2946                 pbn_b0_4_1843200_200 },
2947         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2948                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2949                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2950                 pbn_b0_8_1843200_200 },
2951         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2952                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2953                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2954                 pbn_b0_2_1843200_200 },
2955         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2956                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2957                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2958                 pbn_b0_4_1843200_200 },
2959         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2960                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2961                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2962                 pbn_b0_8_1843200_200 },
2963         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2964                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2965                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2966                 pbn_b0_2_1843200_200 },
2967         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2968                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2969                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2970                 pbn_b0_4_1843200_200 },
2971         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2972                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2973                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2974                 pbn_b0_8_1843200_200 },
2975         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2976                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2977                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2978                 pbn_b0_2_1843200_200 },
2979         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2980                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2981                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2982                 pbn_b0_4_1843200_200 },
2983         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2984                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2985                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2986                 pbn_b0_8_1843200_200 },
2987         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2988                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2989                 0, 0, pbn_exar_ibm_saturn },
2990
2991         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2992                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2993                 pbn_b2_bt_1_115200 },
2994         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2995                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2996                 pbn_b2_bt_2_115200 },
2997         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2999                 pbn_b2_bt_4_115200 },
3000         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3001                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3002                 pbn_b2_bt_2_115200 },
3003         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3005                 pbn_b2_bt_4_115200 },
3006         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3008                 pbn_b2_8_115200 },
3009         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3011                 pbn_b2_8_460800 },
3012         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3013                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3014                 pbn_b2_8_115200 },
3015
3016         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3018                 pbn_b2_bt_2_115200 },
3019         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3021                 pbn_b2_bt_2_921600 },
3022         /*
3023          * VScom SPCOM800, from sl@s.pl
3024          */
3025         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3026                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3027                 pbn_b2_8_921600 },
3028         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3029                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3030                 pbn_b2_4_921600 },
3031         /* Unknown card - subdevice 0x1584 */
3032         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3033                 PCI_VENDOR_ID_PLX,
3034                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3035                 pbn_b0_4_115200 },
3036         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3037                 PCI_SUBVENDOR_ID_KEYSPAN,
3038                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3039                 pbn_panacom },
3040         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3041                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3042                 pbn_panacom4 },
3043         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3045                 pbn_panacom2 },
3046         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3047                 PCI_VENDOR_ID_ESDGMBH,
3048                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3049                 pbn_b2_4_115200 },
3050         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3051                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3052                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3053                 pbn_b2_4_460800 },
3054         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3055                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3056                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3057                 pbn_b2_8_460800 },
3058         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3059                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3060                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3061                 pbn_b2_16_460800 },
3062         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3063                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3064                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3065                 pbn_b2_16_460800 },
3066         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3067                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3068                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3069                 pbn_b2_4_460800 },
3070         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3071                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3072                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3073                 pbn_b2_8_460800 },
3074         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3075                 PCI_SUBVENDOR_ID_EXSYS,
3076                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3077                 pbn_exsys_4055 },
3078         /*
3079          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3080          * (Exoray@isys.ca)
3081          */
3082         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3083                 0x10b5, 0x106a, 0, 0,
3084                 pbn_plx_romulus },
3085         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087                 pbn_b1_4_115200 },
3088         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3090                 pbn_b1_2_115200 },
3091         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3092                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3093                 pbn_b1_8_115200 },
3094         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3095                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3096                 pbn_b1_8_115200 },
3097         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3098                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3099                 0, 0,
3100                 pbn_b0_4_921600 },
3101         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3102                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3103                 0, 0,
3104                 pbn_b0_4_1152000 },
3105         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3107                 pbn_b0_bt_2_921600 },
3108
3109                 /*
3110                  * The below card is a little controversial since it is the
3111                  * subject of a PCI vendor/device ID clash.  (See
3112                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3113                  * For now just used the hex ID 0x950a.
3114                  */
3115         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3116                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3117                 pbn_b0_2_115200 },
3118         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3119                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3120                 pbn_b0_2_1130000 },
3121         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3122                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3123                 pbn_b0_1_921600 },
3124         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3125                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3126                 pbn_b0_4_115200 },
3127         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3128                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3129                 pbn_b0_bt_2_921600 },
3130         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3131                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3132                 pbn_b2_8_1152000 },
3133
3134         /*
3135          * Oxford Semiconductor Inc. Tornado PCI express device range.
3136          */
3137         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3138                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139                 pbn_b0_1_4000000 },
3140         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3141                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3142                 pbn_b0_1_4000000 },
3143         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3144                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3145                 pbn_oxsemi_1_4000000 },
3146         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148                 pbn_oxsemi_1_4000000 },
3149         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3151                 pbn_b0_1_4000000 },
3152         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3154                 pbn_b0_1_4000000 },
3155         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3157                 pbn_oxsemi_1_4000000 },
3158         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3159                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3160                 pbn_oxsemi_1_4000000 },
3161         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3162                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163                 pbn_b0_1_4000000 },
3164         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3165                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3166                 pbn_b0_1_4000000 },
3167         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3168                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3169                 pbn_b0_1_4000000 },
3170         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172                 pbn_b0_1_4000000 },
3173         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175                 pbn_oxsemi_2_4000000 },
3176         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178                 pbn_oxsemi_2_4000000 },
3179         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181                 pbn_oxsemi_4_4000000 },
3182         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3184                 pbn_oxsemi_4_4000000 },
3185         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3187                 pbn_oxsemi_8_4000000 },
3188         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3190                 pbn_oxsemi_8_4000000 },
3191         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3193                 pbn_oxsemi_1_4000000 },
3194         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3196                 pbn_oxsemi_1_4000000 },
3197         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3198                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3199                 pbn_oxsemi_1_4000000 },
3200         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3201                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3202                 pbn_oxsemi_1_4000000 },
3203         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3204                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3205                 pbn_oxsemi_1_4000000 },
3206         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3207                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208                 pbn_oxsemi_1_4000000 },
3209         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3210                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211                 pbn_oxsemi_1_4000000 },
3212         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3213                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214                 pbn_oxsemi_1_4000000 },
3215         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217                 pbn_oxsemi_1_4000000 },
3218         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220                 pbn_oxsemi_1_4000000 },
3221         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223                 pbn_oxsemi_1_4000000 },
3224         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3226                 pbn_oxsemi_1_4000000 },
3227         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3228                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3229                 pbn_oxsemi_1_4000000 },
3230         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3232                 pbn_oxsemi_1_4000000 },
3233         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3235                 pbn_oxsemi_1_4000000 },
3236         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3238                 pbn_oxsemi_1_4000000 },
3239         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3240                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241                 pbn_oxsemi_1_4000000 },
3242         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244                 pbn_oxsemi_1_4000000 },
3245         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3246                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3247                 pbn_oxsemi_1_4000000 },
3248         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3249                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250                 pbn_oxsemi_1_4000000 },
3251         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3252                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253                 pbn_oxsemi_1_4000000 },
3254         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3255                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256                 pbn_oxsemi_1_4000000 },
3257         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3258                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259                 pbn_oxsemi_1_4000000 },
3260         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262                 pbn_oxsemi_1_4000000 },
3263         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3264                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265                 pbn_oxsemi_1_4000000 },
3266         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268                 pbn_oxsemi_1_4000000 },
3269         /*
3270          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3271          */
3272         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3273                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3274                 pbn_oxsemi_1_4000000 },
3275         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3276                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3277                 pbn_oxsemi_2_4000000 },
3278         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3279                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3280                 pbn_oxsemi_4_4000000 },
3281         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3282                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3283                 pbn_oxsemi_8_4000000 },
3284
3285         /*
3286          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3287          */
3288         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3289                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3290                 pbn_oxsemi_2_4000000 },
3291
3292         /*
3293          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3294          * from skokodyn@yahoo.com
3295          */
3296         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3297                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3298                 pbn_sbsxrsio },
3299         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3300                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3301                 pbn_sbsxrsio },
3302         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3303                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3304                 pbn_sbsxrsio },
3305         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3306                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3307                 pbn_sbsxrsio },
3308
3309         /*
3310          * Digitan DS560-558, from jimd@esoft.com
3311          */
3312         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3313                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314                 pbn_b1_1_115200 },
3315
3316         /*
3317          * Titan Electronic cards
3318          *  The 400L and 800L have a custom setup quirk.
3319          */
3320         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3322                 pbn_b0_1_921600 },
3323         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3325                 pbn_b0_2_921600 },
3326         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328                 pbn_b0_4_921600 },
3329         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3331                 pbn_b0_4_921600 },
3332         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334                 pbn_b1_1_921600 },
3335         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3337                 pbn_b1_bt_2_921600 },
3338         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3340                 pbn_b0_bt_4_921600 },
3341         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3342                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3343                 pbn_b0_bt_8_921600 },
3344         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3346                 pbn_b4_bt_2_921600 },
3347         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3348                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3349                 pbn_b4_bt_4_921600 },
3350         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3351                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3352                 pbn_b4_bt_8_921600 },
3353         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3354                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3355                 pbn_b0_4_921600 },
3356         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3357                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3358                 pbn_b0_4_921600 },
3359         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3361                 pbn_b0_4_921600 },
3362         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3364                 pbn_oxsemi_1_4000000 },
3365         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3366                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3367                 pbn_oxsemi_2_4000000 },
3368         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3369                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370                 pbn_oxsemi_4_4000000 },
3371         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3372                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3373                 pbn_oxsemi_8_4000000 },
3374         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3375                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3376                 pbn_oxsemi_2_4000000 },
3377         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3378                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3379                 pbn_oxsemi_2_4000000 },
3380
3381         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3382                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3383                 pbn_b2_1_460800 },
3384         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3385                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3386                 pbn_b2_1_460800 },
3387         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3388                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3389                 pbn_b2_1_460800 },
3390         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3391                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392                 pbn_b2_bt_2_921600 },
3393         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3394                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395                 pbn_b2_bt_2_921600 },
3396         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3397                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398                 pbn_b2_bt_2_921600 },
3399         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3400                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401                 pbn_b2_bt_4_921600 },
3402         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3403                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404                 pbn_b2_bt_4_921600 },
3405         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3406                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407                 pbn_b2_bt_4_921600 },
3408         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3409                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410                 pbn_b0_1_921600 },
3411         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3412                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413                 pbn_b0_1_921600 },
3414         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3415                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416                 pbn_b0_1_921600 },
3417         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3418                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419                 pbn_b0_bt_2_921600 },
3420         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3421                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422                 pbn_b0_bt_2_921600 },
3423         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3424                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425                 pbn_b0_bt_2_921600 },
3426         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3427                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428                 pbn_b0_bt_4_921600 },
3429         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3430                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431                 pbn_b0_bt_4_921600 },
3432         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3433                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434                 pbn_b0_bt_4_921600 },
3435         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3436                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437                 pbn_b0_bt_8_921600 },
3438         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3439                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440                 pbn_b0_bt_8_921600 },
3441         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3442                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443                 pbn_b0_bt_8_921600 },
3444
3445         /*
3446          * Computone devices submitted by Doug McNash dmcnash@computone.com
3447          */
3448         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3449                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3450                 0, 0, pbn_computone_4 },
3451         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3452                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3453                 0, 0, pbn_computone_8 },
3454         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3455                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3456                 0, 0, pbn_computone_6 },
3457
3458         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460                 pbn_oxsemi },
3461         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3462                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3463                 pbn_b0_bt_1_921600 },
3464
3465         /*
3466          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3467          */
3468         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3469                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3470                 pbn_b0_bt_8_115200 },
3471         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3472                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3473                 pbn_b0_bt_8_115200 },
3474
3475         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477                 pbn_b0_bt_2_115200 },
3478         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480                 pbn_b0_bt_2_115200 },
3481         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483                 pbn_b0_bt_2_115200 },
3484         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486                 pbn_b0_bt_2_115200 },
3487         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489                 pbn_b0_bt_2_115200 },
3490         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492                 pbn_b0_bt_4_460800 },
3493         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495                 pbn_b0_bt_4_460800 },
3496         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498                 pbn_b0_bt_2_460800 },
3499         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501                 pbn_b0_bt_2_460800 },
3502         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3504                 pbn_b0_bt_2_460800 },
3505         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507                 pbn_b0_bt_1_115200 },
3508         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510                 pbn_b0_bt_1_460800 },
3511
3512         /*
3513          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3514          * Cards are identified by their subsystem vendor IDs, which
3515          * (in hex) match the model number.
3516          *
3517          * Note that JC140x are RS422/485 cards which require ox950
3518          * ACR = 0x10, and as such are not currently fully supported.
3519          */
3520         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3521                 0x1204, 0x0004, 0, 0,
3522                 pbn_b0_4_921600 },
3523         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3524                 0x1208, 0x0004, 0, 0,
3525                 pbn_b0_4_921600 },
3526 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3527                 0x1402, 0x0002, 0, 0,
3528                 pbn_b0_2_921600 }, */
3529 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3530                 0x1404, 0x0004, 0, 0,
3531                 pbn_b0_4_921600 }, */
3532         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3533                 0x1208, 0x0004, 0, 0,
3534                 pbn_b0_4_921600 },
3535
3536         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3537                 0x1204, 0x0004, 0, 0,
3538                 pbn_b0_4_921600 },
3539         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3540                 0x1208, 0x0004, 0, 0,
3541                 pbn_b0_4_921600 },
3542         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3543                 0x1208, 0x0004, 0, 0,
3544                 pbn_b0_4_921600 },
3545         /*
3546          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3547          */
3548         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3549                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3550                 pbn_b1_1_1382400 },
3551
3552         /*
3553          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3554          */
3555         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3556                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557                 pbn_b1_1_1382400 },
3558
3559         /*
3560          * RAStel 2 port modem, gerg@moreton.com.au
3561          */
3562         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3563                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3564                 pbn_b2_bt_2_115200 },
3565
3566         /*
3567          * EKF addition for i960 Boards form EKF with serial port
3568          */
3569         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3570                 0xE4BF, PCI_ANY_ID, 0, 0,
3571                 pbn_intel_i960 },
3572
3573         /*
3574          * Xircom Cardbus/Ethernet combos
3575          */
3576         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3577                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3578                 pbn_b0_1_115200 },
3579         /*
3580          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3581          */
3582         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3583                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3584                 pbn_b0_1_115200 },
3585
3586         /*
3587          * Untested PCI modems, sent in from various folks...
3588          */
3589
3590         /*
3591          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3592          */
3593         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3594                 0x1048, 0x1500, 0, 0,
3595                 pbn_b1_1_115200 },
3596
3597         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3598                 0xFF00, 0, 0, 0,
3599                 pbn_sgi_ioc3 },
3600
3601         /*
3602          * HP Diva card
3603          */
3604         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3605                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3606                 pbn_b1_1_115200 },
3607         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3608                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3609                 pbn_b0_5_115200 },
3610         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3611                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3612                 pbn_b2_1_115200 },
3613
3614         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616                 pbn_b3_2_115200 },
3617         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3619                 pbn_b3_4_115200 },
3620         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3621                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3622                 pbn_b3_8_115200 },
3623
3624         /*
3625          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3626          */
3627         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3628                 PCI_ANY_ID, PCI_ANY_ID,
3629                 0,
3630                 0, pbn_exar_XR17C152 },
3631         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3632                 PCI_ANY_ID, PCI_ANY_ID,
3633                 0,
3634                 0, pbn_exar_XR17C154 },
3635         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3636                 PCI_ANY_ID, PCI_ANY_ID,
3637                 0,
3638                 0, pbn_exar_XR17C158 },
3639
3640         /*
3641          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3642          */
3643         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3644                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3645                 pbn_b0_1_115200 },
3646         /*
3647          * ITE
3648          */
3649         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3650                 PCI_ANY_ID, PCI_ANY_ID,
3651                 0, 0,
3652                 pbn_b1_bt_1_115200 },
3653
3654         /*
3655          * IntaShield IS-200
3656          */
3657         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3658                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3659                 pbn_b2_2_115200 },
3660         /*
3661          * IntaShield IS-400
3662          */
3663         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3664                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3665                 pbn_b2_4_115200 },
3666         /*
3667          * Perle PCI-RAS cards
3668          */
3669         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3670                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3671                 0, 0, pbn_b2_4_921600 },
3672         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3673                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3674                 0, 0, pbn_b2_8_921600 },
3675
3676         /*
3677          * Mainpine series cards: Fairly standard layout but fools
3678          * parts of the autodetect in some cases and uses otherwise
3679          * unmatched communications subclasses in the PCI Express case
3680          */
3681
3682         {       /* RockForceDUO */
3683                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3684                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3685                 0, 0, pbn_b0_2_115200 },
3686         {       /* RockForceQUATRO */
3687                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3688                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3689                 0, 0, pbn_b0_4_115200 },
3690         {       /* RockForceDUO+ */
3691                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3692                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3693                 0, 0, pbn_b0_2_115200 },
3694         {       /* RockForceQUATRO+ */
3695                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3696                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3697                 0, 0, pbn_b0_4_115200 },
3698         {       /* RockForce+ */
3699                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3700                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3701                 0, 0, pbn_b0_2_115200 },
3702         {       /* RockForce+ */
3703                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3704                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3705                 0, 0, pbn_b0_4_115200 },
3706         {       /* RockForceOCTO+ */
3707                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3708                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3709                 0, 0, pbn_b0_8_115200 },
3710         {       /* RockForceDUO+ */
3711                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3712                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3713                 0, 0, pbn_b0_2_115200 },
3714         {       /* RockForceQUARTRO+ */
3715                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3716                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3717                 0, 0, pbn_b0_4_115200 },
3718         {       /* RockForceOCTO+ */
3719                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3720                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3721                 0, 0, pbn_b0_8_115200 },
3722         {       /* RockForceD1 */
3723                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3724                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3725                 0, 0, pbn_b0_1_115200 },
3726         {       /* RockForceF1 */
3727                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3728                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3729                 0, 0, pbn_b0_1_115200 },
3730         {       /* RockForceD2 */
3731                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3732                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3733                 0, 0, pbn_b0_2_115200 },
3734         {       /* RockForceF2 */
3735                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3736                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3737                 0, 0, pbn_b0_2_115200 },
3738         {       /* RockForceD4 */
3739                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3740                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3741                 0, 0, pbn_b0_4_115200 },
3742         {       /* RockForceF4 */
3743                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3744                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3745                 0, 0, pbn_b0_4_115200 },
3746         {       /* RockForceD8 */
3747                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3748                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3749                 0, 0, pbn_b0_8_115200 },
3750         {       /* RockForceF8 */
3751                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3752                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3753                 0, 0, pbn_b0_8_115200 },
3754         {       /* IQ Express D1 */
3755                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3756                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3757                 0, 0, pbn_b0_1_115200 },
3758         {       /* IQ Express F1 */
3759                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3760                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3761                 0, 0, pbn_b0_1_115200 },
3762         {       /* IQ Express D2 */
3763                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3764                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3765                 0, 0, pbn_b0_2_115200 },
3766         {       /* IQ Express F2 */
3767                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3768                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3769                 0, 0, pbn_b0_2_115200 },
3770         {       /* IQ Express D4 */
3771                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3772                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3773                 0, 0, pbn_b0_4_115200 },
3774         {       /* IQ Express F4 */
3775                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3776                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3777                 0, 0, pbn_b0_4_115200 },
3778         {       /* IQ Express D8 */
3779                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3780                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3781                 0, 0, pbn_b0_8_115200 },
3782         {       /* IQ Express F8 */
3783                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3784                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3785                 0, 0, pbn_b0_8_115200 },
3786
3787
3788         /*
3789          * PA Semi PA6T-1682M on-chip UART
3790          */
3791         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3792                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3793                 pbn_pasemi_1682M },
3794
3795         /*
3796          * National Instruments
3797          */
3798         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3799                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3800                 pbn_b1_16_115200 },
3801         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3802                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3803                 pbn_b1_8_115200 },
3804         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3805                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3806                 pbn_b1_bt_4_115200 },
3807         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3808                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3809                 pbn_b1_bt_2_115200 },
3810         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3811                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3812                 pbn_b1_bt_4_115200 },
3813         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3814                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3815                 pbn_b1_bt_2_115200 },
3816         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3817                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3818                 pbn_b1_16_115200 },
3819         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3820                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3821                 pbn_b1_8_115200 },
3822         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3823                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3824                 pbn_b1_bt_4_115200 },
3825         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3826                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3827                 pbn_b1_bt_2_115200 },
3828         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3830                 pbn_b1_bt_4_115200 },
3831         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3833                 pbn_b1_bt_2_115200 },
3834         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3836                 pbn_ni8430_2 },
3837         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3839                 pbn_ni8430_2 },
3840         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3841                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3842                 pbn_ni8430_4 },
3843         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3844                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3845                 pbn_ni8430_4 },
3846         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3847                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3848                 pbn_ni8430_8 },
3849         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3850                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3851                 pbn_ni8430_8 },
3852         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3853                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3854                 pbn_ni8430_16 },
3855         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3856                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3857                 pbn_ni8430_16 },
3858         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3859                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3860                 pbn_ni8430_2 },
3861         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3862                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3863                 pbn_ni8430_2 },
3864         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3865                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3866                 pbn_ni8430_4 },
3867         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3868                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3869                 pbn_ni8430_4 },
3870
3871         /*
3872         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3873         */
3874         {       PCI_VENDOR_ID_ADDIDATA,
3875                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3876                 PCI_ANY_ID,
3877                 PCI_ANY_ID,
3878                 0,
3879                 0,
3880                 pbn_b0_4_115200 },
3881
3882         {       PCI_VENDOR_ID_ADDIDATA,
3883                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3884                 PCI_ANY_ID,
3885                 PCI_ANY_ID,
3886                 0,
3887                 0,
3888                 pbn_b0_2_115200 },
3889
3890         {       PCI_VENDOR_ID_ADDIDATA,
3891                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3892                 PCI_ANY_ID,
3893                 PCI_ANY_ID,
3894                 0,
3895                 0,
3896                 pbn_b0_1_115200 },
3897
3898         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3899                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3900                 PCI_ANY_ID,
3901                 PCI_ANY_ID,
3902                 0,
3903                 0,
3904                 pbn_b1_8_115200 },
3905
3906         {       PCI_VENDOR_ID_ADDIDATA,
3907                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3908                 PCI_ANY_ID,
3909                 PCI_ANY_ID,
3910                 0,
3911                 0,
3912                 pbn_b0_4_115200 },
3913
3914         {       PCI_VENDOR_ID_ADDIDATA,
3915                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3916                 PCI_ANY_ID,
3917                 PCI_ANY_ID,
3918                 0,
3919                 0,
3920                 pbn_b0_2_115200 },
3921
3922         {       PCI_VENDOR_ID_ADDIDATA,
3923                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3924                 PCI_ANY_ID,
3925                 PCI_ANY_ID,
3926                 0,
3927                 0,
3928                 pbn_b0_1_115200 },
3929
3930         {       PCI_VENDOR_ID_ADDIDATA,
3931                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3932                 PCI_ANY_ID,
3933                 PCI_ANY_ID,
3934                 0,
3935                 0,
3936                 pbn_b0_4_115200 },
3937
3938         {       PCI_VENDOR_ID_ADDIDATA,
3939                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3940                 PCI_ANY_ID,
3941                 PCI_ANY_ID,
3942                 0,
3943                 0,
3944                 pbn_b0_2_115200 },
3945
3946         {       PCI_VENDOR_ID_ADDIDATA,
3947                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3948                 PCI_ANY_ID,
3949                 PCI_ANY_ID,
3950                 0,
3951                 0,
3952                 pbn_b0_1_115200 },
3953
3954         {       PCI_VENDOR_ID_ADDIDATA,
3955                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3956                 PCI_ANY_ID,
3957                 PCI_ANY_ID,
3958                 0,
3959                 0,
3960                 pbn_b0_8_115200 },
3961
3962         {       PCI_VENDOR_ID_ADDIDATA,
3963                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3964                 PCI_ANY_ID,
3965                 PCI_ANY_ID,
3966                 0,
3967                 0,
3968                 pbn_ADDIDATA_PCIe_4_3906250 },
3969
3970         {       PCI_VENDOR_ID_ADDIDATA,
3971                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3972                 PCI_ANY_ID,
3973                 PCI_ANY_ID,
3974                 0,
3975                 0,
3976                 pbn_ADDIDATA_PCIe_2_3906250 },
3977
3978         {       PCI_VENDOR_ID_ADDIDATA,
3979                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3980                 PCI_ANY_ID,
3981                 PCI_ANY_ID,
3982                 0,
3983                 0,
3984                 pbn_ADDIDATA_PCIe_1_3906250 },
3985
3986         {       PCI_VENDOR_ID_ADDIDATA,
3987                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3988                 PCI_ANY_ID,
3989                 PCI_ANY_ID,
3990                 0,
3991                 0,
3992                 pbn_ADDIDATA_PCIe_8_3906250 },
3993
3994         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3995                 PCI_VENDOR_ID_IBM, 0x0299,
3996                 0, 0, pbn_b0_bt_2_115200 },
3997
3998         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3999                 0xA000, 0x1000,
4000                 0, 0, pbn_b0_1_115200 },
4001
4002         /* the 9901 is a rebranded 9912 */
4003         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4004                 0xA000, 0x1000,
4005                 0, 0, pbn_b0_1_115200 },
4006
4007         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4008                 0xA000, 0x1000,
4009                 0, 0, pbn_b0_1_115200 },
4010
4011         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4012                 0xA000, 0x1000,
4013                 0, 0, pbn_b0_1_115200 },
4014
4015         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4016                 0xA000, 0x1000,
4017                 0, 0, pbn_b0_1_115200 },
4018
4019         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4020                 0xA000, 0x3002,
4021                 0, 0, pbn_NETMOS9900_2s_115200 },
4022
4023         /*
4024          * Best Connectivity PCI Multi I/O cards
4025          */
4026
4027         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4028                 0xA000, 0x1000,
4029                 0, 0, pbn_b0_1_115200 },
4030
4031         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4032                 0xA000, 0x3004,
4033                 0, 0, pbn_b0_bt_4_115200 },
4034         /* Intel CE4100 */
4035         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4036                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4037                 pbn_ce4100_1_115200 },
4038
4039         /*
4040          * Cronyx Omega PCI
4041          */
4042         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4043                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4044                 pbn_omegapci },
4045
4046         /*
4047          * These entries match devices with class COMMUNICATION_SERIAL,
4048          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4049          */
4050         {       PCI_ANY_ID, PCI_ANY_ID,
4051                 PCI_ANY_ID, PCI_ANY_ID,
4052                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4053                 0xffff00, pbn_default },
4054         {       PCI_ANY_ID, PCI_ANY_ID,
4055                 PCI_ANY_ID, PCI_ANY_ID,
4056                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4057                 0xffff00, pbn_default },
4058         {       PCI_ANY_ID, PCI_ANY_ID,
4059                 PCI_ANY_ID, PCI_ANY_ID,
4060                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4061                 0xffff00, pbn_default },
4062         { 0, }
4063 };
4064
4065 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4066                                                 pci_channel_state_t state)
4067 {
4068         struct serial_private *priv = pci_get_drvdata(dev);
4069
4070         if (state == pci_channel_io_perm_failure)
4071                 return PCI_ERS_RESULT_DISCONNECT;
4072
4073         if (priv)
4074                 pciserial_suspend_ports(priv);
4075
4076         pci_disable_device(dev);
4077
4078         return PCI_ERS_RESULT_NEED_RESET;
4079 }
4080
4081 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4082 {
4083         int rc;
4084
4085         rc = pci_enable_device(dev);
4086
4087         if (rc)
4088                 return PCI_ERS_RESULT_DISCONNECT;
4089
4090         pci_restore_state(dev);
4091         pci_save_state(dev);
4092
4093         return PCI_ERS_RESULT_RECOVERED;
4094 }
4095
4096 static void serial8250_io_resume(struct pci_dev *dev)
4097 {
4098         struct serial_private *priv = pci_get_drvdata(dev);
4099
4100         if (priv)
4101                 pciserial_resume_ports(priv);
4102 }
4103
4104 static struct pci_error_handlers serial8250_err_handler = {
4105         .error_detected = serial8250_io_error_detected,
4106         .slot_reset = serial8250_io_slot_reset,
4107         .resume = serial8250_io_resume,
4108 };
4109
4110 static struct pci_driver serial_pci_driver = {
4111         .name           = "serial",
4112         .probe          = pciserial_init_one,
4113         .remove         = __devexit_p(pciserial_remove_one),
4114 #ifdef CONFIG_PM
4115         .suspend        = pciserial_suspend_one,
4116         .resume         = pciserial_resume_one,
4117 #endif
4118         .id_table       = serial_pci_tbl,
4119         .err_handler    = &serial8250_err_handler,
4120 };
4121
4122 static int __init serial8250_pci_init(void)
4123 {
4124         return pci_register_driver(&serial_pci_driver);
4125 }
4126
4127 static void __exit serial8250_pci_exit(void)
4128 {
4129         pci_unregister_driver(&serial_pci_driver);
4130 }
4131
4132 module_init(serial8250_pci_init);
4133 module_exit(serial8250_pci_exit);
4134
4135 MODULE_LICENSE("GPL");
4136 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4137 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);