2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60 static struct uart_driver serial8250_reg;
62 static int serial_index(struct uart_port *port)
64 return (serial8250_reg.minor - 64) + port->line;
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
79 #define DEBUG_INTR(fmt...) printk(fmt)
81 #define DEBUG_INTR(fmt...) do { } while (0)
84 #define PASS_LIMIT 512
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
94 #define is_real_interrupt(irq) ((irq) != 0)
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
107 #define CONFIG_HUB6 1
109 #include <asm/serial.h>
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
125 #ifdef CONFIG_SERIAL_8250_RSA
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
159 struct hlist_node node;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
170 * Here we define the default xmit fifo size used for each type of UART.
172 static const struct serial8250_config uart_config[] = {
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
233 .name = "16C950/954",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
319 [PORT_BRCM_TRUMANAGE] = {
323 .flags = UART_CAP_HFIFO,
325 [PORT_ALTR_16550_F32] = {
326 .name = "Altera 16550 FIFO32",
329 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
330 .flags = UART_CAP_FIFO | UART_CAP_AFE,
332 [PORT_ALTR_16550_F64] = {
333 .name = "Altera 16550 FIFO64",
336 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
337 .flags = UART_CAP_FIFO | UART_CAP_AFE,
339 [PORT_ALTR_16550_F128] = {
340 .name = "Altera 16550 FIFO128",
343 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
344 .flags = UART_CAP_FIFO | UART_CAP_AFE,
348 #if defined(CONFIG_MIPS_ALCHEMY)
350 /* Au1x00 UART hardware has a weird register layout */
351 static const u8 au_io_in_map[] = {
361 static const u8 au_io_out_map[] = {
369 /* sane hardware needs no mapping */
370 static inline int map_8250_in_reg(struct uart_port *p, int offset)
372 if (p->iotype != UPIO_AU)
374 return au_io_in_map[offset];
377 static inline int map_8250_out_reg(struct uart_port *p, int offset)
379 if (p->iotype != UPIO_AU)
381 return au_io_out_map[offset];
384 #elif defined(CONFIG_SERIAL_8250_RM9K)
408 static inline int map_8250_in_reg(struct uart_port *p, int offset)
410 if (p->iotype != UPIO_RM9000)
412 return regmap_in[offset];
415 static inline int map_8250_out_reg(struct uart_port *p, int offset)
417 if (p->iotype != UPIO_RM9000)
419 return regmap_out[offset];
424 /* sane hardware needs no mapping */
425 #define map_8250_in_reg(up, offset) (offset)
426 #define map_8250_out_reg(up, offset) (offset)
430 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
432 offset = map_8250_in_reg(p, offset) << p->regshift;
433 outb(p->hub6 - 1 + offset, p->iobase);
434 return inb(p->iobase + 1);
437 static void hub6_serial_out(struct uart_port *p, int offset, int value)
439 offset = map_8250_out_reg(p, offset) << p->regshift;
440 outb(p->hub6 - 1 + offset, p->iobase);
441 outb(value, p->iobase + 1);
444 static unsigned int mem_serial_in(struct uart_port *p, int offset)
446 offset = map_8250_in_reg(p, offset) << p->regshift;
447 return readb(p->membase + offset);
450 static void mem_serial_out(struct uart_port *p, int offset, int value)
452 offset = map_8250_out_reg(p, offset) << p->regshift;
453 writeb(value, p->membase + offset);
456 static void mem32_serial_out(struct uart_port *p, int offset, int value)
458 offset = map_8250_out_reg(p, offset) << p->regshift;
459 writel(value, p->membase + offset);
462 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
464 offset = map_8250_in_reg(p, offset) << p->regshift;
465 return readl(p->membase + offset);
468 static unsigned int au_serial_in(struct uart_port *p, int offset)
470 offset = map_8250_in_reg(p, offset) << p->regshift;
471 return __raw_readl(p->membase + offset);
474 static void au_serial_out(struct uart_port *p, int offset, int value)
476 offset = map_8250_out_reg(p, offset) << p->regshift;
477 __raw_writel(value, p->membase + offset);
480 static unsigned int io_serial_in(struct uart_port *p, int offset)
482 offset = map_8250_in_reg(p, offset) << p->regshift;
483 return inb(p->iobase + offset);
486 static void io_serial_out(struct uart_port *p, int offset, int value)
488 offset = map_8250_out_reg(p, offset) << p->regshift;
489 outb(value, p->iobase + offset);
492 static int serial8250_default_handle_irq(struct uart_port *port);
494 static void set_io_from_upio(struct uart_port *p)
496 struct uart_8250_port *up =
497 container_of(p, struct uart_8250_port, port);
500 p->serial_in = hub6_serial_in;
501 p->serial_out = hub6_serial_out;
505 p->serial_in = mem_serial_in;
506 p->serial_out = mem_serial_out;
511 p->serial_in = mem32_serial_in;
512 p->serial_out = mem32_serial_out;
516 p->serial_in = au_serial_in;
517 p->serial_out = au_serial_out;
521 p->serial_in = io_serial_in;
522 p->serial_out = io_serial_out;
525 /* Remember loaded iotype */
526 up->cur_iotype = p->iotype;
527 p->handle_irq = serial8250_default_handle_irq;
531 serial_out_sync(struct uart_8250_port *up, int offset, int value)
533 struct uart_port *p = &up->port;
538 p->serial_out(p, offset, value);
539 p->serial_in(p, UART_LCR); /* safe, no side-effects */
542 p->serial_out(p, offset, value);
546 #define serial_in(up, offset) \
547 (up->port.serial_in(&(up)->port, (offset)))
548 #define serial_out(up, offset, value) \
549 (up->port.serial_out(&(up)->port, (offset), (value)))
551 * We used to support using pause I/O for certain machines. We
552 * haven't supported this for a while, but just in case it's badly
553 * needed for certain old 386 machines, I've left these #define's
556 #define serial_inp(up, offset) serial_in(up, offset)
557 #define serial_outp(up, offset, value) serial_out(up, offset, value)
559 /* Uart divisor latch read */
560 static inline int _serial_dl_read(struct uart_8250_port *up)
562 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
565 /* Uart divisor latch write */
566 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
568 serial_outp(up, UART_DLL, value & 0xff);
569 serial_outp(up, UART_DLM, value >> 8 & 0xff);
572 #if defined(CONFIG_MIPS_ALCHEMY)
573 /* Au1x00 haven't got a standard divisor latch */
574 static int serial_dl_read(struct uart_8250_port *up)
576 if (up->port.iotype == UPIO_AU)
577 return __raw_readl(up->port.membase + 0x28);
579 return _serial_dl_read(up);
582 static void serial_dl_write(struct uart_8250_port *up, int value)
584 if (up->port.iotype == UPIO_AU)
585 __raw_writel(value, up->port.membase + 0x28);
587 _serial_dl_write(up, value);
589 #elif defined(CONFIG_SERIAL_8250_RM9K)
590 static int serial_dl_read(struct uart_8250_port *up)
592 return (up->port.iotype == UPIO_RM9000) ?
593 (((__raw_readl(up->port.membase + 0x10) << 8) |
594 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
598 static void serial_dl_write(struct uart_8250_port *up, int value)
600 if (up->port.iotype == UPIO_RM9000) {
601 __raw_writel(value, up->port.membase + 0x08);
602 __raw_writel(value >> 8, up->port.membase + 0x10);
604 _serial_dl_write(up, value);
608 #define serial_dl_read(up) _serial_dl_read(up)
609 #define serial_dl_write(up, value) _serial_dl_write(up, value)
615 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
617 serial_out(up, UART_SCR, offset);
618 serial_out(up, UART_ICR, value);
621 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
625 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
626 serial_out(up, UART_SCR, offset);
627 value = serial_in(up, UART_ICR);
628 serial_icr_write(up, UART_ACR, up->acr);
636 static void serial8250_clear_fifos(struct uart_8250_port *p)
638 if (p->capabilities & UART_CAP_FIFO) {
639 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
640 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
641 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
642 serial_outp(p, UART_FCR, 0);
647 * IER sleep support. UARTs which have EFRs need the "extended
648 * capability" bit enabled. Note that on XR16C850s, we need to
649 * reset LCR to write to IER.
651 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
653 if (p->capabilities & UART_CAP_SLEEP) {
654 if (p->capabilities & UART_CAP_EFR) {
655 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
656 serial_outp(p, UART_EFR, UART_EFR_ECB);
657 serial_outp(p, UART_LCR, 0);
659 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
660 if (p->capabilities & UART_CAP_EFR) {
661 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
662 serial_outp(p, UART_EFR, 0);
663 serial_outp(p, UART_LCR, 0);
668 #ifdef CONFIG_SERIAL_8250_RSA
670 * Attempts to turn on the RSA FIFO. Returns zero on failure.
671 * We set the port uart clock rate if we succeed.
673 static int __enable_rsa(struct uart_8250_port *up)
678 mode = serial_inp(up, UART_RSA_MSR);
679 result = mode & UART_RSA_MSR_FIFO;
682 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
683 mode = serial_inp(up, UART_RSA_MSR);
684 result = mode & UART_RSA_MSR_FIFO;
688 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
693 static void enable_rsa(struct uart_8250_port *up)
695 if (up->port.type == PORT_RSA) {
696 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
697 spin_lock_irq(&up->port.lock);
699 spin_unlock_irq(&up->port.lock);
701 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
702 serial_outp(up, UART_RSA_FRR, 0);
707 * Attempts to turn off the RSA FIFO. Returns zero on failure.
708 * It is unknown why interrupts were disabled in here. However,
709 * the caller is expected to preserve this behaviour by grabbing
710 * the spinlock before calling this function.
712 static void disable_rsa(struct uart_8250_port *up)
717 if (up->port.type == PORT_RSA &&
718 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
719 spin_lock_irq(&up->port.lock);
721 mode = serial_inp(up, UART_RSA_MSR);
722 result = !(mode & UART_RSA_MSR_FIFO);
725 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
726 mode = serial_inp(up, UART_RSA_MSR);
727 result = !(mode & UART_RSA_MSR_FIFO);
731 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
732 spin_unlock_irq(&up->port.lock);
735 #endif /* CONFIG_SERIAL_8250_RSA */
738 * This is a quickie test to see how big the FIFO is.
739 * It doesn't work at all the time, more's the pity.
741 static int size_fifo(struct uart_8250_port *up)
743 unsigned char old_fcr, old_mcr, old_lcr;
744 unsigned short old_dl;
747 old_lcr = serial_inp(up, UART_LCR);
748 serial_outp(up, UART_LCR, 0);
749 old_fcr = serial_inp(up, UART_FCR);
750 old_mcr = serial_inp(up, UART_MCR);
751 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
752 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
753 serial_outp(up, UART_MCR, UART_MCR_LOOP);
754 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
755 old_dl = serial_dl_read(up);
756 serial_dl_write(up, 0x0001);
757 serial_outp(up, UART_LCR, 0x03);
758 for (count = 0; count < 256; count++)
759 serial_outp(up, UART_TX, count);
760 mdelay(20);/* FIXME - schedule_timeout */
761 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
762 (count < 256); count++)
763 serial_inp(up, UART_RX);
764 serial_outp(up, UART_FCR, old_fcr);
765 serial_outp(up, UART_MCR, old_mcr);
766 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
767 serial_dl_write(up, old_dl);
768 serial_outp(up, UART_LCR, old_lcr);
774 * Read UART ID using the divisor method - set DLL and DLM to zero
775 * and the revision will be in DLL and device type in DLM. We
776 * preserve the device state across this.
778 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
780 unsigned char old_lcr;
781 unsigned int id, old_dl;
783 old_lcr = serial_inp(p, UART_LCR);
784 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
785 old_dl = serial_dl_read(p);
786 serial_dl_write(p, 0);
787 id = serial_dl_read(p);
788 serial_dl_write(p, old_dl);
790 serial_outp(p, UART_LCR, old_lcr);
796 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
797 * When this function is called we know it is at least a StarTech
798 * 16650 V2, but it might be one of several StarTech UARTs, or one of
799 * its clones. (We treat the broken original StarTech 16650 V1 as a
800 * 16550, and why not? Startech doesn't seem to even acknowledge its
803 * What evil have men's minds wrought...
805 static void autoconfig_has_efr(struct uart_8250_port *up)
807 unsigned int id1, id2, id3, rev;
810 * Everything with an EFR has SLEEP
812 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
815 * First we check to see if it's an Oxford Semiconductor UART.
817 * If we have to do this here because some non-National
818 * Semiconductor clone chips lock up if you try writing to the
819 * LSR register (which serial_icr_read does)
823 * Check for Oxford Semiconductor 16C950.
825 * EFR [4] must be set else this test fails.
827 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
828 * claims that it's needed for 952 dual UART's (which are not
829 * recommended for new designs).
832 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
833 serial_out(up, UART_EFR, UART_EFR_ECB);
834 serial_out(up, UART_LCR, 0x00);
835 id1 = serial_icr_read(up, UART_ID1);
836 id2 = serial_icr_read(up, UART_ID2);
837 id3 = serial_icr_read(up, UART_ID3);
838 rev = serial_icr_read(up, UART_REV);
840 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
842 if (id1 == 0x16 && id2 == 0xC9 &&
843 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
844 up->port.type = PORT_16C950;
847 * Enable work around for the Oxford Semiconductor 952 rev B
848 * chip which causes it to seriously miscalculate baud rates
851 if (id3 == 0x52 && rev == 0x01)
852 up->bugs |= UART_BUG_QUOT;
857 * We check for a XR16C850 by setting DLL and DLM to 0, and then
858 * reading back DLL and DLM. The chip type depends on the DLM
860 * 0x10 - XR16C850 and the DLL contains the chip revision.
864 id1 = autoconfig_read_divisor_id(up);
865 DEBUG_AUTOCONF("850id=%04x ", id1);
868 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
869 up->port.type = PORT_16850;
874 * It wasn't an XR16C850.
876 * We distinguish between the '654 and the '650 by counting
877 * how many bytes are in the FIFO. I'm using this for now,
878 * since that's the technique that was sent to me in the
879 * serial driver update, but I'm not convinced this works.
880 * I've had problems doing this in the past. -TYT
882 if (size_fifo(up) == 64)
883 up->port.type = PORT_16654;
885 up->port.type = PORT_16650V2;
889 * We detected a chip without a FIFO. Only two fall into
890 * this category - the original 8250 and the 16450. The
891 * 16450 has a scratch register (accessible with LCR=0)
893 static void autoconfig_8250(struct uart_8250_port *up)
895 unsigned char scratch, status1, status2;
897 up->port.type = PORT_8250;
899 scratch = serial_in(up, UART_SCR);
900 serial_outp(up, UART_SCR, 0xa5);
901 status1 = serial_in(up, UART_SCR);
902 serial_outp(up, UART_SCR, 0x5a);
903 status2 = serial_in(up, UART_SCR);
904 serial_outp(up, UART_SCR, scratch);
906 if (status1 == 0xa5 && status2 == 0x5a)
907 up->port.type = PORT_16450;
910 static int broken_efr(struct uart_8250_port *up)
913 * Exar ST16C2550 "A2" devices incorrectly detect as
914 * having an EFR, and report an ID of 0x0201. See
915 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
917 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
923 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
925 unsigned char status;
927 status = serial_in(up, 0x04); /* EXCR2 */
928 #define PRESL(x) ((x) & 0x30)
929 if (PRESL(status) == 0x10) {
930 /* already in high speed mode */
933 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
934 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
935 serial_outp(up, 0x04, status);
941 * We know that the chip has FIFOs. Does it have an EFR? The
942 * EFR is located in the same register position as the IIR and
943 * we know the top two bits of the IIR are currently set. The
944 * EFR should contain zero. Try to read the EFR.
946 static void autoconfig_16550a(struct uart_8250_port *up)
948 unsigned char status1, status2;
949 unsigned int iersave;
951 up->port.type = PORT_16550A;
952 up->capabilities |= UART_CAP_FIFO;
955 * Check for presence of the EFR when DLAB is set.
956 * Only ST16C650V1 UARTs pass this test.
958 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
959 if (serial_in(up, UART_EFR) == 0) {
960 serial_outp(up, UART_EFR, 0xA8);
961 if (serial_in(up, UART_EFR) != 0) {
962 DEBUG_AUTOCONF("EFRv1 ");
963 up->port.type = PORT_16650;
964 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
966 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
968 serial_outp(up, UART_EFR, 0);
973 * Maybe it requires 0xbf to be written to the LCR.
974 * (other ST16C650V2 UARTs, TI16C752A, etc)
976 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
977 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
978 DEBUG_AUTOCONF("EFRv2 ");
979 autoconfig_has_efr(up);
984 * Check for a National Semiconductor SuperIO chip.
985 * Attempt to switch to bank 2, read the value of the LOOP bit
986 * from EXCR1. Switch back to bank 0, change it in MCR. Then
987 * switch back to bank 2, read it from EXCR1 again and check
988 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
990 serial_outp(up, UART_LCR, 0);
991 status1 = serial_in(up, UART_MCR);
992 serial_outp(up, UART_LCR, 0xE0);
993 status2 = serial_in(up, 0x02); /* EXCR1 */
995 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
996 serial_outp(up, UART_LCR, 0);
997 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
998 serial_outp(up, UART_LCR, 0xE0);
999 status2 = serial_in(up, 0x02); /* EXCR1 */
1000 serial_outp(up, UART_LCR, 0);
1001 serial_outp(up, UART_MCR, status1);
1003 if ((status2 ^ status1) & UART_MCR_LOOP) {
1004 unsigned short quot;
1006 serial_outp(up, UART_LCR, 0xE0);
1008 quot = serial_dl_read(up);
1011 if (ns16550a_goto_highspeed(up))
1012 serial_dl_write(up, quot);
1014 serial_outp(up, UART_LCR, 0);
1016 up->port.uartclk = 921600*16;
1017 up->port.type = PORT_NS16550A;
1018 up->capabilities |= UART_NATSEMI;
1024 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1025 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1026 * Try setting it with and without DLAB set. Cheap clones
1027 * set bit 5 without DLAB set.
1029 serial_outp(up, UART_LCR, 0);
1030 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1031 status1 = serial_in(up, UART_IIR) >> 5;
1032 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1033 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1034 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1035 status2 = serial_in(up, UART_IIR) >> 5;
1036 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1037 serial_outp(up, UART_LCR, 0);
1039 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1041 if (status1 == 6 && status2 == 7) {
1042 up->port.type = PORT_16750;
1043 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1048 * Try writing and reading the UART_IER_UUE bit (b6).
1049 * If it works, this is probably one of the Xscale platform's
1051 * We're going to explicitly set the UUE bit to 0 before
1052 * trying to write and read a 1 just to make sure it's not
1053 * already a 1 and maybe locked there before we even start start.
1055 iersave = serial_in(up, UART_IER);
1056 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1057 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1059 * OK it's in a known zero state, try writing and reading
1060 * without disturbing the current state of the other bits.
1062 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1063 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1066 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1068 DEBUG_AUTOCONF("Xscale ");
1069 up->port.type = PORT_XSCALE;
1070 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1075 * If we got here we couldn't force the IER_UUE bit to 0.
1076 * Log it and continue.
1078 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1080 serial_outp(up, UART_IER, iersave);
1083 * Exar uarts have EFR in a weird location
1085 if (up->port.flags & UPF_EXAR_EFR) {
1086 up->port.type = PORT_XR17D15X;
1087 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1091 * We distinguish between 16550A and U6 16550A by counting
1092 * how many bytes are in the FIFO.
1094 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1095 up->port.type = PORT_U6_16550A;
1096 up->capabilities |= UART_CAP_AFE;
1101 * This routine is called by rs_init() to initialize a specific serial
1102 * port. It determines what type of UART chip this serial port is
1103 * using: 8250, 16450, 16550, 16550A. The important question is
1104 * whether or not this UART is a 16550A or not, since this will
1105 * determine whether or not we can use its FIFO features or not.
1107 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1109 unsigned char status1, scratch, scratch2, scratch3;
1110 unsigned char save_lcr, save_mcr;
1111 unsigned long flags;
1113 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1116 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1117 serial_index(&up->port), up->port.iobase, up->port.membase);
1120 * We really do need global IRQs disabled here - we're going to
1121 * be frobbing the chips IRQ enable register to see if it exists.
1123 spin_lock_irqsave(&up->port.lock, flags);
1125 up->capabilities = 0;
1128 if (!(up->port.flags & UPF_BUGGY_UART)) {
1130 * Do a simple existence test first; if we fail this,
1131 * there's no point trying anything else.
1133 * 0x80 is used as a nonsense port to prevent against
1134 * false positives due to ISA bus float. The
1135 * assumption is that 0x80 is a non-existent port;
1136 * which should be safe since include/asm/io.h also
1137 * makes this assumption.
1139 * Note: this is safe as long as MCR bit 4 is clear
1140 * and the device is in "PC" mode.
1142 scratch = serial_inp(up, UART_IER);
1143 serial_outp(up, UART_IER, 0);
1148 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1149 * 16C754B) allow only to modify them if an EFR bit is set.
1151 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1152 serial_outp(up, UART_IER, 0x0F);
1156 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1157 serial_outp(up, UART_IER, scratch);
1158 if (scratch2 != 0 || scratch3 != 0x0F) {
1160 * We failed; there's nothing here
1162 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1163 scratch2, scratch3);
1168 save_mcr = serial_in(up, UART_MCR);
1169 save_lcr = serial_in(up, UART_LCR);
1172 * Check to see if a UART is really there. Certain broken
1173 * internal modems based on the Rockwell chipset fail this
1174 * test, because they apparently don't implement the loopback
1175 * test mode. So this test is skipped on the COM 1 through
1176 * COM 4 ports. This *should* be safe, since no board
1177 * manufacturer would be stupid enough to design a board
1178 * that conflicts with COM 1-4 --- we hope!
1180 if (!(up->port.flags & UPF_SKIP_TEST)) {
1181 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1182 status1 = serial_inp(up, UART_MSR) & 0xF0;
1183 serial_outp(up, UART_MCR, save_mcr);
1184 if (status1 != 0x90) {
1185 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1192 * We're pretty sure there's a port here. Lets find out what
1193 * type of port it is. The IIR top two bits allows us to find
1194 * out if it's 8250 or 16450, 16550, 16550A or later. This
1195 * determines what we test for next.
1197 * We also initialise the EFR (if any) to zero for later. The
1198 * EFR occupies the same register location as the FCR and IIR.
1200 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1201 serial_outp(up, UART_EFR, 0);
1202 serial_outp(up, UART_LCR, 0);
1204 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1205 scratch = serial_in(up, UART_IIR) >> 6;
1207 DEBUG_AUTOCONF("iir=%d ", scratch);
1211 autoconfig_8250(up);
1214 up->port.type = PORT_UNKNOWN;
1217 up->port.type = PORT_16550;
1220 autoconfig_16550a(up);
1224 #ifdef CONFIG_SERIAL_8250_RSA
1226 * Only probe for RSA ports if we got the region.
1228 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1231 for (i = 0 ; i < probe_rsa_count; ++i) {
1232 if (probe_rsa[i] == up->port.iobase &&
1234 up->port.type = PORT_RSA;
1241 serial_outp(up, UART_LCR, save_lcr);
1243 if (up->capabilities != uart_config[up->port.type].flags) {
1245 "ttyS%d: detected caps %08x should be %08x\n",
1246 serial_index(&up->port), up->capabilities,
1247 uart_config[up->port.type].flags);
1250 up->port.fifosize = uart_config[up->port.type].fifo_size;
1251 up->capabilities = uart_config[up->port.type].flags;
1252 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1254 if (up->port.type == PORT_UNKNOWN)
1260 #ifdef CONFIG_SERIAL_8250_RSA
1261 if (up->port.type == PORT_RSA)
1262 serial_outp(up, UART_RSA_FRR, 0);
1264 serial_outp(up, UART_MCR, save_mcr);
1265 serial8250_clear_fifos(up);
1266 serial_in(up, UART_RX);
1267 if (up->capabilities & UART_CAP_UUE)
1268 serial_outp(up, UART_IER, UART_IER_UUE);
1270 serial_outp(up, UART_IER, 0);
1273 spin_unlock_irqrestore(&up->port.lock, flags);
1274 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1277 static void autoconfig_irq(struct uart_8250_port *up)
1279 unsigned char save_mcr, save_ier;
1280 unsigned char save_ICP = 0;
1281 unsigned int ICP = 0;
1285 if (up->port.flags & UPF_FOURPORT) {
1286 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1287 save_ICP = inb_p(ICP);
1292 /* forget possible initially masked and pending IRQ */
1293 probe_irq_off(probe_irq_on());
1294 save_mcr = serial_inp(up, UART_MCR);
1295 save_ier = serial_inp(up, UART_IER);
1296 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1298 irqs = probe_irq_on();
1299 serial_outp(up, UART_MCR, 0);
1301 if (up->port.flags & UPF_FOURPORT) {
1302 serial_outp(up, UART_MCR,
1303 UART_MCR_DTR | UART_MCR_RTS);
1305 serial_outp(up, UART_MCR,
1306 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1308 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1309 (void)serial_inp(up, UART_LSR);
1310 (void)serial_inp(up, UART_RX);
1311 (void)serial_inp(up, UART_IIR);
1312 (void)serial_inp(up, UART_MSR);
1313 serial_outp(up, UART_TX, 0xFF);
1315 irq = probe_irq_off(irqs);
1317 serial_outp(up, UART_MCR, save_mcr);
1318 serial_outp(up, UART_IER, save_ier);
1320 if (up->port.flags & UPF_FOURPORT)
1321 outb_p(save_ICP, ICP);
1323 up->port.irq = (irq > 0) ? irq : 0;
1326 static inline void __stop_tx(struct uart_8250_port *p)
1328 if (p->ier & UART_IER_THRI) {
1329 p->ier &= ~UART_IER_THRI;
1330 serial_out(p, UART_IER, p->ier);
1334 static void serial8250_stop_tx(struct uart_port *port)
1336 struct uart_8250_port *up =
1337 container_of(port, struct uart_8250_port, port);
1342 * We really want to stop the transmitter from sending.
1344 if (up->port.type == PORT_16C950) {
1345 up->acr |= UART_ACR_TXDIS;
1346 serial_icr_write(up, UART_ACR, up->acr);
1350 static void transmit_chars(struct uart_8250_port *up);
1352 static void serial8250_start_tx(struct uart_port *port)
1354 struct uart_8250_port *up =
1355 container_of(port, struct uart_8250_port, port);
1357 if (!(up->ier & UART_IER_THRI)) {
1358 up->ier |= UART_IER_THRI;
1359 serial_out(up, UART_IER, up->ier);
1361 if (up->bugs & UART_BUG_TXEN) {
1363 lsr = serial_in(up, UART_LSR);
1364 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1365 if ((up->port.type == PORT_RM9000) ?
1366 (lsr & UART_LSR_THRE) :
1367 (lsr & UART_LSR_TEMT))
1373 * Re-enable the transmitter if we disabled it.
1375 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1376 up->acr &= ~UART_ACR_TXDIS;
1377 serial_icr_write(up, UART_ACR, up->acr);
1381 static void serial8250_stop_rx(struct uart_port *port)
1383 struct uart_8250_port *up =
1384 container_of(port, struct uart_8250_port, port);
1386 up->ier &= ~UART_IER_RLSI;
1387 up->port.read_status_mask &= ~UART_LSR_DR;
1388 serial_out(up, UART_IER, up->ier);
1391 static void serial8250_enable_ms(struct uart_port *port)
1393 struct uart_8250_port *up =
1394 container_of(port, struct uart_8250_port, port);
1396 /* no MSR capabilities */
1397 if (up->bugs & UART_BUG_NOMSR)
1400 up->ier |= UART_IER_MSI;
1401 serial_out(up, UART_IER, up->ier);
1405 * Clear the Tegra rx fifo after a break
1407 * FIXME: This needs to become a port specific callback once we have a
1408 * framework for this
1410 static void clear_rx_fifo(struct uart_8250_port *up)
1412 unsigned int status, tmout = 10000;
1414 status = serial_in(up, UART_LSR);
1415 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1416 status = serial_in(up, UART_RX);
1426 receive_chars(struct uart_8250_port *up, unsigned int *status)
1428 struct tty_struct *tty = up->port.state->port.tty;
1429 unsigned char ch, lsr = *status;
1430 int max_count = 256;
1434 if (likely(lsr & UART_LSR_DR))
1435 ch = serial_inp(up, UART_RX);
1438 * Intel 82571 has a Serial Over Lan device that will
1439 * set UART_LSR_BI without setting UART_LSR_DR when
1440 * it receives a break. To avoid reading from the
1441 * receive buffer without UART_LSR_DR bit set, we
1442 * just force the read character to be 0
1447 up->port.icount.rx++;
1449 lsr |= up->lsr_saved_flags;
1450 up->lsr_saved_flags = 0;
1452 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1454 * For statistics only
1456 if (lsr & UART_LSR_BI) {
1457 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1458 up->port.icount.brk++;
1460 * If tegra port then clear the rx fifo to
1461 * accept another break/character.
1463 if (up->port.type == PORT_TEGRA)
1467 * We do the SysRQ and SAK checking
1468 * here because otherwise the break
1469 * may get masked by ignore_status_mask
1470 * or read_status_mask.
1472 if (uart_handle_break(&up->port))
1474 } else if (lsr & UART_LSR_PE)
1475 up->port.icount.parity++;
1476 else if (lsr & UART_LSR_FE)
1477 up->port.icount.frame++;
1478 if (lsr & UART_LSR_OE)
1479 up->port.icount.overrun++;
1482 * Mask off conditions which should be ignored.
1484 lsr &= up->port.read_status_mask;
1486 if (lsr & UART_LSR_BI) {
1487 DEBUG_INTR("handling break....");
1489 } else if (lsr & UART_LSR_PE)
1491 else if (lsr & UART_LSR_FE)
1494 if (uart_handle_sysrq_char(&up->port, ch))
1497 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1500 lsr = serial_inp(up, UART_LSR);
1501 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1502 spin_unlock(&up->port.lock);
1503 tty_flip_buffer_push(tty);
1504 spin_lock(&up->port.lock);
1508 static void transmit_chars(struct uart_8250_port *up)
1510 struct circ_buf *xmit = &up->port.state->xmit;
1513 if (up->port.x_char) {
1514 serial_outp(up, UART_TX, up->port.x_char);
1515 up->port.icount.tx++;
1516 up->port.x_char = 0;
1519 if (uart_tx_stopped(&up->port)) {
1520 serial8250_stop_tx(&up->port);
1523 if (uart_circ_empty(xmit)) {
1528 count = up->tx_loadsz;
1530 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1531 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1532 up->port.icount.tx++;
1533 if (uart_circ_empty(xmit))
1535 if (up->capabilities & UART_CAP_HFIFO) {
1536 if ((serial_in(up, UART_LSR) & BOTH_EMPTY) !=
1540 } while (--count > 0);
1542 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1543 uart_write_wakeup(&up->port);
1545 DEBUG_INTR("THRE...");
1547 if (uart_circ_empty(xmit))
1551 static unsigned int check_modem_status(struct uart_8250_port *up)
1553 unsigned int status = serial_in(up, UART_MSR);
1555 status |= up->msr_saved_flags;
1556 up->msr_saved_flags = 0;
1557 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1558 up->port.state != NULL) {
1559 if (status & UART_MSR_TERI)
1560 up->port.icount.rng++;
1561 if (status & UART_MSR_DDSR)
1562 up->port.icount.dsr++;
1563 if (status & UART_MSR_DDCD)
1564 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1565 if (status & UART_MSR_DCTS)
1566 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1568 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1575 * This handles the interrupt from one port.
1577 static void serial8250_handle_port(struct uart_8250_port *up)
1579 unsigned int status;
1580 unsigned long flags;
1582 spin_lock_irqsave(&up->port.lock, flags);
1584 status = serial_inp(up, UART_LSR);
1586 DEBUG_INTR("status = %x...", status);
1588 if (status & (UART_LSR_DR | UART_LSR_BI))
1589 receive_chars(up, &status);
1590 check_modem_status(up);
1591 if (status & UART_LSR_THRE)
1594 spin_unlock_irqrestore(&up->port.lock, flags);
1597 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1599 struct uart_8250_port *up =
1600 container_of(port, struct uart_8250_port, port);
1602 if (!(iir & UART_IIR_NO_INT)) {
1603 serial8250_handle_port(up);
1609 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1611 static int serial8250_default_handle_irq(struct uart_port *port)
1613 struct uart_8250_port *up =
1614 container_of(port, struct uart_8250_port, port);
1615 unsigned int iir = serial_in(up, UART_IIR);
1617 return serial8250_handle_irq(port, iir);
1621 * This is the serial driver's interrupt routine.
1623 * Arjan thinks the old way was overly complex, so it got simplified.
1624 * Alan disagrees, saying that need the complexity to handle the weird
1625 * nature of ISA shared interrupts. (This is a special exception.)
1627 * In order to handle ISA shared interrupts properly, we need to check
1628 * that all ports have been serviced, and therefore the ISA interrupt
1629 * line has been de-asserted.
1631 * This means we need to loop through all ports. checking that they
1632 * don't have an interrupt pending.
1634 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1636 struct irq_info *i = dev_id;
1637 struct list_head *l, *end = NULL;
1638 int pass_counter = 0, handled = 0;
1640 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1642 spin_lock(&i->lock);
1646 struct uart_8250_port *up;
1647 struct uart_port *port;
1649 up = list_entry(l, struct uart_8250_port, list);
1652 if (port->handle_irq(port)) {
1655 } else if (end == NULL)
1660 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1661 /* If we hit this, we're dead. */
1662 printk_ratelimited(KERN_ERR
1663 "serial8250: too much work for irq%d\n", irq);
1668 spin_unlock(&i->lock);
1670 DEBUG_INTR("end.\n");
1672 return IRQ_RETVAL(handled);
1676 * To support ISA shared interrupts, we need to have one interrupt
1677 * handler that ensures that the IRQ line has been deasserted
1678 * before returning. Failing to do this will result in the IRQ
1679 * line being stuck active, and, since ISA irqs are edge triggered,
1680 * no more IRQs will be seen.
1682 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1684 spin_lock_irq(&i->lock);
1686 if (!list_empty(i->head)) {
1687 if (i->head == &up->list)
1688 i->head = i->head->next;
1689 list_del(&up->list);
1691 BUG_ON(i->head != &up->list);
1694 spin_unlock_irq(&i->lock);
1695 /* List empty so throw away the hash node */
1696 if (i->head == NULL) {
1697 hlist_del(&i->node);
1702 static int serial_link_irq_chain(struct uart_8250_port *up)
1704 struct hlist_head *h;
1705 struct hlist_node *n;
1707 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1709 mutex_lock(&hash_mutex);
1711 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1713 hlist_for_each(n, h) {
1714 i = hlist_entry(n, struct irq_info, node);
1715 if (i->irq == up->port.irq)
1720 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1722 mutex_unlock(&hash_mutex);
1725 spin_lock_init(&i->lock);
1726 i->irq = up->port.irq;
1727 hlist_add_head(&i->node, h);
1729 mutex_unlock(&hash_mutex);
1731 spin_lock_irq(&i->lock);
1734 list_add(&up->list, i->head);
1735 spin_unlock_irq(&i->lock);
1739 INIT_LIST_HEAD(&up->list);
1740 i->head = &up->list;
1741 spin_unlock_irq(&i->lock);
1742 irq_flags |= up->port.irqflags;
1743 ret = request_irq(up->port.irq, serial8250_interrupt,
1744 irq_flags, "serial", i);
1746 serial_do_unlink(i, up);
1752 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1755 struct hlist_node *n;
1756 struct hlist_head *h;
1758 mutex_lock(&hash_mutex);
1760 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1762 hlist_for_each(n, h) {
1763 i = hlist_entry(n, struct irq_info, node);
1764 if (i->irq == up->port.irq)
1769 BUG_ON(i->head == NULL);
1771 if (list_empty(i->head))
1772 free_irq(up->port.irq, i);
1774 serial_do_unlink(i, up);
1775 mutex_unlock(&hash_mutex);
1779 * This function is used to handle ports that do not have an
1780 * interrupt. This doesn't work very well for 16450's, but gives
1781 * barely passable results for a 16550A. (Although at the expense
1782 * of much CPU overhead).
1784 static void serial8250_timeout(unsigned long data)
1786 struct uart_8250_port *up = (struct uart_8250_port *)data;
1789 iir = serial_in(up, UART_IIR);
1790 if (!(iir & UART_IIR_NO_INT))
1791 serial8250_handle_port(up);
1792 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1795 static void serial8250_backup_timeout(unsigned long data)
1797 struct uart_8250_port *up = (struct uart_8250_port *)data;
1798 unsigned int iir, ier = 0, lsr;
1799 unsigned long flags;
1801 spin_lock_irqsave(&up->port.lock, flags);
1804 * Must disable interrupts or else we risk racing with the interrupt
1807 if (is_real_interrupt(up->port.irq)) {
1808 ier = serial_in(up, UART_IER);
1809 serial_out(up, UART_IER, 0);
1812 iir = serial_in(up, UART_IIR);
1815 * This should be a safe test for anyone who doesn't trust the
1816 * IIR bits on their UART, but it's specifically designed for
1817 * the "Diva" UART used on the management processor on many HP
1818 * ia64 and parisc boxes.
1820 lsr = serial_in(up, UART_LSR);
1821 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1822 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1823 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1824 (lsr & UART_LSR_THRE)) {
1825 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1826 iir |= UART_IIR_THRI;
1829 if (!(iir & UART_IIR_NO_INT))
1832 if (is_real_interrupt(up->port.irq))
1833 serial_out(up, UART_IER, ier);
1835 spin_unlock_irqrestore(&up->port.lock, flags);
1837 /* Standard timer interval plus 0.2s to keep the port running */
1838 mod_timer(&up->timer,
1839 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1842 static unsigned int serial8250_tx_empty(struct uart_port *port)
1844 struct uart_8250_port *up =
1845 container_of(port, struct uart_8250_port, port);
1846 unsigned long flags;
1849 spin_lock_irqsave(&up->port.lock, flags);
1850 lsr = serial_in(up, UART_LSR);
1851 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1852 spin_unlock_irqrestore(&up->port.lock, flags);
1854 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1857 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1859 struct uart_8250_port *up =
1860 container_of(port, struct uart_8250_port, port);
1861 unsigned int status;
1864 status = check_modem_status(up);
1867 if (status & UART_MSR_DCD)
1869 if (status & UART_MSR_RI)
1871 if (status & UART_MSR_DSR)
1873 if (status & UART_MSR_CTS)
1878 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1880 struct uart_8250_port *up =
1881 container_of(port, struct uart_8250_port, port);
1882 unsigned char mcr = 0;
1884 if (mctrl & TIOCM_RTS)
1885 mcr |= UART_MCR_RTS;
1886 if (mctrl & TIOCM_DTR)
1887 mcr |= UART_MCR_DTR;
1888 if (mctrl & TIOCM_OUT1)
1889 mcr |= UART_MCR_OUT1;
1890 if (mctrl & TIOCM_OUT2)
1891 mcr |= UART_MCR_OUT2;
1892 if (mctrl & TIOCM_LOOP)
1893 mcr |= UART_MCR_LOOP;
1895 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1897 serial_out(up, UART_MCR, mcr);
1900 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1902 struct uart_8250_port *up =
1903 container_of(port, struct uart_8250_port, port);
1904 unsigned long flags;
1906 spin_lock_irqsave(&up->port.lock, flags);
1907 if (break_state == -1)
1908 up->lcr |= UART_LCR_SBC;
1910 up->lcr &= ~UART_LCR_SBC;
1911 serial_out(up, UART_LCR, up->lcr);
1912 spin_unlock_irqrestore(&up->port.lock, flags);
1916 * Wait for transmitter & holding register to empty
1918 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1920 unsigned int status, tmout = 10000;
1922 /* Wait up to 10ms for the character(s) to be sent. */
1924 status = serial_in(up, UART_LSR);
1926 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1928 if ((status & bits) == bits)
1935 /* Wait up to 1s for flow control if necessary */
1936 if (up->port.flags & UPF_CONS_FLOW) {
1938 for (tmout = 1000000; tmout; tmout--) {
1939 unsigned int msr = serial_in(up, UART_MSR);
1940 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1941 if (msr & UART_MSR_CTS)
1944 touch_nmi_watchdog();
1949 #ifdef CONFIG_CONSOLE_POLL
1951 * Console polling routines for writing and reading from the uart while
1952 * in an interrupt or debug context.
1955 static int serial8250_get_poll_char(struct uart_port *port)
1957 struct uart_8250_port *up =
1958 container_of(port, struct uart_8250_port, port);
1959 unsigned char lsr = serial_inp(up, UART_LSR);
1961 if (!(lsr & UART_LSR_DR))
1962 return NO_POLL_CHAR;
1964 return serial_inp(up, UART_RX);
1968 static void serial8250_put_poll_char(struct uart_port *port,
1972 struct uart_8250_port *up =
1973 container_of(port, struct uart_8250_port, port);
1976 * First save the IER then disable the interrupts
1978 ier = serial_in(up, UART_IER);
1979 if (up->capabilities & UART_CAP_UUE)
1980 serial_out(up, UART_IER, UART_IER_UUE);
1982 serial_out(up, UART_IER, 0);
1984 wait_for_xmitr(up, BOTH_EMPTY);
1986 * Send the character out.
1987 * If a LF, also do CR...
1989 serial_out(up, UART_TX, c);
1991 wait_for_xmitr(up, BOTH_EMPTY);
1992 serial_out(up, UART_TX, 13);
1996 * Finally, wait for transmitter to become empty
1997 * and restore the IER
1999 wait_for_xmitr(up, BOTH_EMPTY);
2000 serial_out(up, UART_IER, ier);
2003 #endif /* CONFIG_CONSOLE_POLL */
2005 static int serial8250_startup(struct uart_port *port)
2007 struct uart_8250_port *up =
2008 container_of(port, struct uart_8250_port, port);
2009 unsigned long flags;
2010 unsigned char lsr, iir;
2013 up->port.fifosize = uart_config[up->port.type].fifo_size;
2014 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
2015 up->capabilities = uart_config[up->port.type].flags;
2018 if (up->port.iotype != up->cur_iotype)
2019 set_io_from_upio(port);
2021 if (up->port.type == PORT_16C950) {
2022 /* Wake up and initialize UART */
2024 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2025 serial_outp(up, UART_EFR, UART_EFR_ECB);
2026 serial_outp(up, UART_IER, 0);
2027 serial_outp(up, UART_LCR, 0);
2028 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2029 serial_outp(up, UART_LCR, 0xBF);
2030 serial_outp(up, UART_EFR, UART_EFR_ECB);
2031 serial_outp(up, UART_LCR, 0);
2034 #ifdef CONFIG_SERIAL_8250_RSA
2036 * If this is an RSA port, see if we can kick it up to the
2037 * higher speed clock.
2043 * Clear the FIFO buffers and disable them.
2044 * (they will be reenabled in set_termios())
2046 serial8250_clear_fifos(up);
2049 * Clear the interrupt registers.
2051 (void) serial_inp(up, UART_LSR);
2052 (void) serial_inp(up, UART_RX);
2053 (void) serial_inp(up, UART_IIR);
2054 (void) serial_inp(up, UART_MSR);
2057 * At this point, there's no way the LSR could still be 0xff;
2058 * if it is, then bail out, because there's likely no UART
2061 if (!(up->port.flags & UPF_BUGGY_UART) &&
2062 (serial_inp(up, UART_LSR) == 0xff)) {
2063 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2064 serial_index(&up->port));
2069 * For a XR16C850, we need to set the trigger levels
2071 if (up->port.type == PORT_16850) {
2074 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2076 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2077 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2078 serial_outp(up, UART_TRG, UART_TRG_96);
2079 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2080 serial_outp(up, UART_TRG, UART_TRG_96);
2082 serial_outp(up, UART_LCR, 0);
2085 if (is_real_interrupt(up->port.irq)) {
2088 * Test for UARTs that do not reassert THRE when the
2089 * transmitter is idle and the interrupt has already
2090 * been cleared. Real 16550s should always reassert
2091 * this interrupt whenever the transmitter is idle and
2092 * the interrupt is enabled. Delays are necessary to
2093 * allow register changes to become visible.
2095 spin_lock_irqsave(&up->port.lock, flags);
2096 if (up->port.irqflags & IRQF_SHARED)
2097 disable_irq_nosync(up->port.irq);
2099 wait_for_xmitr(up, UART_LSR_THRE);
2100 serial_out_sync(up, UART_IER, UART_IER_THRI);
2101 udelay(1); /* allow THRE to set */
2102 iir1 = serial_in(up, UART_IIR);
2103 serial_out(up, UART_IER, 0);
2104 serial_out_sync(up, UART_IER, UART_IER_THRI);
2105 udelay(1); /* allow a working UART time to re-assert THRE */
2106 iir = serial_in(up, UART_IIR);
2107 serial_out(up, UART_IER, 0);
2109 if (up->port.irqflags & IRQF_SHARED)
2110 enable_irq(up->port.irq);
2111 spin_unlock_irqrestore(&up->port.lock, flags);
2114 * If the interrupt is not reasserted, setup a timer to
2115 * kick the UART on a regular basis.
2117 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2118 up->bugs |= UART_BUG_THRE;
2119 pr_debug("ttyS%d - using backup timer\n",
2120 serial_index(port));
2125 * The above check will only give an accurate result the first time
2126 * the port is opened so this value needs to be preserved.
2128 if (up->bugs & UART_BUG_THRE) {
2129 up->timer.function = serial8250_backup_timeout;
2130 up->timer.data = (unsigned long)up;
2131 mod_timer(&up->timer, jiffies +
2132 uart_poll_timeout(port) + HZ / 5);
2136 * If the "interrupt" for this port doesn't correspond with any
2137 * hardware interrupt, we use a timer-based system. The original
2138 * driver used to do this with IRQ0.
2140 if (!is_real_interrupt(up->port.irq)) {
2141 up->timer.data = (unsigned long)up;
2142 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2144 retval = serial_link_irq_chain(up);
2150 * Now, initialize the UART
2152 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2154 spin_lock_irqsave(&up->port.lock, flags);
2155 if (up->port.flags & UPF_FOURPORT) {
2156 if (!is_real_interrupt(up->port.irq))
2157 up->port.mctrl |= TIOCM_OUT1;
2160 * Most PC uarts need OUT2 raised to enable interrupts.
2162 if (is_real_interrupt(up->port.irq))
2163 up->port.mctrl |= TIOCM_OUT2;
2165 serial8250_set_mctrl(&up->port, up->port.mctrl);
2167 /* Serial over Lan (SoL) hack:
2168 Intel 8257x Gigabit ethernet chips have a
2169 16550 emulation, to be used for Serial Over Lan.
2170 Those chips take a longer time than a normal
2171 serial device to signalize that a transmission
2172 data was queued. Due to that, the above test generally
2173 fails. One solution would be to delay the reading of
2174 iir. However, this is not reliable, since the timeout
2175 is variable. So, let's just don't test if we receive
2176 TX irq. This way, we'll never enable UART_BUG_TXEN.
2178 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2179 goto dont_test_tx_en;
2182 * Do a quick test to see if we receive an
2183 * interrupt when we enable the TX irq.
2185 serial_outp(up, UART_IER, UART_IER_THRI);
2186 lsr = serial_in(up, UART_LSR);
2187 iir = serial_in(up, UART_IIR);
2188 serial_outp(up, UART_IER, 0);
2190 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2191 if (!(up->bugs & UART_BUG_TXEN)) {
2192 up->bugs |= UART_BUG_TXEN;
2193 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2194 serial_index(port));
2197 up->bugs &= ~UART_BUG_TXEN;
2201 spin_unlock_irqrestore(&up->port.lock, flags);
2204 * Clear the interrupt registers again for luck, and clear the
2205 * saved flags to avoid getting false values from polling
2206 * routines or the previous session.
2208 serial_inp(up, UART_LSR);
2209 serial_inp(up, UART_RX);
2210 serial_inp(up, UART_IIR);
2211 serial_inp(up, UART_MSR);
2212 up->lsr_saved_flags = 0;
2213 up->msr_saved_flags = 0;
2216 * Finally, enable interrupts. Note: Modem status interrupts
2217 * are set via set_termios(), which will be occurring imminently
2218 * anyway, so we don't enable them here.
2220 up->ier = UART_IER_RLSI | UART_IER_RDI;
2221 serial_outp(up, UART_IER, up->ier);
2223 if (up->port.flags & UPF_FOURPORT) {
2226 * Enable interrupts on the AST Fourport board
2228 icp = (up->port.iobase & 0xfe0) | 0x01f;
2236 static void serial8250_shutdown(struct uart_port *port)
2238 struct uart_8250_port *up =
2239 container_of(port, struct uart_8250_port, port);
2240 unsigned long flags;
2243 * Disable interrupts from this port
2246 serial_outp(up, UART_IER, 0);
2248 spin_lock_irqsave(&up->port.lock, flags);
2249 if (up->port.flags & UPF_FOURPORT) {
2250 /* reset interrupts on the AST Fourport board */
2251 inb((up->port.iobase & 0xfe0) | 0x1f);
2252 up->port.mctrl |= TIOCM_OUT1;
2254 up->port.mctrl &= ~TIOCM_OUT2;
2256 serial8250_set_mctrl(&up->port, up->port.mctrl);
2257 spin_unlock_irqrestore(&up->port.lock, flags);
2260 * Disable break condition and FIFOs
2262 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2263 serial8250_clear_fifos(up);
2265 #ifdef CONFIG_SERIAL_8250_RSA
2267 * Reset the RSA board back to 115kbps compat mode.
2273 * Read data port to reset things, and then unlink from
2276 (void) serial_in(up, UART_RX);
2278 del_timer_sync(&up->timer);
2279 up->timer.function = serial8250_timeout;
2280 if (is_real_interrupt(up->port.irq))
2281 serial_unlink_irq_chain(up);
2284 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2289 * Handle magic divisors for baud rates above baud_base on
2290 * SMSC SuperIO chips.
2292 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2293 baud == (port->uartclk/4))
2295 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2296 baud == (port->uartclk/8))
2299 quot = uart_get_divisor(port, baud);
2305 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2306 struct ktermios *old)
2308 struct uart_8250_port *up =
2309 container_of(port, struct uart_8250_port, port);
2310 unsigned char cval, fcr = 0;
2311 unsigned long flags;
2312 unsigned int baud, quot;
2314 switch (termios->c_cflag & CSIZE) {
2316 cval = UART_LCR_WLEN5;
2319 cval = UART_LCR_WLEN6;
2322 cval = UART_LCR_WLEN7;
2326 cval = UART_LCR_WLEN8;
2330 if (termios->c_cflag & CSTOPB)
2331 cval |= UART_LCR_STOP;
2332 if (termios->c_cflag & PARENB)
2333 cval |= UART_LCR_PARITY;
2334 if (!(termios->c_cflag & PARODD))
2335 cval |= UART_LCR_EPAR;
2337 if (termios->c_cflag & CMSPAR)
2338 cval |= UART_LCR_SPAR;
2342 * Ask the core to calculate the divisor for us.
2344 baud = uart_get_baud_rate(port, termios, old,
2345 port->uartclk / 16 / 0xffff,
2346 port->uartclk / 16);
2347 quot = serial8250_get_divisor(port, baud);
2350 * Oxford Semi 952 rev B workaround
2352 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2355 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2356 fcr = uart_config[up->port.type].fcr;
2358 fcr &= ~UART_FCR_TRIGGER_MASK;
2359 fcr |= UART_FCR_TRIGGER_1;
2364 * MCR-based auto flow control. When AFE is enabled, RTS will be
2365 * deasserted when the receive FIFO contains more characters than
2366 * the trigger, or the MCR RTS bit is cleared. In the case where
2367 * the remote UART is not using CTS auto flow control, we must
2368 * have sufficient FIFO entries for the latency of the remote
2369 * UART to respond. IOW, at least 32 bytes of FIFO.
2371 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2372 up->mcr &= ~UART_MCR_AFE;
2373 if (termios->c_cflag & CRTSCTS)
2374 up->mcr |= UART_MCR_AFE;
2378 * Ok, we're now changing the port state. Do it with
2379 * interrupts disabled.
2381 spin_lock_irqsave(&up->port.lock, flags);
2384 * Update the per-port timeout.
2386 uart_update_timeout(port, termios->c_cflag, baud);
2388 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2389 if (termios->c_iflag & INPCK)
2390 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2391 if (termios->c_iflag & (BRKINT | PARMRK))
2392 up->port.read_status_mask |= UART_LSR_BI;
2395 * Characteres to ignore
2397 up->port.ignore_status_mask = 0;
2398 if (termios->c_iflag & IGNPAR)
2399 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2400 if (termios->c_iflag & IGNBRK) {
2401 up->port.ignore_status_mask |= UART_LSR_BI;
2403 * If we're ignoring parity and break indicators,
2404 * ignore overruns too (for real raw support).
2406 if (termios->c_iflag & IGNPAR)
2407 up->port.ignore_status_mask |= UART_LSR_OE;
2411 * ignore all characters if CREAD is not set
2413 if ((termios->c_cflag & CREAD) == 0)
2414 up->port.ignore_status_mask |= UART_LSR_DR;
2417 * CTS flow control flag and modem status interrupts
2419 up->ier &= ~UART_IER_MSI;
2420 if (!(up->bugs & UART_BUG_NOMSR) &&
2421 UART_ENABLE_MS(&up->port, termios->c_cflag))
2422 up->ier |= UART_IER_MSI;
2423 if (up->capabilities & UART_CAP_UUE)
2424 up->ier |= UART_IER_UUE;
2425 if (up->capabilities & UART_CAP_RTOIE)
2426 up->ier |= UART_IER_RTOIE;
2428 serial_out(up, UART_IER, up->ier);
2430 if (up->capabilities & UART_CAP_EFR) {
2431 unsigned char efr = 0;
2433 * TI16C752/Startech hardware flow control. FIXME:
2434 * - TI16C752 requires control thresholds to be set.
2435 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2437 if (termios->c_cflag & CRTSCTS)
2438 efr |= UART_EFR_CTS;
2440 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2441 if (up->port.flags & UPF_EXAR_EFR)
2442 serial_outp(up, UART_XR_EFR, efr);
2444 serial_outp(up, UART_EFR, efr);
2447 #ifdef CONFIG_ARCH_OMAP
2448 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2449 if (cpu_is_omap1510() && is_omap_port(up)) {
2450 if (baud == 115200) {
2452 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2454 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2458 if (up->capabilities & UART_NATSEMI) {
2459 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2460 serial_outp(up, UART_LCR, 0xe0);
2462 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2465 serial_dl_write(up, quot);
2468 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2469 * is written without DLAB set, this mode will be disabled.
2471 if (up->port.type == PORT_16750)
2472 serial_outp(up, UART_FCR, fcr);
2474 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2475 up->lcr = cval; /* Save LCR */
2476 if (up->port.type != PORT_16750) {
2477 if (fcr & UART_FCR_ENABLE_FIFO) {
2478 /* emulated UARTs (Lucent Venus 167x) need two steps */
2479 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2481 serial_outp(up, UART_FCR, fcr); /* set fcr */
2483 serial8250_set_mctrl(&up->port, up->port.mctrl);
2484 spin_unlock_irqrestore(&up->port.lock, flags);
2485 /* Don't rewrite B0 */
2486 if (tty_termios_baud_rate(termios))
2487 tty_termios_encode_baud_rate(termios, baud, baud);
2489 EXPORT_SYMBOL(serial8250_do_set_termios);
2492 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2493 struct ktermios *old)
2495 if (port->set_termios)
2496 port->set_termios(port, termios, old);
2498 serial8250_do_set_termios(port, termios, old);
2502 serial8250_set_ldisc(struct uart_port *port, int new)
2505 port->flags |= UPF_HARDPPS_CD;
2506 serial8250_enable_ms(port);
2508 port->flags &= ~UPF_HARDPPS_CD;
2512 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2513 unsigned int oldstate)
2515 struct uart_8250_port *p =
2516 container_of(port, struct uart_8250_port, port);
2518 serial8250_set_sleep(p, state != 0);
2520 EXPORT_SYMBOL(serial8250_do_pm);
2523 serial8250_pm(struct uart_port *port, unsigned int state,
2524 unsigned int oldstate)
2527 port->pm(port, state, oldstate);
2529 serial8250_do_pm(port, state, oldstate);
2532 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2534 if (pt->port.iotype == UPIO_AU)
2536 #ifdef CONFIG_ARCH_OMAP
2537 if (is_omap_port(pt))
2538 return 0x16 << pt->port.regshift;
2540 return 8 << pt->port.regshift;
2544 * Resource handling.
2546 static int serial8250_request_std_resource(struct uart_8250_port *up)
2548 unsigned int size = serial8250_port_size(up);
2551 switch (up->port.iotype) {
2556 if (!up->port.mapbase)
2559 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2564 if (up->port.flags & UPF_IOREMAP) {
2565 up->port.membase = ioremap_nocache(up->port.mapbase,
2567 if (!up->port.membase) {
2568 release_mem_region(up->port.mapbase, size);
2576 if (!request_region(up->port.iobase, size, "serial"))
2583 static void serial8250_release_std_resource(struct uart_8250_port *up)
2585 unsigned int size = serial8250_port_size(up);
2587 switch (up->port.iotype) {
2592 if (!up->port.mapbase)
2595 if (up->port.flags & UPF_IOREMAP) {
2596 iounmap(up->port.membase);
2597 up->port.membase = NULL;
2600 release_mem_region(up->port.mapbase, size);
2605 release_region(up->port.iobase, size);
2610 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2612 unsigned long start = UART_RSA_BASE << up->port.regshift;
2613 unsigned int size = 8 << up->port.regshift;
2616 switch (up->port.iotype) {
2619 start += up->port.iobase;
2620 if (request_region(start, size, "serial-rsa"))
2630 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2632 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2633 unsigned int size = 8 << up->port.regshift;
2635 switch (up->port.iotype) {
2638 release_region(up->port.iobase + offset, size);
2643 static void serial8250_release_port(struct uart_port *port)
2645 struct uart_8250_port *up =
2646 container_of(port, struct uart_8250_port, port);
2648 serial8250_release_std_resource(up);
2649 if (up->port.type == PORT_RSA)
2650 serial8250_release_rsa_resource(up);
2653 static int serial8250_request_port(struct uart_port *port)
2655 struct uart_8250_port *up =
2656 container_of(port, struct uart_8250_port, port);
2659 ret = serial8250_request_std_resource(up);
2660 if (ret == 0 && up->port.type == PORT_RSA) {
2661 ret = serial8250_request_rsa_resource(up);
2663 serial8250_release_std_resource(up);
2669 static void serial8250_config_port(struct uart_port *port, int flags)
2671 struct uart_8250_port *up =
2672 container_of(port, struct uart_8250_port, port);
2673 int probeflags = PROBE_ANY;
2677 * Find the region that we can probe for. This in turn
2678 * tells us whether we can probe for the type of port.
2680 ret = serial8250_request_std_resource(up);
2684 ret = serial8250_request_rsa_resource(up);
2686 probeflags &= ~PROBE_RSA;
2688 if (up->port.iotype != up->cur_iotype)
2689 set_io_from_upio(port);
2691 if (flags & UART_CONFIG_TYPE)
2692 autoconfig(up, probeflags);
2694 /* if access method is AU, it is a 16550 with a quirk */
2695 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2696 up->bugs |= UART_BUG_NOMSR;
2698 /* HW bugs may trigger IRQ while IIR == NO_INT */
2699 if (up->port.type == PORT_TEGRA)
2700 up->bugs |= UART_BUG_NOMSR;
2702 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2705 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2706 serial8250_release_rsa_resource(up);
2707 if (up->port.type == PORT_UNKNOWN)
2708 serial8250_release_std_resource(up);
2712 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2714 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2715 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2716 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2717 ser->type == PORT_STARTECH || uart_config[ser->type].name == NULL)
2723 serial8250_type(struct uart_port *port)
2725 int type = port->type;
2727 if (type >= ARRAY_SIZE(uart_config) || uart_config[type].name == NULL)
2729 return uart_config[type].name;
2732 static struct uart_ops serial8250_pops = {
2733 .tx_empty = serial8250_tx_empty,
2734 .set_mctrl = serial8250_set_mctrl,
2735 .get_mctrl = serial8250_get_mctrl,
2736 .stop_tx = serial8250_stop_tx,
2737 .start_tx = serial8250_start_tx,
2738 .stop_rx = serial8250_stop_rx,
2739 .enable_ms = serial8250_enable_ms,
2740 .break_ctl = serial8250_break_ctl,
2741 .startup = serial8250_startup,
2742 .shutdown = serial8250_shutdown,
2743 .set_termios = serial8250_set_termios,
2744 .set_ldisc = serial8250_set_ldisc,
2745 .pm = serial8250_pm,
2746 .type = serial8250_type,
2747 .release_port = serial8250_release_port,
2748 .request_port = serial8250_request_port,
2749 .config_port = serial8250_config_port,
2750 .verify_port = serial8250_verify_port,
2751 #ifdef CONFIG_CONSOLE_POLL
2752 .poll_get_char = serial8250_get_poll_char,
2753 .poll_put_char = serial8250_put_poll_char,
2757 static struct uart_8250_port serial8250_ports[UART_NR];
2759 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2760 unsigned short *capabilities);
2762 void serial8250_set_isa_configurator(
2763 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2765 serial8250_isa_config = v;
2767 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2769 static void __init serial8250_isa_init_ports(void)
2771 struct uart_8250_port *up;
2772 static int first = 1;
2779 for (i = 0; i < nr_uarts; i++) {
2780 struct uart_8250_port *up = &serial8250_ports[i];
2783 spin_lock_init(&up->port.lock);
2785 init_timer(&up->timer);
2786 up->timer.function = serial8250_timeout;
2789 * ALPHA_KLUDGE_MCR needs to be killed.
2791 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2792 up->mcr_force = ALPHA_KLUDGE_MCR;
2794 up->port.ops = &serial8250_pops;
2798 irqflag = IRQF_SHARED;
2800 for (i = 0, up = serial8250_ports;
2801 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2803 up->port.iobase = old_serial_port[i].port;
2804 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2805 up->port.irqflags = old_serial_port[i].irqflags;
2806 up->port.uartclk = old_serial_port[i].baud_base * 16;
2807 up->port.flags = old_serial_port[i].flags;
2808 up->port.hub6 = old_serial_port[i].hub6;
2809 up->port.membase = old_serial_port[i].iomem_base;
2810 up->port.iotype = old_serial_port[i].io_type;
2811 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2812 set_io_from_upio(&up->port);
2813 up->port.irqflags |= irqflag;
2814 if (serial8250_isa_config != NULL)
2815 serial8250_isa_config(i, &up->port, &up->capabilities);
2821 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2823 up->port.type = type;
2824 up->port.fifosize = uart_config[type].fifo_size;
2825 up->capabilities = uart_config[type].flags;
2826 up->tx_loadsz = uart_config[type].tx_loadsz;
2830 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2834 for (i = 0; i < nr_uarts; i++) {
2835 struct uart_8250_port *up = &serial8250_ports[i];
2836 up->cur_iotype = 0xFF;
2839 serial8250_isa_init_ports();
2841 for (i = 0; i < nr_uarts; i++) {
2842 struct uart_8250_port *up = &serial8250_ports[i];
2846 if (up->port.flags & UPF_FIXED_TYPE)
2847 serial8250_init_fixed_type_port(up, up->port.type);
2849 uart_add_one_port(drv, &up->port);
2853 #ifdef CONFIG_SERIAL_8250_CONSOLE
2855 static void serial8250_console_putchar(struct uart_port *port, int ch)
2857 struct uart_8250_port *up =
2858 container_of(port, struct uart_8250_port, port);
2860 wait_for_xmitr(up, UART_LSR_THRE);
2861 serial_out(up, UART_TX, ch);
2865 * Print a string to the serial port trying not to disturb
2866 * any possible real use of the port...
2868 * The console_lock must be held when we get here.
2871 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2873 struct uart_8250_port *up = &serial8250_ports[co->index];
2874 unsigned long flags;
2878 touch_nmi_watchdog();
2880 local_irq_save(flags);
2881 if (up->port.sysrq) {
2882 /* serial8250_handle_port() already took the lock */
2884 } else if (oops_in_progress) {
2885 locked = spin_trylock(&up->port.lock);
2887 spin_lock(&up->port.lock);
2890 * First save the IER then disable the interrupts
2892 ier = serial_in(up, UART_IER);
2894 if (up->capabilities & UART_CAP_UUE)
2895 serial_out(up, UART_IER, UART_IER_UUE);
2897 serial_out(up, UART_IER, 0);
2899 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2902 * Finally, wait for transmitter to become empty
2903 * and restore the IER
2905 wait_for_xmitr(up, BOTH_EMPTY);
2906 serial_out(up, UART_IER, ier);
2909 * The receive handling will happen properly because the
2910 * receive ready bit will still be set; it is not cleared
2911 * on read. However, modem control will not, we must
2912 * call it if we have saved something in the saved flags
2913 * while processing with interrupts off.
2915 if (up->msr_saved_flags)
2916 check_modem_status(up);
2919 spin_unlock(&up->port.lock);
2920 local_irq_restore(flags);
2923 static int __init serial8250_console_setup(struct console *co, char *options)
2925 struct uart_port *port;
2932 * Check whether an invalid uart number has been specified, and
2933 * if so, search for the first available port that does have
2936 if (co->index >= nr_uarts)
2938 port = &serial8250_ports[co->index].port;
2939 if (!port->iobase && !port->membase)
2943 uart_parse_options(options, &baud, &parity, &bits, &flow);
2945 return uart_set_options(port, co, baud, parity, bits, flow);
2948 static int serial8250_console_early_setup(void)
2950 return serial8250_find_port_for_earlycon();
2953 static struct console serial8250_console = {
2955 .write = serial8250_console_write,
2956 .device = uart_console_device,
2957 .setup = serial8250_console_setup,
2958 .early_setup = serial8250_console_early_setup,
2959 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2961 .data = &serial8250_reg,
2964 static int __init serial8250_console_init(void)
2966 if (nr_uarts > UART_NR)
2969 serial8250_isa_init_ports();
2970 register_console(&serial8250_console);
2973 console_initcall(serial8250_console_init);
2975 int serial8250_find_port(struct uart_port *p)
2978 struct uart_port *port;
2980 for (line = 0; line < nr_uarts; line++) {
2981 port = &serial8250_ports[line].port;
2982 if (uart_match_port(p, port))
2988 #define SERIAL8250_CONSOLE &serial8250_console
2990 #define SERIAL8250_CONSOLE NULL
2993 static struct uart_driver serial8250_reg = {
2994 .owner = THIS_MODULE,
2995 .driver_name = "serial",
2999 .cons = SERIAL8250_CONSOLE,
3003 * early_serial_setup - early registration for 8250 ports
3005 * Setup an 8250 port structure prior to console initialisation. Use
3006 * after console initialisation will cause undefined behaviour.
3008 int __init early_serial_setup(struct uart_port *port)
3010 struct uart_port *p;
3012 if (port->line >= ARRAY_SIZE(serial8250_ports))
3015 serial8250_isa_init_ports();
3016 p = &serial8250_ports[port->line].port;
3017 p->iobase = port->iobase;
3018 p->membase = port->membase;
3020 p->irqflags = port->irqflags;
3021 p->uartclk = port->uartclk;
3022 p->fifosize = port->fifosize;
3023 p->regshift = port->regshift;
3024 p->iotype = port->iotype;
3025 p->flags = port->flags;
3026 p->mapbase = port->mapbase;
3027 p->private_data = port->private_data;
3028 p->type = port->type;
3029 p->line = port->line;
3031 set_io_from_upio(p);
3032 if (port->serial_in)
3033 p->serial_in = port->serial_in;
3034 if (port->serial_out)
3035 p->serial_out = port->serial_out;
3036 if (port->handle_irq)
3037 p->handle_irq = port->handle_irq;
3039 p->handle_irq = serial8250_default_handle_irq;
3045 * serial8250_suspend_port - suspend one serial port
3046 * @line: serial line number
3048 * Suspend one serial port.
3050 void serial8250_suspend_port(int line)
3052 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3056 * serial8250_resume_port - resume one serial port
3057 * @line: serial line number
3059 * Resume one serial port.
3061 void serial8250_resume_port(int line)
3063 struct uart_8250_port *up = &serial8250_ports[line];
3065 if (up->capabilities & UART_NATSEMI) {
3066 /* Ensure it's still in high speed mode */
3067 serial_outp(up, UART_LCR, 0xE0);
3069 ns16550a_goto_highspeed(up);
3071 serial_outp(up, UART_LCR, 0);
3072 up->port.uartclk = 921600*16;
3074 uart_resume_port(&serial8250_reg, &up->port);
3078 * Register a set of serial devices attached to a platform device. The
3079 * list is terminated with a zero flags entry, which means we expect
3080 * all entries to have at least UPF_BOOT_AUTOCONF set.
3082 static int __devinit serial8250_probe(struct platform_device *dev)
3084 struct plat_serial8250_port *p = dev->dev.platform_data;
3085 struct uart_port port;
3086 int ret, i, irqflag = 0;
3088 memset(&port, 0, sizeof(struct uart_port));
3091 irqflag = IRQF_SHARED;
3093 for (i = 0; p && p->flags != 0; p++, i++) {
3094 port.iobase = p->iobase;
3095 port.membase = p->membase;
3097 port.irqflags = p->irqflags;
3098 port.uartclk = p->uartclk;
3099 port.regshift = p->regshift;
3100 port.iotype = p->iotype;
3101 port.flags = p->flags;
3102 port.mapbase = p->mapbase;
3103 port.hub6 = p->hub6;
3104 port.private_data = p->private_data;
3105 port.type = p->type;
3106 port.serial_in = p->serial_in;
3107 port.serial_out = p->serial_out;
3108 port.handle_irq = p->handle_irq;
3109 port.set_termios = p->set_termios;
3111 port.dev = &dev->dev;
3112 port.irqflags |= irqflag;
3113 ret = serial8250_register_port(&port);
3115 dev_err(&dev->dev, "unable to register port at index %d "
3116 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3117 p->iobase, (unsigned long long)p->mapbase,
3125 * Remove serial ports registered against a platform device.
3127 static int __devexit serial8250_remove(struct platform_device *dev)
3131 for (i = 0; i < nr_uarts; i++) {
3132 struct uart_8250_port *up = &serial8250_ports[i];
3134 if (up->port.dev == &dev->dev)
3135 serial8250_unregister_port(i);
3140 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3144 for (i = 0; i < UART_NR; i++) {
3145 struct uart_8250_port *up = &serial8250_ports[i];
3147 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3148 uart_suspend_port(&serial8250_reg, &up->port);
3154 static int serial8250_resume(struct platform_device *dev)
3158 for (i = 0; i < UART_NR; i++) {
3159 struct uart_8250_port *up = &serial8250_ports[i];
3161 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3162 serial8250_resume_port(i);
3168 static struct platform_driver serial8250_isa_driver = {
3169 .probe = serial8250_probe,
3170 .remove = __devexit_p(serial8250_remove),
3171 .suspend = serial8250_suspend,
3172 .resume = serial8250_resume,
3174 .name = "serial8250",
3175 .owner = THIS_MODULE,
3180 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3181 * in the table in include/asm/serial.h
3183 static struct platform_device *serial8250_isa_devs;
3186 * serial8250_register_port and serial8250_unregister_port allows for
3187 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3188 * modems and PCI multiport cards.
3190 static DEFINE_MUTEX(serial_mutex);
3192 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3197 * First, find a port entry which matches.
3199 for (i = 0; i < nr_uarts; i++)
3200 if (uart_match_port(&serial8250_ports[i].port, port))
3201 return &serial8250_ports[i];
3204 * We didn't find a matching entry, so look for the first
3205 * free entry. We look for one which hasn't been previously
3206 * used (indicated by zero iobase).
3208 for (i = 0; i < nr_uarts; i++)
3209 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3210 serial8250_ports[i].port.iobase == 0)
3211 return &serial8250_ports[i];
3214 * That also failed. Last resort is to find any entry which
3215 * doesn't have a real port associated with it.
3217 for (i = 0; i < nr_uarts; i++)
3218 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3219 return &serial8250_ports[i];
3225 * serial8250_register_port - register a serial port
3226 * @port: serial port template
3228 * Configure the serial port specified by the request. If the
3229 * port exists and is in use, it is hung up and unregistered
3232 * The port is then probed and if necessary the IRQ is autodetected
3233 * If this fails an error is returned.
3235 * On success the port is ready to use and the line number is returned.
3237 int serial8250_register_port(struct uart_port *port)
3239 struct uart_8250_port *uart;
3242 if (port->uartclk == 0)
3245 mutex_lock(&serial_mutex);
3247 uart = serial8250_find_match_or_unused(port);
3249 uart_remove_one_port(&serial8250_reg, &uart->port);
3251 uart->port.iobase = port->iobase;
3252 uart->port.membase = port->membase;
3253 uart->port.irq = port->irq;
3254 uart->port.irqflags = port->irqflags;
3255 uart->port.uartclk = port->uartclk;
3256 uart->port.fifosize = port->fifosize;
3257 uart->port.regshift = port->regshift;
3258 uart->port.iotype = port->iotype;
3259 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3260 uart->port.mapbase = port->mapbase;
3261 uart->port.private_data = port->private_data;
3263 uart->port.dev = port->dev;
3265 if (port->flags & UPF_FIXED_TYPE)
3266 serial8250_init_fixed_type_port(uart, port->type);
3268 set_io_from_upio(&uart->port);
3269 /* Possibly override default I/O functions. */
3270 if (port->serial_in)
3271 uart->port.serial_in = port->serial_in;
3272 if (port->serial_out)
3273 uart->port.serial_out = port->serial_out;
3274 if (port->handle_irq)
3275 uart->port.handle_irq = port->handle_irq;
3276 /* Possibly override set_termios call */
3277 if (port->set_termios)
3278 uart->port.set_termios = port->set_termios;
3280 uart->port.pm = port->pm;
3282 if (serial8250_isa_config != NULL)
3283 serial8250_isa_config(0, &uart->port,
3284 &uart->capabilities);
3286 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3288 ret = uart->port.line;
3290 mutex_unlock(&serial_mutex);
3294 EXPORT_SYMBOL(serial8250_register_port);
3297 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3298 * @line: serial line number
3300 * Remove one serial port. This may not be called from interrupt
3301 * context. We hand the port back to the our control.
3303 void serial8250_unregister_port(int line)
3305 struct uart_8250_port *uart = &serial8250_ports[line];
3307 mutex_lock(&serial_mutex);
3308 uart_remove_one_port(&serial8250_reg, &uart->port);
3309 if (serial8250_isa_devs) {
3310 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3311 uart->port.type = PORT_UNKNOWN;
3312 uart->port.dev = &serial8250_isa_devs->dev;
3313 uart->capabilities = uart_config[uart->port.type].flags;
3314 uart_add_one_port(&serial8250_reg, &uart->port);
3316 uart->port.dev = NULL;
3318 mutex_unlock(&serial_mutex);
3320 EXPORT_SYMBOL(serial8250_unregister_port);
3322 static int __init serial8250_init(void)
3326 if (nr_uarts > UART_NR)
3329 printk(KERN_INFO "Serial: 8250/16550 driver, "
3330 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3331 share_irqs ? "en" : "dis");
3334 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3336 serial8250_reg.nr = UART_NR;
3337 ret = uart_register_driver(&serial8250_reg);
3342 serial8250_isa_devs = platform_device_alloc("serial8250",
3343 PLAT8250_DEV_LEGACY);
3344 if (!serial8250_isa_devs) {
3346 goto unreg_uart_drv;
3349 ret = platform_device_add(serial8250_isa_devs);
3353 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3355 ret = platform_driver_register(&serial8250_isa_driver);
3359 platform_device_del(serial8250_isa_devs);
3361 platform_device_put(serial8250_isa_devs);
3364 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3366 uart_unregister_driver(&serial8250_reg);
3372 static void __exit serial8250_exit(void)
3374 struct platform_device *isa_dev = serial8250_isa_devs;
3377 * This tells serial8250_unregister_port() not to re-register
3378 * the ports (thereby making serial8250_isa_driver permanently
3381 serial8250_isa_devs = NULL;
3383 platform_driver_unregister(&serial8250_isa_driver);
3384 platform_device_unregister(isa_dev);
3387 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3389 uart_unregister_driver(&serial8250_reg);
3393 module_init(serial8250_init);
3394 module_exit(serial8250_exit);
3396 EXPORT_SYMBOL(serial8250_suspend_port);
3397 EXPORT_SYMBOL(serial8250_resume_port);
3399 MODULE_LICENSE("GPL");
3400 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3402 module_param(share_irqs, uint, 0644);
3403 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3406 module_param(nr_uarts, uint, 0644);
3407 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3409 module_param(skip_txen_test, uint, 0644);
3410 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3412 #ifdef CONFIG_SERIAL_8250_RSA
3413 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3414 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3416 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);