2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60 static struct uart_driver serial8250_reg;
62 static int serial_index(struct uart_port *port)
64 return (serial8250_reg.minor - 64) + port->line;
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
79 #define DEBUG_INTR(fmt...) printk(fmt)
81 #define DEBUG_INTR(fmt...) do { } while (0)
84 #define PASS_LIMIT 512
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
94 #define is_real_interrupt(irq) ((irq) != 0)
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
107 #define CONFIG_HUB6 1
109 #include <asm/serial.h>
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
125 #ifdef CONFIG_SERIAL_8250_RSA
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
159 struct hlist_node node;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
170 * Here we define the default xmit fifo size used for each type of UART.
172 static const struct serial8250_config uart_config[] = {
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
233 .name = "16C950/954",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
319 [PORT_BRCM_TRUMANAGE] = {
323 .flags = UART_CAP_HFIFO,
327 #if defined(CONFIG_MIPS_ALCHEMY)
329 /* Au1x00 UART hardware has a weird register layout */
330 static const u8 au_io_in_map[] = {
340 static const u8 au_io_out_map[] = {
348 /* sane hardware needs no mapping */
349 static inline int map_8250_in_reg(struct uart_port *p, int offset)
351 if (p->iotype != UPIO_AU)
353 return au_io_in_map[offset];
356 static inline int map_8250_out_reg(struct uart_port *p, int offset)
358 if (p->iotype != UPIO_AU)
360 return au_io_out_map[offset];
363 #elif defined(CONFIG_SERIAL_8250_RM9K)
387 static inline int map_8250_in_reg(struct uart_port *p, int offset)
389 if (p->iotype != UPIO_RM9000)
391 return regmap_in[offset];
394 static inline int map_8250_out_reg(struct uart_port *p, int offset)
396 if (p->iotype != UPIO_RM9000)
398 return regmap_out[offset];
403 /* sane hardware needs no mapping */
404 #define map_8250_in_reg(up, offset) (offset)
405 #define map_8250_out_reg(up, offset) (offset)
409 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
411 offset = map_8250_in_reg(p, offset) << p->regshift;
412 outb(p->hub6 - 1 + offset, p->iobase);
413 return inb(p->iobase + 1);
416 static void hub6_serial_out(struct uart_port *p, int offset, int value)
418 offset = map_8250_out_reg(p, offset) << p->regshift;
419 outb(p->hub6 - 1 + offset, p->iobase);
420 outb(value, p->iobase + 1);
423 static unsigned int mem_serial_in(struct uart_port *p, int offset)
425 offset = map_8250_in_reg(p, offset) << p->regshift;
426 return readb(p->membase + offset);
429 static void mem_serial_out(struct uart_port *p, int offset, int value)
431 offset = map_8250_out_reg(p, offset) << p->regshift;
432 writeb(value, p->membase + offset);
435 static void mem32_serial_out(struct uart_port *p, int offset, int value)
437 offset = map_8250_out_reg(p, offset) << p->regshift;
438 writel(value, p->membase + offset);
441 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
443 offset = map_8250_in_reg(p, offset) << p->regshift;
444 return readl(p->membase + offset);
447 static unsigned int au_serial_in(struct uart_port *p, int offset)
449 offset = map_8250_in_reg(p, offset) << p->regshift;
450 return __raw_readl(p->membase + offset);
453 static void au_serial_out(struct uart_port *p, int offset, int value)
455 offset = map_8250_out_reg(p, offset) << p->regshift;
456 __raw_writel(value, p->membase + offset);
459 static unsigned int io_serial_in(struct uart_port *p, int offset)
461 offset = map_8250_in_reg(p, offset) << p->regshift;
462 return inb(p->iobase + offset);
465 static void io_serial_out(struct uart_port *p, int offset, int value)
467 offset = map_8250_out_reg(p, offset) << p->regshift;
468 outb(value, p->iobase + offset);
471 static int serial8250_default_handle_irq(struct uart_port *port);
473 static void set_io_from_upio(struct uart_port *p)
475 struct uart_8250_port *up =
476 container_of(p, struct uart_8250_port, port);
479 p->serial_in = hub6_serial_in;
480 p->serial_out = hub6_serial_out;
484 p->serial_in = mem_serial_in;
485 p->serial_out = mem_serial_out;
490 p->serial_in = mem32_serial_in;
491 p->serial_out = mem32_serial_out;
495 p->serial_in = au_serial_in;
496 p->serial_out = au_serial_out;
500 p->serial_in = io_serial_in;
501 p->serial_out = io_serial_out;
504 /* Remember loaded iotype */
505 up->cur_iotype = p->iotype;
506 p->handle_irq = serial8250_default_handle_irq;
510 serial_out_sync(struct uart_8250_port *up, int offset, int value)
512 struct uart_port *p = &up->port;
517 p->serial_out(p, offset, value);
518 p->serial_in(p, UART_LCR); /* safe, no side-effects */
521 p->serial_out(p, offset, value);
525 #define serial_in(up, offset) \
526 (up->port.serial_in(&(up)->port, (offset)))
527 #define serial_out(up, offset, value) \
528 (up->port.serial_out(&(up)->port, (offset), (value)))
530 * We used to support using pause I/O for certain machines. We
531 * haven't supported this for a while, but just in case it's badly
532 * needed for certain old 386 machines, I've left these #define's
535 #define serial_inp(up, offset) serial_in(up, offset)
536 #define serial_outp(up, offset, value) serial_out(up, offset, value)
538 /* Uart divisor latch read */
539 static inline int _serial_dl_read(struct uart_8250_port *up)
541 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
544 /* Uart divisor latch write */
545 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
547 serial_outp(up, UART_DLL, value & 0xff);
548 serial_outp(up, UART_DLM, value >> 8 & 0xff);
551 #if defined(CONFIG_MIPS_ALCHEMY)
552 /* Au1x00 haven't got a standard divisor latch */
553 static int serial_dl_read(struct uart_8250_port *up)
555 if (up->port.iotype == UPIO_AU)
556 return __raw_readl(up->port.membase + 0x28);
558 return _serial_dl_read(up);
561 static void serial_dl_write(struct uart_8250_port *up, int value)
563 if (up->port.iotype == UPIO_AU)
564 __raw_writel(value, up->port.membase + 0x28);
566 _serial_dl_write(up, value);
568 #elif defined(CONFIG_SERIAL_8250_RM9K)
569 static int serial_dl_read(struct uart_8250_port *up)
571 return (up->port.iotype == UPIO_RM9000) ?
572 (((__raw_readl(up->port.membase + 0x10) << 8) |
573 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
577 static void serial_dl_write(struct uart_8250_port *up, int value)
579 if (up->port.iotype == UPIO_RM9000) {
580 __raw_writel(value, up->port.membase + 0x08);
581 __raw_writel(value >> 8, up->port.membase + 0x10);
583 _serial_dl_write(up, value);
587 #define serial_dl_read(up) _serial_dl_read(up)
588 #define serial_dl_write(up, value) _serial_dl_write(up, value)
594 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
596 serial_out(up, UART_SCR, offset);
597 serial_out(up, UART_ICR, value);
600 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
604 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
605 serial_out(up, UART_SCR, offset);
606 value = serial_in(up, UART_ICR);
607 serial_icr_write(up, UART_ACR, up->acr);
615 static void serial8250_clear_fifos(struct uart_8250_port *p)
617 if (p->capabilities & UART_CAP_FIFO) {
618 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
619 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
620 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
621 serial_outp(p, UART_FCR, 0);
626 * IER sleep support. UARTs which have EFRs need the "extended
627 * capability" bit enabled. Note that on XR16C850s, we need to
628 * reset LCR to write to IER.
630 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
632 if (p->capabilities & UART_CAP_SLEEP) {
633 if (p->capabilities & UART_CAP_EFR) {
634 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
635 serial_outp(p, UART_EFR, UART_EFR_ECB);
636 serial_outp(p, UART_LCR, 0);
638 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
639 if (p->capabilities & UART_CAP_EFR) {
640 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
641 serial_outp(p, UART_EFR, 0);
642 serial_outp(p, UART_LCR, 0);
647 #ifdef CONFIG_SERIAL_8250_RSA
649 * Attempts to turn on the RSA FIFO. Returns zero on failure.
650 * We set the port uart clock rate if we succeed.
652 static int __enable_rsa(struct uart_8250_port *up)
657 mode = serial_inp(up, UART_RSA_MSR);
658 result = mode & UART_RSA_MSR_FIFO;
661 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
662 mode = serial_inp(up, UART_RSA_MSR);
663 result = mode & UART_RSA_MSR_FIFO;
667 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
672 static void enable_rsa(struct uart_8250_port *up)
674 if (up->port.type == PORT_RSA) {
675 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
676 spin_lock_irq(&up->port.lock);
678 spin_unlock_irq(&up->port.lock);
680 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
681 serial_outp(up, UART_RSA_FRR, 0);
686 * Attempts to turn off the RSA FIFO. Returns zero on failure.
687 * It is unknown why interrupts were disabled in here. However,
688 * the caller is expected to preserve this behaviour by grabbing
689 * the spinlock before calling this function.
691 static void disable_rsa(struct uart_8250_port *up)
696 if (up->port.type == PORT_RSA &&
697 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
698 spin_lock_irq(&up->port.lock);
700 mode = serial_inp(up, UART_RSA_MSR);
701 result = !(mode & UART_RSA_MSR_FIFO);
704 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
705 mode = serial_inp(up, UART_RSA_MSR);
706 result = !(mode & UART_RSA_MSR_FIFO);
710 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
711 spin_unlock_irq(&up->port.lock);
714 #endif /* CONFIG_SERIAL_8250_RSA */
717 * This is a quickie test to see how big the FIFO is.
718 * It doesn't work at all the time, more's the pity.
720 static int size_fifo(struct uart_8250_port *up)
722 unsigned char old_fcr, old_mcr, old_lcr;
723 unsigned short old_dl;
726 old_lcr = serial_inp(up, UART_LCR);
727 serial_outp(up, UART_LCR, 0);
728 old_fcr = serial_inp(up, UART_FCR);
729 old_mcr = serial_inp(up, UART_MCR);
730 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
731 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
732 serial_outp(up, UART_MCR, UART_MCR_LOOP);
733 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
734 old_dl = serial_dl_read(up);
735 serial_dl_write(up, 0x0001);
736 serial_outp(up, UART_LCR, 0x03);
737 for (count = 0; count < 256; count++)
738 serial_outp(up, UART_TX, count);
739 mdelay(20);/* FIXME - schedule_timeout */
740 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
741 (count < 256); count++)
742 serial_inp(up, UART_RX);
743 serial_outp(up, UART_FCR, old_fcr);
744 serial_outp(up, UART_MCR, old_mcr);
745 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
746 serial_dl_write(up, old_dl);
747 serial_outp(up, UART_LCR, old_lcr);
753 * Read UART ID using the divisor method - set DLL and DLM to zero
754 * and the revision will be in DLL and device type in DLM. We
755 * preserve the device state across this.
757 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
759 unsigned char old_dll, old_dlm, old_lcr;
762 old_lcr = serial_inp(p, UART_LCR);
763 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
765 old_dll = serial_inp(p, UART_DLL);
766 old_dlm = serial_inp(p, UART_DLM);
768 serial_outp(p, UART_DLL, 0);
769 serial_outp(p, UART_DLM, 0);
771 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
773 serial_outp(p, UART_DLL, old_dll);
774 serial_outp(p, UART_DLM, old_dlm);
775 serial_outp(p, UART_LCR, old_lcr);
781 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
782 * When this function is called we know it is at least a StarTech
783 * 16650 V2, but it might be one of several StarTech UARTs, or one of
784 * its clones. (We treat the broken original StarTech 16650 V1 as a
785 * 16550, and why not? Startech doesn't seem to even acknowledge its
788 * What evil have men's minds wrought...
790 static void autoconfig_has_efr(struct uart_8250_port *up)
792 unsigned int id1, id2, id3, rev;
795 * Everything with an EFR has SLEEP
797 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
800 * First we check to see if it's an Oxford Semiconductor UART.
802 * If we have to do this here because some non-National
803 * Semiconductor clone chips lock up if you try writing to the
804 * LSR register (which serial_icr_read does)
808 * Check for Oxford Semiconductor 16C950.
810 * EFR [4] must be set else this test fails.
812 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
813 * claims that it's needed for 952 dual UART's (which are not
814 * recommended for new designs).
817 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
818 serial_out(up, UART_EFR, UART_EFR_ECB);
819 serial_out(up, UART_LCR, 0x00);
820 id1 = serial_icr_read(up, UART_ID1);
821 id2 = serial_icr_read(up, UART_ID2);
822 id3 = serial_icr_read(up, UART_ID3);
823 rev = serial_icr_read(up, UART_REV);
825 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
827 if (id1 == 0x16 && id2 == 0xC9 &&
828 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
829 up->port.type = PORT_16C950;
832 * Enable work around for the Oxford Semiconductor 952 rev B
833 * chip which causes it to seriously miscalculate baud rates
836 if (id3 == 0x52 && rev == 0x01)
837 up->bugs |= UART_BUG_QUOT;
842 * We check for a XR16C850 by setting DLL and DLM to 0, and then
843 * reading back DLL and DLM. The chip type depends on the DLM
845 * 0x10 - XR16C850 and the DLL contains the chip revision.
849 id1 = autoconfig_read_divisor_id(up);
850 DEBUG_AUTOCONF("850id=%04x ", id1);
853 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
854 up->port.type = PORT_16850;
859 * It wasn't an XR16C850.
861 * We distinguish between the '654 and the '650 by counting
862 * how many bytes are in the FIFO. I'm using this for now,
863 * since that's the technique that was sent to me in the
864 * serial driver update, but I'm not convinced this works.
865 * I've had problems doing this in the past. -TYT
867 if (size_fifo(up) == 64)
868 up->port.type = PORT_16654;
870 up->port.type = PORT_16650V2;
874 * We detected a chip without a FIFO. Only two fall into
875 * this category - the original 8250 and the 16450. The
876 * 16450 has a scratch register (accessible with LCR=0)
878 static void autoconfig_8250(struct uart_8250_port *up)
880 unsigned char scratch, status1, status2;
882 up->port.type = PORT_8250;
884 scratch = serial_in(up, UART_SCR);
885 serial_outp(up, UART_SCR, 0xa5);
886 status1 = serial_in(up, UART_SCR);
887 serial_outp(up, UART_SCR, 0x5a);
888 status2 = serial_in(up, UART_SCR);
889 serial_outp(up, UART_SCR, scratch);
891 if (status1 == 0xa5 && status2 == 0x5a)
892 up->port.type = PORT_16450;
895 static int broken_efr(struct uart_8250_port *up)
898 * Exar ST16C2550 "A2" devices incorrectly detect as
899 * having an EFR, and report an ID of 0x0201. See
900 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
902 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
908 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
910 unsigned char status;
912 status = serial_in(up, 0x04); /* EXCR2 */
913 #define PRESL(x) ((x) & 0x30)
914 if (PRESL(status) == 0x10) {
915 /* already in high speed mode */
918 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
919 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
920 serial_outp(up, 0x04, status);
926 * We know that the chip has FIFOs. Does it have an EFR? The
927 * EFR is located in the same register position as the IIR and
928 * we know the top two bits of the IIR are currently set. The
929 * EFR should contain zero. Try to read the EFR.
931 static void autoconfig_16550a(struct uart_8250_port *up)
933 unsigned char status1, status2;
934 unsigned int iersave;
936 up->port.type = PORT_16550A;
937 up->capabilities |= UART_CAP_FIFO;
940 * Check for presence of the EFR when DLAB is set.
941 * Only ST16C650V1 UARTs pass this test.
943 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
944 if (serial_in(up, UART_EFR) == 0) {
945 serial_outp(up, UART_EFR, 0xA8);
946 if (serial_in(up, UART_EFR) != 0) {
947 DEBUG_AUTOCONF("EFRv1 ");
948 up->port.type = PORT_16650;
949 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
951 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
953 serial_outp(up, UART_EFR, 0);
958 * Maybe it requires 0xbf to be written to the LCR.
959 * (other ST16C650V2 UARTs, TI16C752A, etc)
961 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
962 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
963 DEBUG_AUTOCONF("EFRv2 ");
964 autoconfig_has_efr(up);
969 * Check for a National Semiconductor SuperIO chip.
970 * Attempt to switch to bank 2, read the value of the LOOP bit
971 * from EXCR1. Switch back to bank 0, change it in MCR. Then
972 * switch back to bank 2, read it from EXCR1 again and check
973 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
975 serial_outp(up, UART_LCR, 0);
976 status1 = serial_in(up, UART_MCR);
977 serial_outp(up, UART_LCR, 0xE0);
978 status2 = serial_in(up, 0x02); /* EXCR1 */
980 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
981 serial_outp(up, UART_LCR, 0);
982 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
983 serial_outp(up, UART_LCR, 0xE0);
984 status2 = serial_in(up, 0x02); /* EXCR1 */
985 serial_outp(up, UART_LCR, 0);
986 serial_outp(up, UART_MCR, status1);
988 if ((status2 ^ status1) & UART_MCR_LOOP) {
991 serial_outp(up, UART_LCR, 0xE0);
993 quot = serial_dl_read(up);
996 if (ns16550a_goto_highspeed(up))
997 serial_dl_write(up, quot);
999 serial_outp(up, UART_LCR, 0);
1001 up->port.uartclk = 921600*16;
1002 up->port.type = PORT_NS16550A;
1003 up->capabilities |= UART_NATSEMI;
1009 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1010 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1011 * Try setting it with and without DLAB set. Cheap clones
1012 * set bit 5 without DLAB set.
1014 serial_outp(up, UART_LCR, 0);
1015 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1016 status1 = serial_in(up, UART_IIR) >> 5;
1017 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1018 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1019 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1020 status2 = serial_in(up, UART_IIR) >> 5;
1021 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1022 serial_outp(up, UART_LCR, 0);
1024 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1026 if (status1 == 6 && status2 == 7) {
1027 up->port.type = PORT_16750;
1028 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1033 * Try writing and reading the UART_IER_UUE bit (b6).
1034 * If it works, this is probably one of the Xscale platform's
1036 * We're going to explicitly set the UUE bit to 0 before
1037 * trying to write and read a 1 just to make sure it's not
1038 * already a 1 and maybe locked there before we even start start.
1040 iersave = serial_in(up, UART_IER);
1041 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1042 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1044 * OK it's in a known zero state, try writing and reading
1045 * without disturbing the current state of the other bits.
1047 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1048 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1051 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1053 DEBUG_AUTOCONF("Xscale ");
1054 up->port.type = PORT_XSCALE;
1055 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1060 * If we got here we couldn't force the IER_UUE bit to 0.
1061 * Log it and continue.
1063 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1065 serial_outp(up, UART_IER, iersave);
1068 * Exar uarts have EFR in a weird location
1070 if (up->port.flags & UPF_EXAR_EFR) {
1071 up->port.type = PORT_XR17D15X;
1072 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1076 * We distinguish between 16550A and U6 16550A by counting
1077 * how many bytes are in the FIFO.
1079 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1080 up->port.type = PORT_U6_16550A;
1081 up->capabilities |= UART_CAP_AFE;
1086 * This routine is called by rs_init() to initialize a specific serial
1087 * port. It determines what type of UART chip this serial port is
1088 * using: 8250, 16450, 16550, 16550A. The important question is
1089 * whether or not this UART is a 16550A or not, since this will
1090 * determine whether or not we can use its FIFO features or not.
1092 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1094 unsigned char status1, scratch, scratch2, scratch3;
1095 unsigned char save_lcr, save_mcr;
1096 unsigned long flags;
1098 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1101 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1102 serial_index(&up->port), up->port.iobase, up->port.membase);
1105 * We really do need global IRQs disabled here - we're going to
1106 * be frobbing the chips IRQ enable register to see if it exists.
1108 spin_lock_irqsave(&up->port.lock, flags);
1110 up->capabilities = 0;
1113 if (!(up->port.flags & UPF_BUGGY_UART)) {
1115 * Do a simple existence test first; if we fail this,
1116 * there's no point trying anything else.
1118 * 0x80 is used as a nonsense port to prevent against
1119 * false positives due to ISA bus float. The
1120 * assumption is that 0x80 is a non-existent port;
1121 * which should be safe since include/asm/io.h also
1122 * makes this assumption.
1124 * Note: this is safe as long as MCR bit 4 is clear
1125 * and the device is in "PC" mode.
1127 scratch = serial_inp(up, UART_IER);
1128 serial_outp(up, UART_IER, 0);
1133 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1134 * 16C754B) allow only to modify them if an EFR bit is set.
1136 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1137 serial_outp(up, UART_IER, 0x0F);
1141 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1142 serial_outp(up, UART_IER, scratch);
1143 if (scratch2 != 0 || scratch3 != 0x0F) {
1145 * We failed; there's nothing here
1147 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1148 scratch2, scratch3);
1153 save_mcr = serial_in(up, UART_MCR);
1154 save_lcr = serial_in(up, UART_LCR);
1157 * Check to see if a UART is really there. Certain broken
1158 * internal modems based on the Rockwell chipset fail this
1159 * test, because they apparently don't implement the loopback
1160 * test mode. So this test is skipped on the COM 1 through
1161 * COM 4 ports. This *should* be safe, since no board
1162 * manufacturer would be stupid enough to design a board
1163 * that conflicts with COM 1-4 --- we hope!
1165 if (!(up->port.flags & UPF_SKIP_TEST)) {
1166 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1167 status1 = serial_inp(up, UART_MSR) & 0xF0;
1168 serial_outp(up, UART_MCR, save_mcr);
1169 if (status1 != 0x90) {
1170 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1177 * We're pretty sure there's a port here. Lets find out what
1178 * type of port it is. The IIR top two bits allows us to find
1179 * out if it's 8250 or 16450, 16550, 16550A or later. This
1180 * determines what we test for next.
1182 * We also initialise the EFR (if any) to zero for later. The
1183 * EFR occupies the same register location as the FCR and IIR.
1185 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1186 serial_outp(up, UART_EFR, 0);
1187 serial_outp(up, UART_LCR, 0);
1189 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1190 scratch = serial_in(up, UART_IIR) >> 6;
1192 DEBUG_AUTOCONF("iir=%d ", scratch);
1196 autoconfig_8250(up);
1199 up->port.type = PORT_UNKNOWN;
1202 up->port.type = PORT_16550;
1205 autoconfig_16550a(up);
1209 #ifdef CONFIG_SERIAL_8250_RSA
1211 * Only probe for RSA ports if we got the region.
1213 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1216 for (i = 0 ; i < probe_rsa_count; ++i) {
1217 if (probe_rsa[i] == up->port.iobase &&
1219 up->port.type = PORT_RSA;
1226 serial_outp(up, UART_LCR, save_lcr);
1228 if (up->capabilities != uart_config[up->port.type].flags) {
1230 "ttyS%d: detected caps %08x should be %08x\n",
1231 serial_index(&up->port), up->capabilities,
1232 uart_config[up->port.type].flags);
1235 up->port.fifosize = uart_config[up->port.type].fifo_size;
1236 up->capabilities = uart_config[up->port.type].flags;
1237 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1239 if (up->port.type == PORT_UNKNOWN)
1245 #ifdef CONFIG_SERIAL_8250_RSA
1246 if (up->port.type == PORT_RSA)
1247 serial_outp(up, UART_RSA_FRR, 0);
1249 serial_outp(up, UART_MCR, save_mcr);
1250 serial8250_clear_fifos(up);
1251 serial_in(up, UART_RX);
1252 if (up->capabilities & UART_CAP_UUE)
1253 serial_outp(up, UART_IER, UART_IER_UUE);
1255 serial_outp(up, UART_IER, 0);
1258 spin_unlock_irqrestore(&up->port.lock, flags);
1259 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1262 static void autoconfig_irq(struct uart_8250_port *up)
1264 unsigned char save_mcr, save_ier;
1265 unsigned char save_ICP = 0;
1266 unsigned int ICP = 0;
1270 if (up->port.flags & UPF_FOURPORT) {
1271 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1272 save_ICP = inb_p(ICP);
1277 /* forget possible initially masked and pending IRQ */
1278 probe_irq_off(probe_irq_on());
1279 save_mcr = serial_inp(up, UART_MCR);
1280 save_ier = serial_inp(up, UART_IER);
1281 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1283 irqs = probe_irq_on();
1284 serial_outp(up, UART_MCR, 0);
1286 if (up->port.flags & UPF_FOURPORT) {
1287 serial_outp(up, UART_MCR,
1288 UART_MCR_DTR | UART_MCR_RTS);
1290 serial_outp(up, UART_MCR,
1291 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1293 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1294 (void)serial_inp(up, UART_LSR);
1295 (void)serial_inp(up, UART_RX);
1296 (void)serial_inp(up, UART_IIR);
1297 (void)serial_inp(up, UART_MSR);
1298 serial_outp(up, UART_TX, 0xFF);
1300 irq = probe_irq_off(irqs);
1302 serial_outp(up, UART_MCR, save_mcr);
1303 serial_outp(up, UART_IER, save_ier);
1305 if (up->port.flags & UPF_FOURPORT)
1306 outb_p(save_ICP, ICP);
1308 up->port.irq = (irq > 0) ? irq : 0;
1311 static inline void __stop_tx(struct uart_8250_port *p)
1313 if (p->ier & UART_IER_THRI) {
1314 p->ier &= ~UART_IER_THRI;
1315 serial_out(p, UART_IER, p->ier);
1319 static void serial8250_stop_tx(struct uart_port *port)
1321 struct uart_8250_port *up =
1322 container_of(port, struct uart_8250_port, port);
1327 * We really want to stop the transmitter from sending.
1329 if (up->port.type == PORT_16C950) {
1330 up->acr |= UART_ACR_TXDIS;
1331 serial_icr_write(up, UART_ACR, up->acr);
1335 static void transmit_chars(struct uart_8250_port *up);
1337 static void serial8250_start_tx(struct uart_port *port)
1339 struct uart_8250_port *up =
1340 container_of(port, struct uart_8250_port, port);
1342 if (!(up->ier & UART_IER_THRI)) {
1343 up->ier |= UART_IER_THRI;
1344 serial_out(up, UART_IER, up->ier);
1346 if (up->bugs & UART_BUG_TXEN) {
1348 lsr = serial_in(up, UART_LSR);
1349 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1350 if ((up->port.type == PORT_RM9000) ?
1351 (lsr & UART_LSR_THRE) :
1352 (lsr & UART_LSR_TEMT))
1358 * Re-enable the transmitter if we disabled it.
1360 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1361 up->acr &= ~UART_ACR_TXDIS;
1362 serial_icr_write(up, UART_ACR, up->acr);
1366 static void serial8250_stop_rx(struct uart_port *port)
1368 struct uart_8250_port *up =
1369 container_of(port, struct uart_8250_port, port);
1371 up->ier &= ~UART_IER_RLSI;
1372 up->port.read_status_mask &= ~UART_LSR_DR;
1373 serial_out(up, UART_IER, up->ier);
1376 static void serial8250_enable_ms(struct uart_port *port)
1378 struct uart_8250_port *up =
1379 container_of(port, struct uart_8250_port, port);
1381 /* no MSR capabilities */
1382 if (up->bugs & UART_BUG_NOMSR)
1385 up->ier |= UART_IER_MSI;
1386 serial_out(up, UART_IER, up->ier);
1390 * Clear the Tegra rx fifo after a break
1392 * FIXME: This needs to become a port specific callback once we have a
1393 * framework for this
1395 static void clear_rx_fifo(struct uart_8250_port *up)
1397 unsigned int status, tmout = 10000;
1399 status = serial_in(up, UART_LSR);
1400 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1401 status = serial_in(up, UART_RX);
1411 receive_chars(struct uart_8250_port *up, unsigned int *status)
1413 struct tty_struct *tty = up->port.state->port.tty;
1414 unsigned char ch, lsr = *status;
1415 int max_count = 256;
1419 if (likely(lsr & UART_LSR_DR))
1420 ch = serial_inp(up, UART_RX);
1423 * Intel 82571 has a Serial Over Lan device that will
1424 * set UART_LSR_BI without setting UART_LSR_DR when
1425 * it receives a break. To avoid reading from the
1426 * receive buffer without UART_LSR_DR bit set, we
1427 * just force the read character to be 0
1432 up->port.icount.rx++;
1434 lsr |= up->lsr_saved_flags;
1435 up->lsr_saved_flags = 0;
1437 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1439 * For statistics only
1441 if (lsr & UART_LSR_BI) {
1442 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1443 up->port.icount.brk++;
1445 * If tegra port then clear the rx fifo to
1446 * accept another break/character.
1448 if (up->port.type == PORT_TEGRA)
1452 * We do the SysRQ and SAK checking
1453 * here because otherwise the break
1454 * may get masked by ignore_status_mask
1455 * or read_status_mask.
1457 if (uart_handle_break(&up->port))
1459 } else if (lsr & UART_LSR_PE)
1460 up->port.icount.parity++;
1461 else if (lsr & UART_LSR_FE)
1462 up->port.icount.frame++;
1463 if (lsr & UART_LSR_OE)
1464 up->port.icount.overrun++;
1467 * Mask off conditions which should be ignored.
1469 lsr &= up->port.read_status_mask;
1471 if (lsr & UART_LSR_BI) {
1472 DEBUG_INTR("handling break....");
1474 } else if (lsr & UART_LSR_PE)
1476 else if (lsr & UART_LSR_FE)
1479 if (uart_handle_sysrq_char(&up->port, ch))
1482 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1485 lsr = serial_inp(up, UART_LSR);
1486 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1487 spin_unlock(&up->port.lock);
1488 tty_flip_buffer_push(tty);
1489 spin_lock(&up->port.lock);
1493 static void transmit_chars(struct uart_8250_port *up)
1495 struct circ_buf *xmit = &up->port.state->xmit;
1498 if (up->port.x_char) {
1499 serial_outp(up, UART_TX, up->port.x_char);
1500 up->port.icount.tx++;
1501 up->port.x_char = 0;
1504 if (uart_tx_stopped(&up->port)) {
1505 serial8250_stop_tx(&up->port);
1508 if (uart_circ_empty(xmit)) {
1513 count = up->tx_loadsz;
1515 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1516 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1517 up->port.icount.tx++;
1518 if (uart_circ_empty(xmit))
1520 if (up->capabilities & UART_CAP_HFIFO) {
1521 if ((serial_in(up, UART_LSR) & BOTH_EMPTY) !=
1525 } while (--count > 0);
1527 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1528 uart_write_wakeup(&up->port);
1530 DEBUG_INTR("THRE...");
1532 if (uart_circ_empty(xmit))
1536 static unsigned int check_modem_status(struct uart_8250_port *up)
1538 unsigned int status = serial_in(up, UART_MSR);
1540 status |= up->msr_saved_flags;
1541 up->msr_saved_flags = 0;
1542 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1543 up->port.state != NULL) {
1544 if (status & UART_MSR_TERI)
1545 up->port.icount.rng++;
1546 if (status & UART_MSR_DDSR)
1547 up->port.icount.dsr++;
1548 if (status & UART_MSR_DDCD)
1549 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1550 if (status & UART_MSR_DCTS)
1551 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1553 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1560 * This handles the interrupt from one port.
1562 static void serial8250_handle_port(struct uart_8250_port *up)
1564 unsigned int status;
1565 unsigned long flags;
1567 spin_lock_irqsave(&up->port.lock, flags);
1569 status = serial_inp(up, UART_LSR);
1571 DEBUG_INTR("status = %x...", status);
1573 if (status & (UART_LSR_DR | UART_LSR_BI))
1574 receive_chars(up, &status);
1575 check_modem_status(up);
1576 if (status & UART_LSR_THRE)
1579 spin_unlock_irqrestore(&up->port.lock, flags);
1582 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1584 struct uart_8250_port *up =
1585 container_of(port, struct uart_8250_port, port);
1587 if (!(iir & UART_IIR_NO_INT)) {
1588 serial8250_handle_port(up);
1594 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1596 static int serial8250_default_handle_irq(struct uart_port *port)
1598 struct uart_8250_port *up =
1599 container_of(port, struct uart_8250_port, port);
1600 unsigned int iir = serial_in(up, UART_IIR);
1602 return serial8250_handle_irq(port, iir);
1606 * This is the serial driver's interrupt routine.
1608 * Arjan thinks the old way was overly complex, so it got simplified.
1609 * Alan disagrees, saying that need the complexity to handle the weird
1610 * nature of ISA shared interrupts. (This is a special exception.)
1612 * In order to handle ISA shared interrupts properly, we need to check
1613 * that all ports have been serviced, and therefore the ISA interrupt
1614 * line has been de-asserted.
1616 * This means we need to loop through all ports. checking that they
1617 * don't have an interrupt pending.
1619 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1621 struct irq_info *i = dev_id;
1622 struct list_head *l, *end = NULL;
1623 int pass_counter = 0, handled = 0;
1625 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1627 spin_lock(&i->lock);
1631 struct uart_8250_port *up;
1632 struct uart_port *port;
1634 up = list_entry(l, struct uart_8250_port, list);
1637 if (port->handle_irq(port)) {
1640 } else if (end == NULL)
1645 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1646 /* If we hit this, we're dead. */
1647 printk_ratelimited(KERN_ERR
1648 "serial8250: too much work for irq%d\n", irq);
1653 spin_unlock(&i->lock);
1655 DEBUG_INTR("end.\n");
1657 return IRQ_RETVAL(handled);
1661 * To support ISA shared interrupts, we need to have one interrupt
1662 * handler that ensures that the IRQ line has been deasserted
1663 * before returning. Failing to do this will result in the IRQ
1664 * line being stuck active, and, since ISA irqs are edge triggered,
1665 * no more IRQs will be seen.
1667 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1669 spin_lock_irq(&i->lock);
1671 if (!list_empty(i->head)) {
1672 if (i->head == &up->list)
1673 i->head = i->head->next;
1674 list_del(&up->list);
1676 BUG_ON(i->head != &up->list);
1679 spin_unlock_irq(&i->lock);
1680 /* List empty so throw away the hash node */
1681 if (i->head == NULL) {
1682 hlist_del(&i->node);
1687 static int serial_link_irq_chain(struct uart_8250_port *up)
1689 struct hlist_head *h;
1690 struct hlist_node *n;
1692 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1694 mutex_lock(&hash_mutex);
1696 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1698 hlist_for_each(n, h) {
1699 i = hlist_entry(n, struct irq_info, node);
1700 if (i->irq == up->port.irq)
1705 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1707 mutex_unlock(&hash_mutex);
1710 spin_lock_init(&i->lock);
1711 i->irq = up->port.irq;
1712 hlist_add_head(&i->node, h);
1714 mutex_unlock(&hash_mutex);
1716 spin_lock_irq(&i->lock);
1719 list_add(&up->list, i->head);
1720 spin_unlock_irq(&i->lock);
1724 INIT_LIST_HEAD(&up->list);
1725 i->head = &up->list;
1726 spin_unlock_irq(&i->lock);
1727 irq_flags |= up->port.irqflags;
1728 ret = request_irq(up->port.irq, serial8250_interrupt,
1729 irq_flags, "serial", i);
1731 serial_do_unlink(i, up);
1737 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1740 struct hlist_node *n;
1741 struct hlist_head *h;
1743 mutex_lock(&hash_mutex);
1745 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1747 hlist_for_each(n, h) {
1748 i = hlist_entry(n, struct irq_info, node);
1749 if (i->irq == up->port.irq)
1754 BUG_ON(i->head == NULL);
1756 if (list_empty(i->head))
1757 free_irq(up->port.irq, i);
1759 serial_do_unlink(i, up);
1760 mutex_unlock(&hash_mutex);
1764 * This function is used to handle ports that do not have an
1765 * interrupt. This doesn't work very well for 16450's, but gives
1766 * barely passable results for a 16550A. (Although at the expense
1767 * of much CPU overhead).
1769 static void serial8250_timeout(unsigned long data)
1771 struct uart_8250_port *up = (struct uart_8250_port *)data;
1774 iir = serial_in(up, UART_IIR);
1775 if (!(iir & UART_IIR_NO_INT))
1776 serial8250_handle_port(up);
1777 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1780 static void serial8250_backup_timeout(unsigned long data)
1782 struct uart_8250_port *up = (struct uart_8250_port *)data;
1783 unsigned int iir, ier = 0, lsr;
1784 unsigned long flags;
1786 spin_lock_irqsave(&up->port.lock, flags);
1789 * Must disable interrupts or else we risk racing with the interrupt
1792 if (is_real_interrupt(up->port.irq)) {
1793 ier = serial_in(up, UART_IER);
1794 serial_out(up, UART_IER, 0);
1797 iir = serial_in(up, UART_IIR);
1800 * This should be a safe test for anyone who doesn't trust the
1801 * IIR bits on their UART, but it's specifically designed for
1802 * the "Diva" UART used on the management processor on many HP
1803 * ia64 and parisc boxes.
1805 lsr = serial_in(up, UART_LSR);
1806 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1807 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1808 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1809 (lsr & UART_LSR_THRE)) {
1810 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1811 iir |= UART_IIR_THRI;
1814 if (!(iir & UART_IIR_NO_INT))
1817 if (is_real_interrupt(up->port.irq))
1818 serial_out(up, UART_IER, ier);
1820 spin_unlock_irqrestore(&up->port.lock, flags);
1822 /* Standard timer interval plus 0.2s to keep the port running */
1823 mod_timer(&up->timer,
1824 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1827 static unsigned int serial8250_tx_empty(struct uart_port *port)
1829 struct uart_8250_port *up =
1830 container_of(port, struct uart_8250_port, port);
1831 unsigned long flags;
1834 spin_lock_irqsave(&up->port.lock, flags);
1835 lsr = serial_in(up, UART_LSR);
1836 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1837 spin_unlock_irqrestore(&up->port.lock, flags);
1839 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1842 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1844 struct uart_8250_port *up =
1845 container_of(port, struct uart_8250_port, port);
1846 unsigned int status;
1849 status = check_modem_status(up);
1852 if (status & UART_MSR_DCD)
1854 if (status & UART_MSR_RI)
1856 if (status & UART_MSR_DSR)
1858 if (status & UART_MSR_CTS)
1863 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1865 struct uart_8250_port *up =
1866 container_of(port, struct uart_8250_port, port);
1867 unsigned char mcr = 0;
1869 if (mctrl & TIOCM_RTS)
1870 mcr |= UART_MCR_RTS;
1871 if (mctrl & TIOCM_DTR)
1872 mcr |= UART_MCR_DTR;
1873 if (mctrl & TIOCM_OUT1)
1874 mcr |= UART_MCR_OUT1;
1875 if (mctrl & TIOCM_OUT2)
1876 mcr |= UART_MCR_OUT2;
1877 if (mctrl & TIOCM_LOOP)
1878 mcr |= UART_MCR_LOOP;
1880 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1882 serial_out(up, UART_MCR, mcr);
1885 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1887 struct uart_8250_port *up =
1888 container_of(port, struct uart_8250_port, port);
1889 unsigned long flags;
1891 spin_lock_irqsave(&up->port.lock, flags);
1892 if (break_state == -1)
1893 up->lcr |= UART_LCR_SBC;
1895 up->lcr &= ~UART_LCR_SBC;
1896 serial_out(up, UART_LCR, up->lcr);
1897 spin_unlock_irqrestore(&up->port.lock, flags);
1901 * Wait for transmitter & holding register to empty
1903 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1905 unsigned int status, tmout = 10000;
1907 /* Wait up to 10ms for the character(s) to be sent. */
1909 status = serial_in(up, UART_LSR);
1911 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1913 if ((status & bits) == bits)
1920 /* Wait up to 1s for flow control if necessary */
1921 if (up->port.flags & UPF_CONS_FLOW) {
1923 for (tmout = 1000000; tmout; tmout--) {
1924 unsigned int msr = serial_in(up, UART_MSR);
1925 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1926 if (msr & UART_MSR_CTS)
1929 touch_nmi_watchdog();
1934 #ifdef CONFIG_CONSOLE_POLL
1936 * Console polling routines for writing and reading from the uart while
1937 * in an interrupt or debug context.
1940 static int serial8250_get_poll_char(struct uart_port *port)
1942 struct uart_8250_port *up =
1943 container_of(port, struct uart_8250_port, port);
1944 unsigned char lsr = serial_inp(up, UART_LSR);
1946 if (!(lsr & UART_LSR_DR))
1947 return NO_POLL_CHAR;
1949 return serial_inp(up, UART_RX);
1953 static void serial8250_put_poll_char(struct uart_port *port,
1957 struct uart_8250_port *up =
1958 container_of(port, struct uart_8250_port, port);
1961 * First save the IER then disable the interrupts
1963 ier = serial_in(up, UART_IER);
1964 if (up->capabilities & UART_CAP_UUE)
1965 serial_out(up, UART_IER, UART_IER_UUE);
1967 serial_out(up, UART_IER, 0);
1969 wait_for_xmitr(up, BOTH_EMPTY);
1971 * Send the character out.
1972 * If a LF, also do CR...
1974 serial_out(up, UART_TX, c);
1976 wait_for_xmitr(up, BOTH_EMPTY);
1977 serial_out(up, UART_TX, 13);
1981 * Finally, wait for transmitter to become empty
1982 * and restore the IER
1984 wait_for_xmitr(up, BOTH_EMPTY);
1985 serial_out(up, UART_IER, ier);
1988 #endif /* CONFIG_CONSOLE_POLL */
1990 static int serial8250_startup(struct uart_port *port)
1992 struct uart_8250_port *up =
1993 container_of(port, struct uart_8250_port, port);
1994 unsigned long flags;
1995 unsigned char lsr, iir;
1998 up->port.fifosize = uart_config[up->port.type].fifo_size;
1999 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
2000 up->capabilities = uart_config[up->port.type].flags;
2003 if (up->port.iotype != up->cur_iotype)
2004 set_io_from_upio(port);
2006 if (up->port.type == PORT_16C950) {
2007 /* Wake up and initialize UART */
2009 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2010 serial_outp(up, UART_EFR, UART_EFR_ECB);
2011 serial_outp(up, UART_IER, 0);
2012 serial_outp(up, UART_LCR, 0);
2013 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2014 serial_outp(up, UART_LCR, 0xBF);
2015 serial_outp(up, UART_EFR, UART_EFR_ECB);
2016 serial_outp(up, UART_LCR, 0);
2019 #ifdef CONFIG_SERIAL_8250_RSA
2021 * If this is an RSA port, see if we can kick it up to the
2022 * higher speed clock.
2028 * Clear the FIFO buffers and disable them.
2029 * (they will be reenabled in set_termios())
2031 serial8250_clear_fifos(up);
2034 * Clear the interrupt registers.
2036 (void) serial_inp(up, UART_LSR);
2037 (void) serial_inp(up, UART_RX);
2038 (void) serial_inp(up, UART_IIR);
2039 (void) serial_inp(up, UART_MSR);
2042 * At this point, there's no way the LSR could still be 0xff;
2043 * if it is, then bail out, because there's likely no UART
2046 if (!(up->port.flags & UPF_BUGGY_UART) &&
2047 (serial_inp(up, UART_LSR) == 0xff)) {
2048 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2049 serial_index(&up->port));
2054 * For a XR16C850, we need to set the trigger levels
2056 if (up->port.type == PORT_16850) {
2059 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2061 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2062 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2063 serial_outp(up, UART_TRG, UART_TRG_96);
2064 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2065 serial_outp(up, UART_TRG, UART_TRG_96);
2067 serial_outp(up, UART_LCR, 0);
2070 if (is_real_interrupt(up->port.irq)) {
2073 * Test for UARTs that do not reassert THRE when the
2074 * transmitter is idle and the interrupt has already
2075 * been cleared. Real 16550s should always reassert
2076 * this interrupt whenever the transmitter is idle and
2077 * the interrupt is enabled. Delays are necessary to
2078 * allow register changes to become visible.
2080 spin_lock_irqsave(&up->port.lock, flags);
2081 if (up->port.irqflags & IRQF_SHARED)
2082 disable_irq_nosync(up->port.irq);
2084 wait_for_xmitr(up, UART_LSR_THRE);
2085 serial_out_sync(up, UART_IER, UART_IER_THRI);
2086 udelay(1); /* allow THRE to set */
2087 iir1 = serial_in(up, UART_IIR);
2088 serial_out(up, UART_IER, 0);
2089 serial_out_sync(up, UART_IER, UART_IER_THRI);
2090 udelay(1); /* allow a working UART time to re-assert THRE */
2091 iir = serial_in(up, UART_IIR);
2092 serial_out(up, UART_IER, 0);
2094 if (up->port.irqflags & IRQF_SHARED)
2095 enable_irq(up->port.irq);
2096 spin_unlock_irqrestore(&up->port.lock, flags);
2099 * If the interrupt is not reasserted, setup a timer to
2100 * kick the UART on a regular basis.
2102 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2103 up->bugs |= UART_BUG_THRE;
2104 pr_debug("ttyS%d - using backup timer\n",
2105 serial_index(port));
2110 * The above check will only give an accurate result the first time
2111 * the port is opened so this value needs to be preserved.
2113 if (up->bugs & UART_BUG_THRE) {
2114 up->timer.function = serial8250_backup_timeout;
2115 up->timer.data = (unsigned long)up;
2116 mod_timer(&up->timer, jiffies +
2117 uart_poll_timeout(port) + HZ / 5);
2121 * If the "interrupt" for this port doesn't correspond with any
2122 * hardware interrupt, we use a timer-based system. The original
2123 * driver used to do this with IRQ0.
2125 if (!is_real_interrupt(up->port.irq)) {
2126 up->timer.data = (unsigned long)up;
2127 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2129 retval = serial_link_irq_chain(up);
2135 * Now, initialize the UART
2137 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2139 spin_lock_irqsave(&up->port.lock, flags);
2140 if (up->port.flags & UPF_FOURPORT) {
2141 if (!is_real_interrupt(up->port.irq))
2142 up->port.mctrl |= TIOCM_OUT1;
2145 * Most PC uarts need OUT2 raised to enable interrupts.
2147 if (is_real_interrupt(up->port.irq))
2148 up->port.mctrl |= TIOCM_OUT2;
2150 serial8250_set_mctrl(&up->port, up->port.mctrl);
2152 /* Serial over Lan (SoL) hack:
2153 Intel 8257x Gigabit ethernet chips have a
2154 16550 emulation, to be used for Serial Over Lan.
2155 Those chips take a longer time than a normal
2156 serial device to signalize that a transmission
2157 data was queued. Due to that, the above test generally
2158 fails. One solution would be to delay the reading of
2159 iir. However, this is not reliable, since the timeout
2160 is variable. So, let's just don't test if we receive
2161 TX irq. This way, we'll never enable UART_BUG_TXEN.
2163 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2164 goto dont_test_tx_en;
2167 * Do a quick test to see if we receive an
2168 * interrupt when we enable the TX irq.
2170 serial_outp(up, UART_IER, UART_IER_THRI);
2171 lsr = serial_in(up, UART_LSR);
2172 iir = serial_in(up, UART_IIR);
2173 serial_outp(up, UART_IER, 0);
2175 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2176 if (!(up->bugs & UART_BUG_TXEN)) {
2177 up->bugs |= UART_BUG_TXEN;
2178 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2179 serial_index(port));
2182 up->bugs &= ~UART_BUG_TXEN;
2186 spin_unlock_irqrestore(&up->port.lock, flags);
2189 * Clear the interrupt registers again for luck, and clear the
2190 * saved flags to avoid getting false values from polling
2191 * routines or the previous session.
2193 serial_inp(up, UART_LSR);
2194 serial_inp(up, UART_RX);
2195 serial_inp(up, UART_IIR);
2196 serial_inp(up, UART_MSR);
2197 up->lsr_saved_flags = 0;
2198 up->msr_saved_flags = 0;
2201 * Finally, enable interrupts. Note: Modem status interrupts
2202 * are set via set_termios(), which will be occurring imminently
2203 * anyway, so we don't enable them here.
2205 up->ier = UART_IER_RLSI | UART_IER_RDI;
2206 serial_outp(up, UART_IER, up->ier);
2208 if (up->port.flags & UPF_FOURPORT) {
2211 * Enable interrupts on the AST Fourport board
2213 icp = (up->port.iobase & 0xfe0) | 0x01f;
2221 static void serial8250_shutdown(struct uart_port *port)
2223 struct uart_8250_port *up =
2224 container_of(port, struct uart_8250_port, port);
2225 unsigned long flags;
2228 * Disable interrupts from this port
2231 serial_outp(up, UART_IER, 0);
2233 spin_lock_irqsave(&up->port.lock, flags);
2234 if (up->port.flags & UPF_FOURPORT) {
2235 /* reset interrupts on the AST Fourport board */
2236 inb((up->port.iobase & 0xfe0) | 0x1f);
2237 up->port.mctrl |= TIOCM_OUT1;
2239 up->port.mctrl &= ~TIOCM_OUT2;
2241 serial8250_set_mctrl(&up->port, up->port.mctrl);
2242 spin_unlock_irqrestore(&up->port.lock, flags);
2245 * Disable break condition and FIFOs
2247 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2248 serial8250_clear_fifos(up);
2250 #ifdef CONFIG_SERIAL_8250_RSA
2252 * Reset the RSA board back to 115kbps compat mode.
2258 * Read data port to reset things, and then unlink from
2261 (void) serial_in(up, UART_RX);
2263 del_timer_sync(&up->timer);
2264 up->timer.function = serial8250_timeout;
2265 if (is_real_interrupt(up->port.irq))
2266 serial_unlink_irq_chain(up);
2269 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2274 * Handle magic divisors for baud rates above baud_base on
2275 * SMSC SuperIO chips.
2277 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2278 baud == (port->uartclk/4))
2280 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2281 baud == (port->uartclk/8))
2284 quot = uart_get_divisor(port, baud);
2290 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2291 struct ktermios *old)
2293 struct uart_8250_port *up =
2294 container_of(port, struct uart_8250_port, port);
2295 unsigned char cval, fcr = 0;
2296 unsigned long flags;
2297 unsigned int baud, quot;
2299 switch (termios->c_cflag & CSIZE) {
2301 cval = UART_LCR_WLEN5;
2304 cval = UART_LCR_WLEN6;
2307 cval = UART_LCR_WLEN7;
2311 cval = UART_LCR_WLEN8;
2315 if (termios->c_cflag & CSTOPB)
2316 cval |= UART_LCR_STOP;
2317 if (termios->c_cflag & PARENB)
2318 cval |= UART_LCR_PARITY;
2319 if (!(termios->c_cflag & PARODD))
2320 cval |= UART_LCR_EPAR;
2322 if (termios->c_cflag & CMSPAR)
2323 cval |= UART_LCR_SPAR;
2327 * Ask the core to calculate the divisor for us.
2329 baud = uart_get_baud_rate(port, termios, old,
2330 port->uartclk / 16 / 0xffff,
2331 port->uartclk / 16);
2332 quot = serial8250_get_divisor(port, baud);
2335 * Oxford Semi 952 rev B workaround
2337 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2340 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2341 fcr = uart_config[up->port.type].fcr;
2343 fcr &= ~UART_FCR_TRIGGER_MASK;
2344 fcr |= UART_FCR_TRIGGER_1;
2349 * MCR-based auto flow control. When AFE is enabled, RTS will be
2350 * deasserted when the receive FIFO contains more characters than
2351 * the trigger, or the MCR RTS bit is cleared. In the case where
2352 * the remote UART is not using CTS auto flow control, we must
2353 * have sufficient FIFO entries for the latency of the remote
2354 * UART to respond. IOW, at least 32 bytes of FIFO.
2356 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2357 up->mcr &= ~UART_MCR_AFE;
2358 if (termios->c_cflag & CRTSCTS)
2359 up->mcr |= UART_MCR_AFE;
2363 * Ok, we're now changing the port state. Do it with
2364 * interrupts disabled.
2366 spin_lock_irqsave(&up->port.lock, flags);
2369 * Update the per-port timeout.
2371 uart_update_timeout(port, termios->c_cflag, baud);
2373 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2374 if (termios->c_iflag & INPCK)
2375 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2376 if (termios->c_iflag & (BRKINT | PARMRK))
2377 up->port.read_status_mask |= UART_LSR_BI;
2380 * Characteres to ignore
2382 up->port.ignore_status_mask = 0;
2383 if (termios->c_iflag & IGNPAR)
2384 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2385 if (termios->c_iflag & IGNBRK) {
2386 up->port.ignore_status_mask |= UART_LSR_BI;
2388 * If we're ignoring parity and break indicators,
2389 * ignore overruns too (for real raw support).
2391 if (termios->c_iflag & IGNPAR)
2392 up->port.ignore_status_mask |= UART_LSR_OE;
2396 * ignore all characters if CREAD is not set
2398 if ((termios->c_cflag & CREAD) == 0)
2399 up->port.ignore_status_mask |= UART_LSR_DR;
2402 * CTS flow control flag and modem status interrupts
2404 up->ier &= ~UART_IER_MSI;
2405 if (!(up->bugs & UART_BUG_NOMSR) &&
2406 UART_ENABLE_MS(&up->port, termios->c_cflag))
2407 up->ier |= UART_IER_MSI;
2408 if (up->capabilities & UART_CAP_UUE)
2409 up->ier |= UART_IER_UUE;
2410 if (up->capabilities & UART_CAP_RTOIE)
2411 up->ier |= UART_IER_RTOIE;
2413 serial_out(up, UART_IER, up->ier);
2415 if (up->capabilities & UART_CAP_EFR) {
2416 unsigned char efr = 0;
2418 * TI16C752/Startech hardware flow control. FIXME:
2419 * - TI16C752 requires control thresholds to be set.
2420 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2422 if (termios->c_cflag & CRTSCTS)
2423 efr |= UART_EFR_CTS;
2425 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2426 if (up->port.flags & UPF_EXAR_EFR)
2427 serial_outp(up, UART_XR_EFR, efr);
2429 serial_outp(up, UART_EFR, efr);
2432 #ifdef CONFIG_ARCH_OMAP
2433 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2434 if (cpu_is_omap1510() && is_omap_port(up)) {
2435 if (baud == 115200) {
2437 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2439 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2443 if (up->capabilities & UART_NATSEMI) {
2444 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2445 serial_outp(up, UART_LCR, 0xe0);
2447 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2450 serial_dl_write(up, quot);
2453 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2454 * is written without DLAB set, this mode will be disabled.
2456 if (up->port.type == PORT_16750)
2457 serial_outp(up, UART_FCR, fcr);
2459 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2460 up->lcr = cval; /* Save LCR */
2461 if (up->port.type != PORT_16750) {
2462 if (fcr & UART_FCR_ENABLE_FIFO) {
2463 /* emulated UARTs (Lucent Venus 167x) need two steps */
2464 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2466 serial_outp(up, UART_FCR, fcr); /* set fcr */
2468 serial8250_set_mctrl(&up->port, up->port.mctrl);
2469 spin_unlock_irqrestore(&up->port.lock, flags);
2470 /* Don't rewrite B0 */
2471 if (tty_termios_baud_rate(termios))
2472 tty_termios_encode_baud_rate(termios, baud, baud);
2474 EXPORT_SYMBOL(serial8250_do_set_termios);
2477 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2478 struct ktermios *old)
2480 if (port->set_termios)
2481 port->set_termios(port, termios, old);
2483 serial8250_do_set_termios(port, termios, old);
2487 serial8250_set_ldisc(struct uart_port *port, int new)
2490 port->flags |= UPF_HARDPPS_CD;
2491 serial8250_enable_ms(port);
2493 port->flags &= ~UPF_HARDPPS_CD;
2497 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2498 unsigned int oldstate)
2500 struct uart_8250_port *p =
2501 container_of(port, struct uart_8250_port, port);
2503 serial8250_set_sleep(p, state != 0);
2505 EXPORT_SYMBOL(serial8250_do_pm);
2508 serial8250_pm(struct uart_port *port, unsigned int state,
2509 unsigned int oldstate)
2512 port->pm(port, state, oldstate);
2514 serial8250_do_pm(port, state, oldstate);
2517 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2519 if (pt->port.iotype == UPIO_AU)
2521 #ifdef CONFIG_ARCH_OMAP
2522 if (is_omap_port(pt))
2523 return 0x16 << pt->port.regshift;
2525 return 8 << pt->port.regshift;
2529 * Resource handling.
2531 static int serial8250_request_std_resource(struct uart_8250_port *up)
2533 unsigned int size = serial8250_port_size(up);
2536 switch (up->port.iotype) {
2541 if (!up->port.mapbase)
2544 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2549 if (up->port.flags & UPF_IOREMAP) {
2550 up->port.membase = ioremap_nocache(up->port.mapbase,
2552 if (!up->port.membase) {
2553 release_mem_region(up->port.mapbase, size);
2561 if (!request_region(up->port.iobase, size, "serial"))
2568 static void serial8250_release_std_resource(struct uart_8250_port *up)
2570 unsigned int size = serial8250_port_size(up);
2572 switch (up->port.iotype) {
2577 if (!up->port.mapbase)
2580 if (up->port.flags & UPF_IOREMAP) {
2581 iounmap(up->port.membase);
2582 up->port.membase = NULL;
2585 release_mem_region(up->port.mapbase, size);
2590 release_region(up->port.iobase, size);
2595 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2597 unsigned long start = UART_RSA_BASE << up->port.regshift;
2598 unsigned int size = 8 << up->port.regshift;
2601 switch (up->port.iotype) {
2604 start += up->port.iobase;
2605 if (request_region(start, size, "serial-rsa"))
2615 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2617 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2618 unsigned int size = 8 << up->port.regshift;
2620 switch (up->port.iotype) {
2623 release_region(up->port.iobase + offset, size);
2628 static void serial8250_release_port(struct uart_port *port)
2630 struct uart_8250_port *up =
2631 container_of(port, struct uart_8250_port, port);
2633 serial8250_release_std_resource(up);
2634 if (up->port.type == PORT_RSA)
2635 serial8250_release_rsa_resource(up);
2638 static int serial8250_request_port(struct uart_port *port)
2640 struct uart_8250_port *up =
2641 container_of(port, struct uart_8250_port, port);
2644 ret = serial8250_request_std_resource(up);
2645 if (ret == 0 && up->port.type == PORT_RSA) {
2646 ret = serial8250_request_rsa_resource(up);
2648 serial8250_release_std_resource(up);
2654 static void serial8250_config_port(struct uart_port *port, int flags)
2656 struct uart_8250_port *up =
2657 container_of(port, struct uart_8250_port, port);
2658 int probeflags = PROBE_ANY;
2662 * Find the region that we can probe for. This in turn
2663 * tells us whether we can probe for the type of port.
2665 ret = serial8250_request_std_resource(up);
2669 ret = serial8250_request_rsa_resource(up);
2671 probeflags &= ~PROBE_RSA;
2673 if (up->port.iotype != up->cur_iotype)
2674 set_io_from_upio(port);
2676 if (flags & UART_CONFIG_TYPE)
2677 autoconfig(up, probeflags);
2679 /* if access method is AU, it is a 16550 with a quirk */
2680 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2681 up->bugs |= UART_BUG_NOMSR;
2683 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2686 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2687 serial8250_release_rsa_resource(up);
2688 if (up->port.type == PORT_UNKNOWN)
2689 serial8250_release_std_resource(up);
2693 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2695 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2696 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2697 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2698 ser->type == PORT_STARTECH || uart_config[ser->type].name == NULL)
2704 serial8250_type(struct uart_port *port)
2706 int type = port->type;
2708 if (type >= ARRAY_SIZE(uart_config) || uart_config[type].name == NULL)
2710 return uart_config[type].name;
2713 static struct uart_ops serial8250_pops = {
2714 .tx_empty = serial8250_tx_empty,
2715 .set_mctrl = serial8250_set_mctrl,
2716 .get_mctrl = serial8250_get_mctrl,
2717 .stop_tx = serial8250_stop_tx,
2718 .start_tx = serial8250_start_tx,
2719 .stop_rx = serial8250_stop_rx,
2720 .enable_ms = serial8250_enable_ms,
2721 .break_ctl = serial8250_break_ctl,
2722 .startup = serial8250_startup,
2723 .shutdown = serial8250_shutdown,
2724 .set_termios = serial8250_set_termios,
2725 .set_ldisc = serial8250_set_ldisc,
2726 .pm = serial8250_pm,
2727 .type = serial8250_type,
2728 .release_port = serial8250_release_port,
2729 .request_port = serial8250_request_port,
2730 .config_port = serial8250_config_port,
2731 .verify_port = serial8250_verify_port,
2732 #ifdef CONFIG_CONSOLE_POLL
2733 .poll_get_char = serial8250_get_poll_char,
2734 .poll_put_char = serial8250_put_poll_char,
2738 static struct uart_8250_port serial8250_ports[UART_NR];
2740 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2741 unsigned short *capabilities);
2743 void serial8250_set_isa_configurator(
2744 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2746 serial8250_isa_config = v;
2748 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2750 static void __init serial8250_isa_init_ports(void)
2752 struct uart_8250_port *up;
2753 static int first = 1;
2760 for (i = 0; i < nr_uarts; i++) {
2761 struct uart_8250_port *up = &serial8250_ports[i];
2764 spin_lock_init(&up->port.lock);
2766 init_timer(&up->timer);
2767 up->timer.function = serial8250_timeout;
2770 * ALPHA_KLUDGE_MCR needs to be killed.
2772 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2773 up->mcr_force = ALPHA_KLUDGE_MCR;
2775 up->port.ops = &serial8250_pops;
2779 irqflag = IRQF_SHARED;
2781 for (i = 0, up = serial8250_ports;
2782 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2784 up->port.iobase = old_serial_port[i].port;
2785 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2786 up->port.irqflags = old_serial_port[i].irqflags;
2787 up->port.uartclk = old_serial_port[i].baud_base * 16;
2788 up->port.flags = old_serial_port[i].flags;
2789 up->port.hub6 = old_serial_port[i].hub6;
2790 up->port.membase = old_serial_port[i].iomem_base;
2791 up->port.iotype = old_serial_port[i].io_type;
2792 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2793 set_io_from_upio(&up->port);
2794 up->port.irqflags |= irqflag;
2795 if (serial8250_isa_config != NULL)
2796 serial8250_isa_config(i, &up->port, &up->capabilities);
2802 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2804 up->port.type = type;
2805 up->port.fifosize = uart_config[type].fifo_size;
2806 up->capabilities = uart_config[type].flags;
2807 up->tx_loadsz = uart_config[type].tx_loadsz;
2811 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2815 for (i = 0; i < nr_uarts; i++) {
2816 struct uart_8250_port *up = &serial8250_ports[i];
2817 up->cur_iotype = 0xFF;
2820 serial8250_isa_init_ports();
2822 for (i = 0; i < nr_uarts; i++) {
2823 struct uart_8250_port *up = &serial8250_ports[i];
2827 if (up->port.flags & UPF_FIXED_TYPE)
2828 serial8250_init_fixed_type_port(up, up->port.type);
2830 uart_add_one_port(drv, &up->port);
2834 #ifdef CONFIG_SERIAL_8250_CONSOLE
2836 static void serial8250_console_putchar(struct uart_port *port, int ch)
2838 struct uart_8250_port *up =
2839 container_of(port, struct uart_8250_port, port);
2841 wait_for_xmitr(up, UART_LSR_THRE);
2842 serial_out(up, UART_TX, ch);
2846 * Print a string to the serial port trying not to disturb
2847 * any possible real use of the port...
2849 * The console_lock must be held when we get here.
2852 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2854 struct uart_8250_port *up = &serial8250_ports[co->index];
2855 unsigned long flags;
2859 touch_nmi_watchdog();
2861 local_irq_save(flags);
2862 if (up->port.sysrq) {
2863 /* serial8250_handle_port() already took the lock */
2865 } else if (oops_in_progress) {
2866 locked = spin_trylock(&up->port.lock);
2868 spin_lock(&up->port.lock);
2871 * First save the IER then disable the interrupts
2873 ier = serial_in(up, UART_IER);
2875 if (up->capabilities & UART_CAP_UUE)
2876 serial_out(up, UART_IER, UART_IER_UUE);
2878 serial_out(up, UART_IER, 0);
2880 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2883 * Finally, wait for transmitter to become empty
2884 * and restore the IER
2886 wait_for_xmitr(up, BOTH_EMPTY);
2887 serial_out(up, UART_IER, ier);
2890 * The receive handling will happen properly because the
2891 * receive ready bit will still be set; it is not cleared
2892 * on read. However, modem control will not, we must
2893 * call it if we have saved something in the saved flags
2894 * while processing with interrupts off.
2896 if (up->msr_saved_flags)
2897 check_modem_status(up);
2900 spin_unlock(&up->port.lock);
2901 local_irq_restore(flags);
2904 static int __init serial8250_console_setup(struct console *co, char *options)
2906 struct uart_port *port;
2913 * Check whether an invalid uart number has been specified, and
2914 * if so, search for the first available port that does have
2917 if (co->index >= nr_uarts)
2919 port = &serial8250_ports[co->index].port;
2920 if (!port->iobase && !port->membase)
2924 uart_parse_options(options, &baud, &parity, &bits, &flow);
2926 return uart_set_options(port, co, baud, parity, bits, flow);
2929 static int serial8250_console_early_setup(void)
2931 return serial8250_find_port_for_earlycon();
2934 static struct console serial8250_console = {
2936 .write = serial8250_console_write,
2937 .device = uart_console_device,
2938 .setup = serial8250_console_setup,
2939 .early_setup = serial8250_console_early_setup,
2940 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2942 .data = &serial8250_reg,
2945 static int __init serial8250_console_init(void)
2947 if (nr_uarts > UART_NR)
2950 serial8250_isa_init_ports();
2951 register_console(&serial8250_console);
2954 console_initcall(serial8250_console_init);
2956 int serial8250_find_port(struct uart_port *p)
2959 struct uart_port *port;
2961 for (line = 0; line < nr_uarts; line++) {
2962 port = &serial8250_ports[line].port;
2963 if (uart_match_port(p, port))
2969 #define SERIAL8250_CONSOLE &serial8250_console
2971 #define SERIAL8250_CONSOLE NULL
2974 static struct uart_driver serial8250_reg = {
2975 .owner = THIS_MODULE,
2976 .driver_name = "serial",
2980 .cons = SERIAL8250_CONSOLE,
2984 * early_serial_setup - early registration for 8250 ports
2986 * Setup an 8250 port structure prior to console initialisation. Use
2987 * after console initialisation will cause undefined behaviour.
2989 int __init early_serial_setup(struct uart_port *port)
2991 struct uart_port *p;
2993 if (port->line >= ARRAY_SIZE(serial8250_ports))
2996 serial8250_isa_init_ports();
2997 p = &serial8250_ports[port->line].port;
2998 p->iobase = port->iobase;
2999 p->membase = port->membase;
3001 p->irqflags = port->irqflags;
3002 p->uartclk = port->uartclk;
3003 p->fifosize = port->fifosize;
3004 p->regshift = port->regshift;
3005 p->iotype = port->iotype;
3006 p->flags = port->flags;
3007 p->mapbase = port->mapbase;
3008 p->private_data = port->private_data;
3009 p->type = port->type;
3010 p->line = port->line;
3012 set_io_from_upio(p);
3013 if (port->serial_in)
3014 p->serial_in = port->serial_in;
3015 if (port->serial_out)
3016 p->serial_out = port->serial_out;
3017 if (port->handle_irq)
3018 p->handle_irq = port->handle_irq;
3020 p->handle_irq = serial8250_default_handle_irq;
3026 * serial8250_suspend_port - suspend one serial port
3027 * @line: serial line number
3029 * Suspend one serial port.
3031 void serial8250_suspend_port(int line)
3033 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3037 * serial8250_resume_port - resume one serial port
3038 * @line: serial line number
3040 * Resume one serial port.
3042 void serial8250_resume_port(int line)
3044 struct uart_8250_port *up = &serial8250_ports[line];
3046 if (up->capabilities & UART_NATSEMI) {
3047 /* Ensure it's still in high speed mode */
3048 serial_outp(up, UART_LCR, 0xE0);
3050 ns16550a_goto_highspeed(up);
3052 serial_outp(up, UART_LCR, 0);
3053 up->port.uartclk = 921600*16;
3055 uart_resume_port(&serial8250_reg, &up->port);
3059 * Register a set of serial devices attached to a platform device. The
3060 * list is terminated with a zero flags entry, which means we expect
3061 * all entries to have at least UPF_BOOT_AUTOCONF set.
3063 static int __devinit serial8250_probe(struct platform_device *dev)
3065 struct plat_serial8250_port *p = dev->dev.platform_data;
3066 struct uart_port port;
3067 int ret, i, irqflag = 0;
3069 memset(&port, 0, sizeof(struct uart_port));
3072 irqflag = IRQF_SHARED;
3074 for (i = 0; p && p->flags != 0; p++, i++) {
3075 port.iobase = p->iobase;
3076 port.membase = p->membase;
3078 port.irqflags = p->irqflags;
3079 port.uartclk = p->uartclk;
3080 port.regshift = p->regshift;
3081 port.iotype = p->iotype;
3082 port.flags = p->flags;
3083 port.mapbase = p->mapbase;
3084 port.hub6 = p->hub6;
3085 port.private_data = p->private_data;
3086 port.type = p->type;
3087 port.serial_in = p->serial_in;
3088 port.serial_out = p->serial_out;
3089 port.handle_irq = p->handle_irq;
3090 port.set_termios = p->set_termios;
3092 port.dev = &dev->dev;
3093 port.irqflags |= irqflag;
3094 ret = serial8250_register_port(&port);
3096 dev_err(&dev->dev, "unable to register port at index %d "
3097 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3098 p->iobase, (unsigned long long)p->mapbase,
3106 * Remove serial ports registered against a platform device.
3108 static int __devexit serial8250_remove(struct platform_device *dev)
3112 for (i = 0; i < nr_uarts; i++) {
3113 struct uart_8250_port *up = &serial8250_ports[i];
3115 if (up->port.dev == &dev->dev)
3116 serial8250_unregister_port(i);
3121 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3125 for (i = 0; i < UART_NR; i++) {
3126 struct uart_8250_port *up = &serial8250_ports[i];
3128 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3129 uart_suspend_port(&serial8250_reg, &up->port);
3135 static int serial8250_resume(struct platform_device *dev)
3139 for (i = 0; i < UART_NR; i++) {
3140 struct uart_8250_port *up = &serial8250_ports[i];
3142 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3143 serial8250_resume_port(i);
3149 static struct platform_driver serial8250_isa_driver = {
3150 .probe = serial8250_probe,
3151 .remove = __devexit_p(serial8250_remove),
3152 .suspend = serial8250_suspend,
3153 .resume = serial8250_resume,
3155 .name = "serial8250",
3156 .owner = THIS_MODULE,
3161 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3162 * in the table in include/asm/serial.h
3164 static struct platform_device *serial8250_isa_devs;
3167 * serial8250_register_port and serial8250_unregister_port allows for
3168 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3169 * modems and PCI multiport cards.
3171 static DEFINE_MUTEX(serial_mutex);
3173 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3178 * First, find a port entry which matches.
3180 for (i = 0; i < nr_uarts; i++)
3181 if (uart_match_port(&serial8250_ports[i].port, port))
3182 return &serial8250_ports[i];
3185 * We didn't find a matching entry, so look for the first
3186 * free entry. We look for one which hasn't been previously
3187 * used (indicated by zero iobase).
3189 for (i = 0; i < nr_uarts; i++)
3190 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3191 serial8250_ports[i].port.iobase == 0)
3192 return &serial8250_ports[i];
3195 * That also failed. Last resort is to find any entry which
3196 * doesn't have a real port associated with it.
3198 for (i = 0; i < nr_uarts; i++)
3199 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3200 return &serial8250_ports[i];
3206 * serial8250_register_port - register a serial port
3207 * @port: serial port template
3209 * Configure the serial port specified by the request. If the
3210 * port exists and is in use, it is hung up and unregistered
3213 * The port is then probed and if necessary the IRQ is autodetected
3214 * If this fails an error is returned.
3216 * On success the port is ready to use and the line number is returned.
3218 int serial8250_register_port(struct uart_port *port)
3220 struct uart_8250_port *uart;
3223 if (port->uartclk == 0)
3226 mutex_lock(&serial_mutex);
3228 uart = serial8250_find_match_or_unused(port);
3230 uart_remove_one_port(&serial8250_reg, &uart->port);
3232 uart->port.iobase = port->iobase;
3233 uart->port.membase = port->membase;
3234 uart->port.irq = port->irq;
3235 uart->port.irqflags = port->irqflags;
3236 uart->port.uartclk = port->uartclk;
3237 uart->port.fifosize = port->fifosize;
3238 uart->port.regshift = port->regshift;
3239 uart->port.iotype = port->iotype;
3240 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3241 uart->port.mapbase = port->mapbase;
3242 uart->port.private_data = port->private_data;
3244 uart->port.dev = port->dev;
3246 if (port->flags & UPF_FIXED_TYPE)
3247 serial8250_init_fixed_type_port(uart, port->type);
3249 set_io_from_upio(&uart->port);
3250 /* Possibly override default I/O functions. */
3251 if (port->serial_in)
3252 uart->port.serial_in = port->serial_in;
3253 if (port->serial_out)
3254 uart->port.serial_out = port->serial_out;
3255 if (port->handle_irq)
3256 uart->port.handle_irq = port->handle_irq;
3257 /* Possibly override set_termios call */
3258 if (port->set_termios)
3259 uart->port.set_termios = port->set_termios;
3261 uart->port.pm = port->pm;
3263 if (serial8250_isa_config != NULL)
3264 serial8250_isa_config(0, &uart->port,
3265 &uart->capabilities);
3267 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3269 ret = uart->port.line;
3271 mutex_unlock(&serial_mutex);
3275 EXPORT_SYMBOL(serial8250_register_port);
3278 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3279 * @line: serial line number
3281 * Remove one serial port. This may not be called from interrupt
3282 * context. We hand the port back to the our control.
3284 void serial8250_unregister_port(int line)
3286 struct uart_8250_port *uart = &serial8250_ports[line];
3288 mutex_lock(&serial_mutex);
3289 uart_remove_one_port(&serial8250_reg, &uart->port);
3290 if (serial8250_isa_devs) {
3291 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3292 uart->port.type = PORT_UNKNOWN;
3293 uart->port.dev = &serial8250_isa_devs->dev;
3294 uart->capabilities = uart_config[uart->port.type].flags;
3295 uart_add_one_port(&serial8250_reg, &uart->port);
3297 uart->port.dev = NULL;
3299 mutex_unlock(&serial_mutex);
3301 EXPORT_SYMBOL(serial8250_unregister_port);
3303 static int __init serial8250_init(void)
3307 if (nr_uarts > UART_NR)
3310 printk(KERN_INFO "Serial: 8250/16550 driver, "
3311 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3312 share_irqs ? "en" : "dis");
3315 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3317 serial8250_reg.nr = UART_NR;
3318 ret = uart_register_driver(&serial8250_reg);
3323 serial8250_isa_devs = platform_device_alloc("serial8250",
3324 PLAT8250_DEV_LEGACY);
3325 if (!serial8250_isa_devs) {
3327 goto unreg_uart_drv;
3330 ret = platform_device_add(serial8250_isa_devs);
3334 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3336 ret = platform_driver_register(&serial8250_isa_driver);
3340 platform_device_del(serial8250_isa_devs);
3342 platform_device_put(serial8250_isa_devs);
3345 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3347 uart_unregister_driver(&serial8250_reg);
3353 static void __exit serial8250_exit(void)
3355 struct platform_device *isa_dev = serial8250_isa_devs;
3358 * This tells serial8250_unregister_port() not to re-register
3359 * the ports (thereby making serial8250_isa_driver permanently
3362 serial8250_isa_devs = NULL;
3364 platform_driver_unregister(&serial8250_isa_driver);
3365 platform_device_unregister(isa_dev);
3368 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3370 uart_unregister_driver(&serial8250_reg);
3374 module_init(serial8250_init);
3375 module_exit(serial8250_exit);
3377 EXPORT_SYMBOL(serial8250_suspend_port);
3378 EXPORT_SYMBOL(serial8250_resume_port);
3380 MODULE_LICENSE("GPL");
3381 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3383 module_param(share_irqs, uint, 0644);
3384 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3387 module_param(nr_uarts, uint, 0644);
3388 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3390 module_param(skip_txen_test, uint, 0644);
3391 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3393 #ifdef CONFIG_SERIAL_8250_RSA
3394 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3395 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3397 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);