drivers/staging/westbridge/astoria/include/linux/westbridge/cyanregs.h

   1 /*  Cypress West Bridge API header file (cyanregs.h)
   2  ## Register and field definitions for the Antioch device.
   3 ## ===========================
   4 ## Copyright (C) 2010  Cypress Semiconductor
   5 ##
   6 ## This program is free software; you can redistribute it and/or
   7 ## modify it under the terms of the GNU General Public License
   8 ## as published by the Free Software Foundation; either version 2
   9 ## of the License, or (at your option) any later version.
  10 ##
  11 ## This program is distributed in the hope that it will be useful,
  12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ## GNU General Public License for more details.
  15 ##
  16 ## You should have received a copy of the GNU General Public License
  17 ## along with this program; if not, write to the Free Software
  18 ## Foundation, Inc., 51 Franklin Street
  19 ## Fifth Floor, Boston, MA  02110-1301, USA.
  20 ## ===========================
  21 */
  22
  23 #ifndef _INCLUDED_CYANREG_H_
  24 #define _INCLUDED_CYANREG_H_
  25
  26 #if !defined(__doxygen__)
  27
  28 #define CY_AN_MEM_CM_WB_CFG_ID  (0x80)
  29 #define         CY_AN_MEM_CM_WB_CFG_ID_VER_MASK (0x000F)
  30 #define         CY_AN_MEM_CM_WB_CFG_ID_HDID_MASK (0xFFF0)
  31 #define         CY_AN_MEM_CM_WB_CFG_ID_HDID_ANTIOCH_VALUE (0xA100)
  32 #define         CY_AN_MEM_CM_WB_CFG_ID_HDID_ASTORIA_FPGA_VALUE (0x6800)
  33 #define         CY_AN_MEM_CM_WB_CFG_ID_HDID_ASTORIA_VALUE (0xA200)
  34
  35
  36 #define CY_AN_MEM_RST_CTRL_REG (0x81)
  37 #define         CY_AN_MEM_RST_CTRL_REG_HARD (0x0003)
  38 #define         CY_AN_MEM_RST_CTRL_REG_SOFT (0x0001)
  39 #define         CY_AN_MEM_RST_RSTCMPT (0x0004)
  40
  41 #define CY_AN_MEM_P0_ENDIAN     (0x82)
  42 #define         CY_AN_LITTLE_ENDIAN      (0x0000)
  43 #define         CY_AN_BIG_ENDIAN (0x0101)
  44
  45 #define CY_AN_MEM_P0_VM_SET     (0x83)
  46 #define         CY_AN_MEM_P0_VM_SET_VMTYPE_MASK (0x0007)
  47 #define         CY_AN_MEM_P0_VM_SET_VMTYPE_RAM (0x0005)
  48 #define         CY_AN_MEM_P0_VM_SET_VMTYPE_VMWIDTH (0x0008)
  49 #define         CY_AN_MEM_P0_VM_SET_VMTYPE_FLOWCTRL (0x0010)
  50 #define         CY_AN_MEM_P0_VM_SET_IFMODE (0x0020)
  51 #define         CY_AN_MEM_P0_VM_SET_CFGMODE (0x0040)
  52 #define         CY_AN_MEM_P0_VM_SET_DACKEOB     (0x0080)
  53 #define         CY_AN_MEM_P0_VM_SET_OVERRIDE (0x0100)
  54 #define         CY_AN_MEM_P0_VM_SET_INTOVERD (0x0200)
  55 #define         CY_AN_MEM_P0_VM_SET_DRQOVERD (0x0400)
  56 #define         CY_AN_MEM_P0_VM_SET_DRQPOL (0x0800)
  57 #define         CY_AN_MEM_P0_VM_SET_DACKPOL (0x1000)
  58
  59
  60 #define CY_AN_MEM_P0_NV_SET (0x84)
  61 #define         CY_AN_MEM_P0_NV_SET_WPSWEN (0x0001)
  62 #define         CY_AN_MEM_P0_NV_SET_WPPOLAR     (0x0002)
  63
  64 #define CY_AN_MEM_PMU_UPDATE (0x85)
  65 #define         CY_AN_MEM_PMU_UPDATE_UVALID (0x0001)
  66 #define         CY_AN_MEM_PMU_UPDATE_USBUPDATE (0x0002)
  67 #define         CY_AN_MEM_PMU_UPDATE_SDIOUPDATE (0x0004)
  68
  69 #define CY_AN_MEM_P0_INTR_REG (0x90)
  70 #define         CY_AN_MEM_P0_INTR_REG_MCUINT (0x0020)
  71 #define         CY_AN_MEM_P0_INTR_REG_DRQINT (0x0800)
  72 #define         CY_AN_MEM_P0_INTR_REG_MBINT     (0x1000)
  73 #define         CY_AN_MEM_P0_INTR_REG_PMINT     (0x2000)
  74 #define          CY_AN_MEM_P0_INTR_REG_PLLLOCKINT (0x4000)
  75
  76 #define CY_AN_MEM_P0_INT_MASK_REG (0x91)
  77 #define         CY_AN_MEM_P0_INT_MASK_REG_MMCUINT (0x0020)
  78 #define         CY_AN_MEM_P0_INT_MASK_REG_MDRQINT (0x0800)
  79 #define         CY_AN_MEM_P0_INT_MASK_REG_MMBINT (0x1000)
  80 #define         CY_AN_MEM_P0_INT_MASK_REG_MPMINT (0x2000)
  81 #define         CY_AN_MEM_P0_INT_MASK_REG_MPLLLOCKINT (0x4000)
  82
  83 #define CY_AN_MEM_MCU_MB_STAT (0x92)
  84 #define         CY_AN_MEM_P0_MCU_MBNOTRD (0x0001)
  85
  86 #define CY_AN_MEM_P0_MCU_STAT (0x94)
  87 #define         CY_AN_MEM_P0_MCU_STAT_CARDINS (0x0001)
  88 #define         CY_AN_MEM_P0_MCU_STAT_CARDREM (0x0002)
  89
  90 #define CY_AN_MEM_PWR_MAGT_STAT (0x95)
  91 #define         CY_AN_MEM_PWR_MAGT_STAT_WAKEUP (0x0001)
  92
  93 #define CY_AN_MEM_P0_RSE_ALLOCATE (0x98)
  94 #define         CY_AN_MEM_P0_RSE_ALLOCATE_SDIOAVI (0x0001)
  95 #define         CY_AN_MEM_P0_RSE_ALLOCATE_SDIOALLO (0x0002)
  96 #define         CY_AN_MEM_P0_RSE_ALLOCATE_NANDAVI (0x0004)
  97 #define         CY_AN_MEM_P0_RSE_ALLOCATE_NANDALLO (0x0008)
  98 #define         CY_AN_MEM_P0_RSE_ALLOCATE_USBAVI (0x0010)
  99 #define         CY_AN_MEM_P0_RSE_ALLOCATE_USBALLO (0x0020)
 100
 101 #define CY_AN_MEM_P0_RSE_MASK (0x9A)
 102 #define         CY_AN_MEM_P0_RSE_MASK_MSDIOBUS_RW (0x0003)
 103 #define         CY_AN_MEM_P0_RSE_MASK_MNANDBUS_RW (0x00C0)
 104 #define         CY_AN_MEM_P0_RSE_MASK_MUSBBUS_RW (0x0030)
 105
 106 #define CY_AN_MEM_P0_DRQ (0xA0)
 107 #define         CY_AN_MEM_P0_DRQ_EP2DRQ (0x0004)
 108 #define         CY_AN_MEM_P0_DRQ_EP3DRQ (0x0008)
 109 #define         CY_AN_MEM_P0_DRQ_EP4DRQ (0x0010)
 110 #define         CY_AN_MEM_P0_DRQ_EP5DRQ (0x0020)
 111 #define         CY_AN_MEM_P0_DRQ_EP6DRQ (0x0040)
 112 #define         CY_AN_MEM_P0_DRQ_EP7DRQ (0x0080)
 113 #define         CY_AN_MEM_P0_DRQ_EP8DRQ (0x0100)
 114 #define         CY_AN_MEM_P0_DRQ_EP9DRQ (0x0200)
 115 #define         CY_AN_MEM_P0_DRQ_EP10DRQ (0x0400)
 116 #define         CY_AN_MEM_P0_DRQ_EP11DRQ (0x0800)
 117 #define         CY_AN_MEM_P0_DRQ_EP12DRQ (0x1000)
 118 #define         CY_AN_MEM_P0_DRQ_EP13DRQ (0x2000)
 119 #define         CY_AN_MEM_P0_DRQ_EP14DRQ (0x4000)
 120 #define         CY_AN_MEM_P0_DRQ_EP15DRQ (0x8000)
 121
 122 #define CY_AN_MEM_P0_DRQ_MASK   (0xA1)
 123 #define         CY_AN_MEM_P0_DRQ_MASK_MEP2DRQ (0x0004)
 124 #define         CY_AN_MEM_P0_DRQ_MASK_MEP3DRQ (0x0008)
 125 #define         CY_AN_MEM_P0_DRQ_MASK_MEP4DRQ (0x0010)
 126 #define         CY_AN_MEM_P0_DRQ_MASK_MEP5DRQ (0x0020)
 127 #define         CY_AN_MEM_P0_DRQ_MASK_MEP6DRQ (0x0040)
 128 #define         CY_AN_MEM_P0_DRQ_MASK_MEP7DRQ (0x0080)
 129 #define         CY_AN_MEM_P0_DRQ_MASK_MEP8DRQ (0x0100)
 130 #define         CY_AN_MEM_P0_DRQ_MASK_MEP9DRQ (0x0200)
 131 #define         CY_AN_MEM_P0_DRQ_MASK_MEP10DRQ (0x0400)
 132 #define         CY_AN_MEM_P0_DRQ_MASK_MEP11DRQ (0x0800)
 133 #define         CY_AN_MEM_P0_DRQ_MASK_MEP12DRQ (0x1000)
 134 #define         CY_AN_MEM_P0_DRQ_MASK_MEP13DRQ (0x2000)
 135 #define         CY_AN_MEM_P0_DRQ_MASK_MEP14DRQ (0x4000)
 136 #define         CY_AN_MEM_P0_DRQ_MASK_MEP15DRQ (0x8000)
 137
 138 #define CY_AN_MEM_P0_EP2_DMA_REG (0xA2)
 139 #define         CY_AN_MEM_P0_E_pn_DMA_REG_COUNT_MASK (0x7FF)
 140 #define         CY_AN_MEM_P0_E_pn_DMA_REG_DMAVAL (1 << 12)
 141 #define CY_AN_MEM_P0_EP3_DMA_REG (0xA3)
 142 #define CY_AN_MEM_P0_EP4_DMA_REG (0xA4)
 143 #define CY_AN_MEM_P0_EP5_DMA_REG (0xA5)
 144 #define CY_AN_MEM_P0_EP6_DMA_REG (0xA6)
 145 #define CY_AN_MEM_P0_EP7_DMA_REG (0xA7)
 146 #define CY_AN_MEM_P0_EP8_DMA_REG (0xA8)
 147 #define CY_AN_MEM_P0_EP9_DMA_REG (0xA9)
 148 #define CY_AN_MEM_P0_EP10_DMA_REG (0xAA)
 149 #define CY_AN_MEM_P0_EP11_DMA_REG (0xAB)
 150 #define CY_AN_MEM_P0_EP12_DMA_REG (0xAC)
 151 #define CY_AN_MEM_P0_EP13_DMA_REG (0xAD)
 152 #define CY_AN_MEM_P0_EP14_DMA_REG (0xAE)
 153 #define CY_AN_MEM_P0_EP15_DMA_REG (0xAF)
 154
 155 #define CY_AN_MEM_IROS_IO_CFG (0xC1)
 156 #define  CY_AN_MEM_IROS_IO_CFG_GPIODRVST_MASK (0x0003)
 157 #define         CY_AN_MEM_IROS_IO_CFG_GPIOSLEW_MASK (0x0004)
 158 #define  CY_AN_MEM_IROS_IO_CFG_PPIODRVST_MASK (0x0018)
 159 #define  CY_AN_MEM_IROS_IO_CFG_PPIOSLEW_MASK (0x0020)
 160 #define         CY_AN_MEM_IROS_IO_CFG_SSIODRVST_MASK (0x0300)
 161 #define  CY_AN_MEM_IROS_IO_CFG_SSIOSLEW_MASK (0x0400)
 162 #define  CY_AN_MEM_IROS_IO_CFG_SNIODRVST_MASK (0x1800)
 163 #define         CY_AN_MEM_IROS_IO_CFG_SNIOSLEW_MASK (0x2000)
 164
 165 #define CY_AN_MEM_PLL_LOCK_LOSS_STAT (0xC4)
 166 #define          CY_AN_MEM_PLL_LOCK_LOSS_STAT_PLLSTAT (0x0800)
 167
 168 #define CY_AN_MEM_P0_MAILBOX0 (0xF0)
 169 #define CY_AN_MEM_P0_MAILBOX1 (0xF1)
 170 #define CY_AN_MEM_P0_MAILBOX2 (0xF2)
 171 #define CY_AN_MEM_P0_MAILBOX3 (0xF3)
 172
 173 #define CY_AN_MEM_MCU_MAILBOX0 (0xF8)
 174 #define CY_AN_MEM_MCU_MAILBOX1 (0xF9)
 175 #define CY_AN_MEM_MCU_MAILBOX2 (0xFA)
 176 #define CY_AN_MEM_MCU_MAILBOX3 (0xFB)
 177
 178 #endif                          /* !defined(__doxygen__) */
 179
 180 #endif                          /* _INCLUDED_CYANREG_H_ */