2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * Derived from ca91c042.c by Michael Wyrick
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/module.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/pci.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/poll.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/time.h>
31 #include <linux/uaccess.h>
34 #include "../vme_bridge.h"
35 #include "vme_ca91cx42.h"
37 static int __init ca91cx42_init(void);
38 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
39 static void ca91cx42_remove(struct pci_dev *);
40 static void __exit ca91cx42_exit(void);
42 /* Module parameters */
45 static const char driver_name[] = "vme_ca91cx42";
47 static DEFINE_PCI_DEVICE_TABLE(ca91cx42_ids) = {
48 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
52 static struct pci_driver ca91cx42_driver = {
54 .id_table = ca91cx42_ids,
55 .probe = ca91cx42_probe,
56 .remove = ca91cx42_remove,
59 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
61 wake_up(&bridge->dma_queue);
63 return CA91CX42_LINT_DMA;
66 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
71 for (i = 0; i < 4; i++) {
72 if (stat & CA91CX42_LINT_LM[i]) {
73 /* We only enable interrupts if the callback is set */
74 bridge->lm_callback[i](i);
75 serviced |= CA91CX42_LINT_LM[i];
82 /* XXX This needs to be split into 4 queues */
83 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
85 wake_up(&bridge->mbox_queue);
87 return CA91CX42_LINT_MBOX;
90 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
92 wake_up(&bridge->iack_queue);
94 return CA91CX42_LINT_SW_IACK;
97 static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
100 struct ca91cx42_driver *bridge;
102 bridge = ca91cx42_bridge->driver_priv;
104 val = ioread32(bridge->base + DGCS);
106 if (!(val & 0x00000800)) {
107 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
108 "Read Error DGCS=%08X\n", val);
111 return CA91CX42_LINT_VERR;
114 static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
117 struct ca91cx42_driver *bridge;
119 bridge = ca91cx42_bridge->driver_priv;
121 val = ioread32(bridge->base + DGCS);
123 if (!(val & 0x00000800))
124 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
125 "Read Error DGCS=%08X\n", val);
127 return CA91CX42_LINT_LERR;
131 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
134 int vec, i, serviced = 0;
135 struct ca91cx42_driver *bridge;
137 bridge = ca91cx42_bridge->driver_priv;
140 for (i = 7; i > 0; i--) {
141 if (stat & (1 << i)) {
142 vec = ioread32(bridge->base +
143 CA91CX42_V_STATID[i]) & 0xff;
145 vme_irq_handler(ca91cx42_bridge, i, vec);
147 serviced |= (1 << i);
154 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
156 u32 stat, enable, serviced = 0;
157 struct vme_bridge *ca91cx42_bridge;
158 struct ca91cx42_driver *bridge;
160 ca91cx42_bridge = ptr;
162 bridge = ca91cx42_bridge->driver_priv;
164 enable = ioread32(bridge->base + LINT_EN);
165 stat = ioread32(bridge->base + LINT_STAT);
167 /* Only look at unmasked interrupts */
173 if (stat & CA91CX42_LINT_DMA)
174 serviced |= ca91cx42_DMA_irqhandler(bridge);
175 if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
177 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
178 if (stat & CA91CX42_LINT_MBOX)
179 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
180 if (stat & CA91CX42_LINT_SW_IACK)
181 serviced |= ca91cx42_IACK_irqhandler(bridge);
182 if (stat & CA91CX42_LINT_VERR)
183 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
184 if (stat & CA91CX42_LINT_LERR)
185 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
186 if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
187 CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
188 CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
189 CA91CX42_LINT_VIRQ7))
190 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
192 /* Clear serviced interrupts */
193 iowrite32(serviced, bridge->base + LINT_STAT);
198 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
201 struct pci_dev *pdev;
202 struct ca91cx42_driver *bridge;
204 bridge = ca91cx42_bridge->driver_priv;
207 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
209 /* Initialise list for VME bus errors */
210 INIT_LIST_HEAD(&ca91cx42_bridge->vme_errors);
212 mutex_init(&ca91cx42_bridge->irq_mtx);
214 /* Disable interrupts from PCI to VME */
215 iowrite32(0, bridge->base + VINT_EN);
217 /* Disable PCI interrupts */
218 iowrite32(0, bridge->base + LINT_EN);
219 /* Clear Any Pending PCI Interrupts */
220 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
222 result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
223 driver_name, ca91cx42_bridge);
225 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
230 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
231 iowrite32(0, bridge->base + LINT_MAP0);
232 iowrite32(0, bridge->base + LINT_MAP1);
233 iowrite32(0, bridge->base + LINT_MAP2);
235 /* Enable DMA, mailbox & LM Interrupts */
236 tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
237 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
238 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
240 iowrite32(tmp, bridge->base + LINT_EN);
245 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
246 struct pci_dev *pdev)
248 /* Disable interrupts from PCI to VME */
249 iowrite32(0, bridge->base + VINT_EN);
251 /* Disable PCI interrupts */
252 iowrite32(0, bridge->base + LINT_EN);
253 /* Clear Any Pending PCI Interrupts */
254 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
256 free_irq(pdev->irq, pdev);
259 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level)
263 tmp = ioread32(bridge->base + LINT_STAT);
265 if (tmp & (1 << level))
272 * Set up an VME interrupt
274 static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level,
278 struct pci_dev *pdev;
280 struct ca91cx42_driver *bridge;
282 bridge = ca91cx42_bridge->driver_priv;
284 /* Enable IRQ level */
285 tmp = ioread32(bridge->base + LINT_EN);
288 tmp &= ~CA91CX42_LINT_VIRQ[level];
290 tmp |= CA91CX42_LINT_VIRQ[level];
292 iowrite32(tmp, bridge->base + LINT_EN);
294 if ((state == 0) && (sync != 0)) {
295 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
298 synchronize_irq(pdev->irq);
302 static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
306 struct ca91cx42_driver *bridge;
308 bridge = ca91cx42_bridge->driver_priv;
310 /* Universe can only generate even vectors */
314 mutex_lock(&bridge->vme_int);
316 tmp = ioread32(bridge->base + VINT_EN);
319 iowrite32(statid << 24, bridge->base + STATID);
321 /* Assert VMEbus IRQ */
322 tmp = tmp | (1 << (level + 24));
323 iowrite32(tmp, bridge->base + VINT_EN);
326 wait_event_interruptible(bridge->iack_queue,
327 ca91cx42_iack_received(bridge, level));
329 /* Return interrupt to low state */
330 tmp = ioread32(bridge->base + VINT_EN);
331 tmp = tmp & ~(1 << (level + 24));
332 iowrite32(tmp, bridge->base + VINT_EN);
334 mutex_unlock(&bridge->vme_int);
339 static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
340 unsigned long long vme_base, unsigned long long size,
341 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
343 unsigned int i, addr = 0, granularity;
344 unsigned int temp_ctl = 0;
345 unsigned int vme_bound, pci_offset;
346 struct vme_bridge *ca91cx42_bridge;
347 struct ca91cx42_driver *bridge;
349 ca91cx42_bridge = image->parent;
351 bridge = ca91cx42_bridge->driver_priv;
357 addr |= CA91CX42_VSI_CTL_VAS_A16;
360 addr |= CA91CX42_VSI_CTL_VAS_A24;
363 addr |= CA91CX42_VSI_CTL_VAS_A32;
366 addr |= CA91CX42_VSI_CTL_VAS_USER1;
369 addr |= CA91CX42_VSI_CTL_VAS_USER2;
376 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
382 * Bound address is a valid address for the window, adjust
385 vme_bound = vme_base + size;
386 pci_offset = pci_base - vme_base;
388 if ((i == 0) || (i == 4))
389 granularity = 0x1000;
391 granularity = 0x10000;
393 if (vme_base & (granularity - 1)) {
394 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
398 if (vme_bound & (granularity - 1)) {
399 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
403 if (pci_offset & (granularity - 1)) {
404 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
409 /* Disable while we are mucking around */
410 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
411 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
412 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
415 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
416 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
417 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
419 /* Setup address space */
420 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
423 /* Setup cycle types */
424 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
425 if (cycle & VME_SUPER)
426 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
427 if (cycle & VME_USER)
428 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
429 if (cycle & VME_PROG)
430 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
431 if (cycle & VME_DATA)
432 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
434 /* Write ctl reg without enable */
435 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
438 temp_ctl |= CA91CX42_VSI_CTL_EN;
440 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
445 static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
446 unsigned long long *vme_base, unsigned long long *size,
447 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
449 unsigned int i, granularity = 0, ctl = 0;
450 unsigned long long vme_bound, pci_offset;
451 struct ca91cx42_driver *bridge;
453 bridge = image->parent->driver_priv;
457 if ((i == 0) || (i == 4))
458 granularity = 0x1000;
460 granularity = 0x10000;
463 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
465 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
466 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
467 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
469 *pci_base = (dma_addr_t)vme_base + pci_offset;
470 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
476 if (ctl & CA91CX42_VSI_CTL_EN)
479 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
483 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
485 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
487 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
490 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
492 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
494 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
496 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
503 * Allocate and map PCI Resource
505 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
506 unsigned long long size)
508 unsigned long long existing_size;
510 struct pci_dev *pdev;
511 struct vme_bridge *ca91cx42_bridge;
513 ca91cx42_bridge = image->parent;
515 /* Find pci_dev container of dev */
516 if (ca91cx42_bridge->parent == NULL) {
517 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
520 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
522 existing_size = (unsigned long long)(image->bus_resource.end -
523 image->bus_resource.start);
525 /* If the existing size is OK, return */
526 if (existing_size == (size - 1))
529 if (existing_size != 0) {
530 iounmap(image->kern_base);
531 image->kern_base = NULL;
532 kfree(image->bus_resource.name);
533 release_resource(&image->bus_resource);
534 memset(&image->bus_resource, 0, sizeof(struct resource));
537 if (image->bus_resource.name == NULL) {
538 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
539 if (image->bus_resource.name == NULL) {
540 dev_err(ca91cx42_bridge->parent, "Unable to allocate "
541 "memory for resource name\n");
547 sprintf((char *)image->bus_resource.name, "%s.%d",
548 ca91cx42_bridge->name, image->number);
550 image->bus_resource.start = 0;
551 image->bus_resource.end = (unsigned long)size;
552 image->bus_resource.flags = IORESOURCE_MEM;
554 retval = pci_bus_alloc_resource(pdev->bus,
555 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
558 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
559 "resource for window %d size 0x%lx start 0x%lx\n",
560 image->number, (unsigned long)size,
561 (unsigned long)image->bus_resource.start);
565 image->kern_base = ioremap_nocache(
566 image->bus_resource.start, size);
567 if (image->kern_base == NULL) {
568 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
576 release_resource(&image->bus_resource);
578 kfree(image->bus_resource.name);
579 memset(&image->bus_resource, 0, sizeof(struct resource));
585 * Free and unmap PCI Resource
587 static void ca91cx42_free_resource(struct vme_master_resource *image)
589 iounmap(image->kern_base);
590 image->kern_base = NULL;
591 release_resource(&image->bus_resource);
592 kfree(image->bus_resource.name);
593 memset(&image->bus_resource, 0, sizeof(struct resource));
597 static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
598 unsigned long long vme_base, unsigned long long size,
599 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
602 unsigned int i, granularity = 0;
603 unsigned int temp_ctl = 0;
604 unsigned long long pci_bound, vme_offset, pci_base;
605 struct vme_bridge *ca91cx42_bridge;
606 struct ca91cx42_driver *bridge;
608 ca91cx42_bridge = image->parent;
610 bridge = ca91cx42_bridge->driver_priv;
614 if ((i == 0) || (i == 4))
615 granularity = 0x1000;
617 granularity = 0x10000;
619 /* Verify input data */
620 if (vme_base & (granularity - 1)) {
621 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
626 if (size & (granularity - 1)) {
627 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
633 spin_lock(&image->lock);
636 * Let's allocate the resource here rather than further up the stack as
637 * it avoids pushing loads of bus dependent stuff up the stack
639 retval = ca91cx42_alloc_resource(image, size);
641 spin_unlock(&image->lock);
642 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
643 "for resource name\n");
648 pci_base = (unsigned long long)image->bus_resource.start;
651 * Bound address is a valid address for the window, adjust
652 * according to window granularity.
654 pci_bound = pci_base + size;
655 vme_offset = vme_base - pci_base;
657 /* Disable while we are mucking around */
658 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
659 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
660 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
662 /* Setup cycle types */
663 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
665 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
666 if (cycle & VME_MBLT)
667 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
669 /* Setup data width */
670 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
673 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
676 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
679 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
682 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
685 spin_unlock(&image->lock);
686 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
692 /* Setup address space */
693 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
696 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
699 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
702 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
705 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
708 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
711 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
717 spin_unlock(&image->lock);
718 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
724 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
725 if (cycle & VME_SUPER)
726 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
727 if (cycle & VME_PROG)
728 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
731 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
732 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
733 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
735 /* Write ctl reg without enable */
736 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
739 temp_ctl |= CA91CX42_LSI_CTL_EN;
741 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
743 spin_unlock(&image->lock);
748 ca91cx42_free_resource(image);
754 static int __ca91cx42_master_get(struct vme_master_resource *image,
755 int *enabled, unsigned long long *vme_base, unsigned long long *size,
756 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
759 unsigned long long pci_base, pci_bound, vme_offset;
760 struct ca91cx42_driver *bridge;
762 bridge = image->parent->driver_priv;
766 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
768 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
769 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
770 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
772 *vme_base = pci_base + vme_offset;
773 *size = (unsigned long long)(pci_bound - pci_base);
780 if (ctl & CA91CX42_LSI_CTL_EN)
783 /* Setup address space */
784 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
785 case CA91CX42_LSI_CTL_VAS_A16:
788 case CA91CX42_LSI_CTL_VAS_A24:
791 case CA91CX42_LSI_CTL_VAS_A32:
794 case CA91CX42_LSI_CTL_VAS_CRCSR:
797 case CA91CX42_LSI_CTL_VAS_USER1:
800 case CA91CX42_LSI_CTL_VAS_USER2:
805 /* XXX Not sure howto check for MBLT */
806 /* Setup cycle types */
807 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
812 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
817 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
822 /* Setup data width */
823 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
824 case CA91CX42_LSI_CTL_VDW_D8:
827 case CA91CX42_LSI_CTL_VDW_D16:
830 case CA91CX42_LSI_CTL_VDW_D32:
833 case CA91CX42_LSI_CTL_VDW_D64:
841 static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
842 unsigned long long *vme_base, unsigned long long *size,
843 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
847 spin_lock(&image->lock);
849 retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
852 spin_unlock(&image->lock);
857 static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
858 void *buf, size_t count, loff_t offset)
861 void *addr = image->kern_base + offset;
862 unsigned int done = 0;
863 unsigned int count32;
868 spin_lock(&image->lock);
870 /* The following code handles VME address alignment problem
871 * in order to assure the maximal data width cycle.
872 * We cannot use memcpy_xxx directly here because it
873 * may cut data transfer in 8-bits cycles, thus making
874 * D16 cycle impossible.
875 * From the other hand, the bridge itself assures that
876 * maximal configured data cycle is used and splits it
877 * automatically for non-aligned addresses.
879 if ((int)addr & 0x1) {
880 *(u8 *)buf = ioread8(addr);
885 if ((int)addr & 0x2) {
886 if ((count - done) < 2) {
887 *(u8 *)(buf + done) = ioread8(addr + done);
891 *(u16 *)(buf + done) = ioread16(addr + done);
896 count32 = (count - done) & ~0x3;
898 memcpy_fromio(buf + done, addr + done, (unsigned int)count);
902 if ((count - done) & 0x2) {
903 *(u16 *)(buf + done) = ioread16(addr + done);
906 if ((count - done) & 0x1) {
907 *(u8 *)(buf + done) = ioread8(addr + done);
912 spin_unlock(&image->lock);
917 static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
918 void *buf, size_t count, loff_t offset)
921 void *addr = image->kern_base + offset;
922 unsigned int done = 0;
923 unsigned int count32;
928 spin_lock(&image->lock);
930 /* Here we apply for the same strategy we do in master_read
931 * function in order to assure D16 cycle when required.
933 if ((int)addr & 0x1) {
934 iowrite8(*(u8 *)buf, addr);
939 if ((int)addr & 0x2) {
940 if ((count - done) < 2) {
941 iowrite8(*(u8 *)(buf + done), addr + done);
945 iowrite16(*(u16 *)(buf + done), addr + done);
950 count32 = (count - done) & ~0x3;
952 memcpy_toio(addr + done, buf + done, count32);
956 if ((count - done) & 0x2) {
957 iowrite16(*(u16 *)(buf + done), addr + done);
960 if ((count - done) & 0x1) {
961 iowrite8(*(u8 *)(buf + done), addr + done);
967 spin_unlock(&image->lock);
972 static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
973 unsigned int mask, unsigned int compare, unsigned int swap,
976 u32 pci_addr, result;
978 struct ca91cx42_driver *bridge;
981 bridge = image->parent->driver_priv;
982 dev = image->parent->parent;
984 /* Find the PCI address that maps to the desired VME address */
987 /* Locking as we can only do one of these at a time */
988 mutex_lock(&bridge->vme_rmw);
991 spin_lock(&image->lock);
993 pci_addr = (u32)image->kern_base + offset;
995 /* Address must be 4-byte aligned */
996 if (pci_addr & 0x3) {
997 dev_err(dev, "RMW Address not 4-byte aligned\n");
1002 /* Ensure RMW Disabled whilst configuring */
1003 iowrite32(0, bridge->base + SCYC_CTL);
1005 /* Configure registers */
1006 iowrite32(mask, bridge->base + SCYC_EN);
1007 iowrite32(compare, bridge->base + SCYC_CMP);
1008 iowrite32(swap, bridge->base + SCYC_SWP);
1009 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
1012 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1014 /* Kick process off with a read to the required address. */
1015 result = ioread32(image->kern_base + offset);
1018 iowrite32(0, bridge->base + SCYC_CTL);
1021 spin_unlock(&image->lock);
1023 mutex_unlock(&bridge->vme_rmw);
1028 static int ca91cx42_dma_list_add(struct vme_dma_list *list,
1029 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1031 struct ca91cx42_dma_entry *entry, *prev;
1032 struct vme_dma_pci *pci_attr;
1033 struct vme_dma_vme *vme_attr;
1034 dma_addr_t desc_ptr;
1038 dev = list->parent->parent->parent;
1040 /* XXX descriptor must be aligned on 64-bit boundaries */
1041 entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
1042 if (entry == NULL) {
1043 dev_err(dev, "Failed to allocate memory for dma resource "
1049 /* Test descriptor alignment */
1050 if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
1051 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
1052 "required: %p\n", &entry->descriptor);
1057 memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));
1059 if (dest->type == VME_DMA_VME) {
1060 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
1061 vme_attr = dest->private;
1062 pci_attr = src->private;
1064 vme_attr = src->private;
1065 pci_attr = dest->private;
1068 /* Check we can do fulfill required attributes */
1069 if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1072 dev_err(dev, "Unsupported cycle type\n");
1077 if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1078 VME_PROG | VME_DATA)) != 0) {
1080 dev_err(dev, "Unsupported cycle type\n");
1085 /* Check to see if we can fulfill source and destination */
1086 if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1087 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1089 dev_err(dev, "Cannot perform transfer with this "
1090 "source-destination combination\n");
1095 /* Setup cycle types */
1096 if (vme_attr->cycle & VME_BLT)
1097 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1099 /* Setup data width */
1100 switch (vme_attr->dwidth) {
1102 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1105 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1108 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1111 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1114 dev_err(dev, "Invalid data width\n");
1118 /* Setup address space */
1119 switch (vme_attr->aspace) {
1121 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1124 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1127 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1130 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1133 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1136 dev_err(dev, "Invalid address space\n");
1141 if (vme_attr->cycle & VME_SUPER)
1142 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1143 if (vme_attr->cycle & VME_PROG)
1144 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1146 entry->descriptor.dtbc = count;
1147 entry->descriptor.dla = pci_attr->address;
1148 entry->descriptor.dva = vme_attr->address;
1149 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1152 list_add_tail(&entry->list, &list->entries);
1154 /* Fill out previous descriptors "Next Address" */
1155 if (entry->list.prev != &list->entries) {
1156 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1158 /* We need the bus address for the pointer */
1159 desc_ptr = virt_to_bus(&entry->descriptor);
1160 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1174 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1177 struct ca91cx42_driver *bridge;
1179 bridge = ca91cx42_bridge->driver_priv;
1181 tmp = ioread32(bridge->base + DGCS);
1183 if (tmp & CA91CX42_DGCS_ACT)
1189 static int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1191 struct vme_dma_resource *ctrlr;
1192 struct ca91cx42_dma_entry *entry;
1194 dma_addr_t bus_addr;
1197 struct ca91cx42_driver *bridge;
1199 ctrlr = list->parent;
1201 bridge = ctrlr->parent->driver_priv;
1202 dev = ctrlr->parent->parent;
1204 mutex_lock(&ctrlr->mtx);
1206 if (!(list_empty(&ctrlr->running))) {
1208 * XXX We have an active DMA transfer and currently haven't
1209 * sorted out the mechanism for "pending" DMA transfers.
1212 /* Need to add to pending here */
1213 mutex_unlock(&ctrlr->mtx);
1216 list_add(&list->list, &ctrlr->running);
1219 /* Get first bus address and write into registers */
1220 entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
1223 bus_addr = virt_to_bus(&entry->descriptor);
1225 mutex_unlock(&ctrlr->mtx);
1227 iowrite32(0, bridge->base + DTBC);
1228 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1230 /* Start the operation */
1231 val = ioread32(bridge->base + DGCS);
1233 /* XXX Could set VMEbus On and Off Counters here */
1234 val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1236 val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1237 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1238 CA91CX42_DGCS_PERR);
1240 iowrite32(val, bridge->base + DGCS);
1242 val |= CA91CX42_DGCS_GO;
1244 iowrite32(val, bridge->base + DGCS);
1246 wait_event_interruptible(bridge->dma_queue,
1247 ca91cx42_dma_busy(ctrlr->parent));
1250 * Read status register, this register is valid until we kick off a
1253 val = ioread32(bridge->base + DGCS);
1255 if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1256 CA91CX42_DGCS_PERR)) {
1258 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
1259 val = ioread32(bridge->base + DCTL);
1262 /* Remove list from running list */
1263 mutex_lock(&ctrlr->mtx);
1264 list_del(&list->list);
1265 mutex_unlock(&ctrlr->mtx);
1271 static int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1273 struct list_head *pos, *temp;
1274 struct ca91cx42_dma_entry *entry;
1276 /* detach and free each entry */
1277 list_for_each_safe(pos, temp, &list->entries) {
1279 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1287 * All 4 location monitors reside at the same base - this is therefore a
1288 * system wide configuration.
1290 * This does not enable the LM monitor - that should be done when the first
1291 * callback is attached and disabled when the last callback is removed.
1293 static int ca91cx42_lm_set(struct vme_lm_resource *lm,
1294 unsigned long long lm_base, vme_address_t aspace, vme_cycle_t cycle)
1296 u32 temp_base, lm_ctl = 0;
1298 struct ca91cx42_driver *bridge;
1301 bridge = lm->parent->driver_priv;
1302 dev = lm->parent->parent;
1304 /* Check the alignment of the location monitor */
1305 temp_base = (u32)lm_base;
1306 if (temp_base & 0xffff) {
1307 dev_err(dev, "Location monitor must be aligned to 64KB "
1312 mutex_lock(&lm->mtx);
1314 /* If we already have a callback attached, we can't move it! */
1315 for (i = 0; i < lm->monitors; i++) {
1316 if (bridge->lm_callback[i] != NULL) {
1317 mutex_unlock(&lm->mtx);
1318 dev_err(dev, "Location monitor callback attached, "
1326 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1329 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1332 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1335 mutex_unlock(&lm->mtx);
1336 dev_err(dev, "Invalid address space\n");
1341 if (cycle & VME_SUPER)
1342 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1343 if (cycle & VME_USER)
1344 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1345 if (cycle & VME_PROG)
1346 lm_ctl |= CA91CX42_LM_CTL_PGM;
1347 if (cycle & VME_DATA)
1348 lm_ctl |= CA91CX42_LM_CTL_DATA;
1350 iowrite32(lm_base, bridge->base + LM_BS);
1351 iowrite32(lm_ctl, bridge->base + LM_CTL);
1353 mutex_unlock(&lm->mtx);
1358 /* Get configuration of the callback monitor and return whether it is enabled
1361 static int ca91cx42_lm_get(struct vme_lm_resource *lm,
1362 unsigned long long *lm_base, vme_address_t *aspace, vme_cycle_t *cycle)
1364 u32 lm_ctl, enabled = 0;
1365 struct ca91cx42_driver *bridge;
1367 bridge = lm->parent->driver_priv;
1369 mutex_lock(&lm->mtx);
1371 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1372 lm_ctl = ioread32(bridge->base + LM_CTL);
1374 if (lm_ctl & CA91CX42_LM_CTL_EN)
1377 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1379 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1381 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1385 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1386 *cycle |= VME_SUPER;
1387 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1389 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1391 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1394 mutex_unlock(&lm->mtx);
1400 * Attach a callback to a specific location monitor.
1402 * Callback will be passed the monitor triggered.
1404 static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1405 void (*callback)(int))
1408 struct ca91cx42_driver *bridge;
1411 bridge = lm->parent->driver_priv;
1412 dev = lm->parent->parent;
1414 mutex_lock(&lm->mtx);
1416 /* Ensure that the location monitor is configured - need PGM or DATA */
1417 lm_ctl = ioread32(bridge->base + LM_CTL);
1418 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1419 mutex_unlock(&lm->mtx);
1420 dev_err(dev, "Location monitor not properly configured\n");
1424 /* Check that a callback isn't already attached */
1425 if (bridge->lm_callback[monitor] != NULL) {
1426 mutex_unlock(&lm->mtx);
1427 dev_err(dev, "Existing callback attached\n");
1431 /* Attach callback */
1432 bridge->lm_callback[monitor] = callback;
1434 /* Enable Location Monitor interrupt */
1435 tmp = ioread32(bridge->base + LINT_EN);
1436 tmp |= CA91CX42_LINT_LM[monitor];
1437 iowrite32(tmp, bridge->base + LINT_EN);
1439 /* Ensure that global Location Monitor Enable set */
1440 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1441 lm_ctl |= CA91CX42_LM_CTL_EN;
1442 iowrite32(lm_ctl, bridge->base + LM_CTL);
1445 mutex_unlock(&lm->mtx);
1451 * Detach a callback function forn a specific location monitor.
1453 static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1456 struct ca91cx42_driver *bridge;
1458 bridge = lm->parent->driver_priv;
1460 mutex_lock(&lm->mtx);
1462 /* Disable Location Monitor and ensure previous interrupts are clear */
1463 tmp = ioread32(bridge->base + LINT_EN);
1464 tmp &= ~CA91CX42_LINT_LM[monitor];
1465 iowrite32(tmp, bridge->base + LINT_EN);
1467 iowrite32(CA91CX42_LINT_LM[monitor],
1468 bridge->base + LINT_STAT);
1470 /* Detach callback */
1471 bridge->lm_callback[monitor] = NULL;
1473 /* If all location monitors disabled, disable global Location Monitor */
1474 if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1475 CA91CX42_LINT_LM3)) == 0) {
1476 tmp = ioread32(bridge->base + LM_CTL);
1477 tmp &= ~CA91CX42_LM_CTL_EN;
1478 iowrite32(tmp, bridge->base + LM_CTL);
1481 mutex_unlock(&lm->mtx);
1486 static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1489 struct ca91cx42_driver *bridge;
1491 bridge = ca91cx42_bridge->driver_priv;
1494 slot = ioread32(bridge->base + VCSR_BS);
1495 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1503 void *ca91cx42_alloc_consistent(struct device *parent, size_t size,
1506 struct pci_dev *pdev;
1508 /* Find pci_dev container of dev */
1509 pdev = container_of(parent, struct pci_dev, dev);
1511 return pci_alloc_consistent(pdev, size, dma);
1514 void ca91cx42_free_consistent(struct device *parent, size_t size, void *vaddr,
1517 struct pci_dev *pdev;
1519 /* Find pci_dev container of dev */
1520 pdev = container_of(parent, struct pci_dev, dev);
1522 pci_free_consistent(pdev, size, vaddr, dma);
1525 static int __init ca91cx42_init(void)
1527 return pci_register_driver(&ca91cx42_driver);
1531 * Configure CR/CSR space
1533 * Access to the CR/CSR can be configured at power-up. The location of the
1534 * CR/CSR registers in the CR/CSR address space is determined by the boards
1535 * Auto-ID or Geographic address. This function ensures that the window is
1536 * enabled at an offset consistent with the boards geopgraphic address.
1538 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1539 struct pci_dev *pdev)
1541 unsigned int crcsr_addr;
1543 struct ca91cx42_driver *bridge;
1545 bridge = ca91cx42_bridge->driver_priv;
1547 slot = ca91cx42_slot_get(ca91cx42_bridge);
1549 /* Write CSR Base Address if slot ID is supplied as a module param */
1551 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1553 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1555 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1560 /* Allocate mem for CR/CSR image */
1561 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1562 &bridge->crcsr_bus);
1563 if (bridge->crcsr_kernel == NULL) {
1564 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1569 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
1571 crcsr_addr = slot * (512 * 1024);
1572 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1574 tmp = ioread32(bridge->base + VCSR_CTL);
1575 tmp |= CA91CX42_VCSR_CTL_EN;
1576 iowrite32(tmp, bridge->base + VCSR_CTL);
1581 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1582 struct pci_dev *pdev)
1585 struct ca91cx42_driver *bridge;
1587 bridge = ca91cx42_bridge->driver_priv;
1589 /* Turn off CR/CSR space */
1590 tmp = ioread32(bridge->base + VCSR_CTL);
1591 tmp &= ~CA91CX42_VCSR_CTL_EN;
1592 iowrite32(tmp, bridge->base + VCSR_CTL);
1595 iowrite32(0, bridge->base + VCSR_TO);
1597 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1601 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1605 struct list_head *pos = NULL;
1606 struct vme_bridge *ca91cx42_bridge;
1607 struct ca91cx42_driver *ca91cx42_device;
1608 struct vme_master_resource *master_image;
1609 struct vme_slave_resource *slave_image;
1610 struct vme_dma_resource *dma_ctrlr;
1611 struct vme_lm_resource *lm;
1613 /* We want to support more than one of each bridge so we need to
1614 * dynamically allocate the bridge structure
1616 ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1618 if (ca91cx42_bridge == NULL) {
1619 dev_err(&pdev->dev, "Failed to allocate memory for device "
1625 ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1627 if (ca91cx42_device == NULL) {
1628 dev_err(&pdev->dev, "Failed to allocate memory for device "
1634 ca91cx42_bridge->driver_priv = ca91cx42_device;
1636 /* Enable the device */
1637 retval = pci_enable_device(pdev);
1639 dev_err(&pdev->dev, "Unable to enable device\n");
1644 retval = pci_request_regions(pdev, driver_name);
1646 dev_err(&pdev->dev, "Unable to reserve resources\n");
1650 /* map registers in BAR 0 */
1651 ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1653 if (!ca91cx42_device->base) {
1654 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1659 /* Check to see if the mapping worked out */
1660 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1661 if (data != PCI_VENDOR_ID_TUNDRA) {
1662 dev_err(&pdev->dev, "PCI_ID check failed\n");
1667 /* Initialize wait queues & mutual exclusion flags */
1668 init_waitqueue_head(&ca91cx42_device->dma_queue);
1669 init_waitqueue_head(&ca91cx42_device->iack_queue);
1670 mutex_init(&ca91cx42_device->vme_int);
1671 mutex_init(&ca91cx42_device->vme_rmw);
1673 ca91cx42_bridge->parent = &pdev->dev;
1674 strcpy(ca91cx42_bridge->name, driver_name);
1677 retval = ca91cx42_irq_init(ca91cx42_bridge);
1679 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1683 /* Add master windows to list */
1684 INIT_LIST_HEAD(&ca91cx42_bridge->master_resources);
1685 for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1686 master_image = kmalloc(sizeof(struct vme_master_resource),
1688 if (master_image == NULL) {
1689 dev_err(&pdev->dev, "Failed to allocate memory for "
1690 "master resource structure\n");
1694 master_image->parent = ca91cx42_bridge;
1695 spin_lock_init(&master_image->lock);
1696 master_image->locked = 0;
1697 master_image->number = i;
1698 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1699 VME_CRCSR | VME_USER1 | VME_USER2;
1700 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1701 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1702 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1703 memset(&master_image->bus_resource, 0,
1704 sizeof(struct resource));
1705 master_image->kern_base = NULL;
1706 list_add_tail(&master_image->list,
1707 &ca91cx42_bridge->master_resources);
1710 /* Add slave windows to list */
1711 INIT_LIST_HEAD(&ca91cx42_bridge->slave_resources);
1712 for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1713 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1715 if (slave_image == NULL) {
1716 dev_err(&pdev->dev, "Failed to allocate memory for "
1717 "slave resource structure\n");
1721 slave_image->parent = ca91cx42_bridge;
1722 mutex_init(&slave_image->mtx);
1723 slave_image->locked = 0;
1724 slave_image->number = i;
1725 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1728 /* Only windows 0 and 4 support A16 */
1729 if (i == 0 || i == 4)
1730 slave_image->address_attr |= VME_A16;
1732 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1733 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1734 list_add_tail(&slave_image->list,
1735 &ca91cx42_bridge->slave_resources);
1738 /* Add dma engines to list */
1739 INIT_LIST_HEAD(&ca91cx42_bridge->dma_resources);
1740 for (i = 0; i < CA91C142_MAX_DMA; i++) {
1741 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1743 if (dma_ctrlr == NULL) {
1744 dev_err(&pdev->dev, "Failed to allocate memory for "
1745 "dma resource structure\n");
1749 dma_ctrlr->parent = ca91cx42_bridge;
1750 mutex_init(&dma_ctrlr->mtx);
1751 dma_ctrlr->locked = 0;
1752 dma_ctrlr->number = i;
1753 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1755 INIT_LIST_HEAD(&dma_ctrlr->pending);
1756 INIT_LIST_HEAD(&dma_ctrlr->running);
1757 list_add_tail(&dma_ctrlr->list,
1758 &ca91cx42_bridge->dma_resources);
1761 /* Add location monitor to list */
1762 INIT_LIST_HEAD(&ca91cx42_bridge->lm_resources);
1763 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1765 dev_err(&pdev->dev, "Failed to allocate memory for "
1766 "location monitor resource structure\n");
1770 lm->parent = ca91cx42_bridge;
1771 mutex_init(&lm->mtx);
1775 list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources);
1777 ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1778 ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1779 ca91cx42_bridge->master_get = ca91cx42_master_get;
1780 ca91cx42_bridge->master_set = ca91cx42_master_set;
1781 ca91cx42_bridge->master_read = ca91cx42_master_read;
1782 ca91cx42_bridge->master_write = ca91cx42_master_write;
1783 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1784 ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1785 ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1786 ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1787 ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1788 ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1789 ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1790 ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1791 ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1792 ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1793 ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1794 ca91cx42_bridge->alloc_consistent = ca91cx42_alloc_consistent;
1795 ca91cx42_bridge->free_consistent = ca91cx42_free_consistent;
1797 data = ioread32(ca91cx42_device->base + MISC_CTL);
1798 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1799 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1800 dev_info(&pdev->dev, "Slot ID is %d\n",
1801 ca91cx42_slot_get(ca91cx42_bridge));
1803 if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
1804 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1806 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1809 retval = vme_register_bridge(ca91cx42_bridge);
1811 dev_err(&pdev->dev, "Chip Registration failed.\n");
1815 pci_set_drvdata(pdev, ca91cx42_bridge);
1820 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1822 /* resources are stored in link list */
1823 list_for_each(pos, &ca91cx42_bridge->lm_resources) {
1824 lm = list_entry(pos, struct vme_lm_resource, list);
1829 /* resources are stored in link list */
1830 list_for_each(pos, &ca91cx42_bridge->dma_resources) {
1831 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1836 /* resources are stored in link list */
1837 list_for_each(pos, &ca91cx42_bridge->slave_resources) {
1838 slave_image = list_entry(pos, struct vme_slave_resource, list);
1843 /* resources are stored in link list */
1844 list_for_each(pos, &ca91cx42_bridge->master_resources) {
1845 master_image = list_entry(pos, struct vme_master_resource,
1848 kfree(master_image);
1851 ca91cx42_irq_exit(ca91cx42_device, pdev);
1854 iounmap(ca91cx42_device->base);
1856 pci_release_regions(pdev);
1858 pci_disable_device(pdev);
1860 kfree(ca91cx42_device);
1862 kfree(ca91cx42_bridge);
1868 static void ca91cx42_remove(struct pci_dev *pdev)
1870 struct list_head *pos = NULL;
1871 struct vme_master_resource *master_image;
1872 struct vme_slave_resource *slave_image;
1873 struct vme_dma_resource *dma_ctrlr;
1874 struct vme_lm_resource *lm;
1875 struct ca91cx42_driver *bridge;
1876 struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1878 bridge = ca91cx42_bridge->driver_priv;
1882 iowrite32(0, bridge->base + LINT_EN);
1884 /* Turn off the windows */
1885 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1886 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1887 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1888 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1889 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1890 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1891 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1892 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1893 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1894 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1895 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1896 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1897 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1898 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1899 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1900 iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1902 vme_unregister_bridge(ca91cx42_bridge);
1904 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1906 /* resources are stored in link list */
1907 list_for_each(pos, &ca91cx42_bridge->lm_resources) {
1908 lm = list_entry(pos, struct vme_lm_resource, list);
1913 /* resources are stored in link list */
1914 list_for_each(pos, &ca91cx42_bridge->dma_resources) {
1915 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1920 /* resources are stored in link list */
1921 list_for_each(pos, &ca91cx42_bridge->slave_resources) {
1922 slave_image = list_entry(pos, struct vme_slave_resource, list);
1927 /* resources are stored in link list */
1928 list_for_each(pos, &ca91cx42_bridge->master_resources) {
1929 master_image = list_entry(pos, struct vme_master_resource,
1932 kfree(master_image);
1935 ca91cx42_irq_exit(bridge, pdev);
1937 iounmap(bridge->base);
1939 pci_release_regions(pdev);
1941 pci_disable_device(pdev);
1943 kfree(ca91cx42_bridge);
1946 static void __exit ca91cx42_exit(void)
1948 pci_unregister_driver(&ca91cx42_driver);
1951 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1952 module_param(geoid, int, 0);
1954 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1955 MODULE_LICENSE("GPL");
1957 module_init(ca91cx42_init);
1958 module_exit(ca91cx42_exit);