drivers/staging/sbe-2t3e3/2t3e3.h

   1 /*
   2  * SBE 2T3E3 synchronous serial card driver for Linux
   3  *
   4  * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * This code is based on a driver written by SBE Inc.
  11  */
  12
  13 #ifndef T3E3_H
  14 #define T3E3_H
  15
  16 #include <linux/hdlc.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/pci.h>
  20 #include <linux/io.h>
  21 #include "ctrl.h"
  22
  23 /**************************************************************
  24  *  21143
  25  **************************************************************/
  26
  27 /* CSR */
  28 #define SBE_2T3E3_21143_REG_BUS_MODE                                    0
  29 #define SBE_2T3E3_21143_REG_TRANSMIT_POLL_DEMAND                        1
  30 #define SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND                         2
  31 #define SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS                   3
  32 #define SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS                  4
  33 #define SBE_2T3E3_21143_REG_STATUS                                      5
  34 #define SBE_2T3E3_21143_REG_OPERATION_MODE                              6
  35 #define SBE_2T3E3_21143_REG_INTERRUPT_ENABLE                            7
  36 #define SBE_2T3E3_21143_REG_MISSED_FRAMES_AND_OVERFLOW_COUNTER          8
  37 #define SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT      9
  38 #define SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS                10
  39 #define SBE_2T3E3_21143_REG_GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL 11
  40 #define SBE_2T3E3_21143_REG_SIA_STATUS                                  12
  41 #define SBE_2T3E3_21143_REG_SIA_CONNECTIVITY                            13
  42 #define SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE                    14
  43 #define SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT                15
  44 #define SBE_2T3E3_21143_REG_MAX                                         16
  45
  46 /* CSR0 - BUS_MODE */
  47 #define SBE_2T3E3_21143_VAL_WRITE_AND_INVALIDATE_ENABLE         0x01000000
  48 #define SBE_2T3E3_21143_VAL_READ_LINE_ENABLE                    0x00800000
  49 #define SBE_2T3E3_21143_VAL_READ_MULTIPLE_ENABLE                0x00200000
  50 #define SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_200us    0x00020000
  51 #define SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_DISABLED 0x00000000
  52 #define SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_32                  0x0000c000
  53 #define SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_16                  0x00008000
  54 #define SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_8                   0x00004000
  55 #define SBE_2T3E3_21143_VAL_BUS_ARBITRATION_RR                  0x00000002
  56 #define SBE_2T3E3_21143_VAL_SOFTWARE_RESET                      0x00000001
  57
  58 /* CSR5 - STATUS */
  59 #define SBE_2T3E3_21143_VAL_GENERAL_PURPOSE_PORT_INTERRUPT      0x04000000
  60 #define SBE_2T3E3_21143_VAL_ERROR_BITS                          0x03800000
  61 #define SBE_2T3E3_21143_VAL_PARITY_ERROR                        0x00000000
  62 #define SBE_2T3E3_21143_VAL_MASTER_ABORT                        0x00800000
  63 #define SBE_2T3E3_21143_VAL_TARGET_ABORT                        0x01000000
  64 #define SBE_2T3E3_21143_VAL_TRANSMISSION_PROCESS_STATE          0x00700000
  65 #define SBE_2T3E3_21143_VAL_TX_STOPPED                          0x00000000
  66 #define SBE_2T3E3_21143_VAL_TX_SUSPENDED                        0x00600000
  67 #define SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STATE               0x000e0000
  68 #define SBE_2T3E3_21143_VAL_RX_STOPPED                          0x00000000
  69 #define SBE_2T3E3_21143_VAL_RX_SUSPENDED                        0x000a0000
  70 #define SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY            0x00010000
  71 #define SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY          0x00008000
  72 #define SBE_2T3E3_21143_VAL_EARLY_RECEIVE_INTERRUPT             0x00004000
  73 #define SBE_2T3E3_21143_VAL_FATAL_BUS_ERROR                     0x00002000
  74 #define SBE_2T3E3_21143_VAL_GENERAL_PURPOSE_TIMER_EXPIRED       0x00000800
  75 #define SBE_2T3E3_21143_VAL_EARLY_TRANSMIT_INTERRUPT            0x00000400
  76 #define SBE_2T3E3_21143_VAL_RECEIVE_WATCHDOG_TIMEOUT            0x00000200
  77 #define SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED             0x00000100
  78 #define SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE          0x00000080
  79 #define SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT                   0x00000040
  80 #define SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW                  0x00000020
  81 #define SBE_2T3E3_21143_VAL_TRANSMIT_JABBER_TIMEOUT             0x00000008
  82 #define SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE         0x00000004
  83 #define SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED            0x00000002
  84 #define SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT                  0x00000001
  85
  86 /* CSR6 - OPERATION_MODE */
  87 #define SBE_2T3E3_21143_VAL_SPECIAL_CAPTURE_EFFECT_ENABLE       0x80000000
  88 #define SBE_2T3E3_21143_VAL_RECEIVE_ALL                         0x40000000
  89 #define SBE_2T3E3_21143_VAL_MUST_BE_ONE                         0x02000000
  90 #define SBE_2T3E3_21143_VAL_SCRAMBLER_MODE                      0x01000000
  91 #define SBE_2T3E3_21143_VAL_PCS_FUNCTION                        0x00800000
  92 #define SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_10Mbs       0x00400000
  93 #define SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_100Mbs      0x00000000
  94 #define SBE_2T3E3_21143_VAL_STORE_AND_FORWARD                   0x00200000
  95 #define SBE_2T3E3_21143_VAL_HEARTBEAT_DISABLE                   0x00080000
  96 #define SBE_2T3E3_21143_VAL_PORT_SELECT                         0x00040000
  97 #define SBE_2T3E3_21143_VAL_CAPTURE_EFFECT_ENABLE               0x00020000
  98 #define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS              0x0000c000
  99 #define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1            0x00000000
 100 #define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_2            0x00004000
 101 #define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_3            0x00008000
 102 #define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_4            0x0000c000
 103 #define SBE_2T3E3_21143_VAL_TRANSMISSION_START                  0x00002000
 104 #define SBE_2T3E3_21143_VAL_OPERATING_MODE                      0x00000c00
 105 #define SBE_2T3E3_21143_VAL_LOOPBACK_OFF                        0x00000000
 106 #define SBE_2T3E3_21143_VAL_LOOPBACK_EXTERNAL                   0x00000800
 107 #define SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL                   0x00000400
 108 #define SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE                    0x00000200
 109 #define SBE_2T3E3_21143_VAL_PASS_ALL_MULTICAST                  0x00000080
 110 #define SBE_2T3E3_21143_VAL_PROMISCUOUS_MODE                    0x00000040
 111 #define SBE_2T3E3_21143_VAL_PASS_BAD_FRAMES                     0x00000008
 112 #define SBE_2T3E3_21143_VAL_RECEIVE_START                       0x00000002
 113
 114 /* CSR7 - INTERRUPT_ENABLE */
 115 #define SBE_2T3E3_21143_VAL_LINK_CHANGED_ENABLE                 0x08000000
 116 #define SBE_2T3E3_21143_VAL_GENERAL_PURPOSE_PORT_ENABLE         0x04000000
 117 #define SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY_ENABLE     0x00010000
 118 #define SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY_ENABLE   0x00008000
 119 #define SBE_2T3E3_21143_VAL_EARLY_RECEIVE_INTERRUPT_ENABLE      0x00004000
 120 #define SBE_2T3E3_21143_VAL_FATAL_BUS_ERROR_ENABLE              0x00002000
 121 #define SBE_2T3E3_21143_VAL_LINK_FAIL_ENABLE                    0x00001000
 122 #define SBE_2T3E3_21143_VAL_GENERAL_PURPOSE_TIMER_ENABLE        0x00000800
 123 #define SBE_2T3E3_21143_VAL_EARLY_TRANSMIT_INTERRUPT_ENABLE     0x00000400
 124 #define SBE_2T3E3_21143_VAL_RECEIVE_WATCHDOG_TIMEOUT_ENABLE     0x00000200
 125 #define SBE_2T3E3_21143_VAL_RECEIVE_STOPPED_ENABLE              0x00000100
 126 #define SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE_ENABLE   0x00000080
 127 #define SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT_ENABLE            0x00000040
 128 #define SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW_INTERRUPT_ENABLE 0x00000020
 129 #define SBE_2T3E3_21143_VAL_TRANSMIT_JABBER_TIMEOUT_ENABLE      0x00000008
 130 #define SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE  0x00000004
 131 #define SBE_2T3E3_21143_VAL_TRANSMIT_STOPPED_ENABLE             0x00000002
 132 #define SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT_ENABLE           0x00000001
 133
 134 /* CSR8 - MISSED_FRAMES_AND_OVERFLOW_COUNTER */
 135 #define SBE_2T3E3_21143_VAL_OVERFLOW_COUNTER_OVERFLOW           0x10000000
 136 #define SBE_2T3E3_21143_VAL_OVERFLOW_COUNTER                    0x0ffe0000
 137 #define SBE_2T3E3_21143_VAL_MISSED_FRAME_OVERFLOW               0x00010000
 138 #define SBE_2T3E3_21143_VAL_MISSED_FRAMES_COUNTER               0x0000ffff
 139
 140 /* CSR9 - BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT */
 141 #define SBE_2T3E3_21143_VAL_MII_MANAGEMENT_DATA_IN              0x00080000
 142 #define SBE_2T3E3_21143_VAL_MII_MANAGEMENT_READ_MODE            0x00040000
 143 #define SBE_2T3E3_21143_VAL_MII_MANAGEMENT_DATA_OUT             0x00020000
 144 #define SBE_2T3E3_21143_VAL_MII_MANAGEMENT_CLOCK                0x00010000
 145 #define SBE_2T3E3_21143_VAL_READ_OPERATION                      0x00004000
 146 #define SBE_2T3E3_21143_VAL_WRITE_OPERATION                     0x00002000
 147 #define SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT                     0x00001000
 148 #define SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT                   0x00000800
 149 #define SBE_2T3E3_21143_VAL_BOOT_ROM_DATA                       0x000000ff
 150 #define SBE_2T3E3_21143_VAL_SERIAL_ROM_DATA_OUT                 0x00000008
 151 #define SBE_2T3E3_21143_VAL_SERIAL_ROM_DATA_IN                  0x00000004
 152 #define SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK                    0x00000002
 153 #define SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT              0x00000001
 154
 155 /* CSR11 - GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL */
 156 #define SBE_2T3E3_21143_VAL_CYCLE_SIZE                          0x80000000
 157 #define SBE_2T3E3_21143_VAL_TRANSMIT_TIMER                      0x78000000
 158 #define SBE_2T3E3_21143_VAL_NUMBER_OF_TRANSMIT_PACKETS          0x07000000
 159 #define SBE_2T3E3_21143_VAL_RECEIVE_TIMER                       0x00f00000
 160 #define SBE_2T3E3_21143_VAL_NUMBER_OF_RECEIVE_PACKETS           0x000e0000
 161 #define SBE_2T3E3_21143_VAL_CONTINUOUS_MODE                     0x00010000
 162 #define SBE_2T3E3_21143_VAL_TIMER_VALUE                         0x0000ffff
 163
 164 /* CSR12 - SIA_STATUS */
 165 #define SBE_2T3E3_21143_VAL_10BASE_T_RECEIVE_PORT_ACTIVITY      0x00000200
 166 #define SBE_2T3E3_21143_VAL_AUI_RECEIVE_PORT_ACTIVITY           0x00000100
 167 #define SBE_2T3E3_21143_VAL_10Mbs_LINK_STATUS                   0x00000004
 168 #define SBE_2T3E3_21143_VAL_100Mbs_LINK_STATUS                  0x00000002
 169 #define SBE_2T3E3_21143_VAL_MII_RECEIVE_PORT_ACTIVITY           0x00000001
 170
 171 /* CSR13 - SIA_CONNECTIVITY */
 172 #define SBE_2T3E3_21143_VAL_10BASE_T_OR_AUI                     0x00000008
 173 #define SBE_2T3E3_21143_VAL_SIA_RESET                           0x00000001
 174
 175 /* CSR14 - SIA_TRANSMIT_AND_RECEIVE */
 176 #define SBE_2T3E3_21143_VAL_100BASE_TX_FULL_DUPLEX              0x00020000
 177 #define SBE_2T3E3_21143_VAL_COLLISION_DETECT_ENABLE             0x00000400
 178 #define SBE_2T3E3_21143_VAL_COLLISION_SQUELCH_ENABLE            0x00000200
 179 #define SBE_2T3E3_21143_VAL_RECEIVE_SQUELCH_ENABLE              0x00000100
 180 #define SBE_2T3E3_21143_VAL_LINK_PULSE_SEND_ENABLE              0x00000004
 181 #define SBE_2T3E3_21143_VAL_ENCODER_ENABLE                      0x00000001
 182
 183 /* CSR15 - SIA_AND_GENERAL_PURPOSE_PORT */
 184 #define SBE_2T3E3_21143_VAL_RECEIVE_WATCHDOG_DISABLE            0x00000010
 185 #define SBE_2T3E3_21143_VAL_AUI_BNC_MODE                        0x00000008
 186 #define SBE_2T3E3_21143_VAL_HOST_UNJAB                          0x00000002
 187 #define SBE_2T3E3_21143_VAL_JABBER_DISABLE                      0x00000001
 188
 189 /**************************************************************
 190  *  CPLD
 191  **************************************************************/
 192
 193 /* reg_map indexes */
 194 #define SBE_2T3E3_CPLD_REG_PCRA                         0
 195 #define SBE_2T3E3_CPLD_REG_PCRB                         1
 196 #define SBE_2T3E3_CPLD_REG_PLCR                         2
 197 #define SBE_2T3E3_CPLD_REG_PLTR                         3
 198 #define SBE_2T3E3_CPLD_REG_PPFR                         4
 199 #define SBE_2T3E3_CPLD_REG_BOARD_ID                     5
 200 #define SBE_2T3E3_CPLD_REG_FPGA_VERSION                 6
 201 #define SBE_2T3E3_CPLD_REG_FRAMER_BASE_ADDRESS          7
 202 #define SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT           8
 203 #define SBE_2T3E3_CPLD_REG_STATIC_RESET                 9
 204 #define SBE_2T3E3_CPLD_REG_PULSE_RESET                  10
 205 #define SBE_2T3E3_CPLD_REG_FPGA_RECONFIGURATION         11
 206 #define SBE_2T3E3_CPLD_REG_LEDR                         12
 207 #define SBE_2T3E3_CPLD_REG_PICSR                        13
 208 #define SBE_2T3E3_CPLD_REG_PIER                         14
 209 #define SBE_2T3E3_CPLD_REG_PCRC                         15
 210 #define SBE_2T3E3_CPLD_REG_PBWF                         16
 211 #define SBE_2T3E3_CPLD_REG_PBWL                         17
 212
 213 #define SBE_2T3E3_CPLD_REG_MAX                          18
 214
 215 /**********/
 216
 217 /* val_map indexes */
 218 #define SBE_2T3E3_CPLD_VAL_LIU_SELECT                   0
 219 #define SBE_2T3E3_CPLD_VAL_DAC_SELECT                   1
 220 #define SBE_2T3E3_CPLD_VAL_LOOP_TIMING_SOURCE           2
 221 #define SBE_2T3E3_CPLD_VAL_LIU_FRAMER_RESET             3
 222
 223 /* PCRA */
 224 #define SBE_2T3E3_CPLD_VAL_CRC32                                0x40
 225 #define SBE_2T3E3_CPLD_VAL_TRANSPARENT_MODE                     0x20
 226 #define SBE_2T3E3_CPLD_VAL_REAR_PANEL                           0x10
 227 #define SBE_2T3E3_CPLD_VAL_RAW_MODE                             0x08
 228 #define SBE_2T3E3_CPLD_VAL_ALT                                  0x04
 229 #define SBE_2T3E3_CPLD_VAL_LOOP_TIMING                          0x02
 230 #define SBE_2T3E3_CPLD_VAL_LOCAL_CLOCK_E3                       0x01
 231
 232 /* PCRB */
 233 #define SBE_2T3E3_CPLD_VAL_PAD_COUNT                            0x30
 234 #define SBE_2T3E3_CPLD_VAL_PAD_COUNT_1                          0x00
 235 #define SBE_2T3E3_CPLD_VAL_PAD_COUNT_2                          0x10
 236 #define SBE_2T3E3_CPLD_VAL_PAD_COUNT_3                          0x20
 237 #define SBE_2T3E3_CPLD_VAL_PAD_COUNT_4                          0x30
 238 #define SBE_2T3E3_CPLD_VAL_SCRAMBLER_TYPE                       0x02
 239 #define SBE_2T3E3_CPLD_VAL_SCRAMBLER_ENABLE                     0x01
 240
 241 /* PCRC */
 242 #define SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_NONE                 0x00
 243 #define SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_0                    0x01
 244 #define SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_1                    0x11
 245 #define SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_2                    0x21
 246
 247 /* PLTR */
 248 #define SBE_2T3E3_CPLD_VAL_LCV_COUNTER                          0xff
 249
 250 /* SCSR */
 251 #define SBE_2T3E3_CPLD_VAL_EEPROM_SELECT                        0x10
 252
 253 /* PICSR */
 254 #define SBE_2T3E3_CPLD_VAL_LOSS_OF_SIGNAL_THRESHOLD_LEVEL_1     0x80
 255 #define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_CHANGE        0x40
 256 #define SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ASSERTED     0x20
 257 #define SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ASSERTED       0x10
 258 #define SBE_2T3E3_CPLD_VAL_LCV_LIMIT_EXCEEDED                   0x08
 259 #define SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED                  0x04
 260 #define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED        0x02
 261 #define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED      0x01
 262
 263 /* PIER */
 264 #define SBE_2T3E3_CPLD_VAL_RECEIVE_LOS_CHANGE_ENABLE            0x40
 265 #define SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ENABLE       0x20
 266 #define SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ENABLE         0x10
 267 #define SBE_2T3E3_CPLD_VAL_LCV_INTERRUPT_ENABLE                 0x08
 268 #define SBE_2T3E3_CPLD_VAL_DMO_ENABLE                           0x04
 269 #define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_ENABLE          0x02
 270 #define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_ENABLE        0x01
 271
 272 /**************************************************************
 273  *  Framer
 274  **************************************************************/
 275
 276 /* reg_map indexes */
 277 /* common */
 278 #define SBE_2T3E3_FRAMER_REG_OPERATING_MODE                             0
 279 #define SBE_2T3E3_FRAMER_REG_IO_CONTROL                                 1
 280 #define SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE                     2
 281 #define SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS                     3
 282 #define SBE_2T3E3_FRAMER_REG_PMON_LCV_EVENT_COUNT_MSB                   28
 283 #define SBE_2T3E3_FRAMER_REG_PMON_LCV_EVENT_COUNT_LSB                   29
 284 #define SBE_2T3E3_FRAMER_REG_PMON_FRAMING_BIT_ERROR_EVENT_COUNT_MSB     30
 285 #define SBE_2T3E3_FRAMER_REG_PMON_FRAMING_BIT_ERROR_EVENT_COUNT_LSB     31
 286 #define SBE_2T3E3_FRAMER_REG_PMON_PARITY_ERROR_EVENT_COUNT_MSB          32
 287 #define SBE_2T3E3_FRAMER_REG_PMON_PARITY_ERROR_EVENT_COUNT_LSB          33
 288 #define SBE_2T3E3_FRAMER_REG_PMON_FEBE_EVENT_COUNT_MSB                  34
 289 #define SBE_2T3E3_FRAMER_REG_PMON_FEBE_EVENT_COUNT_LSB                  35
 290 #define SBE_2T3E3_FRAMER_REG_PMON_CP_BIT_ERROR_EVENT_COUNT_MSB          36
 291 #define SBE_2T3E3_FRAMER_REG_PMON_CP_BIT_ERROR_EVENT_COUNT_LSB          37
 292 #define SBE_2T3E3_FRAMER_REG_PMON_HOLDING_REGISTER                      38
 293 #define SBE_2T3E3_FRAMER_REG_ONE_SECOND_ERROR_STATUS                    39
 294 #define SBE_2T3E3_FRAMER_REG_LCV_ONE_SECOND_ACCUMULATOR_MSB             40
 295 #define SBE_2T3E3_FRAMER_REG_LCV_ONE_SECOND_ACCUMULATOR_LSB             41
 296 #define SBE_2T3E3_FRAMER_REG_FRAME_PARITY_ERROR_ONE_SECOND_ACCUMULATOR_MSB  42
 297 #define SBE_2T3E3_FRAMER_REG_FRAME_PARITY_ERROR_ONE_SECOND_ACCUMULATOR_LSB  43
 298 #define SBE_2T3E3_FRAMER_REG_FRAME_CP_BIT_ERROR_ONE_SECOND_ACCUMULATOR_MSB  44
 299 #define SBE_2T3E3_FRAMER_REG_FRAME_CP_BIT_ERROR_ONE_SECOND_ACCUMULATOR_LSB  45
 300 #define SBE_2T3E3_FRAMER_REG_LINE_INTERFACE_DRIVE                       46
 301 #define SBE_2T3E3_FRAMER_REG_LINE_INTERFACE_SCAN                        47
 302
 303 /* T3 */
 304 #define SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS                 4
 305 #define SBE_2T3E3_FRAMER_REG_T3_RX_STATUS                               5
 306 #define SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE                     6
 307 #define SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS                     7
 308 #define SBE_2T3E3_FRAMER_REG_T3_RX_SYNC_DETECT_ENABLE                   8
 309 #define SBE_2T3E3_FRAMER_REG_T3_RX_FEAC                                 10
 310 #define SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS         11
 311 #define SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL                         12
 312 #define SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_STATUS                          13
 313 #define SBE_2T3E3_FRAMER_REG_T3_TX_CONFIGURATION                        16
 314 #define SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS            17
 315 #define SBE_2T3E3_FRAMER_REG_T3_TX_FEAC                                 18
 316 #define SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_CONFIGURATION                   19
 317 #define SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS                          20
 318 #define SBE_2T3E3_FRAMER_REG_T3_TX_MBIT_MASK                            21
 319 #define SBE_2T3E3_FRAMER_REG_T3_TX_FBIT_MASK                            22
 320 #define SBE_2T3E3_FRAMER_REG_T3_TX_FBIT_MASK_2                          23
 321 #define SBE_2T3E3_FRAMER_REG_T3_TX_FBIT_MASK_3                          24
 322
 323 /* E3 */
 324 #define SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_1               4
 325 #define SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2               5
 326 #define SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1                   6
 327 #define SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2                   7
 328 #define SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1                   8
 329 #define SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2                   9
 330 #define SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL                         12
 331 #define SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_STATUS                          13
 332 #define SBE_2T3E3_FRAMER_REG_E3_RX_NR_BYTE                              14
 333 #define SBE_2T3E3_FRAMER_REG_E3_RX_SERVICE_BITS                         14
 334 #define SBE_2T3E3_FRAMER_REG_E3_RX_GC_BYTE                              15
 335 #define SBE_2T3E3_FRAMER_REG_E3_TX_CONFIGURATION                        16
 336 #define SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_CONFIGURATION                   19
 337 #define SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS                          19
 338 #define SBE_2T3E3_FRAMER_REG_E3_TX_GC_BYTE                              21
 339 #define SBE_2T3E3_FRAMER_REG_E3_TX_SERVICE_BITS                         21
 340 #define SBE_2T3E3_FRAMER_REG_E3_TX_MA_BYTE                              22
 341 #define SBE_2T3E3_FRAMER_REG_E3_TX_NR_BYTE                              23
 342 #define SBE_2T3E3_FRAMER_REG_E3_TX_FA1_ERROR_MASK                       25
 343 #define SBE_2T3E3_FRAMER_REG_E3_TX_FAS_ERROR_MASK_UPPER                 25
 344 #define SBE_2T3E3_FRAMER_REG_E3_TX_FA2_ERROR_MASK                       26
 345 #define SBE_2T3E3_FRAMER_REG_E3_TX_FAS_ERROR_MASK_LOWER                 26
 346 #define SBE_2T3E3_FRAMER_REG_E3_TX_BIP8_MASK                            27
 347 #define SBE_2T3E3_FRAMER_REG_E3_TX_BIP4_MASK                            27
 348
 349 #define SBE_2T3E3_FRAMER_REG_MAX                                        48
 350
 351 /**********/
 352
 353 /* OPERATING_MODE */
 354 #define SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE                0x80
 355 #define SBE_2T3E3_FRAMER_VAL_T3_E3_SELECT                       0x40
 356 #define SBE_2T3E3_FRAMER_VAL_INTERNAL_LOS_ENABLE                0x20
 357 #define SBE_2T3E3_FRAMER_VAL_RESET                              0x10
 358 #define SBE_2T3E3_FRAMER_VAL_INTERRUPT_ENABLE_RESET             0x08
 359 #define SBE_2T3E3_FRAMER_VAL_FRAME_FORMAT_SELECT                0x04
 360 #define SBE_2T3E3_FRAMER_VAL_TIMING_ASYNCH_TXINCLK              0x03
 361 #define SBE_2T3E3_FRAMER_VAL_E3_G751                            0x00
 362 #define SBE_2T3E3_FRAMER_VAL_E3_G832                            0x04
 363 #define SBE_2T3E3_FRAMER_VAL_T3_CBIT                            0x40
 364 #define SBE_2T3E3_FRAMER_VAL_T3_M13                             0x44
 365 #define SBE_2T3E3_FRAMER_VAL_LOOPBACK_ON                        0x80
 366 #define SBE_2T3E3_FRAMER_VAL_LOOPBACK_OFF                       0x00
 367
 368 /* IO_CONTROL */
 369 #define SBE_2T3E3_FRAMER_VAL_DISABLE_TX_LOSS_OF_CLOCK           0x80
 370 #define SBE_2T3E3_FRAMER_VAL_LOSS_OF_CLOCK_STATUS               0x40
 371 #define SBE_2T3E3_FRAMER_VAL_DISABLE_RX_LOSS_OF_CLOCK           0x20
 372 #define SBE_2T3E3_FRAMER_VAL_AMI_LINE_CODE                      0x10
 373 #define SBE_2T3E3_FRAMER_VAL_UNIPOLAR                           0x08
 374 #define SBE_2T3E3_FRAMER_VAL_TX_LINE_CLOCK_INVERT               0x04
 375 #define SBE_2T3E3_FRAMER_VAL_RX_LINE_CLOCK_INVERT               0x02
 376 #define SBE_2T3E3_FRAMER_VAL_REFRAME                            0x01
 377
 378 /* BLOCK_INTERRUPT_ENABLE */
 379 #define SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE                0x80
 380 #define SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE                0x02
 381 #define SBE_2T3E3_FRAMER_VAL_ONE_SECOND_INTERRUPT_ENABLE        0x01
 382
 383 /* BLOCK_INTERRUPT_STATUS */
 384 #define SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_STATUS                0x80
 385 #define SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_STATUS                0x02
 386 #define SBE_2T3E3_FRAMER_VAL_ONE_SECOND_INTERRUPT_STATUS        0x01
 387
 388 /**********/
 389
 390 /* T3_RX_CONFIGURATION_STATUS */
 391 #define SBE_2T3E3_FRAMER_VAL_T3_RX_AIS                          0x80
 392 #define SBE_2T3E3_FRAMER_VAL_T3_RX_LOS                          0x40
 393 #define SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE                         0x20
 394 #define SBE_2T3E3_FRAMER_VAL_T3_RX_OOF                          0x10
 395 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FRAMING_ON_PARITY            0x04
 396 #define SBE_2T3E3_FRAMER_VAL_T3_RX_F_SYNC_ALGO                  0x02
 397 #define SBE_2T3E3_FRAMER_VAL_T3_RX_M_SYNC_ALGO                  0x01
 398
 399 /* T3_RX_STATUS */
 400 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FERF                         0x10
 401 #define SBE_2T3E3_FRAMER_VAL_T3_RX_AIC                          0x04
 402 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FEBE                         0x07
 403
 404 /* T3_RX_INTERRUPT_ENABLE */
 405 #define SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_ENABLE 0x80
 406 #define SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE         0x40
 407 #define SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_ENABLE         0x20
 408 #define SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_ENABLE        0x10
 409 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_ENABLE        0x08
 410 #define SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_ENABLE         0x04
 411 #define SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE         0x02
 412 #define SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_ENABLE       0x01
 413
 414 /* T3_RX_INTERRUPT_STATUS */
 415 #define SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_STATUS 0x80
 416 #define SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_STATUS         0x40
 417 #define SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_STATUS         0x20
 418 #define SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_STATUS        0x10
 419 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_STATUS        0x08
 420 #define SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_STATUS         0x04
 421 #define SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_STATUS         0x02
 422 #define SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_STATUS       0x01
 423
 424 /* T3_RX_FEAC_INTERRUPT_ENABLE_STATUS */
 425 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID                   0x10
 426 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE 0x08
 427 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_STATUS 0x04
 428 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE  0x02
 429 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_STATUS  0x01
 430
 431 /* T3_RX_LAPD_CONTROL */
 432 #define SBE_2T3E3_FRAMER_VAL_T3_RX_LAPD_ENABLE                  0x04
 433 #define SBE_2T3E3_FRAMER_VAL_T3_RX_LAPD_INTERRUPT_ENABLE        0x02
 434 #define SBE_2T3E3_FRAMER_VAL_T3_RX_LAPD_INTERRUPT_STATUS        0x01
 435
 436 /* T3_RX_LAPD_STATUS */
 437 #define SBE_2T3E3_FRAMER_VAL_T3_RX_ABORT                        0x40
 438 #define SBE_2T3E3_FRAMER_VAL_T3_RX_LAPD_TYPE                    0x30
 439 #define SBE_2T3E3_FRAMER_VAL_T3_RX_CR_TYPE                      0x08
 440 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FCS_ERROR                    0x04
 441 #define SBE_2T3E3_FRAMER_VAL_T3_RX_END_OF_MESSAGE               0x02
 442 #define SBE_2T3E3_FRAMER_VAL_T3_RX_FLAG_PRESENT                 0x01
 443
 444 /* T3_TX_CONFIGURATION */
 445 #define SBE_2T3E3_FRAMER_VAL_T3_TX_YELLOW_ALARM                 0x80
 446 #define SBE_2T3E3_FRAMER_VAL_T3_TX_X_BIT                        0x40
 447 #define SBE_2T3E3_FRAMER_VAL_T3_TX_IDLE                         0x20
 448 #define SBE_2T3E3_FRAMER_VAL_T3_TX_AIS                          0x10
 449 #define SBE_2T3E3_FRAMER_VAL_T3_TX_LOS                          0x08
 450 #define SBE_2T3E3_FRAMER_VAL_T3_TX_FERF_ON_LOS                  0x04
 451 #define SBE_2T3E3_FRAMER_VAL_T3_TX_FERF_ON_OOF                  0x02
 452 #define SBE_2T3E3_FRAMER_VAL_T3_TX_FERF_ON_AIS                  0x01
 453
 454 /* T3_TX_FEAC_CONFIGURATION_STATUS */
 455 #define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_INTERRUPT_ENABLE        0x10
 456 #define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_INTERRUPT_STATUS        0x08
 457 #define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_ENABLE                  0x04
 458 #define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_GO                      0x02
 459 #define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_BUSY                    0x01
 460
 461 /* T3_TX_LAPD_STATUS */
 462 #define SBE_2T3E3_FRAMER_VAL_T3_TX_DL_START                     0x08
 463 #define SBE_2T3E3_FRAMER_VAL_T3_TX_DL_BUSY                      0x04
 464 #define SBE_2T3E3_FRAMER_VAL_T3_TX_LAPD_INTERRUPT_ENABLE        0x02
 465 #define SBE_2T3E3_FRAMER_VAL_T3_TX_LAPD_INTERRUPT_STATUS        0x01
 466
 467 /**********/
 468
 469 /* E3_RX_CONFIGURATION_STATUS_1 */
 470 #define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_TYPE                 0xe0
 471 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_ALGO                    0x10
 472 #define SBE_2T3E3_FRAMER_VAL_E3_RX_T_MARK_ALGO                  0x08
 473 #define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_EXPECTED             0x07
 474 #define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP4                         0x01
 475
 476 /* E3_RX_CONFIGURATION_STATUS_2 */
 477 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_ALGO                     0x80
 478 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LOF                          0x40
 479 #define SBE_2T3E3_FRAMER_VAL_E3_RX_OOF                          0x20
 480 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LOS                          0x10
 481 #define SBE_2T3E3_FRAMER_VAL_E3_RX_AIS                          0x08
 482 #define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_UNSTABLE             0x04
 483 #define SBE_2T3E3_FRAMER_VAL_E3_RX_T_MARK                       0x02
 484 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FERF                         0x01
 485
 486 /* E3_RX_INTERRUPT_ENABLE_1 */
 487 #define SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_ENABLE        0x10
 488 #define SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE         0x08
 489 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_ENABLE         0x04
 490 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE         0x02
 491 #define SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_ENABLE         0x01
 492
 493 /* E3_RX_INTERRUPT_ENABLE_2 */
 494 #define SBE_2T3E3_FRAMER_VAL_E3_RX_TTB_CHANGE_INTERRUPT_ENABLE  0x40
 495 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE        0x10
 496 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE        0x08
 497 #define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP8_ERROR_INTERRUPT_ENABLE  0x04
 498 #define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP4_ERROR_INTERRUPT_ENABLE  0x04
 499 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE 0x02
 500 #define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_MISMATCH_INTERRUPT_ENABLE 0x01
 501
 502 /* E3_RX_INTERRUPT_STATUS_1 */
 503 #define SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_STATUS        0x10
 504 #define SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_STATUS         0x08
 505 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_STATUS         0x04
 506 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_STATUS         0x02
 507 #define SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_STATUS         0x01
 508
 509 /* E3_RX_INTERRUPT_STATUS_2 */
 510 #define SBE_2T3E3_FRAMER_VAL_E3_RX_TTB_CHANGE_INTERRUPT_STATUS  0x40
 511 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_STATUS        0x10
 512 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_STATUS        0x08
 513 #define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP8_ERROR_INTERRUPT_STATUS  0x04
 514 #define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP4_ERROR_INTERRUPT_STATUS  0x04
 515 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_STATUS 0x02
 516 #define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_MISMATCH_INTERRUPT_STATUS 0x01
 517
 518 /* E3_RX_LAPD_CONTROL */
 519 #define SBE_2T3E3_FRAMER_VAL_E3_RX_DL_FROM_NR                   0x08
 520 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LAPD_ENABLE                  0x04
 521 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LAPD_INTERRUPT_ENABLE        0x02
 522 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LAPD_INTERRUPT_STATUS        0x01
 523
 524 /* E3_RX_LAPD_STATUS */
 525 #define SBE_2T3E3_FRAMER_VAL_E3_RX_ABORT                        0x40
 526 #define SBE_2T3E3_FRAMER_VAL_E3_RX_LAPD_TYPE                    0x30
 527 #define SBE_2T3E3_FRAMER_VAL_E3_RX_CR_TYPE                      0x08
 528 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FCS_ERROR                    0x04
 529 #define SBE_2T3E3_FRAMER_VAL_E3_RX_END_OF_MESSAGE               0x02
 530 #define SBE_2T3E3_FRAMER_VAL_E3_RX_FLAG_PRESENT                 0x01
 531
 532 /* E3_TX_CONFIGURATION */
 533 #define SBE_2T3E3_FRAMER_VAL_E3_TX_BIP4_ENABLE                  0x80
 534 #define SBE_2T3E3_FRAMER_VAL_E3_TX_A_SOURCE_SELECT              0x60
 535 #define SBE_2T3E3_FRAMER_VAL_E3_TX_DL_IN_NR                     0x10
 536 #define SBE_2T3E3_FRAMER_VAL_E3_TX_N_SOURCE_SELECT              0x18
 537 #define SBE_2T3E3_FRAMER_VAL_E3_TX_AIS_ENABLE                   0x04
 538 #define SBE_2T3E3_FRAMER_VAL_E3_TX_LOS_ENABLE                   0x02
 539 #define SBE_2T3E3_FRAMER_VAL_E3_TX_MA_RX                        0x01
 540 #define SBE_2T3E3_FRAMER_VAL_E3_TX_FAS_SOURCE_SELECT            0x01
 541
 542 /* E3_TX_LAPD_CONFIGURATION */
 543 #define SBE_2T3E3_FRAMER_VAL_E3_TX_AUTO_RETRANSMIT              0x08
 544 #define SBE_2T3E3_FRAMER_VAL_E3_TX_LAPD_MESSAGE_LENGTH          0x02
 545 #define SBE_2T3E3_FRAMER_VAL_E3_TX_LAPD_ENABLE                  0x01
 546
 547 /* E3_TX_LAPD_STATUS_INTERRUPT */
 548 #define SBE_2T3E3_FRAMER_VAL_E3_TX_DL_START                     0x08
 549 #define SBE_2T3E3_FRAMER_VAL_E3_TX_DL_BUSY                      0x04
 550 #define SBE_2T3E3_FRAMER_VAL_E3_TX_LAPD_INTERRUPT_ENABLE        0x02
 551 #define SBE_2T3E3_FRAMER_VAL_E3_TX_LAPD_INTERRUPT_STATUS        0x01
 552
 553
 554
 555
 556
 557
 558 /**************************************************************
 559  *  LIU
 560  **************************************************************/
 561
 562 /* reg_map indexes */
 563 #define SBE_2T3E3_LIU_REG_REG0                  0
 564 #define SBE_2T3E3_LIU_REG_REG1                  1
 565 #define SBE_2T3E3_LIU_REG_REG2                  2
 566 #define SBE_2T3E3_LIU_REG_REG3                  3
 567 #define SBE_2T3E3_LIU_REG_REG4                  4
 568
 569 #define SBE_2T3E3_LIU_REG_MAX                   5
 570
 571 /**********/
 572
 573 /* REG0 */
 574 #define SBE_2T3E3_LIU_VAL_RECEIVE_LOSS_OF_LOCK_STATUS           0x10
 575 #define SBE_2T3E3_LIU_VAL_RECEIVE_LOSS_OF_SIGNAL_STATUS         0x08
 576 #define SBE_2T3E3_LIU_VAL_ANALOG_LOSS_OF_SIGNAL_STATUS          0x04
 577 #define SBE_2T3E3_LIU_VAL_DIGITAL_LOSS_OF_SIGNAL_STATUS         0x02
 578 #define SBE_2T3E3_LIU_VAL_DMO_STATUS                            0x01
 579
 580 /* REG1 */
 581 #define SBE_2T3E3_LIU_VAL_TRANSMITTER_OFF                       0x10
 582 #define SBE_2T3E3_LIU_VAL_TRANSMIT_ALL_ONES                     0x08
 583 #define SBE_2T3E3_LIU_VAL_TRANSMIT_CLOCK_INVERT                 0x04
 584 #define SBE_2T3E3_LIU_VAL_TRANSMIT_LEVEL_SELECT                 0x02
 585 #define SBE_2T3E3_LIU_VAL_TRANSMIT_BINARY_DATA                  0x01
 586
 587 /* REG2 */
 588 #define SBE_2T3E3_LIU_VAL_DECODER_DISABLE                       0x10
 589 #define SBE_2T3E3_LIU_VAL_ENCODER_DISABLE                       0x08
 590 #define SBE_2T3E3_LIU_VAL_ANALOG_LOSS_OF_SIGNAL_DISABLE         0x04
 591 #define SBE_2T3E3_LIU_VAL_DIGITAL_LOSS_OF_SIGNAL_DISABLE        0x02
 592 #define SBE_2T3E3_LIU_VAL_RECEIVE_EQUALIZATION_DISABLE          0x01
 593
 594 /* REG3 */
 595 #define SBE_2T3E3_LIU_VAL_RECEIVE_BINARY_DATA                   0x10
 596 #define SBE_2T3E3_LIU_VAL_RECOVERED_DATA_MUTING                 0x08
 597 #define SBE_2T3E3_LIU_VAL_RECEIVE_CLOCK_OUTPUT_2                0x04
 598 #define SBE_2T3E3_LIU_VAL_INVERT_RECEIVE_CLOCK_2                0x02
 599 #define SBE_2T3E3_LIU_VAL_INVERT_RECEIVE_CLOCK_1                0x01
 600
 601 /* REG4 */
 602 #define SBE_2T3E3_LIU_VAL_T3_MODE_SELECT                        0x00
 603 #define SBE_2T3E3_LIU_VAL_E3_MODE_SELECT                        0x04
 604 #define SBE_2T3E3_LIU_VAL_LOCAL_LOOPBACK                        0x02
 605 #define SBE_2T3E3_LIU_VAL_REMOTE_LOOPBACK                       0x01
 606 #define SBE_2T3E3_LIU_VAL_LOOPBACK_OFF                          0x00
 607 #define SBE_2T3E3_LIU_VAL_LOOPBACK_REMOTE                       0x01
 608 #define SBE_2T3E3_LIU_VAL_LOOPBACK_ANALOG                       0x02
 609 #define SBE_2T3E3_LIU_VAL_LOOPBACK_DIGITAL                      0x03
 610
 611 /**********************************************************************
 612  *
 613  * descriptor list and data buffer
 614  *
 615  **********************************************************************/
 616 typedef struct {
 617         u32 rdes0;
 618         u32 rdes1;
 619         u32 rdes2;
 620         u32 rdes3;
 621 } t3e3_rx_desc_t;
 622
 623 #define SBE_2T3E3_RX_DESC_RING_SIZE                     64
 624
 625 /* RDES0 */
 626 #define SBE_2T3E3_RX_DESC_21143_OWN                     0X80000000
 627 #define SBE_2T3E3_RX_DESC_FRAME_LENGTH                  0x3fff0000
 628 #define SBE_2T3E3_RX_DESC_FRAME_LENGTH_SHIFT            16
 629 #define SBE_2T3E3_RX_DESC_ERROR_SUMMARY                 0x00008000
 630 #define SBE_2T3E3_RX_DESC_DESC_ERROR                    0x00004000
 631 #define SBE_2T3E3_RX_DESC_DATA_TYPE                     0x00003000
 632 #define SBE_2T3E3_RX_DESC_RUNT_FRAME                    0x00000800
 633 #define SBE_2T3E3_RX_DESC_FIRST_DESC                    0x00000200
 634 #define SBE_2T3E3_RX_DESC_LAST_DESC                     0x00000100
 635 #define SBE_2T3E3_RX_DESC_FRAME_TOO_LONG                0x00000080
 636 #define SBE_2T3E3_RX_DESC_COLLISION_SEEN                0x00000040
 637 #define SBE_2T3E3_RX_DESC_FRAME_TYPE                    0x00000020
 638 #define SBE_2T3E3_RX_DESC_RECEIVE_WATCHDOG              0x00000010
 639 #define SBE_2T3E3_RX_DESC_MII_ERROR                     0x00000008
 640 #define SBE_2T3E3_RX_DESC_DRIBBLING_BIT                 0x00000004
 641 #define SBE_2T3E3_RX_DESC_CRC_ERROR                     0x00000002
 642
 643 /* RDES1 */
 644 #define SBE_2T3E3_RX_DESC_END_OF_RING                   0x02000000
 645 #define SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED        0x01000000
 646 #define SBE_2T3E3_RX_DESC_BUFFER_2_SIZE                 0x003ff800
 647 #define SBE_2T3E3_RX_DESC_BUFFER_1_SIZE                 0x000007ff
 648
 649 /*********************/
 650
 651 typedef struct {
 652         u32 tdes0;
 653         u32 tdes1;
 654         u32 tdes2;
 655         u32 tdes3;
 656 } t3e3_tx_desc_t;
 657
 658 #define SBE_2T3E3_TX_DESC_RING_SIZE                     256
 659
 660 /* TDES0 */
 661 #define SBE_2T3E3_TX_DESC_21143_OWN                     0x80000000
 662 #define SBE_2T3E3_TX_DESC_ERROR_SUMMARY                 0x00008000
 663 #define SBE_2T3E3_TX_DESC_TRANSMIT_JABBER_TIMEOUT       0x00004000
 664 #define SBE_2T3E3_TX_DESC_LOSS_OF_CARRIER               0x00000800
 665 #define SBE_2T3E3_TX_DESC_NO_CARRIER                    0x00000400
 666 #define SBE_2T3E3_TX_DESC_LINK_FAIL_REPORT              0x00000004
 667 #define SBE_2T3E3_TX_DESC_UNDERFLOW_ERROR               0x00000002
 668 #define SBE_2T3E3_TX_DESC_DEFFERED                      0x00000001
 669
 670 /* TDES1 */
 671 #define SBE_2T3E3_TX_DESC_INTERRUPT_ON_COMPLETION       0x80000000
 672 #define SBE_2T3E3_TX_DESC_LAST_SEGMENT                  0x40000000
 673 #define SBE_2T3E3_TX_DESC_FIRST_SEGMENT                 0x20000000
 674 #define SBE_2T3E3_TX_DESC_CRC_DISABLE                   0x04000000
 675 #define SBE_2T3E3_TX_DESC_END_OF_RING                   0x02000000
 676 #define SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED        0x01000000
 677 #define SBE_2T3E3_TX_DESC_DISABLE_PADDING               0x00800000
 678 #define SBE_2T3E3_TX_DESC_BUFFER_2_SIZE                 0x003ff800
 679 #define SBE_2T3E3_TX_DESC_BUFFER_1_SIZE                 0x000007ff
 680
 681
 682 #define SBE_2T3E3_MTU                                   1600
 683 #define SBE_2T3E3_CRC16_LENGTH                          2
 684 #define SBE_2T3E3_CRC32_LENGTH                          4
 685
 686 #define MCLBYTES (SBE_2T3E3_MTU + 128)
 687
 688 struct channel {
 689         struct pci_dev *pdev;
 690         struct net_device *dev;
 691         struct card *card;
 692         unsigned long addr;     /* DECchip */
 693
 694         int leds;
 695
 696         /* pci specific */
 697         struct {
 698                 u32 slot;           /* should be 0 or 1 */
 699                 u32 command;
 700                 u8 cache_size;
 701         } h;
 702
 703         /* statistics */
 704         t3e3_stats_t s;
 705
 706         /* running */
 707         struct {
 708                 u32 flags;
 709         } r;
 710
 711         /* parameters */
 712         t3e3_param_t p;
 713
 714         u32 liu_regs[SBE_2T3E3_LIU_REG_MAX];       /* LIU registers */
 715         u32 framer_regs[SBE_2T3E3_FRAMER_REG_MAX]; /* Framer registers */
 716
 717         /* Ethernet Controller */
 718         struct {
 719                 u_int16_t card_serial_number[3];
 720
 721                 u32 reg[SBE_2T3E3_21143_REG_MAX]; /* registers i.e. CSR */
 722
 723                 u32 interrupt_enable_mask;
 724
 725                 /* receive chain/ring */
 726                 t3e3_rx_desc_t *rx_ring;
 727                 struct sk_buff *rx_data[SBE_2T3E3_RX_DESC_RING_SIZE];
 728                 u32 rx_ring_current_read;
 729
 730                 /* transmit chain/ring */
 731                 t3e3_tx_desc_t *tx_ring;
 732                 struct sk_buff *tx_data[SBE_2T3E3_TX_DESC_RING_SIZE];
 733                 u32 tx_ring_current_read;
 734                 u32 tx_ring_current_write;
 735                 int tx_full;
 736                 int tx_free_cnt;
 737                 spinlock_t tx_lock;
 738         } ether;
 739
 740         int32_t interrupt_active;
 741         int32_t rcv_count;
 742 };
 743
 744 struct card {
 745         spinlock_t bootrom_lock;
 746         unsigned long bootrom_addr;
 747         struct timer_list timer; /* for updating LEDs */
 748         struct channel channels[0];
 749 };
 750
 751 #define SBE_2T3E3_FLAG_NETWORK_UP               0x00000001
 752 #define SBE_2T3E3_FLAG_NO_ERROR_MESSAGES        0x00000002
 753
 754 extern const u32 cpld_reg_map[][2];
 755 extern const u32 cpld_val_map[][2];
 756 extern const u32 t3e3_framer_reg_map[];
 757 extern const u32 t3e3_liu_reg_map[];
 758
 759 void t3e3_init(struct channel *);
 760 void t3e3_if_up(struct channel *);
 761 void t3e3_if_down(struct channel *);
 762 int t3e3_if_start_xmit(struct sk_buff *skb, struct net_device *dev);
 763 void t3e3_if_config(struct channel *, u32, char *,
 764                     t3e3_resp_t *, int *);
 765 void t3e3_set_frame_type(struct channel *, u32);
 766 u32 t3e3_eeprom_read_word(struct channel *, u32);
 767 void t3e3_read_card_serial_number(struct channel *);
 768
 769 /* interrupt handlers */
 770 irqreturn_t t3e3_intr(int irq, void *dev_instance);
 771 void dc_intr(struct channel *);
 772 void dc_intr_rx(struct channel *);
 773 void dc_intr_tx(struct channel *);
 774 void dc_intr_tx_underflow(struct channel *);
 775 void exar7250_intr(struct channel *);
 776 void exar7250_E3_intr(struct channel *, u32);
 777 void exar7250_T3_intr(struct channel *, u32);
 778
 779 /* Ethernet controller */
 780 u32 bootrom_read(struct channel *, u32);
 781 void bootrom_write(struct channel *, u32, u32);
 782 void dc_init(struct channel *);
 783 void dc_start(struct channel *);
 784 void dc_stop(struct channel *);
 785 void dc_start_intr(struct channel *);
 786 void dc_stop_intr(struct channel *);
 787 void dc_reset(struct channel *);
 788 void dc_restart(struct channel *);
 789 void dc_receiver_onoff(struct channel *, u32);
 790 void dc_transmitter_onoff(struct channel *, u32);
 791 void dc_set_loopback(struct channel *, u32);
 792 u32 dc_init_descriptor_list(struct channel *);
 793 void dc_clear_descriptor_list(struct channel *);
 794 void dc_drop_descriptor_list(struct channel *);
 795 void dc_set_output_port(struct channel *);
 796 void t3e3_sc_init(struct channel *);
 797
 798 /* CPLD */
 799 void cpld_init(struct channel *sc);
 800 u32 cpld_read(struct channel *sc, u32 reg);
 801 void cpld_set_crc(struct channel *, u32);
 802 void cpld_start_intr(struct channel *);
 803 void cpld_stop_intr(struct channel *);
 804 #if 0
 805 void cpld_led_onoff(struct channel *, u32, u32, u32, u32);
 806 #endif
 807 void cpld_set_clock(struct channel *sc, u32 mode);
 808 void cpld_set_scrambler(struct channel *, u32);
 809 void cpld_select_panel(struct channel *, u32);
 810 void cpld_set_frame_mode(struct channel *, u32);
 811 void cpld_set_frame_type(struct channel *, u32);
 812 void cpld_set_pad_count(struct channel *, u32);
 813 void cpld_set_fractional_mode(struct channel *, u32, u32, u32);
 814 void cpld_LOS_update(struct channel *);
 815
 816 /* Framer */
 817 extern u32 exar7250_read(struct channel *, u32);
 818 extern void exar7250_write(struct channel *, u32, u32);
 819 void exar7250_init(struct channel *);
 820 void exar7250_start_intr(struct channel *, u32);
 821 void exar7250_stop_intr(struct channel *, u32);
 822 void exar7250_set_frame_type(struct channel *, u32);
 823 void exar7250_set_loopback(struct channel *, u32);
 824 void exar7250_unipolar_onoff(struct channel *, u32);
 825
 826 /* LIU */
 827 u32 exar7300_read(struct channel *, u32);
 828 void exar7300_write(struct channel *, u32, u32);
 829 void exar7300_init(struct channel *);
 830 void exar7300_line_build_out_onoff(struct channel *, u32);
 831 void exar7300_set_frame_type(struct channel *, u32);
 832 void exar7300_set_loopback(struct channel *, u32);
 833 void exar7300_transmit_all_ones_onoff(struct channel *, u32);
 834 void exar7300_receive_equalization_onoff(struct channel *, u32);
 835 void exar7300_unipolar_onoff(struct channel *, u32);
 836
 837 void update_led(struct channel *, int);
 838 int setup_device(struct net_device *dev, struct channel *sc);
 839
 840 static inline int has_two_ports(struct pci_dev *pdev)
 841 {
 842         return pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0;
 843 }
 844
 845 #define dev_to_priv(dev) (*(struct channel **) ((hdlc_device*)(dev) + 1))
 846
 847 static inline u32 dc_read(unsigned long addr, u32 reg)
 848 {
 849         return inl(addr + (reg << 3));
 850 }
 851
 852 static inline void dc_write(unsigned long addr, u32 reg, u32 val)
 853 {
 854         outl(val, addr + (reg << 3));
 855 }
 856
 857 static inline void dc_set_bits(unsigned long addr, u32 reg, u32 bits)
 858 {
 859         dc_write(addr, reg, dc_read(addr, reg) | bits);
 860 }
 861
 862 static inline void dc_clear_bits(unsigned long addr, u32 reg, u32 bits)
 863 {
 864         dc_write(addr, reg, dc_read(addr, reg) & ~bits);
 865 }
 866
 867 #define CPLD_MAP_REG(reg, sc)   (cpld_reg_map[(reg)][(sc)->h.slot])
 868
 869 static inline void cpld_write(struct channel *channel, unsigned reg, u32 val)
 870 {
 871         unsigned long flags;
 872         spin_lock_irqsave(&channel->card->bootrom_lock, flags);
 873         bootrom_write(channel, CPLD_MAP_REG(reg, channel), val);
 874         spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
 875 }
 876
 877 #define exar7250_set_bit(sc, reg, bit)                  \
 878         exar7250_write((sc), (reg),                     \
 879                        exar7250_read(sc, reg) | (bit))
 880
 881 #define exar7250_clear_bit(sc, reg, bit)                \
 882         exar7250_write((sc), (reg),                     \
 883                        exar7250_read(sc, reg) & ~(bit))
 884
 885 #define exar7300_set_bit(sc, reg, bit)                  \
 886         exar7300_write((sc), (reg),                     \
 887                        exar7300_read(sc, reg) | (bit))
 888
 889 #define exar7300_clear_bit(sc, reg, bit)                \
 890         exar7300_write((sc), (reg),                     \
 891                        exar7300_read(sc, reg) & ~(bit))
 892
 893
 894 #endif /* T3E3_H */