drivers/staging/rts_pstor/rtsx_chip.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/workqueue.h>
  27
  28 #include "rtsx.h"
  29 #include "rtsx_transport.h"
  30 #include "rtsx_scsi.h"
  31 #include "rtsx_card.h"
  32 #include "rtsx_chip.h"
  33 #include "rtsx_sys.h"
  34 #include "general.h"
  35
  36 #include "sd.h"
  37 #include "xd.h"
  38 #include "ms.h"
  39
  40 static void rtsx_calibration(struct rtsx_chip *chip)
  41 {
  42         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  43         wait_timeout(10);
  44         rtsx_write_phy_register(chip, 0x00, 0x0280);
  45         rtsx_write_phy_register(chip, 0x01, 0x7112);
  46         rtsx_write_phy_register(chip, 0x01, 0x7110);
  47         rtsx_write_phy_register(chip, 0x01, 0x7112);
  48         rtsx_write_phy_register(chip, 0x01, 0x7113);
  49         rtsx_write_phy_register(chip, 0x00, 0x0288);
  50 }
  51
  52 void rtsx_disable_card_int(struct rtsx_chip *chip)
  53 {
  54         u32 reg = rtsx_readl(chip, RTSX_BIER);
  55
  56         reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
  57         rtsx_writel(chip, RTSX_BIER, reg);
  58 }
  59
  60 void rtsx_enable_card_int(struct rtsx_chip *chip)
  61 {
  62         u32 reg = rtsx_readl(chip, RTSX_BIER);
  63         int i;
  64
  65         for (i = 0; i <= chip->max_lun; i++) {
  66                 if (chip->lun2card[i] & XD_CARD)
  67                         reg |= XD_INT_EN;
  68                 if (chip->lun2card[i] & SD_CARD)
  69                         reg |= SD_INT_EN;
  70                 if (chip->lun2card[i] & MS_CARD)
  71                         reg |= MS_INT_EN;
  72         }
  73         if (chip->hw_bypass_sd)
  74                 reg &= ~((u32)SD_INT_EN);
  75
  76         rtsx_writel(chip, RTSX_BIER, reg);
  77 }
  78
  79 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  80 {
  81         u32 reg = 0;
  82 #ifndef DISABLE_CARD_INT
  83         int i;
  84 #endif
  85
  86         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  87
  88 #ifndef DISABLE_CARD_INT
  89         for (i = 0; i <= chip->max_lun; i++) {
  90                 RTSX_DEBUGP("lun2card[%d] = 0x%02x\n", i, chip->lun2card[i]);
  91
  92                 if (chip->lun2card[i] & XD_CARD)
  93                         reg |= XD_INT_EN;
  94                 if (chip->lun2card[i] & SD_CARD)
  95                         reg |= SD_INT_EN;
  96                 if (chip->lun2card[i] & MS_CARD)
  97                         reg |= MS_INT_EN;
  98         }
  99         if (chip->hw_bypass_sd)
 100                 reg &= ~((u32)SD_INT_EN);
 101 #endif
 102
 103         if (chip->ic_version >= IC_VER_C)
 104                 reg |= DELINK_INT_EN;
 105 #ifdef SUPPORT_OCP
 106         if (CHECK_PID(chip, 0x5209)) {
 107                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 108                         reg |= MS_OC_INT_EN | SD_OC_INT_EN;
 109                 } else {
 110                         reg |= SD_OC_INT_EN;
 111                 }
 112         } else {
 113                 reg |= OC_INT_EN;
 114         }
 115 #endif
 116         if (!chip->adma_mode)
 117                 reg |= DATA_DONE_INT_EN;
 118
 119         /* Enable Bus Interrupt */
 120         rtsx_writel(chip, RTSX_BIER, reg);
 121
 122         RTSX_DEBUGP("RTSX_BIER: 0x%08x\n", reg);
 123 }
 124
 125 void rtsx_disable_bus_int(struct rtsx_chip *chip)
 126 {
 127         rtsx_writel(chip, RTSX_BIER, 0);
 128 }
 129
 130 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
 131 {
 132         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 133                 if (chip->asic_code) {
 134                         RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
 135                                 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
 136                 } else {
 137                         RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, FPGA_SD_PULL_CTL_EN);
 138                 }
 139                 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD);
 140
 141                 /* Enable SDIO internal clock */
 142                 RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01);
 143
 144                 RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF, SDIO_BUS_CTRL | SDIO_CD_CTRL);
 145
 146                 chip->sd_int = 1;
 147                 chip->sd_io = 1;
 148         } else {
 149                 chip->need_reset |= SD_CARD;
 150         }
 151
 152         return STATUS_SUCCESS;
 153 }
 154
 155 #ifdef HW_AUTO_SWITCH_SD_BUS
 156 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 157 {
 158         u8 tmp;
 159         int sw_bypass_sd = 0;
 160         int retval;
 161
 162         if (chip->driver_first_load) {
 163                 if (CHECK_PID(chip, 0x5288)) {
 164                         RTSX_READ_REG(chip, 0xFE5A, &tmp);
 165                         if (tmp & 0x08)
 166                                 sw_bypass_sd = 1;
 167                 } else if (CHECK_PID(chip, 0x5208)) {
 168                         RTSX_READ_REG(chip, 0xFE70, &tmp);
 169                         if (tmp & 0x80)
 170                                 sw_bypass_sd = 1;
 171                 } else if (CHECK_PID(chip, 0x5209)) {
 172                         RTSX_READ_REG(chip, SDIO_CFG, &tmp);
 173                         if (tmp & SDIO_BUS_AUTO_SWITCH)
 174                                 sw_bypass_sd = 1;
 175                 }
 176         } else {
 177                 if (chip->sdio_in_charge)
 178                         sw_bypass_sd = 1;
 179         }
 180         RTSX_DEBUGP("chip->sdio_in_charge = %d\n", chip->sdio_in_charge);
 181         RTSX_DEBUGP("chip->driver_first_load = %d\n", chip->driver_first_load);
 182         RTSX_DEBUGP("sw_bypass_sd = %d\n", sw_bypass_sd);
 183
 184         if (sw_bypass_sd) {
 185                 u8 cd_toggle_mask = 0;
 186
 187                 RTSX_READ_REG(chip, TLPTISTAT, &tmp);
 188                 if (CHECK_PID(chip, 0x5209)) {
 189                         cd_toggle_mask = 0x10;
 190                 } else {
 191                         cd_toggle_mask = 0x08;
 192                 }
 193                 if (tmp & cd_toggle_mask) {
 194                         /* Disable sdio_bus_auto_switch */
 195                         if (CHECK_PID(chip, 0x5288)) {
 196                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00);
 197                         } else if (CHECK_PID(chip, 0x5208)) {
 198                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00);
 199                         } else {
 200                                 RTSX_WRITE_REG(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, 0);
 201                         }
 202                         RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp);
 203
 204                         chip->need_reset |= SD_CARD;
 205                 } else {
 206                         RTSX_DEBUGP("Chip inserted with SDIO!\n");
 207
 208                         if (chip->asic_code) {
 209                                 retval = sd_pull_ctl_enable(chip);
 210                                 if (retval != STATUS_SUCCESS) {
 211                                         TRACE_RET(chip, STATUS_FAIL);
 212                                 }
 213                         } else {
 214                                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0);
 215                         }
 216                         retval = card_share_mode(chip, SD_CARD);
 217                         if (retval != STATUS_SUCCESS) {
 218                                 TRACE_RET(chip, STATUS_FAIL);
 219                         }
 220
 221                         /* Enable sdio_bus_auto_switch */
 222                         if (CHECK_PID(chip, 0x5288)) {
 223                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08);
 224                         } else if (CHECK_PID(chip, 0x5208)) {
 225                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80);
 226                         } else {
 227                                 RTSX_WRITE_REG(chip, SDIO_CFG,
 228                                         SDIO_BUS_AUTO_SWITCH, SDIO_BUS_AUTO_SWITCH);
 229                         }
 230                         chip->chip_insert_with_sdio = 1;
 231                         chip->sd_io = 1;
 232                 }
 233         } else {
 234                 if (CHECK_PID(chip, 0x5209)) {
 235                         RTSX_WRITE_REG(chip, TLPTISTAT, 0x10, 0x10);
 236                 } else {
 237                         RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08);
 238                 }
 239                 chip->need_reset |= SD_CARD;
 240         }
 241
 242         return STATUS_SUCCESS;
 243 }
 244 #endif
 245
 246 int rtsx_reset_chip(struct rtsx_chip *chip)
 247 {
 248         int retval;
 249
 250         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 251
 252         rtsx_disable_aspm(chip);
 253
 254         if (CHECK_PID(chip, 0x5209) && chip->asic_code) {
 255                 u16 val;
 256
 257                 /* optimize PHY */
 258                 retval = rtsx_write_phy_register(chip, 0x00, 0xB966);
 259                 if (retval != STATUS_SUCCESS) {
 260                         TRACE_RET(chip, STATUS_FAIL);
 261                 }
 262                 retval = rtsx_write_phy_register(chip, 0x01, 0x713F);
 263                 if (retval != STATUS_SUCCESS) {
 264                         TRACE_RET(chip, STATUS_FAIL);
 265                 }
 266                 retval = rtsx_write_phy_register(chip, 0x03, 0xA549);
 267                 if (retval != STATUS_SUCCESS) {
 268                         TRACE_RET(chip, STATUS_FAIL);
 269                 }
 270                 retval = rtsx_write_phy_register(chip, 0x06, 0xB235);
 271                 if (retval != STATUS_SUCCESS) {
 272                         TRACE_RET(chip, STATUS_FAIL);
 273                 }
 274                 retval = rtsx_write_phy_register(chip, 0x07, 0xEF40);
 275                 if (retval != STATUS_SUCCESS) {
 276                         TRACE_RET(chip, STATUS_FAIL);
 277                 }
 278                 retval = rtsx_write_phy_register(chip, 0x1E, 0xF8EB);
 279                 if (retval != STATUS_SUCCESS) {
 280                         TRACE_RET(chip, STATUS_FAIL);
 281                 }
 282                 retval = rtsx_write_phy_register(chip, 0x19, 0xFE6C);
 283                 if (retval != STATUS_SUCCESS) {
 284                         TRACE_RET(chip, STATUS_FAIL);
 285                 }
 286                 wait_timeout(1);
 287                 retval = rtsx_write_phy_register(chip, 0x0A, 0x05C0);
 288                 if (retval != STATUS_SUCCESS) {
 289                         TRACE_RET(chip, STATUS_FAIL);
 290                 }
 291
 292                 retval = rtsx_write_cfg_dw(chip, 1, 0x110, 0xFFFF, 0xFFFF);
 293                 if (retval != STATUS_SUCCESS) {
 294                         TRACE_RET(chip, STATUS_FAIL);
 295                 }
 296
 297                 retval = rtsx_read_phy_register(chip, 0x08, &val);
 298                 if (retval != STATUS_SUCCESS) {
 299                         TRACE_RET(chip, STATUS_FAIL);
 300                 }
 301                 RTSX_DEBUGP("Read from phy 0x08: 0x%04x\n", val);
 302
 303                 if (chip->phy_voltage) {
 304                         chip->phy_voltage &= 0x3F;
 305                         RTSX_DEBUGP("chip->phy_voltage = 0x%x\n", chip->phy_voltage);
 306                         val &= ~0x3F;
 307                         val |= chip->phy_voltage;
 308                         RTSX_DEBUGP("Write to phy 0x08: 0x%04x\n", val);
 309                         retval = rtsx_write_phy_register(chip, 0x08, val);
 310                         if (retval != STATUS_SUCCESS) {
 311                                 TRACE_RET(chip, STATUS_FAIL);
 312                         }
 313                 } else {
 314                         chip->phy_voltage = (u8)(val & 0x3F);
 315                         RTSX_DEBUGP("Default, chip->phy_voltage = 0x%x\n", chip->phy_voltage);
 316                 }
 317         }
 318
 319         RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 320
 321         /* Disable card clock */
 322         RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0);
 323
 324 #ifdef SUPPORT_OCP
 325         /* SSC power on, OCD power on */
 326         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 327                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0);
 328         } else {
 329                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN);
 330         }
 331         if (CHECK_PID(chip, 0x5209)) {
 332                 RTSX_WRITE_REG(chip, OCPPARA1, SD_OCP_TIME_MASK | MS_OCP_TIME_MASK,
 333                                     SD_OCP_TIME_800 | MS_OCP_TIME_800);
 334                 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK | MS_OCP_THD_MASK,
 335                                     chip->sd_400mA_ocp_thd | (chip->ms_ocp_thd << 4));
 336                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 337                         RTSX_WRITE_REG(chip, OCPGLITCH, SD_OCP_GLITCH_MASK | MS_OCP_GLITCH_MASK,
 338                                        SD_OCP_GLITCH_10000 | MS_OCP_GLITCH_10000);
 339                 } else {
 340                         RTSX_WRITE_REG(chip, OCPGLITCH, SD_OCP_GLITCH_MASK, SD_OCP_GLITCH_10000);
 341                 }
 342                 RTSX_WRITE_REG(chip, OCPCTL, 0xFF,
 343                                     SD_OCP_INT_EN | SD_DETECT_EN | MS_OCP_INT_EN | MS_DETECT_EN);
 344         } else {
 345                 RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800);
 346                 RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946);
 347                 RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN);
 348         }
 349 #else
 350         /* OC power down */
 351         RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN);
 352 #endif
 353
 354         if (!CHECK_PID(chip, 0x5288)) {
 355                 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 356         }
 357
 358         /* Turn off LED */
 359         RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03);
 360
 361         /* Reset delink mode */
 362         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0);
 363
 364         /* Card driving select */
 365         RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel);
 366         if (CHECK_PID(chip, 0x5209)) {
 367                 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3);
 368         }
 369
 370 #ifdef LED_AUTO_BLINK
 371         RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF,
 372                         LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 373 #endif
 374
 375         if (chip->asic_code) {
 376                 /* Enable SSC Clock */
 377                 RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M);
 378                 RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12);
 379         }
 380
 381         /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 382               0xFE5B
 383               bit[1]    u_cd_rst_core_en        rst_value = 0
 384               bit[2]    u_force_rst_core_en     rst_value = 0
 385               bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 386               bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 387         */
 388         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 389
 390         /* Enable ASPM */
 391         if (chip->aspm_l0s_l1_en) {
 392                 if (chip->dynamic_aspm) {
 393                         if (CHK_SDIO_EXIST(chip)) {
 394                                 if (CHECK_PID(chip, 0x5209)) {
 395                                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 396                                         if (retval != STATUS_SUCCESS) {
 397                                                 TRACE_RET(chip, STATUS_FAIL);
 398                                         }
 399                                 } else if (CHECK_PID(chip, 0x5288)) {
 400                                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 401                                         if (retval != STATUS_SUCCESS) {
 402                                                 TRACE_RET(chip, STATUS_FAIL);
 403                                         }
 404                                 }
 405                         }
 406                 } else {
 407                         if (CHECK_PID(chip, 0x5208)) {
 408                                 RTSX_WRITE_REG(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
 409                         }
 410
 411                         retval = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 412                         if (retval != STATUS_SUCCESS) {
 413                                 TRACE_RET(chip, STATUS_FAIL);
 414                         }
 415                         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 416                         if (CHK_SDIO_EXIST(chip)) {
 417                                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 418                                 if (CHECK_PID(chip, 0x5288)) {
 419                                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 420                                 } else {
 421                                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 422                                 }
 423                                 if (retval != STATUS_SUCCESS) {
 424                                         TRACE_RET(chip, STATUS_FAIL);
 425                                 }
 426                         }
 427
 428                         chip->aspm_enabled = 1;
 429                 }
 430         } else {
 431                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 432                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 433                         if (retval != STATUS_SUCCESS) {
 434                                 TRACE_RET(chip, STATUS_FAIL);
 435                         }
 436                 }
 437                 retval = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 438                 if (retval != STATUS_SUCCESS) {
 439                         TRACE_RET(chip, STATUS_FAIL);
 440                 }
 441         }
 442
 443         retval = rtsx_write_config_byte(chip, 0x81, 1);
 444         if (retval != STATUS_SUCCESS) {
 445                 TRACE_RET(chip, STATUS_FAIL);
 446         }
 447
 448         if (CHK_SDIO_EXIST(chip)) {
 449                 if (CHECK_PID(chip, 0x5288)) {
 450                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100);
 451                 } else {
 452                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100);
 453                 }
 454                 if (retval != STATUS_SUCCESS) {
 455                         TRACE_RET(chip, STATUS_FAIL);
 456                 }
 457         }
 458
 459         if (CHECK_PID(chip, 0x5209)) {
 460                 retval = rtsx_write_cfg_dw(chip, 0, 0x70C, 0xFF000000, 0x5B);
 461                 if (retval != STATUS_SUCCESS) {
 462                         TRACE_RET(chip, STATUS_FAIL);
 463                 }
 464         }
 465
 466         if (CHECK_PID(chip, 0x5288)) {
 467                 if (!CHK_SDIO_EXIST(chip)) {
 468                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
 469                         if (retval != STATUS_SUCCESS) {
 470                                 TRACE_RET(chip, STATUS_FAIL);
 471                         }
 472                         retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 473                         if (retval != STATUS_SUCCESS) {
 474                                 TRACE_RET(chip, STATUS_FAIL);
 475                         }
 476                 }
 477         }
 478
 479         RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
 480
 481         RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 482
 483         if (CHECK_PID(chip, 0x5209)) {
 484                 RTSX_WRITE_REG(chip, PWD_SUSPEND_EN, 0xFF, 0xFF);
 485                 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, PWR_GATE_EN, PWR_GATE_EN);
 486         }
 487
 488         /* Enable PCIE interrupt */
 489         if (chip->asic_code) {
 490                 if (CHECK_PID(chip, 0x5208)) {
 491                         if (chip->phy_debug_mode) {
 492                                 RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0);
 493                                 rtsx_disable_bus_int(chip);
 494                         } else {
 495                                 rtsx_enable_bus_int(chip);
 496                         }
 497
 498                         if (chip->ic_version >= IC_VER_D) {
 499                                 u16 reg;
 500                                 retval = rtsx_read_phy_register(chip, 0x00, &reg);
 501                                 if (retval != STATUS_SUCCESS) {
 502                                         TRACE_RET(chip, STATUS_FAIL);
 503                                 }
 504                                 reg &= 0xFE7F;
 505                                 reg |= 0x80;
 506                                 retval = rtsx_write_phy_register(chip, 0x00, reg);
 507                                 if (retval != STATUS_SUCCESS) {
 508                                         TRACE_RET(chip, STATUS_FAIL);
 509                                 }
 510                                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 511                                 if (retval != STATUS_SUCCESS) {
 512                                         TRACE_RET(chip, STATUS_FAIL);
 513                                 }
 514                                 reg &= 0xFFF7;
 515                                 retval = rtsx_write_phy_register(chip, 0x1C, reg);
 516                                 if (retval != STATUS_SUCCESS) {
 517                                         TRACE_RET(chip, STATUS_FAIL);
 518                                 }
 519                         }
 520
 521                         if (chip->driver_first_load && (chip->ic_version < IC_VER_C)) {
 522                                 rtsx_calibration(chip);
 523                         }
 524                 } else {
 525                         rtsx_enable_bus_int(chip);
 526                 }
 527         } else {
 528                 rtsx_enable_bus_int(chip);
 529         }
 530
 531 #ifdef HW_INT_WRITE_CLR
 532         if (CHECK_PID(chip, 0x5209)) {
 533                 /* Set interrupt write clear */
 534                 RTSX_WRITE_REG(chip, NFTS_TX_CTRL, 0x02, 0);
 535         }
 536 #endif
 537
 538         chip->need_reset = 0;
 539
 540         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 541 #ifdef HW_INT_WRITE_CLR
 542         if (CHECK_PID(chip, 0x5209)) {
 543                 /* Clear interrupt flag */
 544                 rtsx_writel(chip, RTSX_BIPR, chip->int_reg);
 545         }
 546 #endif
 547         if (chip->hw_bypass_sd)
 548                 goto NextCard;
 549         RTSX_DEBUGP("In rtsx_reset_chip, chip->int_reg = 0x%x\n", chip->int_reg);
 550         if (chip->int_reg & SD_EXIST) {
 551 #ifdef HW_AUTO_SWITCH_SD_BUS
 552                 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C)) {
 553                         retval = rtsx_pre_handle_sdio_old(chip);
 554                 } else {
 555                         retval = rtsx_pre_handle_sdio_new(chip);
 556                 }
 557                 RTSX_DEBUGP("chip->need_reset = 0x%x (rtsx_reset_chip)\n", (unsigned int)(chip->need_reset));
 558 #else  /* HW_AUTO_SWITCH_SD_BUS */
 559                 retval = rtsx_pre_handle_sdio_old(chip);
 560 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 561                 if (retval != STATUS_SUCCESS) {
 562                         TRACE_RET(chip, STATUS_FAIL);
 563                 }
 564         } else {
 565                 chip->sd_io = 0;
 566                 RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
 567         }
 568
 569 NextCard:
 570         if (chip->int_reg & XD_EXIST)
 571                 chip->need_reset |= XD_CARD;
 572         if (chip->int_reg & MS_EXIST)
 573                 chip->need_reset |= MS_CARD;
 574         if (chip->int_reg & CARD_EXIST) {
 575                 RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 576         }
 577
 578         RTSX_DEBUGP("In rtsx_init_chip, chip->need_reset = 0x%x\n", (unsigned int)(chip->need_reset));
 579
 580         RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00);
 581
 582         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 583                 /* Turn off main power when entering S3/S4 state */
 584                 RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03);
 585         }
 586
 587         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 588                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07);
 589                 if (chip->aux_pwr_exist) {
 590                         RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33);
 591                 }
 592         } else {
 593                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04);
 594                 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30);
 595         }
 596
 597         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
 598                 RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14);
 599         } else if (CHECK_PID(chip, 0x5209)) {
 600                 if (chip->force_clkreq_0) {
 601                         RTSX_WRITE_REG(chip, PETXCFG, 0x08, 0x08);
 602                 } else {
 603                         RTSX_WRITE_REG(chip, PETXCFG, 0x08, 0x00);
 604                 }
 605         }
 606
 607         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 608                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 609                 if (retval != STATUS_SUCCESS) {
 610                         TRACE_RET(chip, STATUS_FAIL);
 611                 }
 612         }
 613
 614         if (chip->ft2_fast_mode) {
 615                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
 616                 udelay(chip->pmos_pwr_on_interval);
 617                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, MS_POWER_ON | SD_POWER_ON);
 618
 619                 wait_timeout(200);
 620         }
 621
 622         /* Reset card */
 623         rtsx_reset_detected_cards(chip, 0);
 624
 625         chip->driver_first_load = 0;
 626
 627         return STATUS_SUCCESS;
 628 }
 629
 630 static inline int check_sd_speed_prior(u32 sd_speed_prior)
 631 {
 632         int i, fake_para = 0;
 633
 634         for (i = 0; i < 4; i++) {
 635                 u8 tmp = (u8)(sd_speed_prior >> (i*8));
 636                 if ((tmp < 0x01) || (tmp > 0x04)) {
 637                         fake_para = 1;
 638                         break;
 639                 }
 640         }
 641
 642         return !fake_para;
 643 }
 644
 645 static inline int check_sd_current_prior(u32 sd_current_prior)
 646 {
 647         int i, fake_para = 0;
 648
 649         for (i = 0; i < 4; i++) {
 650                 u8 tmp = (u8)(sd_current_prior >> (i*8));
 651                 if (tmp > 0x03) {
 652                         fake_para = 1;
 653                         break;
 654                 }
 655         }
 656
 657         return !fake_para;
 658 }
 659
 660 static int rts5209_init(struct rtsx_chip *chip)
 661 {
 662         int retval;
 663         u32 lval = 0;
 664         u8 val = 0;
 665
 666         val = rtsx_readb(chip, 0x1C);
 667         if ((val & 0x10) == 0) {
 668                 chip->asic_code = 1;
 669         } else {
 670                 chip->asic_code = 0;
 671         }
 672
 673         chip->ic_version = val & 0x0F;
 674         chip->phy_debug_mode = 0;
 675
 676         chip->aux_pwr_exist = 0;
 677
 678         chip->ms_power_class_en = 0x03;
 679
 680         retval = rtsx_read_cfg_dw(chip, 0, 0x724, &lval);
 681         if (retval != STATUS_SUCCESS) {
 682                 TRACE_RET(chip, STATUS_FAIL);
 683         }
 684         RTSX_DEBUGP("dw in 0x724: 0x%x\n", lval);
 685         val = (u8)lval;
 686         if (!(val & 0x80)) {
 687                 if (val & 0x08)
 688                         chip->lun_mode = DEFAULT_SINGLE;
 689                 else
 690                         chip->lun_mode = SD_MS_2LUN;
 691
 692                 if (val & 0x04) {
 693                         SET_SDIO_EXIST(chip);
 694                 } else {
 695                         CLR_SDIO_EXIST(chip);
 696                 }
 697
 698                 if (val & 0x02) {
 699                         chip->hw_bypass_sd = 0;
 700                 } else {
 701                         chip->hw_bypass_sd = 1;
 702                 }
 703         } else {
 704                 SET_SDIO_EXIST(chip);
 705                 chip->hw_bypass_sd = 0;
 706         }
 707
 708         if (chip->use_hw_setting) {
 709                 u8 clk;
 710
 711                 chip->aspm_l0s_l1_en = (val >> 5) & 0x03;
 712
 713                 val = (u8)(lval >> 8);
 714
 715                 clk = (val >> 5) & 0x07;
 716                 if (clk != 0x07) {
 717                         chip->asic_sd_sdr50_clk = 98 - clk * 2;
 718                 }
 719
 720                 if (val & 0x10) {
 721                         chip->auto_delink_en = 1;
 722                 } else {
 723                         chip->auto_delink_en = 0;
 724                 }
 725
 726                 if (chip->ss_en == 2) {
 727                         chip->ss_en = 0;
 728                 } else {
 729                         if (val & 0x08) {
 730                                 chip->ss_en = 1;
 731                         } else {
 732                                 chip->ss_en = 0;
 733                         }
 734                 }
 735
 736                 clk = val & 0x07;
 737                 if (clk != 0x07)
 738                         chip->asic_ms_hg_clk = (59 - clk) * 2;
 739
 740                 val = (u8)(lval >> 16);
 741
 742                 clk = (val >> 6) & 0x03;
 743                 if (clk != 0x03) {
 744                         chip->asic_sd_hs_clk = (49 - clk * 2) * 2;
 745                         chip->asic_mmc_52m_clk = (49 - clk * 2) * 2;
 746                 }
 747
 748                 clk = (val >> 4) & 0x03;
 749                 if (clk != 0x03)
 750                         chip->asic_sd_ddr50_clk = (48 - clk * 2) * 2;
 751
 752                 if (val & 0x01) {
 753                         chip->sdr104_en = 1;
 754                 } else {
 755                         chip->sdr104_en = 0;
 756                 }
 757                 if (val & 0x02) {
 758                         chip->ddr50_en = 1;
 759                 } else {
 760                         chip->ddr50_en = 0;
 761                 }
 762                 if (val & 0x04) {
 763                         chip->sdr50_en = 1;
 764                 } else {
 765                         chip->sdr50_en = 0;
 766                 }
 767
 768                 val = (u8)(lval >> 24);
 769
 770                 clk = (val >> 5) & 0x07;
 771                 if (clk != 0x07)
 772                         chip->asic_sd_sdr104_clk = 206 - clk * 3;
 773
 774                 if (val & 0x10) {
 775                         chip->power_down_in_ss = 1;
 776                 } else {
 777                         chip->power_down_in_ss = 0;
 778                 }
 779
 780                 chip->ms_power_class_en = val & 0x03;
 781         }
 782
 783         if (chip->hp_watch_bios_hotplug && chip->auto_delink_en) {
 784                 u8 reg58, reg5b;
 785
 786                 retval = rtsx_read_pci_cfg_byte(0x00,
 787                                                 0x1C, 0x02, 0x58, &reg58);
 788                 if (retval < 0) {
 789                         return STATUS_SUCCESS;
 790                 }
 791                 retval = rtsx_read_pci_cfg_byte(0x00,
 792                                                 0x1C, 0x02, 0x5B, &reg5b);
 793                 if (retval < 0) {
 794                         return STATUS_SUCCESS;
 795                 }
 796
 797                 RTSX_DEBUGP("reg58 = 0x%x, reg5b = 0x%x\n", reg58, reg5b);
 798
 799                 if ((reg58 == 0x00) && (reg5b == 0x01)) {
 800                         chip->auto_delink_en = 0;
 801                 }
 802         }
 803
 804         return STATUS_SUCCESS;
 805 }
 806
 807 static int rts5208_init(struct rtsx_chip *chip)
 808 {
 809         int retval;
 810         u16 reg = 0;
 811         u8 val = 0;
 812
 813         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 814         RTSX_READ_REG(chip, CLK_SEL, &val);
 815         if (val == 0) {
 816                 chip->asic_code = 1;
 817         } else {
 818                 chip->asic_code = 0;
 819         }
 820
 821         if (chip->asic_code) {
 822                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 823                 if (retval != STATUS_SUCCESS) {
 824                         TRACE_RET(chip, STATUS_FAIL);
 825                 }
 826                 RTSX_DEBUGP("Value of phy register 0x1C is 0x%x\n", reg);
 827                 chip->ic_version = (reg >> 4) & 0x07;
 828                 if (reg & PHY_DEBUG_MODE) {
 829                         chip->phy_debug_mode = 1;
 830                 } else {
 831                         chip->phy_debug_mode = 0;
 832                 }
 833         } else {
 834                 RTSX_READ_REG(chip, 0xFE80, &val);
 835                 chip->ic_version = val;
 836                 chip->phy_debug_mode = 0;
 837         }
 838
 839         RTSX_READ_REG(chip, PDINFO, &val);
 840         RTSX_DEBUGP("PDINFO: 0x%x\n", val);
 841         if (val & AUX_PWR_DETECTED) {
 842                 chip->aux_pwr_exist = 1;
 843         } else {
 844                 chip->aux_pwr_exist = 0;
 845         }
 846
 847         RTSX_READ_REG(chip, 0xFE50, &val);
 848         if (val & 0x01) {
 849                 chip->hw_bypass_sd = 1;
 850         } else {
 851                 chip->hw_bypass_sd = 0;
 852         }
 853
 854         rtsx_read_config_byte(chip, 0x0E, &val);
 855         if (val & 0x80) {
 856                 SET_SDIO_EXIST(chip);
 857         } else {
 858                 CLR_SDIO_EXIST(chip);
 859         }
 860
 861         if (chip->use_hw_setting) {
 862                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 863                 if (val & 0x80) {
 864                         chip->auto_delink_en = 1;
 865                 } else {
 866                         chip->auto_delink_en = 0;
 867                 }
 868         }
 869
 870         return STATUS_SUCCESS;
 871 }
 872
 873 static int rts5288_init(struct rtsx_chip *chip)
 874 {
 875         int retval;
 876         u8 val = 0, max_func;
 877         u32 lval = 0;
 878
 879         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 880         RTSX_READ_REG(chip, CLK_SEL, &val);
 881         if (val == 0) {
 882                 chip->asic_code = 1;
 883         } else {
 884                 chip->asic_code = 0;
 885         }
 886
 887         chip->ic_version = 0;
 888         chip->phy_debug_mode = 0;
 889
 890         RTSX_READ_REG(chip, PDINFO, &val);
 891         RTSX_DEBUGP("PDINFO: 0x%x\n", val);
 892         if (val & AUX_PWR_DETECTED) {
 893                 chip->aux_pwr_exist = 1;
 894         } else {
 895                 chip->aux_pwr_exist = 0;
 896         }
 897
 898         RTSX_READ_REG(chip, CARD_SHARE_MODE, &val);
 899         RTSX_DEBUGP("CARD_SHARE_MODE: 0x%x\n", val);
 900         if (val & 0x04) {
 901                 chip->baro_pkg = QFN;
 902         } else {
 903                 chip->baro_pkg = LQFP;
 904         }
 905
 906         RTSX_READ_REG(chip, 0xFE5A, &val);
 907         if (val & 0x10) {
 908                 chip->hw_bypass_sd = 1;
 909         } else {
 910                 chip->hw_bypass_sd = 0;
 911         }
 912
 913         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 914         if (retval != STATUS_SUCCESS) {
 915                 TRACE_RET(chip, STATUS_FAIL);
 916         }
 917         max_func = (u8)((lval >> 29) & 0x07);
 918         RTSX_DEBUGP("Max function number: %d\n", max_func);
 919         if (max_func == 0x02) {
 920                 SET_SDIO_EXIST(chip);
 921         } else {
 922                 CLR_SDIO_EXIST(chip);
 923         }
 924
 925         if (chip->use_hw_setting) {
 926                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 927                 if (val & 0x80) {
 928                         chip->auto_delink_en = 1;
 929                 } else {
 930                         chip->auto_delink_en = 0;
 931                 }
 932
 933                 if (CHECK_BARO_PKG(chip, LQFP)) {
 934                         chip->lun_mode = SD_MS_1LUN;
 935                 } else {
 936                         chip->lun_mode = DEFAULT_SINGLE;
 937                 }
 938         }
 939
 940         return STATUS_SUCCESS;
 941 }
 942
 943 int rtsx_init_chip(struct rtsx_chip *chip)
 944 {
 945         struct sd_info *sd_card = &(chip->sd_card);
 946         struct xd_info *xd_card = &(chip->xd_card);
 947         struct ms_info *ms_card = &(chip->ms_card);
 948         int retval;
 949         unsigned int i;
 950
 951         RTSX_DEBUGP("Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 952                      chip->vendor_id, chip->product_id);
 953
 954         chip->ic_version = 0;
 955
 956 #ifdef _MSG_TRACE
 957         chip->msg_idx = 0;
 958 #endif
 959
 960         memset(xd_card, 0, sizeof(struct xd_info));
 961         memset(sd_card, 0, sizeof(struct sd_info));
 962         memset(ms_card, 0, sizeof(struct ms_info));
 963
 964         chip->xd_reset_counter = 0;
 965         chip->sd_reset_counter = 0;
 966         chip->ms_reset_counter = 0;
 967
 968         chip->xd_show_cnt = MAX_SHOW_CNT;
 969         chip->sd_show_cnt = MAX_SHOW_CNT;
 970         chip->ms_show_cnt = MAX_SHOW_CNT;
 971
 972         chip->sd_io = 0;
 973         chip->auto_delink_cnt = 0;
 974         chip->auto_delink_allowed = 1;
 975         rtsx_set_stat(chip, RTSX_STAT_INIT);
 976
 977         chip->aspm_enabled = 0;
 978         chip->chip_insert_with_sdio = 0;
 979         chip->sdio_aspm = 0;
 980         chip->sdio_idle = 0;
 981         chip->sdio_counter = 0;
 982         chip->cur_card = 0;
 983         chip->phy_debug_mode = 0;
 984         chip->sdio_func_exist = 0;
 985         memset(chip->sdio_raw_data, 0, 12);
 986
 987         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 988                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 989                 chip->rw_fail_cnt[i] = 0;
 990         }
 991
 992         if (!check_sd_speed_prior(chip->sd_speed_prior)) {
 993                 chip->sd_speed_prior = 0x01040203;
 994         }
 995         RTSX_DEBUGP("sd_speed_prior = 0x%08x\n", chip->sd_speed_prior);
 996
 997         if (!check_sd_current_prior(chip->sd_current_prior)) {
 998                 chip->sd_current_prior = 0x00010203;
 999         }
1000         RTSX_DEBUGP("sd_current_prior = 0x%08x\n", chip->sd_current_prior);
1001
1002         if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0)) {
1003                 chip->sd_ddr_tx_phase = 0;
1004         }
1005         if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0)) {
1006                 chip->mmc_ddr_tx_phase = 0;
1007         }
1008
1009         RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0);
1010         wait_timeout(200);
1011         RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07);
1012         RTSX_DEBUGP("chip->use_hw_setting = %d\n", chip->use_hw_setting);
1013
1014         if (CHECK_PID(chip, 0x5209)) {
1015                 retval = rts5209_init(chip);
1016                 if (retval != STATUS_SUCCESS) {
1017                         TRACE_RET(chip, STATUS_FAIL);
1018                 }
1019         } else if (CHECK_PID(chip, 0x5208)) {
1020                 retval = rts5208_init(chip);
1021                 if (retval != STATUS_SUCCESS) {
1022                         TRACE_RET(chip, STATUS_FAIL);
1023                 }
1024         } else if (CHECK_PID(chip, 0x5288)) {
1025                 retval = rts5288_init(chip);
1026                 if (retval != STATUS_SUCCESS) {
1027                         TRACE_RET(chip, STATUS_FAIL);
1028                 }
1029         }
1030
1031         if (chip->ss_en == 2) {
1032                 chip->ss_en = 0;
1033         }
1034
1035         RTSX_DEBUGP("chip->asic_code = %d\n", chip->asic_code);
1036         RTSX_DEBUGP("chip->ic_version = 0x%x\n", chip->ic_version);
1037         RTSX_DEBUGP("chip->phy_debug_mode = %d\n", chip->phy_debug_mode);
1038         RTSX_DEBUGP("chip->aux_pwr_exist = %d\n", chip->aux_pwr_exist);
1039         RTSX_DEBUGP("chip->sdio_func_exist = %d\n", chip->sdio_func_exist);
1040         RTSX_DEBUGP("chip->hw_bypass_sd = %d\n", chip->hw_bypass_sd);
1041         RTSX_DEBUGP("chip->aspm_l0s_l1_en = %d\n", chip->aspm_l0s_l1_en);
1042         RTSX_DEBUGP("chip->lun_mode = %d\n", chip->lun_mode);
1043         RTSX_DEBUGP("chip->auto_delink_en = %d\n", chip->auto_delink_en);
1044         RTSX_DEBUGP("chip->ss_en = %d\n", chip->ss_en);
1045         RTSX_DEBUGP("chip->baro_pkg = %d\n", chip->baro_pkg);
1046
1047         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1048                 chip->card2lun[SD_CARD] = 0;
1049                 chip->card2lun[MS_CARD] = 1;
1050                 chip->card2lun[XD_CARD] = 0xFF;
1051                 chip->lun2card[0] = SD_CARD;
1052                 chip->lun2card[1] = MS_CARD;
1053                 chip->max_lun = 1;
1054                 SET_SDIO_IGNORED(chip);
1055         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1056                 chip->card2lun[SD_CARD] = 0;
1057                 chip->card2lun[MS_CARD] = 0;
1058                 chip->card2lun[XD_CARD] = 0xFF;
1059                 chip->lun2card[0] = SD_CARD | MS_CARD;
1060                 chip->max_lun = 0;
1061         } else {
1062                 chip->card2lun[XD_CARD] = 0;
1063                 chip->card2lun[SD_CARD] = 0;
1064                 chip->card2lun[MS_CARD] = 0;
1065                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1066                 chip->max_lun = 0;
1067         }
1068
1069         retval = rtsx_reset_chip(chip);
1070         if (retval != STATUS_SUCCESS) {
1071                 TRACE_RET(chip, STATUS_FAIL);
1072         }
1073
1074         return STATUS_SUCCESS;
1075 }
1076
1077 void rtsx_release_chip(struct rtsx_chip *chip)
1078 {
1079         xd_free_l2p_tbl(chip);
1080         ms_free_l2p_tbl(chip);
1081         chip->card_exist = 0;
1082         chip->card_ready = 0;
1083 }
1084
1085 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1086 static inline void rtsx_blink_led(struct rtsx_chip *chip)
1087 {
1088         if (chip->card_exist && chip->blink_led) {
1089                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1090                         chip->led_toggle_counter++;
1091                 } else {
1092                         chip->led_toggle_counter = 0;
1093                         toggle_gpio(chip, LED_GPIO);
1094                 }
1095         }
1096 }
1097 #endif
1098
1099 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1100 {
1101         int maybe_support_aspm, reg_changed;
1102         u32 tmp = 0;
1103         u8 reg0 = 0, reg1 = 0;
1104
1105         maybe_support_aspm = 0;
1106         reg_changed = 0;
1107         rtsx_read_config_byte(chip, LCTLR, &reg0);
1108         if (chip->aspm_level[0] != reg0) {
1109                 reg_changed = 1;
1110                 chip->aspm_level[0] = reg0;
1111         }
1112         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1113                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1114                 reg1 = (u8)tmp;
1115                 if (chip->aspm_level[1] != reg1) {
1116                         reg_changed = 1;
1117                         chip->aspm_level[1] = reg1;
1118                 }
1119
1120                 if ((reg0 & 0x03) && (reg1 & 0x03)) {
1121                         maybe_support_aspm = 1;
1122                 }
1123         } else {
1124                 if (reg0 & 0x03) {
1125                         maybe_support_aspm = 1;
1126                 }
1127         }
1128
1129         if (reg_changed) {
1130                 if (maybe_support_aspm) {
1131                         chip->aspm_l0s_l1_en = 0x03;
1132                 }
1133                 RTSX_DEBUGP("aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1134                               chip->aspm_level[0], chip->aspm_level[1]);
1135
1136                 if (chip->aspm_l0s_l1_en) {
1137                         chip->aspm_enabled = 1;
1138                 } else {
1139                         chip->aspm_enabled = 0;
1140                         chip->sdio_aspm = 0;
1141                 }
1142                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1143                         0x30 | chip->aspm_level[0] | (chip->aspm_level[1] << 2));
1144         }
1145 }
1146
1147 void rtsx_polling_func(struct rtsx_chip *chip)
1148 {
1149 #ifdef SUPPORT_SD_LOCK
1150         struct sd_info *sd_card = &(chip->sd_card);
1151 #endif
1152         int ss_allowed;
1153
1154         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1155                 return;
1156
1157         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1158                 goto Delink_Stage;
1159
1160         if (chip->polling_config) {
1161                 u8 val;
1162                 rtsx_read_config_byte(chip, 0, &val);
1163         }
1164
1165         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1166                 return;
1167
1168 #ifdef SUPPORT_OCP
1169         if (chip->ocp_int) {
1170                 rtsx_read_register(chip, OCPSTAT, &(chip->ocp_stat));
1171
1172                 if (CHECK_PID(chip, 0x5209) &&
1173                                 CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1174                         if (chip->ocp_int & SD_OC_INT)
1175                                 sd_power_off_card3v3(chip);
1176                         if (chip->ocp_int & MS_OC_INT)
1177                                 ms_power_off_card3v3(chip);
1178                 } else {
1179                         if (chip->card_exist & SD_CARD) {
1180                                 sd_power_off_card3v3(chip);
1181                         } else if (chip->card_exist & MS_CARD) {
1182                                 ms_power_off_card3v3(chip);
1183                         } else if (chip->card_exist & XD_CARD) {
1184                                 xd_power_off_card3v3(chip);
1185                         }
1186                 }
1187
1188                 chip->ocp_int = 0;
1189         }
1190 #endif
1191
1192 #ifdef SUPPORT_SD_LOCK
1193         if (sd_card->sd_erase_status) {
1194                 if (chip->card_exist & SD_CARD) {
1195                         u8 val;
1196                         if (CHECK_PID(chip, 0x5209)) {
1197                                 rtsx_read_register(chip, SD_BUS_STAT, &val);
1198                                 if (val & SD_DAT0_STATUS) {
1199                                         sd_card->sd_erase_status = SD_NOT_ERASE;
1200                                         sd_card->sd_lock_notify = 1;
1201                                         chip->need_reinit |= SD_CARD;
1202                                 }
1203                         } else {
1204                                 rtsx_read_register(chip, 0xFD30, &val);
1205                                 if (val & 0x02) {
1206                                         sd_card->sd_erase_status = SD_NOT_ERASE;
1207                                         sd_card->sd_lock_notify = 1;
1208                                         chip->need_reinit |= SD_CARD;
1209                                 }
1210                         }
1211                 } else {
1212                         sd_card->sd_erase_status = SD_NOT_ERASE;
1213                 }
1214         }
1215 #endif
1216
1217         rtsx_init_cards(chip);
1218
1219         if (chip->ss_en) {
1220                 ss_allowed = 1;
1221
1222                 if (CHECK_PID(chip, 0x5288)) {
1223                         ss_allowed = 0;
1224                 } else {
1225                         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1226                                 u32 val;
1227                                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1228                                 if (val & 0x07) {
1229                                         ss_allowed = 0;
1230                                 }
1231                         }
1232                 }
1233         } else {
1234                 ss_allowed = 0;
1235         }
1236
1237         if (ss_allowed && !chip->sd_io) {
1238                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1239                         chip->ss_counter = 0;
1240                 } else {
1241                         if (chip->ss_counter <
1242                                 (chip->ss_idle_period / POLLING_INTERVAL)) {
1243                                 chip->ss_counter++;
1244                         } else {
1245                                 rtsx_exclusive_enter_ss(chip);
1246                                 return;
1247                         }
1248                 }
1249         }
1250
1251         if (CHECK_PID(chip, 0x5208)) {
1252                 rtsx_monitor_aspm_config(chip);
1253
1254 #ifdef SUPPORT_SDIO_ASPM
1255                 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) &&
1256                                 chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
1257                         if (chip->sd_io) {
1258                                 dynamic_configure_sdio_aspm(chip);
1259                         } else {
1260                                 if (!chip->sdio_aspm) {
1261                                         RTSX_DEBUGP("SDIO enter ASPM!\n");
1262                                         rtsx_write_register(chip,
1263                                                 ASPM_FORCE_CTL, 0xFC,
1264                                                 0x30 | (chip->aspm_level[1] << 2));
1265                                         chip->sdio_aspm = 1;
1266                                 }
1267                         }
1268                 }
1269 #endif
1270         }
1271
1272         if (chip->idle_counter < IDLE_MAX_COUNT) {
1273                 chip->idle_counter++;
1274         } else {
1275                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1276                         RTSX_DEBUGP("Idle state!\n");
1277                         rtsx_set_stat(chip, RTSX_STAT_IDLE);
1278
1279 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1280                         chip->led_toggle_counter = 0;
1281 #endif
1282                         rtsx_force_power_on(chip, SSC_PDCTL);
1283
1284                         turn_off_led(chip, LED_GPIO);
1285
1286                         if (chip->auto_power_down && !chip->card_ready && !chip->sd_io) {
1287                                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1288                         }
1289                 }
1290         }
1291
1292         switch (rtsx_get_stat(chip)) {
1293         case RTSX_STAT_RUN:
1294 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1295                 rtsx_blink_led(chip);
1296 #endif
1297                 do_remaining_work(chip);
1298                 break;
1299
1300         case RTSX_STAT_IDLE:
1301                 if (chip->sd_io && !chip->sd_int) {
1302                         try_to_switch_sdio_ctrl(chip);
1303                 }
1304                 rtsx_enable_aspm(chip);
1305                 break;
1306
1307         default:
1308                 break;
1309         }
1310
1311
1312 #ifdef SUPPORT_OCP
1313         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1314                 #if CONFIG_RTS_PSTOR_DEBUG
1315                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER)) {
1316                         RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
1317                 }
1318                 #endif
1319
1320                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1321                         if (chip->card_exist & SD_CARD) {
1322                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1323                                 card_power_off(chip, SD_CARD);
1324                                 chip->card_fail |= SD_CARD;
1325                         }
1326                 }
1327                 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
1328                         if (chip->card_exist & MS_CARD) {
1329                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1330                                 card_power_off(chip, MS_CARD);
1331                                 chip->card_fail |= MS_CARD;
1332                         }
1333                 }
1334         } else {
1335                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1336                         RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
1337                         if (chip->card_exist & SD_CARD) {
1338                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1339                                 chip->card_fail |= SD_CARD;
1340                         } else if (chip->card_exist & MS_CARD) {
1341                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1342                                 chip->card_fail |= MS_CARD;
1343                         } else if (chip->card_exist & XD_CARD) {
1344                                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1345                                 chip->card_fail |= XD_CARD;
1346                         }
1347                         card_power_off(chip, SD_CARD);
1348                 }
1349         }
1350 #endif
1351
1352 Delink_Stage:
1353         if (chip->auto_delink_en && chip->auto_delink_allowed &&
1354                         !chip->card_ready && !chip->card_ejected && !chip->sd_io) {
1355                 int enter_L1 = chip->auto_delink_in_L1 && (chip->aspm_l0s_l1_en || chip->ss_en);
1356                 int delink_stage1_cnt = chip->delink_stage1_step;
1357                 int delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1358                 int delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1359
1360                 if (chip->auto_delink_cnt <= delink_stage3_cnt) {
1361                         if (chip->auto_delink_cnt == delink_stage1_cnt) {
1362                                 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1363
1364                                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
1365                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1366                                 }
1367                                 if (chip->card_exist) {
1368                                         RTSX_DEBUGP("False card inserted, do force delink\n");
1369
1370                                         if (enter_L1) {
1371                                                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1372                                         }
1373                                         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1374
1375                                         if (enter_L1) {
1376                                                 rtsx_enter_L1(chip);
1377                                         }
1378
1379                                         chip->auto_delink_cnt = delink_stage3_cnt + 1;
1380                                 } else {
1381                                         RTSX_DEBUGP("No card inserted, do delink\n");
1382
1383                                         if (enter_L1) {
1384                                                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1385                                         }
1386 #ifdef HW_INT_WRITE_CLR
1387                                         if (CHECK_PID(chip, 0x5209)) {
1388                                                 rtsx_writel(chip, RTSX_BIPR, 0xFFFFFFFF);
1389                                                 RTSX_DEBUGP("RTSX_BIPR: 0x%x\n", rtsx_readl(chip, RTSX_BIPR));
1390                                         }
1391 #endif
1392                                         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0x02);
1393
1394                                         if (enter_L1) {
1395                                                 rtsx_enter_L1(chip);
1396                                         }
1397                                 }
1398                         }
1399
1400                         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1401                                 RTSX_DEBUGP("Try to do force delink\n");
1402
1403                                 if (enter_L1) {
1404                                         rtsx_exit_L1(chip);
1405                                 }
1406
1407                                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
1408                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1409                                 }
1410                                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1411                         }
1412
1413                         chip->auto_delink_cnt++;
1414                 }
1415         } else {
1416                 chip->auto_delink_cnt = 0;
1417         }
1418 }
1419
1420 void rtsx_undo_delink(struct rtsx_chip *chip)
1421 {
1422         chip->auto_delink_allowed = 0;
1423         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1424 }
1425
1426 /**
1427  * rtsx_stop_cmd - stop command transfer and DMA transfer
1428  * @chip: Realtek's card reader chip
1429  * @card: flash card type
1430  *
1431  * Stop command transfer and DMA transfer.
1432  * This function is called in error handler.
1433  */
1434 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1435 {
1436         int i;
1437
1438         for (i = 0; i <= 8; i++) {
1439                 int addr = RTSX_HCBAR + i * 4;
1440                 u32 reg;
1441                 reg = rtsx_readl(chip, addr);
1442                 RTSX_DEBUGP("BAR (0x%02x): 0x%08x\n", addr, reg);
1443         }
1444         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1445         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1446
1447         for (i = 0; i < 16; i++) {
1448                 u16 addr = 0xFE20 + (u16)i;
1449                 u8 val;
1450                 rtsx_read_register(chip, addr, &val);
1451                 RTSX_DEBUGP("0x%04X: 0x%02x\n", addr, val);
1452         }
1453
1454         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1455         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1456 }
1457
1458 #define MAX_RW_REG_CNT          1024
1459
1460 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1461 {
1462         int i;
1463         u32 val = 3 << 30;
1464
1465         val |= (u32)(addr & 0x3FFF) << 16;
1466         val |= (u32)mask << 8;
1467         val |= (u32)data;
1468
1469         rtsx_writel(chip, RTSX_HAIMR, val);
1470
1471         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1472                 val = rtsx_readl(chip, RTSX_HAIMR);
1473                 if ((val & (1 << 31)) == 0) {
1474                         if (data != (u8)val) {
1475                                 TRACE_RET(chip, STATUS_FAIL);
1476                         }
1477                         return STATUS_SUCCESS;
1478                 }
1479         }
1480
1481         TRACE_RET(chip, STATUS_TIMEDOUT);
1482 }
1483
1484 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1485 {
1486         u32 val = 2 << 30;
1487         int i;
1488
1489         if (data) {
1490                 *data = 0;
1491         }
1492
1493         val |= (u32)(addr & 0x3FFF) << 16;
1494
1495         rtsx_writel(chip, RTSX_HAIMR, val);
1496
1497         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1498                 val = rtsx_readl(chip, RTSX_HAIMR);
1499                 if ((val & (1 << 31)) == 0) {
1500                         break;
1501                 }
1502         }
1503
1504         if (i >= MAX_RW_REG_CNT) {
1505                 TRACE_RET(chip, STATUS_TIMEDOUT);
1506         }
1507
1508         if (data) {
1509                 *data = (u8)(val & 0xFF);
1510         }
1511
1512         return STATUS_SUCCESS;
1513 }
1514
1515 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val)
1516 {
1517         u8 mode = 0, tmp;
1518         int i;
1519
1520         for (i = 0; i < 4; i++) {
1521                 if (mask & 0xFF) {
1522                         RTSX_WRITE_REG(chip, CFGDATA0 + i,
1523                                        0xFF, (u8)(val & mask & 0xFF));
1524                         mode |= (1 << i);
1525                 }
1526                 mask >>= 8;
1527                 val >>= 8;
1528         }
1529
1530         if (mode) {
1531                 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1532                 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1533
1534                 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF,
1535                                0x80 | mode | ((func_no & 0x03) << 4));
1536
1537                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1538                         RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1539                         if ((tmp & 0x80) == 0) {
1540                                 break;
1541                         }
1542                 }
1543         }
1544
1545         return STATUS_SUCCESS;
1546 }
1547
1548 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1549 {
1550         int i;
1551         u8 tmp;
1552         u32 data = 0;
1553
1554         RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1555         RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1556         RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4));
1557
1558         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1559                 RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1560                 if ((tmp & 0x80) == 0) {
1561                         break;
1562                 }
1563         }
1564
1565         for (i = 0; i < 4; i++) {
1566                 RTSX_READ_REG(chip, CFGDATA0 + i, &tmp);
1567                 data |= (u32)tmp << (i * 8);
1568         }
1569
1570         if (val) {
1571                 *val = data;
1572         }
1573
1574         return STATUS_SUCCESS;
1575 }
1576
1577 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len)
1578 {
1579         u32 *data, *mask;
1580         u16 offset = addr % 4;
1581         u16 aligned_addr = addr - offset;
1582         int dw_len, i, j;
1583         int retval;
1584
1585         RTSX_DEBUGP("%s\n", __func__);
1586
1587         if (!buf) {
1588                 TRACE_RET(chip, STATUS_NOMEM);
1589         }
1590
1591         if ((len + offset) % 4) {
1592                 dw_len = (len + offset) / 4 + 1;
1593         } else {
1594                 dw_len = (len + offset) / 4;
1595         }
1596         RTSX_DEBUGP("dw_len = %d\n", dw_len);
1597
1598         data = (u32 *)vmalloc(dw_len * 4);
1599         if (!data) {
1600                 TRACE_RET(chip, STATUS_NOMEM);
1601         }
1602         memset(data, 0, dw_len * 4);
1603
1604         mask = (u32 *)vmalloc(dw_len * 4);
1605         if (!mask) {
1606                 vfree(data);
1607                 TRACE_RET(chip, STATUS_NOMEM);
1608         }
1609         memset(mask, 0, dw_len * 4);
1610
1611         j = 0;
1612         for (i = 0; i < len; i++) {
1613                 mask[j] |= 0xFF << (offset * 8);
1614                 data[j] |= buf[i] << (offset * 8);
1615                 if (++offset == 4) {
1616                         j++;
1617                         offset = 0;
1618                 }
1619         }
1620
1621         RTSX_DUMP(mask, dw_len * 4);
1622         RTSX_DUMP(data, dw_len * 4);
1623
1624         for (i = 0; i < dw_len; i++) {
1625                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4, mask[i], data[i]);
1626                 if (retval != STATUS_SUCCESS) {
1627                         vfree(data);
1628                         vfree(mask);
1629                         TRACE_RET(chip, STATUS_FAIL);
1630                 }
1631         }
1632
1633         vfree(data);
1634         vfree(mask);
1635
1636         return STATUS_SUCCESS;
1637 }
1638
1639 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len)
1640 {
1641         u32 *data;
1642         u16 offset = addr % 4;
1643         u16 aligned_addr = addr - offset;
1644         int dw_len, i, j;
1645         int retval;
1646
1647         RTSX_DEBUGP("%s\n", __func__);
1648
1649         if ((len + offset) % 4) {
1650                 dw_len = (len + offset) / 4 + 1;
1651         } else {
1652                 dw_len = (len + offset) / 4;
1653         }
1654         RTSX_DEBUGP("dw_len = %d\n", dw_len);
1655
1656         data = (u32 *)vmalloc(dw_len * 4);
1657         if (!data) {
1658                 TRACE_RET(chip, STATUS_NOMEM);
1659         }
1660
1661         for (i = 0; i < dw_len; i++) {
1662                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4, data + i);
1663                 if (retval != STATUS_SUCCESS) {
1664                         vfree(data);
1665                         TRACE_RET(chip, STATUS_FAIL);
1666                 }
1667         }
1668
1669         if (buf) {
1670                 j = 0;
1671
1672                 for (i = 0; i < len; i++) {
1673                         buf[i] = (u8)(data[j] >> (offset * 8));
1674                         if (++offset == 4) {
1675                                 j++;
1676                                 offset = 0;
1677                         }
1678                 }
1679         }
1680
1681         vfree(data);
1682
1683         return STATUS_SUCCESS;
1684 }
1685
1686 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1687 {
1688         int i, finished = 0;
1689         u8 tmp;
1690
1691         RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val);
1692         RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1693         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1694         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81);
1695
1696         for (i = 0; i < 100000; i++) {
1697                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1698                 if (!(tmp & 0x80)) {
1699                         finished = 1;
1700                         break;
1701                 }
1702         }
1703
1704         if (!finished) {
1705                 TRACE_RET(chip, STATUS_FAIL);
1706         }
1707
1708         return STATUS_SUCCESS;
1709 }
1710
1711 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1712 {
1713         int i, finished = 0;
1714         u16 data = 0;
1715         u8 tmp;
1716
1717         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1718         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80);
1719
1720         for (i = 0; i < 100000; i++) {
1721                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1722                 if (!(tmp & 0x80)) {
1723                         finished = 1;
1724                         break;
1725                 }
1726         }
1727
1728         if (!finished) {
1729                 TRACE_RET(chip, STATUS_FAIL);
1730         }
1731
1732         RTSX_READ_REG(chip, PHYDATA0, &tmp);
1733         data = tmp;
1734         RTSX_READ_REG(chip, PHYDATA1, &tmp);
1735         data |= (u16)tmp << 8;
1736
1737         if (val)
1738                 *val = data;
1739
1740         return STATUS_SUCCESS;
1741 }
1742
1743 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1744 {
1745         int i;
1746         u8 data = 0;
1747
1748         RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr);
1749
1750         for (i = 0; i < 100; i++) {
1751                 RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1752                 if (!(data & 0x80))
1753                         break;
1754                 udelay(1);
1755         }
1756
1757         if (data & 0x80) {
1758                 TRACE_RET(chip, STATUS_TIMEDOUT);
1759         }
1760
1761         RTSX_READ_REG(chip, EFUSE_DATA, &data);
1762         if (val)
1763                 *val = data;
1764
1765         return STATUS_SUCCESS;
1766 }
1767
1768 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1769 {
1770         int i, j;
1771         u8 data = 0, tmp = 0xFF;
1772
1773         for (i = 0; i < 8; i++) {
1774                 if (val & (u8)(1 << i))
1775                         continue;
1776
1777                 tmp &= (~(u8)(1 << i));
1778                 RTSX_DEBUGP("Write 0x%x to 0x%x\n", tmp, addr);
1779
1780                 RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp);
1781                 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr);
1782
1783                 for (j = 0; j < 100; j++) {
1784                         RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1785                         if (!(data & 0x80))
1786                                 break;
1787                         wait_timeout(3);
1788                 }
1789
1790                 if (data & 0x80) {
1791                         TRACE_RET(chip, STATUS_TIMEDOUT);
1792                 }
1793
1794                 wait_timeout(5);
1795         }
1796
1797         return STATUS_SUCCESS;
1798 }
1799
1800 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1801 {
1802         int retval;
1803         u16 value;
1804
1805         retval = rtsx_read_phy_register(chip, reg, &value);
1806         if (retval != STATUS_SUCCESS) {
1807                 TRACE_RET(chip, STATUS_FAIL);
1808         }
1809         if (value & (1 << bit)) {
1810                 value &= ~(1 << bit);
1811                 retval = rtsx_write_phy_register(chip, reg, value);
1812                 if (retval != STATUS_SUCCESS) {
1813                         TRACE_RET(chip, STATUS_FAIL);
1814                 }
1815         }
1816
1817         return STATUS_SUCCESS;
1818 }
1819
1820 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1821 {
1822         int retval;
1823         u16 value;
1824
1825         retval = rtsx_read_phy_register(chip, reg, &value);
1826         if (retval != STATUS_SUCCESS) {
1827                 TRACE_RET(chip, STATUS_FAIL);
1828         }
1829         if (0 == (value & (1 << bit))) {
1830                 value |= (1 << bit);
1831                 retval = rtsx_write_phy_register(chip, reg, value);
1832                 if (retval != STATUS_SUCCESS) {
1833                         TRACE_RET(chip, STATUS_FAIL);
1834                 }
1835         }
1836
1837         return STATUS_SUCCESS;
1838 }
1839
1840 int rtsx_check_link_ready(struct rtsx_chip *chip)
1841 {
1842         u8 val;
1843
1844         RTSX_READ_REG(chip, IRQSTAT0, &val);
1845
1846         RTSX_DEBUGP("IRQSTAT0: 0x%x\n", val);
1847         if (val & LINK_RDY_INT) {
1848                 RTSX_DEBUGP("Delinked!\n");
1849                 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1850                 return STATUS_FAIL;
1851         }
1852
1853         return STATUS_SUCCESS;
1854 }
1855
1856 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1857 {
1858         u32 ultmp;
1859
1860         RTSX_DEBUGP("%04x set pm_dstate to %d\n", chip->product_id, dstate);
1861
1862         if (CHK_SDIO_EXIST(chip)) {
1863                 u8 func_no;
1864
1865                 if (CHECK_PID(chip, 0x5288)) {
1866                         func_no = 2;
1867                 } else {
1868                         func_no = 1;
1869                 }
1870                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
1871                 RTSX_DEBUGP("pm_dstate of function %d: 0x%x\n", (int)func_no, ultmp);
1872                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
1873         }
1874
1875         rtsx_write_config_byte(chip, 0x44, dstate);
1876         rtsx_write_config_byte(chip, 0x45, 0);
1877 }
1878
1879 void rtsx_enter_L1(struct rtsx_chip *chip)
1880 {
1881         rtsx_handle_pm_dstate(chip, 2);
1882 }
1883
1884 void rtsx_exit_L1(struct rtsx_chip *chip)
1885 {
1886         rtsx_write_config_byte(chip, 0x44, 0);
1887         rtsx_write_config_byte(chip, 0x45, 0);
1888 }
1889
1890 void rtsx_enter_ss(struct rtsx_chip *chip)
1891 {
1892         RTSX_DEBUGP("Enter Selective Suspend State!\n");
1893
1894         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1895
1896         if (chip->power_down_in_ss) {
1897                 rtsx_power_off_card(chip);
1898                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1899         }
1900
1901         if (CHK_SDIO_EXIST(chip)) {
1902                 if (CHECK_PID(chip, 0x5288)) {
1903                         rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100);
1904                 } else {
1905                         rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100);
1906                 }
1907         }
1908
1909         if (chip->auto_delink_en) {
1910                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
1911         } else {
1912                 if (!chip->phy_debug_mode) {
1913                         u32 tmp;
1914                         tmp = rtsx_readl(chip, RTSX_BIER);
1915                         tmp |= CARD_INT;
1916                         rtsx_writel(chip, RTSX_BIER, tmp);
1917                 }
1918
1919                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
1920         }
1921
1922         rtsx_enter_L1(chip);
1923
1924         RTSX_CLR_DELINK(chip);
1925         rtsx_set_stat(chip, RTSX_STAT_SS);
1926 }
1927
1928 void rtsx_exit_ss(struct rtsx_chip *chip)
1929 {
1930         RTSX_DEBUGP("Exit Selective Suspend State!\n");
1931
1932         rtsx_exit_L1(chip);
1933
1934         if (chip->power_down_in_ss) {
1935                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
1936                 udelay(1000);
1937         }
1938
1939         if (RTSX_TST_DELINK(chip)) {
1940                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1941                 rtsx_reinit_cards(chip, 1);
1942                 RTSX_CLR_DELINK(chip);
1943         } else if (chip->power_down_in_ss) {
1944                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1945                 rtsx_reinit_cards(chip, 0);
1946         }
1947 }
1948
1949 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
1950 {
1951         u32 status, int_enable;
1952         int exit_ss = 0;
1953 #ifdef SUPPORT_OCP
1954         u32 ocp_int = 0;
1955
1956         if (CHECK_PID(chip, 0x5209)) {
1957                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1958                         ocp_int = MS_OC_INT | SD_OC_INT;
1959                 } else {
1960                         ocp_int = SD_OC_INT;
1961                 }
1962         } else {
1963                 ocp_int = OC_INT;
1964         }
1965 #endif
1966
1967         if (chip->ss_en) {
1968                 chip->ss_counter = 0;
1969                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
1970                         exit_ss = 1;
1971                         rtsx_exit_L1(chip);
1972                         rtsx_set_stat(chip, RTSX_STAT_RUN);
1973                 }
1974         }
1975
1976         int_enable = rtsx_readl(chip, RTSX_BIER);
1977         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
1978
1979 #ifdef HW_INT_WRITE_CLR
1980         if (CHECK_PID(chip, 0x5209)) {
1981                 rtsx_writel(chip, RTSX_BIPR, chip->int_reg);
1982         }
1983 #endif
1984
1985         if (((chip->int_reg & int_enable) == 0) || (chip->int_reg == 0xFFFFFFFF))
1986                 return STATUS_FAIL;
1987
1988         if (!chip->msi_en) {
1989                 if (CHECK_PID(chip, 0x5209)) {
1990                         u8 val;
1991                         rtsx_read_config_byte(chip, 0x05, &val);
1992                         if (val & 0x04) {
1993                                 return STATUS_FAIL;
1994                         }
1995                 }
1996         }
1997
1998         status = chip->int_reg &= (int_enable | 0x7FFFFF);
1999
2000         if (status & CARD_INT) {
2001                 chip->auto_delink_cnt = 0;
2002
2003                 if (status & SD_INT) {
2004                         if (status & SD_EXIST) {
2005                                 set_bit(SD_NR, &(chip->need_reset));
2006                         } else {
2007                                 set_bit(SD_NR, &(chip->need_release));
2008                                 chip->sd_reset_counter = 0;
2009                                 chip->sd_show_cnt = 0;
2010                                 clear_bit(SD_NR, &(chip->need_reset));
2011                         }
2012                 } else {
2013                         /* If multi-luns, it's possible that
2014                            when plugging/unplugging one card
2015                            there is another card which still
2016                            exists in the slot. In this case,
2017                            all existed cards should be reset.
2018                         */
2019                         if (exit_ss && (status & SD_EXIST))
2020                                 set_bit(SD_NR, &(chip->need_reinit));
2021                 }
2022                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
2023                         if (status & XD_INT) {
2024                                 if (status & XD_EXIST) {
2025                                         set_bit(XD_NR, &(chip->need_reset));
2026                                 } else {
2027                                         set_bit(XD_NR, &(chip->need_release));
2028                                         chip->xd_reset_counter = 0;
2029                                         chip->xd_show_cnt = 0;
2030                                         clear_bit(XD_NR, &(chip->need_reset));
2031                                 }
2032                         } else {
2033                                 if (exit_ss && (status & XD_EXIST))
2034                                         set_bit(XD_NR, &(chip->need_reinit));
2035                         }
2036                 }
2037                 if (status & MS_INT) {
2038                         if (status & MS_EXIST) {
2039                                 set_bit(MS_NR, &(chip->need_reset));
2040                         } else {
2041                                 set_bit(MS_NR, &(chip->need_release));
2042                                 chip->ms_reset_counter = 0;
2043                                 chip->ms_show_cnt = 0;
2044                                 clear_bit(MS_NR, &(chip->need_reset));
2045                         }
2046                 } else {
2047                         if (exit_ss && (status & MS_EXIST))
2048                                 set_bit(MS_NR, &(chip->need_reinit));
2049                 }
2050         }
2051
2052 #ifdef SUPPORT_OCP
2053         chip->ocp_int = ocp_int & status;
2054 #endif
2055
2056         if (chip->sd_io) {
2057                 if (chip->int_reg & DATA_DONE_INT)
2058                         chip->int_reg &= ~(u32)DATA_DONE_INT;
2059         }
2060
2061         return STATUS_SUCCESS;
2062 }
2063
2064 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2065 {
2066         int retval;
2067
2068         RTSX_DEBUGP("rtsx_do_before_power_down, pm_stat = %d\n", pm_stat);
2069
2070         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2071
2072         retval = rtsx_force_power_on(chip, SSC_PDCTL);
2073         if (retval != STATUS_SUCCESS)
2074                 return;
2075
2076         rtsx_release_cards(chip);
2077         rtsx_disable_bus_int(chip);
2078         turn_off_led(chip, LED_GPIO);
2079
2080 #ifdef HW_AUTO_SWITCH_SD_BUS
2081         if (chip->sd_io) {
2082                 chip->sdio_in_charge = 1;
2083                 if (CHECK_PID(chip, 0x5208)) {
2084                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2085                         /* Enable sdio_bus_auto_switch */
2086                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2087                 } else if (CHECK_PID(chip, 0x5288)) {
2088                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2089                         /* Enable sdio_bus_auto_switch */
2090                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2091                 } else if (CHECK_PID(chip, 0x5209)) {
2092                         rtsx_write_register(chip, TLPTISTAT, 0x10, 0x10);
2093                         /* Enable sdio_bus_auto_switch */
2094                         rtsx_write_register(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, SDIO_BUS_AUTO_SWITCH);
2095                 }
2096         }
2097 #endif
2098
2099         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2100                 /* u_force_clkreq_0 */
2101                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2102         } else if (CHECK_PID(chip, 0x5209)) {
2103                 /* u_force_clkreq_0 */
2104                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2105         }
2106
2107         if (pm_stat == PM_S1) {
2108                 RTSX_DEBUGP("Host enter S1\n");
2109                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, HOST_ENTER_S1);
2110         } else if (pm_stat == PM_S3) {
2111                 if (chip->s3_pwr_off_delay > 0) {
2112                         wait_timeout(chip->s3_pwr_off_delay);
2113                 }
2114                 RTSX_DEBUGP("Host enter S3\n");
2115                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, HOST_ENTER_S3);
2116         }
2117
2118         if (chip->do_delink_before_power_down && chip->auto_delink_en) {
2119                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2120         }
2121
2122         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2123
2124         chip->cur_clk = 0;
2125         chip->cur_card = 0;
2126         chip->card_exist = 0;
2127 }
2128
2129 void rtsx_enable_aspm(struct rtsx_chip *chip)
2130 {
2131         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
2132                 if (!chip->aspm_enabled) {
2133                         RTSX_DEBUGP("Try to enable ASPM\n");
2134                         chip->aspm_enabled = 1;
2135
2136                         if (chip->asic_code && CHECK_PID(chip, 0x5208))
2137                                 rtsx_write_phy_register(chip, 0x07, 0);
2138                         if (CHECK_PID(chip, 0x5208)) {
2139                                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2140                                         0x30 | chip->aspm_level[0]);
2141                         } else {
2142                                 rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
2143                         }
2144
2145                         if (CHK_SDIO_EXIST(chip)) {
2146                                 u16 val = chip->aspm_l0s_l1_en | 0x0100;
2147                                 if (CHECK_PID(chip, 0x5288)) {
2148                                         rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, val);
2149                                 } else {
2150                                         rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFFFF, val);
2151                                 }
2152                         }
2153                 }
2154         }
2155
2156         return;
2157 }
2158
2159 void rtsx_disable_aspm(struct rtsx_chip *chip)
2160 {
2161         if (CHECK_PID(chip, 0x5208))
2162                 rtsx_monitor_aspm_config(chip);
2163
2164         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
2165                 if (chip->aspm_enabled) {
2166                         RTSX_DEBUGP("Try to disable ASPM\n");
2167                         chip->aspm_enabled = 0;
2168
2169                         if (chip->asic_code && CHECK_PID(chip, 0x5208))
2170                                 rtsx_write_phy_register(chip, 0x07, 0x0129);
2171                         if (CHECK_PID(chip, 0x5208)) {
2172                                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, 0x30);
2173                         } else {
2174                                 rtsx_write_config_byte(chip, LCTLR, 0x00);
2175                         }
2176                         wait_timeout(1);
2177                 }
2178         }
2179
2180         return;
2181 }
2182
2183 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2184 {
2185         int retval;
2186         int i, j;
2187         u16 reg_addr;
2188         u8 *ptr;
2189
2190         if (!buf) {
2191                 TRACE_RET(chip, STATUS_ERROR);
2192         }
2193
2194         ptr = buf;
2195         reg_addr = PPBUF_BASE2;
2196         for (i = 0; i < buf_len/256; i++) {
2197                 rtsx_init_cmd(chip);
2198
2199                 for (j = 0; j < 256; j++)
2200                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2201
2202                 retval = rtsx_send_cmd(chip, 0, 250);
2203                 if (retval < 0) {
2204                         TRACE_RET(chip, STATUS_FAIL);
2205                 }
2206
2207                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2208                 ptr += 256;
2209         }
2210
2211         if (buf_len%256) {
2212                 rtsx_init_cmd(chip);
2213
2214                 for (j = 0; j < buf_len%256; j++)
2215                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2216
2217                 retval = rtsx_send_cmd(chip, 0, 250);
2218                 if (retval < 0) {
2219                         TRACE_RET(chip, STATUS_FAIL);
2220                 }
2221         }
2222
2223         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
2224
2225         return STATUS_SUCCESS;
2226 }
2227
2228 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2229 {
2230         int retval;
2231         int i, j;
2232         u16 reg_addr;
2233         u8 *ptr;
2234
2235         if (!buf) {
2236                 TRACE_RET(chip, STATUS_ERROR);
2237         }
2238
2239         ptr = buf;
2240         reg_addr = PPBUF_BASE2;
2241         for (i = 0; i < buf_len/256; i++) {
2242                 rtsx_init_cmd(chip);
2243
2244                 for (j = 0; j < 256; j++) {
2245                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr);
2246                         ptr++;
2247                 }
2248
2249                 retval = rtsx_send_cmd(chip, 0, 250);
2250                 if (retval < 0) {
2251                         TRACE_RET(chip, STATUS_FAIL);
2252                 }
2253         }
2254
2255         if (buf_len%256) {
2256                 rtsx_init_cmd(chip);
2257
2258                 for (j = 0; j < buf_len%256; j++) {
2259                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr);
2260                         ptr++;
2261                 }
2262
2263                 retval = rtsx_send_cmd(chip, 0, 250);
2264                 if (retval < 0) {
2265                         TRACE_RET(chip, STATUS_FAIL);
2266                 }
2267         }
2268
2269         return STATUS_SUCCESS;
2270 }
2271
2272 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2273 {
2274         if (rtsx_readl(chip, 0) == 0xFFFFFFFF) {
2275                 TRACE_RET(chip, STATUS_FAIL);
2276         }
2277
2278         return STATUS_SUCCESS;
2279 }
2280
2281 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2282 {
2283         int retval;
2284         u8 mask = 0;
2285
2286         if (ctl & SSC_PDCTL)
2287                 mask |= SSC_POWER_DOWN;
2288
2289 #ifdef SUPPORT_OCP
2290         if (ctl & OC_PDCTL) {
2291                 mask |= SD_OC_POWER_DOWN;
2292                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
2293                         mask |= MS_OC_POWER_DOWN;
2294                 }
2295         }
2296 #endif
2297
2298         if (mask) {
2299                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2300                 if (retval != STATUS_SUCCESS) {
2301                         TRACE_RET(chip, STATUS_FAIL);
2302                 }
2303
2304                 if (CHECK_PID(chip, 0x5288))
2305                         wait_timeout(200);
2306         }
2307
2308         return STATUS_SUCCESS;
2309 }
2310
2311 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2312 {
2313         int retval;
2314         u8 mask = 0, val = 0;
2315
2316         if (ctl & SSC_PDCTL)
2317                 mask |= SSC_POWER_DOWN;
2318
2319 #ifdef SUPPORT_OCP
2320         if (ctl & OC_PDCTL) {
2321                 mask |= SD_OC_POWER_DOWN;
2322                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2323                         mask |= MS_OC_POWER_DOWN;
2324         }
2325 #endif
2326
2327         if (mask) {
2328                 val = mask;
2329                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2330                 if (retval != STATUS_SUCCESS) {
2331                         TRACE_RET(chip, STATUS_FAIL);
2332                 }
2333         }
2334
2335         return STATUS_SUCCESS;
2336 }