drivers/staging/rtl8712/rtl8712_spec.h

   1 #ifndef __RTL8712_SPEC_H__
   2 #define __RTL8712_SPEC_H__
   3
   4 #define RTL8712_IOBASE_TXPKT            0x10200000      /*IOBASE_TXPKT*/
   5 #define RTL8712_IOBASE_RXPKT            0x10210000      /*IOBASE_RXPKT*/
   6 #define RTL8712_IOBASE_RXCMD            0x10220000      /*IOBASE_RXCMD*/
   7 #define RTL8712_IOBASE_TXSTATUS         0x10230000      /*IOBASE_TXSTATUS*/
   8 #define RTL8712_IOBASE_RXSTATUS         0x10240000      /*IOBASE_RXSTATUS*/
   9 #define RTL8712_IOBASE_IOREG            0x10250000      /*IOBASE_IOREG ADDR*/
  10 #define RTL8712_IOBASE_SCHEDULER        0x10260000      /*IOBASE_SCHEDULE*/
  11
  12 #define RTL8712_IOBASE_TRXDMA           0x10270000      /*IOBASE_TRXDMA*/
  13 #define RTL8712_IOBASE_TXLLT            0x10280000      /*IOBASE_TXLLT*/
  14 #define RTL8712_IOBASE_WMAC             0x10290000      /*IOBASE_WMAC*/
  15 #define RTL8712_IOBASE_FW2HW            0x102A0000      /*IOBASE_FW2HW*/
  16 #define RTL8712_IOBASE_ACCESS_PHYREG    0x102B0000      /*IOBASE_ACCESS_PHYREG*/
  17
  18 #define RTL8712_IOBASE_FF       0x10300000 /*IOBASE_FIFO 0x1031000~0x103AFFFF*/
  19
  20
  21 /*IOREG Offset for 8712*/
  22 #define RTL8712_SYSCFG_         RTL8712_IOBASE_IOREG
  23 #define RTL8712_CMDCTRL_        (RTL8712_IOBASE_IOREG + 0x40)
  24 #define RTL8712_MACIDSETTING_   (RTL8712_IOBASE_IOREG + 0x50)
  25 #define RTL8712_TIMECTRL_       (RTL8712_IOBASE_IOREG + 0x80)
  26 #define RTL8712_FIFOCTRL_       (RTL8712_IOBASE_IOREG + 0xA0)
  27 #define RTL8712_RATECTRL_       (RTL8712_IOBASE_IOREG + 0x160)
  28 #define RTL8712_EDCASETTING_    (RTL8712_IOBASE_IOREG + 0x1D0)
  29 #define RTL8712_WMAC_           (RTL8712_IOBASE_IOREG + 0x200)
  30 #define RTL8712_SECURITY_       (RTL8712_IOBASE_IOREG + 0x240)
  31 #define RTL8712_POWERSAVE_      (RTL8712_IOBASE_IOREG + 0x260)
  32 #define RTL8712_GP_             (RTL8712_IOBASE_IOREG + 0x2E0)
  33 #define RTL8712_INTERRUPT_      (RTL8712_IOBASE_IOREG + 0x300)
  34 #define RTL8712_DEBUGCTRL_      (RTL8712_IOBASE_IOREG + 0x310)
  35 #define RTL8712_OFFLOAD_        (RTL8712_IOBASE_IOREG + 0x2D0)
  36
  37
  38 /*FIFO for 8712*/
  39 #define RTL8712_DMA_BCNQ        (RTL8712_IOBASE_FF + 0x10000)
  40 #define RTL8712_DMA_MGTQ        (RTL8712_IOBASE_FF + 0x20000)
  41 #define RTL8712_DMA_BMCQ        (RTL8712_IOBASE_FF + 0x30000)
  42 #define RTL8712_DMA_VOQ         (RTL8712_IOBASE_FF + 0x40000)
  43 #define RTL8712_DMA_VIQ         (RTL8712_IOBASE_FF + 0x50000)
  44 #define RTL8712_DMA_BEQ         (RTL8712_IOBASE_FF + 0x60000)
  45 #define RTL8712_DMA_BKQ         (RTL8712_IOBASE_FF + 0x70000)
  46 #define RTL8712_DMA_RX0FF       (RTL8712_IOBASE_FF + 0x80000)
  47 #define RTL8712_DMA_H2CCMD      (RTL8712_IOBASE_FF + 0x90000)
  48 #define RTL8712_DMA_C2HCMD      (RTL8712_IOBASE_FF + 0xA0000)
  49
  50
  51 /*------------------------------*/
  52
  53 /*BIT 16 15*/
  54 #define DID_SDIO_LOCAL                  0       /* 0 0*/
  55 #define DID_WLAN_IOREG                  1       /* 0 1*/
  56 #define DID_WLAN_FIFO                   3       /* 1 1*/
  57 #define   DID_UNDEFINE                          (-1)
  58
  59 #define CMD_ADDR_MAPPING_SHIFT          2       /*SDIO CMD ADDR MAPPING,
  60                                                  *shift 2 bit for match
  61                                                  * offset[14:2]*/
  62
  63 /*Offset for SDIO LOCAL*/
  64 #define OFFSET_SDIO_LOCAL                               0x0FFF
  65
  66 /*Offset for WLAN IOREG*/
  67 #define OFFSET_WLAN_IOREG                               0x0FFF
  68
  69 /*Offset for WLAN FIFO*/
  70 #define OFFSET_TX_BCNQ                          0x0300
  71 #define OFFSET_TX_HIQ                                   0x0310
  72 #define OFFSET_TX_CMDQ                          0x0320
  73 #define OFFSET_TX_MGTQ                          0x0330
  74 #define OFFSET_TX_HCCAQ                         0x0340
  75 #define OFFSET_TX_VOQ                                   0x0350
  76 #define OFFSET_TX_VIQ                                   0x0360
  77 #define OFFSET_TX_BEQ                                   0x0370
  78 #define OFFSET_TX_BKQ                                   0x0380
  79 #define OFFSET_RX_RX0FFQ                                0x0390
  80 #define OFFSET_RX_C2HFFQ                                0x03A0
  81
  82 #define BK_QID_01       1
  83 #define BK_QID_02       2
  84 #define BE_QID_01       0
  85 #define BE_QID_02       3
  86 #define VI_QID_01       4
  87 #define VI_QID_02       5
  88 #define VO_QID_01       6
  89 #define VO_QID_02       7
  90 #define HCCA_QID_01     8
  91 #define HCCA_QID_02     9
  92 #define HCCA_QID_03     10
  93 #define HCCA_QID_04     11
  94 #define HCCA_QID_05     12
  95 #define HCCA_QID_06     13
  96 #define HCCA_QID_07     14
  97 #define HCCA_QID_08     15
  98 #define HI_QID          17
  99 #define CMD_QID 19
 100 #define MGT_QID 18
 101 #define BCN_QID 16
 102
 103 #include "rtl8712_regdef.h"
 104
 105 #include "rtl8712_bitdef.h"
 106
 107 #include "basic_types.h"
 108
 109 #endif /* __RTL8712_SPEC_H__ */
 110