2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
14 We want to tanks the Authors of those projects and the Ndiswrapper
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 //#include <linux/config.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/netdevice.h>
30 //#include <linux/pci.h>
31 #include <linux/usb.h>
32 #include <linux/etherdevice.h>
33 #include <linux/delay.h>
34 #include <linux/rtnetlink.h> //for rtnl_lock()
35 #include <linux/wireless.h>
36 #include <linux/timer.h>
37 #include <linux/proc_fs.h> // Necessary because we use the proc fs
38 #include <linux/if_arp.h>
39 #include <linux/random.h>
40 #include <linux/version.h>
43 #include "ieee80211/ieee80211.h"
45 #include "r8192S_firmware.h"
46 #include "r8192SU_led.h"
48 /* EEPROM defs for use with linux/eeprom_93cx6.h */
49 #define RTL819X_EEPROM_CMD_READ (1 << 0)
50 #define RTL819X_EEPROM_CMD_WRITE (1 << 1)
51 #define RTL819X_EEPROM_CMD_CK (1 << 2)
52 #define RTL819X_EEPROM_CMD_CS (1 << 3)
55 #define RTL819xU_MODULE_NAME "rtl819xU"
56 //added for HW security, john.0629
59 #define MAX_KEY_LEN 61
60 #define KEY_BUF_SIZE 5
62 #define BIT0 0x00000001
63 #define BIT1 0x00000002
64 #define BIT2 0x00000004
65 #define BIT3 0x00000008
66 #define BIT4 0x00000010
67 #define BIT5 0x00000020
68 #define BIT6 0x00000040
69 #define BIT7 0x00000080
70 #define BIT8 0x00000100
71 #define BIT9 0x00000200
72 #define BIT10 0x00000400
73 #define BIT11 0x00000800
74 #define BIT12 0x00001000
75 #define BIT13 0x00002000
76 #define BIT14 0x00004000
77 #define BIT15 0x00008000
78 #define BIT16 0x00010000
79 #define BIT17 0x00020000
80 #define BIT18 0x00040000
81 #define BIT19 0x00080000
82 #define BIT20 0x00100000
83 #define BIT21 0x00200000
84 #define BIT22 0x00400000
85 #define BIT23 0x00800000
86 #define BIT24 0x01000000
87 #define BIT25 0x02000000
88 #define BIT26 0x04000000
89 #define BIT27 0x08000000
90 #define BIT28 0x10000000
91 #define BIT29 0x20000000
92 #define BIT30 0x40000000
93 #define BIT31 0x80000000
96 #define Rx_Smooth_Factor 20
98 #define DMESGW(x,a...)
99 #define DMESGE(x,a...)
100 extern u32 rt_global_debug_component;
101 #define RT_TRACE(component, x, args...) \
102 do { if(rt_global_debug_component & component) \
103 printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
106 //----------------------------------------------------------------------
107 //// Get 8192SU Rx descriptor. Added by Roger, 2008.04.15.
108 ////----------------------------------------------------------------------
109 #define RX_DESC_SIZE 24
110 #define RX_DRV_INFO_SIZE_UNIT 8
112 #define IS_UNDER_11N_AES_MODE(_ieee) ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\
113 (_ieee->pairwise_key_type==KEY_TYPE_CCMP))
115 #define COMP_TRACE BIT0 // For function call tracing.
116 #define COMP_DBG BIT1 // Only for temporary debug message.
117 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
120 #define COMP_RECV BIT3 // Reveive part data path.
121 #define COMP_SEND BIT4 // Send part path.
122 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
123 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
124 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
125 #define COMP_SWBW BIT8 // For bandwidth switch.
126 #define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING
127 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
128 #define COMP_QOS BIT11 // For QoS.
129 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
130 #define COMP_LPS BIT13 // For Radio Measurement.
131 #define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
132 #define COMP_PHY BIT15
133 #define COMP_CH BIT16 //channel setting debug
134 #define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
135 #define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
136 #define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko.
137 #define COMP_SEC BIT20 // Event handling
138 #define COMP_LED BIT21 // For LED.
139 #define COMP_RF BIT22 // For RF.
140 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
141 #define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
142 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
143 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
145 #define COMP_FIRMWARE BIT24 //for firmware downloading
146 #define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11
147 #define COMP_AMSDU BIT26 // For A-MSDU Debugging
149 #define COMP_SCAN BIT27
150 #define COMP_CMD BIT28
151 #define COMP_DOWN BIT29 //for rm driver module
152 #define COMP_RESET BIT30 //for silent reset
153 #define COMP_ERR BIT31 //for error out, always on
155 #define RTL819x_DEBUG
157 #define assert(expr) \
159 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
160 #expr,__FILE__,__FUNCTION__,__LINE__); \
162 //wb added to debug out data buf
163 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
164 #define RT_DEBUG_DATA(level, data, datalen) \
165 do{ if ((rt_global_debug_component & (level)) == (level)) \
168 u8* pdata = (u8*) data; \
169 printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \
170 for(i=0; i<(int)(datalen); i++) \
172 printk("%2x ", pdata[i]); \
173 if ((i+1)%16 == 0) printk("\n"); \
179 #define assert(expr) do {} while (0)
180 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
181 #endif /* RTL8169_DEBUG */
184 //2TODO: We should define 8192S firmware related macro settings here!!
185 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
186 #define RTL819X_TOTAL_RF_PATH 2
188 //#define Rtl819XFwBootArray Rtl8192UsbFwBootArray
189 //#define Rtl819XFwMainArray Rtl8192UsbFwMainArray
190 //#define Rtl819XFwDataArray Rtl8192UsbFwDataArray
192 #define Rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
193 #define Rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
194 #define Rtl819XPHY_REGArray Rtl8192UsbPHY_REGArray
195 #define Rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
196 //#define Rtl819XRadioA_Array Rtl8192UsbRadioA_Array
197 //#define Rtl819XRadioB_Array Rtl8192UsbRadioB_Array
198 #define Rtl819XRadioC_Array Rtl8192UsbRadioC_Array
199 #define Rtl819XRadioD_Array Rtl8192UsbRadioD_Array
202 #define Rtl819XFwImageArray Rtl8192SUFwImgArray
203 #define Rtl819XMAC_Array Rtl8192SUMAC_2T_Array
204 #define Rtl819XAGCTAB_Array Rtl8192SUAGCTAB_Array
205 #define Rtl819XPHY_REG_Array Rtl8192SUPHY_REG_2T2RArray
206 #define Rtl819XPHY_REG_to1T1R_Array Rtl8192SUPHY_ChangeTo_1T1RArray
207 #define Rtl819XPHY_REG_to1T2R_Array Rtl8192SUPHY_ChangeTo_1T2RArray
208 #define Rtl819XPHY_REG_to2T2R_Array Rtl8192SUPHY_ChangeTo_2T2RArray
209 #define Rtl819XPHY_REG_Array_PG Rtl8192SUPHY_REG_Array_PG
210 #define Rtl819XRadioA_Array Rtl8192SURadioA_1T_Array
211 #define Rtl819XRadioB_Array Rtl8192SURadioB_Array
212 #define Rtl819XRadioB_GM_Array Rtl8192SURadioB_GM_Array
213 #define Rtl819XRadioA_to1T_Array Rtl8192SURadioA_to1T_Array
214 #define Rtl819XRadioA_to2T_Array Rtl8192SURadioA_to2T_Array
218 // Queue Select Value in TxDesc
224 #define QSLT_BEACON 0x10
225 #define QSLT_HIGH 0x11
226 #define QSLT_MGNT 0x12
227 #define QSLT_CMD 0x13
229 #define DESC90_RATE1M 0x00
230 #define DESC90_RATE2M 0x01
231 #define DESC90_RATE5_5M 0x02
232 #define DESC90_RATE11M 0x03
233 #define DESC90_RATE6M 0x04
234 #define DESC90_RATE9M 0x05
235 #define DESC90_RATE12M 0x06
236 #define DESC90_RATE18M 0x07
237 #define DESC90_RATE24M 0x08
238 #define DESC90_RATE36M 0x09
239 #define DESC90_RATE48M 0x0a
240 #define DESC90_RATE54M 0x0b
241 #define DESC90_RATEMCS0 0x00
242 #define DESC90_RATEMCS1 0x01
243 #define DESC90_RATEMCS2 0x02
244 #define DESC90_RATEMCS3 0x03
245 #define DESC90_RATEMCS4 0x04
246 #define DESC90_RATEMCS5 0x05
247 #define DESC90_RATEMCS6 0x06
248 #define DESC90_RATEMCS7 0x07
249 #define DESC90_RATEMCS8 0x08
250 #define DESC90_RATEMCS9 0x09
251 #define DESC90_RATEMCS10 0x0a
252 #define DESC90_RATEMCS11 0x0b
253 #define DESC90_RATEMCS12 0x0c
254 #define DESC90_RATEMCS13 0x0d
255 #define DESC90_RATEMCS14 0x0e
256 #define DESC90_RATEMCS15 0x0f
257 #define DESC90_RATEMCS32 0x20
260 // CCK Rates, TxHT = 0
261 #define DESC92S_RATE1M 0x00
262 #define DESC92S_RATE2M 0x01
263 #define DESC92S_RATE5_5M 0x02
264 #define DESC92S_RATE11M 0x03
266 // OFDM Rates, TxHT = 0
267 #define DESC92S_RATE6M 0x04
268 #define DESC92S_RATE9M 0x05
269 #define DESC92S_RATE12M 0x06
270 #define DESC92S_RATE18M 0x07
271 #define DESC92S_RATE24M 0x08
272 #define DESC92S_RATE36M 0x09
273 #define DESC92S_RATE48M 0x0a
274 #define DESC92S_RATE54M 0x0b
276 // MCS Rates, TxHT = 1
277 #define DESC92S_RATEMCS0 0x0c
278 #define DESC92S_RATEMCS1 0x0d
279 #define DESC92S_RATEMCS2 0x0e
280 #define DESC92S_RATEMCS3 0x0f
281 #define DESC92S_RATEMCS4 0x10
282 #define DESC92S_RATEMCS5 0x11
283 #define DESC92S_RATEMCS6 0x12
284 #define DESC92S_RATEMCS7 0x13
285 #define DESC92S_RATEMCS8 0x14
286 #define DESC92S_RATEMCS9 0x15
287 #define DESC92S_RATEMCS10 0x16
288 #define DESC92S_RATEMCS11 0x17
289 #define DESC92S_RATEMCS12 0x18
290 #define DESC92S_RATEMCS13 0x19
291 #define DESC92S_RATEMCS14 0x1a
292 #define DESC92S_RATEMCS15 0x1b
293 #define DESC92S_RATEMCS15_SG 0x1c
294 #define DESC92S_RATEMCS32 0x20
297 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
299 #define IEEE80211_WATCH_DOG_TIME 2000
300 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
301 //for txpowertracking by amy
302 #define OFDM_Table_Length 19
303 #define CCK_Table_length 12
306 //Tx Descriptor for RLT8192SU(Normal mode)
308 typedef struct _tx_desc_819x_usb {
312 u8 Type:2; // Reserved for MAC header Frame Type subfield.
336 u8 PktOffset:5; //padding_len (hw)
343 u32 RTSRC:6; // Reserved for HW RTS Retry Count.
344 u32 DATARC:6; // Reserved for HW DATA Retry Count.
346 u32 AllowAggregation:1;
347 u32 BK:1; //Aggregation break.
351 u8 NextHeadPage;//:8;
362 u32 RaBRSRID:3; //Rate adaptive BRSR ID.
364 u32 TxShort:1;//for data
387 //u16 TxBuffSize;//:16;//pcie
392 }tx_desc_819x_usb, *ptx_desc_819x_usb;
393 typedef struct _tx_status_desc_8192s_usb{
421 }tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb;
426 //Tx Descriptor for RLT8192SU(Load FW mode)
428 typedef struct _tx_desc_cmd_819x_usb{
437 // DWORD 1, 2, 3, 4, 5, 6 are all reserved.
446 u16 TxBuffSize;//pcie
448 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
450 //H2C Command for RLT8192SU(Host TxCmd)
452 typedef struct _tx_h2c_desc_cmd_8192s_usb{
477 }tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb;
480 typedef struct _tx_h2c_cmd_hdr_8192s_usb{
488 }tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb;
490 typedef struct _tx_fwinfo_819x_usb{
497 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
498 u8 TxBandwidth:1; // This is used for HT MCS rate only.
499 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
501 u8 AllowAggregation:1;
502 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
503 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
504 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
505 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
507 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
513 u32 TxAGCOffSet:4;//TxAGCOffset:4;
517 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
519 typedef struct rtl8192_rx_info {
521 struct net_device *dev;
525 //typedef struct _RX_DESC_STATUS_8192SU{
526 typedef struct rx_desc_819x_usb{
585 //}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU;
586 }rx_desc_819x_usb, *prx_desc_819x_usb;
590 // Driver info are written to the begining of the RxBuffer
592 //typedef struct _RX_DRIVER_INFO_8192S{
593 typedef struct rx_drvinfo_819x_usb{
595 // Driver info contain PHY status and other variabel size info
596 // PHY Status content as below
622 u4Byte cfotail_2:8;*/
626 /*u4Byte cfotail_3:8;
642 u4Byte csi_current_0:8;
643 u4Byte csi_current_1:8;
644 u4Byte csi_target_0:8;*/
649 /*u4Byte csi_target_1:8;
652 u4Byte ex_intf_flag:1;
663 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
665 #define HWSET_MAX_SIZE_92S 128
666 #define MAX_802_11_HEADER_LENGTH 40
667 #define MAX_PKT_AGG_NUM 256
668 #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN
670 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
671 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
672 //#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
673 #define ENCRYPTION_MAX_OVERHEAD 128
674 #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
675 //#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
676 #define MAX_FRAGMENT_COUNT 8
678 #define MAX_TRANSMIT_BUFFER_SIZE 8000
680 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
682 #define scrclng 4 // octets for crc32 (FCS, ICV)
684 typedef enum rf_optype
686 RF_OP_By_SW_3wire = 0,
690 /* 8190 Loopback Mode definition */
691 typedef enum _rtl819xUsb_loopback{
692 RTL819xU_NO_LOOPBACK = 0,
693 RTL819xU_MAC_LOOPBACK = 1,
694 RTL819xU_DMA_LOOPBACK = 2,
695 RTL819xU_CCK_LOOPBACK = 3,
696 }rtl819xUsb_loopback_e;
699 typedef enum _RT_STATUS{
700 RT_STATUS_SUCCESS = 0,
701 RT_STATUS_FAILURE = 1,
702 RT_STATUS_PENDING = 2,
703 RT_STATUS_RESOURCE = 3
704 }RT_STATUS,*PRT_STATUS;
707 typedef enum _RTL8192SUSB_LOOPBACK{
708 RTL8192SU_NO_LOOPBACK = 0,
709 RTL8192SU_MAC_LOOPBACK = 1,
710 RTL8192SU_DMA_LOOPBACK = 2,
711 RTL8192SU_CCK_LOOPBACK = 3,
712 }RTL8192SUSB_LOOPBACK_E;
716 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
719 /* Firmware Queue Layout */
720 #define NUM_OF_FIRMWARE_QUEUE 10
721 #define NUM_OF_PAGES_IN_FW 0x100
724 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
725 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
726 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
727 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
728 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
729 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
730 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
731 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
732 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
733 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
736 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
737 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
738 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
739 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
740 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
741 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
742 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
743 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
744 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
746 #define DEFAULT_FRAG_THRESHOLD 2342U
747 #define MIN_FRAG_THRESHOLD 256U
748 #define DEFAULT_BEACONINTERVAL 0x64U
749 #define DEFAULT_BEACON_ESSID "Rtl819xU"
751 #define DEFAULT_SSID ""
752 #define DEFAULT_RETRY_RTS 7
753 #define DEFAULT_RETRY_DATA 7
754 #define PRISM_HDR_SIZE 64
756 #define PHY_RSSI_SLID_WIN_MAX 100
759 typedef enum _WIRELESS_MODE {
760 WIRELESS_MODE_UNKNOWN = 0x00,
761 WIRELESS_MODE_A = 0x01,
762 WIRELESS_MODE_B = 0x02,
763 WIRELESS_MODE_G = 0x04,
764 WIRELESS_MODE_AUTO = 0x08,
765 WIRELESS_MODE_N_24G = 0x10,
766 WIRELESS_MODE_N_5G = 0x20
770 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
772 typedef struct buffer
779 typedef struct rtl_reg_debug{
785 unsigned char length;
787 unsigned char buf[0xff];
790 typedef struct _rt_9x_tx_rate_history {
793 // HT_MCS[0][]: BW=0 SG=0
794 // HT_MCS[1][]: BW=1 SG=0
795 // HT_MCS[2][]: BW=0 SG=1
796 // HT_MCS[3][]: BW=1 SG=1
798 }rt_tx_rahis_t, *prt_tx_rahis_t;
799 typedef struct _RT_SMOOTH_DATA_4RF {
800 char elements[4][100];//array to store values
801 u32 index; //index to current array to store
802 u32 TotalNum; //num of valid elements
803 u32 TotalVal[4]; //sum of valid elements
804 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
806 #define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size
807 //stats seems messed up, clean it ASAP
811 // unsigned long rxrdu;
812 //unsigned long rxnolast;
813 //unsigned long rxnodata;
814 // unsigned long rxreset;
815 // unsigned long rxnopointer;
817 unsigned long rxframgment;
818 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
819 unsigned long rxurberr;
820 unsigned long rxstaterr;
821 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
822 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
823 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
824 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
825 unsigned long numpacket_matchbssid; // debug use only.
826 unsigned long numpacket_toself; // debug use only.
827 unsigned long num_process_phyinfo; // debug use only.
828 unsigned long numqry_phystatus;
829 unsigned long numqry_phystatusCCK;
830 unsigned long numqry_phystatusHT;
831 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
832 unsigned long txnperr;
833 unsigned long txnpdrop;
834 unsigned long txresumed;
835 // unsigned long rxerr;
836 // unsigned long rxoverflow;
837 // unsigned long rxint;
838 unsigned long txnpokint;
839 // unsigned long txhpokint;
840 // unsigned long txhperr;
841 // unsigned long ints;
842 // unsigned long shints;
843 unsigned long txoverflow;
844 // unsigned long rxdmafail;
845 // unsigned long txbeacon;
846 // unsigned long txbeaconerr;
847 unsigned long txlpokint;
848 unsigned long txlpdrop;
849 unsigned long txlperr;
850 unsigned long txbeokint;
851 unsigned long txbedrop;
852 unsigned long txbeerr;
853 unsigned long txbkokint;
854 unsigned long txbkdrop;
855 unsigned long txbkerr;
856 unsigned long txviokint;
857 unsigned long txvidrop;
858 unsigned long txvierr;
859 unsigned long txvookint;
860 unsigned long txvodrop;
861 unsigned long txvoerr;
862 unsigned long txbeaconokint;
863 unsigned long txbeacondrop;
864 unsigned long txbeaconerr;
865 unsigned long txmanageokint;
866 unsigned long txmanagedrop;
867 unsigned long txmanageerr;
868 unsigned long txdatapkt;
869 unsigned long txfeedback;
870 unsigned long txfeedbackok;
872 unsigned long txoktotal;
873 unsigned long txokbytestotal;
874 unsigned long txokinperiod;
875 unsigned long txmulticast;
876 unsigned long txbytesmulticast;
877 unsigned long txbroadcast;
878 unsigned long txbytesbroadcast;
879 unsigned long txunicast;
880 unsigned long txbytesunicast;
882 unsigned long rxoktotal;
883 unsigned long rxbytesunicast;
884 unsigned long txfeedbackfail;
885 unsigned long txerrtotal;
886 unsigned long txerrbytestotal;
887 unsigned long txerrmulticast;
888 unsigned long txerrbroadcast;
889 unsigned long txerrunicast;
890 unsigned long txretrycount;
891 unsigned long txfeedbackretry;
893 unsigned long slide_signal_strength[100];
894 unsigned long slide_evm[100];
895 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
896 unsigned long slide_evm_total; // For recording sliding window's EVM value
897 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
899 long last_signal_strength_inpercent;
900 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
901 u8 rx_rssi_percentage[4];
902 u8 rx_evm_percentage[2];
904 rt_tx_rahis_t txrate;
905 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
906 u32 Slide_Beacon_Total; //cosa add for beacon rssi
907 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
909 u32 CurrentShowTxate;
914 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
915 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
916 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
920 typedef struct ChnlAccessSetting {
927 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
929 typedef struct _BB_REGISTER_DEFINITION{
930 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
931 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
932 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
933 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
934 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
935 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
936 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
937 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
938 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
939 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
940 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
941 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
942 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
943 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
944 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
945 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
946 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
947 u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
948 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
950 typedef enum _RT_RF_TYPE_819xU{
955 RF_6052=4, // 4 11b/g/n RF
957 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
960 typedef enum _RF_POWER_STATE{
965 }RF_POWER_STATE, *PRF_POWER_STATE;
968 typedef struct _rate_adaptive
970 u8 rate_adaptive_disabled;
974 u32 high_rssi_thresh_for_ra;
975 u32 high2low_rssi_thresh_for_ra;
976 u8 low2high_rssi_thresh_for_ra40M;
977 u32 low_rssi_thresh_for_ra40M;
978 u8 low2high_rssi_thresh_for_ra20M;
979 u32 low_rssi_thresh_for_ra20M;
980 u32 upper_rssi_threshold_ratr;
981 u32 middle_rssi_threshold_ratr;
982 u32 low_rssi_threshold_ratr;
983 u32 low_rssi_threshold_ratr_40M;
984 u32 low_rssi_threshold_ratr_20M;
985 u8 ping_rssi_enable; //cosa add for test
986 u32 ping_rssi_ratr; //cosa add for test
987 u32 ping_rssi_thresh_for_ra;//cosa add for test
990 } rate_adaptive, *prate_adaptive;
992 #define TxBBGainTableLength 37
993 #define CCKTxBBGainTableLength 23
995 typedef struct _txbbgain_struct
997 long txbb_iq_amplifygain;
999 } txbbgain_struct, *ptxbbgain_struct;
1001 typedef struct _ccktxbbgain_struct
1003 //The Value is from a22 to a29 one Byte one time is much Safer
1004 u8 ccktxbb_valuearray[8];
1005 } ccktxbbgain_struct,*pccktxbbgain_struct;
1008 typedef struct _init_gain
1016 } init_gain, *pinit_gain;
1019 typedef struct _phy_ofdm_rx_status_report_819xusb
1028 u8 csi_current_X[2];
1033 u8 rxsc_sgien_exflg;
1034 }phy_sts_ofdm_819xusb_t;
1036 typedef struct _phy_cck_rx_status_report_819xusb
1038 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
1039 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
1043 }phy_sts_cck_819xusb_t;
1046 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
1051 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
1053 typedef enum _RT_CUSTOMER_ID
1056 RT_CID_8187_ALPHA0 = 1,
1057 RT_CID_8187_SERCOMM_PS = 2,
1058 RT_CID_8187_HW_LED = 3,
1059 RT_CID_8187_NETGEAR = 4,
1061 RT_CID_819x_CAMEO = 6,
1062 RT_CID_819x_RUNTOP = 7,
1063 RT_CID_819x_Senao = 8,
1064 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
1065 RT_CID_819x_Netcore = 10,
1066 RT_CID_Nettronix = 11,
1069 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
1071 typedef enum _RESET_TYPE {
1072 RESET_TYPE_NORESET = 0x00,
1073 RESET_TYPE_NORMAL = 0x01,
1074 RESET_TYPE_SILENT = 0x02
1077 /* The simple tx command OP code. */
1078 typedef enum _tag_TxCmd_Config_Index{
1079 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
1080 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
1081 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
1082 TXCMD_SET_TX_DURATION = 0xFF900003,
1083 TXCMD_SET_RX_RSSI = 0xFF900004,
1084 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
1096 //definded by WB. Ready to fill handlers for different NIC types.
1097 //add handle here when necessary.
1100 void (* rtl819x_read_eeprom_info)(struct net_device *dev);
1101 short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb);
1102 short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb);
1103 void (* rtl819x_rx_nomal)(struct sk_buff* skb);
1104 void (* rtl819x_rx_cmd)(struct sk_buff *skb);
1105 bool (* rtl819x_adapter_start)(struct net_device *dev);
1106 void (* rtl819x_link_change)(struct net_device *dev);
1107 void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation);
1108 void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
1111 typedef struct r8192_priv
1113 struct rtl819x_ops* ops;
1114 struct usb_device *udev;
1115 /* added for maintain info from eeprom */
1118 u8 eeprom_CustomerID;
1119 u8 eeprom_SubCustomerID;
1120 u8 eeprom_ChannelPlan;
1121 RT_CUSTOMER_ID CustomerID;
1122 LED_STRATEGY_819xUsb LedStrategy;
1123 u8 txqueue_to_outpipemap[9];
1130 struct ieee80211_device *ieee80211;
1132 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1133 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
1134 // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
1136 enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
1138 short plcp_preamble_mode;
1140 spinlock_t irq_lock;
1141 // spinlock_t irq_th_lock;
1145 spinlock_t rf_lock; //used to lock rf write operation added by wb
1148 // short irq_enabled;
1149 // struct net_device *dev; //comment this out.
1155 // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1156 // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1157 // u8 cck_txpwr_base;
1158 // u8 ofdm_txpwr_base;
1159 // u8 challow[15]; //channels from 1 to 14, 0 not used
1161 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1164 // struct timer_list scan_timer;
1165 /*short scanpending;
1167 // spinlock_t scan_lock;
1169 //u8 active_scan_num;
1170 struct semaphore wx_sem;
1171 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1178 // short rcr_csense;
1179 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1180 RT_RF_TYPE_819xU rf_chip;
1183 short (*rf_set_sens)(struct net_device *dev,short sens);
1184 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1185 void (*rf_close)(struct net_device *dev);
1186 void (*rf_init)(struct net_device *dev);
1191 struct iw_statistics wstats;
1192 struct proc_dir_entry *dir_dev;
1197 // dma_addr_t rxringdma;
1198 struct urb **rx_urb;
1199 struct urb **rx_cmd_urb;
1201 /* modified by davad for Rx process */
1202 struct sk_buff_head rx_queue;
1203 struct sk_buff_head skb_queue;
1205 struct work_struct qos_activate;
1208 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1211 struct tasklet_struct irq_rx_tasklet;
1212 struct urb *rxurb_task;
1214 //2 Tx Related variables
1215 u16 ShortRetryLimit;
1218 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1220 u32 LastRxDescTSFHigh;
1221 u32 LastRxDescTSFLow;
1224 //2 Rx Related variables
1225 u16 EarlyRxThreshold;
1235 struct ChnlAccessSetting ChannelAccessSetting;
1237 struct work_struct reset_wq;
1239 /**********************************************************/
1245 bool bCurrentRxAggrEnable;
1246 u8 Rf_Mode; //add for Firmware RF -R/W switch
1247 prt_firmware pFirmware;
1248 rtl819xUsb_loopback_e LoopbackMode;
1251 u16 EEPROMTxPowerDiff;
1252 u8 EEPROMThermalMeter;
1254 u8 EEPROMCrystalCap;
1256 u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1257 u8 EEPROMTxPowerLevelCCK_V1[3];
1258 u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1259 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1262 bool bDmDisableProtect;
1263 bool bIgnoreDiffRateTxPowerOffset;
1265 // For EEPROM TX Power Index like 8190 series
1266 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1267 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1268 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1269 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1271 // F92S new definition
1272 //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14]
1273 u8 RfCckChnlAreaTxPwr[2][3];
1274 u8 RfOfdmChnlAreaTxPwr1T[2][3];
1275 u8 RfOfdmChnlAreaTxPwr2T[2][3];
1277 // Add For EEPROM Efuse switch and Efuse Shadow map Setting
1279 bool bBootFromEfuse; // system boot form EFUSE
1280 u8 EfuseMap[2][HWSET_MAX_SIZE_92S];
1283 u8 EEPROMUsbPhyParam[5];
1286 bool bBootFromEEPROM; // system boot from EEPROM
1289 u8 EEPROMHT2T_TxPwr[6]; // For channel 1, 7 and 13 on path A/B.
1290 u8 EEPROMTxPwrTkMode;
1292 u8 bTXPowerDataReadFromEEPORM;
1295 u8 EEPROMUsbEndPointNumber;
1297 bool AutoloadFailFlag;
1298 u8 RfTxPwrLevelCck[2][14];
1299 u8 RfTxPwrLevelOfdm1T[2][14];
1300 u8 RfTxPwrLevelOfdm2T[2][14];
1301 // 2009/01/20 MH Add for new EEPROM format.
1302 u8 TxPwrHt20Diff[2][14]; // HT 20<->40 Pwr diff
1303 u8 TxPwrLegacyHtDiff[2][14]; // For HT<->legacy pwr diff
1304 u8 TxPwrbandEdgeHt40[2][2]; // Band edge for HY 40MHZlow/up channel
1305 u8 TxPwrbandEdgeHt20[2][2]; // Band edge for HY 40MHZ low/up channel
1306 u8 TxPwrbandEdgeLegacyOfdm[2][2]; // Band edge for legacy ofdm low/up channel
1307 u8 TxPwrbandEdgeFlag; // Band edge enable flag
1309 // L1 and L2 high power threshold.
1310 u8 MidHighPwrTHR_L1;
1311 u8 MidHighPwrTHR_L2;
1312 u8 TxPwrSafetyFlag; // for Tx power safety spec
1316 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1317 // Read/write are allow for following hardware information variables
1318 u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM
1319 u32 CCKTxPowerLevelOriginalOffset;
1320 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1321 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1322 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1325 u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1326 u8 CrystalCap; // CrystalCap.
1327 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1330 // Use to calculate PWBD.
1332 long undecorated_smoothed_pwdb;
1335 u8 SwChnlInProgress;
1338 u8 SetBWModeInProgress;
1339 HT_CHANNEL_WIDTH CurrentChannelBW;
1344 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1345 // Joseph test for shorten RF configuration time.
1346 // We save RF reg0 in this variable to reduce RF reading.
1350 bool brfpath_rxenable[4];
1352 bool SetRFPowerStateInProgress;
1354 struct timer_list watch_dog_timer;
1356 //+by amy 080515 for dynamic mechenism
1357 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1358 bool bdynamic_txpower; //bDynamicTxPower
1359 bool bDynamicTxHighPower; // Tx high power state
1360 bool bDynamicTxLowPower; // Tx low power state
1361 bool bLastDTPFlag_High;
1362 bool bLastDTPFlag_Low;
1364 bool bstore_last_dtpflag;
1365 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1366 //Add by amy for Rate Adaptive
1367 rate_adaptive rate_adaptive;
1368 //Add by amy for TX power tracking
1369 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1370 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1371 u8 EEPROMTxPowerTrackEnable;
1372 u8 txpower_count;//For 6 sec do tracking again
1373 bool btxpower_trackingInit;
1376 //2007/09/10 Mars Add CCK TX Power Tracking
1377 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1378 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1379 u8 rfa_txpowertrackingindex;
1380 u8 rfa_txpowertrackingindex_real;
1381 u8 rfa_txpowertracking_default;
1382 u8 rfc_txpowertrackingindex;
1383 u8 rfc_txpowertrackingindex_real;
1385 s8 cck_present_attentuation;
1386 u8 cck_present_attentuation_20Mdefault;
1387 u8 cck_present_attentuation_40Mdefault;
1388 char cck_present_attentuation_difference;
1389 bool btxpower_tracking;
1391 bool btxpowerdata_readfromEEPORM;
1393 //For Backup Initial Gain
1394 init_gain initgain_backup;
1395 u8 DefaultInitialGain[4];
1396 // For EDCA Turbo mode, Added by amy 080515.
1397 bool bis_any_nonbepkts;
1398 bool bcurrent_turbo_EDCA;
1399 bool bis_cur_rdlstate;
1400 struct timer_list fsync_timer;
1401 bool bfsync_processing; // 500ms Fsync timer is active or not
1403 u32 rateCountDiffRecord;
1404 u32 ContiuneDiffCount;
1409 u8 framesyncMonitor;
1410 //Added by amy 080516 for RX related
1412 u8 nrxAMPDU_aggr_num;
1417 //by amy for reset_count
1421 u32 txpower_checkcnt;
1422 u32 txpower_tracking_callback_cnt;
1423 u8 thermal_read_val[40];
1424 u8 thermal_readback_index;
1425 u32 ccktxpower_adjustcnt_not_ch14;
1426 u32 ccktxpower_adjustcnt_ch14;
1427 u8 tx_fwinfo_force_subcarriermode;
1428 u8 tx_fwinfo_force_subcarrierval;
1429 //by amy for silent reset
1430 RESET_TYPE ResetProgress;
1431 bool bForcedSilentReset;
1432 bool bDisableNormalResetCheck;
1435 int IrpPendingCount;
1436 bool bResetInProgress;
1438 u8 InitialGainOperateType;
1442 //define work item by amy 080526
1443 struct delayed_work update_beacon_wq;
1444 struct delayed_work watch_dog_wq;
1445 struct delayed_work txpower_tracking_wq;
1446 struct delayed_work rfpath_check_wq;
1447 struct delayed_work gpio_change_rf_wq;
1448 struct delayed_work initialgain_operate_wq;
1450 struct workqueue_struct *priv_wq;
1454 // RF and BB access related synchronization flags.
1455 bool bChangeBBInProgress; // BaseBand RW is still in progress.
1456 bool bChangeRFInProgress; // RF RW is still in progress.
1458 u32 CCKTxPowerAdjustCntCh14; //debug only
1459 u32 CCKTxPowerAdjustCntNotCh14; //debug only
1460 u32 TXPowerTrackingCallbackCnt; //debug only
1461 u32 TxPowerCheckCnt; //debug only
1462 u32 RFWritePageCnt[3]; //debug only
1463 u32 RFReadPageCnt[3]; //debug only
1464 u8 ThermalReadBackIndex; //debug only
1465 u8 ThermalReadVal[40]; //debug only
1467 // For HCT test, 2005.07.15, by rcnjko.
1468 // not realize true, just define it, set it 0 default, because some func use it
1471 // The current Tx Power Level
1472 u8 CurrentCckTxPwrIdx;
1473 u8 CurrentOfdm24GTxPwrIdx;
1475 // For pass 92S common phycfg.c compiler
1476 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1477 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1478 u8 TxPowerLevelCCK_C[14]; // RF-C, CCK channel 1~14
1479 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1480 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1481 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1483 bool bRFSiOrPi;//0=si, 1=pi.
1486 bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only
1493 /* added for led control */
1498 struct work_struct BlinkWorkItem;
1499 /* added for led control */
1510 // now mirging to rtl8187B
1513 LOW_PRIORITY = 0x02,
1519 BULK_PRIORITY = 0x01,
1530 BEACON_PRIORITY, //0x0A
1535 UART_PRIORITY //0x0F
1539 struct ssid_thread {
1540 struct net_device *dev;
1541 u8 name[IW_ESSID_MAX_SIZE + 1];
1545 short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1546 short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
1547 bool FirmwareDownload92S(struct net_device *dev);
1549 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1550 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1552 u32 read_cam(struct net_device *dev, u8 addr);
1553 void write_cam(struct net_device *dev, u8 addr, u32 data);
1555 u8 read_nic_byte(struct net_device *dev, int x);
1556 u8 read_nic_byte_E(struct net_device *dev, int x);
1557 u32 read_nic_dword(struct net_device *dev, int x);
1558 u16 read_nic_word(struct net_device *dev, int x) ;
1559 void write_nic_byte(struct net_device *dev, int x,u8 y);
1560 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1561 void write_nic_word(struct net_device *dev, int x,u16 y);
1562 void write_nic_dword(struct net_device *dev, int x,u32 y);
1563 void force_pci_posting(struct net_device *dev);
1565 void rtl8192_rtx_disable(struct net_device *);
1566 void rtl8192_rx_enable(struct net_device *);
1567 void rtl8192_tx_enable(struct net_device *);
1569 void rtl8192_disassociate(struct net_device *dev);
1570 //void fix_rx_fifo(struct net_device *dev);
1571 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1573 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1574 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1575 void rtl8192_update_msr(struct net_device *dev);
1576 int rtl8192_down(struct net_device *dev);
1577 int rtl8192_up(struct net_device *dev);
1578 void rtl8192_commit(struct net_device *dev);
1579 void rtl8192_set_chan(struct net_device *dev,short ch);
1580 void write_phy(struct net_device *dev, u8 adr, u8 data);
1581 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1582 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1583 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1584 void rtl8192_set_rxconf(struct net_device *dev);
1585 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1586 extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate);
1587 void CamResetAllEntry(struct net_device* dev);
1588 void EnableHWSecurityConfig8192(struct net_device *dev);
1589 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1590 short rtl8192_is_tx_queue_empty(struct net_device *dev);