drivers/staging/pata_rdc/pata_rdc.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <linux/module.h>
   4
   5 #include <linux/pci.h>
   6 #include <linux/device.h>
   7
   8 #include <scsi/scsi_host.h>
   9 #include <linux/libata.h>
  10
  11 #include "pata_rdc.h"
  12
  13 static const struct pci_device_id rdc_pata_id_table[] = {
  14         { PCI_DEVICE(0x17F3, 0x1011), RDC_17F31011},
  15         { PCI_DEVICE(0x17F3, 0x1012), RDC_17F31012},
  16         { }     /* terminate list */
  17 };
  18 MODULE_DEVICE_TABLE(pci, rdc_pata_id_table);
  19
  20 /* see ATA Host Adapters Standards. */
  21 static struct pci_bits ATA_Decode_Enable_Bits[] = {
  22         { 0x41U, 1U, 0x80UL, 0x80UL },  /* port (Channel) 0 */
  23         { 0x43U, 1U, 0x80UL, 0x80UL },  /* port (Channel) 1 */
  24 };
  25
  26 static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
  27 {
  28         uint funcresult;
  29         unchar *pchar;
  30         uint i;
  31
  32         funcresult = TRUE;
  33
  34         pchar = pBuffer;
  35
  36         for (i = 0; i < Length; i++) {
  37                 pci_read_config_byte(pdev, Offset, pchar);
  38                 Offset++;
  39                 pchar++;
  40         }
  41
  42         funcresult = TRUE;
  43
  44         goto funcexit;
  45 funcexit:
  46
  47         return funcresult;
  48 }
  49
  50 static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
  51 {
  52         uint funcresult;
  53         unchar *pchar;
  54         uint i;
  55
  56         funcresult = TRUE;
  57
  58         pchar = pBuffer;
  59
  60         for (i = 0; i < Length; i++) {
  61                 pci_write_config_byte(pdev, Offset, *pchar);
  62                 Offset++;
  63                 pchar++;
  64         }
  65
  66         funcresult = TRUE;
  67
  68         goto funcexit;
  69 funcexit:
  70
  71         return funcresult;
  72 }
  73
  74 static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID,
  75                                          uint PIOTimingMode, uint DMAEnable,
  76                                          uint PrefetchPostingEnable)
  77 {
  78         uint funcresult;
  79         uint result;
  80         uint ATATimingRegister;
  81         uint Device1TimingRegister;
  82
  83         funcresult = TRUE;
  84
  85         ATATimingRegister = 0;
  86         Device1TimingRegister = 0;
  87
  88         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
  89                                                  ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
  90                                                  ATAConfiguration_ID_PrimaryTiming_Size,
  91                                                  &ATATimingRegister);
  92         if (result == FALSE) {
  93                 funcresult = FALSE;
  94                 goto funcexit;
  95         }
  96
  97         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
  98                                                   ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
  99                                                   ATAConfiguration_ID_Device1Timing_Size,
 100                                                   &Device1TimingRegister);
 101         if (result == FALSE) {
 102                 funcresult = FALSE;
 103                 goto funcexit;
 104         }
 105
 106         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
 107
 108         switch (DeviceID) {
 109         case 0:
 110                 /* mask clear */
 111                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
 112                                       ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
 113                                       ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
 114                                       ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
 115                                       ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
 116                                       ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
 117
 118                 if (PIOTimingMode > PIO0)
 119                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
 120
 121                 if (PIOTimingMode >= PIO3)
 122                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
 123
 124                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 125                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
 126
 127                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 128                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
 129
 130                 if (PIOTimingMode <= PIO2)
 131                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
 132                 else if (PIOTimingMode == PIO3)
 133                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
 134                 else if (PIOTimingMode == PIO4)
 135                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
 136
 137                 if (PIOTimingMode <= PIO1)
 138                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
 139                 else if (PIOTimingMode == PIO2)
 140                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
 141                 else if (PIOTimingMode <= PIO4)
 142                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
 143                 break;
 144         case 1:
 145                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
 146                                        ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
 147                                        ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
 148                                        ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
 149
 150                 if (PIOTimingMode > PIO0)
 151                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
 152
 153                 if (PIOTimingMode >= PIO3)
 154                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
 155
 156                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 157                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
 158
 159                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 160                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
 161
 162                 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode |
 163                                            ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode);
 164
 165                 if (PIOTimingMode <= PIO2)
 166                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0;
 167                 else if (PIOTimingMode == PIO3)
 168                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1;
 169                 else if (PIOTimingMode == PIO4)
 170                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3;
 171
 172                 if (PIOTimingMode <= PIO1)
 173                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0;
 174                 else if (PIOTimingMode == PIO2)
 175                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1;
 176                 else if (PIOTimingMode <= PIO4)
 177                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2;
 178                 break;
 179         default:
 180                 funcresult = FALSE;
 181                 goto funcexit;
 182                 break;
 183         }
 184
 185         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 186                                                    ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
 187                                                    ATAConfiguration_ID_PrimaryTiming_Size,
 188                                                    &ATATimingRegister);
 189         if (result == FALSE) {
 190                 funcresult = FALSE;
 191                 goto funcexit;
 192         }
 193
 194         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 195                                                    ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 196                                                    ATAConfiguration_ID_Device1Timing_Size,
 197                                                    &Device1TimingRegister);
 198         if (result == FALSE) {
 199                 funcresult = FALSE;
 200                 goto funcexit;
 201         }
 202
 203         goto funcexit;
 204 funcexit:
 205
 206         return funcresult;
 207 }
 208
 209 static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID,
 210                                            uint PIOTimingMode, uint DMAEnable,
 211                                            uint PrefetchPostingEnable)
 212 {
 213         uint funcresult;
 214         uint result;
 215         uint ATATimingRegister;
 216         uint Device1TimingRegister;
 217
 218         funcresult = TRUE;
 219
 220         ATATimingRegister = 0;
 221         Device1TimingRegister = 0;
 222
 223         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 224                                                   ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
 225                                                   ATAConfiguration_ID_SecondaryTiming_Size,
 226                                                   &ATATimingRegister);
 227         if (result == FALSE) {
 228                 funcresult = FALSE;
 229                 goto funcexit;
 230         }
 231
 232         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 233                                                   ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 234                                                   ATAConfiguration_ID_Device1Timing_Size,
 235                                                   &Device1TimingRegister);
 236         if (result == FALSE) {
 237                 funcresult = FALSE;
 238                 goto funcexit;
 239         }
 240
 241         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
 242
 243         switch (DeviceID) {
 244         case 0:
 245                 /* mask clear */
 246                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
 247                                        ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
 248                                        ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
 249                                        ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
 250                                        ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
 251                                        ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
 252
 253                 if (PIOTimingMode > PIO0)
 254                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
 255
 256                 if (PIOTimingMode >= PIO3)
 257                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
 258
 259                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 260                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
 261
 262                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 263                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
 264
 265                 if (PIOTimingMode <= PIO2)
 266                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
 267                 else if (PIOTimingMode == PIO3)
 268                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
 269                 else if (PIOTimingMode == PIO4)
 270                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
 271
 272                 if (PIOTimingMode <= PIO1)
 273                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
 274                 else if (PIOTimingMode == PIO2)
 275                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
 276                 else if (PIOTimingMode <= PIO4)
 277                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
 278                 break;
 279         case 1:
 280                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
 281                                        ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
 282                                        ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
 283                                        ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
 284
 285                 if (PIOTimingMode > PIO0)
 286                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
 287
 288                 if (PIOTimingMode >= PIO3)
 289                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
 290
 291                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 292                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
 293
 294                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 295                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
 296
 297                 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode |
 298                                            ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode);
 299
 300                 if (PIOTimingMode <= PIO2)
 301                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0;
 302                 else if (PIOTimingMode == PIO3)
 303                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1;
 304                 else if (PIOTimingMode == PIO4)
 305                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3;
 306
 307                 if (PIOTimingMode <= PIO1)
 308                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0;
 309                 else if (PIOTimingMode == PIO2)
 310                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1;
 311                 else if (PIOTimingMode <= PIO4)
 312                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2;
 313                 break;
 314         default:
 315                 funcresult = FALSE;
 316                 goto funcexit;
 317                 break;
 318         }
 319
 320         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 321                                                    ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
 322                                                    ATAConfiguration_ID_SecondaryTiming_Size,
 323                                                    &ATATimingRegister);
 324         if (result == FALSE) {
 325                 funcresult = FALSE;
 326                 goto funcexit;
 327         }
 328
 329         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 330                                                    ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 331                                                    ATAConfiguration_ID_Device1Timing_Size,
 332                                                    &Device1TimingRegister);
 333         if (result == FALSE) {
 334                 funcresult = FALSE;
 335                 goto funcexit;
 336         }
 337
 338         goto funcexit;
 339 funcexit:
 340         return funcresult;
 341 }
 342
 343 static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID,
 344                                           uint UDMAEnable, uint UDMATimingMode)
 345 {
 346         uint funcresult;
 347         uint result;
 348         uint UDMAControlRegister;
 349         uint UDMATimingRegister;
 350         ulong IDEIOConfigurationRegister;
 351
 352         funcresult = TRUE;
 353         UDMAControlRegister = 0;
 354         UDMATimingRegister = 0;
 355         IDEIOConfigurationRegister = 0;
 356
 357         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 358                                                   ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 359                                                   ATAConfiguration_ID_UDMAControl_Size,
 360                                                   &UDMAControlRegister);
 361         if (result == FALSE) {
 362                 funcresult = FALSE;
 363                 goto funcexit;
 364         }
 365
 366         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 367                                                   ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 368                                                   ATAConfiguration_ID_UDMATiming_Size,
 369                                                   &UDMATimingRegister);
 370         if (result == FALSE) {
 371                 funcresult = FALSE;
 372                 goto funcexit;
 373         }
 374
 375         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 376                                                   ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 377                                                   ATAConfiguration_ID_IDEIOConfiguration_Size,
 378                                                   &IDEIOConfigurationRegister);
 379         if (result == FALSE) {
 380                 funcresult = FALSE;
 381                 goto funcexit;
 382         }
 383
 384         /*Rom Code will determine the device cable type and ATA 100.*/
 385         /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/
 386         /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/
 387
 388         switch (DeviceID) {
 389         case 0:
 390                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable);
 391                 if (UDMAEnable == TRUE)
 392                         UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable;
 393
 394                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable |
 395                                                 ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable);
 396
 397                 if (UDMATimingMode >= UDMA5)
 398                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable;
 399                 else if (UDMATimingMode >= UDMA3)
 400                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable;
 401
 402                 /* if 80 cable report */
 403                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime);
 404
 405                 if (UDMATimingMode == UDMA0) {
 406                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0;
 407                 } else if (UDMATimingMode == UDMA1 ||
 408                            UDMATimingMode == UDMA3 ||
 409                            UDMATimingMode == UDMA5) {
 410                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1;
 411                 } else if (UDMATimingMode == UDMA2 ||
 412                            UDMATimingMode == UDMA4) {
 413                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2;
 414                 }
 415                 break;
 416         case 1:
 417                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable);
 418                 if (UDMAEnable == TRUE)
 419                         UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable;
 420
 421                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable |
 422                                                 ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable);
 423
 424                 if (UDMATimingMode >= UDMA5)
 425                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable;
 426                 else if (UDMATimingMode >= UDMA3)
 427                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable;
 428
 429                 /* if 80 cable report */
 430                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime);
 431
 432                 if (UDMATimingMode == UDMA0) {
 433                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0;
 434                 } else if (UDMATimingMode == UDMA1 ||
 435                            UDMATimingMode == UDMA3 ||
 436                            UDMATimingMode == UDMA5) {
 437                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1;
 438                 } else if (UDMATimingMode == UDMA2 ||
 439                            UDMATimingMode == UDMA4) {
 440                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2;
 441                 }
 442                 break;
 443         default:
 444                 funcresult = FALSE;
 445                 goto funcexit;
 446                 break;
 447         }
 448
 449         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 450                                                    ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 451                                                    ATAConfiguration_ID_UDMAControl_Size,
 452                                                    &UDMAControlRegister);
 453         if (result == FALSE) {
 454                 funcresult = FALSE;
 455                 goto funcexit;
 456         }
 457
 458         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 459                                                    ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 460                                                    ATAConfiguration_ID_UDMATiming_Size,
 461                                                    &UDMATimingRegister);
 462         if (result == FALSE) {
 463                 funcresult = FALSE;
 464                 goto funcexit;
 465         }
 466
 467         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 468                                                    ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 469                                                    ATAConfiguration_ID_IDEIOConfiguration_Size,
 470                                                    &IDEIOConfigurationRegister);
 471         if (result == FALSE) {
 472                 funcresult = FALSE;
 473                 goto funcexit;
 474         }
 475
 476         goto funcexit;
 477 funcexit:
 478         return funcresult;
 479 }
 480
 481 static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID,
 482                                             uint UDMAEnable, uint UDMATimingMode)
 483 {
 484         uint funcresult;
 485         uint result;
 486         uint UDMAControlRegister;
 487         uint UDMATimingRegister;
 488         ulong IDEIOConfigurationRegister;
 489
 490         funcresult = TRUE;
 491
 492         UDMAControlRegister = 0;
 493         UDMATimingRegister = 0;
 494         IDEIOConfigurationRegister = 0;
 495
 496         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 497                                                   ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 498                                                   ATAConfiguration_ID_UDMAControl_Size,
 499                                                   &UDMAControlRegister);
 500         if (result == FALSE) {
 501                 funcresult = FALSE;
 502                 goto funcexit;
 503         }
 504
 505         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 506                                                   ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 507                                                   ATAConfiguration_ID_UDMATiming_Size,
 508                                                   &UDMATimingRegister);
 509         if (result == FALSE) {
 510                 funcresult = FALSE;
 511                 goto funcexit;
 512         }
 513
 514         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 515                                                   ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 516                                                   ATAConfiguration_ID_IDEIOConfiguration_Size,
 517                                                   &IDEIOConfigurationRegister);
 518         if (result == FALSE) {
 519                 funcresult = FALSE;
 520                 goto funcexit;
 521         }
 522
 523         /* Rom Code will determine the device cable type and ATA 100. */
 524         /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */
 525         /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */
 526
 527         switch (DeviceID) {
 528         case 0:
 529                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable);
 530                 if (UDMAEnable == TRUE)
 531                         UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable;
 532
 533                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable |
 534                                                 ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable);
 535
 536                 if (UDMATimingMode >= UDMA5)
 537                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable;
 538                 else if (UDMATimingMode >= UDMA3)
 539                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable;
 540
 541                 /* if 80 cable report */
 542                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime);
 543
 544                 if (UDMATimingMode == UDMA0) {
 545                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0;
 546                 } else if (UDMATimingMode == UDMA1 ||
 547                            UDMATimingMode == UDMA3 ||
 548                            UDMATimingMode == UDMA5) {
 549                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1;
 550                 } else if (UDMATimingMode == UDMA2 ||
 551                            UDMATimingMode == UDMA4) {
 552                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2;
 553                 }
 554                 break;
 555         case 1:
 556                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable);
 557                 if (UDMAEnable == TRUE)
 558                         UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable;
 559
 560                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable |
 561                                                 ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable);
 562
 563                 if (UDMATimingMode >= UDMA5)
 564                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable;
 565                 else if (UDMATimingMode >= UDMA3)
 566                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable;
 567
 568                 /* if 80 cable report */
 569                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime);
 570
 571                 if (UDMATimingMode == UDMA0) {
 572                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0;
 573                 } else if (UDMATimingMode == UDMA1 ||
 574                            UDMATimingMode == UDMA3 ||
 575                            UDMATimingMode == UDMA5) {
 576                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1;
 577                 } else if (UDMATimingMode == UDMA2 ||
 578                            UDMATimingMode == UDMA4) {
 579                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2;
 580                 }
 581                 break;
 582         default:
 583                 funcresult = FALSE;
 584                 goto funcexit;
 585                 break;
 586         }
 587
 588         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 589                                                    ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 590                                                    ATAConfiguration_ID_UDMAControl_Size,
 591                                                    &UDMAControlRegister);
 592         if (result == FALSE) {
 593                 funcresult = FALSE;
 594                 goto funcexit;
 595         }
 596
 597         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 598                                                    ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 599                                                    ATAConfiguration_ID_UDMATiming_Size,
 600                                                    &UDMATimingRegister);
 601         if (result == FALSE) {
 602                 funcresult = FALSE;
 603                 goto funcexit;
 604         }
 605
 606         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 607                                                    ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 608                                                    ATAConfiguration_ID_IDEIOConfiguration_Size,
 609                                                    &IDEIOConfigurationRegister);
 610         if (result == FALSE) {
 611                 funcresult = FALSE;
 612                 goto funcexit;
 613         }
 614
 615         goto funcexit;
 616 funcexit:
 617         return funcresult;
 618 }
 619
 620 static int rdc_pata_port_start(struct ata_port *ap)
 621 {
 622         uint    Channel;
 623
 624         Channel = ap->port_no;
 625         dev_dbg(ap->dev, "%s: Channel: %u\n", __func__, Channel);
 626         if (ap->ioaddr.bmdma_addr) {
 627                 return ata_port_start(ap);
 628         } else {
 629                 dev_dbg(ap->dev, "%s: return 0!!!\n", __func__);
 630                 return 0;
 631         }
 632 }
 633
 634 static void rdc_pata_port_stop(struct ata_port *ap)
 635 {
 636         uint    Channel;
 637
 638         Channel = ap->port_no;
 639
 640         dev_dbg(ap->dev, "%s Channel: %u\n", __func__, Channel);
 641 }
 642
 643 static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
 644 {
 645         struct pci_dev *pdev;
 646         struct ata_port *ap;
 647         uint Channel;
 648
 649         dev_dbg(link->ap->dev, "%s\n", __func__);
 650
 651         ap = link->ap;
 652         pdev = to_pci_dev(ap->host->dev);
 653
 654         Channel = ap->port_no;
 655
 656         /* test ATA Decode Enable Bits, should be enable. */
 657         if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) {
 658                 dev_dbg(link->ap->dev, "%s: Channel: %u, Decode Disable\n",
 659                         __func__, Channel);
 660                 return -ENOENT;
 661         } else {
 662                 dev_dbg(link->ap->dev, "%s: Channel: %u, Decode Enable\n",
 663                         __func__, Channel);
 664                 return ata_std_prereset(link, deadline);
 665         }
 666 }
 667
 668 static int rdc_pata_cable_detect(struct ata_port *ap)
 669 {
 670         struct pci_dev *pdev;
 671         uint Channel;
 672         uint Mask;
 673         u32 u32Value;
 674
 675         dev_dbg(ap->dev, "%s\n", __func__);
 676
 677         pdev = to_pci_dev(ap->host->dev);
 678
 679         Channel = ap->port_no;
 680
 681         if (Channel == 0)
 682                 Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report;
 683         else
 684                 Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report;
 685
 686         /* check BIOS cable detect results */
 687         pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
 688
 689         if ((u32Value & Mask) == 0) {
 690                 dev_dbg(ap->dev, "%s: Channel: %u, PATA40 \n",
 691                         __func__, Channel);
 692                 return ATA_CBL_PATA40;
 693         } else {
 694                 dev_dbg(ap->dev, "%s: Channel: %u, PATA80 \n",
 695                         __func__, Channel);
 696                 return ATA_CBL_PATA80;
 697         }
 698 }
 699
 700 static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev)
 701 {
 702         struct pci_dev *pdev;
 703         uint    Channel;
 704         uint    DeviceID;
 705         uint    PIOTimingMode;
 706         uint    PrefetchPostingEnable;
 707
 708         dev_dbg(ap->dev, "%s\n", __func__);
 709
 710         pdev = to_pci_dev(ap->host->dev);
 711
 712         Channel = ap->port_no;
 713         DeviceID = adev->devno;
 714         /*
 715          * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
 716          * XFER_PIO_2, XFER_PIO_3...
 717          */
 718         PIOTimingMode = adev->pio_mode - XFER_PIO_0;
 719
 720         if (adev->class == ATA_DEV_ATA) {
 721                 PrefetchPostingEnable = TRUE;
 722         } else {
 723                 /* ATAPI, CD DVD Rom */
 724                 PrefetchPostingEnable = FALSE;
 725         }
 726
 727         /* PIO configuration clears DTE unconditionally.  It will be
 728          * programmed in set_dmamode which is guaranteed to be called
 729          * after set_piomode if any DMA mode is available.
 730          */
 731
 732         /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
 733          * selected */
 734
 735         if (Channel == 0) {
 736                 ATAHostAdapter_SetPrimaryPIO(
 737                     pdev,
 738                     DeviceID,
 739                     PIOTimingMode,
 740                     TRUE,
 741                     PrefetchPostingEnable
 742                     );
 743
 744                 ATAHostAdapter_SetPrimaryUDMA(
 745                     pdev,
 746                     DeviceID,
 747                     FALSE,
 748                     UDMA0
 749                     );
 750         } else {
 751                 ATAHostAdapter_SetSecondaryPIO(
 752                     pdev,
 753                     DeviceID,
 754                     PIOTimingMode,
 755                     TRUE,
 756                     PrefetchPostingEnable
 757                     );
 758
 759                 ATAHostAdapter_SetSecondaryUDMA(
 760                     pdev,
 761                     DeviceID,
 762                     FALSE,
 763                     UDMA0
 764                     );
 765         }
 766         dev_dbg(ap->dev, "%s: Channel: %u, DeviceID: %u, PIO: %d\n",
 767                 __func__, Channel, DeviceID, PIOTimingMode);
 768 }
 769
 770 static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 771 {
 772         struct pci_dev *pdev;
 773         uint    Channel;
 774         uint    DeviceID;
 775         uint    PIOTimingMode;
 776         uint    PrefetchPostingEnable;
 777         uint    DMATimingMode;
 778         uint    UDMAEnable;
 779
 780         dev_dbg(ap->dev, "%s\n", __func__);
 781
 782         pdev = to_pci_dev(ap->host->dev);
 783
 784         Channel = ap->port_no;
 785         DeviceID = adev->devno;
 786         PIOTimingMode = adev->pio_mode - XFER_PIO_0;  /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
 787         DMATimingMode = adev->dma_mode; /* UDMA or MDMA */
 788
 789         if (adev->class == ATA_DEV_ATA) {
 790                 PrefetchPostingEnable = TRUE;
 791         } else {
 792                 /* ATAPI, CD DVD Rom */
 793                 PrefetchPostingEnable = FALSE;
 794         }
 795
 796         if (ap->udma_mask == 0) {
 797                 /* ata_port dont support udma. depend on hardware spec. */
 798                 UDMAEnable = FALSE;
 799         } else {
 800                 UDMAEnable = TRUE;
 801         }
 802
 803         if (Channel == 0) {
 804                 if (DMATimingMode >= XFER_UDMA_0) {
 805                         /* UDMA */
 806                         ATAHostAdapter_SetPrimaryPIO(pdev,
 807                                 DeviceID,
 808                                 PIOTimingMode,
 809                                 TRUE,
 810                                 PrefetchPostingEnable);
 811
 812                         ATAHostAdapter_SetPrimaryUDMA(pdev,
 813                                 DeviceID,
 814                                 UDMAEnable,
 815                                 DMATimingMode - XFER_UDMA_0);
 816                         dev_dbg(ap->dev,
 817                                 "%s: Channel: %u, DeviceID: %u, UDMA: %u\n",
 818                                 __func__, Channel, DeviceID,
 819                                 (uint)(DMATimingMode - XFER_UDMA_0));
 820                 } else {
 821                         /* MDMA */
 822                         ATAHostAdapter_SetPrimaryPIO(pdev,
 823                                 DeviceID,
 824                                 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
 825                                 TRUE,
 826                                 PrefetchPostingEnable);
 827
 828                         ATAHostAdapter_SetPrimaryUDMA(pdev,
 829                                 DeviceID,
 830                                 FALSE,
 831                                 UDMA0);
 832                         dev_dbg(ap->dev,
 833                                 "%s: Channel: %u, DeviceID: %u, MDMA: %u\n",
 834                                 __func__, Channel, DeviceID,
 835                                 (uint)(DMATimingMode - XFER_MW_DMA_0));
 836                 }
 837         } else {
 838                 if (DMATimingMode >= XFER_UDMA_0) {
 839                         /* UDMA */
 840                         ATAHostAdapter_SetSecondaryPIO(pdev,
 841                                 DeviceID,
 842                                 PIOTimingMode,
 843                                 TRUE,
 844                                 PrefetchPostingEnable);
 845
 846                         ATAHostAdapter_SetSecondaryUDMA(pdev,
 847                                 DeviceID,
 848                                 UDMAEnable,
 849                                 DMATimingMode - XFER_UDMA_0);
 850                         dev_dbg(ap->dev,
 851                                 "%s: Channel: %u, DeviceID: %u, UDMA: %u\n",
 852                                 __func__, Channel, DeviceID,
 853                                 (uint)(DMATimingMode - XFER_UDMA_0));
 854                 } else {
 855                         /* MDMA */
 856                         ATAHostAdapter_SetSecondaryPIO(pdev,
 857                                 DeviceID,
 858                                 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
 859                                 TRUE,
 860                                 PrefetchPostingEnable);
 861
 862                         ATAHostAdapter_SetSecondaryUDMA(pdev,
 863                                 DeviceID,
 864                                 FALSE,
 865                                 UDMA0);
 866                         dev_dbg(ap->dev,
 867                                 "%s: Channel: %u, DeviceID: %u, MDMA: %u \n",
 868                                 __func__, Channel, DeviceID,
 869                                 (uint)(DMATimingMode - XFER_MW_DMA_0));
 870                 }
 871         }
 872 }
 873
 874 static struct scsi_host_template rdc_pata_sht = {
 875         ATA_BMDMA_SHT(KBUILD_MODNAME),
 876 };
 877
 878 static struct ata_port_operations rdc_pata_ops = {
 879         .inherits       = &ata_bmdma_port_ops,
 880
 881         .port_start     = rdc_pata_port_start,
 882         .port_stop      = rdc_pata_port_stop,
 883         .prereset       = rdc_pata_prereset,
 884         .cable_detect   = rdc_pata_cable_detect,
 885         .set_piomode    = rdc_pata_set_piomode,
 886         .set_dmamode    = rdc_pata_set_dmamode,
 887 };
 888
 889 static struct ata_port_info rdc_pata_port_info[] = {
 890         [RDC_17F31011] = {
 891         .flags          = ATA_FLAG_SLAVE_POSS,
 892         .pio_mask       = 0x1f,         /* pio0-4 */
 893         .mwdma_mask     = 0x07,         /* mwdma0-2 */
 894         .udma_mask      = ATA_UDMA5,    /* udma0-5 */
 895         .port_ops       = &rdc_pata_ops,
 896         },
 897
 898         [RDC_17F31012] = {
 899         .flags          = ATA_FLAG_SLAVE_POSS,
 900         .pio_mask       = 0x1f,         /* pio0-4 */
 901         .mwdma_mask     = 0x07,         /* mwdma0-2 */
 902         .udma_mask      = ATA_UDMA5,    /* udma0-5 */
 903         .port_ops       = &rdc_pata_ops,
 904         },
 905 };
 906
 907 static int __devinit rdc_init_one(struct pci_dev *pdev,
 908                                   const struct pci_device_id *ent)
 909 {
 910         struct ata_port_info port_info[2];
 911         const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] };
 912
 913         int rc;
 914
 915         dev_dbg(&pdev->dev, "%s\n", __func__);
 916
 917         port_info[0] = rdc_pata_port_info[ent->driver_data];
 918         port_info[1] = rdc_pata_port_info[ent->driver_data];
 919
 920         rc = pci_enable_device(pdev);
 921         if (rc) {
 922                 dev_dbg(&pdev->dev, "%s pci_enable_device failed\n", __func__);
 923                 return rc;
 924         }
 925         pci_intx(pdev, 1);
 926
 927         return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
 928 }
 929
 930 static struct pci_driver rdc_pata_driver = {
 931         .name           = KBUILD_MODNAME,
 932         .id_table       = rdc_pata_id_table,
 933         .probe          = rdc_init_one,
 934         .remove         = ata_pci_remove_one,
 935 #ifdef CONFIG_PM
 936         .suspend        = ata_pci_device_suspend,
 937         .resume         = ata_pci_device_resume,
 938 #endif
 939 };
 940
 941 static int __init pata_rdc_init(void)
 942 {
 943         return pci_register_driver(&rdc_pata_driver);
 944 }
 945
 946 static void __exit pata_rdc_exit(void)
 947 {
 948         pci_unregister_driver(&rdc_pata_driver);
 949 }
 950
 951 module_init(pata_rdc_init);
 952 module_exit(pata_rdc_exit);
 953
 954 MODULE_LICENSE("GPL");
 955 MODULE_DESCRIPTION("RDC PCI IDE Driver");