Merge branch 'x86-olpc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[pandora-kernel.git] / drivers / staging / gma500 / mrst_hdmi.c
1 /*
2  * Copyright © 2010 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Li Peng <peng.li@intel.com>
25  */
26
27 #include <drm/drmP.h>
28 #include <drm/drm.h>
29 #include "psb_intel_drv.h"
30 #include "psb_intel_reg.h"
31 #include "psb_drv.h"
32
33 #define HDMI_READ(reg)          readl(hdmi_dev->regs + (reg))
34 #define HDMI_WRITE(reg, val)    writel(val, hdmi_dev->regs + (reg))
35
36 #define HDMI_HCR        0x1000
37 #define HCR_ENABLE_HDCP         (1 << 5)
38 #define HCR_ENABLE_AUDIO        (1 << 2)
39 #define HCR_ENABLE_PIXEL        (1 << 1)
40 #define HCR_ENABLE_TMDS         (1 << 0)
41
42 #define HDMI_HICR       0x1004
43 #define HDMI_HSR        0x1008
44 #define HDMI_HISR       0x100C
45 #define HDMI_DETECT_HDP         (1 << 0)
46
47 #define HDMI_VIDEO_REG  0x3000
48 #define HDMI_UNIT_EN            (1 << 7)
49 #define HDMI_MODE_OUTPUT        (1 << 0)
50 #define HDMI_HBLANK_A   0x3100
51
52 #define HDMI_AUDIO_CTRL 0x4000
53 #define HDMI_ENABLE_AUDIO       (1 << 0)
54
55 #define PCH_HTOTAL_B    0x3100
56 #define PCH_HBLANK_B    0x3104
57 #define PCH_HSYNC_B     0x3108
58 #define PCH_VTOTAL_B    0x310C
59 #define PCH_VBLANK_B    0x3110
60 #define PCH_VSYNC_B     0x3114
61 #define PCH_PIPEBSRC    0x311C
62
63 #define PCH_PIPEB_DSL   0x3800
64 #define PCH_PIPEB_SLC   0x3804
65 #define PCH_PIPEBCONF   0x3808
66 #define PCH_PIPEBSTAT   0x3824
67
68 #define CDVO_DFT        0x5000
69 #define CDVO_SLEWRATE   0x5004
70 #define CDVO_STRENGTH   0x5008
71 #define CDVO_RCOMP      0x500C
72
73 #define DPLL_CTRL       0x6000
74 #define DPLL_PDIV_SHIFT         16
75 #define DPLL_PDIV_MASK          (0xf << 16)
76 #define DPLL_PWRDN              (1 << 4)
77 #define DPLL_RESET              (1 << 3)
78 #define DPLL_FASTEN             (1 << 2)
79 #define DPLL_ENSTAT             (1 << 1)
80 #define DPLL_DITHEN             (1 << 0)
81
82 #define DPLL_DIV_CTRL   0x6004
83 #define DPLL_CLKF_MASK          0xffffffc0
84 #define DPLL_CLKR_MASK          (0x3f)
85
86 #define DPLL_CLK_ENABLE 0x6008
87 #define DPLL_EN_DISP            (1 << 31)
88 #define DPLL_SEL_HDMI           (1 << 8)
89 #define DPLL_EN_HDMI            (1 << 1)
90 #define DPLL_EN_VGA             (1 << 0)
91
92 #define DPLL_ADJUST     0x600C
93 #define DPLL_STATUS     0x6010
94 #define DPLL_UPDATE     0x6014
95 #define DPLL_DFT        0x6020
96
97 struct intel_range {
98         int     min, max;
99 };
100
101 struct mrst_hdmi_limit {
102         struct intel_range vco, np, nr, nf;
103 };
104
105 struct mrst_hdmi_clock {
106         int np;
107         int nr;
108         int nf;
109         int dot;
110 };
111
112 #define VCO_MIN         320000
113 #define VCO_MAX         1650000
114 #define NP_MIN          1
115 #define NP_MAX          15
116 #define NR_MIN          1
117 #define NR_MAX          64
118 #define NF_MIN          2
119 #define NF_MAX          4095
120
121 static const struct mrst_hdmi_limit mrst_hdmi_limit = {
122         .vco = { .min = VCO_MIN,                .max = VCO_MAX },
123         .np  = { .min = NP_MIN,                 .max = NP_MAX  },
124         .nr  = { .min = NR_MIN,                 .max = NR_MAX  },
125         .nf  = { .min = NF_MIN,                 .max = NF_MAX  },
126 };
127
128 static void wait_for_vblank(struct drm_device *dev)
129 {
130         /* FIXME: Can we do this as a sleep ? */
131         /* Wait for 20ms, i.e. one cycle at 50hz. */
132         udelay(20000);
133 }
134
135 static void scu_busy_loop(void *scu_base)
136 {
137         u32 status = 0;
138         u32 loop_count = 0;
139
140         status = readl(scu_base + 0x04);
141         while (status & 1) {
142                 udelay(1); /* scu processing time is in few u secods */
143                 status = readl(scu_base + 0x04);
144                 loop_count++;
145                 /* break if scu doesn't reset busy bit after huge retry */
146                 if (loop_count > 1000) {
147                         DRM_DEBUG_KMS("SCU IPC timed out");
148                         return;
149                 }
150         }
151 }
152
153 static void mrst_hdmi_reset(struct drm_device *dev)
154 {
155         void *base;
156         /* FIXME: at least make these defines */
157         unsigned int scu_ipc_mmio = 0xff11c000;
158         int scu_len = 1024;
159
160         base = ioremap((resource_size_t)scu_ipc_mmio, scu_len);
161         if (base == NULL) {
162                 DRM_ERROR("failed to map SCU mmio\n");
163                 return;
164         }
165
166         /* scu ipc: assert hdmi controller reset */
167         writel(0xff11d118, base + 0x0c);
168         writel(0x7fffffdf, base + 0x80);
169         writel(0x42005, base + 0x0);
170         scu_busy_loop(base);
171
172         /* scu ipc: de-assert hdmi controller reset */
173         writel(0xff11d118, base + 0x0c);
174         writel(0x7fffffff, base + 0x80);
175         writel(0x42005, base + 0x0);
176         scu_busy_loop(base);
177
178         iounmap(base);
179 }
180
181 static void mrst_hdmi_audio_enable(struct drm_device *dev)
182 {
183         struct drm_psb_private *dev_priv = dev->dev_private;
184         struct mrst_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
185
186         HDMI_WRITE(HDMI_HCR, 0x67);
187         HDMI_READ(HDMI_HCR);
188
189         HDMI_WRITE(0x51a8, 0x10);
190         HDMI_READ(0x51a8);
191
192         HDMI_WRITE(HDMI_AUDIO_CTRL, 0x1);
193         HDMI_READ(HDMI_AUDIO_CTRL);
194 }
195
196 static void mrst_hdmi_audio_disable(struct drm_device *dev)
197 {
198         struct drm_psb_private *dev_priv = dev->dev_private;
199         struct mrst_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
200
201         HDMI_WRITE(0x51a8, 0x0);
202         HDMI_READ(0x51a8);
203
204         HDMI_WRITE(HDMI_AUDIO_CTRL, 0x0);
205         HDMI_READ(HDMI_AUDIO_CTRL);
206
207         HDMI_WRITE(HDMI_HCR, 0x47);
208         HDMI_READ(HDMI_HCR);
209 }
210
211 void mrst_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode)
212 {
213         struct drm_device *dev = crtc->dev;
214         u32 temp;
215
216         switch (mode) {
217         case DRM_MODE_DPMS_OFF:
218                 /* Disable VGACNTRL */
219                 REG_WRITE(VGACNTRL, 0x80000000);
220
221                 /* Disable plane */
222                 temp = REG_READ(DSPBCNTR);
223                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
224                         REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);
225                         REG_READ(DSPBCNTR);
226                         /* Flush the plane changes */
227                         REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
228                         REG_READ(DSPBSURF);
229                 }
230
231                 /* Disable pipe B */
232                 temp = REG_READ(PIPEBCONF);
233                 if ((temp & PIPEACONF_ENABLE) != 0) {
234                         REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);
235                         REG_READ(PIPEBCONF);
236                 }
237
238                 /* Disable LNW Pipes, etc */
239                 temp = REG_READ(PCH_PIPEBCONF);
240                 if ((temp & PIPEACONF_ENABLE) != 0) {
241                         REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);
242                         REG_READ(PCH_PIPEBCONF);
243                 }
244                 /* wait for pipe off */
245                 udelay(150);
246                 /* Disable dpll */
247                 temp = REG_READ(DPLL_CTRL);
248                 if ((temp & DPLL_PWRDN) == 0) {
249                         REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));
250                         REG_WRITE(DPLL_STATUS, 0x1);
251                 }
252                 /* wait for dpll off */
253                 udelay(150);
254                 break;
255         case DRM_MODE_DPMS_ON:
256         case DRM_MODE_DPMS_STANDBY:
257         case DRM_MODE_DPMS_SUSPEND:
258                 /* Enable dpll */
259                 temp = REG_READ(DPLL_CTRL);
260                 if ((temp & DPLL_PWRDN) != 0) {
261                         REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));
262                         temp = REG_READ(DPLL_CLK_ENABLE);
263                         REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);
264                         REG_READ(DPLL_CLK_ENABLE);
265                 }
266                 /* wait for dpll warm up */
267                 udelay(150);
268
269                 /* Enable pipe B */
270                 temp = REG_READ(PIPEBCONF);
271                 if ((temp & PIPEACONF_ENABLE) == 0) {
272                         REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);
273                         REG_READ(PIPEBCONF);
274                 }
275
276                 /* Enable LNW Pipe B */
277                 temp = REG_READ(PCH_PIPEBCONF);
278                 if ((temp & PIPEACONF_ENABLE) == 0) {
279                         REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);
280                         REG_READ(PCH_PIPEBCONF);
281                 }
282                 wait_for_vblank(dev);
283
284                 /* Enable plane */
285                 temp = REG_READ(DSPBCNTR);
286                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
287                         REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);
288                         /* Flush the plane changes */
289                         REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
290                         REG_READ(DSPBSURF);
291                 }
292                 psb_intel_crtc_load_lut(crtc);
293         }
294         /* DSPARB */
295         REG_WRITE(DSPARB, 0x00003fbf);
296         /* FW1 */
297         REG_WRITE(0x70034, 0x3f880a0a);
298         /* FW2 */
299         REG_WRITE(0x70038, 0x0b060808);
300         /* FW4 */
301         REG_WRITE(0x70050, 0x08030404);
302         /* FW5 */
303         REG_WRITE(0x70054, 0x04040404);
304         /* LNC Chicken Bits */
305         REG_WRITE(0x70400, 0x4000);
306 }
307
308
309 static void mrst_hdmi_dpms(struct drm_encoder *encoder, int mode)
310 {
311         static int dpms_mode = -1;
312
313         struct drm_device *dev = encoder->dev;
314         struct drm_psb_private *dev_priv = dev->dev_private;
315         struct mrst_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
316         u32 temp;
317
318         if (dpms_mode == mode)
319                 return;
320
321         if (mode != DRM_MODE_DPMS_ON)
322                 temp = 0x0;
323         else
324                 temp = 0x99;
325
326         dpms_mode = mode;
327         HDMI_WRITE(HDMI_VIDEO_REG, temp);
328 }
329
330 static unsigned int htotal_calculate(struct drm_display_mode *mode)
331 {
332         u32 htotal, new_crtc_htotal;
333
334         htotal = (mode->crtc_hdisplay - 1) | ((mode->crtc_htotal - 1) << 16);
335
336         /*
337          * 1024 x 768  new_crtc_htotal = 0x1024;
338          * 1280 x 1024 new_crtc_htotal = 0x0c34;
339          */
340         new_crtc_htotal = (mode->crtc_htotal - 1) * 200 * 1000 / mode->clock;
341
342         return (mode->crtc_hdisplay - 1) | (new_crtc_htotal << 16);
343 }
344
345 static void mrst_hdmi_find_dpll(struct drm_crtc *crtc, int target,
346                                 int refclk, struct mrst_hdmi_clock *best_clock)
347 {
348         int np_min, np_max, nr_min, nr_max;
349         int np, nr, nf;
350
351         np_min = DIV_ROUND_UP(mrst_hdmi_limit.vco.min, target * 10);
352         np_max = mrst_hdmi_limit.vco.max / (target * 10);
353         if (np_min < mrst_hdmi_limit.np.min)
354                 np_min = mrst_hdmi_limit.np.min;
355         if (np_max > mrst_hdmi_limit.np.max)
356                 np_max = mrst_hdmi_limit.np.max;
357
358         nr_min = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_max));
359         nr_max = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_min));
360         if (nr_min < mrst_hdmi_limit.nr.min)
361                 nr_min = mrst_hdmi_limit.nr.min;
362         if (nr_max > mrst_hdmi_limit.nr.max)
363                 nr_max = mrst_hdmi_limit.nr.max;
364
365         np = DIV_ROUND_UP((refclk * 1000), (target * 10 * nr_max));
366         nr = DIV_ROUND_UP((refclk * 1000), (target * 10 * np));
367         nf = DIV_ROUND_CLOSEST((target * 10 * np * nr), refclk);
368         DRM_DEBUG_KMS("np, nr, nf %d %d %d\n", np, nr, nf);
369
370         /*
371          * 1024 x 768  np = 1; nr = 0x26; nf = 0x0fd8000;
372          * 1280 x 1024 np = 1; nr = 0x17; nf = 0x1034000;
373          */
374         best_clock->np = np;
375         best_clock->nr = nr - 1;
376         best_clock->nf = (nf << 14);
377 }
378
379 int mrst_crtc_hdmi_mode_set(struct drm_crtc *crtc,
380                             struct drm_display_mode *mode,
381                             struct drm_display_mode *adjusted_mode,
382                             int x, int y,
383                             struct drm_framebuffer *old_fb)
384 {
385         struct drm_device *dev = crtc->dev;
386         struct drm_psb_private *dev_priv = dev->dev_private;
387         struct mrst_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
388         int pipe = 1;
389         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
390         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
391         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
392         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
393         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
394         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
395         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
396         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
397         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
398         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
399         int refclk;
400         struct mrst_hdmi_clock clock;
401         u32 dspcntr, pipeconf, dpll, temp;
402         int dspcntr_reg = DSPBCNTR;
403
404         /* Disable the VGA plane that we never use */
405         REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
406
407         /* XXX: Disable the panel fitter if it was on our pipe */
408
409         /* Disable dpll if necessary */
410         dpll = REG_READ(DPLL_CTRL);
411         if ((dpll & DPLL_PWRDN) == 0) {
412                 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));
413                 REG_WRITE(DPLL_DIV_CTRL, 0x00000000);
414                 REG_WRITE(DPLL_STATUS, 0x1);
415         }
416         udelay(150);
417
418         /* reset controller: FIXME - can we sort out the ioremap mess ? */
419         iounmap(hdmi_dev->regs);
420         mrst_hdmi_reset(dev);
421
422         /* program and enable dpll */
423         refclk = 25000;
424         mrst_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock);
425
426         /* Setting DPLL */
427         dpll = REG_READ(DPLL_CTRL);
428         dpll &= ~DPLL_PDIV_MASK;
429         dpll &= ~(DPLL_PWRDN | DPLL_RESET);
430         REG_WRITE(DPLL_CTRL, 0x00000008);
431         REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr));
432         REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1));
433         REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));
434         REG_WRITE(DPLL_UPDATE, 0x80000000);
435         REG_WRITE(DPLL_CLK_ENABLE, 0x80050102);
436         udelay(150);
437
438         hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len);
439         if (hdmi_dev->regs == NULL) {
440                 DRM_ERROR("failed to do hdmi mmio mapping\n");
441                 return -ENOMEM;
442         }
443
444         /* configure HDMI */
445         HDMI_WRITE(0x1004, 0x1fd);
446         HDMI_WRITE(0x2000, 0x1);
447         HDMI_WRITE(0x2008, 0x0);
448         HDMI_WRITE(0x3130, 0x8);
449         HDMI_WRITE(0x101c, 0x1800810);
450
451         temp = htotal_calculate(adjusted_mode);
452         REG_WRITE(htot_reg, temp);
453         REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
454         REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
455         REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
456         REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
457         REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
458         REG_WRITE(pipesrc_reg,
459                 ((mode->crtc_hdisplay - 1) << 16) |  (mode->crtc_vdisplay - 1));
460
461         REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
462         REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
463         REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
464         REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
465         REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
466         REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
467         REG_WRITE(PCH_PIPEBSRC,
468                 ((mode->crtc_hdisplay - 1) << 16) |  (mode->crtc_vdisplay - 1));
469
470         temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
471         HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) |  temp);
472
473         REG_WRITE(dspsize_reg,
474                         ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
475         REG_WRITE(dsppos_reg, 0);
476
477         /* Flush the plane changes */
478         {
479                 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
480                 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
481         }
482
483         /* Set up the display plane register */
484         dspcntr = REG_READ(dspcntr_reg);
485         dspcntr |= DISPPLANE_GAMMA_ENABLE;
486         dspcntr |= DISPPLANE_SEL_PIPE_B;
487         dspcntr |= DISPLAY_PLANE_ENABLE;
488
489         /* setup pipeconf */
490         pipeconf = REG_READ(pipeconf_reg);
491         pipeconf |= PIPEACONF_ENABLE;
492
493         REG_WRITE(pipeconf_reg, pipeconf);
494         REG_READ(pipeconf_reg);
495
496         REG_WRITE(PCH_PIPEBCONF, pipeconf);
497         REG_READ(PCH_PIPEBCONF);
498         wait_for_vblank(dev);
499
500         REG_WRITE(dspcntr_reg, dspcntr);
501         wait_for_vblank(dev);
502
503         return 0;
504 }
505
506 static int mrst_hdmi_mode_valid(struct drm_connector *connector,
507                                 struct drm_display_mode *mode)
508 {
509         if (mode->clock > 165000)
510                 return MODE_CLOCK_HIGH;
511         if (mode->clock < 20000)
512                 return MODE_CLOCK_LOW;
513
514         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
515                 return MODE_NO_DBLESCAN;
516
517         return MODE_OK;
518 }
519
520 static bool mrst_hdmi_mode_fixup(struct drm_encoder *encoder,
521                                  struct drm_display_mode *mode,
522                                  struct drm_display_mode *adjusted_mode)
523 {
524         return true;
525 }
526
527 static enum drm_connector_status
528 mrst_hdmi_detect(struct drm_connector *connector, bool force)
529 {
530         enum drm_connector_status status;
531         struct drm_device *dev = connector->dev;
532         struct drm_psb_private *dev_priv = dev->dev_private;
533         struct mrst_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
534         u32 temp;
535
536         temp = HDMI_READ(HDMI_HSR);
537         DRM_DEBUG_KMS("HDMI_HSR %x\n", temp);
538
539         if ((temp & HDMI_DETECT_HDP) != 0)
540                 status = connector_status_connected;
541         else
542                 status = connector_status_disconnected;
543
544         return status;
545 }
546
547 static const unsigned char raw_edid[] = {
548         0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xac, 0x2f, 0xa0,
549         0x53, 0x55, 0x33, 0x30, 0x16, 0x13, 0x01, 0x03, 0x0e, 0x3a, 0x24, 0x78,
550         0xea, 0xe9, 0xf5, 0xac, 0x51, 0x30, 0xb4, 0x25, 0x11, 0x50, 0x54, 0xa5,
551         0x4b, 0x00, 0x81, 0x80, 0xa9, 0x40, 0x71, 0x4f, 0xb3, 0x00, 0x01, 0x01,
552         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
553         0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x46, 0x6c, 0x21, 0x00, 0x00, 0x1a,
554         0x00, 0x00, 0x00, 0xff, 0x00, 0x47, 0x4e, 0x37, 0x32, 0x31, 0x39, 0x35,
555         0x52, 0x30, 0x33, 0x55, 0x53, 0x0a, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x44,
556         0x45, 0x4c, 0x4c, 0x20, 0x32, 0x37, 0x30, 0x39, 0x57, 0x0a, 0x20, 0x20,
557         0x00, 0x00, 0x00, 0xfd, 0x00, 0x38, 0x4c, 0x1e, 0x53, 0x11, 0x00, 0x0a,
558         0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x8d
559 };
560
561 static int mrst_hdmi_get_modes(struct drm_connector *connector)
562 {
563         struct drm_device *dev = connector->dev;
564         struct drm_psb_private *dev_priv = dev->dev_private;
565         struct i2c_adapter *i2c_adap;
566         struct edid *edid;
567         struct drm_display_mode *mode, *t;
568         int i = 0, ret = 0;
569
570         i2c_adap = i2c_get_adapter(3);
571         if (i2c_adap == NULL) {
572                 DRM_ERROR("No ddc adapter available!\n");
573                 edid = (struct edid *)raw_edid;
574         } else {
575                 edid = (struct edid *)raw_edid;
576                 /* FIXME ? edid = drm_get_edid(connector, i2c_adap); */
577         }
578
579         if (edid) {
580                 drm_mode_connector_update_edid_property(connector, edid);
581                 ret = drm_add_edid_modes(connector, edid);
582                 connector->display_info.raw_edid = NULL;
583         }
584
585         /*
586          * prune modes that require frame buffer bigger than stolen mem
587          */
588         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
589                 if ((mode->hdisplay * mode->vdisplay * 4) >= dev_priv->vram_stolen_size) {
590                         i++;
591                         drm_mode_remove(connector, mode);
592                 }
593         }
594         return ret - i;
595 }
596
597 static void mrst_hdmi_mode_set(struct drm_encoder *encoder,
598                                struct drm_display_mode *mode,
599                                struct drm_display_mode *adjusted_mode)
600 {
601         struct drm_device *dev = encoder->dev;
602
603         mrst_hdmi_audio_enable(dev);
604         return;
605 }
606
607 static void mrst_hdmi_destroy(struct drm_connector *connector)
608 {
609         return;
610 }
611
612 static const struct drm_encoder_helper_funcs mrst_hdmi_helper_funcs = {
613         .dpms = mrst_hdmi_dpms,
614         .mode_fixup = mrst_hdmi_mode_fixup,
615         .prepare = psb_intel_encoder_prepare,
616         .mode_set = mrst_hdmi_mode_set,
617         .commit = psb_intel_encoder_commit,
618 };
619
620 static const struct drm_connector_helper_funcs
621                                         mrst_hdmi_connector_helper_funcs = {
622         .get_modes = mrst_hdmi_get_modes,
623         .mode_valid = mrst_hdmi_mode_valid,
624         .best_encoder = psb_intel_best_encoder,
625 };
626
627 static const struct drm_connector_funcs mrst_hdmi_connector_funcs = {
628         .dpms = drm_helper_connector_dpms,
629         .detect = mrst_hdmi_detect,
630         .fill_modes = drm_helper_probe_single_connector_modes,
631         .destroy = mrst_hdmi_destroy,
632 };
633
634 static void mrst_hdmi_enc_destroy(struct drm_encoder *encoder)
635 {
636         drm_encoder_cleanup(encoder);
637 }
638
639 static const struct drm_encoder_funcs mrst_hdmi_enc_funcs = {
640         .destroy = mrst_hdmi_enc_destroy,
641 };
642
643 void mrst_hdmi_init(struct drm_device *dev,
644                                         struct psb_intel_mode_device *mode_dev)
645 {
646         struct psb_intel_output *psb_intel_output;
647         struct drm_connector *connector;
648         struct drm_encoder *encoder;
649
650         psb_intel_output = kzalloc(sizeof(struct psb_intel_output), GFP_KERNEL);
651         if (!psb_intel_output)
652                 return;
653
654         psb_intel_output->mode_dev = mode_dev;
655         connector = &psb_intel_output->base;
656         encoder = &psb_intel_output->enc;
657         drm_connector_init(dev, &psb_intel_output->base,
658                            &mrst_hdmi_connector_funcs,
659                            DRM_MODE_CONNECTOR_DVID);
660
661         drm_encoder_init(dev, &psb_intel_output->enc,
662                          &mrst_hdmi_enc_funcs,
663                          DRM_MODE_ENCODER_TMDS);
664
665         drm_mode_connector_attach_encoder(&psb_intel_output->base,
666                                           &psb_intel_output->enc);
667
668         psb_intel_output->type = INTEL_OUTPUT_HDMI;
669         drm_encoder_helper_add(encoder, &mrst_hdmi_helper_funcs);
670         drm_connector_helper_add(connector, &mrst_hdmi_connector_helper_funcs);
671
672         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
673         connector->interlace_allowed = false;
674         connector->doublescan_allowed = false;
675         drm_sysfs_connector_add(connector);
676
677         return;
678 }
679
680 static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = {
681         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080d) },
682         {}
683 };
684
685 void mrst_hdmi_setup(struct drm_device *dev)
686 {
687         struct drm_psb_private *dev_priv = dev->dev_private;
688         struct pci_dev *pdev;
689         struct mrst_hdmi_dev *hdmi_dev;
690         int ret;
691
692         pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x080d, NULL);
693         if (!pdev)
694                 return;
695
696         hdmi_dev = kzalloc(sizeof(struct mrst_hdmi_dev), GFP_KERNEL);
697         if (!hdmi_dev) {
698                 dev_err(dev->dev, "failed to allocate memory\n");
699                 goto out;
700         }
701
702
703         ret = pci_enable_device(pdev);
704         if (ret) {
705                 dev_err(dev->dev, "failed to enable hdmi controller\n");
706                 goto free;
707         }
708
709         hdmi_dev->mmio = pci_resource_start(pdev, 0);
710         hdmi_dev->mmio_len = pci_resource_len(pdev, 0);
711         hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len);
712         if (!hdmi_dev->regs) {
713                 dev_err(dev->dev, "failed to map hdmi mmio\n");
714                 goto free;
715         }
716
717         hdmi_dev->dev = pdev;
718         pci_set_drvdata(pdev, hdmi_dev);
719
720         /* Initialize i2c controller */
721         ret = mrst_hdmi_i2c_init(hdmi_dev->dev);
722         if (ret)
723                 dev_err(dev->dev, "HDMI I2C initialization failed\n");
724
725         dev_priv->hdmi_priv = hdmi_dev;
726         mrst_hdmi_audio_disable(dev);
727         return;
728
729 free:
730         kfree(hdmi_dev);
731 out:
732         return;
733 }
734
735 void mrst_hdmi_teardown(struct drm_device *dev)
736 {
737         struct drm_psb_private *dev_priv = dev->dev_private;
738         struct mrst_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
739         struct pci_dev *pdev;
740
741         if (hdmi_dev) {
742                 pdev = hdmi_dev->dev;
743                 pci_set_drvdata(pdev, NULL);
744                 mrst_hdmi_i2c_exit(pdev);
745                 iounmap(hdmi_dev->regs);
746                 kfree(hdmi_dev);
747                 pci_dev_put(pdev);
748         }
749 }
750
751 /* save HDMI register state */
752 void mrst_hdmi_save(struct drm_device *dev)
753 {
754         struct drm_psb_private *dev_priv = dev->dev_private;
755         struct mrst_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
756         int i;
757
758         /* dpll */
759         hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL);
760         hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL);
761         hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST);
762         hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE);
763         hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
764
765         /* pipe B */
766         dev_priv->savePIPEBCONF = PSB_RVDC32(PIPEBCONF);
767         dev_priv->savePIPEBSRC  = PSB_RVDC32(PIPEBSRC);
768         dev_priv->saveHTOTAL_B  = PSB_RVDC32(HTOTAL_B);
769         dev_priv->saveHBLANK_B  = PSB_RVDC32(HBLANK_B);
770         dev_priv->saveHSYNC_B   = PSB_RVDC32(HSYNC_B);
771         dev_priv->saveVTOTAL_B  = PSB_RVDC32(VTOTAL_B);
772         dev_priv->saveVBLANK_B  = PSB_RVDC32(VBLANK_B);
773         dev_priv->saveVSYNC_B   = PSB_RVDC32(VSYNC_B);
774
775         hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
776         hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
777         hdmi_dev->savePCH_HTOTAL_B = PSB_RVDC32(PCH_HTOTAL_B);
778         hdmi_dev->savePCH_HBLANK_B = PSB_RVDC32(PCH_HBLANK_B);
779         hdmi_dev->savePCH_HSYNC_B  = PSB_RVDC32(PCH_HSYNC_B);
780         hdmi_dev->savePCH_VTOTAL_B = PSB_RVDC32(PCH_VTOTAL_B);
781         hdmi_dev->savePCH_VBLANK_B = PSB_RVDC32(PCH_VBLANK_B);
782         hdmi_dev->savePCH_VSYNC_B  = PSB_RVDC32(PCH_VSYNC_B);
783
784         /* plane */
785         dev_priv->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR);
786         dev_priv->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE);
787         dev_priv->saveDSPBADDR = PSB_RVDC32(DSPBBASE);
788         dev_priv->saveDSPBSURF = PSB_RVDC32(DSPBSURF);
789         dev_priv->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF);
790         dev_priv->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF);
791
792         /* cursor B */
793         dev_priv->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
794         dev_priv->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
795         dev_priv->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
796
797         /* save palette */
798         for (i = 0; i < 256; i++)
799                 dev_priv->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2));
800 }
801
802 /* restore HDMI register state */
803 void mrst_hdmi_restore(struct drm_device *dev)
804 {
805         struct drm_psb_private *dev_priv = dev->dev_private;
806         struct mrst_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
807         int i;
808
809         /* dpll */
810         PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL);
811         PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL);
812         PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST);
813         PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE);
814         PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE);
815         DRM_UDELAY(150);
816
817         /* pipe */
818         PSB_WVDC32(dev_priv->savePIPEBSRC, PIPEBSRC);
819         PSB_WVDC32(dev_priv->saveHTOTAL_B, HTOTAL_B);
820         PSB_WVDC32(dev_priv->saveHBLANK_B, HBLANK_B);
821         PSB_WVDC32(dev_priv->saveHSYNC_B,  HSYNC_B);
822         PSB_WVDC32(dev_priv->saveVTOTAL_B, VTOTAL_B);
823         PSB_WVDC32(dev_priv->saveVBLANK_B, VBLANK_B);
824         PSB_WVDC32(dev_priv->saveVSYNC_B,  VSYNC_B);
825
826         PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
827         PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
828         PSB_WVDC32(hdmi_dev->savePCH_HBLANK_B, PCH_HBLANK_B);
829         PSB_WVDC32(hdmi_dev->savePCH_HSYNC_B,  PCH_HSYNC_B);
830         PSB_WVDC32(hdmi_dev->savePCH_VTOTAL_B, PCH_VTOTAL_B);
831         PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
832         PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B,  PCH_VSYNC_B);
833
834         PSB_WVDC32(dev_priv->savePIPEBCONF, PIPEBCONF);
835         PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
836
837         /* plane */
838         PSB_WVDC32(dev_priv->saveDSPBLINOFF, DSPBLINOFF);
839         PSB_WVDC32(dev_priv->saveDSPBSTRIDE, DSPBSTRIDE);
840         PSB_WVDC32(dev_priv->saveDSPBTILEOFF, DSPBTILEOFF);
841         PSB_WVDC32(dev_priv->saveDSPBCNTR, DSPBCNTR);
842         PSB_WVDC32(dev_priv->saveDSPBSURF, DSPBSURF);
843
844         /* cursor B */
845         PSB_WVDC32(dev_priv->saveDSPBCURSOR_CTRL, CURBCNTR);
846         PSB_WVDC32(dev_priv->saveDSPBCURSOR_POS, CURBPOS);
847         PSB_WVDC32(dev_priv->saveDSPBCURSOR_BASE, CURBBASE);
848
849         /* restore palette */
850         for (i = 0; i < 256; i++)
851                 PSB_WVDC32(dev_priv->save_palette_b[i], PALETTE_B + (i << 2));
852 }