2 * comedi/drivers/adv_pci_dio.c
4 * Author: Michal Dobes <dobes@tesnet.cz>
6 * Hardware driver for Advantech PCI DIO cards.
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1750, PCI-1751, PCI-1752, PCI-1753/E,
12 PCI-1754, PCI-1756, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
20 Updated: Tue, 04 May 2010 13:00:00 +0000
22 This driver supports now only insn interface for DI/DO/DIO.
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
32 #include "../comedidev.h"
34 #include <linux/delay.h>
36 #include "comedi_pci.h"
40 #undef PCI_DIO_EXTDEBUG /* if defined, enable extensive debug logging */
43 #ifdef PCI_DIO_EXTDEBUG
44 #define DPRINTK(fmt, args...) printk(fmt, ## args)
46 #define DPRINTK(fmt, args...)
49 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
51 /* hardware types of the cards */
53 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
57 TYPE_PCI1753, TYPE_PCI1753E,
58 TYPE_PCI1754, TYPE_PCI1756,
63 /* which I/O instructions to use */
68 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
69 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
70 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
72 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
74 /* (could be more than one 8254 per
77 #define SIZE_8254 4 /* 8254 IO space length */
78 #define SIZE_8255 4 /* 8255 IO space length */
80 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
82 /* Register offset definitions */
83 /* Advantech PCI-1730/3/4 */
84 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
85 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
86 #define PCI1730_DI 2 /* R: Digital input 0-15 */
87 #define PCI1730_DO 2 /* W: Digital output 0-15 */
88 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
89 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
90 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
92 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
93 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
94 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
96 /* Advantech PCI-1735U */
97 #define PCI1735_DI 0 /* R: Digital input 0-31 */
98 #define PCI1735_DO 0 /* W: Digital output 0-31 */
99 #define PCI1735_C8254 4 /* R/W: 8254 counter */
100 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
102 /* Advantech PCI-1736UP */
103 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
104 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
105 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
106 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
108 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
109 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
110 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
112 /* Advantech PCI-1750 */
113 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
114 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
115 #define PCI1750_ICR 32 /* W: Interrupt control register */
116 #define PCI1750_ISR 32 /* R: Interrupt status register */
118 /* Advantech PCI-1751/3/3E */
119 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
120 #define PCI1751_ICR 32 /* W: Interrupt control register */
121 #define PCI1751_ISR 32 /* R: Interrupt status register */
122 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
123 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
124 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
125 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
126 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
127 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
128 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
129 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
130 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
131 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
133 /* Advantech PCI-1752/4/6 */
134 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
135 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
136 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
137 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
138 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
139 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
140 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
141 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
142 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
143 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
144 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
145 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
147 /* Advantech PCI-1762 registers */
148 #define PCI1762_RO 0 /* R/W: Relays status/output */
149 #define PCI1762_IDI 2 /* R: Isolated input status */
150 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
151 #define PCI1762_ICR 6 /* W: Interrupt control register */
152 #define PCI1762_ISR 6 /* R: Interrupt status register */
154 /* Advantech PCI-1760 registers */
155 #define OMB0 0x0c /* W: Mailbox outgoing registers */
159 #define IMB0 0x1c /* R: Mailbox incoming registers */
163 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
168 /* PCI-1760 mailbox commands */
169 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
170 * DI status in IMB3 */
171 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
172 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
173 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
174 * register in OMB0, result in IMB0 */
175 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
177 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
179 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
181 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
183 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
185 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
187 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
188 * OMB0 to its reset values */
189 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
190 * interrupts based on bits in OMB0 */
191 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
192 * interrupts based on bits in OMB0 */
193 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
194 * - rising, =1 - falling) */
195 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
197 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
199 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
201 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
203 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
205 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
207 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
209 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
211 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
213 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
215 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
217 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
219 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
221 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
223 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
225 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
227 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
230 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
232 static int pci_dio_attach(struct comedi_device *dev,
233 struct comedi_devconfig *it);
234 static int pci_dio_detach(struct comedi_device *dev);
236 struct diosubd_data {
237 int chans; /* num of chans */
238 int addr; /* PCI address ofset */
239 int regs; /* number of registers to read or 8255
240 subdevices or 8254 chips */
241 unsigned int specflags; /* addon subdevice flags */
244 struct dio_boardtype {
245 const char *name; /* board name */
246 int vendor_id; /* vendor/device PCI ID */
248 int main_pci_region; /* main I/O PCI region */
249 enum hw_cards_id cardtype;
250 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
251 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
252 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
253 struct diosubd_data boardid; /* card supports board ID switch */
254 struct diosubd_data s8254[MAX_8254_SUBDEVS]; /* 8254 subdevices */
255 enum hw_io_access io_access;
258 static DEFINE_PCI_DEVICE_TABLE(pci_dio_pci_table) = {
259 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1730) },
260 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1733) },
261 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1734) },
262 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1735) },
263 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1736) },
264 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1750) },
265 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1751) },
266 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1752) },
267 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1753) },
268 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1754) },
269 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1756) },
270 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1760) },
271 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1762) },
275 MODULE_DEVICE_TABLE(pci, pci_dio_pci_table);
277 static const struct dio_boardtype boardtypes[] = {
278 {"pci1730", PCI_VENDOR_ID_ADVANTECH, 0x1730, PCIDIO_MAINREG,
280 { {16, PCI1730_DI, 2, 0}, {16, PCI1730_IDI, 2, 0} },
281 { {16, PCI1730_DO, 2, 0}, {16, PCI1730_IDO, 2, 0} },
282 { {0, 0, 0, 0}, {0, 0, 0, 0} },
283 {4, PCI173x_BOARDID, 1, SDF_INTERNAL},
286 {"pci1733", PCI_VENDOR_ID_ADVANTECH, 0x1733, PCIDIO_MAINREG,
288 { {0, 0, 0, 0}, {32, PCI1733_IDI, 4, 0} },
289 { {0, 0, 0, 0}, {0, 0, 0, 0} },
290 { {0, 0, 0, 0}, {0, 0, 0, 0} },
291 {4, PCI173x_BOARDID, 1, SDF_INTERNAL},
294 {"pci1734", PCI_VENDOR_ID_ADVANTECH, 0x1734, PCIDIO_MAINREG,
296 { {0, 0, 0, 0}, {0, 0, 0, 0} },
297 { {0, 0, 0, 0}, {32, PCI1734_IDO, 4, 0} },
298 { {0, 0, 0, 0}, {0, 0, 0, 0} },
299 {4, PCI173x_BOARDID, 1, SDF_INTERNAL},
302 {"pci1735", PCI_VENDOR_ID_ADVANTECH, 0x1735, PCIDIO_MAINREG,
304 { {32, PCI1735_DI, 4, 0}, {0, 0, 0, 0} },
305 { {32, PCI1735_DO, 4, 0}, {0, 0, 0, 0} },
306 { {0, 0, 0, 0}, {0, 0, 0, 0} },
307 { 4, PCI1735_BOARDID, 1, SDF_INTERNAL},
308 { {3, PCI1735_C8254, 1, 0} },
310 {"pci1736", PCI_VENDOR_ID_ADVANTECH, 0x1736, PCI1736_MAINREG,
312 { {0, 0, 0, 0}, {16, PCI1736_IDI, 2, 0} },
313 { {0, 0, 0, 0}, {16, PCI1736_IDO, 2, 0} },
314 { {0, 0, 0, 0}, {0, 0, 0, 0} },
315 {4, PCI1736_BOARDID, 1, SDF_INTERNAL},
318 {"pci1750", PCI_VENDOR_ID_ADVANTECH, 0x1750, PCIDIO_MAINREG,
320 { {0, 0, 0, 0}, {16, PCI1750_IDI, 2, 0} },
321 { {0, 0, 0, 0}, {16, PCI1750_IDO, 2, 0} },
322 { {0, 0, 0, 0}, {0, 0, 0, 0} },
326 {"pci1751", PCI_VENDOR_ID_ADVANTECH, 0x1751, PCIDIO_MAINREG,
328 { {0, 0, 0, 0}, {0, 0, 0, 0} },
329 { {0, 0, 0, 0}, {0, 0, 0, 0} },
330 { {48, PCI1751_DIO, 2, 0}, {0, 0, 0, 0} },
334 {"pci1752", PCI_VENDOR_ID_ADVANTECH, 0x1752, PCIDIO_MAINREG,
336 { {0, 0, 0, 0}, {0, 0, 0, 0} },
337 { {32, PCI1752_IDO, 2, 0}, {32, PCI1752_IDO2, 2, 0} },
338 { {0, 0, 0, 0}, {0, 0, 0, 0} },
339 {4, PCI175x_BOARDID, 1, SDF_INTERNAL},
342 {"pci1753", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG,
344 { {0, 0, 0, 0}, {0, 0, 0, 0} },
345 { {0, 0, 0, 0}, {0, 0, 0, 0} },
346 { {96, PCI1753_DIO, 4, 0}, {0, 0, 0, 0} },
350 {"pci1753e", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG,
352 { {0, 0, 0, 0}, {0, 0, 0, 0} },
353 { {0, 0, 0, 0}, {0, 0, 0, 0} },
354 { {96, PCI1753_DIO, 4, 0}, {96, PCI1753E_DIO, 4, 0} },
358 {"pci1754", PCI_VENDOR_ID_ADVANTECH, 0x1754, PCIDIO_MAINREG,
360 { {32, PCI1754_IDI, 2, 0}, {32, PCI1754_IDI2, 2, 0} },
361 { {0, 0, 0, 0}, {0, 0, 0, 0} },
362 { {0, 0, 0, 0}, {0, 0, 0, 0} },
363 {4, PCI175x_BOARDID, 1, SDF_INTERNAL},
366 {"pci1756", PCI_VENDOR_ID_ADVANTECH, 0x1756, PCIDIO_MAINREG,
368 { {0, 0, 0, 0}, {32, PCI1756_IDI, 2, 0} },
369 { {0, 0, 0, 0}, {32, PCI1756_IDO, 2, 0} },
370 { {0, 0, 0, 0}, {0, 0, 0, 0} },
371 {4, PCI175x_BOARDID, 1, SDF_INTERNAL},
374 {"pci1760", PCI_VENDOR_ID_ADVANTECH, 0x1760, 0,
376 { {0, 0, 0, 0}, {0, 0, 0, 0} }, /* This card have own setup work */
377 { {0, 0, 0, 0}, {0, 0, 0, 0} },
378 { {0, 0, 0, 0}, {0, 0, 0, 0} },
382 {"pci1762", PCI_VENDOR_ID_ADVANTECH, 0x1762, PCIDIO_MAINREG,
384 { {0, 0, 0, 0}, {16, PCI1762_IDI, 1, 0} },
385 { {0, 0, 0, 0}, {16, PCI1762_RO, 1, 0} },
386 { {0, 0, 0, 0}, {0, 0, 0, 0} },
387 {4, PCI1762_BOARDID, 1, SDF_INTERNAL},
392 #define n_boardtypes (sizeof(boardtypes)/sizeof(struct dio_boardtype))
394 static struct comedi_driver driver_pci_dio = {
395 .driver_name = "adv_pci_dio",
396 .module = THIS_MODULE,
397 .attach = pci_dio_attach,
398 .detach = pci_dio_detach
401 struct pci_dio_private {
402 struct pci_dio_private *prev; /* previous private struct */
403 struct pci_dio_private *next; /* next private struct */
404 struct pci_dev *pcidev; /* pointer to board's pci_dev */
405 char valid; /* card is usable */
406 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
407 /* PCI-1760 specific data */
408 unsigned char IDICntEnable; /* counter's counting enable status */
409 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
411 unsigned char IDICntMatchEnable; /* counter's match interrupts
413 unsigned char IDICntEdge; /* counter's count edge value
414 * (bit=0 - rising, =1 - falling) */
415 unsigned short CntResValue[8]; /* counters' reset value */
416 unsigned short CntMatchValue[8]; /* counters' match interrupt value */
417 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
418 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
419 unsigned char IDIPatMatchValue; /* IDI's pattern match value */
420 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
421 unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */
424 static struct pci_dio_private *pci_priv = NULL; /* list of allocated cards */
426 #define devpriv ((struct pci_dio_private *)dev->private)
427 #define this_board ((const struct dio_boardtype *)dev->board_ptr)
430 ==============================================================================
432 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
433 struct comedi_subdevice *s,
434 struct comedi_insn *insn, unsigned int *data)
436 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
440 for (i = 0; i < d->regs; i++)
441 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
448 ==============================================================================
450 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
451 struct comedi_subdevice *s,
452 struct comedi_insn *insn, unsigned int *data)
454 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
458 for (i = 0; i < d->regs; i++)
459 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
465 ==============================================================================
467 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
468 struct comedi_subdevice *s,
469 struct comedi_insn *insn, unsigned int *data)
471 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
475 s->state &= ~data[0];
476 s->state |= (data[0] & data[1]);
477 for (i = 0; i < d->regs; i++)
478 outb((s->state >> (8 * i)) & 0xff,
479 dev->iobase + d->addr + i);
487 ==============================================================================
489 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
490 struct comedi_subdevice *s,
491 struct comedi_insn *insn, unsigned int *data)
493 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
497 s->state &= ~data[0];
498 s->state |= (data[0] & data[1]);
499 for (i = 0; i < d->regs; i++)
500 outw((s->state >> (16 * i)) & 0xffff,
501 dev->iobase + d->addr + 2 * i);
509 ==============================================================================
511 static int pci_8254_insn_read(struct comedi_device *dev,
512 struct comedi_subdevice *s,
513 struct comedi_insn *insn, unsigned int *data)
515 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
516 unsigned int chan, chip, chipchan;
519 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
520 chip = chan / 3; /* chip on subdevice */
521 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
522 spin_lock_irqsave(&s->spin_lock, flags);
523 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip),
525 spin_unlock_irqrestore(&s->spin_lock, flags);
530 ==============================================================================
532 static int pci_8254_insn_write(struct comedi_device *dev,
533 struct comedi_subdevice *s,
534 struct comedi_insn *insn, unsigned int *data)
536 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
537 unsigned int chan, chip, chipchan;
540 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
541 chip = chan / 3; /* chip on subdevice */
542 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
543 spin_lock_irqsave(&s->spin_lock, flags);
544 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip),
545 0, chipchan, data[0]);
546 spin_unlock_irqrestore(&s->spin_lock, flags);
551 ==============================================================================
553 static int pci_8254_insn_config(struct comedi_device *dev,
554 struct comedi_subdevice *s,
555 struct comedi_insn *insn, unsigned int *data)
557 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
558 unsigned int chan, chip, chipchan;
559 unsigned long iobase;
563 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
564 chip = chan / 3; /* chip on subdevice */
565 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
566 iobase = dev->iobase + d->addr + (SIZE_8254 * chip);
567 spin_lock_irqsave(&s->spin_lock, flags);
569 case INSN_CONFIG_SET_COUNTER_MODE:
570 ret = i8254_set_mode(iobase, 0, chipchan, data[1]);
574 case INSN_CONFIG_8254_READ_STATUS:
575 data[1] = i8254_status(iobase, 0, chipchan);
581 spin_unlock_irqrestore(&s->spin_lock, flags);
582 return ret < 0 ? ret : insn->n;
586 ==============================================================================
588 static int pci1760_unchecked_mbxrequest(struct comedi_device *dev,
589 unsigned char *omb, unsigned char *imb,
592 int cnt, tout, ok = 0;
594 for (cnt = 0; cnt < repeats; cnt++) {
595 outb(omb[0], dev->iobase + OMB0);
596 outb(omb[1], dev->iobase + OMB1);
597 outb(omb[2], dev->iobase + OMB2);
598 outb(omb[3], dev->iobase + OMB3);
599 for (tout = 0; tout < 251; tout++) {
600 imb[2] = inb(dev->iobase + IMB2);
601 if (imb[2] == omb[2]) {
602 imb[0] = inb(dev->iobase + IMB0);
603 imb[1] = inb(dev->iobase + IMB1);
604 imb[3] = inb(dev->iobase + IMB3);
614 comedi_error(dev, "PCI-1760 mailbox request timeout!");
618 static int pci1760_clear_imb2(struct comedi_device *dev)
620 unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 };
621 unsigned char imb[4];
622 /* check if imb2 is already clear */
623 if (inb(dev->iobase + IMB2) == CMD_ClearIMB2)
625 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
628 static int pci1760_mbxrequest(struct comedi_device *dev,
629 unsigned char *omb, unsigned char *imb)
631 if (omb[2] == CMD_ClearIMB2) {
633 "bug! this function should not be used for CMD_ClearIMB2 command");
636 if (inb(dev->iobase + IMB2) == omb[2]) {
638 retval = pci1760_clear_imb2(dev);
642 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
646 ==============================================================================
648 static int pci1760_insn_bits_di(struct comedi_device *dev,
649 struct comedi_subdevice *s,
650 struct comedi_insn *insn, unsigned int *data)
652 data[1] = inb(dev->iobase + IMB3);
658 ==============================================================================
660 static int pci1760_insn_bits_do(struct comedi_device *dev,
661 struct comedi_subdevice *s,
662 struct comedi_insn *insn, unsigned int *data)
665 unsigned char omb[4] = {
671 unsigned char imb[4];
674 s->state &= ~data[0];
675 s->state |= (data[0] & data[1]);
677 ret = pci1760_mbxrequest(dev, omb, imb);
687 ==============================================================================
689 static int pci1760_insn_cnt_read(struct comedi_device *dev,
690 struct comedi_subdevice *s,
691 struct comedi_insn *insn, unsigned int *data)
694 unsigned char omb[4] = {
695 CR_CHAN(insn->chanspec) & 0x07,
697 CMD_GetIDICntCurValue,
700 unsigned char imb[4];
702 for (n = 0; n < insn->n; n++) {
703 ret = pci1760_mbxrequest(dev, omb, imb);
706 data[n] = (imb[1] << 8) + imb[0];
713 ==============================================================================
715 static int pci1760_insn_cnt_write(struct comedi_device *dev,
716 struct comedi_subdevice *s,
717 struct comedi_insn *insn, unsigned int *data)
720 unsigned char chan = CR_CHAN(insn->chanspec) & 0x07;
721 unsigned char bitmask = 1 << chan;
722 unsigned char omb[4] = {
724 (data[0] >> 8) & 0xff,
725 CMD_SetIDI0CntResetValue + chan,
728 unsigned char imb[4];
730 /* Set reset value if different */
731 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
732 ret = pci1760_mbxrequest(dev, omb, imb);
735 devpriv->CntResValue[chan] = data[0] & 0xffff;
738 omb[0] = bitmask; /* reset counter to it reset value */
739 omb[2] = CMD_ResetIDICounters;
740 ret = pci1760_mbxrequest(dev, omb, imb);
744 /* start counter if it don't run */
745 if (!(bitmask & devpriv->IDICntEnable)) {
747 omb[2] = CMD_EnableIDICounters;
748 ret = pci1760_mbxrequest(dev, omb, imb);
751 devpriv->IDICntEnable |= bitmask;
757 ==============================================================================
759 static int pci1760_reset(struct comedi_device *dev)
762 unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 };
763 unsigned char imb[4];
765 outb(0, dev->iobase + INTCSR0); /* disable IRQ */
766 outb(0, dev->iobase + INTCSR1);
767 outb(0, dev->iobase + INTCSR2);
768 outb(0, dev->iobase + INTCSR3);
769 devpriv->GlobalIrqEnabled = 0;
772 omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */
773 pci1760_mbxrequest(dev, omb, imb);
776 omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */
777 pci1760_mbxrequest(dev, omb, imb);
778 devpriv->IDICntEnable = 0;
781 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
783 pci1760_mbxrequest(dev, omb, imb);
784 devpriv->IDICntOverEnable = 0;
787 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
789 pci1760_mbxrequest(dev, omb, imb);
790 devpriv->IDICntMatchEnable = 0;
794 for (i = 0; i < 8; i++) { /* set IDI up counters match value */
795 omb[2] = CMD_SetIDI0CntMatchValue + i;
796 pci1760_mbxrequest(dev, omb, imb);
797 devpriv->CntMatchValue[i] = 0x8000;
802 for (i = 0; i < 8; i++) { /* set IDI up counters reset value */
803 omb[2] = CMD_SetIDI0CntResetValue + i;
804 pci1760_mbxrequest(dev, omb, imb);
805 devpriv->CntResValue[i] = 0x0000;
809 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
811 pci1760_mbxrequest(dev, omb, imb);
814 omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */
815 pci1760_mbxrequest(dev, omb, imb);
816 devpriv->IDICntEdge = 0x00;
819 omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */
820 pci1760_mbxrequest(dev, omb, imb);
821 devpriv->IDIFiltersEn = 0x00;
824 omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */
825 pci1760_mbxrequest(dev, omb, imb);
826 devpriv->IDIPatMatchEn = 0x00;
829 omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */
830 pci1760_mbxrequest(dev, omb, imb);
831 devpriv->IDIPatMatchValue = 0x00;
837 ==============================================================================
839 static int pci_dio_reset(struct comedi_device *dev)
841 DPRINTK("adv_pci_dio EDBG: BGN: pci171x_reset(...)\n");
843 switch (this_board->cardtype) {
845 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
846 outb(0, dev->iobase + PCI1730_DO + 1);
847 outb(0, dev->iobase + PCI1730_IDO);
848 outb(0, dev->iobase + PCI1730_IDO + 1);
849 /* NO break there! */
851 /* disable interrupts */
852 outb(0, dev->iobase + PCI1730_3_INT_EN);
853 /* clear interrupts */
854 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
855 /* set rising edge trigger */
856 outb(0, dev->iobase + PCI1730_3_INT_RF);
859 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
860 outb(0, dev->iobase + PCI1734_IDO + 1);
861 outb(0, dev->iobase + PCI1734_IDO + 2);
862 outb(0, dev->iobase + PCI1734_IDO + 3);
865 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
866 outb(0, dev->iobase + PCI1735_DO + 1);
867 outb(0, dev->iobase + PCI1735_DO + 2);
868 outb(0, dev->iobase + PCI1735_DO + 3);
869 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 0, I8254_MODE0);
870 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 1, I8254_MODE0);
871 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 2, I8254_MODE0);
875 outb(0, dev->iobase + PCI1736_IDO);
876 outb(0, dev->iobase + PCI1736_IDO + 1);
877 /* disable interrupts */
878 outb(0, dev->iobase + PCI1736_3_INT_EN);
879 /* clear interrupts */
880 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
881 /* set rising edge trigger */
882 outb(0, dev->iobase + PCI1736_3_INT_RF);
887 /* disable & clear interrupts */
888 outb(0x88, dev->iobase + PCI1750_ICR);
891 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
893 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
894 outw(0, dev->iobase + PCI1752_IDO + 2);
895 outw(0, dev->iobase + PCI1752_IDO2);
896 outw(0, dev->iobase + PCI1752_IDO2 + 2);
899 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
901 outb(0x80, dev->iobase + PCI1753E_ICR1);
902 outb(0x80, dev->iobase + PCI1753E_ICR2);
903 outb(0x80, dev->iobase + PCI1753E_ICR3);
904 /* NO break there! */
906 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
908 outb(0x80, dev->iobase + PCI1753_ICR1);
909 outb(0x80, dev->iobase + PCI1753_ICR2);
910 outb(0x80, dev->iobase + PCI1753_ICR3);
913 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
915 outw(0x08, dev->iobase + PCI1754_6_ICR1);
916 outw(0x08, dev->iobase + PCI1754_ICR2);
917 outw(0x08, dev->iobase + PCI1754_ICR3);
920 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
922 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
924 outw(0x08, dev->iobase + PCI1754_6_ICR1);
925 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
926 outw(0, dev->iobase + PCI1756_IDO + 2);
932 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
937 DPRINTK("adv_pci_dio EDBG: END: pci171x_reset(...)\n");
943 ==============================================================================
945 static int pci1760_attach(struct comedi_device *dev,
946 struct comedi_devconfig *it)
948 struct comedi_subdevice *s;
951 s = dev->subdevices + subdev;
952 s->type = COMEDI_SUBD_DI;
953 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
957 s->range_table = &range_digital;
958 s->insn_bits = pci1760_insn_bits_di;
961 s = dev->subdevices + subdev;
962 s->type = COMEDI_SUBD_DO;
963 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
967 s->range_table = &range_digital;
969 s->insn_bits = pci1760_insn_bits_do;
972 s = dev->subdevices + subdev;
973 s->type = COMEDI_SUBD_TIMER;
974 s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL;
976 s->maxdata = 0xffffffff;
978 /* s->insn_config=pci1760_insn_pwm_cfg; */
981 s = dev->subdevices + subdev;
982 s->type = COMEDI_SUBD_COUNTER;
983 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
987 s->insn_read = pci1760_insn_cnt_read;
988 s->insn_write = pci1760_insn_cnt_write;
989 /* s->insn_config=pci1760_insn_cnt_cfg; */
996 ==============================================================================
998 static int pci_dio_add_di(struct comedi_device *dev, struct comedi_subdevice *s,
999 const struct diosubd_data *d, int subdev)
1001 s->type = COMEDI_SUBD_DI;
1002 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | d->specflags;
1004 s->subdev_flags |= SDF_LSAMPL;
1005 s->n_chan = d->chans;
1007 s->len_chanlist = d->chans;
1008 s->range_table = &range_digital;
1009 switch (this_board->io_access) {
1011 s->insn_bits = pci_dio_insn_bits_di_b;
1014 s->insn_bits = pci_dio_insn_bits_di_w;
1017 s->private = (void *)d;
1023 ==============================================================================
1025 static int pci_dio_add_do(struct comedi_device *dev, struct comedi_subdevice *s,
1026 const struct diosubd_data *d, int subdev)
1028 s->type = COMEDI_SUBD_DO;
1029 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1031 s->subdev_flags |= SDF_LSAMPL;
1032 s->n_chan = d->chans;
1034 s->len_chanlist = d->chans;
1035 s->range_table = &range_digital;
1037 switch (this_board->io_access) {
1039 s->insn_bits = pci_dio_insn_bits_do_b;
1042 s->insn_bits = pci_dio_insn_bits_do_w;
1045 s->private = (void *)d;
1051 ==============================================================================
1053 static int pci_dio_add_8254(struct comedi_device *dev,
1054 struct comedi_subdevice *s,
1055 const struct diosubd_data *d, int subdev)
1057 s->type = COMEDI_SUBD_COUNTER;
1058 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1059 s->n_chan = d->chans;
1061 s->len_chanlist = d->chans;
1062 s->insn_read = pci_8254_insn_read;
1063 s->insn_write = pci_8254_insn_write;
1064 s->insn_config = pci_8254_insn_config;
1065 s->private = (void *)d;
1071 ==============================================================================
1073 static int CheckAndAllocCard(struct comedi_device *dev,
1074 struct comedi_devconfig *it,
1075 struct pci_dev *pcidev)
1077 struct pci_dio_private *pr, *prev;
1079 for (pr = pci_priv, prev = NULL; pr != NULL; prev = pr, pr = pr->next) {
1080 if (pr->pcidev == pcidev)
1081 return 0; /* this card is used, look for another */
1086 devpriv->prev = prev;
1087 prev->next = devpriv;
1092 devpriv->pcidev = pcidev;
1098 ==============================================================================
1100 static int pci_dio_attach(struct comedi_device *dev,
1101 struct comedi_devconfig *it)
1103 struct comedi_subdevice *s;
1104 int ret, subdev, n_subdevices, i, j;
1105 unsigned long iobase;
1106 struct pci_dev *pcidev = NULL;
1108 printk("comedi%d: adv_pci_dio: ", dev->minor);
1110 ret = alloc_private(dev, sizeof(struct pci_dio_private));
1112 printk(", Error: Cann't allocate private memory!\n");
1116 for_each_pci_dev(pcidev) {
1117 /* loop through cards supported by this driver */
1118 for (i = 0; i < n_boardtypes; ++i) {
1119 if (boardtypes[i].vendor_id != pcidev->vendor)
1121 if (boardtypes[i].device_id != pcidev->device)
1123 /* was a particular bus/slot requested? */
1124 if (it->options[0] || it->options[1]) {
1125 /* are we on the wrong bus/slot? */
1126 if (pcidev->bus->number != it->options[0] ||
1127 PCI_SLOT(pcidev->devfn) != it->options[1]) {
1131 ret = CheckAndAllocCard(dev, it, pcidev);
1134 dev->board_ptr = boardtypes + i;
1141 if (!dev->board_ptr) {
1142 printk(", Error: Requested type of the card was not found!\n");
1146 if (comedi_pci_enable(pcidev, driver_pci_dio.driver_name)) {
1148 (", Error: Can't enable PCI device and request regions!\n");
1151 iobase = pci_resource_start(pcidev, this_board->main_pci_region);
1152 printk(", b:s:f=%d:%d:%d, io=0x%4lx",
1153 pcidev->bus->number, PCI_SLOT(pcidev->devfn),
1154 PCI_FUNC(pcidev->devfn), iobase);
1156 dev->iobase = iobase;
1157 dev->board_name = this_board->name;
1159 if (this_board->cardtype == TYPE_PCI1760) {
1160 n_subdevices = 4; /* 8 IDI, 8 IDO, 2 PWM, 8 CNT */
1163 for (i = 0; i < MAX_DI_SUBDEVS; i++)
1164 if (this_board->sdi[i].chans)
1166 for (i = 0; i < MAX_DO_SUBDEVS; i++)
1167 if (this_board->sdo[i].chans)
1169 for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1170 n_subdevices += this_board->sdio[i].regs;
1171 if (this_board->boardid.chans)
1173 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1174 if (this_board->s8254[i].chans)
1178 ret = alloc_subdevices(dev, n_subdevices);
1180 printk(", Error: Cann't allocate subdevice memory!\n");
1188 for (i = 0; i < MAX_DI_SUBDEVS; i++)
1189 if (this_board->sdi[i].chans) {
1190 s = dev->subdevices + subdev;
1191 pci_dio_add_di(dev, s, &this_board->sdi[i], subdev);
1195 for (i = 0; i < MAX_DO_SUBDEVS; i++)
1196 if (this_board->sdo[i].chans) {
1197 s = dev->subdevices + subdev;
1198 pci_dio_add_do(dev, s, &this_board->sdo[i], subdev);
1202 for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1203 for (j = 0; j < this_board->sdio[i].regs; j++) {
1204 s = dev->subdevices + subdev;
1205 subdev_8255_init(dev, s, NULL,
1207 this_board->sdio[i].addr +
1212 if (this_board->boardid.chans) {
1213 s = dev->subdevices + subdev;
1214 s->type = COMEDI_SUBD_DI;
1215 pci_dio_add_di(dev, s, &this_board->boardid, subdev);
1219 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1220 if (this_board->s8254[i].chans) {
1221 s = dev->subdevices + subdev;
1222 pci_dio_add_8254(dev, s, &this_board->s8254[i], subdev);
1226 if (this_board->cardtype == TYPE_PCI1760)
1227 pci1760_attach(dev, it);
1237 ==============================================================================
1239 static int pci_dio_detach(struct comedi_device *dev)
1242 struct comedi_subdevice *s;
1250 /* This shows the silliness of using this kind of
1251 * scheme for numbering subdevices. Don't do it. --ds */
1253 for (i = 0; i < MAX_DI_SUBDEVS; i++) {
1254 if (this_board->sdi[i].chans)
1258 for (i = 0; i < MAX_DO_SUBDEVS; i++) {
1259 if (this_board->sdo[i].chans)
1263 for (i = 0; i < MAX_DIO_SUBDEVG; i++) {
1264 for (j = 0; j < this_board->sdio[i].regs; j++) {
1265 s = dev->subdevices + subdev;
1266 subdev_8255_cleanup(dev, s);
1271 if (this_board->boardid.chans)
1274 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1275 if (this_board->s8254[i].chans)
1278 for (i = 0; i < dev->n_subdevices; i++) {
1279 s = dev->subdevices + i;
1283 if (devpriv->pcidev) {
1285 comedi_pci_disable(devpriv->pcidev);
1287 pci_dev_put(devpriv->pcidev);
1291 devpriv->prev->next = devpriv->next;
1293 pci_priv = devpriv->next;
1296 devpriv->next->prev = devpriv->prev;
1304 ==============================================================================
1306 static int __devinit driver_pci_dio_pci_probe(struct pci_dev *dev,
1307 const struct pci_device_id *ent)
1309 return comedi_pci_auto_config(dev, driver_pci_dio.driver_name);
1312 static void __devexit driver_pci_dio_pci_remove(struct pci_dev *dev)
1314 comedi_pci_auto_unconfig(dev);
1317 static struct pci_driver driver_pci_dio_pci_driver = {
1318 .id_table = pci_dio_pci_table,
1319 .probe = &driver_pci_dio_pci_probe,
1320 .remove = __devexit_p(&driver_pci_dio_pci_remove)
1323 static int __init driver_pci_dio_init_module(void)
1327 retval = comedi_driver_register(&driver_pci_dio);
1331 driver_pci_dio_pci_driver.name = (char *)driver_pci_dio.driver_name;
1332 return pci_register_driver(&driver_pci_dio_pci_driver);
1335 static void __exit driver_pci_dio_cleanup_module(void)
1337 pci_unregister_driver(&driver_pci_dio_pci_driver);
1338 comedi_driver_unregister(&driver_pci_dio);
1341 module_init(driver_pci_dio_init_module);
1342 module_exit(driver_pci_dio_cleanup_module);
1344 ==============================================================================
1347 MODULE_AUTHOR("Comedi http://www.comedi.org");
1348 MODULE_DESCRIPTION("Comedi low-level driver");
1349 MODULE_LICENSE("GPL");