2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/kernel.h>
17 #include <linux/string.h>
27 #include "siutils_priv.h"
29 #define PMU_ERROR(args)
32 #define PMU_MSG(args) printf args
37 /* To check in verbose debugging messages not intended
38 * to be on except on private builds.
40 #define PMU_NONE(args)
42 /* PLL controls/clocks */
43 static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc,
45 static u32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
46 static u32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
49 static bool si_pmu_res_depfltr_bb(si_t *sih);
50 static bool si_pmu_res_depfltr_ncb(si_t *sih);
51 static bool si_pmu_res_depfltr_paldo(si_t *sih);
52 static bool si_pmu_res_depfltr_npaldo(si_t *sih);
53 static u32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc,
55 static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
57 static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax);
58 static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
59 osl_t *osh, u8 spuravoid);
61 static void si_pmu_set_4330_plldivs(si_t *sih);
64 #define FVCO_880 880000 /* 880MHz */
65 #define FVCO_1760 1760000 /* 1760MHz */
66 #define FVCO_1440 1440000 /* 1440MHz */
67 #define FVCO_960 960000 /* 960MHz */
69 /* Read/write a chipcontrol reg */
70 u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
72 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
74 return si_corereg(sih, SI_CC_IDX,
75 offsetof(chipcregs_t, chipcontrol_data), mask, val);
78 /* Read/write a regcontrol reg */
79 u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
81 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
83 return si_corereg(sih, SI_CC_IDX,
84 offsetof(chipcregs_t, regcontrol_data), mask, val);
87 /* Read/write a pllcontrol reg */
88 u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
90 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
92 return si_corereg(sih, SI_CC_IDX,
93 offsetof(chipcregs_t, pllcontrol_data), mask, val);
97 void si_pmu_pllupd(si_t *sih)
99 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
100 PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
103 /* Setup switcher voltage */
104 void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh, u8 bb_voltage,
110 ASSERT(sih->cccaps & CC_CAP_PMU);
112 /* Remember original core before switch to chipc */
113 origidx = si_coreidx(sih);
114 cc = si_setcoreidx(sih, SI_CC_IDX);
117 W_REG(osh, &cc->regcontrol_addr, 0x01);
118 W_REG(osh, &cc->regcontrol_data, (u32) (bb_voltage & 0x1f) << 22);
120 W_REG(osh, &cc->regcontrol_addr, 0x00);
121 W_REG(osh, &cc->regcontrol_data, (u32) (rf_voltage & 0x1f) << 14);
123 /* Return to original core */
124 si_setcoreidx(sih, origidx);
127 void si_pmu_set_ldo_voltage(si_t *sih, osl_t *osh, u8 ldo, u8 voltage)
129 u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
132 ASSERT(sih->cccaps & CC_CAP_PMU);
134 switch (CHIPID(sih->chip)) {
135 case BCM4336_CHIP_ID:
137 case SET_LDO_VOLTAGE_CLDO_PWM:
142 case SET_LDO_VOLTAGE_CLDO_BURST:
147 case SET_LDO_VOLTAGE_LNLDO1:
157 case BCM4330_CHIP_ID:
159 case SET_LDO_VOLTAGE_CBUCK_PWM:
174 shift = sr_cntl_shift + rc_shift;
176 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
178 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
179 mask << shift, (voltage & mask) << shift);
182 /* d11 slow to fast clock transition time in slow clock cycles */
183 #define D11SCC_SLOW2FAST_TRANSITION 2
185 u16 si_pmu_fast_pwrup_delay(si_t *sih, osl_t *osh)
187 uint delay = PMU_MAX_TRANSITION_DLY;
192 chn[0] = 0; /* to suppress compile error */
195 ASSERT(sih->cccaps & CC_CAP_PMU);
197 /* Remember original core before switch to chipc */
198 origidx = si_coreidx(sih);
199 cc = si_setcoreidx(sih, SI_CC_IDX);
202 switch (CHIPID(sih->chip)) {
203 case BCM43224_CHIP_ID:
204 case BCM43225_CHIP_ID:
205 case BCM43421_CHIP_ID:
206 case BCM43235_CHIP_ID:
207 case BCM43236_CHIP_ID:
208 case BCM43238_CHIP_ID:
209 case BCM4331_CHIP_ID:
210 case BCM6362_CHIP_ID:
211 case BCM4313_CHIP_ID:
212 delay = ISSIM_ENAB(sih) ? 70 : 3700;
214 case BCM4329_CHIP_ID:
218 u32 ilp = si_ilp_clock(sih);
220 (si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) +
221 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
223 delay = (11 * delay) / 10;
226 case BCM4319_CHIP_ID:
227 delay = ISSIM_ENAB(sih) ? 70 : 3700;
229 case BCM4336_CHIP_ID:
233 u32 ilp = si_ilp_clock(sih);
235 (si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) +
236 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
238 delay = (11 * delay) / 10;
241 case BCM4330_CHIP_ID:
245 u32 ilp = si_ilp_clock(sih);
247 (si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) +
248 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
250 delay = (11 * delay) / 10;
256 /* Return to original core */
257 si_setcoreidx(sih, origidx);
262 u32 si_pmu_force_ilp(si_t *sih, osl_t *osh, bool force)
268 ASSERT(sih->cccaps & CC_CAP_PMU);
270 /* Remember original core before switch to chipc */
271 origidx = si_coreidx(sih);
272 cc = si_setcoreidx(sih, SI_CC_IDX);
275 oldpmucontrol = R_REG(osh, &cc->pmucontrol);
277 W_REG(osh, &cc->pmucontrol, oldpmucontrol &
278 ~(PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN));
280 W_REG(osh, &cc->pmucontrol, oldpmucontrol |
281 (PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN));
283 /* Return to original core */
284 si_setcoreidx(sih, origidx);
286 return oldpmucontrol;
289 /* Setup resource up/down timers */
295 /* Change resource dependancies masks */
297 u32 res_mask; /* resources (chip specific) */
298 s8 action; /* action */
299 u32 depend_mask; /* changes to the dependancies mask */
300 bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return true */
303 /* Resource dependancies mask change action */
304 #define RES_DEPEND_SET 0 /* Override the dependancies mask */
305 #define RES_DEPEND_ADD 1 /* Add to the dependancies mask */
306 #define RES_DEPEND_REMOVE -1 /* Remove from the dependancies mask */
308 static const pmu_res_updown_t bcm4328a0_res_updown[] = {
310 RES4328_EXT_SWITCHER_PWM, 0x0101}, {
311 RES4328_BB_SWITCHER_PWM, 0x1f01}, {
312 RES4328_BB_SWITCHER_BURST, 0x010f}, {
313 RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, {
314 RES4328_ILP_REQUEST, 0x0202}, {
315 RES4328_RADIO_SWITCHER_PWM, 0x0f01}, {
316 RES4328_RADIO_SWITCHER_BURST, 0x0f01}, {
317 RES4328_ROM_SWITCH, 0x0101}, {
318 RES4328_PA_REF_LDO, 0x0f01}, {
319 RES4328_RADIO_LDO, 0x0f01}, {
320 RES4328_AFE_LDO, 0x0f01}, {
321 RES4328_PLL_LDO, 0x0f01}, {
322 RES4328_BG_FILTBYP, 0x0101}, {
323 RES4328_TX_FILTBYP, 0x0101}, {
324 RES4328_RX_FILTBYP, 0x0101}, {
325 RES4328_XTAL_PU, 0x0101}, {
326 RES4328_XTAL_EN, 0xa001}, {
327 RES4328_BB_PLL_FILTBYP, 0x0101}, {
328 RES4328_RF_PLL_FILTBYP, 0x0101}, {
329 RES4328_BB_PLL_PU, 0x0701}
332 static const pmu_res_depend_t bcm4328a0_res_depend[] = {
333 /* Adjust ILP request resource not to force ext/BB switchers into burst mode */
335 PMURES_BIT(RES4328_ILP_REQUEST),
337 PMURES_BIT(RES4328_EXT_SWITCHER_PWM) |
338 PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL}
341 static const pmu_res_updown_t bcm4325a0_res_updown_qt[] = {
343 RES4325_HT_AVAIL, 0x0300}, {
344 RES4325_BBPLL_PWRSW_PU, 0x0101}, {
345 RES4325_RFPLL_PWRSW_PU, 0x0101}, {
346 RES4325_ALP_AVAIL, 0x0100}, {
347 RES4325_XTAL_PU, 0x1000}, {
348 RES4325_LNLDO1_PU, 0x0800}, {
349 RES4325_CLDO_CBUCK_PWM, 0x0101}, {
350 RES4325_CBUCK_PWM, 0x0803}
353 static const pmu_res_updown_t bcm4325a0_res_updown[] = {
355 RES4325_XTAL_PU, 0x1501}
358 static const pmu_res_depend_t bcm4325a0_res_depend[] = {
359 /* Adjust OTP PU resource dependencies - remove BB BURST */
361 PMURES_BIT(RES4325_OTP_PU),
363 PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL},
364 /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */
366 PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL),
368 PMURES_BIT(RES4325_BUCK_BOOST_BURST) |
369 PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb},
370 /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
372 PMURES_BIT(RES4325_HT_AVAIL),
374 PMURES_BIT(RES4325_RX_PWRSW_PU) |
375 PMURES_BIT(RES4325_TX_PWRSW_PU) |
376 PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
377 PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL},
378 /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
380 PMURES_BIT(RES4325_ILP_REQUEST) |
381 PMURES_BIT(RES4325_ABUCK_BURST) |
382 PMURES_BIT(RES4325_ABUCK_PWM) |
383 PMURES_BIT(RES4325_LNLDO1_PU) |
384 PMURES_BIT(RES4325C1_LNLDO2_PU) |
385 PMURES_BIT(RES4325_XTAL_PU) |
386 PMURES_BIT(RES4325_ALP_AVAIL) |
387 PMURES_BIT(RES4325_RX_PWRSW_PU) |
388 PMURES_BIT(RES4325_TX_PWRSW_PU) |
389 PMURES_BIT(RES4325_RFPLL_PWRSW_PU) |
390 PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
391 PMURES_BIT(RES4325_AFE_PWRSW_PU) |
392 PMURES_BIT(RES4325_BBPLL_PWRSW_PU) |
393 PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE,
394 PMURES_BIT(RES4325B0_CBUCK_LPOM) |
395 PMURES_BIT(RES4325B0_CBUCK_BURST) |
396 PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb}
399 static const pmu_res_updown_t bcm4315a0_res_updown_qt[] = {
401 RES4315_HT_AVAIL, 0x0101}, {
402 RES4315_XTAL_PU, 0x0100}, {
403 RES4315_LNLDO1_PU, 0x0100}, {
404 RES4315_PALDO_PU, 0x0100}, {
405 RES4315_CLDO_PU, 0x0100}, {
406 RES4315_CBUCK_PWM, 0x0100}, {
407 RES4315_CBUCK_BURST, 0x0100}, {
408 RES4315_CBUCK_LPOM, 0x0100}
411 static const pmu_res_updown_t bcm4315a0_res_updown[] = {
413 RES4315_XTAL_PU, 0x2501}
416 static const pmu_res_depend_t bcm4315a0_res_depend[] = {
417 /* Adjust OTP PU resource dependencies - not need PALDO unless write */
419 PMURES_BIT(RES4315_OTP_PU),
421 PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo},
422 /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */
424 PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL),
426 PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo},
427 /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
429 PMURES_BIT(RES4315_HT_AVAIL),
431 PMURES_BIT(RES4315_RX_PWRSW_PU) |
432 PMURES_BIT(RES4315_TX_PWRSW_PU) |
433 PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
434 PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL},
435 /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
437 PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) |
438 PMURES_BIT(RES4315_LNLDO1_PU) |
439 PMURES_BIT(RES4315_OTP_PU) |
440 PMURES_BIT(RES4315_LNLDO2_PU) |
441 PMURES_BIT(RES4315_XTAL_PU) |
442 PMURES_BIT(RES4315_ALP_AVAIL) |
443 PMURES_BIT(RES4315_RX_PWRSW_PU) |
444 PMURES_BIT(RES4315_TX_PWRSW_PU) |
445 PMURES_BIT(RES4315_RFPLL_PWRSW_PU) |
446 PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
447 PMURES_BIT(RES4315_AFE_PWRSW_PU) |
448 PMURES_BIT(RES4315_BBPLL_PWRSW_PU) |
449 PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE,
450 PMURES_BIT(RES4315_CBUCK_LPOM) |
451 PMURES_BIT(RES4315_CBUCK_BURST) |
452 PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb}
455 /* 4329 specific. needs to come back this issue later */
456 static const pmu_res_updown_t bcm4329_res_updown[] = {
458 RES4329_XTAL_PU, 0x1501}
461 static const pmu_res_depend_t bcm4329_res_depend[] = {
462 /* Adjust HT Avail resource dependencies */
464 PMURES_BIT(RES4329_HT_AVAIL),
466 PMURES_BIT(RES4329_CBUCK_LPOM) |
467 PMURES_BIT(RES4329_CBUCK_BURST) |
468 PMURES_BIT(RES4329_CBUCK_PWM) |
469 PMURES_BIT(RES4329_CLDO_PU) |
470 PMURES_BIT(RES4329_PALDO_PU) |
471 PMURES_BIT(RES4329_LNLDO1_PU) |
472 PMURES_BIT(RES4329_XTAL_PU) |
473 PMURES_BIT(RES4329_ALP_AVAIL) |
474 PMURES_BIT(RES4329_RX_PWRSW_PU) |
475 PMURES_BIT(RES4329_TX_PWRSW_PU) |
476 PMURES_BIT(RES4329_RFPLL_PWRSW_PU) |
477 PMURES_BIT(RES4329_LOGEN_PWRSW_PU) |
478 PMURES_BIT(RES4329_AFE_PWRSW_PU) |
479 PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL}
482 static const pmu_res_updown_t bcm4319a0_res_updown_qt[] = {
484 RES4319_HT_AVAIL, 0x0101}, {
485 RES4319_XTAL_PU, 0x0100}, {
486 RES4319_LNLDO1_PU, 0x0100}, {
487 RES4319_PALDO_PU, 0x0100}, {
488 RES4319_CLDO_PU, 0x0100}, {
489 RES4319_CBUCK_PWM, 0x0100}, {
490 RES4319_CBUCK_BURST, 0x0100}, {
491 RES4319_CBUCK_LPOM, 0x0100}
494 static const pmu_res_updown_t bcm4319a0_res_updown[] = {
496 RES4319_XTAL_PU, 0x3f01}
499 static const pmu_res_depend_t bcm4319a0_res_depend[] = {
500 /* Adjust OTP PU resource dependencies - not need PALDO unless write */
502 PMURES_BIT(RES4319_OTP_PU),
504 PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo},
505 /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */
507 PMURES_BIT(RES4319_HT_AVAIL),
509 PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo},
510 /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
512 PMURES_BIT(RES4319_HT_AVAIL),
514 PMURES_BIT(RES4319_RX_PWRSW_PU) |
515 PMURES_BIT(RES4319_TX_PWRSW_PU) |
516 PMURES_BIT(RES4319_RFPLL_PWRSW_PU) |
517 PMURES_BIT(RES4319_LOGEN_PWRSW_PU) |
518 PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL}
521 static const pmu_res_updown_t bcm4336a0_res_updown_qt[] = {
523 RES4336_HT_AVAIL, 0x0101}, {
524 RES4336_XTAL_PU, 0x0100}, {
525 RES4336_CLDO_PU, 0x0100}, {
526 RES4336_CBUCK_PWM, 0x0100}, {
527 RES4336_CBUCK_BURST, 0x0100}, {
528 RES4336_CBUCK_LPOM, 0x0100}
531 static const pmu_res_updown_t bcm4336a0_res_updown[] = {
533 RES4336_HT_AVAIL, 0x0D01}
536 static const pmu_res_depend_t bcm4336a0_res_depend[] = {
537 /* Just a dummy entry for now */
539 PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL}
542 static const pmu_res_updown_t bcm4330a0_res_updown_qt[] = {
544 RES4330_HT_AVAIL, 0x0101}, {
545 RES4330_XTAL_PU, 0x0100}, {
546 RES4330_CLDO_PU, 0x0100}, {
547 RES4330_CBUCK_PWM, 0x0100}, {
548 RES4330_CBUCK_BURST, 0x0100}, {
549 RES4330_CBUCK_LPOM, 0x0100}
552 static const pmu_res_updown_t bcm4330a0_res_updown[] = {
554 RES4330_HT_AVAIL, 0x0e02}
557 static const pmu_res_depend_t bcm4330a0_res_depend[] = {
558 /* Just a dummy entry for now */
560 PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL}
563 /* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
564 static bool si_pmu_res_depfltr_bb(si_t *sih)
566 return (sih->boardflags & BFL_BUCKBOOST) != 0;
569 /* true if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
570 static bool si_pmu_res_depfltr_ncb(si_t *sih)
573 return (sih->boardflags & BFL_NOCBUCK) != 0;
576 /* true if the power topology uses the PALDO */
577 static bool si_pmu_res_depfltr_paldo(si_t *sih)
579 return (sih->boardflags & BFL_PALDO) != 0;
582 /* true if the power topology doesn't use the PALDO */
583 static bool si_pmu_res_depfltr_npaldo(si_t *sih)
585 return (sih->boardflags & BFL_PALDO) == 0;
588 #define BCM94325_BBVDDIOSD_BOARDS(sih) (sih->boardtype == BCM94325DEVBU_BOARD || \
589 sih->boardtype == BCM94325BGABU_BOARD)
591 /* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
592 static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
594 u32 min_mask = 0, max_mask = 0;
599 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
601 /* determine min/max rsrc masks */
602 switch (CHIPID(sih->chip)) {
603 case BCM43224_CHIP_ID:
604 case BCM43225_CHIP_ID:
605 case BCM43421_CHIP_ID:
606 case BCM43235_CHIP_ID:
607 case BCM43236_CHIP_ID:
608 case BCM43238_CHIP_ID:
609 case BCM4331_CHIP_ID:
610 case BCM6362_CHIP_ID:
614 case BCM4329_CHIP_ID:
615 /* 4329 spedific issue. Needs to come back this issue later */
616 /* Down to save the power. */
618 PMURES_BIT(RES4329_CBUCK_LPOM) |
619 PMURES_BIT(RES4329_CLDO_PU);
620 /* Allow (but don't require) PLL to turn on */
623 case BCM4319_CHIP_ID:
624 /* We only need a few resources to be kept on all the time */
625 min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
626 PMURES_BIT(RES4319_CLDO_PU);
628 /* Allow everything else to be turned on upon requests */
629 max_mask = ~(~0 << rsrcs);
631 case BCM4336_CHIP_ID:
632 /* Down to save the power. */
634 PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU)
635 | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU)
636 | PMURES_BIT(RES4336_DIS_INT_RESET_PD);
637 /* Allow (but don't require) PLL to turn on */
638 max_mask = 0x1ffffff;
641 case BCM4330_CHIP_ID:
642 /* Down to save the power. */
644 PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU)
645 | PMURES_BIT(RES4330_DIS_INT_RESET_PD) |
646 PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU);
647 /* Allow (but don't require) PLL to turn on */
648 max_mask = 0xfffffff;
651 case BCM4313_CHIP_ID:
652 min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
653 PMURES_BIT(RES4313_XTAL_PU_RSRC) |
654 PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
655 PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
662 /* Apply nvram override to min mask */
663 val = getvar(NULL, "rmin");
665 PMU_MSG(("Applying rmin=%s to min_mask\n", val));
666 min_mask = (u32) simple_strtoul(val, NULL, 0);
668 /* Apply nvram override to max mask */
669 val = getvar(NULL, "rmax");
671 PMU_MSG(("Applying rmax=%s to max_mask\n", val));
672 max_mask = (u32) simple_strtoul(val, NULL, 0);
679 /* initialize PMU resources */
680 void si_pmu_res_init(si_t *sih, osl_t *osh)
684 const pmu_res_updown_t *pmu_res_updown_table = NULL;
685 uint pmu_res_updown_table_sz = 0;
686 const pmu_res_depend_t *pmu_res_depend_table = NULL;
687 uint pmu_res_depend_table_sz = 0;
688 u32 min_mask = 0, max_mask = 0;
692 ASSERT(sih->cccaps & CC_CAP_PMU);
694 /* Remember original core before switch to chipc */
695 origidx = si_coreidx(sih);
696 cc = si_setcoreidx(sih, SI_CC_IDX);
699 switch (CHIPID(sih->chip)) {
700 case BCM4329_CHIP_ID:
701 /* Optimize resources up/down timers */
702 if (ISSIM_ENAB(sih)) {
703 pmu_res_updown_table = NULL;
704 pmu_res_updown_table_sz = 0;
706 pmu_res_updown_table = bcm4329_res_updown;
707 pmu_res_updown_table_sz = ARRAY_SIZE(bcm4329_res_updown);
709 /* Optimize resources dependencies */
710 pmu_res_depend_table = bcm4329_res_depend;
711 pmu_res_depend_table_sz = ARRAY_SIZE(bcm4329_res_depend);
714 case BCM4319_CHIP_ID:
715 /* Optimize resources up/down timers */
716 if (ISSIM_ENAB(sih)) {
717 pmu_res_updown_table = bcm4319a0_res_updown_qt;
718 pmu_res_updown_table_sz =
719 ARRAY_SIZE(bcm4319a0_res_updown_qt);
721 pmu_res_updown_table = bcm4319a0_res_updown;
722 pmu_res_updown_table_sz =
723 ARRAY_SIZE(bcm4319a0_res_updown);
725 /* Optimize resources dependancies masks */
726 pmu_res_depend_table = bcm4319a0_res_depend;
727 pmu_res_depend_table_sz = ARRAY_SIZE(bcm4319a0_res_depend);
730 case BCM4336_CHIP_ID:
731 /* Optimize resources up/down timers */
732 if (ISSIM_ENAB(sih)) {
733 pmu_res_updown_table = bcm4336a0_res_updown_qt;
734 pmu_res_updown_table_sz =
735 ARRAY_SIZE(bcm4336a0_res_updown_qt);
737 pmu_res_updown_table = bcm4336a0_res_updown;
738 pmu_res_updown_table_sz =
739 ARRAY_SIZE(bcm4336a0_res_updown);
741 /* Optimize resources dependancies masks */
742 pmu_res_depend_table = bcm4336a0_res_depend;
743 pmu_res_depend_table_sz = ARRAY_SIZE(bcm4336a0_res_depend);
746 case BCM4330_CHIP_ID:
747 /* Optimize resources up/down timers */
748 if (ISSIM_ENAB(sih)) {
749 pmu_res_updown_table = bcm4330a0_res_updown_qt;
750 pmu_res_updown_table_sz =
751 ARRAY_SIZE(bcm4330a0_res_updown_qt);
753 pmu_res_updown_table = bcm4330a0_res_updown;
754 pmu_res_updown_table_sz =
755 ARRAY_SIZE(bcm4330a0_res_updown);
757 /* Optimize resources dependancies masks */
758 pmu_res_depend_table = bcm4330a0_res_depend;
759 pmu_res_depend_table_sz = ARRAY_SIZE(bcm4330a0_res_depend);
767 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
769 /* Program up/down timers */
770 while (pmu_res_updown_table_sz--) {
771 ASSERT(pmu_res_updown_table != NULL);
772 PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n",
773 pmu_res_updown_table[pmu_res_updown_table_sz].resnum,
774 pmu_res_updown_table[pmu_res_updown_table_sz].updown));
775 W_REG(osh, &cc->res_table_sel,
776 pmu_res_updown_table[pmu_res_updown_table_sz].resnum);
777 W_REG(osh, &cc->res_updn_timer,
778 pmu_res_updown_table[pmu_res_updown_table_sz].updown);
780 /* Apply nvram overrides to up/down timers */
781 for (i = 0; i < rsrcs; i++) {
782 snprintf(name, sizeof(name), "r%dt", i);
783 val = getvar(NULL, name);
786 PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name,
788 W_REG(osh, &cc->res_table_sel, (u32) i);
789 W_REG(osh, &cc->res_updn_timer,
790 (u32) simple_strtoul(val, NULL, 0));
793 /* Program resource dependencies table */
794 while (pmu_res_depend_table_sz--) {
795 ASSERT(pmu_res_depend_table != NULL);
796 if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL
797 && !(pmu_res_depend_table[pmu_res_depend_table_sz].
800 for (i = 0; i < rsrcs; i++) {
801 if ((pmu_res_depend_table[pmu_res_depend_table_sz].
802 res_mask & PMURES_BIT(i)) == 0)
804 W_REG(osh, &cc->res_table_sel, i);
805 switch (pmu_res_depend_table[pmu_res_depend_table_sz].
808 PMU_MSG(("Changing rsrc %d res_dep_mask to 0x%x\n", i, pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask));
809 W_REG(osh, &cc->res_dep_mask,
811 [pmu_res_depend_table_sz].depend_mask);
814 PMU_MSG(("Adding 0x%x to rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i));
815 OR_REG(osh, &cc->res_dep_mask,
817 [pmu_res_depend_table_sz].depend_mask);
819 case RES_DEPEND_REMOVE:
820 PMU_MSG(("Removing 0x%x from rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i));
821 AND_REG(osh, &cc->res_dep_mask,
822 ~pmu_res_depend_table
823 [pmu_res_depend_table_sz].depend_mask);
831 /* Apply nvram overrides to dependancies masks */
832 for (i = 0; i < rsrcs; i++) {
833 snprintf(name, sizeof(name), "r%dd", i);
834 val = getvar(NULL, name);
837 PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val,
839 W_REG(osh, &cc->res_table_sel, (u32) i);
840 W_REG(osh, &cc->res_dep_mask,
841 (u32) simple_strtoul(val, NULL, 0));
844 /* Determine min/max rsrc masks */
845 si_pmu_res_masks(sih, &min_mask, &max_mask);
847 /* It is required to program max_mask first and then min_mask */
849 /* Program max resource mask */
852 PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask));
853 W_REG(osh, &cc->max_res_mask, max_mask);
856 /* Program min resource mask */
859 PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask));
860 W_REG(osh, &cc->min_res_mask, min_mask);
863 /* Add some delay; allow resources to come up and settle. */
866 /* Return to original core */
867 si_setcoreidx(sih, origidx);
870 /* setup pll and query clock speed */
878 /* the following table is based on 880Mhz fvco */
879 static const pmu0_xtaltab0_t pmu0_xtaltab0[] = {
881 12000, 1, 73, 349525}, {
882 13000, 2, 67, 725937}, {
883 14400, 3, 61, 116508}, {
884 15360, 4, 57, 305834}, {
885 16200, 5, 54, 336579}, {
886 16800, 6, 52, 399457}, {
887 19200, 7, 45, 873813}, {
888 19800, 8, 44, 466033}, {
890 25000, 10, 70, 419430}, {
891 26000, 11, 67, 725937}, {
892 30000, 12, 58, 699050}, {
893 38400, 13, 45, 873813}, {
898 #define PMU0_XTAL0_DEFAULT 8
900 /* setup pll and query clock speed */
910 static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = {
912 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
913 13000, 2, 1, 6, 0xb, 0x483483}, {
914 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
915 15360, 4, 1, 5, 0xb, 0x755555}, {
916 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
917 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
918 19200, 7, 1, 4, 0xb, 0x755555}, {
919 19800, 8, 1, 11, 0x4, 0xA57EB}, {
920 20000, 9, 1, 11, 0x4, 0x0}, {
921 24000, 10, 3, 11, 0xa, 0x0}, {
922 25000, 11, 5, 16, 0xb, 0x0}, {
923 26000, 12, 1, 1, 0x21, 0xD89D89}, {
924 30000, 13, 3, 8, 0xb, 0x0}, {
925 37400, 14, 3, 1, 0x46, 0x969696}, {
926 38400, 15, 1, 1, 0x16, 0xEAAAAA}, {
927 40000, 16, 1, 2, 0xb, 0}, {
931 /* the following table is based on 880Mhz fvco */
932 static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = {
934 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
935 13000, 2, 1, 6, 0xb, 0x483483}, {
936 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
937 15360, 4, 1, 5, 0xb, 0x755555}, {
938 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
939 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
940 19200, 7, 1, 4, 0xb, 0x755555}, {
941 19800, 8, 1, 11, 0x4, 0xA57EB}, {
942 20000, 9, 1, 11, 0x4, 0x0}, {
943 24000, 10, 3, 11, 0xa, 0x0}, {
944 25000, 11, 5, 16, 0xb, 0x0}, {
945 26000, 12, 1, 2, 0x10, 0xEC4EC4}, {
946 30000, 13, 3, 8, 0xb, 0x0}, {
947 33600, 14, 1, 2, 0xd, 0x186186}, {
948 38400, 15, 1, 2, 0xb, 0x755555}, {
949 40000, 16, 1, 2, 0xb, 0}, {
953 #define PMU1_XTALTAB0_880_12000K 0
954 #define PMU1_XTALTAB0_880_13000K 1
955 #define PMU1_XTALTAB0_880_14400K 2
956 #define PMU1_XTALTAB0_880_15360K 3
957 #define PMU1_XTALTAB0_880_16200K 4
958 #define PMU1_XTALTAB0_880_16800K 5
959 #define PMU1_XTALTAB0_880_19200K 6
960 #define PMU1_XTALTAB0_880_19800K 7
961 #define PMU1_XTALTAB0_880_20000K 8
962 #define PMU1_XTALTAB0_880_24000K 9
963 #define PMU1_XTALTAB0_880_25000K 10
964 #define PMU1_XTALTAB0_880_26000K 11
965 #define PMU1_XTALTAB0_880_30000K 12
966 #define PMU1_XTALTAB0_880_37400K 13
967 #define PMU1_XTALTAB0_880_38400K 14
968 #define PMU1_XTALTAB0_880_40000K 15
970 /* the following table is based on 1760Mhz fvco */
971 static const pmu1_xtaltab0_t pmu1_xtaltab0_1760[] = {
973 12000, 1, 3, 44, 0x9, 0xFFFFEF}, {
974 13000, 2, 1, 12, 0xb, 0x483483}, {
975 14400, 3, 1, 20, 0xa, 0x1C71C7}, {
976 15360, 4, 1, 10, 0xb, 0x755555}, {
977 16200, 5, 1, 20, 0x5, 0x6E9E06}, {
978 16800, 6, 1, 20, 0x5, 0x3Cf3Cf}, {
979 19200, 7, 1, 18, 0x5, 0x17B425}, {
980 19800, 8, 1, 22, 0x4, 0xA57EB}, {
981 20000, 9, 1, 22, 0x4, 0x0}, {
982 24000, 10, 3, 22, 0xa, 0x0}, {
983 25000, 11, 5, 32, 0xb, 0x0}, {
984 26000, 12, 1, 4, 0x10, 0xEC4EC4}, {
985 30000, 13, 3, 16, 0xb, 0x0}, {
986 38400, 14, 1, 10, 0x4, 0x955555}, {
987 40000, 15, 1, 4, 0xb, 0}, {
992 #define PMU1_XTALTAB0_1760_12000K 0
993 #define PMU1_XTALTAB0_1760_13000K 1
994 #define PMU1_XTALTAB0_1760_14400K 2
995 #define PMU1_XTALTAB0_1760_15360K 3
996 #define PMU1_XTALTAB0_1760_16200K 4
997 #define PMU1_XTALTAB0_1760_16800K 5
998 #define PMU1_XTALTAB0_1760_19200K 6
999 #define PMU1_XTALTAB0_1760_19800K 7
1000 #define PMU1_XTALTAB0_1760_20000K 8
1001 #define PMU1_XTALTAB0_1760_24000K 9
1002 #define PMU1_XTALTAB0_1760_25000K 10
1003 #define PMU1_XTALTAB0_1760_26000K 11
1004 #define PMU1_XTALTAB0_1760_30000K 12
1005 #define PMU1_XTALTAB0_1760_38400K 13
1006 #define PMU1_XTALTAB0_1760_40000K 14
1008 /* the following table is based on 1440Mhz fvco */
1009 static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = {
1011 12000, 1, 1, 1, 0x78, 0x0}, {
1012 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, {
1013 14400, 3, 1, 1, 0x64, 0x0}, {
1014 15360, 4, 1, 1, 0x5D, 0xC00000}, {
1015 16200, 5, 1, 1, 0x58, 0xE38E38}, {
1016 16800, 6, 1, 1, 0x55, 0xB6DB6D}, {
1017 19200, 7, 1, 1, 0x4B, 0}, {
1018 19800, 8, 1, 1, 0x48, 0xBA2E8B}, {
1019 20000, 9, 1, 1, 0x48, 0x0}, {
1020 25000, 10, 1, 1, 0x39, 0x999999}, {
1021 26000, 11, 1, 1, 0x37, 0x627627}, {
1022 30000, 12, 1, 1, 0x30, 0x0}, {
1023 37400, 13, 2, 1, 0x4D, 0x15E76}, {
1024 38400, 13, 2, 1, 0x4B, 0x0}, {
1025 40000, 14, 2, 1, 0x48, 0x0}, {
1026 48000, 15, 2, 1, 0x3c, 0x0}, {
1031 #define PMU1_XTALTAB0_1440_12000K 0
1032 #define PMU1_XTALTAB0_1440_13000K 1
1033 #define PMU1_XTALTAB0_1440_14400K 2
1034 #define PMU1_XTALTAB0_1440_15360K 3
1035 #define PMU1_XTALTAB0_1440_16200K 4
1036 #define PMU1_XTALTAB0_1440_16800K 5
1037 #define PMU1_XTALTAB0_1440_19200K 6
1038 #define PMU1_XTALTAB0_1440_19800K 7
1039 #define PMU1_XTALTAB0_1440_20000K 8
1040 #define PMU1_XTALTAB0_1440_25000K 9
1041 #define PMU1_XTALTAB0_1440_26000K 10
1042 #define PMU1_XTALTAB0_1440_30000K 11
1043 #define PMU1_XTALTAB0_1440_37400K 12
1044 #define PMU1_XTALTAB0_1440_38400K 13
1045 #define PMU1_XTALTAB0_1440_40000K 14
1046 #define PMU1_XTALTAB0_1440_48000K 15
1048 #define XTAL_FREQ_24000MHZ 24000
1049 #define XTAL_FREQ_30000MHZ 30000
1050 #define XTAL_FREQ_37400MHZ 37400
1051 #define XTAL_FREQ_48000MHZ 48000
1053 static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = {
1055 12000, 1, 1, 1, 0x50, 0x0}, {
1056 13000, 2, 1, 1, 0x49, 0xD89D89}, {
1057 14400, 3, 1, 1, 0x42, 0xAAAAAA}, {
1058 15360, 4, 1, 1, 0x3E, 0x800000}, {
1059 16200, 5, 1, 1, 0x39, 0x425ED0}, {
1060 16800, 6, 1, 1, 0x39, 0x249249}, {
1061 19200, 7, 1, 1, 0x32, 0x0}, {
1062 19800, 8, 1, 1, 0x30, 0x7C1F07}, {
1063 20000, 9, 1, 1, 0x30, 0x0}, {
1064 25000, 10, 1, 1, 0x26, 0x666666}, {
1065 26000, 11, 1, 1, 0x24, 0xEC4EC4}, {
1066 30000, 12, 1, 1, 0x20, 0x0}, {
1067 37400, 13, 2, 1, 0x33, 0x563EF9}, {
1068 38400, 14, 2, 1, 0x32, 0x0}, {
1069 40000, 15, 2, 1, 0x30, 0x0}, {
1070 48000, 16, 2, 1, 0x28, 0x0}, {
1075 #define PMU1_XTALTAB0_960_12000K 0
1076 #define PMU1_XTALTAB0_960_13000K 1
1077 #define PMU1_XTALTAB0_960_14400K 2
1078 #define PMU1_XTALTAB0_960_15360K 3
1079 #define PMU1_XTALTAB0_960_16200K 4
1080 #define PMU1_XTALTAB0_960_16800K 5
1081 #define PMU1_XTALTAB0_960_19200K 6
1082 #define PMU1_XTALTAB0_960_19800K 7
1083 #define PMU1_XTALTAB0_960_20000K 8
1084 #define PMU1_XTALTAB0_960_25000K 9
1085 #define PMU1_XTALTAB0_960_26000K 10
1086 #define PMU1_XTALTAB0_960_30000K 11
1087 #define PMU1_XTALTAB0_960_37400K 12
1088 #define PMU1_XTALTAB0_960_38400K 13
1089 #define PMU1_XTALTAB0_960_40000K 14
1090 #define PMU1_XTALTAB0_960_48000K 15
1092 /* select xtal table for each chip */
1093 static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(si_t *sih)
1098 switch (CHIPID(sih->chip)) {
1099 case BCM4329_CHIP_ID:
1100 return pmu1_xtaltab0_880_4329;
1101 case BCM4319_CHIP_ID:
1102 return pmu1_xtaltab0_1440;
1103 case BCM4336_CHIP_ID:
1104 return pmu1_xtaltab0_960;
1105 case BCM4330_CHIP_ID:
1106 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1107 return pmu1_xtaltab0_960;
1109 return pmu1_xtaltab0_1440;
1111 PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n",
1112 bcm_chipname(sih->chip, chn, 8)));
1119 /* select default xtal frequency for each chip */
1120 static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(si_t *sih)
1126 switch (CHIPID(sih->chip)) {
1127 case BCM4329_CHIP_ID:
1128 /* Default to 38400Khz */
1129 return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K];
1130 case BCM4319_CHIP_ID:
1131 /* Default to 30000Khz */
1132 return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K];
1133 case BCM4336_CHIP_ID:
1134 /* Default to 26000Khz */
1135 return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K];
1136 case BCM4330_CHIP_ID:
1137 /* Default to 37400Khz */
1138 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1139 return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K];
1141 return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K];
1143 PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n",
1144 bcm_chipname(sih->chip, chn, 8)));
1151 /* select default pll fvco for each chip */
1152 static u32 si_pmu1_pllfvco0(si_t *sih)
1158 switch (CHIPID(sih->chip)) {
1159 case BCM4329_CHIP_ID:
1161 case BCM4319_CHIP_ID:
1163 case BCM4336_CHIP_ID:
1165 case BCM4330_CHIP_ID:
1166 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1171 PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n",
1172 bcm_chipname(sih->chip, chn, 8)));
1179 /* query alp/xtal clock frequency */
1181 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc)
1183 const pmu1_xtaltab0_t *xt;
1186 /* Find the frequency in the table */
1187 xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
1188 PCTL_XTALFREQ_SHIFT;
1189 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
1192 /* Could not find it so assign a default value */
1193 if (xt == NULL || xt->fref == 0)
1194 xt = si_pmu1_xtaldef0(sih);
1195 ASSERT(xt != NULL && xt->fref != 0);
1197 return xt->fref * 1000;
1200 /* Set up PLL registers in the PMU as per the crystal speed.
1201 * XtalFreq field in pmucontrol register being 0 indicates the PLL
1202 * is not programmed and the h/w default is assumed to work, in which
1203 * case the xtal frequency is unknown to the s/w so we need to call
1204 * si_pmu1_xtaldef0() wherever it is needed to return a default value.
1206 static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
1208 const pmu1_xtaltab0_t *xt;
1210 u32 buf_strength = 0;
1213 /* Use h/w default PLL config */
1215 PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n"));
1219 /* Find the frequency in the table */
1220 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
1221 if (xt->fref == xtal)
1224 /* Check current PLL state, bail out if it has been programmed or
1225 * we don't know how to program it.
1227 if (xt == NULL || xt->fref == 0) {
1228 PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n", xtal / 1000, xtal % 1000));
1231 /* for 4319 bootloader already programs the PLL but bootloader does not program the
1232 PLL4 and PLL5. So Skip this check for 4319
1234 if ((((R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
1235 PCTL_XTALFREQ_SHIFT) == xt->xf) &&
1236 !((CHIPID(sih->chip) == BCM4319_CHIP_ID)
1237 || (CHIPID(sih->chip) == BCM4330_CHIP_ID))) {
1238 PMU_MSG(("PLL already programmed for %d.%d MHz\n",
1239 xt->fref / 1000, xt->fref % 1000));
1243 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
1244 PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000,
1247 switch (CHIPID(sih->chip)) {
1248 case BCM4329_CHIP_ID:
1249 /* Change the BBPLL drive strength to 8 for all channels */
1250 buf_strength = 0x888888;
1251 AND_REG(osh, &cc->min_res_mask,
1252 ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
1253 PMURES_BIT(RES4329_HT_AVAIL)));
1254 AND_REG(osh, &cc->max_res_mask,
1255 ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
1256 PMURES_BIT(RES4329_HT_AVAIL)));
1257 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1258 PMU_MAX_TRANSITION_DLY);
1259 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1260 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
1261 if (xt->fref == 38400)
1263 else if (xt->fref == 37400)
1265 else if (xt->fref == 26000)
1268 tmp = 0x200005C0; /* Chip Dflt Settings */
1269 W_REG(osh, &cc->pllcontrol_data, tmp);
1270 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
1273 &cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK;
1274 if ((xt->fref == 38400) || (xt->fref == 37400)
1275 || (xt->fref == 26000))
1278 tmp |= 0x25; /* Chip Dflt Settings */
1279 W_REG(osh, &cc->pllcontrol_data, tmp);
1282 case BCM4319_CHIP_ID:
1283 /* Change the BBPLL drive strength to 2 for all channels */
1284 buf_strength = 0x222222;
1286 /* Make sure the PLL is off */
1287 /* WAR65104: Disable the HT_AVAIL resource first and then
1288 * after a delay (more than downtime for HT_AVAIL) remove the
1289 * BBPLL resource; backplane clock moves to ALP from HT.
1291 AND_REG(osh, &cc->min_res_mask,
1292 ~(PMURES_BIT(RES4319_HT_AVAIL)));
1293 AND_REG(osh, &cc->max_res_mask,
1294 ~(PMURES_BIT(RES4319_HT_AVAIL)));
1297 AND_REG(osh, &cc->min_res_mask,
1298 ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
1299 AND_REG(osh, &cc->max_res_mask,
1300 ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
1303 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1304 PMU_MAX_TRANSITION_DLY);
1305 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1306 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
1308 W_REG(osh, &cc->pllcontrol_data, tmp);
1311 case BCM4336_CHIP_ID:
1312 AND_REG(osh, &cc->min_res_mask,
1313 ~(PMURES_BIT(RES4336_HT_AVAIL) |
1314 PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
1315 AND_REG(osh, &cc->max_res_mask,
1316 ~(PMURES_BIT(RES4336_HT_AVAIL) |
1317 PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
1319 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1320 PMU_MAX_TRANSITION_DLY);
1321 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1324 case BCM4330_CHIP_ID:
1325 AND_REG(osh, &cc->min_res_mask,
1326 ~(PMURES_BIT(RES4330_HT_AVAIL) |
1327 PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
1328 AND_REG(osh, &cc->max_res_mask,
1329 ~(PMURES_BIT(RES4330_HT_AVAIL) |
1330 PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
1332 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1333 PMU_MAX_TRANSITION_DLY);
1334 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1341 PMU_MSG(("Done masking\n"));
1343 /* Write p1div and p2div to pllcontrol[0] */
1344 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
1345 tmp = R_REG(osh, &cc->pllcontrol_data) &
1346 ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK);
1349 p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
1351 p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK);
1352 W_REG(osh, &cc->pllcontrol_data, tmp);
1354 if ((CHIPID(sih->chip) == BCM4330_CHIP_ID))
1355 si_pmu_set_4330_plldivs(sih);
1357 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID)
1358 && (CHIPREV(sih->chiprev) == 0)) {
1360 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
1361 tmp = R_REG(osh, &cc->pllcontrol_data);
1362 tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK);
1363 tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL;
1364 W_REG(osh, &cc->pllcontrol_data, tmp);
1366 if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
1367 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
1368 (CHIPID(sih->chip) == BCM4330_CHIP_ID))
1369 ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB;
1371 ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH;
1373 /* Write ndiv_int and ndiv_mode to pllcontrol[2] */
1374 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
1375 tmp = R_REG(osh, &cc->pllcontrol_data) &
1376 ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK);
1379 ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) &
1380 PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode <<
1381 PMU1_PLL0_PC2_NDIV_MODE_SHIFT) &
1382 PMU1_PLL0_PC2_NDIV_MODE_MASK);
1383 W_REG(osh, &cc->pllcontrol_data, tmp);
1385 /* Write ndiv_frac to pllcontrol[3] */
1386 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
1387 tmp = R_REG(osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
1388 tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) &
1389 PMU1_PLL0_PC3_NDIV_FRAC_MASK);
1390 W_REG(osh, &cc->pllcontrol_data, tmp);
1392 /* Write clock driving strength to pllcontrol[5] */
1394 PMU_MSG(("Adjusting PLL buffer drive strength: %x\n",
1397 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
1400 &cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
1401 tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT);
1402 W_REG(osh, &cc->pllcontrol_data, tmp);
1405 PMU_MSG(("Done pll\n"));
1407 /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs
1410 if ((CHIPID(sih->chip) == BCM4319_CHIP_ID)
1411 && (xt->fref != XTAL_FREQ_30000MHZ)) {
1412 W_REG(osh, &cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
1415 &cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK;
1416 if (xt->fref == XTAL_FREQ_24000MHZ) {
1418 (CCTL_4319USB_24MHZ_PLL_SEL <<
1419 CCTL_4319USB_XTAL_SEL_SHIFT);
1420 } else if (xt->fref == XTAL_FREQ_48000MHZ) {
1422 (CCTL_4319USB_48MHZ_PLL_SEL <<
1423 CCTL_4319USB_XTAL_SEL_SHIFT);
1425 W_REG(osh, &cc->chipcontrol_data, tmp);
1428 /* Flush deferred pll control registers writes */
1429 if (sih->pmurev >= 2)
1430 OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
1432 /* Write XtalFreq. Set the divisor also. */
1433 tmp = R_REG(osh, &cc->pmucontrol) &
1434 ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK);
1435 tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) &
1436 PCTL_ILP_DIV_MASK) |
1437 ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
1439 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID)
1440 && CHIPREV(sih->chiprev) == 0) {
1441 /* clear the htstretch before clearing HTReqEn */
1442 AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT);
1443 tmp &= ~PCTL_HT_REQ_EN;
1446 W_REG(osh, &cc->pmucontrol, tmp);
1449 /* query the CPU clock frequency */
1451 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc)
1455 u32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
1458 u32 FVCO = si_pmu1_pllfvco0(sih);
1460 /* Read m1div from pllcontrol[1] */
1461 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
1462 tmp = R_REG(osh, &cc->pllcontrol_data);
1463 m1div = (tmp & PMU1_PLL0_PC1_M1DIV_MASK) >> PMU1_PLL0_PC1_M1DIV_SHIFT;
1466 /* Read p2div/p1div from pllcontrol[0] */
1467 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
1468 tmp = R_REG(osh, &cc->pllcontrol_data);
1469 p2div = (tmp & PMU1_PLL0_PC0_P2DIV_MASK) >> PMU1_PLL0_PC0_P2DIV_SHIFT;
1470 p1div = (tmp & PMU1_PLL0_PC0_P1DIV_MASK) >> PMU1_PLL0_PC0_P1DIV_SHIFT;
1472 /* Calculate fvco based on xtal freq and ndiv and pdiv */
1473 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
1474 tmp = R_REG(osh, &cc->pllcontrol_data);
1476 (tmp & PMU1_PLL0_PC2_NDIV_INT_MASK) >> PMU1_PLL0_PC2_NDIV_INT_SHIFT;
1478 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
1479 tmp = R_REG(osh, &cc->pllcontrol_data);
1481 (tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >>
1482 PMU1_PLL0_PC3_NDIV_FRAC_SHIFT;
1484 fref = si_pmu1_alpclk0(sih, osh, cc) / 1000;
1486 fvco = (fref * ndiv_int) << 8;
1487 fvco += (fref * (ndiv_frac >> 12)) >> 4;
1488 fvco += (fref * (ndiv_frac & 0xfff)) >> 12;
1495 PMU_MSG(("si_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco));
1500 /* Return ARM/SB clock */
1501 return FVCO / m1div * 1000;
1504 /* initialize PLL */
1505 void si_pmu_pll_init(si_t *sih, osl_t *osh, uint xtalfreq)
1513 ASSERT(sih->cccaps & CC_CAP_PMU);
1515 /* Remember original core before switch to chipc */
1516 origidx = si_coreidx(sih);
1517 cc = si_setcoreidx(sih, SI_CC_IDX);
1520 switch (CHIPID(sih->chip)) {
1521 case BCM4329_CHIP_ID:
1524 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
1526 case BCM4313_CHIP_ID:
1527 case BCM43224_CHIP_ID:
1528 case BCM43225_CHIP_ID:
1529 case BCM43421_CHIP_ID:
1530 case BCM43235_CHIP_ID:
1531 case BCM43236_CHIP_ID:
1532 case BCM43238_CHIP_ID:
1533 case BCM4331_CHIP_ID:
1534 case BCM6362_CHIP_ID:
1537 case BCM4319_CHIP_ID:
1538 case BCM4336_CHIP_ID:
1539 case BCM4330_CHIP_ID:
1540 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
1543 PMU_MSG(("No PLL init done for chip %s rev %d pmurev %d\n",
1544 bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1549 #ifdef BCMDBG_FORCEHT
1550 OR_REG(osh, &cc->clk_ctl_st, CCS_FORCEHT);
1553 /* Return to original core */
1554 si_setcoreidx(sih, origidx);
1557 /* query alp/xtal clock frequency */
1558 u32 si_pmu_alp_clock(si_t *sih, osl_t *osh)
1562 u32 clock = ALP_CLOCK;
1567 ASSERT(sih->cccaps & CC_CAP_PMU);
1569 /* Remember original core before switch to chipc */
1570 origidx = si_coreidx(sih);
1571 cc = si_setcoreidx(sih, SI_CC_IDX);
1574 switch (CHIPID(sih->chip)) {
1575 case BCM43224_CHIP_ID:
1576 case BCM43225_CHIP_ID:
1577 case BCM43421_CHIP_ID:
1578 case BCM43235_CHIP_ID:
1579 case BCM43236_CHIP_ID:
1580 case BCM43238_CHIP_ID:
1581 case BCM4331_CHIP_ID:
1582 case BCM6362_CHIP_ID:
1583 case BCM4716_CHIP_ID:
1584 case BCM4748_CHIP_ID:
1585 case BCM47162_CHIP_ID:
1586 case BCM4313_CHIP_ID:
1587 case BCM5357_CHIP_ID:
1589 clock = 20000 * 1000;
1591 case BCM4329_CHIP_ID:
1592 case BCM4319_CHIP_ID:
1593 case BCM4336_CHIP_ID:
1594 case BCM4330_CHIP_ID:
1596 clock = si_pmu1_alpclk0(sih, osh, cc);
1598 case BCM5356_CHIP_ID:
1600 clock = 25000 * 1000;
1603 PMU_MSG(("No ALP clock specified "
1604 "for chip %s rev %d pmurev %d, using default %d Hz\n",
1605 bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1606 sih->pmurev, clock));
1610 /* Return to original core */
1611 si_setcoreidx(sih, origidx);
1615 /* Find the output of the "m" pll divider given pll controls that start with
1616 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
1619 si_pmu5_clock(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0,
1621 u32 tmp, div, ndiv, p1, p2, fc;
1623 if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) {
1624 PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0));
1628 /* Strictly there is an m5 divider, but I'm not sure we use it */
1629 if ((m == 0) || (m > 4)) {
1630 PMU_ERROR(("%s: Bad m divider: %d\n", __func__, m));
1634 if (CHIPID(sih->chip) == BCM5357_CHIP_ID) {
1635 /* Detect failure in clock setting */
1636 if ((R_REG(osh, &cc->chipstatus) & 0x40000) != 0) {
1637 return 133 * 1000000;
1641 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF);
1642 (void)R_REG(osh, &cc->pllcontrol_addr);
1643 tmp = R_REG(osh, &cc->pllcontrol_data);
1644 p1 = (tmp & PMU5_PLL_P1_MASK) >> PMU5_PLL_P1_SHIFT;
1645 p2 = (tmp & PMU5_PLL_P2_MASK) >> PMU5_PLL_P2_SHIFT;
1647 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF);
1648 (void)R_REG(osh, &cc->pllcontrol_addr);
1649 tmp = R_REG(osh, &cc->pllcontrol_data);
1650 div = (tmp >> ((m - 1) * PMU5_PLL_MDIV_WIDTH)) & PMU5_PLL_MDIV_MASK;
1652 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF);
1653 (void)R_REG(osh, &cc->pllcontrol_addr);
1654 tmp = R_REG(osh, &cc->pllcontrol_data);
1655 ndiv = (tmp & PMU5_PLL_NDIV_MASK) >> PMU5_PLL_NDIV_SHIFT;
1657 /* Do calculation in Mhz */
1658 fc = si_pmu_alp_clock(sih, osh) / 1000000;
1659 fc = (p1 * ndiv * fc) / p2;
1661 PMU_NONE(("%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n",
1662 __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div));
1664 /* Return clock in Hertz */
1665 return (fc / div) * 1000000;
1668 /* query backplane clock frequency */
1669 /* For designs that feed the same clock to both backplane
1670 * and CPU just return the CPU clock speed.
1672 u32 si_pmu_si_clock(si_t *sih, osl_t *osh)
1676 u32 clock = HT_CLOCK;
1681 ASSERT(sih->cccaps & CC_CAP_PMU);
1683 /* Remember original core before switch to chipc */
1684 origidx = si_coreidx(sih);
1685 cc = si_setcoreidx(sih, SI_CC_IDX);
1688 switch (CHIPID(sih->chip)) {
1689 case BCM43224_CHIP_ID:
1690 case BCM43225_CHIP_ID:
1691 case BCM43421_CHIP_ID:
1692 case BCM4331_CHIP_ID:
1693 case BCM6362_CHIP_ID:
1694 /* 96MHz backplane clock */
1695 clock = 96000 * 1000;
1697 case BCM4716_CHIP_ID:
1698 case BCM4748_CHIP_ID:
1699 case BCM47162_CHIP_ID:
1701 si_pmu5_clock(sih, osh, cc, PMU4716_MAINPLL_PLL0,
1704 case BCM4329_CHIP_ID:
1705 if (CHIPREV(sih->chiprev) == 0)
1706 clock = 38400 * 1000;
1708 clock = si_pmu1_cpuclk0(sih, osh, cc);
1710 case BCM4319_CHIP_ID:
1711 case BCM4336_CHIP_ID:
1712 case BCM4330_CHIP_ID:
1713 clock = si_pmu1_cpuclk0(sih, osh, cc);
1715 case BCM4313_CHIP_ID:
1716 /* 80MHz backplane clock */
1717 clock = 80000 * 1000;
1719 case BCM43235_CHIP_ID:
1720 case BCM43236_CHIP_ID:
1721 case BCM43238_CHIP_ID:
1723 (cc->chipstatus & CST43236_BP_CLK) ? (120000 *
1727 case BCM5356_CHIP_ID:
1729 si_pmu5_clock(sih, osh, cc, PMU5356_MAINPLL_PLL0,
1732 case BCM5357_CHIP_ID:
1734 si_pmu5_clock(sih, osh, cc, PMU5357_MAINPLL_PLL0,
1738 PMU_MSG(("No backplane clock specified "
1739 "for chip %s rev %d pmurev %d, using default %d Hz\n",
1740 bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1741 sih->pmurev, clock));
1745 /* Return to original core */
1746 si_setcoreidx(sih, origidx);
1750 /* query CPU clock frequency */
1751 u32 si_pmu_cpu_clock(si_t *sih, osl_t *osh)
1757 ASSERT(sih->cccaps & CC_CAP_PMU);
1759 if ((sih->pmurev >= 5) &&
1760 !((CHIPID(sih->chip) == BCM4329_CHIP_ID) ||
1761 (CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
1762 (CHIPID(sih->chip) == BCM43236_CHIP_ID) ||
1763 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
1764 (CHIPID(sih->chip) == BCM4330_CHIP_ID))) {
1767 switch (CHIPID(sih->chip)) {
1768 case BCM5356_CHIP_ID:
1769 pll = PMU5356_MAINPLL_PLL0;
1771 case BCM5357_CHIP_ID:
1772 pll = PMU5357_MAINPLL_PLL0;
1775 pll = PMU4716_MAINPLL_PLL0;
1779 /* Remember original core before switch to chipc */
1780 origidx = si_coreidx(sih);
1781 cc = si_setcoreidx(sih, SI_CC_IDX);
1784 clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_CPU);
1786 /* Return to original core */
1787 si_setcoreidx(sih, origidx);
1789 clock = si_pmu_si_clock(sih, osh);
1794 /* query memory clock frequency */
1795 u32 si_pmu_mem_clock(si_t *sih, osl_t *osh)
1801 ASSERT(sih->cccaps & CC_CAP_PMU);
1803 if ((sih->pmurev >= 5) &&
1804 !((CHIPID(sih->chip) == BCM4329_CHIP_ID) ||
1805 (CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
1806 (CHIPID(sih->chip) == BCM4330_CHIP_ID) ||
1807 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
1808 (CHIPID(sih->chip) == BCM43236_CHIP_ID))) {
1811 switch (CHIPID(sih->chip)) {
1812 case BCM5356_CHIP_ID:
1813 pll = PMU5356_MAINPLL_PLL0;
1815 case BCM5357_CHIP_ID:
1816 pll = PMU5357_MAINPLL_PLL0;
1819 pll = PMU4716_MAINPLL_PLL0;
1823 /* Remember original core before switch to chipc */
1824 origidx = si_coreidx(sih);
1825 cc = si_setcoreidx(sih, SI_CC_IDX);
1828 clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_MEM);
1830 /* Return to original core */
1831 si_setcoreidx(sih, origidx);
1833 clock = si_pmu_si_clock(sih, osh);
1839 /* Measure ILP clock frequency */
1840 #define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */
1842 static u32 ilpcycles_per_sec;
1844 u32 si_pmu_ilp_clock(si_t *sih, osl_t *osh)
1846 if (ISSIM_ENAB(sih))
1849 if (ilpcycles_per_sec == 0) {
1850 u32 start, end, delta;
1851 u32 origidx = si_coreidx(sih);
1852 chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
1854 start = R_REG(osh, &cc->pmutimer);
1855 mdelay(ILP_CALC_DUR);
1856 end = R_REG(osh, &cc->pmutimer);
1857 delta = end - start;
1858 ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
1859 si_setcoreidx(sih, origidx);
1862 return ilpcycles_per_sec;
1865 /* SDIO Pad drive strength to select value mappings */
1867 u8 strength; /* Pad Drive Strength in mA */
1868 u8 sel; /* Chip-specific select value */
1869 } sdiod_drive_str_t;
1871 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
1872 static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = {
1880 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
1881 static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = {
1892 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
1893 static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = {
1905 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
1908 si_sdiod_drive_strength_init(si_t *sih, osl_t *osh,
1909 u32 drivestrength) {
1911 uint origidx, intr_val = 0;
1912 sdiod_drive_str_t *str_tab = NULL;
1919 if (!(sih->cccaps & CC_CAP_PMU)) {
1923 /* Remember original core before switch to chipc */
1924 cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
1927 switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) {
1928 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
1929 str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1;
1930 str_mask = 0x30000000;
1933 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
1934 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
1935 str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2;
1936 str_mask = 0x00003800;
1939 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
1940 str_tab = (sdiod_drive_str_t *) &sdiod_drive_strength_tab3;
1941 str_mask = 0x00003800;
1946 PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev));
1951 if (str_tab != NULL) {
1952 u32 drivestrength_sel = 0;
1956 for (i = 0; str_tab[i].strength != 0; i++) {
1957 if (drivestrength >= str_tab[i].strength) {
1958 drivestrength_sel = str_tab[i].sel;
1963 W_REG(osh, &cc->chipcontrol_addr, 1);
1964 cc_data_temp = R_REG(osh, &cc->chipcontrol_data);
1965 cc_data_temp &= ~str_mask;
1966 drivestrength_sel <<= str_shift;
1967 cc_data_temp |= drivestrength_sel;
1968 W_REG(osh, &cc->chipcontrol_data, cc_data_temp);
1970 PMU_MSG(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
1971 drivestrength, cc_data_temp));
1974 /* Return to original core */
1975 si_restore_core(sih, origidx, intr_val);
1978 /* initialize PMU */
1979 void si_pmu_init(si_t *sih, osl_t *osh)
1984 ASSERT(sih->cccaps & CC_CAP_PMU);
1986 /* Remember original core before switch to chipc */
1987 origidx = si_coreidx(sih);
1988 cc = si_setcoreidx(sih, SI_CC_IDX);
1991 if (sih->pmurev == 1)
1992 AND_REG(osh, &cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
1993 else if (sih->pmurev >= 2)
1994 OR_REG(osh, &cc->pmucontrol, PCTL_NOILP_ON_WAIT);
1996 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
1997 /* Fix for 4329b0 bad LPOM state. */
1998 W_REG(osh, &cc->regcontrol_addr, 2);
1999 OR_REG(osh, &cc->regcontrol_data, 0x100);
2001 W_REG(osh, &cc->regcontrol_addr, 3);
2002 OR_REG(osh, &cc->regcontrol_data, 0x4);
2005 /* Return to original core */
2006 si_setcoreidx(sih, origidx);
2009 /* Return up time in ILP cycles for the given resource. */
2011 si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
2014 uint up, i, dup, dmax;
2015 u32 min_mask = 0, max_mask = 0;
2017 /* uptime of resource 'rsrc' */
2018 W_REG(osh, &cc->res_table_sel, rsrc);
2019 up = (R_REG(osh, &cc->res_updn_timer) >> 8) & 0xff;
2021 /* direct dependancies of resource 'rsrc' */
2022 deps = si_pmu_res_deps(sih, osh, cc, PMURES_BIT(rsrc), false);
2023 for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2024 if (!(deps & PMURES_BIT(i)))
2026 deps &= ~si_pmu_res_deps(sih, osh, cc, PMURES_BIT(i), true);
2028 si_pmu_res_masks(sih, &min_mask, &max_mask);
2031 /* max uptime of direct dependancies */
2033 for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2034 if (!(deps & PMURES_BIT(i)))
2036 dup = si_pmu_res_uptime(sih, osh, cc, (u8) i);
2041 PMU_MSG(("si_pmu_res_uptime: rsrc %u uptime %u(deps 0x%08x uptime %u)\n", rsrc, up, deps, dmax));
2043 return up + dmax + PMURES_UP_TRANSITION;
2046 /* Return dependancies (direct or all/indirect) for the given resources */
2048 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 rsrcs,
2054 for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2055 if (!(rsrcs & PMURES_BIT(i)))
2057 W_REG(osh, &cc->res_table_sel, i);
2058 deps |= R_REG(osh, &cc->res_dep_mask);
2061 return !all ? deps : (deps
2063 si_pmu_res_deps(sih, osh, cc, deps,
2067 /* power up/down OTP through PMU resources */
2068 void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on)
2072 u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
2074 ASSERT(sih->cccaps & CC_CAP_PMU);
2076 /* Don't do anything if OTP is disabled */
2077 if (si_is_otp_disabled(sih)) {
2078 PMU_MSG(("si_pmu_otp_power: OTP is disabled\n"));
2082 /* Remember original core before switch to chipc */
2083 origidx = si_coreidx(sih);
2084 cc = si_setcoreidx(sih, SI_CC_IDX);
2087 switch (CHIPID(sih->chip)) {
2088 case BCM4329_CHIP_ID:
2089 rsrcs = PMURES_BIT(RES4329_OTP_PU);
2091 case BCM4319_CHIP_ID:
2092 rsrcs = PMURES_BIT(RES4319_OTP_PU);
2094 case BCM4336_CHIP_ID:
2095 rsrcs = PMURES_BIT(RES4336_OTP_PU);
2097 case BCM4330_CHIP_ID:
2098 rsrcs = PMURES_BIT(RES4330_OTP_PU);
2107 /* Figure out the dependancies (exclude min_res_mask) */
2108 u32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, true);
2109 u32 min_mask = 0, max_mask = 0;
2110 si_pmu_res_masks(sih, &min_mask, &max_mask);
2112 /* Turn on/off the power */
2114 PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n",
2116 OR_REG(osh, &cc->min_res_mask, (rsrcs | deps));
2117 SPINWAIT(!(R_REG(osh, &cc->res_state) & rsrcs),
2118 PMU_MAX_TRANSITION_DLY);
2119 ASSERT(R_REG(osh, &cc->res_state) & rsrcs);
2121 PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n",
2123 AND_REG(osh, &cc->min_res_mask, ~(rsrcs | deps));
2126 SPINWAIT((((otps = R_REG(osh, &cc->otpstatus)) & OTPS_READY) !=
2127 (on ? OTPS_READY : 0)), 100);
2128 ASSERT((otps & OTPS_READY) == (on ? OTPS_READY : 0));
2129 if ((otps & OTPS_READY) != (on ? OTPS_READY : 0))
2130 PMU_MSG(("OTP ready bit not %s after wait\n",
2131 (on ? "ON" : "OFF")));
2134 /* Return to original core */
2135 si_setcoreidx(sih, origidx);
2138 void si_pmu_rcal(si_t *sih, osl_t *osh)
2143 ASSERT(sih->cccaps & CC_CAP_PMU);
2145 /* Remember original core before switch to chipc */
2146 origidx = si_coreidx(sih);
2147 cc = si_setcoreidx(sih, SI_CC_IDX);
2150 switch (CHIPID(sih->chip)) {
2151 case BCM4329_CHIP_ID:{
2156 W_REG(osh, &cc->chipcontrol_addr, 1);
2158 /* Power Down RCAL Block */
2159 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
2161 /* Power Up RCAL block */
2162 OR_REG(osh, &cc->chipcontrol_data, 0x04);
2164 /* Wait for completion */
2165 SPINWAIT(0 == (R_REG(osh, &cc->chipstatus) & 0x08),
2167 ASSERT(R_REG(osh, &cc->chipstatus) & 0x08);
2169 /* Drop the LSB to convert from 5 bit code to 4 bit code */
2171 (u8) (R_REG(osh, &cc->chipstatus) >> 5) & 0x0f;
2173 PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n",
2174 R_REG(osh, &cc->chipstatus), rcal_code));
2176 /* Write RCal code into pmu_vreg_ctrl[32:29] */
2177 W_REG(osh, &cc->regcontrol_addr, 0);
2181 regcontrol_data) & ~((u32) 0x07 << 29);
2182 val |= (u32) (rcal_code & 0x07) << 29;
2183 W_REG(osh, &cc->regcontrol_data, val);
2184 W_REG(osh, &cc->regcontrol_addr, 1);
2185 val = R_REG(osh, &cc->regcontrol_data) & ~(u32) 0x01;
2186 val |= (u32) ((rcal_code >> 3) & 0x01);
2187 W_REG(osh, &cc->regcontrol_data, val);
2189 /* Write RCal code into pmu_chip_ctrl[33:30] */
2190 W_REG(osh, &cc->chipcontrol_addr, 0);
2194 chipcontrol_data) & ~((u32) 0x03 << 30);
2195 val |= (u32) (rcal_code & 0x03) << 30;
2196 W_REG(osh, &cc->chipcontrol_data, val);
2197 W_REG(osh, &cc->chipcontrol_addr, 1);
2199 R_REG(osh, &cc->chipcontrol_data) & ~(u32) 0x03;
2200 val |= (u32) ((rcal_code >> 2) & 0x03);
2201 W_REG(osh, &cc->chipcontrol_data, val);
2203 /* Set override in pmu_chip_ctrl[29] */
2204 W_REG(osh, &cc->chipcontrol_addr, 0);
2205 OR_REG(osh, &cc->chipcontrol_data, (0x01 << 29));
2207 /* Power off RCal block */
2208 W_REG(osh, &cc->chipcontrol_addr, 1);
2209 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
2217 /* Return to original core */
2218 si_setcoreidx(sih, origidx);
2221 void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid)
2224 uint origidx, intr_val;
2227 /* Remember original core before switch to chipc */
2228 cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
2232 /* force the HT off */
2233 if (CHIPID(sih->chip) == BCM4336_CHIP_ID) {
2234 tmp = R_REG(osh, &cc->max_res_mask);
2235 tmp &= ~RES4336_HT_AVAIL;
2236 W_REG(osh, &cc->max_res_mask, tmp);
2237 /* wait for the ht to really go away */
2238 SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0),
2240 ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0);
2243 /* update the pll changes */
2244 si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
2246 /* enable HT back on */
2247 if (CHIPID(sih->chip) == BCM4336_CHIP_ID) {
2248 tmp = R_REG(osh, &cc->max_res_mask);
2249 tmp |= RES4336_HT_AVAIL;
2250 W_REG(osh, &cc->max_res_mask, tmp);
2253 /* Return to original core */
2254 si_restore_core(sih, origidx, intr_val);
2258 si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh,
2262 u8 phypll_offset = 0;
2263 u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
2264 u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
2266 switch (CHIPID(sih->chip)) {
2267 case BCM5357_CHIP_ID:
2268 case BCM43235_CHIP_ID:
2269 case BCM43236_CHIP_ID:
2270 case BCM43238_CHIP_ID:
2272 /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */
2273 phypll_offset = (CHIPID(sih->chip) == BCM5357_CHIP_ID) ? 6 : 0;
2275 /* RMW only the P1 divider */
2276 W_REG(osh, &cc->pllcontrol_addr,
2277 PMU1_PLL0_PLLCTL0 + phypll_offset);
2278 tmp = R_REG(osh, &cc->pllcontrol_data);
2279 tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK));
2281 (bcm5357_bcm43236_p1div[spuravoid] <<
2282 PMU1_PLL0_PC0_P1DIV_SHIFT);
2283 W_REG(osh, &cc->pllcontrol_data, tmp);
2285 /* RMW only the int feedback divider */
2286 W_REG(osh, &cc->pllcontrol_addr,
2287 PMU1_PLL0_PLLCTL2 + phypll_offset);
2288 tmp = R_REG(osh, &cc->pllcontrol_data);
2289 tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK);
2291 (bcm5357_bcm43236_ndiv[spuravoid]) <<
2292 PMU1_PLL0_PC2_NDIV_INT_SHIFT;
2293 W_REG(osh, &cc->pllcontrol_data, tmp);
2298 case BCM4331_CHIP_ID:
2299 if (spuravoid == 2) {
2300 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2301 W_REG(osh, &cc->pllcontrol_data, 0x11500014);
2302 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2303 W_REG(osh, &cc->pllcontrol_data, 0x0FC00a08);
2304 } else if (spuravoid == 1) {
2305 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2306 W_REG(osh, &cc->pllcontrol_data, 0x11500014);
2307 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2308 W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
2310 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2311 W_REG(osh, &cc->pllcontrol_data, 0x11100014);
2312 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2313 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2318 case BCM43224_CHIP_ID:
2319 case BCM43225_CHIP_ID:
2320 case BCM43421_CHIP_ID:
2321 case BCM6362_CHIP_ID:
2322 if (spuravoid == 1) {
2323 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2324 W_REG(osh, &cc->pllcontrol_data, 0x11500010);
2325 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2326 W_REG(osh, &cc->pllcontrol_data, 0x000C0C06);
2327 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2328 W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
2329 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2330 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2331 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2332 W_REG(osh, &cc->pllcontrol_data, 0x2001E920);
2333 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2334 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2336 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2337 W_REG(osh, &cc->pllcontrol_data, 0x11100010);
2338 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2339 W_REG(osh, &cc->pllcontrol_data, 0x000c0c06);
2340 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2341 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2342 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2343 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2344 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2345 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2346 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2347 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2352 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2353 W_REG(osh, &cc->pllcontrol_data, 0x11100008);
2354 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2355 W_REG(osh, &cc->pllcontrol_data, 0x0c000c06);
2356 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2357 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2358 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2359 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2360 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2361 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2362 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2363 W_REG(osh, &cc->pllcontrol_data, 0x88888855);
2368 case BCM4716_CHIP_ID:
2369 case BCM4748_CHIP_ID:
2370 case BCM47162_CHIP_ID:
2371 if (spuravoid == 1) {
2372 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2373 W_REG(osh, &cc->pllcontrol_data, 0x11500060);
2374 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2375 W_REG(osh, &cc->pllcontrol_data, 0x080C0C06);
2376 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2377 W_REG(osh, &cc->pllcontrol_data, 0x0F600000);
2378 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2379 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2380 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2381 W_REG(osh, &cc->pllcontrol_data, 0x2001E924);
2382 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2383 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2385 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2386 W_REG(osh, &cc->pllcontrol_data, 0x11100060);
2387 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2388 W_REG(osh, &cc->pllcontrol_data, 0x080c0c06);
2389 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2390 W_REG(osh, &cc->pllcontrol_data, 0x03000000);
2391 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2392 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2393 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2394 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2395 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2396 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2402 case BCM4319_CHIP_ID:
2403 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2404 W_REG(osh, &cc->pllcontrol_data, 0x11100070);
2405 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2406 W_REG(osh, &cc->pllcontrol_data, 0x1014140a);
2407 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2408 W_REG(osh, &cc->pllcontrol_data, 0x88888854);
2410 if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */
2411 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2412 W_REG(osh, &cc->pllcontrol_data, 0x05201828);
2413 } else { /* enable 40/80/160Mhz clock mode */
2414 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2415 W_REG(osh, &cc->pllcontrol_data, 0x05001828);
2418 case BCM4336_CHIP_ID:
2419 /* Looks like these are only for default xtal freq 26MHz */
2420 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2421 W_REG(osh, &cc->pllcontrol_data, 0x02100020);
2423 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2424 W_REG(osh, &cc->pllcontrol_data, 0x0C0C0C0C);
2426 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2427 W_REG(osh, &cc->pllcontrol_data, 0x01240C0C);
2429 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2430 W_REG(osh, &cc->pllcontrol_data, 0x202C2820);
2432 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2433 W_REG(osh, &cc->pllcontrol_data, 0x88888825);
2435 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2436 if (spuravoid == 1) {
2437 W_REG(osh, &cc->pllcontrol_data, 0x00EC4EC4);
2439 W_REG(osh, &cc->pllcontrol_data, 0x00762762);
2442 tmp = PCTL_PLL_PLLCTL_UPD;
2446 PMU_ERROR(("%s: unknown spuravoidance settings for chip %s, not changing PLL\n", __func__, bcm_chipname(sih->chip, chn, 8)));
2450 tmp |= R_REG(osh, &cc->pmucontrol);
2451 W_REG(osh, &cc->pmucontrol, tmp);
2454 bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh)
2460 /* Remember original core before switch to chipc */
2461 idx = si_coreidx(sih);
2462 cc = si_setcoreidx(sih, SI_CC_IDX);
2465 switch (CHIPID(sih->chip)) {
2466 case BCM4329_CHIP_ID:
2467 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4329_OTP_PU))
2470 case BCM4319_CHIP_ID:
2471 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4319_OTP_PU))
2474 case BCM4336_CHIP_ID:
2475 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4336_OTP_PU))
2478 case BCM4330_CHIP_ID:
2479 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4330_OTP_PU))
2483 /* These chip doesn't use PMU bit to power up/down OTP. OTP always on.
2484 * Use OTP_INIT command to reset/refresh state.
2486 case BCM43224_CHIP_ID:
2487 case BCM43225_CHIP_ID:
2488 case BCM43421_CHIP_ID:
2489 case BCM43236_CHIP_ID:
2490 case BCM43235_CHIP_ID:
2491 case BCM43238_CHIP_ID:
2499 /* Return to original core */
2500 si_setcoreidx(sih, idx);
2506 si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
2508 si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
2514 /* Remember original core before switch to chipc */
2515 origidx = si_coreidx(sih);
2516 cc = si_setcoreidx(sih, SI_CC_IDX);
2519 /* Return to original core */
2520 si_setcoreidx(sih, origidx);
2523 /* initialize PMU chip controls and other chip level stuff */
2524 void si_pmu_chip_init(si_t *sih, osl_t *osh)
2528 ASSERT(sih->cccaps & CC_CAP_PMU);
2530 #ifdef CHIPC_UART_ALWAYS_ON
2531 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, clk_ctl_st),
2532 CCS_FORCEALP, CCS_FORCEALP);
2533 #endif /* CHIPC_UART_ALWAYS_ON */
2535 /* Gate off SPROM clock and chip select signals */
2536 si_pmu_sprom_enable(sih, osh, false);
2538 /* Remember original core */
2539 origidx = si_coreidx(sih);
2541 /* Return to original core */
2542 si_setcoreidx(sih, origidx);
2545 /* initialize PMU switch/regulators */
2546 void si_pmu_swreg_init(si_t *sih, osl_t *osh)
2548 ASSERT(sih->cccaps & CC_CAP_PMU);
2550 switch (CHIPID(sih->chip)) {
2551 case BCM4336_CHIP_ID:
2552 /* Reduce CLDO PWM output voltage to 1.2V */
2553 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
2554 /* Reduce CLDO BURST output voltage to 1.2V */
2555 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST,
2557 /* Reduce LNLDO1 output voltage to 1.2V */
2558 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe);
2559 if (CHIPREV(sih->chiprev) == 0)
2560 si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
2563 case BCM4330_CHIP_ID:
2564 /* CBUCK Voltage is 1.8 by default and set that to 1.5 */
2565 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
2572 void si_pmu_radio_enable(si_t *sih, bool enable)
2574 ASSERT(sih->cccaps & CC_CAP_PMU);
2576 switch (CHIPID(sih->chip)) {
2577 case BCM4319_CHIP_ID:
2579 si_write_wrapperreg(sih, AI_OOBSELOUTB74,
2582 si_write_wrapperreg(sih, AI_OOBSELOUTB74,
2588 /* Wait for a particular clock level to be on the backplane */
2590 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, u32 clk,
2596 ASSERT(sih->cccaps & CC_CAP_PMU);
2598 /* Remember original core before switch to chipc */
2599 origidx = si_coreidx(sih);
2600 cc = si_setcoreidx(sih, SI_CC_IDX);
2604 SPINWAIT(((R_REG(osh, &cc->pmustatus) & clk) != clk), delay);
2606 /* Return to original core */
2607 si_setcoreidx(sih, origidx);
2609 return R_REG(osh, &cc->pmustatus) & clk;
2613 * Measures the ALP clock frequency in KHz. Returns 0 if not possible.
2614 * Possible only if PMU rev >= 10 and there is an external LPO 32768Hz crystal.
2617 #define EXT_ILP_HZ 32768
2619 u32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh)
2625 if (sih->pmurev < 10)
2628 ASSERT(sih->cccaps & CC_CAP_PMU);
2630 /* Remember original core before switch to chipc */
2631 origidx = si_coreidx(sih);
2632 cc = si_setcoreidx(sih, SI_CC_IDX);
2635 if (R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL) {
2636 u32 ilp_ctr, alp_hz;
2638 /* Enable the reg to measure the freq, in case disabled before */
2639 W_REG(osh, &cc->pmu_xtalfreq,
2640 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
2642 /* Delay for well over 4 ILP clocks */
2645 /* Read the latched number of ALP ticks per 4 ILP ticks */
2648 &cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
2650 /* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT bit to save power */
2651 W_REG(osh, &cc->pmu_xtalfreq, 0);
2653 /* Calculate ALP frequency */
2654 alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
2656 /* Round to nearest 100KHz, and at the same time convert to KHz */
2657 alp_khz = (alp_hz + 50000) / 100000 * 100;
2661 /* Return to original core */
2662 si_setcoreidx(sih, origidx);
2667 static void si_pmu_set_4330_plldivs(si_t *sih)
2669 u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
2670 u32 m1div, m2div, m3div, m4div, m5div, m6div;
2673 m2div = m3div = m4div = m6div = FVCO / 80;
2676 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
2681 (m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div <<
2682 PMU1_PLL0_PC1_M2DIV_SHIFT) |
2683 (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div <<
2684 PMU1_PLL0_PC1_M4DIV_SHIFT);
2685 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1);
2687 pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
2688 pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK);
2690 ((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) |
2691 (m6div << PMU1_PLL0_PC2_M6DIV_SHIFT));
2692 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2);