2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #ifdef SI_ENUM_BASE_VARIABLE
21 #define SI_ENUM_BASE (sii->pub.si_enum_base)
23 #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
24 #endif /* SI_ENUM_BASE_VARIABLE */
27 #define NODEV_CORE_ID 0x700 /* Invalid coreid */
28 #define CC_CORE_ID 0x800 /* chipcommon core */
29 #define ILINE20_CORE_ID 0x801 /* iline20 core */
30 #define SRAM_CORE_ID 0x802 /* sram core */
31 #define SDRAM_CORE_ID 0x803 /* sdram core */
32 #define PCI_CORE_ID 0x804 /* pci core */
33 #define MIPS_CORE_ID 0x805 /* mips core */
34 #define ENET_CORE_ID 0x806 /* enet mac core */
35 #define CODEC_CORE_ID 0x807 /* v90 codec core */
36 #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
37 #define ADSL_CORE_ID 0x809 /* ADSL core */
38 #define ILINE100_CORE_ID 0x80a /* iline100 core */
39 #define IPSEC_CORE_ID 0x80b /* ipsec core */
40 #define UTOPIA_CORE_ID 0x80c /* utopia core */
41 #define PCMCIA_CORE_ID 0x80d /* pcmcia core */
42 #define SOCRAM_CORE_ID 0x80e /* internal memory core */
43 #define MEMC_CORE_ID 0x80f /* memc sdram core */
44 #define OFDM_CORE_ID 0x810 /* OFDM phy core */
45 #define EXTIF_CORE_ID 0x811 /* external interface core */
46 #define D11_CORE_ID 0x812 /* 802.11 MAC core */
47 #define APHY_CORE_ID 0x813 /* 802.11a phy core */
48 #define BPHY_CORE_ID 0x814 /* 802.11b phy core */
49 #define GPHY_CORE_ID 0x815 /* 802.11g phy core */
50 #define MIPS33_CORE_ID 0x816 /* mips3302 core */
51 #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
52 #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
53 #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
54 #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
55 #define SDIOH_CORE_ID 0x81b /* sdio host core */
56 #define ROBO_CORE_ID 0x81c /* roboswitch core */
57 #define ATA100_CORE_ID 0x81d /* parallel ATA core */
58 #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
59 #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
60 #define PCIE_CORE_ID 0x820 /* pci express core */
61 #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
62 #define SRAMC_CORE_ID 0x822 /* SRAM controller core */
63 #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
64 #define ARM11_CORE_ID 0x824 /* ARM 1176 core */
65 #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
66 #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
67 #define PMU_CORE_ID 0x827 /* PMU core */
68 #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
69 #define SDIOD_CORE_ID 0x829 /* SDIO device core */
70 #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
71 #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
72 #define MIPS74K_CORE_ID 0x82c /* mips 74k core */
73 #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
74 #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
75 #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
76 #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
77 #define SC_CORE_ID 0x831 /* shared common core */
78 #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
79 #define SPIH_CORE_ID 0x833 /* SPI host core */
80 #define I2S_CORE_ID 0x834 /* I2S core */
81 #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
82 #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
83 #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
84 #define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
85 * unused address ranges
88 /* Common core control flags */
89 #define SICF_BIST_EN 0x8000
90 #define SICF_PME_EN 0x4000
91 #define SICF_CORE_BITS 0x3ffc
92 #define SICF_FGC 0x0002
93 #define SICF_CLOCK_EN 0x0001
95 #endif /* _BRCM_SOC_H */