2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
23 #include BCMEMBEDIMAGE
24 #endif /* BCMEMBEDIMAGE */
28 #include <bcmendian.h>
35 #include <hndrte_armtrap.h>
36 #include <hndrte_cons.h>
37 #endif /* DHD_DEBUG */
43 #include <sbsdpcmdev.h>
46 #include <proto/ethernet.h>
47 #include <proto/802.1d.h>
48 #include <proto/802.11.h>
50 #include <dngl_stats.h>
53 #include <dhd_proto.h>
57 #include <siutils_priv.h>
59 #ifndef DHDSDIO_MEM_DUMP_FNAME
60 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
63 #define QLEN 256 /* bulk rx and tx queue lengths */
64 #define FCHI (QLEN - 10)
65 #define FCLOW (FCHI / 2)
68 #define TXRETRIES 2 /* # of retries for tx frames */
70 #if defined(CONFIG_MACH_SANDGATE2G)
71 #define DHD_RXBOUND 250 /* Default for max rx frames in
74 #define DHD_RXBOUND 50 /* Default for max rx frames in
76 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
78 #define DHD_TXBOUND 20 /* Default for max tx frames in
81 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
83 #define MEMBLOCK 2048 /* Block size used for downloading
85 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
86 biggest possible glom */
88 /* Packet alignment for most efficient SDIO (can change based on platform) */
90 #define DHD_SDALIGN 32
92 #if !ISPOWEROF2(DHD_SDALIGN)
93 #error DHD_SDALIGN is not a power of 2!
97 #define DHD_FIRSTREAD 32
99 #if !ISPOWEROF2(DHD_FIRSTREAD)
100 #error DHD_FIRSTREAD is not a power of 2!
103 /* Total length of frame header for dongle protocol */
104 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
106 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
108 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
111 /* Space for header read, limit for data packets */
113 #define MAX_HDR_READ 32
115 #if !ISPOWEROF2(MAX_HDR_READ)
116 #error MAX_HDR_READ is not a power of 2!
119 #define MAX_RX_DATASZ 2048
121 /* Maximum milliseconds to wait for F2 to come up */
122 #define DHD_WAIT_F2RDY 3000
124 /* Bump up limit on waiting for HT to account for first startup;
125 * if the image is doing a CRC calculation before programming the PMU
126 * for HT availability, it could take a couple hundred ms more, so
127 * max out at a 1 second (1000000us).
129 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
130 #undef PMU_MAX_TRANSITION_DLY
131 #define PMU_MAX_TRANSITION_DLY 1000000
134 /* Value for ChipClockCSR during initial setup */
135 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
136 SBSDIO_ALP_AVAIL_REQ)
137 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
139 /* Flags for SDH calls */
140 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
142 /* Packet free applicable unconditionally for sdio and sdspi. Conditional if
143 * bufpool was present for gspi bus.
145 #define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
146 PKTFREE(bus->dhd->osh, pkt, false);
147 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
148 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
152 /* Device console log buffer state */
153 typedef struct dhd_console {
154 uint count; /* Poll interval msec counter */
155 uint log_addr; /* Log struct address (fixed) */
156 hndrte_log_t log; /* Log struct (host copy) */
157 uint bufsize; /* Size of log buffer */
158 u8 *buf; /* Log buffer (host copy) */
159 uint last; /* Last buffer read index */
161 #endif /* DHD_DEBUG */
163 /* Private data for SDIO bus interaction */
164 typedef struct dhd_bus {
167 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
168 si_t *sih; /* Handle for SI calls */
169 char *vars; /* Variables (from CIS and/or other) */
170 uint varsz; /* Size of variables buffer */
171 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
173 sdpcmd_regs_t *regs; /* Registers for SDIO core */
174 uint sdpcmrev; /* SDIO core revision */
175 uint armrev; /* CPU core revision */
176 uint ramrev; /* SOCRAM core revision */
177 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
178 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
180 u32 bus; /* gSPI or SDIO bus */
181 u32 hostintmask; /* Copy of Host Interrupt Mask */
182 u32 intstatus; /* Intstatus bits (events) pending */
183 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
184 bool fcstate; /* State of dongle flow-control */
186 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
187 char *fw_path; /* module_param: path to firmware image */
188 char *nv_path; /* module_param: path to nvram vars file */
189 const char *nvram_params; /* user specified nvram params. */
191 uint blocksize; /* Block size of SDIO transfers */
192 uint roundup; /* Max roundup limit */
194 struct pktq txq; /* Queue length used for flow-control */
195 u8 flowcontrol; /* per prio flow control bitmask */
196 u8 tx_seq; /* Transmit sequence number (next) */
197 u8 tx_max; /* Maximum transmit sequence allowed */
199 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
200 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
201 u16 nextlen; /* Next Read Len from last header */
202 u8 rx_seq; /* Receive sequence number (expected) */
203 bool rxskip; /* Skip receive (awaiting NAK ACK) */
205 void *glomd; /* Packet containing glomming descriptor */
206 void *glom; /* Packet chain for glommed superframe */
207 uint glomerr; /* Glom packet read errors */
209 u8 *rxbuf; /* Buffer for receiving control packets */
210 uint rxblen; /* Allocated length of rxbuf */
211 u8 *rxctl; /* Aligned pointer into rxbuf */
212 u8 *databuf; /* Buffer for receiving big glom packet */
213 u8 *dataptr; /* Aligned pointer into databuf */
214 uint rxlen; /* Length of valid data in buffer */
216 u8 sdpcm_ver; /* Bus protocol reported by dongle */
218 bool intr; /* Use interrupts */
219 bool poll; /* Use polling */
220 bool ipend; /* Device interrupt is pending */
221 bool intdis; /* Interrupts disabled by isr */
222 uint intrcount; /* Count of device interrupt callbacks */
223 uint lastintrs; /* Count as of last watchdog timer */
224 uint spurious; /* Count of spurious interrupts */
225 uint pollrate; /* Ticks between device polls */
226 uint polltick; /* Tick counter */
227 uint pollcnt; /* Count of active polls */
230 dhd_console_t console; /* Console output polling support */
231 uint console_addr; /* Console address from shared struct */
232 #endif /* DHD_DEBUG */
234 uint regfails; /* Count of R_REG/W_REG failures */
236 uint clkstate; /* State of sd and backplane clock(s) */
237 bool activity; /* Activity flag for clock down */
238 s32 idletime; /* Control for activity timeout */
239 s32 idlecount; /* Activity timeout counter */
240 s32 idleclock; /* How to set bus driver when idle */
241 s32 sd_divisor; /* Speed control to bus driver */
242 s32 sd_mode; /* Mode control to bus driver */
243 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
244 bool use_rxchain; /* If dhd should use PKT chains */
245 bool sleeping; /* Is SDIO bus sleeping? */
246 bool rxflow_mode; /* Rx flow control mode */
247 bool rxflow; /* Is rx flow control on */
248 uint prev_rxlim_hit; /* Is prev rx limit exceeded
249 (per dpc schedule) */
250 bool alp_only; /* Don't use HT clock (ALP only) */
251 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
255 /* external loopback */
259 /* pktgen configuration */
260 uint pktgen_freq; /* Ticks between bursts */
261 uint pktgen_count; /* Packets to send each burst */
262 uint pktgen_print; /* Bursts between count displays */
263 uint pktgen_total; /* Stop after this many */
264 uint pktgen_minlen; /* Minimum packet data len */
265 uint pktgen_maxlen; /* Maximum packet data len */
266 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
267 uint pktgen_stop; /* Number of tx failures causing stop */
269 /* active pktgen fields */
270 uint pktgen_tick; /* Tick counter for bursts */
271 uint pktgen_ptick; /* Burst counter for printing */
272 uint pktgen_sent; /* Number of test packets generated */
273 uint pktgen_rcvd; /* Number of test packets received */
274 uint pktgen_fail; /* Number of failed send attempts */
275 u16 pktgen_len; /* Length of next packet to send */
278 /* Some additional counters */
279 uint tx_sderrs; /* Count of tx attempts with sd errors */
280 uint fcqueued; /* Tx packets that got queued */
281 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
282 uint rx_toolong; /* Receive frames too long to receive */
283 uint rxc_errors; /* SDIO errors when reading control frames */
284 uint rx_hdrfail; /* SDIO errors on header reads */
285 uint rx_badhdr; /* Bad received headers (roosync?) */
286 uint rx_badseq; /* Mismatched rx sequence number */
287 uint fc_rcvd; /* Number of flow-control events received */
288 uint fc_xoff; /* Number which turned on flow-control */
289 uint fc_xon; /* Number which turned off flow-control */
290 uint rxglomfail; /* Failed deglom attempts */
291 uint rxglomframes; /* Number of glom frames (superframes) */
292 uint rxglompkts; /* Number of packets from glom frames */
293 uint f2rxhdrs; /* Number of header reads */
294 uint f2rxdata; /* Number of frame data reads */
295 uint f2txdata; /* Number of f2 frame writes */
296 uint f1regdata; /* Number of f1 register accesses */
300 bool ctrl_frame_stat;
306 #define CLK_PENDING 2 /* Not used yet */
309 #define DHD_NOPMU(dhd) (false)
312 static int qcount[NUMPRIO];
313 static int tx_packets[NUMPRIO];
314 #endif /* DHD_DEBUG */
316 /* Deferred transmit */
317 const uint dhd_deferred_tx = 1;
319 extern uint dhd_watchdog_ms;
320 extern void dhd_os_wd_timer(void *bus, uint wdtick);
327 /* override the RAM size if possible */
328 #define DONGLE_MIN_MEMSIZE (128 * 1024)
329 int dhd_dongle_memsize;
331 static bool dhd_doflow;
332 static bool dhd_alignctl;
336 static bool retrydata;
337 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
339 static const uint watermark = 8;
340 static const uint firstread = DHD_FIRSTREAD;
342 #define HDATLEN (firstread - (SDPCM_HDRLEN))
344 /* Retry count for register access failures */
345 static const uint retry_limit = 2;
347 /* Force even SD lengths (some host controllers mess up on odd bytes) */
348 static bool forcealign;
352 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
353 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
356 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
357 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
358 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
359 #define PKTALIGN(osh, p, len, align) \
362 datalign = (unsigned long)PKTDATA((p)); \
363 datalign = roundup(datalign, (align)) - datalign; \
364 ASSERT(datalign < (align)); \
365 ASSERT(PKTLEN((p)) >= ((len) + datalign)); \
367 PKTPULL((p), datalign); \
368 PKTSETLEN((p), (len)); \
371 /* Limit on rounding up frames */
372 static const uint max_roundup = 512;
374 /* Try doing readahead */
375 static bool dhd_readahead;
377 /* To check if there's window offered */
378 #define DATAOK(bus) \
379 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
380 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
382 /* Macros to get register read/write status */
383 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
384 #define R_SDREG(regvar, regaddr, retryvar) \
388 regvar = R_REG(bus->dhd->osh, regaddr); \
389 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
391 bus->regfails += (retryvar-1); \
392 if (retryvar > retry_limit) { \
393 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
394 __func__, __LINE__)); \
400 #define W_SDREG(regval, regaddr, retryvar) \
404 W_REG(bus->dhd->osh, regaddr, regval); \
405 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
407 bus->regfails += (retryvar-1); \
408 if (retryvar > retry_limit) \
409 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
410 __func__, __LINE__)); \
414 #define DHD_BUS SDIO_BUS
416 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
418 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
420 #define GSPI_PR55150_BAILOUT
423 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
424 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
428 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
429 static int dhdsdio_mem_dump(dhd_bus_t *bus);
430 #endif /* DHD_DEBUG */
431 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
433 static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh);
434 static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh);
435 static void dhdsdio_disconnect(void *ptr);
436 static bool dhdsdio_chipmatch(u16 chipid);
437 static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh,
438 void *regsva, u16 devid);
439 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh);
440 static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh);
441 static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh);
443 static uint process_nvram_vars(char *varbuf, uint len);
445 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
446 static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
447 uint flags, u8 *buf, uint nbytes, void *pkt,
448 bcmsdh_cmplt_fn_t complete, void *handle);
449 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
450 uint flags, u8 *buf, uint nbytes, void *pkt,
451 bcmsdh_cmplt_fn_t complete, void *handle);
453 static bool dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh,
455 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
457 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
458 static int dhdsdio_download_nvram(struct dhd_bus *bus);
460 static int dhdsdio_download_code_array(struct dhd_bus *bus);
463 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
465 s32 min_size = DONGLE_MIN_MEMSIZE;
466 /* Restrict the memsize to user specified limit */
467 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
468 dhd_dongle_memsize, min_size));
469 if ((dhd_dongle_memsize > min_size) &&
470 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
471 bus->ramsize = dhd_dongle_memsize;
474 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
477 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
478 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
480 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
481 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
483 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
484 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
489 /* Turn backplane clock on or off */
490 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
493 u8 clkctl, clkreq, devctl;
496 DHD_TRACE(("%s: Enter\n", __func__));
498 #if defined(OOB_INTR_ONLY)
505 /* Request HT Avail */
507 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
509 if ((bus->sih->chip == BCM4329_CHIP_ID)
510 && (bus->sih->chiprev == 0))
511 clkreq |= SBSDIO_FORCE_ALP;
513 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
516 DHD_ERROR(("%s: HT Avail request error: %d\n",
521 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
522 && (bus->sih->buscorerev == 9))) {
524 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
527 /* Check current status */
529 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
532 DHD_ERROR(("%s: HT Avail read error: %d\n",
537 /* Go to pending and await interrupt if appropriate */
538 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
539 /* Allow only clock-available interrupt */
541 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
544 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
549 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
550 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
552 DHD_INFO(("CLKCTL: set PENDING\n"));
553 bus->clkstate = CLK_PENDING;
556 } else if (bus->clkstate == CLK_PENDING) {
557 /* Cancel CA-only interrupt filter */
559 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
561 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
562 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
566 /* Otherwise, wait here (polling) for HT Avail */
567 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
568 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
570 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
571 SBSDIO_FUNC1_CHIPCLKCSR,
573 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
574 PMU_MAX_TRANSITION_DLY);
577 DHD_ERROR(("%s: HT Avail request error: %d\n",
581 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
582 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
583 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
587 /* Mark clock available */
588 bus->clkstate = CLK_AVAIL;
589 DHD_INFO(("CLKCTL: turned ON\n"));
591 #if defined(DHD_DEBUG)
592 if (bus->alp_only == true) {
593 #if !defined(BCMLXSDMMC)
594 if (!SBSDIO_ALPONLY(clkctl)) {
595 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
598 #endif /* !defined(BCMLXSDMMC) */
600 if (SBSDIO_ALPONLY(clkctl)) {
601 DHD_ERROR(("%s: HT Clock should be on.\n",
605 #endif /* defined (DHD_DEBUG) */
607 bus->activity = true;
611 if (bus->clkstate == CLK_PENDING) {
612 /* Cancel CA-only interrupt filter */
614 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
616 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
617 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
621 bus->clkstate = CLK_SDONLY;
622 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
624 DHD_INFO(("CLKCTL: turned OFF\n"));
626 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
634 /* Change idle/active SD state */
635 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
640 DHD_TRACE(("%s: Enter\n", __func__));
643 if (bus->idleclock == DHD_IDLE_STOP) {
644 /* Turn on clock and restore mode */
646 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
647 &iovalue, sizeof(iovalue), true);
649 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
654 iovalue = bus->sd_mode;
655 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
656 &iovalue, sizeof(iovalue), true);
658 DHD_ERROR(("%s: error changing sd_mode: %d\n",
662 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
663 /* Restore clock speed */
664 iovalue = bus->sd_divisor;
665 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
666 &iovalue, sizeof(iovalue), true);
668 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
673 bus->clkstate = CLK_SDONLY;
675 /* Stop or slow the SD clock itself */
676 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
677 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
678 __func__, bus->sd_divisor, bus->sd_mode));
681 if (bus->idleclock == DHD_IDLE_STOP) {
683 /* Change to SD1 mode and turn off clock */
686 bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL,
688 sizeof(iovalue), true);
690 DHD_ERROR(("%s: error changing sd_clock: %d\n",
697 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
698 &iovalue, sizeof(iovalue), true);
700 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
704 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
705 /* Set divisor to idle value */
706 iovalue = bus->idleclock;
707 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
708 &iovalue, sizeof(iovalue), true);
710 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
715 bus->clkstate = CLK_NONE;
721 /* Transition SD and backplane clock readiness */
722 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
725 uint oldstate = bus->clkstate;
726 #endif /* DHD_DEBUG */
728 DHD_TRACE(("%s: Enter\n", __func__));
730 /* Early exit if we're already there */
731 if (bus->clkstate == target) {
732 if (target == CLK_AVAIL) {
733 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
734 bus->activity = true;
741 /* Make sure SD clock is available */
742 if (bus->clkstate == CLK_NONE)
743 dhdsdio_sdclk(bus, true);
744 /* Now request HT Avail on the backplane */
745 dhdsdio_htclk(bus, true, pendok);
746 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
747 bus->activity = true;
751 /* Remove HT request, or bring up SD clock */
752 if (bus->clkstate == CLK_NONE)
753 dhdsdio_sdclk(bus, true);
754 else if (bus->clkstate == CLK_AVAIL)
755 dhdsdio_htclk(bus, false, false);
757 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
758 bus->clkstate, target));
759 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
763 /* Make sure to remove HT request */
764 if (bus->clkstate == CLK_AVAIL)
765 dhdsdio_htclk(bus, false, false);
766 /* Now remove the SD clock */
767 dhdsdio_sdclk(bus, false);
768 dhd_os_wd_timer(bus->dhd, 0);
772 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
773 #endif /* DHD_DEBUG */
778 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
780 bcmsdh_info_t *sdh = bus->sdh;
781 sdpcmd_regs_t *regs = bus->regs;
784 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
785 (sleep ? "SLEEP" : "WAKE"),
786 (bus->sleeping ? "SLEEP" : "WAKE")));
788 /* Done if we're already in the requested state */
789 if (sleep == bus->sleeping)
792 /* Going to sleep: set the alarm and turn off the lights... */
794 /* Don't sleep if something is pending */
795 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
798 /* Disable SDIO interrupts (no longer interested) */
799 bcmsdh_intr_disable(bus->sdh);
801 /* Make sure the controller has the bus up */
802 dhdsdio_clkctl(bus, CLK_AVAIL, false);
804 /* Tell device to start using OOB wakeup */
805 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
806 if (retries > retry_limit)
807 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
809 /* Turn off our contribution to the HT clock request */
810 dhdsdio_clkctl(bus, CLK_SDONLY, false);
812 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
813 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
815 /* Isolate the bus */
816 if (bus->sih->chip != BCM4329_CHIP_ID
817 && bus->sih->chip != BCM4319_CHIP_ID) {
818 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
819 SBSDIO_DEVCTL_PADS_ISO, NULL);
823 bus->sleeping = true;
826 /* Waking up: bus power up is ok, set local state */
828 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
831 /* Force pad isolation off if possible
832 (in case power never toggled) */
833 if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
834 && (bus->sih->buscorerev >= 10))
835 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
838 /* Make sure the controller has the bus up */
839 dhdsdio_clkctl(bus, CLK_AVAIL, false);
841 /* Send misc interrupt to indicate OOB not needed */
842 W_SDREG(0, ®s->tosbmailboxdata, retries);
843 if (retries <= retry_limit)
844 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
846 if (retries > retry_limit)
847 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
849 /* Make sure we have SD bus access */
850 dhdsdio_clkctl(bus, CLK_SDONLY, false);
853 bus->sleeping = false;
855 /* Enable interrupts again */
856 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
858 bcmsdh_intr_enable(bus->sdh);
865 #if defined(OOB_INTR_ONLY)
866 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
869 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
871 sdpcmd_regs_t *regs = bus->regs;
874 dhdsdio_clkctl(bus, CLK_AVAIL, false);
875 if (enable == true) {
877 /* Tell device to start using OOB wakeup */
878 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
879 if (retries > retry_limit)
880 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
883 /* Send misc interrupt to indicate OOB not needed */
884 W_SDREG(0, ®s->tosbmailboxdata, retries);
885 if (retries <= retry_limit)
886 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
889 /* Turn off our contribution to the HT clock request */
890 dhdsdio_clkctl(bus, CLK_SDONLY, false);
891 #endif /* !defined(HW_OOB) */
893 #endif /* defined(OOB_INTR_ONLY) */
895 #define BUS_WAKE(bus) \
897 if ((bus)->sleeping) \
898 dhdsdio_bussleep((bus), false); \
901 /* Writes a HW/SW header into the packet and sends it. */
902 /* Assumes: (a) header space already there, (b) caller holds lock */
903 static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt)
915 DHD_TRACE(("%s: Enter\n", __func__));
920 if (bus->dhd->dongle_reset) {
925 frame = (u8 *) PKTDATA(pkt);
927 /* Add alignment padding, allocate new packet if needed */
928 pad = ((unsigned long)frame % DHD_SDALIGN);
930 if (PKTHEADROOM(pkt) < pad) {
931 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
932 __func__, (int)PKTHEADROOM(pkt), pad));
933 bus->dhd->tx_realloc++;
934 new = PKTGET(osh, (PKTLEN(pkt) + DHD_SDALIGN), true);
936 DHD_ERROR(("%s: couldn't allocate new %d-byte "
938 __func__, PKTLEN(pkt) + DHD_SDALIGN));
943 PKTALIGN(osh, new, PKTLEN(pkt), DHD_SDALIGN);
944 bcopy(PKTDATA(pkt), PKTDATA(new), PKTLEN(pkt));
946 PKTFREE(osh, pkt, true);
947 /* free the pkt if canned one is not used */
950 frame = (u8 *) PKTDATA(pkt);
951 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
955 frame = (u8 *) PKTDATA(pkt);
957 ASSERT((pad + SDPCM_HDRLEN) <= (int)PKTLEN(pkt));
958 bzero(frame, pad + SDPCM_HDRLEN);
961 ASSERT(pad < DHD_SDALIGN);
963 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
964 len = (u16) PKTLEN(pkt);
965 *(u16 *) frame = htol16(len);
966 *(((u16 *) frame) + 1) = htol16(~len);
968 /* Software tag: channel, sequence number, data offset */
970 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
972 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
973 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
974 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
977 tx_packets[PKTPRIO(pkt)]++;
978 if (DHD_BYTES_ON() &&
979 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
980 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
981 prhex("Tx Frame", frame, len);
982 } else if (DHD_HDRS_ON()) {
983 prhex("TxHdr", frame, min_t(u16, len, 16));
987 /* Raise len to next SDIO block to eliminate tail command */
988 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
989 u16 pad = bus->blocksize - (len % bus->blocksize);
990 if ((pad <= bus->roundup) && (pad < bus->blocksize))
992 if (pad <= PKTTAILROOM(pkt))
995 } else if (len % DHD_SDALIGN) {
996 len += DHD_SDALIGN - (len % DHD_SDALIGN);
999 /* Some controllers have trouble with odd bytes -- round to even */
1000 if (forcealign && (len & (ALIGNMENT - 1))) {
1002 if (PKTTAILROOM(pkt))
1004 len = roundup(len, ALIGNMENT);
1007 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1014 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1015 F2SYNC, frame, len, pkt, NULL, NULL);
1017 ASSERT(ret != BCME_PENDING);
1020 /* On failure, abort the command
1021 and terminate the frame */
1022 DHD_INFO(("%s: sdio error %d, abort command and "
1023 "terminate frame.\n", __func__, ret));
1026 bcmsdh_abort(sdh, SDIO_FUNC_2);
1027 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1028 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1032 for (i = 0; i < 3; i++) {
1034 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1035 SBSDIO_FUNC1_WFRAMEBCHI,
1037 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1038 SBSDIO_FUNC1_WFRAMEBCLO,
1040 bus->f1regdata += 2;
1041 if ((hi == 0) && (lo == 0))
1047 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1049 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1052 /* restore pkt buffer pointer before calling tx complete routine */
1053 PKTPULL(pkt, SDPCM_HDRLEN + pad);
1054 dhd_os_sdunlock(bus->dhd);
1055 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1056 dhd_os_sdlock(bus->dhd);
1059 PKTFREE(osh, pkt, true);
1064 int dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
1066 int ret = BCME_ERROR;
1070 DHD_TRACE(("%s: Enter\n", __func__));
1072 osh = bus->dhd->osh;
1073 datalen = PKTLEN(pkt);
1076 /* Push the test header if doing loopback */
1077 if (bus->ext_loop) {
1079 PKTPUSH(pkt, SDPCM_TEST_HDRLEN);
1080 data = PKTDATA(pkt);
1081 *data++ = SDPCM_TEST_ECHOREQ;
1082 *data++ = (u8) bus->loopid++;
1083 *data++ = (datalen >> 0);
1084 *data++ = (datalen >> 8);
1085 datalen += SDPCM_TEST_HDRLEN;
1089 /* Add space for the header */
1090 PKTPUSH(pkt, SDPCM_HDRLEN);
1091 ASSERT(IS_ALIGNED((unsigned long)PKTDATA(pkt), 2));
1093 prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK));
1095 /* Check for existing queue, current flow-control,
1096 pending event, or pending clock */
1097 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1098 || bus->dpc_sched || (!DATAOK(bus))
1099 || (bus->flowcontrol & NBITVAL(prec))
1100 || (bus->clkstate != CLK_AVAIL)) {
1101 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1102 pktq_len(&bus->txq)));
1105 /* Priority based enq */
1106 dhd_os_sdlock_txq(bus->dhd);
1107 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1108 PKTPULL(pkt, SDPCM_HDRLEN);
1109 dhd_txcomplete(bus->dhd, pkt, false);
1110 PKTFREE(osh, pkt, true);
1111 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1112 ret = BCME_NORESOURCE;
1116 dhd_os_sdunlock_txq(bus->dhd);
1118 if ((pktq_len(&bus->txq) >= FCHI) && dhd_doflow)
1119 dhd_txflowcontrol(bus->dhd, 0, ON);
1122 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1123 qcount[prec] = pktq_plen(&bus->txq, prec);
1125 /* Schedule DPC if needed to send queued packet(s) */
1126 if (dhd_deferred_tx && !bus->dpc_sched) {
1127 bus->dpc_sched = true;
1128 dhd_sched_dpc(bus->dhd);
1131 /* Lock: we're about to use shared data/code (and SDIO) */
1132 dhd_os_sdlock(bus->dhd);
1134 /* Otherwise, send it now */
1136 /* Make sure back plane ht clk is on, no pending allowed */
1137 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1140 DHD_TRACE(("%s: calling txpkt\n", __func__));
1141 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1143 ret = dhdsdio_txpkt(bus, pkt,
1144 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1145 SDPCM_DATA_CHANNEL), true);
1148 bus->dhd->tx_errors++;
1150 bus->dhd->dstats.tx_bytes += datalen;
1152 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1153 bus->activity = false;
1154 dhdsdio_clkctl(bus, CLK_NONE, true);
1157 dhd_os_sdunlock(bus->dhd);
1163 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1168 int ret = 0, prec_out;
1173 dhd_pub_t *dhd = bus->dhd;
1174 sdpcmd_regs_t *regs = bus->regs;
1176 DHD_TRACE(("%s: Enter\n", __func__));
1178 tx_prec_map = ~bus->flowcontrol;
1180 /* Send frames until the limit or some other event */
1181 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1182 dhd_os_sdlock_txq(bus->dhd);
1183 pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1185 dhd_os_sdunlock_txq(bus->dhd);
1188 dhd_os_sdunlock_txq(bus->dhd);
1189 datalen = PKTLEN(pkt) - SDPCM_HDRLEN;
1192 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1194 ret = dhdsdio_txpkt(bus, pkt,
1195 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1196 SDPCM_DATA_CHANNEL), true);
1199 bus->dhd->tx_errors++;
1201 bus->dhd->dstats.tx_bytes += datalen;
1203 /* In poll mode, need to check for other events */
1204 if (!bus->intr && cnt) {
1205 /* Check device status, signal pending interrupt */
1206 R_SDREG(intstatus, ®s->intstatus, retries);
1208 if (bcmsdh_regfail(bus->sdh))
1210 if (intstatus & bus->hostintmask)
1215 /* Deflow-control stack if needed */
1216 if (dhd_doflow && dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1217 dhd->txoff && (pktq_len(&bus->txq) < FCLOW))
1218 dhd_txflowcontrol(dhd, 0, OFF);
1223 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1229 bcmsdh_info_t *sdh = bus->sdh;
1234 DHD_TRACE(("%s: Enter\n", __func__));
1236 if (bus->dhd->dongle_reset)
1239 /* Back the pointer to make a room for bus header */
1240 frame = msg - SDPCM_HDRLEN;
1241 len = (msglen += SDPCM_HDRLEN);
1243 /* Add alignment padding (optional for ctl frames) */
1245 doff = ((unsigned long)frame % DHD_SDALIGN);
1250 bzero(frame, doff + SDPCM_HDRLEN);
1252 ASSERT(doff < DHD_SDALIGN);
1254 doff += SDPCM_HDRLEN;
1256 /* Round send length to next SDIO block */
1257 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1258 u16 pad = bus->blocksize - (len % bus->blocksize);
1259 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1261 } else if (len % DHD_SDALIGN) {
1262 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1265 /* Satisfy length-alignment requirements */
1266 if (forcealign && (len & (ALIGNMENT - 1)))
1267 len = roundup(len, ALIGNMENT);
1269 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1271 /* Need to lock here to protect txseq and SDIO tx calls */
1272 dhd_os_sdlock(bus->dhd);
1276 /* Make sure backplane clock is on */
1277 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1279 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1280 *(u16 *) frame = htol16((u16) msglen);
1281 *(((u16 *) frame) + 1) = htol16(~msglen);
1283 /* Software tag: channel, sequence number, data offset */
1285 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1287 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1288 SDPCM_DOFFSET_MASK);
1289 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
1290 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1293 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1294 __func__, bus->tx_max, bus->tx_seq));
1295 bus->ctrl_frame_stat = true;
1297 bus->ctrl_frame_buf = frame;
1298 bus->ctrl_frame_len = len;
1300 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1302 if (bus->ctrl_frame_stat == false) {
1303 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1306 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1313 if (DHD_BYTES_ON() && DHD_CTL_ON())
1314 prhex("Tx Frame", frame, len);
1315 else if (DHD_HDRS_ON())
1316 prhex("TxHdr", frame, min_t(u16, len, 16));
1320 bus->ctrl_frame_stat = false;
1322 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1323 SDIO_FUNC_2, F2SYNC, frame, len,
1326 ASSERT(ret != BCME_PENDING);
1329 /* On failure, abort the command and
1330 terminate the frame */
1331 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1335 bcmsdh_abort(sdh, SDIO_FUNC_2);
1337 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1338 SBSDIO_FUNC1_FRAMECTRL,
1342 for (i = 0; i < 3; i++) {
1344 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1345 SBSDIO_FUNC1_WFRAMEBCHI,
1347 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1348 SBSDIO_FUNC1_WFRAMEBCLO,
1350 bus->f1regdata += 2;
1351 if ((hi == 0) && (lo == 0))
1358 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1360 } while ((ret < 0) && retries++ < TXRETRIES);
1363 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1364 bus->activity = false;
1365 dhdsdio_clkctl(bus, CLK_NONE, true);
1368 dhd_os_sdunlock(bus->dhd);
1371 bus->dhd->tx_ctlerrs++;
1373 bus->dhd->tx_ctlpkts++;
1375 return ret ? -EIO : 0;
1378 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1384 DHD_TRACE(("%s: Enter\n", __func__));
1386 if (bus->dhd->dongle_reset)
1389 /* Wait until control frame is available */
1390 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1392 dhd_os_sdlock(bus->dhd);
1394 bcopy(bus->rxctl, msg, min(msglen, rxlen));
1396 dhd_os_sdunlock(bus->dhd);
1399 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1400 __func__, rxlen, msglen));
1401 } else if (timeleft == 0) {
1402 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1404 dhd_os_sdlock(bus->dhd);
1405 dhdsdio_checkdied(bus, NULL, 0);
1406 dhd_os_sdunlock(bus->dhd);
1407 #endif /* DHD_DEBUG */
1408 } else if (pending == true) {
1409 DHD_CTL(("%s: cancelled\n", __func__));
1410 return -ERESTARTSYS;
1412 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1414 dhd_os_sdlock(bus->dhd);
1415 dhdsdio_checkdied(bus, NULL, 0);
1416 dhd_os_sdunlock(bus->dhd);
1417 #endif /* DHD_DEBUG */
1421 bus->dhd->rx_ctlpkts++;
1423 bus->dhd->rx_ctlerrs++;
1425 return rxlen ? (int)rxlen : -ETIMEDOUT;
1464 const bcm_iovar_t dhdsdio_iovars[] = {
1465 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1466 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1467 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1468 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1469 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1470 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1471 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1472 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1473 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1474 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1475 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1476 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1477 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1478 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1479 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1480 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1482 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1484 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1486 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1488 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1490 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1492 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1494 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1496 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1499 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1501 #endif /* DHD_DEBUG */
1502 #endif /* DHD_DEBUG */
1504 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1506 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1514 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1519 bcm_bprintf(strbuf, "%s N/A", desc);
1522 q2 = (100 * (num - (q1 * div))) / div;
1523 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1527 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1529 dhd_bus_t *bus = dhdp->bus;
1531 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1533 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1534 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1536 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1537 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1538 bus->rxskip, bus->rxlen, bus->rx_seq);
1539 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1540 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1541 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1542 bus->pollrate, bus->pollcnt, bus->regfails);
1544 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1546 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1547 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1549 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1550 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1551 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1552 bus->fc_xoff, bus->fc_xon);
1553 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1554 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1555 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1556 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1557 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1559 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1560 (bus->f2rxhdrs + bus->f2rxdata));
1561 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1563 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1564 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1565 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1567 bcm_bprintf(strbuf, "\n");
1569 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1570 bus->dhd->rx_packets);
1571 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1573 bcm_bprintf(strbuf, "\n");
1575 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1577 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1579 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1580 (bus->f2txdata + bus->f1regdata));
1581 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1583 bcm_bprintf(strbuf, "\n");
1585 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1586 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1587 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1588 dhd_dump_pct(strbuf, ", pkts/f1sd",
1589 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1591 dhd_dump_pct(strbuf, ", pkts/sd",
1592 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1593 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1595 dhd_dump_pct(strbuf, ", pkts/int",
1596 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1598 bcm_bprintf(strbuf, "\n\n");
1602 if (bus->pktgen_count) {
1603 bcm_bprintf(strbuf, "pktgen config and count:\n");
1605 "freq %d count %d print %d total %d min %d len %d\n",
1606 bus->pktgen_freq, bus->pktgen_count,
1607 bus->pktgen_print, bus->pktgen_total,
1608 bus->pktgen_minlen, bus->pktgen_maxlen);
1609 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1610 bus->pktgen_sent, bus->pktgen_rcvd,
1615 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1617 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1618 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1620 #endif /* DHD_DEBUG */
1622 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1623 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1627 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1629 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1631 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1632 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1633 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1634 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1635 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1636 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1640 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1642 dhd_pktgen_t pktgen;
1644 pktgen.version = DHD_PKTGEN_VERSION;
1645 pktgen.freq = bus->pktgen_freq;
1646 pktgen.count = bus->pktgen_count;
1647 pktgen.print = bus->pktgen_print;
1648 pktgen.total = bus->pktgen_total;
1649 pktgen.minlen = bus->pktgen_minlen;
1650 pktgen.maxlen = bus->pktgen_maxlen;
1651 pktgen.numsent = bus->pktgen_sent;
1652 pktgen.numrcvd = bus->pktgen_rcvd;
1653 pktgen.numfail = bus->pktgen_fail;
1654 pktgen.mode = bus->pktgen_mode;
1655 pktgen.stop = bus->pktgen_stop;
1657 bcopy(&pktgen, arg, sizeof(pktgen));
1662 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1664 dhd_pktgen_t pktgen;
1665 uint oldcnt, oldmode;
1667 bcopy(arg, &pktgen, sizeof(pktgen));
1668 if (pktgen.version != DHD_PKTGEN_VERSION)
1671 oldcnt = bus->pktgen_count;
1672 oldmode = bus->pktgen_mode;
1674 bus->pktgen_freq = pktgen.freq;
1675 bus->pktgen_count = pktgen.count;
1676 bus->pktgen_print = pktgen.print;
1677 bus->pktgen_total = pktgen.total;
1678 bus->pktgen_minlen = pktgen.minlen;
1679 bus->pktgen_maxlen = pktgen.maxlen;
1680 bus->pktgen_mode = pktgen.mode;
1681 bus->pktgen_stop = pktgen.stop;
1683 bus->pktgen_tick = bus->pktgen_ptick = 0;
1684 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1685 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1687 /* Clear counts for a new pktgen (mode change, or was stopped) */
1688 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1689 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1696 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1703 /* Determine initial transfer parameters */
1704 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1705 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1706 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1710 /* Set the backplane window to include the start address */
1711 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1713 DHD_ERROR(("%s: window change failed\n", __func__));
1717 /* Do the transfer(s) */
1719 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1720 __func__, (write ? "write" : "read"), dsize,
1721 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1723 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1725 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1729 /* Adjust for next transfer (if any) */
1734 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1736 DHD_ERROR(("%s: window change failed\n",
1741 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1746 /* Return the window to backplane enumeration space for core access */
1747 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1748 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1749 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1756 static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1761 /* Read last word in memory to determine address of
1762 sdpcm_shared structure */
1763 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
1767 addr = ltoh32(addr);
1769 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1772 * Check if addr is valid.
1773 * NVRAM length at the end of memory should have been overwritten.
1775 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1776 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1781 /* Read hndrte_shared structure */
1782 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
1783 sizeof(sdpcm_shared_t));
1788 sh->flags = ltoh32(sh->flags);
1789 sh->trap_addr = ltoh32(sh->trap_addr);
1790 sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
1791 sh->assert_file_addr = ltoh32(sh->assert_file_addr);
1792 sh->assert_line = ltoh32(sh->assert_line);
1793 sh->console_addr = ltoh32(sh->console_addr);
1794 sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
1796 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1797 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1798 "is different than sdpcm_shared version %d in dongle\n",
1799 __func__, SDPCM_SHARED_VERSION,
1800 sh->flags & SDPCM_SHARED_VERSION_MASK));
1807 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1811 char *mbuffer = NULL;
1812 uint maxstrlen = 256;
1815 sdpcm_shared_t sdpcm_shared;
1816 struct bcmstrbuf strbuf;
1818 DHD_TRACE(("%s: Enter\n", __func__));
1822 * Called after a rx ctrl timeout. "data" is NULL.
1823 * allocate memory to trace the trap or assert.
1826 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1827 if (mbuffer == NULL) {
1828 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1830 bcmerror = BCME_NOMEM;
1835 str = kmalloc(maxstrlen, GFP_ATOMIC);
1837 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1838 bcmerror = BCME_NOMEM;
1842 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1846 bcm_binit(&strbuf, data, size);
1848 bcm_bprintf(&strbuf,
1849 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1850 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1852 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1853 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1854 * (Avoids conflict with real asserts for programmatic
1855 * parsing of output.)
1857 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1860 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1862 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1863 * (Avoids conflict with real asserts for programmatic
1864 * parsing of output.)
1866 bcm_bprintf(&strbuf, "No trap%s in dongle",
1867 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1870 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1871 /* Download assert */
1872 bcm_bprintf(&strbuf, "Dongle assert");
1873 if (sdpcm_shared.assert_exp_addr != 0) {
1875 bcmerror = dhdsdio_membytes(bus, false,
1876 sdpcm_shared.assert_exp_addr,
1877 (u8 *) str, maxstrlen);
1881 str[maxstrlen - 1] = '\0';
1882 bcm_bprintf(&strbuf, " expr \"%s\"", str);
1885 if (sdpcm_shared.assert_file_addr != 0) {
1887 bcmerror = dhdsdio_membytes(bus, false,
1888 sdpcm_shared.assert_file_addr,
1889 (u8 *) str, maxstrlen);
1893 str[maxstrlen - 1] = '\0';
1894 bcm_bprintf(&strbuf, " file \"%s\"", str);
1897 bcm_bprintf(&strbuf, " line %d ",
1898 sdpcm_shared.assert_line);
1901 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1902 bcmerror = dhdsdio_membytes(bus, false,
1903 sdpcm_shared.trap_addr, (u8 *)&tr,
1908 bcm_bprintf(&strbuf,
1909 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1910 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1911 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1912 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1913 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1914 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1919 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1920 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
1923 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1924 /* Mem dump to a file on device */
1925 dhdsdio_mem_dump(bus);
1927 #endif /* DHD_DEBUG */
1938 static int dhdsdio_mem_dump(dhd_bus_t *bus)
1941 int size; /* Full mem size */
1942 int start = 0; /* Start address */
1943 int read_size = 0; /* Read size of each iteration */
1944 u8 *buf = NULL, *databuf = NULL;
1946 /* Get full mem size */
1947 size = bus->ramsize;
1948 buf = kmalloc(size, GFP_ATOMIC);
1950 printf("%s: Out of memory (%d bytes)\n", __func__, size);
1954 /* Read mem content */
1955 printf("Dump dongle memory");
1958 read_size = min(MEMBLOCK, size);
1959 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
1961 printf("%s: Error membytes %d\n", __func__, ret);
1968 /* Decrement size and increment start address */
1971 databuf += read_size;
1975 /* free buf before return !!! */
1976 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1977 printf("%s: Error writing to files\n", __func__);
1981 /* buf free handled in write_to_file, not here */
1985 #define CONSOLE_LINE_MAX 192
1987 static int dhdsdio_readconsole(dhd_bus_t *bus)
1989 dhd_console_t *c = &bus->console;
1990 u8 line[CONSOLE_LINE_MAX], ch;
1994 /* Don't do anything until FWREADY updates console address */
1995 if (bus->console_addr == 0)
1998 /* Read console log struct */
1999 addr = bus->console_addr + offsetof(hndrte_cons_t, log);
2000 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2005 /* Allocate console buffer (one time only) */
2006 if (c->buf == NULL) {
2007 c->bufsize = ltoh32(c->log.buf_size);
2008 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2013 idx = ltoh32(c->log.idx);
2015 /* Protect against corrupt value */
2016 if (idx > c->bufsize)
2019 /* Skip reading the console buffer if the index pointer
2024 /* Read the console buffer */
2025 addr = ltoh32(c->log.buf);
2026 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2030 while (c->last != idx) {
2031 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2032 if (c->last == idx) {
2033 /* This would output a partial line.
2035 * the buffer pointer and output this
2036 * line next time around.
2041 c->last = c->bufsize - n;
2044 ch = c->buf[c->last];
2045 c->last = (c->last + 1) % c->bufsize;
2052 if (line[n - 1] == '\r')
2055 printf("CONSOLE: %s\n", line);
2062 #endif /* DHD_DEBUG */
2064 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2066 int bcmerror = BCME_OK;
2068 DHD_TRACE(("%s: Enter\n", __func__));
2070 /* Basic sanity checks */
2072 bcmerror = BCME_NOTDOWN;
2076 bcmerror = BCME_BUFTOOSHORT;
2080 /* Free the old ones and replace with passed variables */
2084 bus->vars = kmalloc(len, GFP_ATOMIC);
2085 bus->varsz = bus->vars ? len : 0;
2086 if (bus->vars == NULL) {
2087 bcmerror = BCME_NOMEM;
2091 /* Copy the passed variables, which should include the
2092 terminating double-null */
2093 bcopy(arg, bus->vars, bus->varsz);
2099 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2100 const char *name, void *params, int plen, void *arg, int len,
2107 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2108 "len %d val_size %d\n",
2109 __func__, actionid, name, params, plen, arg, len, val_size));
2111 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2115 if (plen >= (int)sizeof(int_val))
2116 bcopy(params, &int_val, sizeof(int_val));
2118 bool_val = (int_val != 0) ? true : false;
2120 /* Some ioctls use the bus */
2121 dhd_os_sdlock(bus->dhd);
2123 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2124 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2125 actionid == IOV_GVAL(IOV_DEVRESET))) {
2126 bcmerror = BCME_NOTREADY;
2130 /* Handle sleep stuff before any clock mucking */
2131 if (vi->varid == IOV_SLEEP) {
2132 if (IOV_ISSET(actionid)) {
2133 bcmerror = dhdsdio_bussleep(bus, bool_val);
2135 int_val = (s32) bus->sleeping;
2136 bcopy(&int_val, arg, val_size);
2141 /* Request clock to allow SDIO accesses */
2142 if (!bus->dhd->dongle_reset) {
2144 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2148 case IOV_GVAL(IOV_INTR):
2149 int_val = (s32) bus->intr;
2150 bcopy(&int_val, arg, val_size);
2153 case IOV_SVAL(IOV_INTR):
2154 bus->intr = bool_val;
2155 bus->intdis = false;
2158 DHD_INTR(("%s: enable SDIO device interrupts\n",
2160 bcmsdh_intr_enable(bus->sdh);
2162 DHD_INTR(("%s: disable SDIO interrupts\n",
2164 bcmsdh_intr_disable(bus->sdh);
2169 case IOV_GVAL(IOV_POLLRATE):
2170 int_val = (s32) bus->pollrate;
2171 bcopy(&int_val, arg, val_size);
2174 case IOV_SVAL(IOV_POLLRATE):
2175 bus->pollrate = (uint) int_val;
2176 bus->poll = (bus->pollrate != 0);
2179 case IOV_GVAL(IOV_IDLETIME):
2180 int_val = bus->idletime;
2181 bcopy(&int_val, arg, val_size);
2184 case IOV_SVAL(IOV_IDLETIME):
2185 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2186 bcmerror = BCME_BADARG;
2188 bus->idletime = int_val;
2191 case IOV_GVAL(IOV_IDLECLOCK):
2192 int_val = (s32) bus->idleclock;
2193 bcopy(&int_val, arg, val_size);
2196 case IOV_SVAL(IOV_IDLECLOCK):
2197 bus->idleclock = int_val;
2200 case IOV_GVAL(IOV_SD1IDLE):
2201 int_val = (s32) sd1idle;
2202 bcopy(&int_val, arg, val_size);
2205 case IOV_SVAL(IOV_SD1IDLE):
2209 case IOV_SVAL(IOV_MEMBYTES):
2210 case IOV_GVAL(IOV_MEMBYTES):
2216 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2218 ASSERT(plen >= 2 * sizeof(int));
2220 address = (u32) int_val;
2221 bcopy((char *)params + sizeof(int_val), &int_val,
2223 size = (uint) int_val;
2225 /* Do some validation */
2226 dsize = set ? plen - (2 * sizeof(int)) : len;
2228 DHD_ERROR(("%s: error on %s membytes, addr "
2229 "0x%08x size %d dsize %d\n",
2230 __func__, (set ? "set" : "get"),
2231 address, size, dsize));
2232 bcmerror = BCME_BADARG;
2236 DHD_INFO(("%s: Request to %s %d bytes at address "
2238 __func__, (set ? "write" : "read"), size, address));
2240 /* If we know about SOCRAM, check for a fit */
2241 if ((bus->orig_ramsize) &&
2242 ((address > bus->orig_ramsize)
2243 || (address + size > bus->orig_ramsize))) {
2244 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2245 "bytes at 0x%08x\n",
2246 __func__, bus->orig_ramsize, size, address));
2247 bcmerror = BCME_BADARG;
2251 /* Generate the actual data pointer */
2253 set ? (u8 *) params +
2254 2 * sizeof(int) : (u8 *) arg;
2256 /* Call to do the transfer */
2258 dhdsdio_membytes(bus, set, address, data, size);
2263 case IOV_GVAL(IOV_MEMSIZE):
2264 int_val = (s32) bus->ramsize;
2265 bcopy(&int_val, arg, val_size);
2268 case IOV_GVAL(IOV_SDIOD_DRIVE):
2269 int_val = (s32) dhd_sdiod_drive_strength;
2270 bcopy(&int_val, arg, val_size);
2273 case IOV_SVAL(IOV_SDIOD_DRIVE):
2274 dhd_sdiod_drive_strength = int_val;
2275 si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh,
2276 dhd_sdiod_drive_strength);
2279 case IOV_SVAL(IOV_DOWNLOAD):
2280 bcmerror = dhdsdio_download_state(bus, bool_val);
2283 case IOV_SVAL(IOV_VARS):
2284 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2287 case IOV_GVAL(IOV_READAHEAD):
2288 int_val = (s32) dhd_readahead;
2289 bcopy(&int_val, arg, val_size);
2292 case IOV_SVAL(IOV_READAHEAD):
2293 if (bool_val && !dhd_readahead)
2295 dhd_readahead = bool_val;
2298 case IOV_GVAL(IOV_SDRXCHAIN):
2299 int_val = (s32) bus->use_rxchain;
2300 bcopy(&int_val, arg, val_size);
2303 case IOV_SVAL(IOV_SDRXCHAIN):
2304 if (bool_val && !bus->sd_rxchain)
2305 bcmerror = BCME_UNSUPPORTED;
2307 bus->use_rxchain = bool_val;
2309 case IOV_GVAL(IOV_ALIGNCTL):
2310 int_val = (s32) dhd_alignctl;
2311 bcopy(&int_val, arg, val_size);
2314 case IOV_SVAL(IOV_ALIGNCTL):
2315 dhd_alignctl = bool_val;
2318 case IOV_GVAL(IOV_SDALIGN):
2319 int_val = DHD_SDALIGN;
2320 bcopy(&int_val, arg, val_size);
2324 case IOV_GVAL(IOV_VARS):
2325 if (bus->varsz < (uint) len)
2326 bcopy(bus->vars, arg, bus->varsz);
2328 bcmerror = BCME_BUFTOOSHORT;
2330 #endif /* DHD_DEBUG */
2333 case IOV_GVAL(IOV_SDREG):
2338 sd_ptr = (sdreg_t *) params;
2340 addr = (unsigned long)bus->regs + sd_ptr->offset;
2341 size = sd_ptr->func;
2342 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2343 if (bcmsdh_regfail(bus->sdh))
2344 bcmerror = BCME_SDIO_ERROR;
2345 bcopy(&int_val, arg, sizeof(s32));
2349 case IOV_SVAL(IOV_SDREG):
2354 sd_ptr = (sdreg_t *) params;
2356 addr = (unsigned long)bus->regs + sd_ptr->offset;
2357 size = sd_ptr->func;
2358 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2359 if (bcmsdh_regfail(bus->sdh))
2360 bcmerror = BCME_SDIO_ERROR;
2364 /* Same as above, but offset is not backplane
2366 case IOV_GVAL(IOV_SBREG):
2371 bcopy(params, &sdreg, sizeof(sdreg));
2373 addr = SI_ENUM_BASE + sdreg.offset;
2375 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2376 if (bcmsdh_regfail(bus->sdh))
2377 bcmerror = BCME_SDIO_ERROR;
2378 bcopy(&int_val, arg, sizeof(s32));
2382 case IOV_SVAL(IOV_SBREG):
2387 bcopy(params, &sdreg, sizeof(sdreg));
2389 addr = SI_ENUM_BASE + sdreg.offset;
2391 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2392 if (bcmsdh_regfail(bus->sdh))
2393 bcmerror = BCME_SDIO_ERROR;
2397 case IOV_GVAL(IOV_SDCIS):
2401 strcat(arg, "\nFunc 0\n");
2402 bcmsdh_cis_read(bus->sdh, 0x10,
2403 (u8 *) arg + strlen(arg),
2404 SBSDIO_CIS_SIZE_LIMIT);
2405 strcat(arg, "\nFunc 1\n");
2406 bcmsdh_cis_read(bus->sdh, 0x11,
2407 (u8 *) arg + strlen(arg),
2408 SBSDIO_CIS_SIZE_LIMIT);
2409 strcat(arg, "\nFunc 2\n");
2410 bcmsdh_cis_read(bus->sdh, 0x12,
2411 (u8 *) arg + strlen(arg),
2412 SBSDIO_CIS_SIZE_LIMIT);
2416 case IOV_GVAL(IOV_FORCEEVEN):
2417 int_val = (s32) forcealign;
2418 bcopy(&int_val, arg, val_size);
2421 case IOV_SVAL(IOV_FORCEEVEN):
2422 forcealign = bool_val;
2425 case IOV_GVAL(IOV_TXBOUND):
2426 int_val = (s32) dhd_txbound;
2427 bcopy(&int_val, arg, val_size);
2430 case IOV_SVAL(IOV_TXBOUND):
2431 dhd_txbound = (uint) int_val;
2434 case IOV_GVAL(IOV_RXBOUND):
2435 int_val = (s32) dhd_rxbound;
2436 bcopy(&int_val, arg, val_size);
2439 case IOV_SVAL(IOV_RXBOUND):
2440 dhd_rxbound = (uint) int_val;
2443 case IOV_GVAL(IOV_TXMINMAX):
2444 int_val = (s32) dhd_txminmax;
2445 bcopy(&int_val, arg, val_size);
2448 case IOV_SVAL(IOV_TXMINMAX):
2449 dhd_txminmax = (uint) int_val;
2451 #endif /* DHD_DEBUG */
2454 case IOV_GVAL(IOV_EXTLOOP):
2455 int_val = (s32) bus->ext_loop;
2456 bcopy(&int_val, arg, val_size);
2459 case IOV_SVAL(IOV_EXTLOOP):
2460 bus->ext_loop = bool_val;
2463 case IOV_GVAL(IOV_PKTGEN):
2464 bcmerror = dhdsdio_pktgen_get(bus, arg);
2467 case IOV_SVAL(IOV_PKTGEN):
2468 bcmerror = dhdsdio_pktgen_set(bus, arg);
2472 case IOV_SVAL(IOV_DEVRESET):
2473 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2475 __func__, bool_val, bus->dhd->dongle_reset,
2476 bus->dhd->busstate));
2478 ASSERT(bus->dhd->osh);
2479 /* ASSERT(bus->cl_devid); */
2481 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2485 case IOV_GVAL(IOV_DEVRESET):
2486 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2488 /* Get its status */
2489 int_val = (bool) bus->dhd->dongle_reset;
2490 bcopy(&int_val, arg, val_size);
2495 bcmerror = BCME_UNSUPPORTED;
2500 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2501 bus->activity = false;
2502 dhdsdio_clkctl(bus, CLK_NONE, true);
2505 dhd_os_sdunlock(bus->dhd);
2507 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2508 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2513 static int dhdsdio_write_vars(dhd_bus_t *bus)
2521 char *nvram_ularray;
2522 #endif /* DHD_DEBUG */
2524 /* Even if there are no vars are to be written, we still
2525 need to set the ramsize. */
2526 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2527 varaddr = (bus->ramsize - 4) - varsize;
2530 vbuffer = kmalloc(varsize, GFP_ATOMIC);
2534 bzero(vbuffer, varsize);
2535 bcopy(bus->vars, vbuffer, bus->varsz);
2537 /* Write the vars list */
2539 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2541 /* Verify NVRAM bytes */
2542 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2543 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2547 /* Upload image to verify downloaded contents. */
2548 memset(nvram_ularray, 0xaa, varsize);
2550 /* Read the vars list to temp buffer for comparison */
2552 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2555 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2556 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2558 /* Compare the org NVRAM with the one read from RAM */
2559 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2560 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2563 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2566 kfree(nvram_ularray);
2567 #endif /* DHD_DEBUG */
2572 /* adjust to the user specified RAM */
2573 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2574 bus->orig_ramsize, bus->ramsize));
2575 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2576 varsize = ((bus->orig_ramsize - 4) - varaddr);
2579 * Determine the length token:
2580 * Varsize, converted to words, in lower 16-bits, checksum
2586 varsizew = varsize / 4;
2587 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2588 varsizew = htol32(varsizew);
2591 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2594 /* Write the length token to the last word */
2595 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2596 (u8 *)&varsizew, 4);
2601 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2606 /* To enter download state, disable ARM and reset SOCRAM.
2607 * To exit download state, simply reset ARM (default is RAM boot).
2611 bus->alp_only = true;
2613 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2614 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2615 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2616 bcmerror = BCME_ERROR;
2620 si_core_disable(bus->sih, 0);
2621 if (bcmsdh_regfail(bus->sdh)) {
2622 bcmerror = BCME_SDIO_ERROR;
2626 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2627 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2629 bcmerror = BCME_ERROR;
2633 si_core_reset(bus->sih, 0, 0);
2634 if (bcmsdh_regfail(bus->sdh)) {
2635 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2637 bcmerror = BCME_SDIO_ERROR;
2641 /* Clear the top bit of memory */
2644 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2648 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2649 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2651 bcmerror = BCME_ERROR;
2655 if (!si_iscoreup(bus->sih)) {
2656 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2658 bcmerror = BCME_ERROR;
2662 bcmerror = dhdsdio_write_vars(bus);
2664 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2668 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2669 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2670 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2672 bcmerror = BCME_ERROR;
2675 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2677 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2678 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2679 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2680 bcmerror = BCME_ERROR;
2684 si_core_reset(bus->sih, 0, 0);
2685 if (bcmsdh_regfail(bus->sdh)) {
2686 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2688 bcmerror = BCME_SDIO_ERROR;
2692 /* Allow HT Clock now that the ARM is running. */
2693 bus->alp_only = false;
2695 bus->dhd->busstate = DHD_BUS_LOAD;
2699 /* Always return to SDIOD core */
2700 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2701 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2707 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2708 void *params, int plen, void *arg, int len, bool set)
2710 dhd_bus_t *bus = dhdp->bus;
2711 const bcm_iovar_t *vi = NULL;
2716 DHD_TRACE(("%s: Enter\n", __func__));
2721 /* Get MUST have return space */
2722 ASSERT(set || (arg && len));
2724 /* Set does NOT take qualifiers */
2725 ASSERT(!set || (!params && !plen));
2727 /* Look up var locally; if not found pass to host driver */
2728 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2730 dhd_os_sdlock(bus->dhd);
2734 /* Turn on clock in case SD command needs backplane */
2735 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2738 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2741 /* Check for bus configuration changes of interest */
2743 /* If it was divisor change, read the new one */
2744 if (set && strcmp(name, "sd_divisor") == 0) {
2745 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2746 &bus->sd_divisor, sizeof(s32),
2747 false) != BCME_OK) {
2748 bus->sd_divisor = -1;
2749 DHD_ERROR(("%s: fail on %s get\n", __func__,
2752 DHD_INFO(("%s: noted %s update, value now %d\n",
2753 __func__, name, bus->sd_divisor));
2756 /* If it was a mode change, read the new one */
2757 if (set && strcmp(name, "sd_mode") == 0) {
2758 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2759 &bus->sd_mode, sizeof(s32),
2760 false) != BCME_OK) {
2762 DHD_ERROR(("%s: fail on %s get\n", __func__,
2765 DHD_INFO(("%s: noted %s update, value now %d\n",
2766 __func__, name, bus->sd_mode));
2769 /* Similar check for blocksize change */
2770 if (set && strcmp(name, "sd_blocksize") == 0) {
2773 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2774 &bus->blocksize, sizeof(s32),
2775 false) != BCME_OK) {
2777 DHD_ERROR(("%s: fail on %s get\n", __func__,
2780 DHD_INFO(("%s: noted %s update, value now %d\n",
2781 __func__, "sd_blocksize",
2785 bus->roundup = min(max_roundup, bus->blocksize);
2787 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2788 bus->activity = false;
2789 dhdsdio_clkctl(bus, CLK_NONE, true);
2792 dhd_os_sdunlock(bus->dhd);
2796 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2797 name, (set ? "set" : "get"), len, plen));
2799 /* set up 'params' pointer in case this is a set command so that
2800 * the convenience int and bool code can be common to set and get
2802 if (params == NULL) {
2807 if (vi->type == IOVT_VOID)
2809 else if (vi->type == IOVT_BUFFER)
2812 /* all other types are integer sized */
2813 val_size = sizeof(int);
2815 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2817 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2824 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2826 osl_t *osh = bus->dhd->osh;
2827 u32 local_hostintmask;
2832 DHD_TRACE(("%s: Enter\n", __func__));
2835 dhd_os_sdlock(bus->dhd);
2839 /* Enable clock for device interrupts */
2840 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2842 /* Disable and clear interrupts at the chip level also */
2843 W_SDREG(0, &bus->regs->hostintmask, retries);
2844 local_hostintmask = bus->hostintmask;
2845 bus->hostintmask = 0;
2847 /* Change our idea of bus state */
2848 bus->dhd->busstate = DHD_BUS_DOWN;
2850 /* Force clocks on backplane to be sure F2 interrupt propagates */
2852 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2855 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2856 (saveclk | SBSDIO_FORCE_HT), &err);
2859 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2863 /* Turn off the bus (F2), free any pending packets */
2864 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2865 bcmsdh_intr_disable(bus->sdh);
2866 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2867 SDIO_FUNC_ENABLE_1, NULL);
2869 /* Clear any pending interrupts now that F2 is disabled */
2870 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2872 /* Turn off the backplane clock (only) */
2873 dhdsdio_clkctl(bus, CLK_SDONLY, false);
2875 /* Clear the data packet queues */
2876 pktq_flush(osh, &bus->txq, true);
2878 /* Clear any held glomming stuff */
2880 PKTFREE(osh, bus->glomd, false);
2883 PKTFREE(osh, bus->glom, false);
2885 bus->glom = bus->glomd = NULL;
2887 /* Clear rx control and wake any waiters */
2889 dhd_os_ioctl_resp_wake(bus->dhd);
2891 /* Reset some F2 state stuff */
2892 bus->rxskip = false;
2893 bus->tx_seq = bus->rx_seq = 0;
2896 dhd_os_sdunlock(bus->dhd);
2899 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2901 dhd_bus_t *bus = dhdp->bus;
2908 DHD_TRACE(("%s: Enter\n", __func__));
2915 dhd_os_sdlock(bus->dhd);
2917 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2918 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2919 if (bus->clkstate != CLK_AVAIL)
2922 /* Force clocks on backplane to be sure F2 interrupt propagates */
2924 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2927 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2928 (saveclk | SBSDIO_FORCE_HT), &err);
2931 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2936 /* Enable function 2 (frame transfers) */
2937 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2938 &bus->regs->tosbmailboxdata, retries);
2939 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2941 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2943 /* Give the dongle some time to do its thing and set IOR2 */
2944 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2947 while (ready != enable && !dhd_timeout_expired(&tmo))
2949 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2952 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2953 __func__, enable, ready, tmo.elapsed));
2955 /* If F2 successfully enabled, set core and enable interrupts */
2956 if (ready == enable) {
2957 /* Make sure we're talking to the core. */
2958 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2960 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2962 /* Set up the interrupt mask and enable interrupts */
2963 bus->hostintmask = HOSTINTMASK;
2964 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
2966 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
2967 (u8) watermark, &err);
2969 /* Set bus state according to enable result */
2970 dhdp->busstate = DHD_BUS_DATA;
2972 /* bcmsdh_intr_unmask(bus->sdh); */
2974 bus->intdis = false;
2976 DHD_INTR(("%s: enable SDIO device interrupts\n",
2978 bcmsdh_intr_enable(bus->sdh);
2980 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2981 bcmsdh_intr_disable(bus->sdh);
2987 /* Disable F2 again */
2988 enable = SDIO_FUNC_ENABLE_1;
2989 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
2993 /* Restore previous clock setting */
2994 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2997 /* If we didn't come up, turn off backplane clock */
2998 if (dhdp->busstate != DHD_BUS_DATA)
2999 dhdsdio_clkctl(bus, CLK_NONE, false);
3003 dhd_os_sdunlock(bus->dhd);
3008 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3010 bcmsdh_info_t *sdh = bus->sdh;
3011 sdpcmd_regs_t *regs = bus->regs;
3017 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3018 (abort ? "abort command, " : ""),
3019 (rtx ? ", send NAK" : "")));
3022 bcmsdh_abort(sdh, SDIO_FUNC_2);
3024 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3028 /* Wait until the packet has been flushed (device/FIFO stable) */
3029 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3030 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3032 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3034 bus->f1regdata += 2;
3036 if ((hi == 0) && (lo == 0))
3039 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3040 DHD_ERROR(("%s: count growing: last 0x%04x now "
3042 __func__, lastrbc, ((hi << 8) + lo)));
3044 lastrbc = (hi << 8) + lo;
3048 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3049 __func__, lastrbc));
3051 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3052 (0xffff - retries)));
3057 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3059 if (retries <= retry_limit)
3063 /* Clear partial in any case */
3066 /* If we can't reach the device, signal failure */
3067 if (err || bcmsdh_regfail(sdh))
3068 bus->dhd->busstate = DHD_BUS_DOWN;
3072 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3074 bcmsdh_info_t *sdh = bus->sdh;
3079 DHD_TRACE(("%s: Enter\n", __func__));
3081 /* Control data already received in aligned rxctl */
3082 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3086 /* Set rxctl for frame (w/optional alignment) */
3087 bus->rxctl = bus->rxbuf;
3089 bus->rxctl += firstread;
3090 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3092 bus->rxctl += (DHD_SDALIGN - pad);
3093 bus->rxctl -= firstread;
3095 ASSERT(bus->rxctl >= bus->rxbuf);
3097 /* Copy the already-read portion over */
3098 bcopy(hdr, bus->rxctl, firstread);
3099 if (len <= firstread)
3102 /* Copy the full data pkt in gSPI case and process ioctl. */
3103 if (bus->bus == SPI_BUS) {
3104 bcopy(hdr, bus->rxctl, len);
3108 /* Raise rdlen to next SDIO block to avoid tail command */
3109 rdlen = len - firstread;
3110 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3111 pad = bus->blocksize - (rdlen % bus->blocksize);
3112 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3113 ((len + pad) < bus->dhd->maxctl))
3115 } else if (rdlen % DHD_SDALIGN) {
3116 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3119 /* Satisfy length-alignment requirements */
3120 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3121 rdlen = roundup(rdlen, ALIGNMENT);
3123 /* Drop if the read is too big or it exceeds our maximum */
3124 if ((rdlen + firstread) > bus->dhd->maxctl) {
3125 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3126 __func__, rdlen, bus->dhd->maxctl));
3127 bus->dhd->rx_errors++;
3128 dhdsdio_rxfail(bus, false, false);
3132 if ((len - doff) > bus->dhd->maxctl) {
3133 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3135 __func__, len, (len - doff), bus->dhd->maxctl));
3136 bus->dhd->rx_errors++;
3138 dhdsdio_rxfail(bus, false, false);
3142 /* Read remainder of frame body into the rxctl buffer */
3144 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3145 (bus->rxctl + firstread), rdlen, NULL, NULL,
3148 ASSERT(sdret != BCME_PENDING);
3150 /* Control frame failures need retransmission */
3152 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3153 __func__, rdlen, sdret));
3154 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3155 dhdsdio_rxfail(bus, true, true);
3162 if (DHD_BYTES_ON() && DHD_CTL_ON())
3163 prhex("RxCtrl", bus->rxctl, len);
3166 /* Point to valid data and indicate its length */
3168 bus->rxlen = len - doff;
3171 /* Awake any waiters */
3172 dhd_os_ioctl_resp_wake(bus->dhd);
3175 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3181 void *pfirst, *plast, *pnext, *save_pfirst;
3182 osl_t *osh = bus->dhd->osh;
3185 u8 chan, seq, doff, sfdoff;
3189 bool usechain = bus->use_rxchain;
3191 /* If packets, issue read(s) and send up packet chain */
3192 /* Return sequence numbers consumed? */
3194 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3197 /* If there's a descriptor, generate the packet chain */
3199 dhd_os_sdlock_rxq(bus->dhd);
3201 pfirst = plast = pnext = NULL;
3202 dlen = (u16) PKTLEN(bus->glomd);
3203 dptr = PKTDATA(bus->glomd);
3204 if (!dlen || (dlen & 1)) {
3205 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3210 for (totlen = num = 0; dlen; num++) {
3211 /* Get (and move past) next length */
3212 sublen = ltoh16_ua(dptr);
3213 dlen -= sizeof(u16);
3214 dptr += sizeof(u16);
3215 if ((sublen < SDPCM_HDRLEN) ||
3216 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3217 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3218 __func__, num, sublen));
3222 if (sublen % DHD_SDALIGN) {
3223 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3224 __func__, sublen, DHD_SDALIGN));
3229 /* For last frame, adjust read len so total
3230 is a block multiple */
3233 (roundup(totlen, bus->blocksize) - totlen);
3234 totlen = roundup(totlen, bus->blocksize);
3237 /* Allocate/chain packet for next subframe */
3238 pnext = PKTGET(osh, sublen + DHD_SDALIGN, false);
3239 if (pnext == NULL) {
3240 DHD_ERROR(("%s: PKTGET failed, num %d len %d\n",
3241 __func__, num, sublen));
3244 ASSERT(!PKTLINK(pnext));
3247 pfirst = plast = pnext;
3250 PKTSETNEXT(plast, pnext);
3254 /* Adhere to start alignment requirements */
3255 PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
3258 /* If all allocations succeeded, save packet chain
3261 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3262 "subframes\n", __func__, totlen, num));
3263 if (DHD_GLOM_ON() && bus->nextlen) {
3264 if (totlen != bus->nextlen) {
3265 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3266 __func__, bus->nextlen,
3271 pfirst = pnext = NULL;
3274 PKTFREE(osh, pfirst, false);
3279 /* Done with descriptor packet */
3280 PKTFREE(osh, bus->glomd, false);
3284 dhd_os_sdunlock_rxq(bus->dhd);
3287 /* Ok -- either we just generated a packet chain,
3288 or had one from before */
3290 if (DHD_GLOM_ON()) {
3291 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3293 for (pnext = bus->glom; pnext; pnext = PKTNEXT(pnext)) {
3294 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3295 pnext, (u8 *) PKTDATA(pnext),
3296 PKTLEN(pnext), PKTLEN(pnext)));
3301 dlen = (u16) pkttotlen(osh, pfirst);
3303 /* Do an SDIO read for the superframe. Configurable iovar to
3304 * read directly into the chained packet, or allocate a large
3305 * packet and and copy into the chain.
3308 errcode = dhd_bcmsdh_recv_buf(bus,
3310 (bus->sdh), SDIO_FUNC_2,
3312 (u8 *) PKTDATA(pfirst),
3313 dlen, pfirst, NULL, NULL);
3314 } else if (bus->dataptr) {
3315 errcode = dhd_bcmsdh_recv_buf(bus,
3317 (bus->sdh), SDIO_FUNC_2,
3318 F2SYNC, bus->dataptr,
3319 dlen, NULL, NULL, NULL);
3321 (u16) pktfrombuf(osh, pfirst, 0, dlen,
3323 if (sublen != dlen) {
3324 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3325 __func__, dlen, sublen));
3330 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3335 ASSERT(errcode != BCME_PENDING);
3337 /* On failure, kill the superframe, allow a couple retries */
3339 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3340 __func__, dlen, errcode));
3341 bus->dhd->rx_errors++;
3343 if (bus->glomerr++ < 3) {
3344 dhdsdio_rxfail(bus, true, true);
3347 dhdsdio_rxfail(bus, true, false);
3348 dhd_os_sdlock_rxq(bus->dhd);
3349 PKTFREE(osh, bus->glom, false);
3350 dhd_os_sdunlock_rxq(bus->dhd);
3357 if (DHD_GLOM_ON()) {
3358 prhex("SUPERFRAME", PKTDATA(pfirst),
3359 min_t(int, PKTLEN(pfirst), 48));
3363 /* Validate the superframe header */
3364 dptr = (u8 *) PKTDATA(pfirst);
3365 sublen = ltoh16_ua(dptr);
3366 check = ltoh16_ua(dptr + sizeof(u16));
3368 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3369 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3370 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3371 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3372 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3373 __func__, bus->nextlen, seq));
3376 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3377 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3380 if ((u16)~(sublen ^ check)) {
3381 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3382 "0x%04x/0x%04x\n", __func__, sublen, check));
3384 } else if (roundup(sublen, bus->blocksize) != dlen) {
3385 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3386 "0x%04x, expect 0x%04x\n",
3388 roundup(sublen, bus->blocksize), dlen));
3390 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3391 SDPCM_GLOM_CHANNEL) {
3392 DHD_ERROR(("%s (superframe): bad channel %d\n",
3394 SDPCM_PACKET_CHANNEL(&dptr
3395 [SDPCM_FRAMETAG_LEN])));
3397 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3398 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3401 } else if ((doff < SDPCM_HDRLEN) ||
3402 (doff > (PKTLEN(pfirst) - SDPCM_HDRLEN))) {
3403 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3405 __func__, doff, sublen,
3406 PKTLEN(pfirst), SDPCM_HDRLEN));
3410 /* Check sequence number of superframe SW header */
3412 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3413 __func__, seq, rxseq));
3418 /* Check window for sanity */
3419 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3420 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3421 __func__, txmax, bus->tx_seq));
3422 txmax = bus->tx_seq + 2;
3424 bus->tx_max = txmax;
3426 /* Remove superframe header, remember offset */
3427 PKTPULL(pfirst, doff);
3430 /* Validate all the subframe headers */
3431 for (num = 0, pnext = pfirst; pnext && !errcode;
3432 num++, pnext = PKTNEXT(pnext)) {
3433 dptr = (u8 *) PKTDATA(pnext);
3434 dlen = (u16) PKTLEN(pnext);
3435 sublen = ltoh16_ua(dptr);
3436 check = ltoh16_ua(dptr + sizeof(u16));
3437 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3438 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3441 prhex("subframe", dptr, 32);
3444 if ((u16)~(sublen ^ check)) {
3445 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3446 "len/check 0x%04x/0x%04x\n",
3447 __func__, num, sublen, check));
3449 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3450 DHD_ERROR(("%s (subframe %d): length mismatch: "
3451 "len 0x%04x, expect 0x%04x\n",
3452 __func__, num, sublen, dlen));
3454 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3455 (chan != SDPCM_EVENT_CHANNEL)) {
3456 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3457 __func__, num, chan));
3459 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3460 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3461 __func__, num, doff, sublen,
3468 /* Terminate frame on error, request
3470 if (bus->glomerr++ < 3) {
3471 /* Restore superframe header space */
3472 PKTPUSH(pfirst, sfdoff);
3473 dhdsdio_rxfail(bus, true, true);
3476 dhdsdio_rxfail(bus, true, false);
3477 dhd_os_sdlock_rxq(bus->dhd);
3478 PKTFREE(osh, bus->glom, false);
3479 dhd_os_sdunlock_rxq(bus->dhd);
3487 /* Basic SD framing looks ok - process each packet (header) */
3488 save_pfirst = pfirst;
3492 dhd_os_sdlock_rxq(bus->dhd);
3493 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3494 pnext = PKTNEXT(pfirst);
3495 PKTSETNEXT(pfirst, NULL);
3497 dptr = (u8 *) PKTDATA(pfirst);
3498 sublen = ltoh16_ua(dptr);
3499 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3500 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3501 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3503 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3505 __func__, num, pfirst, PKTDATA(pfirst),
3506 PKTLEN(pfirst), sublen, chan, seq));
3508 ASSERT((chan == SDPCM_DATA_CHANNEL)
3509 || (chan == SDPCM_EVENT_CHANNEL));
3512 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3513 __func__, seq, rxseq));
3518 if (DHD_BYTES_ON() && DHD_DATA_ON())
3519 prhex("Rx Subframe Data", dptr, dlen);
3522 PKTSETLEN(pfirst, sublen);
3523 PKTPULL(pfirst, doff);
3525 if (PKTLEN(pfirst) == 0) {
3526 PKTFREE(bus->dhd->osh, pfirst, false);
3528 PKTSETNEXT(plast, pnext);
3530 ASSERT(save_pfirst == pfirst);
3531 save_pfirst = pnext;
3534 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3536 DHD_ERROR(("%s: rx protocol error\n",
3538 bus->dhd->rx_errors++;
3539 PKTFREE(osh, pfirst, false);
3541 PKTSETNEXT(plast, pnext);
3543 ASSERT(save_pfirst == pfirst);
3544 save_pfirst = pnext;
3549 /* this packet will go up, link back into
3550 chain and count it */
3551 PKTSETNEXT(pfirst, pnext);
3556 if (DHD_GLOM_ON()) {
3557 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3559 __func__, num, pfirst, PKTDATA(pfirst),
3560 PKTLEN(pfirst), PKTNEXT(pfirst),
3562 prhex("", (u8 *) PKTDATA(pfirst),
3563 min_t(int, PKTLEN(pfirst), 32));
3565 #endif /* DHD_DEBUG */
3567 dhd_os_sdunlock_rxq(bus->dhd);
3569 dhd_os_sdunlock(bus->dhd);
3570 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3571 dhd_os_sdlock(bus->dhd);
3574 bus->rxglomframes++;
3575 bus->rxglompkts += num;
3580 /* Return true if there may be more frames to read */
3581 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3583 osl_t *osh = bus->dhd->osh;
3584 bcmsdh_info_t *sdh = bus->sdh;
3586 u16 len, check; /* Extracted hardware header fields */
3587 u8 chan, seq, doff; /* Extracted software header fields */
3588 u8 fcbits; /* Extracted fcbits from software header */
3591 void *pkt; /* Packet for event or data frames */
3592 u16 pad; /* Number of pad bytes to read */
3593 u16 rdlen; /* Total number of bytes to read */
3594 u8 rxseq; /* Next sequence number to expect */
3595 uint rxleft = 0; /* Remaining number of frames allowed */
3596 int sdret; /* Return code from bcmsdh calls */
3597 u8 txmax; /* Maximum tx sequence offered */
3598 bool len_consistent; /* Result of comparing readahead len and
3602 uint rxcount = 0; /* Total frames read */
3604 #if defined(DHD_DEBUG) || defined(SDTEST)
3605 bool sdtest = false; /* To limit message spew from test mode */
3608 DHD_TRACE(("%s: Enter\n", __func__));
3613 /* Allow pktgen to override maxframes */
3614 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3615 maxframes = bus->pktgen_count;
3620 /* Not finished unless we encounter no more frames indication */
3623 for (rxseq = bus->rx_seq, rxleft = maxframes;
3624 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3625 rxseq++, rxleft--) {
3627 /* Handle glomming separately */
3628 if (bus->glom || bus->glomd) {
3630 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3631 __func__, bus->glomd, bus->glom));
3632 cnt = dhdsdio_rxglom(bus, rxseq);
3633 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3635 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3639 /* Try doing single read if we can */
3640 if (dhd_readahead && bus->nextlen) {
3641 u16 nextlen = bus->nextlen;
3644 if (bus->bus == SPI_BUS) {
3645 rdlen = len = nextlen;
3647 rdlen = len = nextlen << 4;
3649 /* Pad read to blocksize for efficiency */
3650 if (bus->roundup && bus->blocksize
3651 && (rdlen > bus->blocksize)) {
3654 (rdlen % bus->blocksize);
3655 if ((pad <= bus->roundup)
3656 && (pad < bus->blocksize)
3657 && ((rdlen + pad + firstread) <
3660 } else if (rdlen % DHD_SDALIGN) {
3662 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3666 /* We use bus->rxctl buffer in WinXP for initial
3667 * control pkt receives.
3668 * Later we use buffer-poll for data as well
3669 * as control packets.
3670 * This is required becuase dhd receives full
3671 * frame in gSPI unlike SDIO.
3672 * After the frame is received we have to
3673 * distinguish whether it is data
3674 * or non-data frame.
3676 /* Allocate a packet buffer */
3677 dhd_os_sdlock_rxq(bus->dhd);
3678 pkt = PKTGET(osh, rdlen + DHD_SDALIGN, false);
3680 if (bus->bus == SPI_BUS) {
3681 bus->usebufpool = false;
3682 bus->rxctl = bus->rxbuf;
3684 bus->rxctl += firstread;
3685 pad = ((unsigned long)bus->rxctl %
3689 (DHD_SDALIGN - pad);
3690 bus->rxctl -= firstread;
3692 ASSERT(bus->rxctl >= bus->rxbuf);
3694 /* Read the entire frame */
3695 sdret = dhd_bcmsdh_recv_buf(bus,
3704 ASSERT(sdret != BCME_PENDING);
3706 /* Control frame failures need
3709 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3712 /* dhd.rx_ctlerrs is higher */
3714 dhd_os_sdunlock_rxq(bus->dhd);
3715 dhdsdio_rxfail(bus, true,
3723 request rtx of events */
3724 DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d " "expected rxseq %d\n",
3725 __func__, len, rdlen, rxseq));
3726 /* Just go try again w/normal
3728 dhd_os_sdunlock_rxq(bus->dhd);
3732 if (bus->bus == SPI_BUS)
3733 bus->usebufpool = true;
3735 ASSERT(!PKTLINK(pkt));
3736 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
3737 rxbuf = (u8 *) PKTDATA(pkt);
3738 /* Read the entire frame */
3740 dhd_bcmsdh_recv_buf(bus,
3741 bcmsdh_cur_sbwad(sdh),
3742 SDIO_FUNC_2, F2SYNC,
3743 rxbuf, rdlen, pkt, NULL,
3746 ASSERT(sdret != BCME_PENDING);
3749 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3750 __func__, rdlen, sdret));
3751 PKTFREE(bus->dhd->osh, pkt, false);
3752 bus->dhd->rx_errors++;
3753 dhd_os_sdunlock_rxq(bus->dhd);
3754 /* Force retry w/normal header read.
3755 * Don't attemp NAK for
3758 dhdsdio_rxfail(bus, true,
3765 dhd_os_sdunlock_rxq(bus->dhd);
3767 /* Now check the header */
3768 bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
3770 /* Extract hardware header fields */
3771 len = ltoh16_ua(bus->rxhdr);
3772 check = ltoh16_ua(bus->rxhdr + sizeof(u16));
3774 /* All zeros means readahead info was bad */
3775 if (!(len | check)) {
3776 DHD_INFO(("%s (nextlen): read zeros in HW "
3777 "header???\n", __func__));
3778 dhd_os_sdlock_rxq(bus->dhd);
3780 dhd_os_sdunlock_rxq(bus->dhd);
3781 GSPI_PR55150_BAILOUT;
3785 /* Validate check bytes */
3786 if ((u16)~(len ^ check)) {
3787 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3788 __func__, nextlen, len, check));
3789 dhd_os_sdlock_rxq(bus->dhd);
3791 dhd_os_sdunlock_rxq(bus->dhd);
3793 dhdsdio_rxfail(bus, false, false);
3794 GSPI_PR55150_BAILOUT;
3798 /* Validate frame length */
3799 if (len < SDPCM_HDRLEN) {
3800 DHD_ERROR(("%s (nextlen): HW hdr length "
3801 "invalid: %d\n", __func__, len));
3802 dhd_os_sdlock_rxq(bus->dhd);
3804 dhd_os_sdunlock_rxq(bus->dhd);
3805 GSPI_PR55150_BAILOUT;
3809 /* Check for consistency withreadahead info */
3810 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3811 if (len_consistent) {
3812 /* Mismatch, force retry w/normal
3813 header (may be >4K) */
3814 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3816 len, roundup(len, 16), rxseq));
3817 dhd_os_sdlock_rxq(bus->dhd);
3819 dhd_os_sdunlock_rxq(bus->dhd);
3820 dhdsdio_rxfail(bus, true,
3822 SPI_BUS) ? false : true);
3823 GSPI_PR55150_BAILOUT;
3827 /* Extract software header fields */
3829 SDPCM_PACKET_CHANNEL(&bus->rxhdr
3830 [SDPCM_FRAMETAG_LEN]);
3832 SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3833 [SDPCM_FRAMETAG_LEN]);
3835 SDPCM_DOFFSET_VALUE(&bus->rxhdr
3836 [SDPCM_FRAMETAG_LEN]);
3838 SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3841 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3842 SDPCM_NEXTLEN_OFFSET];
3843 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3844 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3845 __func__, bus->nextlen, seq));
3849 bus->dhd->rx_readahead_cnt++;
3850 /* Handle Flow Control */
3852 SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3855 if (~bus->flowcontrol & fcbits) {
3859 if (bus->flowcontrol & ~fcbits) {
3866 bus->flowcontrol = fcbits;
3869 /* Check and update sequence number */
3871 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3872 "%d\n", __func__, seq, rxseq));
3877 /* Check window for sanity */
3878 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3879 DHD_ERROR(("%s: got unlikely tx max %d with "
3881 __func__, txmax, bus->tx_seq));
3882 txmax = bus->tx_seq + 2;
3884 bus->tx_max = txmax;
3887 if (DHD_BYTES_ON() && DHD_DATA_ON())
3888 prhex("Rx Data", rxbuf, len);
3889 else if (DHD_HDRS_ON())
3890 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3893 if (chan == SDPCM_CONTROL_CHANNEL) {
3894 if (bus->bus == SPI_BUS) {
3895 dhdsdio_read_control(bus, rxbuf, len,
3897 if (bus->usebufpool) {
3898 dhd_os_sdlock_rxq(bus->dhd);
3899 PKTFREE(bus->dhd->osh, pkt,
3901 dhd_os_sdunlock_rxq(bus->dhd);
3905 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3907 /* Force retry w/normal header read */
3909 dhdsdio_rxfail(bus, false, true);
3910 dhd_os_sdlock_rxq(bus->dhd);
3912 dhd_os_sdunlock_rxq(bus->dhd);
3917 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3918 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3923 /* Validate data offset */
3924 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3925 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3926 __func__, doff, len, SDPCM_HDRLEN));
3927 dhd_os_sdlock_rxq(bus->dhd);
3929 dhd_os_sdunlock_rxq(bus->dhd);
3931 dhdsdio_rxfail(bus, false, false);
3935 /* All done with this one -- now deliver the packet */
3938 /* gSPI frames should not be handled in fractions */
3939 if (bus->bus == SPI_BUS)
3942 /* Read frame header (hardware and software) */
3944 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3945 F2SYNC, bus->rxhdr, firstread, NULL,
3948 ASSERT(sdret != BCME_PENDING);
3951 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3954 dhdsdio_rxfail(bus, true, true);
3958 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3959 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3962 /* Extract hardware header fields */
3963 len = ltoh16_ua(bus->rxhdr);
3964 check = ltoh16_ua(bus->rxhdr + sizeof(u16));
3966 /* All zeros means no more frames */
3967 if (!(len | check)) {
3972 /* Validate check bytes */
3973 if ((u16) ~(len ^ check)) {
3974 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3975 __func__, len, check));
3977 dhdsdio_rxfail(bus, false, false);
3981 /* Validate frame length */
3982 if (len < SDPCM_HDRLEN) {
3983 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3988 /* Extract software header fields */
3989 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3990 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3991 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3992 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3994 /* Validate data offset */
3995 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3996 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
3998 __func__, doff, len, SDPCM_HDRLEN, seq));
4001 dhdsdio_rxfail(bus, false, false);
4005 /* Save the readahead length if there is one */
4007 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4008 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4009 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4011 __func__, bus->nextlen, seq));
4015 /* Handle Flow Control */
4016 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4019 if (~bus->flowcontrol & fcbits) {
4023 if (bus->flowcontrol & ~fcbits) {
4030 bus->flowcontrol = fcbits;
4033 /* Check and update sequence number */
4035 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4041 /* Check window for sanity */
4042 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4043 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4044 __func__, txmax, bus->tx_seq));
4045 txmax = bus->tx_seq + 2;
4047 bus->tx_max = txmax;
4049 /* Call a separate function for control frames */
4050 if (chan == SDPCM_CONTROL_CHANNEL) {
4051 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4055 ASSERT((chan == SDPCM_DATA_CHANNEL)
4056 || (chan == SDPCM_EVENT_CHANNEL)
4057 || (chan == SDPCM_TEST_CHANNEL)
4058 || (chan == SDPCM_GLOM_CHANNEL));
4060 /* Length to read */
4061 rdlen = (len > firstread) ? (len - firstread) : 0;
4063 /* May pad read to blocksize for efficiency */
4064 if (bus->roundup && bus->blocksize &&
4065 (rdlen > bus->blocksize)) {
4066 pad = bus->blocksize - (rdlen % bus->blocksize);
4067 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4068 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4070 } else if (rdlen % DHD_SDALIGN) {
4071 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4074 /* Satisfy length-alignment requirements */
4075 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4076 rdlen = roundup(rdlen, ALIGNMENT);
4078 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4079 /* Too long -- skip this frame */
4080 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4081 __func__, len, rdlen));
4082 bus->dhd->rx_errors++;
4084 dhdsdio_rxfail(bus, false, false);
4088 dhd_os_sdlock_rxq(bus->dhd);
4089 pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), false);
4091 /* Give up on data, request rtx of events */
4092 DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n",
4093 __func__, rdlen, chan));
4094 bus->dhd->rx_dropped++;
4095 dhd_os_sdunlock_rxq(bus->dhd);
4096 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4099 dhd_os_sdunlock_rxq(bus->dhd);
4101 ASSERT(!PKTLINK(pkt));
4103 /* Leave room for what we already read, and align remainder */
4104 ASSERT(firstread < (PKTLEN(pkt)));
4105 PKTPULL(pkt, firstread);
4106 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
4108 /* Read the remaining frame data */
4110 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4111 F2SYNC, ((u8 *) PKTDATA(pkt)), rdlen,
4114 ASSERT(sdret != BCME_PENDING);
4117 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4120 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4122 ? "data" : "test")),
4124 dhd_os_sdlock_rxq(bus->dhd);
4125 PKTFREE(bus->dhd->osh, pkt, false);
4126 dhd_os_sdunlock_rxq(bus->dhd);
4127 bus->dhd->rx_errors++;
4128 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4132 /* Copy the already-read portion */
4133 PKTPUSH(pkt, firstread);
4134 bcopy(bus->rxhdr, PKTDATA(pkt), firstread);
4137 if (DHD_BYTES_ON() && DHD_DATA_ON())
4138 prhex("Rx Data", PKTDATA(pkt), len);
4142 /* Save superframe descriptor and allocate packet frame */
4143 if (chan == SDPCM_GLOM_CHANNEL) {
4144 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4145 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4148 if (DHD_GLOM_ON()) {
4149 prhex("Glom Data", PKTDATA(pkt), len);
4152 PKTSETLEN(pkt, len);
4153 ASSERT(doff == SDPCM_HDRLEN);
4154 PKTPULL(pkt, SDPCM_HDRLEN);
4157 DHD_ERROR(("%s: glom superframe w/o "
4158 "descriptor!\n", __func__));
4159 dhdsdio_rxfail(bus, false, false);
4164 /* Fill in packet len and prio, deliver upward */
4165 PKTSETLEN(pkt, len);
4169 /* Test channel packets are processed separately */
4170 if (chan == SDPCM_TEST_CHANNEL) {
4171 dhdsdio_testrcv(bus, pkt, seq);
4176 if (PKTLEN(pkt) == 0) {
4177 dhd_os_sdlock_rxq(bus->dhd);
4178 PKTFREE(bus->dhd->osh, pkt, false);
4179 dhd_os_sdunlock_rxq(bus->dhd);
4181 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4182 DHD_ERROR(("%s: rx protocol error\n", __func__));
4183 dhd_os_sdlock_rxq(bus->dhd);
4184 PKTFREE(bus->dhd->osh, pkt, false);
4185 dhd_os_sdunlock_rxq(bus->dhd);
4186 bus->dhd->rx_errors++;
4190 /* Unlock during rx call */
4191 dhd_os_sdunlock(bus->dhd);
4192 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4193 dhd_os_sdlock(bus->dhd);
4195 rxcount = maxframes - rxleft;
4197 /* Message if we hit the limit */
4198 if (!rxleft && !sdtest)
4199 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4202 #endif /* DHD_DEBUG */
4203 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4204 /* Back off rxseq if awaiting rtx, update rx_seq */
4207 bus->rx_seq = rxseq;
4212 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4214 sdpcmd_regs_t *regs = bus->regs;
4220 DHD_TRACE(("%s: Enter\n", __func__));
4222 /* Read mailbox data and ack that we did so */
4223 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4224 if (retries <= retry_limit)
4225 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4226 bus->f1regdata += 2;
4228 /* Dongle recomposed rx frames, accept them again */
4229 if (hmb_data & HMB_DATA_NAKHANDLED) {
4230 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4233 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4235 bus->rxskip = false;
4236 intstatus |= I_HMB_FRAME_IND;
4240 * DEVREADY does not occur with gSPI.
4242 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4244 (hmb_data & HMB_DATA_VERSION_MASK) >>
4245 HMB_DATA_VERSION_SHIFT;
4246 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4247 DHD_ERROR(("Version mismatch, dongle reports %d, "
4249 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4251 DHD_INFO(("Dongle ready, protocol version %d\n",
4256 * Flow Control has been moved into the RX headers and this out of band
4257 * method isn't used any more. Leae this here for possibly
4258 * remaining backward
4259 * compatible with older dongles
4261 if (hmb_data & HMB_DATA_FC) {
4263 (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4265 if (fcbits & ~bus->flowcontrol)
4267 if (bus->flowcontrol & ~fcbits)
4271 bus->flowcontrol = fcbits;
4274 /* Shouldn't be any others */
4275 if (hmb_data & ~(HMB_DATA_DEVREADY |
4276 HMB_DATA_NAKHANDLED |
4279 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4280 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4286 bool dhdsdio_dpc(dhd_bus_t *bus)
4288 bcmsdh_info_t *sdh = bus->sdh;
4289 sdpcmd_regs_t *regs = bus->regs;
4290 u32 intstatus, newstatus = 0;
4292 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4293 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4294 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4295 bool rxdone = true; /* Flag for no more read data */
4296 bool resched = false; /* Flag indicating resched wanted */
4298 DHD_TRACE(("%s: Enter\n", __func__));
4300 /* Start with leftover status bits */
4301 intstatus = bus->intstatus;
4303 dhd_os_sdlock(bus->dhd);
4305 /* If waiting for HTAVAIL, check status */
4306 if (bus->clkstate == CLK_PENDING) {
4308 u8 clkctl, devctl = 0;
4311 /* Check for inconsistent device control */
4313 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4315 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4317 bus->dhd->busstate = DHD_BUS_DOWN;
4319 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4321 #endif /* DHD_DEBUG */
4323 /* Read CSR, if clock on switch to AVAIL, else ignore */
4325 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4328 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4330 bus->dhd->busstate = DHD_BUS_DOWN;
4333 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4336 if (SBSDIO_HTAV(clkctl)) {
4338 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4341 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4343 bus->dhd->busstate = DHD_BUS_DOWN;
4345 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4346 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4349 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4351 bus->dhd->busstate = DHD_BUS_DOWN;
4353 bus->clkstate = CLK_AVAIL;
4361 /* Make sure backplane clock is on */
4362 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4363 if (bus->clkstate == CLK_PENDING)
4366 /* Pending interrupt indicates new device status */
4369 R_SDREG(newstatus, ®s->intstatus, retries);
4371 if (bcmsdh_regfail(bus->sdh))
4373 newstatus &= bus->hostintmask;
4374 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4376 W_SDREG(newstatus, ®s->intstatus, retries);
4381 /* Merge new bits with previous */
4382 intstatus |= newstatus;
4385 /* Handle flow-control change: read new state in case our ack
4386 * crossed another change interrupt. If change still set, assume
4387 * FC ON for safety, let next loop through do the debounce.
4389 if (intstatus & I_HMB_FC_CHANGE) {
4390 intstatus &= ~I_HMB_FC_CHANGE;
4391 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4392 R_SDREG(newstatus, ®s->intstatus, retries);
4393 bus->f1regdata += 2;
4395 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4396 intstatus |= (newstatus & bus->hostintmask);
4399 /* Handle host mailbox indication */
4400 if (intstatus & I_HMB_HOST_INT) {
4401 intstatus &= ~I_HMB_HOST_INT;
4402 intstatus |= dhdsdio_hostmail(bus);
4405 /* Generally don't ask for these, can get CRC errors... */
4406 if (intstatus & I_WR_OOSYNC) {
4407 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4408 intstatus &= ~I_WR_OOSYNC;
4411 if (intstatus & I_RD_OOSYNC) {
4412 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4413 intstatus &= ~I_RD_OOSYNC;
4416 if (intstatus & I_SBINT) {
4417 DHD_ERROR(("Dongle reports SBINT\n"));
4418 intstatus &= ~I_SBINT;
4421 /* Would be active due to wake-wlan in gSPI */
4422 if (intstatus & I_CHIPACTIVE) {
4423 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4424 intstatus &= ~I_CHIPACTIVE;
4427 /* Ignore frame indications if rxskip is set */
4429 intstatus &= ~I_HMB_FRAME_IND;
4431 /* On frame indication, read available frames */
4432 if (PKT_AVAILABLE()) {
4433 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4434 if (rxdone || bus->rxskip)
4435 intstatus &= ~I_HMB_FRAME_IND;
4436 rxlimit -= min(framecnt, rxlimit);
4439 /* Keep still-pending events for next scheduling */
4440 bus->intstatus = intstatus;
4443 #if defined(OOB_INTR_ONLY)
4444 bcmsdh_oob_intr_set(1);
4445 #endif /* (OOB_INTR_ONLY) */
4446 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4447 * or clock availability. (Allows tx loop to check ipend if desired.)
4448 * (Unless register access seems hosed, as we may not be able to ACK...)
4450 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4451 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4452 __func__, rxdone, framecnt));
4453 bus->intdis = false;
4454 bcmsdh_intr_enable(sdh);
4457 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4458 (bus->clkstate == CLK_AVAIL)) {
4462 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4463 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4464 (u32) bus->ctrl_frame_len, NULL,
4466 ASSERT(ret != BCME_PENDING);
4469 /* On failure, abort the command and
4470 terminate the frame */
4471 DHD_INFO(("%s: sdio error %d, abort command and "
4472 "terminate frame.\n", __func__, ret));
4475 bcmsdh_abort(sdh, SDIO_FUNC_2);
4477 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4478 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4482 for (i = 0; i < 3; i++) {
4484 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4485 SBSDIO_FUNC1_WFRAMEBCHI,
4487 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4488 SBSDIO_FUNC1_WFRAMEBCLO,
4490 bus->f1regdata += 2;
4491 if ((hi == 0) && (lo == 0))
4497 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4499 printf("Return_dpc value is : %d\n", ret);
4500 bus->ctrl_frame_stat = false;
4501 dhd_wait_event_wakeup(bus->dhd);
4503 /* Send queued frames (limit 1 if rx may still be pending) */
4504 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4505 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4507 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4508 framecnt = dhdsdio_sendfromq(bus, framecnt);
4509 txlimit -= framecnt;
4512 /* Resched if events or tx frames are pending,
4513 else await next interrupt */
4514 /* On failed register access, all bets are off:
4515 no resched or interrupts */
4516 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4517 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4518 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4519 bus->dhd->busstate = DHD_BUS_DOWN;
4521 } else if (bus->clkstate == CLK_PENDING) {
4522 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4523 "I_CHIPACTIVE interrupt\n", __func__));
4525 } else if (bus->intstatus || bus->ipend ||
4526 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4527 DATAOK(bus)) || PKT_AVAILABLE()) {
4531 bus->dpc_sched = resched;
4533 /* If we're done for now, turn off clock request. */
4534 if ((bus->clkstate != CLK_PENDING)
4535 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4536 bus->activity = false;
4537 dhdsdio_clkctl(bus, CLK_NONE, false);
4540 dhd_os_sdunlock(bus->dhd);
4545 bool dhd_bus_dpc(struct dhd_bus *bus)
4549 /* Call the DPC directly. */
4550 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4551 resched = dhdsdio_dpc(bus);
4556 void dhdsdio_isr(void *arg)
4558 dhd_bus_t *bus = (dhd_bus_t *) arg;
4561 DHD_TRACE(("%s: Enter\n", __func__));
4564 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4569 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4570 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4574 /* Count the interrupt call */
4578 /* Shouldn't get this interrupt if we're sleeping? */
4579 if (bus->sleeping) {
4580 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4584 /* Disable additional interrupts (is this needed now)? */
4586 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4588 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4590 bcmsdh_intr_disable(sdh);
4593 #if defined(SDIO_ISR_THREAD)
4594 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4595 while (dhdsdio_dpc(bus))
4598 bus->dpc_sched = true;
4599 dhd_sched_dpc(bus->dhd);
4605 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4607 /* Default to specified length, or full range */
4608 if (dhd_pktgen_len) {
4609 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4610 bus->pktgen_minlen = bus->pktgen_maxlen;
4612 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4613 bus->pktgen_minlen = 0;
4615 bus->pktgen_len = (u16) bus->pktgen_minlen;
4617 /* Default to per-watchdog burst with 10s print time */
4618 bus->pktgen_freq = 1;
4619 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4620 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4622 /* Default to echo mode */
4623 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4624 bus->pktgen_stop = 1;
4627 static void dhdsdio_pktgen(dhd_bus_t *bus)
4633 osl_t *osh = bus->dhd->osh;
4636 /* Display current count if appropriate */
4637 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4638 bus->pktgen_ptick = 0;
4639 printf("%s: send attempts %d rcvd %d\n",
4640 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4643 /* For recv mode, just make sure dongle has started sending */
4644 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4645 if (!bus->pktgen_rcvd)
4646 dhdsdio_sdtest_set(bus, true);
4650 /* Otherwise, generate or request the specified number of packets */
4651 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4652 /* Stop if total has been reached */
4653 if (bus->pktgen_total
4654 && (bus->pktgen_sent >= bus->pktgen_total)) {
4655 bus->pktgen_count = 0;
4659 /* Allocate an appropriate-sized packet */
4660 len = bus->pktgen_len;
4662 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4665 DHD_ERROR(("%s: PKTGET failed!\n", __func__));
4668 PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4670 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4672 /* Write test header cmd and extra based on mode */
4673 switch (bus->pktgen_mode) {
4674 case DHD_PKTGEN_ECHO:
4675 *data++ = SDPCM_TEST_ECHOREQ;
4676 *data++ = (u8) bus->pktgen_sent;
4679 case DHD_PKTGEN_SEND:
4680 *data++ = SDPCM_TEST_DISCARD;
4681 *data++ = (u8) bus->pktgen_sent;
4684 case DHD_PKTGEN_RXBURST:
4685 *data++ = SDPCM_TEST_BURST;
4686 *data++ = (u8) bus->pktgen_count;
4690 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4692 PKTFREE(osh, pkt, true);
4693 bus->pktgen_count = 0;
4697 /* Write test header length field */
4698 *data++ = (len >> 0);
4699 *data++ = (len >> 8);
4701 /* Then fill in the remainder -- N/A for burst,
4703 for (fillbyte = 0; fillbyte < len; fillbyte++)
4705 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4708 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4709 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4710 prhex("dhdsdio_pktgen: Tx Data", data,
4711 PKTLEN(pkt) - SDPCM_HDRLEN);
4716 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4718 if (bus->pktgen_stop
4719 && bus->pktgen_stop == bus->pktgen_fail)
4720 bus->pktgen_count = 0;
4724 /* Bump length if not fixed, wrap at max */
4725 if (++bus->pktgen_len > bus->pktgen_maxlen)
4726 bus->pktgen_len = (u16) bus->pktgen_minlen;
4728 /* Special case for burst mode: just send one request! */
4729 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4734 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4738 osl_t *osh = bus->dhd->osh;
4740 /* Allocate the packet */
4741 pkt = PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4744 DHD_ERROR(("%s: PKTGET failed!\n", __func__));
4747 PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4748 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4750 /* Fill in the test header */
4751 *data++ = SDPCM_TEST_SEND;
4753 *data++ = (bus->pktgen_maxlen >> 0);
4754 *data++ = (bus->pktgen_maxlen >> 8);
4757 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4761 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq)
4763 osl_t *osh = bus->dhd->osh;
4772 /* Check for min length */
4773 pktlen = PKTLEN(pkt);
4774 if (pktlen < SDPCM_TEST_HDRLEN) {
4775 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4777 PKTFREE(osh, pkt, false);
4781 /* Extract header fields */
4782 data = PKTDATA(pkt);
4786 len += *data++ << 8;
4788 /* Check length for relevant commands */
4789 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4790 || cmd == SDPCM_TEST_ECHORSP) {
4791 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4792 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4793 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4794 pktlen, seq, cmd, extra, len));
4795 PKTFREE(osh, pkt, false);
4800 /* Process as per command */
4802 case SDPCM_TEST_ECHOREQ:
4803 /* Rx->Tx turnaround ok (even on NDIS w/current
4805 *(u8 *) (PKTDATA(pkt)) = SDPCM_TEST_ECHORSP;
4806 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4810 PKTFREE(osh, pkt, false);
4815 case SDPCM_TEST_ECHORSP:
4816 if (bus->ext_loop) {
4817 PKTFREE(osh, pkt, false);
4822 for (offset = 0; offset < len; offset++, data++) {
4823 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4824 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4826 SDPCM_TEST_FILL(offset, extra), *data));
4830 PKTFREE(osh, pkt, false);
4834 case SDPCM_TEST_DISCARD:
4835 PKTFREE(osh, pkt, false);
4839 case SDPCM_TEST_BURST:
4840 case SDPCM_TEST_SEND:
4842 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4843 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4844 pktlen, seq, cmd, extra, len));
4845 PKTFREE(osh, pkt, false);
4849 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4850 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4851 if (bus->pktgen_total
4852 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4853 bus->pktgen_count = 0;
4854 dhdsdio_sdtest_set(bus, false);
4860 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4864 DHD_TIMER(("%s: Enter\n", __func__));
4868 if (bus->dhd->dongle_reset)
4871 /* Ignore the timer if simulating bus down */
4875 dhd_os_sdlock(bus->dhd);
4877 /* Poll period: check device if appropriate. */
4878 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4881 /* Reset poll tick */
4884 /* Check device if no interrupts */
4885 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4887 if (!bus->dpc_sched) {
4889 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4893 devpend & (INTR_STATUS_FUNC1 |
4897 /* If there is something, make like the ISR and
4903 bcmsdh_intr_disable(bus->sdh);
4905 bus->dpc_sched = true;
4906 dhd_sched_dpc(bus->dhd);
4911 /* Update interrupt tracking */
4912 bus->lastintrs = bus->intrcount;
4915 /* Poll for console output periodically */
4916 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4917 bus->console.count += dhd_watchdog_ms;
4918 if (bus->console.count >= dhd_console_ms) {
4919 bus->console.count -= dhd_console_ms;
4920 /* Make sure backplane clock is on */
4921 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4922 if (dhdsdio_readconsole(bus) < 0)
4923 dhd_console_ms = 0; /* On error,
4927 #endif /* DHD_DEBUG */
4930 /* Generate packets if configured */
4931 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4932 /* Make sure backplane clock is on */
4933 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4934 bus->pktgen_tick = 0;
4935 dhdsdio_pktgen(bus);
4939 /* On idle timeout clear activity flag and/or turn off clock */
4940 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4941 if (++bus->idlecount >= bus->idletime) {
4943 if (bus->activity) {
4944 bus->activity = false;
4945 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4947 dhdsdio_clkctl(bus, CLK_NONE, false);
4952 dhd_os_sdunlock(bus->dhd);
4958 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4960 dhd_bus_t *bus = dhdp->bus;
4965 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4966 if (bus->console_addr == 0)
4967 return BCME_UNSUPPORTED;
4969 /* Exclusive bus access */
4970 dhd_os_sdlock(bus->dhd);
4972 /* Don't allow input if dongle is in reset */
4973 if (bus->dhd->dongle_reset) {
4974 dhd_os_sdunlock(bus->dhd);
4975 return BCME_NOTREADY;
4978 /* Request clock to allow SDIO accesses */
4980 /* No pend allowed since txpkt is called later, ht clk has to be on */
4981 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4983 /* Zero cbuf_index */
4984 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf_idx);
4986 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4990 /* Write message into cbuf */
4991 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf);
4992 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
4996 /* Write length into vcons_in */
4997 addr = bus->console_addr + offsetof(hndrte_cons_t, vcons_in);
4998 val = htol32(msglen);
4999 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5003 /* Bump dongle by sending an empty event pkt.
5004 * sdpcm_sendup (RX) checks for virtual console input.
5006 pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, true);
5007 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5008 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5011 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5012 bus->activity = false;
5013 dhdsdio_clkctl(bus, CLK_NONE, true);
5016 dhd_os_sdunlock(bus->dhd);
5020 #endif /* DHD_DEBUG */
5023 static void dhd_dump_cis(uint fn, u8 *cis)
5025 uint byte, tag, tdata;
5026 DHD_INFO(("Function %d CIS:\n", fn));
5028 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5029 if ((byte % 16) == 0)
5031 DHD_INFO(("%02x ", cis[byte]));
5032 if ((byte % 16) == 15)
5040 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5041 tdata = cis[byte + 1] + 1;
5046 if ((byte % 16) != 15)
5049 #endif /* DHD_DEBUG */
5051 static bool dhdsdio_chipmatch(u16 chipid)
5053 if (chipid == BCM4325_CHIP_ID)
5055 if (chipid == BCM4329_CHIP_ID)
5057 if (chipid == BCM4319_CHIP_ID)
5062 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5063 u16 slot, u16 func, uint bustype, void *regsva,
5064 osl_t *osh, void *sdh)
5069 /* Init global variables at run-time, not as part of the declaration.
5070 * This is required to support init/de-init of the driver.
5072 * of globals as part of the declaration results in non-deterministic
5073 * behavior since the value of the globals may be different on the
5074 * first time that the driver is initialized vs subsequent
5077 dhd_txbound = DHD_TXBOUND;
5078 dhd_rxbound = DHD_RXBOUND;
5079 dhd_alignctl = true;
5081 dhd_readahead = true;
5084 dhd_dongle_memsize = 0;
5085 dhd_txminmax = DHD_TXMINMAX;
5091 DHD_TRACE(("%s: Enter\n", __func__));
5092 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5094 /* We make assumptions about address window mappings */
5095 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5097 /* BCMSDH passes venid and devid based on CIS parsing -- but
5099 * means early parse could fail, so here we should get either an ID
5100 * we recognize OR (-1) indicating we must request power first.
5102 /* Check the Vendor ID */
5105 case VENDOR_BROADCOM:
5108 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5112 /* Check the Device ID and make sure it's one that we support */
5114 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5115 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5116 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5117 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5119 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5120 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5121 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5123 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5125 case BCM4319_D11N_ID: /* 4319 802.11n id */
5126 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5127 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5128 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5131 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5136 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5137 __func__, venid, devid));
5142 /* Ask the OS interface part for an OSL handle */
5143 osh = dhd_osl_attach(sdh, DHD_BUS);
5145 DHD_ERROR(("%s: osl_attach failed!\n", __func__));
5150 /* Allocate private bus interface state */
5151 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5153 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5157 bus->cl_devid = (u16) devid;
5159 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5160 bus->usebufpool = false; /* Use bufpool if allocated,
5161 else use locally malloced rxbuf */
5163 /* attempt to attach to the dongle */
5164 if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
5165 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5169 /* Attach to the dhd/OS/network interface */
5170 bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE);
5172 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5176 /* Allocate buffers */
5177 if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
5178 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5182 if (!(dhdsdio_probe_init(bus, osh, sdh))) {
5183 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5187 /* Register interrupt callback, but mask it (not operational yet). */
5188 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5190 bcmsdh_intr_disable(sdh);
5191 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5193 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5197 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5199 DHD_INFO(("%s: completed!!\n", __func__));
5201 /* if firmware path present try to download and bring up bus */
5202 ret = dhd_bus_start(bus->dhd);
5204 if (ret == BCME_NOTUP) {
5205 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5209 /* Ok, have the per-port tell the stack we're open for business */
5210 if (dhd_net_attach(bus->dhd, 0) != 0) {
5211 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5218 dhdsdio_release(bus, osh);
5223 dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
5229 bus->alp_only = true;
5231 /* Return the window to backplane enumeration space for core access */
5232 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5233 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5236 printf("F1 signature read @0x18000000=0x%4x\n",
5237 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5239 #endif /* DHD_DEBUG */
5241 /* Force PLL off until si_attach() programs PLL control regs */
5243 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5244 DHD_INIT_CLKCTL1, &err);
5247 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5250 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5251 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5252 "0x%02x read 0x%02x\n",
5253 err, DHD_INIT_CLKCTL1, clkctl));
5257 if (DHD_INFO_ON()) {
5259 u8 *cis[SDIOD_MAX_IOFUNCS];
5262 numfn = bcmsdh_query_iofnum(sdh);
5263 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5265 /* Make sure ALP is available before trying to read CIS */
5266 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5267 SBSDIO_FUNC1_CHIPCLKCSR,
5269 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5271 /* Now request ALP be put on the bus */
5272 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5273 DHD_INIT_CLKCTL2, &err);
5276 for (fn = 0; fn <= numfn; fn++) {
5277 cis[fn] = kmalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5279 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5283 bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5285 err = bcmsdh_cis_read(sdh, fn, cis[fn],
5286 SBSDIO_CIS_SIZE_LIMIT);
5288 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5289 "err %d\n", fn, err));
5293 dhd_dump_cis(fn, cis[fn]);
5302 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5306 #endif /* DHD_DEBUG */
5308 /* si_attach() will provide an SI handle and scan the backplane */
5309 bus->sih = si_attach((uint) devid, osh, regsva, DHD_BUS, sdh,
5310 &bus->vars, &bus->varsz);
5312 DHD_ERROR(("%s: si_attach failed!\n", __func__));
5316 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5318 if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
5319 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5320 __func__, bus->sih->chip));
5324 si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
5326 /* Get info on the ARM and SOCRAM cores... */
5327 if (!DHD_NOPMU(bus)) {
5328 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5329 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5330 bus->armrev = si_corerev(bus->sih);
5332 DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5335 bus->orig_ramsize = si_socram_size(bus->sih);
5336 if (!(bus->orig_ramsize)) {
5337 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5341 bus->ramsize = bus->orig_ramsize;
5342 if (dhd_dongle_memsize)
5343 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5345 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5346 bus->ramsize, bus->orig_ramsize));
5349 /* ...but normally deal with the SDPCMDEV core */
5350 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
5352 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5354 DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5359 bus->sdpcmrev = si_corerev(bus->sih);
5361 /* Set core control so an SDIO reset does a backplane reset */
5362 OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
5364 pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
5366 /* Locate an appropriately-aligned portion of hdrbuf */
5367 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5369 /* Set the poll and/or interrupt flags */
5370 bus->intr = (bool) dhd_intr;
5371 bus->poll = (bool) dhd_poll;
5381 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh)
5383 DHD_TRACE(("%s: Enter\n", __func__));
5385 if (bus->dhd->maxctl) {
5387 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5388 ALIGNMENT) + DHD_SDALIGN;
5389 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5390 if (!(bus->rxbuf)) {
5391 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5392 __func__, bus->rxblen));
5397 /* Allocate buffer to receive glomed packet */
5398 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5399 if (!(bus->databuf)) {
5400 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5401 __func__, MAX_DATA_BUF));
5402 /* release rxbuf which was already located as above */
5408 /* Align the buffer */
5409 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5411 bus->databuf + (DHD_SDALIGN -
5412 ((unsigned long)bus->databuf % DHD_SDALIGN));
5414 bus->dataptr = bus->databuf;
5422 static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh)
5426 DHD_TRACE(("%s: Enter\n", __func__));
5429 dhdsdio_pktgen_init(bus);
5432 /* Disable F2 to clear any intermediate frame state on the dongle */
5433 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5436 bus->dhd->busstate = DHD_BUS_DOWN;
5437 bus->sleeping = false;
5438 bus->rxflow = false;
5439 bus->prev_rxlim_hit = 0;
5441 /* Done with backplane-dependent accesses, can drop clock... */
5442 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5444 /* ...and initialize clock/power states */
5445 bus->clkstate = CLK_SDONLY;
5446 bus->idletime = (s32) dhd_idletime;
5447 bus->idleclock = DHD_IDLE_ACTIVE;
5449 /* Query the SD clock speed */
5450 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5451 &bus->sd_divisor, sizeof(s32),
5452 false) != BCME_OK) {
5453 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5454 bus->sd_divisor = -1;
5456 DHD_INFO(("%s: Initial value for %s is %d\n",
5457 __func__, "sd_divisor", bus->sd_divisor));
5460 /* Query the SD bus mode */
5461 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5462 &bus->sd_mode, sizeof(s32), false) != BCME_OK) {
5463 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5466 DHD_INFO(("%s: Initial value for %s is %d\n",
5467 __func__, "sd_mode", bus->sd_mode));
5470 /* Query the F2 block size, set roundup accordingly */
5472 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5473 &bus->blocksize, sizeof(s32), false) != BCME_OK) {
5475 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5477 DHD_INFO(("%s: Initial value for %s is %d\n",
5478 __func__, "sd_blocksize", bus->blocksize));
5480 bus->roundup = min(max_roundup, bus->blocksize);
5482 /* Query if bus module supports packet chaining,
5483 default to use if supported */
5484 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5485 &bus->sd_rxchain, sizeof(s32),
5486 false) != BCME_OK) {
5487 bus->sd_rxchain = false;
5489 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5491 (bus->sd_rxchain ? "supports" : "does not support")));
5493 bus->use_rxchain = (bool) bus->sd_rxchain;
5499 dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
5500 char *fw_path, char *nv_path)
5503 bus->fw_path = fw_path;
5504 bus->nv_path = nv_path;
5506 ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
5512 dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh)
5516 /* Download the firmware */
5517 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5519 ret = _dhdsdio_download_firmware(bus) == 0;
5521 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5526 /* Detach and free everything */
5527 static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh)
5529 DHD_TRACE(("%s: Enter\n", __func__));
5534 /* De-register interrupt handler */
5535 bcmsdh_intr_disable(bus->sdh);
5536 bcmsdh_intr_dereg(bus->sdh);
5540 dhdsdio_release_dongle(bus, osh);
5542 dhd_detach(bus->dhd);
5546 dhdsdio_release_malloc(bus, osh);
5552 dhd_osl_detach(osh);
5554 DHD_TRACE(("%s: Disconnected\n", __func__));
5557 static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh)
5559 DHD_TRACE(("%s: Enter\n", __func__));
5561 if (bus->dhd && bus->dhd->dongle_reset)
5566 bus->rxctl = bus->rxbuf = NULL;
5571 kfree(bus->databuf);
5572 bus->databuf = NULL;
5576 static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh)
5578 DHD_TRACE(("%s: Enter\n", __func__));
5580 if (bus->dhd && bus->dhd->dongle_reset)
5584 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5585 #if !defined(BCMLXSDMMC)
5586 si_watchdog(bus->sih, 4);
5587 #endif /* !defined(BCMLXSDMMC) */
5588 dhdsdio_clkctl(bus, CLK_NONE, false);
5589 si_detach(bus->sih);
5590 if (bus->vars && bus->varsz)
5595 DHD_TRACE(("%s: Disconnected\n", __func__));
5598 static void dhdsdio_disconnect(void *ptr)
5600 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5602 DHD_TRACE(("%s: Enter\n", __func__));
5606 dhdsdio_release(bus, bus->dhd->osh);
5609 DHD_TRACE(("%s: Disconnected\n", __func__));
5612 /* Register/Unregister functions are called by the main DHD entry
5613 * point (e.g. module insertion) to link with the bus driver, in
5614 * order to look for or await the device.
5617 static bcmsdh_driver_t dhd_sdio = {
5622 int dhd_bus_register(void)
5624 DHD_TRACE(("%s: Enter\n", __func__));
5626 return bcmsdh_register(&dhd_sdio);
5629 void dhd_bus_unregister(void)
5631 DHD_TRACE(("%s: Enter\n", __func__));
5633 bcmsdh_unregister();
5636 #ifdef BCMEMBEDIMAGE
5637 static int dhdsdio_download_code_array(struct dhd_bus *bus)
5642 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5644 /* Download image */
5645 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5647 dhdsdio_membytes(bus, true, offset, dlarray + offset,
5650 DHD_ERROR(("%s: error %d on writing %d membytes at "
5652 __func__, bcmerror, MEMBLOCK, offset));
5659 if (offset < sizeof(dlarray)) {
5660 bcmerror = dhdsdio_membytes(bus, true, offset,
5662 sizeof(dlarray) - offset);
5664 DHD_ERROR(("%s: error %d on writing %d membytes at "
5665 "0x%08x\n", __func__, bcmerror,
5666 sizeof(dlarray) - offset, offset));
5671 /* Upload and compare the downloaded code */
5673 unsigned char *ularray;
5675 ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
5676 /* Upload image to verify downloaded contents. */
5678 memset(ularray, 0xaa, bus->ramsize);
5679 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5681 dhdsdio_membytes(bus, false, offset,
5682 ularray + offset, MEMBLOCK);
5684 DHD_ERROR(("%s: error %d on reading %d membytes"
5686 __func__, bcmerror, MEMBLOCK, offset));
5693 if (offset < sizeof(dlarray)) {
5694 bcmerror = dhdsdio_membytes(bus, false, offset,
5696 sizeof(dlarray) - offset);
5698 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5700 sizeof(dlarray) - offset, offset));
5705 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5706 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5711 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5716 #endif /* DHD_DEBUG */
5721 #endif /* BCMEMBEDIMAGE */
5723 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5729 u8 *memblock = NULL, *memptr;
5731 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5733 image = dhd_os_open_image(fw_path);
5737 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5738 if (memblock == NULL) {
5739 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5740 __func__, MEMBLOCK));
5743 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5745 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5747 /* Download image */
5749 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5750 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5752 DHD_ERROR(("%s: error %d on writing %d membytes at "
5753 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5765 dhd_os_close_image(image);
5771 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5772 * and ending in a NUL.
5773 * Removes carriage returns, empty lines, comment lines, and converts
5775 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5779 static uint process_nvram_vars(char *varbuf, uint len)
5788 findNewline = false;
5791 for (n = 0; n < len; n++) {
5794 if (varbuf[n] == '\r')
5796 if (findNewline && varbuf[n] != '\n')
5798 findNewline = false;
5799 if (varbuf[n] == '#') {
5803 if (varbuf[n] == '\n') {
5813 buf_len = dp - varbuf;
5815 while (dp < varbuf + n)
5822 EXAMPLE: nvram_array
5825 Use carriage return at the end of each assignment,
5826 and an empty string with
5827 carriage return at the end of array.
5830 unsigned char nvram_array[] = {"name1=value1\n",
5831 "name2=value2\n", "\n"};
5832 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5834 Search "EXAMPLE: nvram_array" to see how the array is activated.
5837 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5839 bus->nvram_params = nvram_params;
5842 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5847 char *memblock = NULL;
5850 bool nvram_file_exists;
5852 nv_path = bus->nv_path;
5854 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5855 if (!nvram_file_exists && (bus->nvram_params == NULL))
5858 if (nvram_file_exists) {
5859 image = dhd_os_open_image(nv_path);
5864 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5865 if (memblock == NULL) {
5866 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5867 __func__, MEMBLOCK));
5871 /* Download variables */
5872 if (nvram_file_exists) {
5873 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5875 len = strlen(bus->nvram_params);
5876 ASSERT(len <= MEMBLOCK);
5879 memcpy(memblock, bus->nvram_params, len);
5882 if (len > 0 && len < MEMBLOCK) {
5883 bufp = (char *)memblock;
5885 len = process_nvram_vars(bufp, len);
5889 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5891 DHD_ERROR(("%s: error downloading vars: %d\n",
5892 __func__, bcmerror));
5895 DHD_ERROR(("%s: error reading nvram file: %d\n",
5897 bcmerror = BCME_SDIO_ERROR;
5905 dhd_os_close_image(image);
5910 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5914 bool embed = false; /* download embedded firmware */
5915 bool dlok = false; /* download firmware succeeded */
5917 /* Out immediately if no image to download */
5918 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5919 #ifdef BCMEMBEDIMAGE
5926 /* Keep arm in reset */
5927 if (dhdsdio_download_state(bus, true)) {
5928 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5932 /* External image takes precedence if specified */
5933 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5934 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5935 DHD_ERROR(("%s: dongle image file download failed\n",
5937 #ifdef BCMEMBEDIMAGE
5947 #ifdef BCMEMBEDIMAGE
5949 if (dhdsdio_download_code_array(bus)) {
5950 DHD_ERROR(("%s: dongle image array download failed\n",
5959 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5963 /* EXAMPLE: nvram_array */
5964 /* If a valid nvram_arry is specified as above, it can be passed
5966 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5968 /* External nvram takes precedence if specified */
5969 if (dhdsdio_download_nvram(bus)) {
5970 DHD_ERROR(("%s: dongle nvram file download failed\n",
5974 /* Take arm out of reset */
5975 if (dhdsdio_download_state(bus, false)) {
5976 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5988 dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5989 u8 *buf, uint nbytes, void *pkt,
5990 bcmsdh_cmplt_fn_t complete, void *handle)
5994 /* 4329: GSPI check */
5996 bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
6002 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
6003 u8 *buf, uint nbytes, void *pkt,
6004 bcmsdh_cmplt_fn_t complete, void *handle)
6006 return bcmsdh_send_buf
6007 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
6011 uint dhd_bus_chip(struct dhd_bus *bus)
6013 ASSERT(bus->sih != NULL);
6014 return bus->sih->chip;
6017 void *dhd_bus_pub(struct dhd_bus *bus)
6022 void *dhd_bus_txq(struct dhd_bus *bus)
6027 uint dhd_bus_hdrlen(struct dhd_bus *bus)
6029 return SDPCM_HDRLEN;
6032 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
6040 if (!bus->dhd->dongle_reset) {
6041 /* Expect app to have torn down any
6042 connection before calling */
6043 /* Stop the bus, disable F2 */
6044 dhd_bus_stop(bus, false);
6046 /* Clean tx/rx buffer pointers,
6047 detach from the dongle */
6048 dhdsdio_release_dongle(bus, bus->dhd->osh);
6050 bus->dhd->dongle_reset = true;
6051 bus->dhd->up = false;
6053 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6054 /* App can now remove power from device */
6056 bcmerror = BCME_SDIO_ERROR;
6058 /* App must have restored power to device before calling */
6060 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6062 if (bus->dhd->dongle_reset) {
6064 /* Reset SD client */
6065 bcmsdh_reset(bus->sdh);
6067 /* Attempt to re-attach & download */
6068 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
6069 (u32 *) SI_ENUM_BASE,
6071 /* Attempt to download binary to the dongle */
6072 if (dhdsdio_probe_init
6073 (bus, bus->dhd->osh, bus->sdh)
6074 && dhdsdio_download_firmware(bus,
6078 /* Re-init bus, enable F2 transfer */
6079 dhd_bus_init((dhd_pub_t *) bus->dhd,
6082 #if defined(OOB_INTR_ONLY)
6083 dhd_enable_oob_intr(bus, true);
6084 #endif /* defined(OOB_INTR_ONLY) */
6086 bus->dhd->dongle_reset = false;
6087 bus->dhd->up = true;
6089 DHD_TRACE(("%s: WLAN ON DONE\n",
6092 bcmerror = BCME_SDIO_ERROR;
6094 bcmerror = BCME_SDIO_ERROR;
6096 bcmerror = BCME_NOTDOWN;
6097 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6098 "is on\n", __func__));
6099 bcmerror = BCME_SDIO_ERROR;
git.openpandora.org / pandora-kernel.git / blob