1 // ------------------------------------------------------------------
2 // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
5 // Permission to use, copy, modify, and/or distribute this software for any
6 // purpose with or without fee is hereby granted, provided that the above
7 // copyright notice and this permission notice appear in all copies.
9 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 // ------------------------------------------------------------------
19 //===================================================================
20 // Author(s): ="Atheros"
21 //===================================================================
24 #ifndef _UART_REG_REG_H_
25 #define _UART_REG_REG_H_
27 #define UART_DATA_ADDRESS 0x00000000
28 #define UART_DATA_OFFSET 0x00000000
29 #define UART_DATA_TX_CSR_MSB 9
30 #define UART_DATA_TX_CSR_LSB 9
31 #define UART_DATA_TX_CSR_MASK 0x00000200
32 #define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB)
33 #define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK)
34 #define UART_DATA_RX_CSR_MSB 8
35 #define UART_DATA_RX_CSR_LSB 8
36 #define UART_DATA_RX_CSR_MASK 0x00000100
37 #define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB)
38 #define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK)
39 #define UART_DATA_TXRX_DATA_MSB 7
40 #define UART_DATA_TXRX_DATA_LSB 0
41 #define UART_DATA_TXRX_DATA_MASK 0x000000ff
42 #define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB)
43 #define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK)
45 #define UART_CONTROL_ADDRESS 0x00000004
46 #define UART_CONTROL_OFFSET 0x00000004
47 #define UART_CONTROL_RX_BUSY_MSB 15
48 #define UART_CONTROL_RX_BUSY_LSB 15
49 #define UART_CONTROL_RX_BUSY_MASK 0x00008000
50 #define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB)
51 #define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK)
52 #define UART_CONTROL_TX_BUSY_MSB 14
53 #define UART_CONTROL_TX_BUSY_LSB 14
54 #define UART_CONTROL_TX_BUSY_MASK 0x00004000
55 #define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB)
56 #define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK)
57 #define UART_CONTROL_HOST_INT_ENABLE_MSB 13
58 #define UART_CONTROL_HOST_INT_ENABLE_LSB 13
59 #define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000
60 #define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB)
61 #define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK)
62 #define UART_CONTROL_HOST_INT_MSB 12
63 #define UART_CONTROL_HOST_INT_LSB 12
64 #define UART_CONTROL_HOST_INT_MASK 0x00001000
65 #define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB)
66 #define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK)
67 #define UART_CONTROL_TX_BREAK_MSB 11
68 #define UART_CONTROL_TX_BREAK_LSB 11
69 #define UART_CONTROL_TX_BREAK_MASK 0x00000800
70 #define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB)
71 #define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK)
72 #define UART_CONTROL_RX_BREAK_MSB 10
73 #define UART_CONTROL_RX_BREAK_LSB 10
74 #define UART_CONTROL_RX_BREAK_MASK 0x00000400
75 #define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB)
76 #define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK)
77 #define UART_CONTROL_SERIAL_TX_READY_MSB 9
78 #define UART_CONTROL_SERIAL_TX_READY_LSB 9
79 #define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200
80 #define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB)
81 #define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK)
82 #define UART_CONTROL_TX_READY_ORIDE_MSB 8
83 #define UART_CONTROL_TX_READY_ORIDE_LSB 8
84 #define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100
85 #define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB)
86 #define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK)
87 #define UART_CONTROL_RX_READY_ORIDE_MSB 7
88 #define UART_CONTROL_RX_READY_ORIDE_LSB 7
89 #define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080
90 #define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB)
91 #define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK)
92 #define UART_CONTROL_DMA_ENABLE_MSB 6
93 #define UART_CONTROL_DMA_ENABLE_LSB 6
94 #define UART_CONTROL_DMA_ENABLE_MASK 0x00000040
95 #define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB)
96 #define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK)
97 #define UART_CONTROL_FLOW_ENABLE_MSB 5
98 #define UART_CONTROL_FLOW_ENABLE_LSB 5
99 #define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020
100 #define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB)
101 #define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK)
102 #define UART_CONTROL_FLOW_INVERT_MSB 4
103 #define UART_CONTROL_FLOW_INVERT_LSB 4
104 #define UART_CONTROL_FLOW_INVERT_MASK 0x00000010
105 #define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB)
106 #define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK)
107 #define UART_CONTROL_IFC_ENABLE_MSB 3
108 #define UART_CONTROL_IFC_ENABLE_LSB 3
109 #define UART_CONTROL_IFC_ENABLE_MASK 0x00000008
110 #define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB)
111 #define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK)
112 #define UART_CONTROL_IFC_DCE_MSB 2
113 #define UART_CONTROL_IFC_DCE_LSB 2
114 #define UART_CONTROL_IFC_DCE_MASK 0x00000004
115 #define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB)
116 #define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK)
117 #define UART_CONTROL_PARITY_ENABLE_MSB 1
118 #define UART_CONTROL_PARITY_ENABLE_LSB 1
119 #define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002
120 #define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB)
121 #define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK)
122 #define UART_CONTROL_PARITY_EVEN_MSB 0
123 #define UART_CONTROL_PARITY_EVEN_LSB 0
124 #define UART_CONTROL_PARITY_EVEN_MASK 0x00000001
125 #define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB)
126 #define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK)
128 #define UART_CLKDIV_ADDRESS 0x00000008
129 #define UART_CLKDIV_OFFSET 0x00000008
130 #define UART_CLKDIV_CLK_SCALE_MSB 23
131 #define UART_CLKDIV_CLK_SCALE_LSB 16
132 #define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000
133 #define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB)
134 #define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK)
135 #define UART_CLKDIV_CLK_STEP_MSB 15
136 #define UART_CLKDIV_CLK_STEP_LSB 0
137 #define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff
138 #define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB)
139 #define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK)
141 #define UART_INT_ADDRESS 0x0000000c
142 #define UART_INT_OFFSET 0x0000000c
143 #define UART_INT_TX_EMPTY_INT_MSB 9
144 #define UART_INT_TX_EMPTY_INT_LSB 9
145 #define UART_INT_TX_EMPTY_INT_MASK 0x00000200
146 #define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB)
147 #define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK)
148 #define UART_INT_RX_FULL_INT_MSB 8
149 #define UART_INT_RX_FULL_INT_LSB 8
150 #define UART_INT_RX_FULL_INT_MASK 0x00000100
151 #define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB)
152 #define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK)
153 #define UART_INT_RX_BREAK_OFF_INT_MSB 7
154 #define UART_INT_RX_BREAK_OFF_INT_LSB 7
155 #define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080
156 #define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB)
157 #define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK)
158 #define UART_INT_RX_BREAK_ON_INT_MSB 6
159 #define UART_INT_RX_BREAK_ON_INT_LSB 6
160 #define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040
161 #define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB)
162 #define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK)
163 #define UART_INT_RX_PARITY_ERR_INT_MSB 5
164 #define UART_INT_RX_PARITY_ERR_INT_LSB 5
165 #define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020
166 #define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB)
167 #define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK)
168 #define UART_INT_TX_OFLOW_ERR_INT_MSB 4
169 #define UART_INT_TX_OFLOW_ERR_INT_LSB 4
170 #define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010
171 #define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB)
172 #define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK)
173 #define UART_INT_RX_OFLOW_ERR_INT_MSB 3
174 #define UART_INT_RX_OFLOW_ERR_INT_LSB 3
175 #define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008
176 #define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB)
177 #define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK)
178 #define UART_INT_RX_FRAMING_ERR_INT_MSB 2
179 #define UART_INT_RX_FRAMING_ERR_INT_LSB 2
180 #define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004
181 #define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB)
182 #define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK)
183 #define UART_INT_TX_READY_INT_MSB 1
184 #define UART_INT_TX_READY_INT_LSB 1
185 #define UART_INT_TX_READY_INT_MASK 0x00000002
186 #define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB)
187 #define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK)
188 #define UART_INT_RX_VALID_INT_MSB 0
189 #define UART_INT_RX_VALID_INT_LSB 0
190 #define UART_INT_RX_VALID_INT_MASK 0x00000001
191 #define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB)
192 #define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK)
194 #define UART_INT_EN_ADDRESS 0x00000010
195 #define UART_INT_EN_OFFSET 0x00000010
196 #define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9
197 #define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9
198 #define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200
199 #define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB)
200 #define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK)
201 #define UART_INT_EN_RX_FULL_INT_EN_MSB 8
202 #define UART_INT_EN_RX_FULL_INT_EN_LSB 8
203 #define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100
204 #define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB)
205 #define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK)
206 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7
207 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7
208 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080
209 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB)
210 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK)
211 #define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6
212 #define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6
213 #define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040
214 #define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB)
215 #define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK)
216 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5
217 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5
218 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020
219 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB)
220 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK)
221 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4
222 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4
223 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010
224 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB)
225 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK)
226 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3
227 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3
228 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008
229 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB)
230 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK)
231 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2
232 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2
233 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004
234 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB)
235 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK)
236 #define UART_INT_EN_TX_READY_INT_EN_MSB 1
237 #define UART_INT_EN_TX_READY_INT_EN_LSB 1
238 #define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002
239 #define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB)
240 #define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK)
241 #define UART_INT_EN_RX_VALID_INT_EN_MSB 0
242 #define UART_INT_EN_RX_VALID_INT_EN_LSB 0
243 #define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001
244 #define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB)
245 #define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK)
248 #ifndef __ASSEMBLER__
250 typedef struct uart_reg_reg_s {
251 volatile unsigned int uart_data;
252 volatile unsigned int uart_control;
253 volatile unsigned int uart_clkdiv;
254 volatile unsigned int uart_int;
255 volatile unsigned int uart_int_en;
258 #endif /* __ASSEMBLER__ */
260 #endif /* _UART_REG_H_ */
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